Diff: mmRTL/reg_16.txt

Revision:

0:8e898e1270d6

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mmRTL/reg_16.txt	Tue Sep 17 19:42:49 2013 +0000
@@ -0,0 +1,72 @@
+/*----------------------------------copyright---------------------------------*/
+//      licensed for personal and academic use.
+//      commercial use must be approved by the account-holder of
+//      gated.clock@gmail.com
+/*-----------------------------------module-----------------------------------*/
+        module reg_16
+        (
+         oParallel,                             // parallel-output data.
+         iParallel1,                            // parallel-input  data.
+         iParallel0,                            // parallel-input  data.
+         iSel,                                  // select the parallel input.
+         oSerial,                               // serial-output data.
+         iSerial,                               // serial-input data.
+         iLoadEnable,                           // parallel-load-enable.
+         iShiftEnable,                          // serial-shift-enable.
+         iResetN,                               // synchronous reset*.
+         iClk                                   // module clock.
+        );
+/*--------------------------------description-----------------------------------
+        a 16-bit parallel shift-register with 2 selectable input buses.
+-------------------------------------notes--------------------------------------
+        shifting is LSB->MSB.
+------------------------------------defines-----------------------------------*/
+/*-----------------------------------ports------------------------------------*/
+        output  [15:0]  oParallel;              // parallel-output data.
+        input   [15:0]  iParallel1;             // parallel-input  data.
+        input   [15:0]  iParallel0;             // parallel-input  data.
+        input           iSel;                   // select the parallel input.
+        output          oSerial;                // serial-output data.
+        input           iSerial;                // serial-input data.
+        input           iLoadEnable;            // parallel-load-enable.
+        input           iShiftEnable;           // serial-shift-enable.
+        input           iResetN;                // synchronous reset*.
+        input           iClk;                   // module clock.
+/*-----------------------------------wires------------------------------------*/
+        wire    [15:0]  oParallel;              // parallel-output data.
+        wire    [15:0]  iParallel1;             // parallel-input  data.
+        wire    [15:0]  iParallel0;             // parallel-input  data.
+        wire            iSel;                   // select the parallel input.
+        wire    [15:0]  wParallelIn;            // select the parallel input.
+        wire            oSerial;                // serial-output data.
+        wire            iSerial;                // serial-input data.
+        wire            iLoadEnable;            // parallel-load-enable.
+        wire            iShiftEnable;           // serial-shift-enable.
+        wire            iResetN;                // synchronous reset*.
+        wire            iClk;                   // module clock.
+/*---------------------------------registers----------------------------------*/
+        reg     [15:0]  rRegister;              // the register.
+/*---------------------------------variables----------------------------------*/
+/*---------------------------------parameters---------------------------------*/
+/*-----------------------------------clocks-----------------------------------*/
+/*---------------------------------instances----------------------------------*/
+        mux16x2 U0_mux16x2                      // data-input selection.
+        (
+         .iDin1(iParallel1),
+         .iDin0(iParallel0),
+         .iSel (iSel),
+         .oDout(wParallelIn)
+        );
+/*-----------------------------------logic------------------------------------*/
+        always @ (posedge iClk or negedge iResetN)
+        begin
+               if (!iResetN)     rRegister <= 16'h0000;
+          else if (iLoadEnable)  rRegister <= wParallelIn;
+          else if (iShiftEnable) rRegister <= {rRegister[14:0], iSerial};
+          else                   rRegister <= rRegister;
+        end
+
+        assign oParallel = rRegister;           // propagate parallel-out.
+        assign oSerial   = rRegister[15];       // propagate serial-out.
+/*-------------------------------*/endmodule/*--------------------------------*/
+