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core_sc000.h
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00001 /**************************************************************************//** 00002 * @file core_sc000.h 00003 * @brief CMSIS SC000 Core Peripheral Access Layer Header File 00004 * @version V5.0.2 00005 * @date 13. February 2017 00006 ******************************************************************************/ 00007 /* 00008 * Copyright (c) 2009-2017 ARM Limited. All rights reserved. 00009 * 00010 * SPDX-License-Identifier: Apache-2.0 00011 * 00012 * Licensed under the Apache License, Version 2.0 (the License); you may 00013 * not use this file except in compliance with the License. 00014 * You may obtain a copy of the License at 00015 * 00016 * www.apache.org/licenses/LICENSE-2.0 00017 * 00018 * Unless required by applicable law or agreed to in writing, software 00019 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 00020 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 00021 * See the License for the specific language governing permissions and 00022 * limitations under the License. 00023 */ 00024 00025 #if defined ( __ICCARM__ ) 00026 #pragma system_include /* treat file as system include file for MISRA check */ 00027 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 00028 #pragma clang system_header /* treat file as system include file */ 00029 #endif 00030 00031 #ifndef __CORE_SC000_H_GENERIC 00032 #define __CORE_SC000_H_GENERIC 00033 00034 #include <stdint.h> 00035 00036 #ifdef __cplusplus 00037 extern "C" { 00038 #endif 00039 00040 /** 00041 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 00042 CMSIS violates the following MISRA-C:2004 rules: 00043 00044 \li Required Rule 8.5, object/function definition in header file.<br> 00045 Function definitions in header files are used to allow 'inlining'. 00046 00047 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> 00048 Unions are used for effective representation of core registers. 00049 00050 \li Advisory Rule 19.7, Function-like macro defined.<br> 00051 Function-like macros are used to allow more efficient code. 00052 */ 00053 00054 00055 /******************************************************************************* 00056 * CMSIS definitions 00057 ******************************************************************************/ 00058 /** 00059 \ingroup SC000 00060 @{ 00061 */ 00062 00063 /* CMSIS SC000 definitions */ 00064 #define __SC000_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ 00065 #define __SC000_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ 00066 #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ 00067 __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ 00068 00069 #define __CORTEX_SC (000U) /*!< Cortex secure core */ 00070 00071 /** __FPU_USED indicates whether an FPU is used or not. 00072 This core does not support an FPU at all 00073 */ 00074 #define __FPU_USED 0U 00075 00076 #if defined ( __CC_ARM ) 00077 #if defined __TARGET_FPU_VFP 00078 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00079 #endif 00080 00081 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 00082 #if defined __ARM_PCS_VFP 00083 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00084 #endif 00085 00086 #elif defined ( __GNUC__ ) 00087 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 00088 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00089 #endif 00090 00091 #elif defined ( __ICCARM__ ) 00092 #if defined __ARMVFP__ 00093 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00094 #endif 00095 00096 #elif defined ( __TI_ARM__ ) 00097 #if defined __TI_VFP_SUPPORT__ 00098 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00099 #endif 00100 00101 #elif defined ( __TASKING__ ) 00102 #if defined __FPU_VFP__ 00103 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00104 #endif 00105 00106 #elif defined ( __CSMC__ ) 00107 #if ( __CSMC__ & 0x400U) 00108 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00109 #endif 00110 00111 #endif 00112 00113 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ 00114 00115 00116 #ifdef __cplusplus 00117 } 00118 #endif 00119 00120 #endif /* __CORE_SC000_H_GENERIC */ 00121 00122 #ifndef __CMSIS_GENERIC 00123 00124 #ifndef __CORE_SC000_H_DEPENDANT 00125 #define __CORE_SC000_H_DEPENDANT 00126 00127 #ifdef __cplusplus 00128 extern "C" { 00129 #endif 00130 00131 /* check device defines and use defaults */ 00132 #if defined __CHECK_DEVICE_DEFINES 00133 #ifndef __SC000_REV 00134 #define __SC000_REV 0x0000U 00135 #warning "__SC000_REV not defined in device header file; using default!" 00136 #endif 00137 00138 #ifndef __MPU_PRESENT 00139 #define __MPU_PRESENT 0U 00140 #warning "__MPU_PRESENT not defined in device header file; using default!" 00141 #endif 00142 00143 #ifndef __NVIC_PRIO_BITS 00144 #define __NVIC_PRIO_BITS 2U 00145 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 00146 #endif 00147 00148 #ifndef __Vendor_SysTickConfig 00149 #define __Vendor_SysTickConfig 0U 00150 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 00151 #endif 00152 #endif 00153 00154 /* IO definitions (access restrictions to peripheral registers) */ 00155 /** 00156 \defgroup CMSIS_glob_defs CMSIS Global Defines 00157 00158 <strong>IO Type Qualifiers</strong> are used 00159 \li to specify the access to peripheral variables. 00160 \li for automatic generation of peripheral register debug information. 00161 */ 00162 #ifdef __cplusplus 00163 #define __I volatile /*!< Defines 'read only' permissions */ 00164 #else 00165 #define __I volatile const /*!< Defines 'read only' permissions */ 00166 #endif 00167 #define __O volatile /*!< Defines 'write only' permissions */ 00168 #define __IO volatile /*!< Defines 'read / write' permissions */ 00169 00170 /* following defines should be used for structure members */ 00171 #define __IM volatile const /*! Defines 'read only' structure member permissions */ 00172 #define __OM volatile /*! Defines 'write only' structure member permissions */ 00173 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ 00174 00175 /*@} end of group SC000 */ 00176 00177 00178 00179 /******************************************************************************* 00180 * Register Abstraction 00181 Core Register contain: 00182 - Core Register 00183 - Core NVIC Register 00184 - Core SCB Register 00185 - Core SysTick Register 00186 - Core MPU Register 00187 ******************************************************************************/ 00188 /** 00189 \defgroup CMSIS_core_register Defines and Type Definitions 00190 \brief Type definitions and defines for Cortex-M processor based devices. 00191 */ 00192 00193 /** 00194 \ingroup CMSIS_core_register 00195 \defgroup CMSIS_CORE Status and Control Registers 00196 \brief Core Register type definitions. 00197 @{ 00198 */ 00199 00200 /** 00201 \brief Union type to access the Application Program Status Register (APSR). 00202 */ 00203 typedef union 00204 { 00205 struct 00206 { 00207 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ 00208 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00209 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00210 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00211 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00212 } b; /*!< Structure used for bit access */ 00213 uint32_t w; /*!< Type used for word access */ 00214 } APSR_Type; 00215 00216 /* APSR Register Definitions */ 00217 #define APSR_N_Pos 31U /*!< APSR: N Position */ 00218 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ 00219 00220 #define APSR_Z_Pos 30U /*!< APSR: Z Position */ 00221 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ 00222 00223 #define APSR_C_Pos 29U /*!< APSR: C Position */ 00224 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ 00225 00226 #define APSR_V_Pos 28U /*!< APSR: V Position */ 00227 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ 00228 00229 00230 /** 00231 \brief Union type to access the Interrupt Program Status Register (IPSR). 00232 */ 00233 typedef union 00234 { 00235 struct 00236 { 00237 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00238 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ 00239 } b; /*!< Structure used for bit access */ 00240 uint32_t w; /*!< Type used for word access */ 00241 } IPSR_Type; 00242 00243 /* IPSR Register Definitions */ 00244 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ 00245 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ 00246 00247 00248 /** 00249 \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 00250 */ 00251 typedef union 00252 { 00253 struct 00254 { 00255 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00256 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ 00257 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ 00258 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ 00259 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00260 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00261 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00262 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00263 } b; /*!< Structure used for bit access */ 00264 uint32_t w; /*!< Type used for word access */ 00265 } xPSR_Type; 00266 00267 /* xPSR Register Definitions */ 00268 #define xPSR_N_Pos 31U /*!< xPSR: N Position */ 00269 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ 00270 00271 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ 00272 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ 00273 00274 #define xPSR_C_Pos 29U /*!< xPSR: C Position */ 00275 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ 00276 00277 #define xPSR_V_Pos 28U /*!< xPSR: V Position */ 00278 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ 00279 00280 #define xPSR_T_Pos 24U /*!< xPSR: T Position */ 00281 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ 00282 00283 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ 00284 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ 00285 00286 00287 /** 00288 \brief Union type to access the Control Registers (CONTROL). 00289 */ 00290 typedef union 00291 { 00292 struct 00293 { 00294 uint32_t _reserved0:1; /*!< bit: 0 Reserved */ 00295 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ 00296 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ 00297 } b; /*!< Structure used for bit access */ 00298 uint32_t w; /*!< Type used for word access */ 00299 } CONTROL_Type; 00300 00301 /* CONTROL Register Definitions */ 00302 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ 00303 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ 00304 00305 /*@} end of group CMSIS_CORE */ 00306 00307 00308 /** 00309 \ingroup CMSIS_core_register 00310 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 00311 \brief Type definitions for the NVIC Registers 00312 @{ 00313 */ 00314 00315 /** 00316 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 00317 */ 00318 typedef struct 00319 { 00320 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 00321 uint32_t RESERVED0[31U]; 00322 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ 00323 uint32_t RSERVED1[31U]; 00324 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ 00325 uint32_t RESERVED2[31U]; 00326 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ 00327 uint32_t RESERVED3[31U]; 00328 uint32_t RESERVED4[64U]; 00329 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ 00330 } NVIC_Type; 00331 00332 /*@} end of group CMSIS_NVIC */ 00333 00334 00335 /** 00336 \ingroup CMSIS_core_register 00337 \defgroup CMSIS_SCB System Control Block (SCB) 00338 \brief Type definitions for the System Control Block Registers 00339 @{ 00340 */ 00341 00342 /** 00343 \brief Structure type to access the System Control Block (SCB). 00344 */ 00345 typedef struct 00346 { 00347 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 00348 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ 00349 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ 00350 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ 00351 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ 00352 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ 00353 uint32_t RESERVED0[1U]; 00354 __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ 00355 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ 00356 uint32_t RESERVED1[154U]; 00357 __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ 00358 } SCB_Type; 00359 00360 /* SCB CPUID Register Definitions */ 00361 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ 00362 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ 00363 00364 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ 00365 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ 00366 00367 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ 00368 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ 00369 00370 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ 00371 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ 00372 00373 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ 00374 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ 00375 00376 /* SCB Interrupt Control State Register Definitions */ 00377 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ 00378 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ 00379 00380 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ 00381 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ 00382 00383 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ 00384 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ 00385 00386 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ 00387 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ 00388 00389 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ 00390 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ 00391 00392 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ 00393 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ 00394 00395 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ 00396 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ 00397 00398 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ 00399 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ 00400 00401 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ 00402 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ 00403 00404 /* SCB Interrupt Control State Register Definitions */ 00405 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ 00406 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ 00407 00408 /* SCB Application Interrupt and Reset Control Register Definitions */ 00409 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ 00410 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ 00411 00412 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ 00413 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ 00414 00415 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ 00416 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ 00417 00418 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ 00419 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ 00420 00421 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ 00422 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ 00423 00424 /* SCB System Control Register Definitions */ 00425 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ 00426 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ 00427 00428 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ 00429 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ 00430 00431 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ 00432 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ 00433 00434 /* SCB Configuration Control Register Definitions */ 00435 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ 00436 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ 00437 00438 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ 00439 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ 00440 00441 /* SCB System Handler Control and State Register Definitions */ 00442 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ 00443 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ 00444 00445 /*@} end of group CMSIS_SCB */ 00446 00447 00448 /** 00449 \ingroup CMSIS_core_register 00450 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) 00451 \brief Type definitions for the System Control and ID Register not in the SCB 00452 @{ 00453 */ 00454 00455 /** 00456 \brief Structure type to access the System Control and ID Register not in the SCB. 00457 */ 00458 typedef struct 00459 { 00460 uint32_t RESERVED0[2U]; 00461 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ 00462 } SCnSCB_Type; 00463 00464 /* Auxiliary Control Register Definitions */ 00465 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ 00466 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ 00467 00468 /*@} end of group CMSIS_SCnotSCB */ 00469 00470 00471 /** 00472 \ingroup CMSIS_core_register 00473 \defgroup CMSIS_SysTick System Tick Timer (SysTick) 00474 \brief Type definitions for the System Timer Registers. 00475 @{ 00476 */ 00477 00478 /** 00479 \brief Structure type to access the System Timer (SysTick). 00480 */ 00481 typedef struct 00482 { 00483 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ 00484 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 00485 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ 00486 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 00487 } SysTick_Type; 00488 00489 /* SysTick Control / Status Register Definitions */ 00490 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ 00491 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ 00492 00493 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ 00494 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ 00495 00496 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ 00497 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ 00498 00499 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ 00500 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ 00501 00502 /* SysTick Reload Register Definitions */ 00503 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ 00504 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ 00505 00506 /* SysTick Current Register Definitions */ 00507 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ 00508 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ 00509 00510 /* SysTick Calibration Register Definitions */ 00511 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ 00512 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ 00513 00514 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ 00515 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ 00516 00517 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ 00518 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ 00519 00520 /*@} end of group CMSIS_SysTick */ 00521 00522 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 00523 /** 00524 \ingroup CMSIS_core_register 00525 \defgroup CMSIS_MPU Memory Protection Unit (MPU) 00526 \brief Type definitions for the Memory Protection Unit (MPU) 00527 @{ 00528 */ 00529 00530 /** 00531 \brief Structure type to access the Memory Protection Unit (MPU). 00532 */ 00533 typedef struct 00534 { 00535 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ 00536 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ 00537 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ 00538 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ 00539 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ 00540 } MPU_Type; 00541 00542 /* MPU Type Register Definitions */ 00543 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ 00544 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ 00545 00546 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ 00547 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ 00548 00549 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ 00550 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ 00551 00552 /* MPU Control Register Definitions */ 00553 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ 00554 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ 00555 00556 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ 00557 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ 00558 00559 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ 00560 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ 00561 00562 /* MPU Region Number Register Definitions */ 00563 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ 00564 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ 00565 00566 /* MPU Region Base Address Register Definitions */ 00567 #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ 00568 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ 00569 00570 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ 00571 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ 00572 00573 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ 00574 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ 00575 00576 /* MPU Region Attribute and Size Register Definitions */ 00577 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ 00578 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ 00579 00580 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ 00581 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ 00582 00583 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ 00584 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ 00585 00586 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ 00587 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ 00588 00589 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ 00590 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ 00591 00592 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ 00593 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ 00594 00595 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ 00596 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ 00597 00598 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ 00599 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ 00600 00601 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ 00602 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ 00603 00604 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ 00605 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ 00606 00607 /*@} end of group CMSIS_MPU */ 00608 #endif 00609 00610 00611 /** 00612 \ingroup CMSIS_core_register 00613 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 00614 \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. 00615 Therefore they are not covered by the SC000 header file. 00616 @{ 00617 */ 00618 /*@} end of group CMSIS_CoreDebug */ 00619 00620 00621 /** 00622 \ingroup CMSIS_core_register 00623 \defgroup CMSIS_core_bitfield Core register bit field macros 00624 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). 00625 @{ 00626 */ 00627 00628 /** 00629 \brief Mask and shift a bit field value for use in a register bit range. 00630 \param[in] field Name of the register bit field. 00631 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. 00632 \return Masked and shifted value. 00633 */ 00634 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) 00635 00636 /** 00637 \brief Mask and shift a register value to extract a bit filed value. 00638 \param[in] field Name of the register bit field. 00639 \param[in] value Value of register. This parameter is interpreted as an uint32_t type. 00640 \return Masked and shifted bit field value. 00641 */ 00642 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) 00643 00644 /*@} end of group CMSIS_core_bitfield */ 00645 00646 00647 /** 00648 \ingroup CMSIS_core_register 00649 \defgroup CMSIS_core_base Core Definitions 00650 \brief Definitions for base addresses, unions, and structures. 00651 @{ 00652 */ 00653 00654 /* Memory mapping of Core Hardware */ 00655 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ 00656 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 00657 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 00658 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ 00659 00660 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ 00661 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ 00662 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ 00663 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ 00664 00665 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 00666 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ 00667 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ 00668 #endif 00669 00670 /*@} */ 00671 00672 00673 00674 /******************************************************************************* 00675 * Hardware Abstraction Layer 00676 Core Function Interface contains: 00677 - Core NVIC Functions 00678 - Core SysTick Functions 00679 - Core Register Access Functions 00680 ******************************************************************************/ 00681 /** 00682 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 00683 */ 00684 00685 00686 00687 /* ########################## NVIC functions #################################### */ 00688 /** 00689 \ingroup CMSIS_Core_FunctionInterface 00690 \defgroup CMSIS_Core_NVICFunctions NVIC Functions 00691 \brief Functions that manage interrupts and exceptions via the NVIC. 00692 @{ 00693 */ 00694 00695 #ifdef CMSIS_NVIC_VIRTUAL 00696 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE 00697 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" 00698 #endif 00699 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE 00700 #else 00701 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ 00702 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ 00703 #define NVIC_EnableIRQ __NVIC_EnableIRQ 00704 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ 00705 #define NVIC_DisableIRQ __NVIC_DisableIRQ 00706 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ 00707 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ 00708 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ 00709 /*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ 00710 #define NVIC_SetPriority __NVIC_SetPriority 00711 #define NVIC_GetPriority __NVIC_GetPriority 00712 #define NVIC_SystemReset __NVIC_SystemReset 00713 #endif /* CMSIS_NVIC_VIRTUAL */ 00714 00715 #ifdef CMSIS_VECTAB_VIRTUAL 00716 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE 00717 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" 00718 #endif 00719 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE 00720 #else 00721 #define NVIC_SetVector __NVIC_SetVector 00722 #define NVIC_GetVector __NVIC_GetVector 00723 #endif /* (CMSIS_VECTAB_VIRTUAL) */ 00724 00725 #define NVIC_USER_IRQ_OFFSET 16 00726 00727 00728 /* Interrupt Priorities are WORD accessible only under ARMv6M */ 00729 /* The following MACROS handle generation of the register offset and byte masks */ 00730 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) 00731 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) 00732 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) 00733 00734 00735 /** 00736 \brief Enable Interrupt 00737 \details Enables a device specific interrupt in the NVIC interrupt controller. 00738 \param [in] IRQn Device specific interrupt number. 00739 \note IRQn must not be negative. 00740 */ 00741 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) 00742 { 00743 if ((int32_t)(IRQn) >= 0) 00744 { 00745 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); 00746 } 00747 } 00748 00749 00750 /** 00751 \brief Get Interrupt Enable status 00752 \details Returns a device specific interrupt enable status from the NVIC interrupt controller. 00753 \param [in] IRQn Device specific interrupt number. 00754 \return 0 Interrupt is not enabled. 00755 \return 1 Interrupt is enabled. 00756 \note IRQn must not be negative. 00757 */ 00758 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) 00759 { 00760 if ((int32_t)(IRQn) >= 0) 00761 { 00762 return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 00763 } 00764 else 00765 { 00766 return(0U); 00767 } 00768 } 00769 00770 00771 /** 00772 \brief Disable Interrupt 00773 \details Disables a device specific interrupt in the NVIC interrupt controller. 00774 \param [in] IRQn Device specific interrupt number. 00775 \note IRQn must not be negative. 00776 */ 00777 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) 00778 { 00779 if ((int32_t)(IRQn) >= 0) 00780 { 00781 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); 00782 __DSB(); 00783 __ISB(); 00784 } 00785 } 00786 00787 00788 /** 00789 \brief Get Pending Interrupt 00790 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. 00791 \param [in] IRQn Device specific interrupt number. 00792 \return 0 Interrupt status is not pending. 00793 \return 1 Interrupt status is pending. 00794 \note IRQn must not be negative. 00795 */ 00796 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) 00797 { 00798 if ((int32_t)(IRQn) >= 0) 00799 { 00800 return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 00801 } 00802 else 00803 { 00804 return(0U); 00805 } 00806 } 00807 00808 00809 /** 00810 \brief Set Pending Interrupt 00811 \details Sets the pending bit of a device specific interrupt in the NVIC pending register. 00812 \param [in] IRQn Device specific interrupt number. 00813 \note IRQn must not be negative. 00814 */ 00815 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) 00816 { 00817 if ((int32_t)(IRQn) >= 0) 00818 { 00819 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); 00820 } 00821 } 00822 00823 00824 /** 00825 \brief Clear Pending Interrupt 00826 \details Clears the pending bit of a device specific interrupt in the NVIC pending register. 00827 \param [in] IRQn Device specific interrupt number. 00828 \note IRQn must not be negative. 00829 */ 00830 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) 00831 { 00832 if ((int32_t)(IRQn) >= 0) 00833 { 00834 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); 00835 } 00836 } 00837 00838 00839 /** 00840 \brief Set Interrupt Priority 00841 \details Sets the priority of a device specific interrupt or a processor exception. 00842 The interrupt number can be positive to specify a device specific interrupt, 00843 or negative to specify a processor exception. 00844 \param [in] IRQn Interrupt number. 00845 \param [in] priority Priority to set. 00846 \note The priority cannot be set for every processor exception. 00847 */ 00848 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 00849 { 00850 if ((int32_t)(IRQn) >= 0) 00851 { 00852 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 00853 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 00854 } 00855 else 00856 { 00857 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 00858 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 00859 } 00860 } 00861 00862 00863 /** 00864 \brief Get Interrupt Priority 00865 \details Reads the priority of a device specific interrupt or a processor exception. 00866 The interrupt number can be positive to specify a device specific interrupt, 00867 or negative to specify a processor exception. 00868 \param [in] IRQn Interrupt number. 00869 \return Interrupt Priority. 00870 Value is aligned automatically to the implemented priority bits of the microcontroller. 00871 */ 00872 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) 00873 { 00874 00875 if ((int32_t)(IRQn) >= 0) 00876 { 00877 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); 00878 } 00879 else 00880 { 00881 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); 00882 } 00883 } 00884 00885 00886 /** 00887 \brief Set Interrupt Vector 00888 \details Sets an interrupt vector in SRAM based interrupt vector table. 00889 The interrupt number can be positive to specify a device specific interrupt, 00890 or negative to specify a processor exception. 00891 VTOR must been relocated to SRAM before. 00892 \param [in] IRQn Interrupt number 00893 \param [in] vector Address of interrupt handler function 00894 */ 00895 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) 00896 { 00897 uint32_t *vectors = (uint32_t *)SCB->VTOR; 00898 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; 00899 } 00900 00901 00902 /** 00903 \brief Get Interrupt Vector 00904 \details Reads an interrupt vector from interrupt vector table. 00905 The interrupt number can be positive to specify a device specific interrupt, 00906 or negative to specify a processor exception. 00907 \param [in] IRQn Interrupt number. 00908 \return Address of interrupt handler function 00909 */ 00910 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) 00911 { 00912 uint32_t *vectors = (uint32_t *)SCB->VTOR; 00913 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; 00914 } 00915 00916 00917 /** 00918 \brief System Reset 00919 \details Initiates a system reset request to reset the MCU. 00920 */ 00921 __STATIC_INLINE void __NVIC_SystemReset(void) 00922 { 00923 __DSB(); /* Ensure all outstanding memory accesses included 00924 buffered write are completed before reset */ 00925 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 00926 SCB_AIRCR_SYSRESETREQ_Msk); 00927 __DSB(); /* Ensure completion of memory access */ 00928 00929 for(;;) /* wait until reset */ 00930 { 00931 __NOP(); 00932 } 00933 } 00934 00935 /*@} end of CMSIS_Core_NVICFunctions */ 00936 00937 00938 /* ########################## FPU functions #################################### */ 00939 /** 00940 \ingroup CMSIS_Core_FunctionInterface 00941 \defgroup CMSIS_Core_FpuFunctions FPU Functions 00942 \brief Function that provides FPU type. 00943 @{ 00944 */ 00945 00946 /** 00947 \brief get FPU type 00948 \details returns the FPU type 00949 \returns 00950 - \b 0: No FPU 00951 - \b 1: Single precision FPU 00952 - \b 2: Double + Single precision FPU 00953 */ 00954 __STATIC_INLINE uint32_t SCB_GetFPUType(void) 00955 { 00956 return 0U; /* No FPU */ 00957 } 00958 00959 00960 /*@} end of CMSIS_Core_FpuFunctions */ 00961 00962 00963 00964 /* ################################## SysTick function ############################################ */ 00965 /** 00966 \ingroup CMSIS_Core_FunctionInterface 00967 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions 00968 \brief Functions that configure the System. 00969 @{ 00970 */ 00971 00972 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) 00973 00974 /** 00975 \brief System Tick Configuration 00976 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. 00977 Counter is in free running mode to generate periodic interrupts. 00978 \param [in] ticks Number of ticks between two interrupts. 00979 \return 0 Function succeeded. 00980 \return 1 Function failed. 00981 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 00982 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> 00983 must contain a vendor-specific implementation of this function. 00984 */ 00985 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) 00986 { 00987 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 00988 { 00989 return (1UL); /* Reload value impossible */ 00990 } 00991 00992 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 00993 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 00994 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 00995 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 00996 SysTick_CTRL_TICKINT_Msk | 00997 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 00998 return (0UL); /* Function successful */ 00999 } 01000 01001 #endif 01002 01003 /*@} end of CMSIS_Core_SysTickFunctions */ 01004 01005 01006 01007 01008 #ifdef __cplusplus 01009 } 01010 #endif 01011 01012 #endif /* __CORE_SC000_H_DEPENDANT */ 01013 01014 #endif /* __CMSIS_GENERIC */ 01015
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