Fawwaz Nadzmy
/
mbed-dev
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Fork of
mbed-dev
by 
mbed official
targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/MBRZA1H.h@119:3921aeca8633, 2016-04-29 (annotated)
- Committer:
- mbed_official
- Date:
- Fri Apr 29 01:15:11 2016 +0100
- Revision:
- 119:3921aeca8633
- Parent:
- 0:9b334a45a8ff
- Child:
- 144:ef7eb2e8f9f7
Synchronized with git revision fe9720f24b1adc71ab6962506ec51290f6afd270
Full URL: https://github.com/mbedmicro/mbed/commit/fe9720f24b1adc71ab6962506ec51290f6afd270/
[Renesas RZ/A1H] Enable asynchronous communications
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| bogdanm | 0:9b334a45a8ff | 1 | /******************************************************************************* |
| bogdanm | 0:9b334a45a8ff | 2 | * DISCLAIMER |
| bogdanm | 0:9b334a45a8ff | 3 | * This software is supplied by Renesas Electronics Corporation and is only |
| bogdanm | 0:9b334a45a8ff | 4 | * intended for use with Renesas products. No other uses are authorized. This |
| bogdanm | 0:9b334a45a8ff | 5 | * software is owned by Renesas Electronics Corporation and is protected under |
| bogdanm | 0:9b334a45a8ff | 6 | * all applicable laws, including copyright laws. |
| bogdanm | 0:9b334a45a8ff | 7 | * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING |
| bogdanm | 0:9b334a45a8ff | 8 | * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT |
| bogdanm | 0:9b334a45a8ff | 9 | * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE |
| bogdanm | 0:9b334a45a8ff | 10 | * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. |
| bogdanm | 0:9b334a45a8ff | 11 | * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS |
| bogdanm | 0:9b334a45a8ff | 12 | * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE |
| bogdanm | 0:9b334a45a8ff | 13 | * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR |
| bogdanm | 0:9b334a45a8ff | 14 | * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE |
| bogdanm | 0:9b334a45a8ff | 15 | * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. |
| bogdanm | 0:9b334a45a8ff | 16 | * Renesas reserves the right, without notice, to make changes to this software |
| bogdanm | 0:9b334a45a8ff | 17 | * and to discontinue the availability of this software. By using this software, |
| bogdanm | 0:9b334a45a8ff | 18 | * you agree to the additional terms and conditions found by accessing the |
| bogdanm | 0:9b334a45a8ff | 19 | * following link: |
| bogdanm | 0:9b334a45a8ff | 20 | * http://www.renesas.com/disclaimer |
| bogdanm | 0:9b334a45a8ff | 21 | * Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. |
| bogdanm | 0:9b334a45a8ff | 22 | *******************************************************************************/ |
| bogdanm | 0:9b334a45a8ff | 23 | /**************************************************************************//** |
| bogdanm | 0:9b334a45a8ff | 24 | * @file MBRZA1H.h |
| bogdanm | 0:9b334a45a8ff | 25 | * @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File for |
| bogdanm | 0:9b334a45a8ff | 26 | * Renesas MBRZA1H Device Series |
| bogdanm | 0:9b334a45a8ff | 27 | * @version |
| bogdanm | 0:9b334a45a8ff | 28 | * @date 19 Sept 2013 |
| bogdanm | 0:9b334a45a8ff | 29 | * |
| bogdanm | 0:9b334a45a8ff | 30 | * @note |
| bogdanm | 0:9b334a45a8ff | 31 | * |
| bogdanm | 0:9b334a45a8ff | 32 | ******************************************************************************/ |
| bogdanm | 0:9b334a45a8ff | 33 | |
| bogdanm | 0:9b334a45a8ff | 34 | #ifndef __MBRZA1H_H__ |
| bogdanm | 0:9b334a45a8ff | 35 | #define __MBRZA1H_H__ |
| bogdanm | 0:9b334a45a8ff | 36 | |
| bogdanm | 0:9b334a45a8ff | 37 | #ifdef __cplusplus |
| bogdanm | 0:9b334a45a8ff | 38 | extern "C" { |
| bogdanm | 0:9b334a45a8ff | 39 | #endif |
| bogdanm | 0:9b334a45a8ff | 40 | |
| bogdanm | 0:9b334a45a8ff | 41 | |
| bogdanm | 0:9b334a45a8ff | 42 | /* ------------------------- Interrupt Number Definition ------------------------ */ |
| bogdanm | 0:9b334a45a8ff | 43 | |
| bogdanm | 0:9b334a45a8ff | 44 | typedef enum IRQn |
| bogdanm | 0:9b334a45a8ff | 45 | { |
| bogdanm | 0:9b334a45a8ff | 46 | /****** SGI Interrupts Numbers ****************************************/ |
| bogdanm | 0:9b334a45a8ff | 47 | SGI0_IRQn = 0, |
| bogdanm | 0:9b334a45a8ff | 48 | SGI1_IRQn = 1, |
| bogdanm | 0:9b334a45a8ff | 49 | SGI2_IRQn = 2, |
| bogdanm | 0:9b334a45a8ff | 50 | SGI3_IRQn = 3, |
| bogdanm | 0:9b334a45a8ff | 51 | SGI4_IRQn = 4, |
| bogdanm | 0:9b334a45a8ff | 52 | SGI5_IRQn = 5, |
| bogdanm | 0:9b334a45a8ff | 53 | SGI6_IRQn = 6, |
| bogdanm | 0:9b334a45a8ff | 54 | SGI7_IRQn = 7, |
| bogdanm | 0:9b334a45a8ff | 55 | SGI8_IRQn = 8, |
| bogdanm | 0:9b334a45a8ff | 56 | SGI9_IRQn = 9, |
| bogdanm | 0:9b334a45a8ff | 57 | SGI10_IRQn = 10, |
| bogdanm | 0:9b334a45a8ff | 58 | SGI11_IRQn = 11, |
| bogdanm | 0:9b334a45a8ff | 59 | SGI12_IRQn = 12, |
| bogdanm | 0:9b334a45a8ff | 60 | SGI13_IRQn = 13, |
| bogdanm | 0:9b334a45a8ff | 61 | SGI14_IRQn = 14, |
| bogdanm | 0:9b334a45a8ff | 62 | SGI15_IRQn = 15, |
| bogdanm | 0:9b334a45a8ff | 63 | |
| bogdanm | 0:9b334a45a8ff | 64 | /****** Cortex-A9 Processor Exceptions Numbers ****************************************/ |
| bogdanm | 0:9b334a45a8ff | 65 | /* 16 - 578 */ |
| bogdanm | 0:9b334a45a8ff | 66 | PMUIRQ0_IRQn = 16, |
| bogdanm | 0:9b334a45a8ff | 67 | COMMRX0_IRQn = 17, |
| bogdanm | 0:9b334a45a8ff | 68 | COMMTX0_IRQn = 18, |
| bogdanm | 0:9b334a45a8ff | 69 | CTIIRQ0_IRQn = 19, |
| bogdanm | 0:9b334a45a8ff | 70 | |
| bogdanm | 0:9b334a45a8ff | 71 | IRQ0_IRQn = 32, |
| bogdanm | 0:9b334a45a8ff | 72 | IRQ1_IRQn = 33, |
| bogdanm | 0:9b334a45a8ff | 73 | IRQ2_IRQn = 34, |
| bogdanm | 0:9b334a45a8ff | 74 | IRQ3_IRQn = 35, |
| bogdanm | 0:9b334a45a8ff | 75 | IRQ4_IRQn = 36, |
| bogdanm | 0:9b334a45a8ff | 76 | IRQ5_IRQn = 37, |
| bogdanm | 0:9b334a45a8ff | 77 | IRQ6_IRQn = 38, |
| bogdanm | 0:9b334a45a8ff | 78 | IRQ7_IRQn = 39, |
| bogdanm | 0:9b334a45a8ff | 79 | |
| bogdanm | 0:9b334a45a8ff | 80 | PL310ERR_IRQn = 40, |
| bogdanm | 0:9b334a45a8ff | 81 | |
| bogdanm | 0:9b334a45a8ff | 82 | DMAINT0_IRQn = 41, /*!< DMAC Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 83 | DMAINT1_IRQn = 42, /*!< DMAC Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 84 | DMAINT2_IRQn = 43, /*!< DMAC Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 85 | DMAINT3_IRQn = 44, /*!< DMAC Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 86 | DMAINT4_IRQn = 45, /*!< DMAC Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 87 | DMAINT5_IRQn = 46, /*!< DMAC Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 88 | DMAINT6_IRQn = 47, /*!< DMAC Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 89 | DMAINT7_IRQn = 48, /*!< DMAC Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 90 | DMAINT8_IRQn = 49, /*!< DMAC Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 91 | DMAINT9_IRQn = 50, /*!< DMAC Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 92 | DMAINT10_IRQn = 51, /*!< DMAC Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 93 | DMAINT11_IRQn = 52, /*!< DMAC Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 94 | DMAINT12_IRQn = 53, /*!< DMAC Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 95 | DMAINT13_IRQn = 54, /*!< DMAC Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 96 | DMAINT14_IRQn = 55, /*!< DMAC Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 97 | DMAINT15_IRQn = 56, /*!< DMAC Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 98 | DMAERR_IRQn = 57, /*!< DMAC Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 99 | |
| bogdanm | 0:9b334a45a8ff | 100 | /* 58-72 Reserved */ |
| bogdanm | 0:9b334a45a8ff | 101 | |
| bogdanm | 0:9b334a45a8ff | 102 | USBI0_IRQn = 73, |
| bogdanm | 0:9b334a45a8ff | 103 | USBI1_IRQn = 74, |
| bogdanm | 0:9b334a45a8ff | 104 | |
| bogdanm | 0:9b334a45a8ff | 105 | S0_VI_VSYNC0_IRQn = 75, |
| bogdanm | 0:9b334a45a8ff | 106 | S0_LO_VSYNC0_IRQn = 76, |
| bogdanm | 0:9b334a45a8ff | 107 | S0_VSYNCERR0_IRQn = 77, |
| bogdanm | 0:9b334a45a8ff | 108 | GR3_VLINE0_IRQn = 78, |
| bogdanm | 0:9b334a45a8ff | 109 | S0_VFIELD0_IRQn = 79, |
| bogdanm | 0:9b334a45a8ff | 110 | IV1_VBUFERR0_IRQn = 80, |
| bogdanm | 0:9b334a45a8ff | 111 | IV3_VBUFERR0_IRQn = 81, |
| bogdanm | 0:9b334a45a8ff | 112 | IV5_VBUFERR0_IRQn = 82, |
| bogdanm | 0:9b334a45a8ff | 113 | IV6_VBUFERR0_IRQn = 83, |
| bogdanm | 0:9b334a45a8ff | 114 | S0_WLINE0_IRQn = 84, |
| bogdanm | 0:9b334a45a8ff | 115 | S1_VI_VSYNC0_IRQn = 85, |
| bogdanm | 0:9b334a45a8ff | 116 | S1_LO_VSYNC0_IRQn = 86, |
| bogdanm | 0:9b334a45a8ff | 117 | S1_VSYNCERR0_IRQn = 87, |
| bogdanm | 0:9b334a45a8ff | 118 | S1_VFIELD0_IRQn = 88, |
| bogdanm | 0:9b334a45a8ff | 119 | IV2_VBUFERR0_IRQn = 89, |
| bogdanm | 0:9b334a45a8ff | 120 | IV4_VBUFERR0_IRQn = 90, |
| bogdanm | 0:9b334a45a8ff | 121 | S1_WLINE0_IRQn = 91, |
| bogdanm | 0:9b334a45a8ff | 122 | OIR_VI_VSYNC0_IRQn = 92, |
| bogdanm | 0:9b334a45a8ff | 123 | OIR_LO_VSYNC0_IRQn = 93, |
| bogdanm | 0:9b334a45a8ff | 124 | OIR_VSYNCERR0_IRQn = 94, |
| bogdanm | 0:9b334a45a8ff | 125 | OIR_VFIELD0_IRQn = 95, |
| bogdanm | 0:9b334a45a8ff | 126 | IV7_VBUFERR0_IRQn = 96, |
| bogdanm | 0:9b334a45a8ff | 127 | IV8_VBUFERR0_IRQn = 97, |
| bogdanm | 0:9b334a45a8ff | 128 | /* 98 Reserved */ |
| bogdanm | 0:9b334a45a8ff | 129 | S0_VI_VSYNC1_IRQn = 99, |
| bogdanm | 0:9b334a45a8ff | 130 | S0_LO_VSYNC1_IRQn = 100, |
| bogdanm | 0:9b334a45a8ff | 131 | S0_VSYNCERR1_IRQn = 101, |
| bogdanm | 0:9b334a45a8ff | 132 | GR3_VLINE1_IRQn = 102, |
| bogdanm | 0:9b334a45a8ff | 133 | S0_VFIELD1_IRQn = 103, |
| bogdanm | 0:9b334a45a8ff | 134 | IV1_VBUFERR1_IRQn = 104, |
| bogdanm | 0:9b334a45a8ff | 135 | IV3_VBUFERR1_IRQn = 105, |
| bogdanm | 0:9b334a45a8ff | 136 | IV5_VBUFERR1_IRQn = 106, |
| bogdanm | 0:9b334a45a8ff | 137 | IV6_VBUFERR1_IRQn = 107, |
| bogdanm | 0:9b334a45a8ff | 138 | S0_WLINE1_IRQn = 108, |
| bogdanm | 0:9b334a45a8ff | 139 | S1_VI_VSYNC1_IRQn = 109, |
| bogdanm | 0:9b334a45a8ff | 140 | S1_LO_VSYNC1_IRQn = 110, |
| bogdanm | 0:9b334a45a8ff | 141 | S1_VSYNCERR1_IRQn = 111, |
| bogdanm | 0:9b334a45a8ff | 142 | S1_VFIELD1_IRQn = 112, |
| bogdanm | 0:9b334a45a8ff | 143 | IV2_VBUFERR1_IRQn = 113, |
| bogdanm | 0:9b334a45a8ff | 144 | IV4_VBUFERR1_IRQn = 114, |
| bogdanm | 0:9b334a45a8ff | 145 | S1_WLINE1_IRQn = 115, |
| bogdanm | 0:9b334a45a8ff | 146 | OIR_VI_VSYNC1_IRQn = 116, |
| bogdanm | 0:9b334a45a8ff | 147 | OIR_LO_VSYNC1_IRQn = 117, |
| bogdanm | 0:9b334a45a8ff | 148 | OIR_VSYNCERR1_IRQn = 118, |
| bogdanm | 0:9b334a45a8ff | 149 | OIR_VFIELD1_IRQn = 119, |
| bogdanm | 0:9b334a45a8ff | 150 | IV7_VBUFERR1_IRQn = 120, |
| bogdanm | 0:9b334a45a8ff | 151 | IV8_VBUFERR1_IRQn = 121, |
| bogdanm | 0:9b334a45a8ff | 152 | /* Reserved = 122 */ |
| bogdanm | 0:9b334a45a8ff | 153 | |
| bogdanm | 0:9b334a45a8ff | 154 | IMRDI_IRQn = 123, |
| bogdanm | 0:9b334a45a8ff | 155 | IMR2I0_IRQn = 124, |
| bogdanm | 0:9b334a45a8ff | 156 | IMR2I1_IRQn = 125, |
| bogdanm | 0:9b334a45a8ff | 157 | |
| bogdanm | 0:9b334a45a8ff | 158 | JEDI_IRQn = 126, |
| bogdanm | 0:9b334a45a8ff | 159 | JDTI_IRQn = 127, |
| bogdanm | 0:9b334a45a8ff | 160 | |
| bogdanm | 0:9b334a45a8ff | 161 | CMP0_IRQn = 128, |
| bogdanm | 0:9b334a45a8ff | 162 | CMP1_IRQn = 129, |
| bogdanm | 0:9b334a45a8ff | 163 | |
| bogdanm | 0:9b334a45a8ff | 164 | INT0_IRQn = 130, |
| bogdanm | 0:9b334a45a8ff | 165 | INT1_IRQn = 131, |
| bogdanm | 0:9b334a45a8ff | 166 | INT2_IRQn = 132, |
| bogdanm | 0:9b334a45a8ff | 167 | INT3_IRQn = 133, |
| bogdanm | 0:9b334a45a8ff | 168 | |
| bogdanm | 0:9b334a45a8ff | 169 | OSTMI0TINT_IRQn = 134, /*!< OSTM Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 170 | OSTMI1TINT_IRQn = 135, /*!< OSTM Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 171 | |
| bogdanm | 0:9b334a45a8ff | 172 | CMI_IRQn = 136, |
| bogdanm | 0:9b334a45a8ff | 173 | WTOUT_IRQn = 137, |
| bogdanm | 0:9b334a45a8ff | 174 | |
| bogdanm | 0:9b334a45a8ff | 175 | ITI_IRQn = 138, |
| bogdanm | 0:9b334a45a8ff | 176 | |
| bogdanm | 0:9b334a45a8ff | 177 | TGI0A_IRQn = 139, |
| bogdanm | 0:9b334a45a8ff | 178 | TGI0B_IRQn = 140, |
| bogdanm | 0:9b334a45a8ff | 179 | TGI0C_IRQn = 141, |
| bogdanm | 0:9b334a45a8ff | 180 | TGI0D_IRQn = 142, |
| bogdanm | 0:9b334a45a8ff | 181 | TGI0V_IRQn = 143, |
| bogdanm | 0:9b334a45a8ff | 182 | TGI0E_IRQn = 144, |
| bogdanm | 0:9b334a45a8ff | 183 | TGI0F_IRQn = 145, |
| bogdanm | 0:9b334a45a8ff | 184 | TGI1A_IRQn = 146, |
| bogdanm | 0:9b334a45a8ff | 185 | TGI1B_IRQn = 147, |
| bogdanm | 0:9b334a45a8ff | 186 | TGI1V_IRQn = 148, |
| bogdanm | 0:9b334a45a8ff | 187 | TGI1U_IRQn = 149, |
| bogdanm | 0:9b334a45a8ff | 188 | TGI2A_IRQn = 150, |
| bogdanm | 0:9b334a45a8ff | 189 | TGI2B_IRQn = 151, |
| bogdanm | 0:9b334a45a8ff | 190 | TGI2V_IRQn = 152, |
| bogdanm | 0:9b334a45a8ff | 191 | TGI2U_IRQn = 153, |
| bogdanm | 0:9b334a45a8ff | 192 | TGI3A_IRQn = 154, |
| bogdanm | 0:9b334a45a8ff | 193 | TGI3B_IRQn = 155, |
| bogdanm | 0:9b334a45a8ff | 194 | TGI3C_IRQn = 156, |
| bogdanm | 0:9b334a45a8ff | 195 | TGI3D_IRQn = 157, |
| bogdanm | 0:9b334a45a8ff | 196 | TGI3V_IRQn = 158, |
| bogdanm | 0:9b334a45a8ff | 197 | TGI4A_IRQn = 159, |
| bogdanm | 0:9b334a45a8ff | 198 | TGI4B_IRQn = 160, |
| bogdanm | 0:9b334a45a8ff | 199 | TGI4C_IRQn = 161, |
| bogdanm | 0:9b334a45a8ff | 200 | TGI4D_IRQn = 162, |
| bogdanm | 0:9b334a45a8ff | 201 | TGI4V_IRQn = 163, |
| bogdanm | 0:9b334a45a8ff | 202 | |
| bogdanm | 0:9b334a45a8ff | 203 | CMI1_IRQn = 164, |
| bogdanm | 0:9b334a45a8ff | 204 | CMI2_IRQn = 165, |
| bogdanm | 0:9b334a45a8ff | 205 | |
| bogdanm | 0:9b334a45a8ff | 206 | SGDEI0_IRQn = 166, |
| bogdanm | 0:9b334a45a8ff | 207 | SGDEI1_IRQn = 167, |
| bogdanm | 0:9b334a45a8ff | 208 | SGDEI2_IRQn = 168, |
| bogdanm | 0:9b334a45a8ff | 209 | SGDEI3_IRQn = 169, |
| bogdanm | 0:9b334a45a8ff | 210 | |
| bogdanm | 0:9b334a45a8ff | 211 | ADI_IRQn = 170, |
| bogdanm | 0:9b334a45a8ff | 212 | LMTI_IRQn = 171, |
| bogdanm | 0:9b334a45a8ff | 213 | |
| bogdanm | 0:9b334a45a8ff | 214 | SSII0_IRQn = 172, /*!< SSIF Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 215 | SSIRXI0_IRQn = 173, /*!< SSIF Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 216 | SSITXI0_IRQn = 174, /*!< SSIF Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 217 | SSII1_IRQn = 175, /*!< SSIF Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 218 | SSIRXI1_IRQn = 176, /*!< SSIF Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 219 | SSITXI1_IRQn = 177, /*!< SSIF Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 220 | SSII2_IRQn = 178, /*!< SSIF Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 221 | SSIRTI2_IRQn = 179, /*!< SSIF Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 222 | SSII3_IRQn = 180, /*!< SSIF Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 223 | SSIRXI3_IRQn = 181, /*!< SSIF Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 224 | SSITXI3_IRQn = 182, /*!< SSIF Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 225 | SSII4_IRQn = 183, /*!< SSIF Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 226 | SSIRTI4_IRQn = 184, /*!< SSIF Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 227 | SSII5_IRQn = 185, /*!< SSIF Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 228 | SSIRXI5_IRQn = 186, /*!< SSIF Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 229 | SSITXI5_IRQn = 187, /*!< SSIF Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 230 | |
| bogdanm | 0:9b334a45a8ff | 231 | SPDIFI_IRQn = 188, |
| bogdanm | 0:9b334a45a8ff | 232 | |
| bogdanm | 0:9b334a45a8ff | 233 | INTIICTEI0_IRQn = 189, /*!< RIIC Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 234 | INTIICRI0_IRQn = 190, /*!< RIIC Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 235 | INTIICTI0_IRQn = 191, /*!< RIIC Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 236 | INTIICSPI0_IRQn = 192, /*!< RIIC Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 237 | INTIICSTI0_IRQn = 193, /*!< RIIC Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 238 | INTIICNAKI0_IRQn = 194, /*!< RIIC Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 239 | INTIICALI0_IRQn = 195, /*!< RIIC Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 240 | INTIICTMOI0_IRQn = 196, /*!< RIIC Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 241 | INTIICTEI1_IRQn = 197, /*!< RIIC Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 242 | INTIICRI1_IRQn = 198, /*!< RIIC Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 243 | INTIICTI1_IRQn = 199, /*!< RIIC Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 244 | INTIICSPI1_IRQn = 200, /*!< RIIC Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 245 | INTIICSTI1_IRQn = 201, /*!< RIIC Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 246 | INTIICNAKI1_IRQn = 202, /*!< RIIC Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 247 | INTIICALI1_IRQn = 203, /*!< RIIC Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 248 | INTIICTMOI1_IRQn = 204, /*!< RIIC Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 249 | INTIICTEI2_IRQn = 205, /*!< RIIC Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 250 | INTIICRI2_IRQn = 206, /*!< RIIC Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 251 | INTIICTI2_IRQn = 207, /*!< RIIC Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 252 | INTIICSPI2_IRQn = 208, /*!< RIIC Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 253 | INTIICSTI2_IRQn = 209, /*!< RIIC Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 254 | INTIICNAKI2_IRQn = 210, /*!< RIIC Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 255 | INTIICALI2_IRQn = 211, /*!< RIIC Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 256 | INTIICTMOI2_IRQn = 212, /*!< RIIC Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 257 | INTIICTEI3_IRQn = 213, /*!< RIIC Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 258 | INTIICRI3_IRQn = 214, /*!< RIIC Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 259 | INTIICTI3_IRQn = 215, /*!< RIIC Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 260 | INTIICSPI3_IRQn = 216, /*!< RIIC Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 261 | INTIICSTI3_IRQn = 217, /*!< RIIC Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 262 | INTIICNAKI3_IRQn = 218, /*!< RIIC Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 263 | INTIICALI3_IRQn = 219, /*!< RIIC Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 264 | INTIICTMOI3_IRQn = 220, /*!< RIIC Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 265 | |
| bogdanm | 0:9b334a45a8ff | 266 | SCIFBRI0_IRQn = 221, /*!< SCIF Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 267 | SCIFERI0_IRQn = 222, /*!< SCIF Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 268 | SCIFRXI0_IRQn = 223, /*!< SCIF Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 269 | SCIFTXI0_IRQn = 224, /*!< SCIF Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 270 | SCIFBRI1_IRQn = 225, /*!< SCIF Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 271 | SCIFERI1_IRQn = 226, /*!< SCIF Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 272 | SCIFRXI1_IRQn = 227, /*!< SCIF Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 273 | SCIFTXI1_IRQn = 228, /*!< SCIF Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 274 | SCIFBRI2_IRQn = 229, /*!< SCIF Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 275 | SCIFERI2_IRQn = 230, /*!< SCIF Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 276 | SCIFRXI2_IRQn = 231, /*!< SCIF Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 277 | SCIFTXI2_IRQn = 232, /*!< SCIF Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 278 | SCIFBRI3_IRQn = 233, /*!< SCIF Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 279 | SCIFERI3_IRQn = 234, /*!< SCIF Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 280 | SCIFRXI3_IRQn = 235, /*!< SCIF Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 281 | SCIFTXI3_IRQn = 236, /*!< SCIF Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 282 | SCIFBRI4_IRQn = 237, /*!< SCIF Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 283 | SCIFERI4_IRQn = 238, /*!< SCIF Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 284 | SCIFRXI4_IRQn = 239, /*!< SCIF Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 285 | SCIFTXI4_IRQn = 240, /*!< SCIF Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 286 | SCIFBRI5_IRQn = 241, /*!< SCIF Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 287 | SCIFERI5_IRQn = 242, /*!< SCIF Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 288 | SCIFRXI5_IRQn = 243, /*!< SCIF Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 289 | SCIFTXI5_IRQn = 244, /*!< SCIF Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 290 | SCIFBRI6_IRQn = 245, /*!< SCIF Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 291 | SCIFERI6_IRQn = 246, /*!< SCIF Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 292 | SCIFRXI6_IRQn = 247, /*!< SCIF Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 293 | SCIFTXI6_IRQn = 248, /*!< SCIF Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 294 | SCIFBRI7_IRQn = 249, /*!< SCIF Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 295 | SCIFERI7_IRQn = 250, /*!< SCIF Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 296 | SCIFRXI7_IRQn = 251, /*!< SCIF Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 297 | SCIFTXI7_IRQn = 252, /*!< SCIF Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 298 | |
| bogdanm | 0:9b334a45a8ff | 299 | INTRCANGERR_IRQn = 253, |
| bogdanm | 0:9b334a45a8ff | 300 | INTRCANGRECC_IRQn = 254, |
| bogdanm | 0:9b334a45a8ff | 301 | INTRCAN0REC_IRQn = 255, |
| bogdanm | 0:9b334a45a8ff | 302 | INTRCAN0ERR_IRQn = 256, |
| bogdanm | 0:9b334a45a8ff | 303 | INTRCAN0TRX_IRQn = 257, |
| bogdanm | 0:9b334a45a8ff | 304 | INTRCAN1REC_IRQn = 258, |
| bogdanm | 0:9b334a45a8ff | 305 | INTRCAN1ERR_IRQn = 259, |
| bogdanm | 0:9b334a45a8ff | 306 | INTRCAN1TRX_IRQn = 260, |
| bogdanm | 0:9b334a45a8ff | 307 | INTRCAN2REC_IRQn = 261, |
| bogdanm | 0:9b334a45a8ff | 308 | INTRCAN2ERR_IRQn = 262, |
| bogdanm | 0:9b334a45a8ff | 309 | INTRCAN2TRX_IRQn = 263, |
| bogdanm | 0:9b334a45a8ff | 310 | INTRCAN3REC_IRQn = 264, |
| bogdanm | 0:9b334a45a8ff | 311 | INTRCAN3ERR_IRQn = 265, |
| bogdanm | 0:9b334a45a8ff | 312 | INTRCAN3TRX_IRQn = 266, |
| bogdanm | 0:9b334a45a8ff | 313 | INTRCAN4REC_IRQn = 267, |
| bogdanm | 0:9b334a45a8ff | 314 | INTRCAN4ERR_IRQn = 268, |
| bogdanm | 0:9b334a45a8ff | 315 | INTRCAN4TRX_IRQn = 269, |
| bogdanm | 0:9b334a45a8ff | 316 | |
| bogdanm | 0:9b334a45a8ff | 317 | RSPISPEI0_IRQn = 270, /*!< RSPI Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 318 | RSPISPRI0_IRQn = 271, /*!< RSPI Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 319 | RSPISPTI0_IRQn = 272, /*!< RSPI Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 320 | RSPISPEI1_IRQn = 273, /*!< RSPI Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 321 | RSPISPRI1_IRQn = 274, /*!< RSPI Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 322 | RSPISPTI1_IRQn = 275, /*!< RSPI Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 323 | RSPISPEI2_IRQn = 276, /*!< RSPI Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 324 | RSPISPRI2_IRQn = 277, /*!< RSPI Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 325 | RSPISPTI2_IRQn = 278, /*!< RSPI Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 326 | RSPISPEI3_IRQn = 279, /*!< RSPI Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 327 | RSPISPRI3_IRQn = 280, /*!< RSPI Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 328 | RSPISPTI3_IRQn = 281, /*!< RSPI Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 329 | RSPISPEI4_IRQn = 282, /*!< RSPI Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 330 | RSPISPRI4_IRQn = 283, /*!< RSPI Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 331 | RSPISPTI4_IRQn = 284, /*!< RSPI Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 332 | |
| bogdanm | 0:9b334a45a8ff | 333 | IEBBTD_IRQn = 285, |
| bogdanm | 0:9b334a45a8ff | 334 | IEBBTERR_IRQn = 286, |
| bogdanm | 0:9b334a45a8ff | 335 | IEBBTSTA_IRQn = 287, |
| bogdanm | 0:9b334a45a8ff | 336 | IEBBTV_IRQn = 288, |
| bogdanm | 0:9b334a45a8ff | 337 | |
| bogdanm | 0:9b334a45a8ff | 338 | ISY_IRQn = 289, |
| bogdanm | 0:9b334a45a8ff | 339 | IERR_IRQn = 290, |
| bogdanm | 0:9b334a45a8ff | 340 | ITARG_IRQn = 291, |
| bogdanm | 0:9b334a45a8ff | 341 | ISEC_IRQn = 292, |
| bogdanm | 0:9b334a45a8ff | 342 | IBUF_IRQn = 293, |
| bogdanm | 0:9b334a45a8ff | 343 | IREADY_IRQn = 294, |
| bogdanm | 0:9b334a45a8ff | 344 | |
| bogdanm | 0:9b334a45a8ff | 345 | STERB_IRQn = 295, |
| bogdanm | 0:9b334a45a8ff | 346 | FLTENDI_IRQn = 296, |
| bogdanm | 0:9b334a45a8ff | 347 | FLTREQ0I_IRQn = 297, |
| bogdanm | 0:9b334a45a8ff | 348 | FLTREQ1I_IRQn = 298, |
| bogdanm | 0:9b334a45a8ff | 349 | |
| bogdanm | 0:9b334a45a8ff | 350 | MMC0_IRQn = 299, |
| bogdanm | 0:9b334a45a8ff | 351 | MMC1_IRQn = 300, |
| bogdanm | 0:9b334a45a8ff | 352 | MMC2_IRQn = 301, |
| bogdanm | 0:9b334a45a8ff | 353 | |
| bogdanm | 0:9b334a45a8ff | 354 | SCHI0_3_IRQn = 302, |
| bogdanm | 0:9b334a45a8ff | 355 | SDHI0_0_IRQn = 303, |
| bogdanm | 0:9b334a45a8ff | 356 | SDHI0_1_IRQn = 304, |
| bogdanm | 0:9b334a45a8ff | 357 | SCHI1_3_IRQn = 305, |
| bogdanm | 0:9b334a45a8ff | 358 | SDHI1_0_IRQn = 306, |
| bogdanm | 0:9b334a45a8ff | 359 | SDHI1_1_IRQn = 307, |
| bogdanm | 0:9b334a45a8ff | 360 | |
| bogdanm | 0:9b334a45a8ff | 361 | ARM_IRQn = 308, |
| bogdanm | 0:9b334a45a8ff | 362 | PRD_IRQn = 309, |
| bogdanm | 0:9b334a45a8ff | 363 | CUP_IRQn = 310, |
| bogdanm | 0:9b334a45a8ff | 364 | |
| bogdanm | 0:9b334a45a8ff | 365 | SCUAI0_IRQn = 311, |
| bogdanm | 0:9b334a45a8ff | 366 | SCUAI1_IRQn = 312, |
| bogdanm | 0:9b334a45a8ff | 367 | SCUFDI0_IRQn = 313, |
| bogdanm | 0:9b334a45a8ff | 368 | SCUFDI1_IRQn = 314, |
| bogdanm | 0:9b334a45a8ff | 369 | SCUFDI2_IRQn = 315, |
| bogdanm | 0:9b334a45a8ff | 370 | SCUFDI3_IRQn = 316, |
| bogdanm | 0:9b334a45a8ff | 371 | SCUFUI0_IRQn = 317, |
| bogdanm | 0:9b334a45a8ff | 372 | SCUFUI1_IRQn = 318, |
| bogdanm | 0:9b334a45a8ff | 373 | SCUFUI2_IRQn = 319, |
| bogdanm | 0:9b334a45a8ff | 374 | SCUFUI3_IRQn = 320, |
| bogdanm | 0:9b334a45a8ff | 375 | SCUDVI0_IRQn = 321, |
| bogdanm | 0:9b334a45a8ff | 376 | SCUDVI1_IRQn = 322, |
| bogdanm | 0:9b334a45a8ff | 377 | SCUDVI2_IRQn = 323, |
| bogdanm | 0:9b334a45a8ff | 378 | SCUDVI3_IRQn = 324, |
| bogdanm | 0:9b334a45a8ff | 379 | |
| bogdanm | 0:9b334a45a8ff | 380 | MLB_CINT_IRQn = 325, |
| bogdanm | 0:9b334a45a8ff | 381 | MLB_SINT_IRQn = 326, |
| bogdanm | 0:9b334a45a8ff | 382 | |
| bogdanm | 0:9b334a45a8ff | 383 | DRC10_IRQn = 327, |
| bogdanm | 0:9b334a45a8ff | 384 | DRC11_IRQn = 328, |
| bogdanm | 0:9b334a45a8ff | 385 | |
| bogdanm | 0:9b334a45a8ff | 386 | /* 329-330 Reserved */ |
| bogdanm | 0:9b334a45a8ff | 387 | |
| bogdanm | 0:9b334a45a8ff | 388 | LINI0_INT_T_IRQn = 331, |
| bogdanm | 0:9b334a45a8ff | 389 | LINI0_INT_R_IRQn = 332, |
| bogdanm | 0:9b334a45a8ff | 390 | LINI0_INT_S_IRQn = 333, |
| bogdanm | 0:9b334a45a8ff | 391 | LINI0_INT_M_IRQn = 334, |
| bogdanm | 0:9b334a45a8ff | 392 | LINI1_INT_T_IRQn = 335, |
| bogdanm | 0:9b334a45a8ff | 393 | LINI1_INT_R_IRQn = 336, |
| bogdanm | 0:9b334a45a8ff | 394 | LINI1_INT_S_IRQn = 337, |
| bogdanm | 0:9b334a45a8ff | 395 | LINI1_INT_M_IRQn = 338, |
| bogdanm | 0:9b334a45a8ff | 396 | |
| bogdanm | 0:9b334a45a8ff | 397 | /* 339-346 Reserved */ |
| bogdanm | 0:9b334a45a8ff | 398 | |
| bogdanm | 0:9b334a45a8ff | 399 | SCIERI0_IRQn = 347, |
| bogdanm | 0:9b334a45a8ff | 400 | SCIRXI0_IRQn = 348, |
| bogdanm | 0:9b334a45a8ff | 401 | SCITXI0_IRQn = 349, |
| bogdanm | 0:9b334a45a8ff | 402 | SCITEI0_IRQn = 350, |
| bogdanm | 0:9b334a45a8ff | 403 | SCIERI1_IRQn = 351, |
| bogdanm | 0:9b334a45a8ff | 404 | SCIRXI1_IRQn = 352, |
| bogdanm | 0:9b334a45a8ff | 405 | SCITXI1_IRQn = 353, |
| bogdanm | 0:9b334a45a8ff | 406 | SCITEI1_IRQn = 354, |
| bogdanm | 0:9b334a45a8ff | 407 | |
| bogdanm | 0:9b334a45a8ff | 408 | AVBI_DATA = 355, |
| bogdanm | 0:9b334a45a8ff | 409 | AVBI_ERROR = 356, |
| bogdanm | 0:9b334a45a8ff | 410 | AVBI_MANAGE = 357, |
| bogdanm | 0:9b334a45a8ff | 411 | AVBI_MAC = 358, |
| bogdanm | 0:9b334a45a8ff | 412 | |
| bogdanm | 0:9b334a45a8ff | 413 | ETHERI_IRQn = 359, |
| bogdanm | 0:9b334a45a8ff | 414 | |
| bogdanm | 0:9b334a45a8ff | 415 | /* 360-363 Reserved */ |
| bogdanm | 0:9b334a45a8ff | 416 | |
| bogdanm | 0:9b334a45a8ff | 417 | CEUI_IRQn = 364, |
| bogdanm | 0:9b334a45a8ff | 418 | |
| bogdanm | 0:9b334a45a8ff | 419 | /* 365-380 Reserved */ |
| bogdanm | 0:9b334a45a8ff | 420 | |
| bogdanm | 0:9b334a45a8ff | 421 | |
| bogdanm | 0:9b334a45a8ff | 422 | H2XMLB_ERRINT_IRQn = 381, |
| bogdanm | 0:9b334a45a8ff | 423 | H2XIC1_ERRINT_IRQn = 382, |
| bogdanm | 0:9b334a45a8ff | 424 | X2HPERI1_ERRINT_IRQn = 383, |
| bogdanm | 0:9b334a45a8ff | 425 | X2HPERR2_ERRINT_IRQn = 384, |
| bogdanm | 0:9b334a45a8ff | 426 | X2HPERR34_ERRINT_IRQn= 385, |
| bogdanm | 0:9b334a45a8ff | 427 | X2HPERR5_ERRINT_IRQn = 386, |
| bogdanm | 0:9b334a45a8ff | 428 | X2HPERR67_ERRINT_IRQn= 387, |
| bogdanm | 0:9b334a45a8ff | 429 | X2HDBGR_ERRINT_IRQn = 388, |
| bogdanm | 0:9b334a45a8ff | 430 | X2HBSC_ERRINT_IRQn = 389, |
| bogdanm | 0:9b334a45a8ff | 431 | X2HSPI1_ERRINT_IRQn = 390, |
| bogdanm | 0:9b334a45a8ff | 432 | X2HSPI2_ERRINT_IRQn = 391, |
| bogdanm | 0:9b334a45a8ff | 433 | PRRI_IRQn = 392, |
| bogdanm | 0:9b334a45a8ff | 434 | |
| bogdanm | 0:9b334a45a8ff | 435 | IFEI0_IRQn = 393, |
| bogdanm | 0:9b334a45a8ff | 436 | OFFI0_IRQn = 394, |
| bogdanm | 0:9b334a45a8ff | 437 | PFVEI0_IRQn = 395, |
| bogdanm | 0:9b334a45a8ff | 438 | IFEI1_IRQn = 396, |
| bogdanm | 0:9b334a45a8ff | 439 | OFFI1_IRQn = 397, |
| bogdanm | 0:9b334a45a8ff | 440 | PFVEI1_IRQn = 398, |
| bogdanm | 0:9b334a45a8ff | 441 | |
| bogdanm | 0:9b334a45a8ff | 442 | /* 399-415 Reserved */ |
| bogdanm | 0:9b334a45a8ff | 443 | TINT0_IRQn = 416, |
| bogdanm | 0:9b334a45a8ff | 444 | TINT1_IRQn = 417, |
| bogdanm | 0:9b334a45a8ff | 445 | TINT2_IRQn = 418, |
| bogdanm | 0:9b334a45a8ff | 446 | TINT3_IRQn = 419, |
| bogdanm | 0:9b334a45a8ff | 447 | TINT4_IRQn = 420, |
| bogdanm | 0:9b334a45a8ff | 448 | TINT5_IRQn = 421, |
| bogdanm | 0:9b334a45a8ff | 449 | TINT6_IRQn = 422, |
| bogdanm | 0:9b334a45a8ff | 450 | TINT7_IRQn = 423, |
| bogdanm | 0:9b334a45a8ff | 451 | TINT8_IRQn = 424, |
| bogdanm | 0:9b334a45a8ff | 452 | TINT9_IRQn = 425, |
| bogdanm | 0:9b334a45a8ff | 453 | TINT10_IRQn = 426, |
| bogdanm | 0:9b334a45a8ff | 454 | TINT11_IRQn = 427, |
| bogdanm | 0:9b334a45a8ff | 455 | TINT12_IRQn = 428, |
| bogdanm | 0:9b334a45a8ff | 456 | TINT13_IRQn = 429, |
| bogdanm | 0:9b334a45a8ff | 457 | TINT14_IRQn = 430, |
| bogdanm | 0:9b334a45a8ff | 458 | TINT15_IRQn = 431, |
| bogdanm | 0:9b334a45a8ff | 459 | TINT16_IRQn = 432, |
| bogdanm | 0:9b334a45a8ff | 460 | TINT17_IRQn = 433, |
| bogdanm | 0:9b334a45a8ff | 461 | TINT18_IRQn = 434, |
| bogdanm | 0:9b334a45a8ff | 462 | TINT19_IRQn = 435, |
| bogdanm | 0:9b334a45a8ff | 463 | TINT20_IRQn = 436, |
| bogdanm | 0:9b334a45a8ff | 464 | TINT21_IRQn = 437, |
| bogdanm | 0:9b334a45a8ff | 465 | TINT22_IRQn = 438, |
| bogdanm | 0:9b334a45a8ff | 466 | TINT23_IRQn = 439, |
| bogdanm | 0:9b334a45a8ff | 467 | TINT24_IRQn = 440, |
| bogdanm | 0:9b334a45a8ff | 468 | TINT25_IRQn = 441, |
| bogdanm | 0:9b334a45a8ff | 469 | TINT26_IRQn = 442, |
| bogdanm | 0:9b334a45a8ff | 470 | TINT27_IRQn = 443, |
| bogdanm | 0:9b334a45a8ff | 471 | TINT28_IRQn = 444, |
| bogdanm | 0:9b334a45a8ff | 472 | TINT29_IRQn = 445, |
| bogdanm | 0:9b334a45a8ff | 473 | TINT30_IRQn = 446, |
| bogdanm | 0:9b334a45a8ff | 474 | TINT31_IRQn = 447, |
| bogdanm | 0:9b334a45a8ff | 475 | TINT32_IRQn = 448, |
| bogdanm | 0:9b334a45a8ff | 476 | TINT33_IRQn = 449, |
| bogdanm | 0:9b334a45a8ff | 477 | TINT34_IRQn = 450, |
| bogdanm | 0:9b334a45a8ff | 478 | TINT35_IRQn = 451, |
| bogdanm | 0:9b334a45a8ff | 479 | TINT36_IRQn = 452, |
| bogdanm | 0:9b334a45a8ff | 480 | TINT37_IRQn = 453, |
| bogdanm | 0:9b334a45a8ff | 481 | TINT38_IRQn = 454, |
| bogdanm | 0:9b334a45a8ff | 482 | TINT39_IRQn = 455, |
| bogdanm | 0:9b334a45a8ff | 483 | TINT40_IRQn = 456, |
| bogdanm | 0:9b334a45a8ff | 484 | TINT41_IRQn = 457, |
| bogdanm | 0:9b334a45a8ff | 485 | TINT42_IRQn = 458, |
| bogdanm | 0:9b334a45a8ff | 486 | TINT43_IRQn = 459, |
| bogdanm | 0:9b334a45a8ff | 487 | TINT44_IRQn = 460, |
| bogdanm | 0:9b334a45a8ff | 488 | TINT45_IRQn = 461, |
| bogdanm | 0:9b334a45a8ff | 489 | TINT46_IRQn = 462, |
| bogdanm | 0:9b334a45a8ff | 490 | TINT47_IRQn = 463, |
| bogdanm | 0:9b334a45a8ff | 491 | TINT48_IRQn = 464, |
| bogdanm | 0:9b334a45a8ff | 492 | TINT49_IRQn = 465, |
| bogdanm | 0:9b334a45a8ff | 493 | TINT50_IRQn = 466, |
| bogdanm | 0:9b334a45a8ff | 494 | TINT51_IRQn = 467, |
| bogdanm | 0:9b334a45a8ff | 495 | TINT52_IRQn = 468, |
| bogdanm | 0:9b334a45a8ff | 496 | TINT53_IRQn = 469, |
| bogdanm | 0:9b334a45a8ff | 497 | TINT54_IRQn = 470, |
| bogdanm | 0:9b334a45a8ff | 498 | TINT55_IRQn = 471, |
| bogdanm | 0:9b334a45a8ff | 499 | TINT56_IRQn = 472, |
| bogdanm | 0:9b334a45a8ff | 500 | TINT57_IRQn = 473, |
| bogdanm | 0:9b334a45a8ff | 501 | TINT58_IRQn = 474, |
| bogdanm | 0:9b334a45a8ff | 502 | TINT59_IRQn = 475, |
| bogdanm | 0:9b334a45a8ff | 503 | TINT60_IRQn = 476, |
| bogdanm | 0:9b334a45a8ff | 504 | TINT61_IRQn = 477, |
| bogdanm | 0:9b334a45a8ff | 505 | TINT62_IRQn = 478, |
| bogdanm | 0:9b334a45a8ff | 506 | TINT63_IRQn = 479, |
| bogdanm | 0:9b334a45a8ff | 507 | TINT64_IRQn = 480, |
| bogdanm | 0:9b334a45a8ff | 508 | TINT65_IRQn = 481, |
| bogdanm | 0:9b334a45a8ff | 509 | TINT66_IRQn = 482, |
| bogdanm | 0:9b334a45a8ff | 510 | TINT67_IRQn = 483, |
| bogdanm | 0:9b334a45a8ff | 511 | TINT68_IRQn = 484, |
| bogdanm | 0:9b334a45a8ff | 512 | TINT69_IRQn = 485, |
| bogdanm | 0:9b334a45a8ff | 513 | TINT70_IRQn = 486, |
| bogdanm | 0:9b334a45a8ff | 514 | TINT71_IRQn = 487, |
| bogdanm | 0:9b334a45a8ff | 515 | TINT72_IRQn = 488, |
| bogdanm | 0:9b334a45a8ff | 516 | TINT73_IRQn = 489, |
| bogdanm | 0:9b334a45a8ff | 517 | TINT74_IRQn = 490, |
| bogdanm | 0:9b334a45a8ff | 518 | TINT75_IRQn = 491, |
| bogdanm | 0:9b334a45a8ff | 519 | TINT76_IRQn = 492, |
| bogdanm | 0:9b334a45a8ff | 520 | TINT77_IRQn = 493, |
| bogdanm | 0:9b334a45a8ff | 521 | TINT78_IRQn = 494, |
| bogdanm | 0:9b334a45a8ff | 522 | TINT79_IRQn = 495, |
| bogdanm | 0:9b334a45a8ff | 523 | TINT80_IRQn = 496, |
| bogdanm | 0:9b334a45a8ff | 524 | TINT81_IRQn = 497, |
| bogdanm | 0:9b334a45a8ff | 525 | TINT82_IRQn = 498, |
| bogdanm | 0:9b334a45a8ff | 526 | TINT83_IRQn = 499, |
| bogdanm | 0:9b334a45a8ff | 527 | TINT84_IRQn = 500, |
| bogdanm | 0:9b334a45a8ff | 528 | TINT85_IRQn = 501, |
| bogdanm | 0:9b334a45a8ff | 529 | TINT86_IRQn = 502, |
| bogdanm | 0:9b334a45a8ff | 530 | TINT87_IRQn = 503, |
| bogdanm | 0:9b334a45a8ff | 531 | TINT88_IRQn = 504, |
| bogdanm | 0:9b334a45a8ff | 532 | TINT89_IRQn = 505, |
| bogdanm | 0:9b334a45a8ff | 533 | TINT90_IRQn = 506, |
| bogdanm | 0:9b334a45a8ff | 534 | TINT91_IRQn = 507, |
| bogdanm | 0:9b334a45a8ff | 535 | TINT92_IRQn = 508, |
| bogdanm | 0:9b334a45a8ff | 536 | TINT93_IRQn = 509, |
| bogdanm | 0:9b334a45a8ff | 537 | TINT94_IRQn = 510, |
| bogdanm | 0:9b334a45a8ff | 538 | TINT95_IRQn = 511, |
| bogdanm | 0:9b334a45a8ff | 539 | TINT96_IRQn = 512, |
| bogdanm | 0:9b334a45a8ff | 540 | TINT97_IRQn = 513, |
| bogdanm | 0:9b334a45a8ff | 541 | TINT98_IRQn = 514, |
| bogdanm | 0:9b334a45a8ff | 542 | TINT99_IRQn = 515, |
| bogdanm | 0:9b334a45a8ff | 543 | TINT100_IRQn = 516, |
| bogdanm | 0:9b334a45a8ff | 544 | TINT101_IRQn = 517, |
| bogdanm | 0:9b334a45a8ff | 545 | TINT102_IRQn = 518, |
| bogdanm | 0:9b334a45a8ff | 546 | TINT103_IRQn = 519, |
| bogdanm | 0:9b334a45a8ff | 547 | TINT104_IRQn = 520, |
| bogdanm | 0:9b334a45a8ff | 548 | TINT105_IRQn = 521, |
| bogdanm | 0:9b334a45a8ff | 549 | TINT106_IRQn = 522, |
| bogdanm | 0:9b334a45a8ff | 550 | TINT107_IRQn = 523, |
| bogdanm | 0:9b334a45a8ff | 551 | TINT108_IRQn = 524, |
| bogdanm | 0:9b334a45a8ff | 552 | TINT109_IRQn = 525, |
| bogdanm | 0:9b334a45a8ff | 553 | TINT110_IRQn = 526, |
| bogdanm | 0:9b334a45a8ff | 554 | TINT111_IRQn = 527, |
| bogdanm | 0:9b334a45a8ff | 555 | TINT112_IRQn = 528, |
| bogdanm | 0:9b334a45a8ff | 556 | TINT113_IRQn = 529, |
| bogdanm | 0:9b334a45a8ff | 557 | TINT114_IRQn = 530, |
| bogdanm | 0:9b334a45a8ff | 558 | TINT115_IRQn = 531, |
| bogdanm | 0:9b334a45a8ff | 559 | TINT116_IRQn = 532, |
| bogdanm | 0:9b334a45a8ff | 560 | TINT117_IRQn = 533, |
| bogdanm | 0:9b334a45a8ff | 561 | TINT118_IRQn = 534, |
| bogdanm | 0:9b334a45a8ff | 562 | TINT119_IRQn = 535, |
| bogdanm | 0:9b334a45a8ff | 563 | TINT120_IRQn = 536, |
| bogdanm | 0:9b334a45a8ff | 564 | TINT121_IRQn = 537, |
| bogdanm | 0:9b334a45a8ff | 565 | TINT122_IRQn = 538, |
| bogdanm | 0:9b334a45a8ff | 566 | TINT123_IRQn = 539, |
| bogdanm | 0:9b334a45a8ff | 567 | TINT124_IRQn = 540, |
| bogdanm | 0:9b334a45a8ff | 568 | TINT125_IRQn = 541, |
| bogdanm | 0:9b334a45a8ff | 569 | TINT126_IRQn = 542, |
| bogdanm | 0:9b334a45a8ff | 570 | TINT127_IRQn = 543, |
| bogdanm | 0:9b334a45a8ff | 571 | TINT128_IRQn = 544, |
| bogdanm | 0:9b334a45a8ff | 572 | TINT129_IRQn = 545, |
| bogdanm | 0:9b334a45a8ff | 573 | TINT130_IRQn = 546, |
| bogdanm | 0:9b334a45a8ff | 574 | TINT131_IRQn = 547, |
| bogdanm | 0:9b334a45a8ff | 575 | TINT132_IRQn = 548, |
| bogdanm | 0:9b334a45a8ff | 576 | TINT133_IRQn = 549, |
| bogdanm | 0:9b334a45a8ff | 577 | TINT134_IRQn = 550, |
| bogdanm | 0:9b334a45a8ff | 578 | TINT135_IRQn = 551, |
| bogdanm | 0:9b334a45a8ff | 579 | TINT136_IRQn = 552, |
| bogdanm | 0:9b334a45a8ff | 580 | TINT137_IRQn = 553, |
| bogdanm | 0:9b334a45a8ff | 581 | TINT138_IRQn = 554, |
| bogdanm | 0:9b334a45a8ff | 582 | TINT139_IRQn = 555, |
| bogdanm | 0:9b334a45a8ff | 583 | TINT140_IRQn = 556, |
| bogdanm | 0:9b334a45a8ff | 584 | TINT141_IRQn = 557, |
| bogdanm | 0:9b334a45a8ff | 585 | TINT142_IRQn = 558, |
| bogdanm | 0:9b334a45a8ff | 586 | TINT143_IRQn = 559, |
| bogdanm | 0:9b334a45a8ff | 587 | TINT144_IRQn = 560, |
| bogdanm | 0:9b334a45a8ff | 588 | TINT145_IRQn = 561, |
| bogdanm | 0:9b334a45a8ff | 589 | TINT146_IRQn = 562, |
| bogdanm | 0:9b334a45a8ff | 590 | TINT147_IRQn = 563, |
| bogdanm | 0:9b334a45a8ff | 591 | TINT148_IRQn = 564, |
| bogdanm | 0:9b334a45a8ff | 592 | TINT149_IRQn = 565, |
| bogdanm | 0:9b334a45a8ff | 593 | TINT150_IRQn = 566, |
| bogdanm | 0:9b334a45a8ff | 594 | TINT151_IRQn = 567, |
| bogdanm | 0:9b334a45a8ff | 595 | TINT152_IRQn = 568, |
| bogdanm | 0:9b334a45a8ff | 596 | TINT153_IRQn = 569, |
| bogdanm | 0:9b334a45a8ff | 597 | TINT154_IRQn = 570, |
| bogdanm | 0:9b334a45a8ff | 598 | TINT155_IRQn = 571, |
| bogdanm | 0:9b334a45a8ff | 599 | TINT156_IRQn = 572, |
| bogdanm | 0:9b334a45a8ff | 600 | TINT157_IRQn = 573, |
| bogdanm | 0:9b334a45a8ff | 601 | TINT158_IRQn = 574, |
| bogdanm | 0:9b334a45a8ff | 602 | TINT159_IRQn = 575, |
| bogdanm | 0:9b334a45a8ff | 603 | TINT160_IRQn = 576, |
| bogdanm | 0:9b334a45a8ff | 604 | TINT161_IRQn = 577, |
| bogdanm | 0:9b334a45a8ff | 605 | TINT162_IRQn = 578, |
| bogdanm | 0:9b334a45a8ff | 606 | TINT163_IRQn = 579, |
| bogdanm | 0:9b334a45a8ff | 607 | TINT164_IRQn = 580, |
| bogdanm | 0:9b334a45a8ff | 608 | TINT165_IRQn = 581, |
| bogdanm | 0:9b334a45a8ff | 609 | TINT166_IRQn = 582, |
| bogdanm | 0:9b334a45a8ff | 610 | TINT167_IRQn = 583, |
| bogdanm | 0:9b334a45a8ff | 611 | TINT168_IRQn = 584, |
| bogdanm | 0:9b334a45a8ff | 612 | TINT169_IRQn = 585, |
| bogdanm | 0:9b334a45a8ff | 613 | TINT170_IRQn = 586 |
| bogdanm | 0:9b334a45a8ff | 614 | |
| bogdanm | 0:9b334a45a8ff | 615 | } IRQn_Type; |
| bogdanm | 0:9b334a45a8ff | 616 | |
| bogdanm | 0:9b334a45a8ff | 617 | #define Renesas_RZ_A1_IRQ_MAX TINT170_IRQn |
| bogdanm | 0:9b334a45a8ff | 618 | |
| bogdanm | 0:9b334a45a8ff | 619 | /* -------- Configuration of the Cortex-A9 Processor and Core Peripherals ------- */ |
| bogdanm | 0:9b334a45a8ff | 620 | #define __CA9_REV 0x0000 /*!< Core revision r0 */ |
| bogdanm | 0:9b334a45a8ff | 621 | |
| bogdanm | 0:9b334a45a8ff | 622 | #define __MPU_PRESENT 1 /*!< MPU present or not */ |
| bogdanm | 0:9b334a45a8ff | 623 | |
| bogdanm | 0:9b334a45a8ff | 624 | #define __FPU_PRESENT 1 /*!< FPU present or not */ |
| bogdanm | 0:9b334a45a8ff | 625 | |
| bogdanm | 0:9b334a45a8ff | 626 | #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */ |
| bogdanm | 0:9b334a45a8ff | 627 | #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ |
| bogdanm | 0:9b334a45a8ff | 628 | |
| bogdanm | 0:9b334a45a8ff | 629 | #include <core_ca9.h> |
| bogdanm | 0:9b334a45a8ff | 630 | #include "system_MBRZA1H.h" |
| bogdanm | 0:9b334a45a8ff | 631 | |
| bogdanm | 0:9b334a45a8ff | 632 | |
| bogdanm | 0:9b334a45a8ff | 633 | /******************************************************************************/ |
| bogdanm | 0:9b334a45a8ff | 634 | /* Device Specific Peripheral Section */ |
| bogdanm | 0:9b334a45a8ff | 635 | /******************************************************************************/ |
| bogdanm | 0:9b334a45a8ff | 636 | /** @addtogroup Renesas_RZ_A1_Peripherals Renesas_RZ_A1 Peripherals |
| bogdanm | 0:9b334a45a8ff | 637 | Renesas_RZ_A1 Device Specific Peripheral registers structures |
| bogdanm | 0:9b334a45a8ff | 638 | @{ |
| bogdanm | 0:9b334a45a8ff | 639 | */ |
| bogdanm | 0:9b334a45a8ff | 640 | |
| bogdanm | 0:9b334a45a8ff | 641 | #if defined ( __CC_ARM ) |
| bogdanm | 0:9b334a45a8ff | 642 | #pragma anon_unions |
| bogdanm | 0:9b334a45a8ff | 643 | #endif |
| bogdanm | 0:9b334a45a8ff | 644 | |
| bogdanm | 0:9b334a45a8ff | 645 | #include "pl310.h" |
| bogdanm | 0:9b334a45a8ff | 646 | #include "gic.h" |
| bogdanm | 0:9b334a45a8ff | 647 | #include "nvic_wrapper.h" |
| bogdanm | 0:9b334a45a8ff | 648 | #include "cmsis_nvic.h" |
| bogdanm | 0:9b334a45a8ff | 649 | |
| bogdanm | 0:9b334a45a8ff | 650 | #include "ostm_iodefine.h" |
| bogdanm | 0:9b334a45a8ff | 651 | #include "gpio_iodefine.h" |
| bogdanm | 0:9b334a45a8ff | 652 | #include "cpg_iodefine.h" |
| bogdanm | 0:9b334a45a8ff | 653 | #include "l2c_iodefine.h" |
| bogdanm | 0:9b334a45a8ff | 654 | |
| bogdanm | 0:9b334a45a8ff | 655 | #if defined ( __CC_ARM ) |
| bogdanm | 0:9b334a45a8ff | 656 | #pragma no_anon_unions |
| bogdanm | 0:9b334a45a8ff | 657 | #endif |
| bogdanm | 0:9b334a45a8ff | 658 | |
| bogdanm | 0:9b334a45a8ff | 659 | /*@}*/ /* end of group Renesas_RZ_A1_Peripherals */ |
| bogdanm | 0:9b334a45a8ff | 660 | |
| bogdanm | 0:9b334a45a8ff | 661 | |
| bogdanm | 0:9b334a45a8ff | 662 | /******************************************************************************/ |
| bogdanm | 0:9b334a45a8ff | 663 | /* Peripheral memory map */ |
| bogdanm | 0:9b334a45a8ff | 664 | /******************************************************************************/ |
| bogdanm | 0:9b334a45a8ff | 665 | /** @addtogroup Renesas_RZ_A1_MemoryMap Renesas_RZ_A1 Memory Mapping |
| bogdanm | 0:9b334a45a8ff | 666 | @{ |
| bogdanm | 0:9b334a45a8ff | 667 | */ |
| bogdanm | 0:9b334a45a8ff | 668 | |
| bogdanm | 0:9b334a45a8ff | 669 | /* R7S72100 CPU board */ |
| bogdanm | 0:9b334a45a8ff | 670 | #define Renesas_RZ_A1_NORFLASH_BASE0 (0x00000000UL) /*!< (FLASH0 ) Base Address */ |
| bogdanm | 0:9b334a45a8ff | 671 | #define Renesas_RZ_A1_NORFLASH_BASE1 (0x04000000UL) /*!< (FLASH1 ) Base Address */ |
| bogdanm | 0:9b334a45a8ff | 672 | #define Renesas_RZ_A1_SDRAM_BASE0 (0x08000000UL) /*!< (SDRAM0 ) Base Address */ |
| bogdanm | 0:9b334a45a8ff | 673 | #define Renesas_RZ_A1_SDRAM_BASE1 (0x0C000000UL) /*!< (SDRAM1 ) Base Address */ |
| bogdanm | 0:9b334a45a8ff | 674 | #define Renesas_RZ_A1_USER_AREA0 (0x10000000UL) /*!< (USER0 ) Base Address */ |
| bogdanm | 0:9b334a45a8ff | 675 | #define Renesas_RZ_A1_USER_AREA1 (0x14000000UL) /*!< (USER1 ) Base Address */ |
| bogdanm | 0:9b334a45a8ff | 676 | #define Renesas_RZ_A1_SPI_IO0 (0x18000000UL) /*!< (SPI_IO0 ) Base Address */ |
| bogdanm | 0:9b334a45a8ff | 677 | #define Renesas_RZ_A1_SPI_IO1 (0x1C000000UL) /*!< (SPI_IO1 ) Base Address */ |
| bogdanm | 0:9b334a45a8ff | 678 | #define Renesas_RZ_A1_ONCHIP_SRAM_BASE (0x20000000UL) /*!< (SRAM_OC ) Base Address */ |
| bogdanm | 0:9b334a45a8ff | 679 | #define Renesas_RZ_A1_SPI_MIO_BASE (0x3fe00000UL) /*!< (SPI_MIO ) Base Address */ |
| bogdanm | 0:9b334a45a8ff | 680 | #define Renesas_RZ_A1_BSC_BASE (0x3ff00000UL) /*!< (BSC ) Base Address */ |
| bogdanm | 0:9b334a45a8ff | 681 | #define Renesas_RZ_A1_PERIPH_BASE0 (0xe8000000UL) /*!< (PERIPH0 ) Base Address */ |
| bogdanm | 0:9b334a45a8ff | 682 | #define Renesas_RZ_A1_PERIPH_BASE1 (0xfcf00000UL) /*!< (PERIPH1 ) Base Address */ |
| bogdanm | 0:9b334a45a8ff | 683 | #define Renesas_RZ_A1_GIC_DISTRIBUTOR_BASE (0xe8201000UL) /*!< (GIC DIST ) Base Address */ |
| bogdanm | 0:9b334a45a8ff | 684 | #define Renesas_RZ_A1_GIC_INTERFACE_BASE (0xe8202000UL) /*!< (GIC CPU IF) Base Address */ |
| bogdanm | 0:9b334a45a8ff | 685 | #define Renesas_RZ_A1_PL310_BASE (0x3ffff000UL) /*!< (PL310 ) Base Address */ |
| bogdanm | 0:9b334a45a8ff | 686 | #define Renesas_RZ_A1_ONCHIP_SRAM_NC_BASE (0x60000000UL) /*!< (SRAM_OC ) Base Address */ |
| bogdanm | 0:9b334a45a8ff | 687 | |
| bogdanm | 0:9b334a45a8ff | 688 | //Following macros define the descriptors and attributes used to define the Renesas_RZ_A1 MMU flat-map |
| bogdanm | 0:9b334a45a8ff | 689 | //Sect_Normal. Outer & inner wb/wa, non-shareable, executable, rw, domain 0. |
| bogdanm | 0:9b334a45a8ff | 690 | #define section_normal(descriptor_l1, region) region.rg_t = SECTION; \ |
| bogdanm | 0:9b334a45a8ff | 691 | region.domain = 0x0; \ |
| bogdanm | 0:9b334a45a8ff | 692 | region.e_t = ECC_DISABLED; \ |
| bogdanm | 0:9b334a45a8ff | 693 | region.g_t = GLOBAL; \ |
| bogdanm | 0:9b334a45a8ff | 694 | region.inner_norm_t = WB_WA; \ |
| bogdanm | 0:9b334a45a8ff | 695 | region.outer_norm_t = WB_WA; \ |
| bogdanm | 0:9b334a45a8ff | 696 | region.mem_t = NORMAL; \ |
| bogdanm | 0:9b334a45a8ff | 697 | region.sec_t = NON_SECURE; \ |
| bogdanm | 0:9b334a45a8ff | 698 | region.xn_t = EXECUTE; \ |
| bogdanm | 0:9b334a45a8ff | 699 | region.priv_t = RW; \ |
| bogdanm | 0:9b334a45a8ff | 700 | region.user_t = RW; \ |
| bogdanm | 0:9b334a45a8ff | 701 | region.sh_t = NON_SHARED; \ |
| bogdanm | 0:9b334a45a8ff | 702 | __get_section_descriptor(&descriptor_l1, region); |
| bogdanm | 0:9b334a45a8ff | 703 | |
| bogdanm | 0:9b334a45a8ff | 704 | #define section_normal_nc(descriptor_l1, region) region.rg_t = SECTION; \ |
| bogdanm | 0:9b334a45a8ff | 705 | region.domain = 0x0; \ |
| bogdanm | 0:9b334a45a8ff | 706 | region.e_t = ECC_DISABLED; \ |
| bogdanm | 0:9b334a45a8ff | 707 | region.g_t = GLOBAL; \ |
| bogdanm | 0:9b334a45a8ff | 708 | region.inner_norm_t = NON_CACHEABLE; \ |
| bogdanm | 0:9b334a45a8ff | 709 | region.outer_norm_t = NON_CACHEABLE; \ |
| bogdanm | 0:9b334a45a8ff | 710 | region.mem_t = NORMAL; \ |
| bogdanm | 0:9b334a45a8ff | 711 | region.sec_t = SECURE; \ |
| bogdanm | 0:9b334a45a8ff | 712 | region.xn_t = EXECUTE; \ |
| bogdanm | 0:9b334a45a8ff | 713 | region.priv_t = RW; \ |
| bogdanm | 0:9b334a45a8ff | 714 | region.user_t = RW; \ |
| bogdanm | 0:9b334a45a8ff | 715 | region.sh_t = NON_SHARED; \ |
| bogdanm | 0:9b334a45a8ff | 716 | __get_section_descriptor(&descriptor_l1, region); |
| bogdanm | 0:9b334a45a8ff | 717 | |
| bogdanm | 0:9b334a45a8ff | 718 | //Sect_Normal_Cod. Outer & inner wb/wa, non-shareable, executable, ro, domain 0. |
| bogdanm | 0:9b334a45a8ff | 719 | #define section_normal_cod(descriptor_l1, region) region.rg_t = SECTION; \ |
| bogdanm | 0:9b334a45a8ff | 720 | region.domain = 0x0; \ |
| bogdanm | 0:9b334a45a8ff | 721 | region.e_t = ECC_DISABLED; \ |
| bogdanm | 0:9b334a45a8ff | 722 | region.g_t = GLOBAL; \ |
| bogdanm | 0:9b334a45a8ff | 723 | region.inner_norm_t = WB_WA; \ |
| bogdanm | 0:9b334a45a8ff | 724 | region.outer_norm_t = WB_WA; \ |
| bogdanm | 0:9b334a45a8ff | 725 | region.mem_t = NORMAL; \ |
| bogdanm | 0:9b334a45a8ff | 726 | region.sec_t = NON_SECURE; \ |
| bogdanm | 0:9b334a45a8ff | 727 | region.xn_t = EXECUTE; \ |
| bogdanm | 0:9b334a45a8ff | 728 | region.priv_t = READ; \ |
| bogdanm | 0:9b334a45a8ff | 729 | region.user_t = READ; \ |
| bogdanm | 0:9b334a45a8ff | 730 | region.sh_t = NON_SHARED; \ |
| bogdanm | 0:9b334a45a8ff | 731 | __get_section_descriptor(&descriptor_l1, region); |
| bogdanm | 0:9b334a45a8ff | 732 | |
| bogdanm | 0:9b334a45a8ff | 733 | //Sect_Normal_RO. Sect_Normal_Cod, but not executable |
| bogdanm | 0:9b334a45a8ff | 734 | #define section_normal_ro(descriptor_l1, region) region.rg_t = SECTION; \ |
| bogdanm | 0:9b334a45a8ff | 735 | region.domain = 0x0; \ |
| bogdanm | 0:9b334a45a8ff | 736 | region.e_t = ECC_DISABLED; \ |
| bogdanm | 0:9b334a45a8ff | 737 | region.g_t = GLOBAL; \ |
| bogdanm | 0:9b334a45a8ff | 738 | region.inner_norm_t = WB_WA; \ |
| bogdanm | 0:9b334a45a8ff | 739 | region.outer_norm_t = WB_WA; \ |
| bogdanm | 0:9b334a45a8ff | 740 | region.mem_t = NORMAL; \ |
| bogdanm | 0:9b334a45a8ff | 741 | region.sec_t = NON_SECURE; \ |
| bogdanm | 0:9b334a45a8ff | 742 | region.xn_t = NON_EXECUTE; \ |
| bogdanm | 0:9b334a45a8ff | 743 | region.priv_t = READ; \ |
| bogdanm | 0:9b334a45a8ff | 744 | region.user_t = READ; \ |
| bogdanm | 0:9b334a45a8ff | 745 | region.sh_t = NON_SHARED; \ |
| bogdanm | 0:9b334a45a8ff | 746 | __get_section_descriptor(&descriptor_l1, region); |
| bogdanm | 0:9b334a45a8ff | 747 | |
| bogdanm | 0:9b334a45a8ff | 748 | //Sect_Normal_RW. Sect_Normal_Cod, but writeable and not executable |
| bogdanm | 0:9b334a45a8ff | 749 | #define section_normal_rw(descriptor_l1, region) region.rg_t = SECTION; \ |
| bogdanm | 0:9b334a45a8ff | 750 | region.domain = 0x0; \ |
| bogdanm | 0:9b334a45a8ff | 751 | region.e_t = ECC_DISABLED; \ |
| bogdanm | 0:9b334a45a8ff | 752 | region.g_t = GLOBAL; \ |
| bogdanm | 0:9b334a45a8ff | 753 | region.inner_norm_t = WB_WA; \ |
| bogdanm | 0:9b334a45a8ff | 754 | region.outer_norm_t = WB_WA; \ |
| bogdanm | 0:9b334a45a8ff | 755 | region.mem_t = NORMAL; \ |
| bogdanm | 0:9b334a45a8ff | 756 | region.sec_t = NON_SECURE; \ |
| mbed_official | 119:3921aeca8633 | 757 | region.xn_t = EXECUTE; \ |
| bogdanm | 0:9b334a45a8ff | 758 | region.priv_t = RW; \ |
| bogdanm | 0:9b334a45a8ff | 759 | region.user_t = RW; \ |
| bogdanm | 0:9b334a45a8ff | 760 | region.sh_t = NON_SHARED; \ |
| bogdanm | 0:9b334a45a8ff | 761 | __get_section_descriptor(&descriptor_l1, region); |
| mbed_official | 119:3921aeca8633 | 762 | |
| bogdanm | 0:9b334a45a8ff | 763 | //Sect_SO. Strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0 |
| bogdanm | 0:9b334a45a8ff | 764 | #define section_so(descriptor_l1, region) region.rg_t = SECTION; \ |
| bogdanm | 0:9b334a45a8ff | 765 | region.domain = 0x0; \ |
| bogdanm | 0:9b334a45a8ff | 766 | region.e_t = ECC_DISABLED; \ |
| bogdanm | 0:9b334a45a8ff | 767 | region.g_t = GLOBAL; \ |
| bogdanm | 0:9b334a45a8ff | 768 | region.inner_norm_t = NON_CACHEABLE; \ |
| bogdanm | 0:9b334a45a8ff | 769 | region.outer_norm_t = NON_CACHEABLE; \ |
| bogdanm | 0:9b334a45a8ff | 770 | region.mem_t = STRONGLY_ORDERED; \ |
| bogdanm | 0:9b334a45a8ff | 771 | region.sec_t = SECURE; \ |
| bogdanm | 0:9b334a45a8ff | 772 | region.xn_t = NON_EXECUTE; \ |
| bogdanm | 0:9b334a45a8ff | 773 | region.priv_t = RW; \ |
| bogdanm | 0:9b334a45a8ff | 774 | region.user_t = RW; \ |
| bogdanm | 0:9b334a45a8ff | 775 | region.sh_t = NON_SHARED; \ |
| bogdanm | 0:9b334a45a8ff | 776 | __get_section_descriptor(&descriptor_l1, region); |
| bogdanm | 0:9b334a45a8ff | 777 | |
| bogdanm | 0:9b334a45a8ff | 778 | //Sect_Device_RO. Device, non-shareable, non-executable, ro, domain 0, base addr 0 |
| bogdanm | 0:9b334a45a8ff | 779 | #define section_device_ro(descriptor_l1, region) region.rg_t = SECTION; \ |
| bogdanm | 0:9b334a45a8ff | 780 | region.domain = 0x0; \ |
| bogdanm | 0:9b334a45a8ff | 781 | region.e_t = ECC_DISABLED; \ |
| bogdanm | 0:9b334a45a8ff | 782 | region.g_t = GLOBAL; \ |
| bogdanm | 0:9b334a45a8ff | 783 | region.inner_norm_t = NON_CACHEABLE; \ |
| bogdanm | 0:9b334a45a8ff | 784 | region.outer_norm_t = NON_CACHEABLE; \ |
| bogdanm | 0:9b334a45a8ff | 785 | region.mem_t = STRONGLY_ORDERED; \ |
| bogdanm | 0:9b334a45a8ff | 786 | region.sec_t = SECURE; \ |
| bogdanm | 0:9b334a45a8ff | 787 | region.xn_t = NON_EXECUTE; \ |
| bogdanm | 0:9b334a45a8ff | 788 | region.priv_t = READ; \ |
| bogdanm | 0:9b334a45a8ff | 789 | region.user_t = READ; \ |
| bogdanm | 0:9b334a45a8ff | 790 | region.sh_t = NON_SHARED; \ |
| bogdanm | 0:9b334a45a8ff | 791 | __get_section_descriptor(&descriptor_l1, region); |
| mbed_official | 119:3921aeca8633 | 792 | |
| bogdanm | 0:9b334a45a8ff | 793 | //Sect_Device_RW. Sect_Device_RO, but writeable |
| bogdanm | 0:9b334a45a8ff | 794 | #define section_device_rw(descriptor_l1, region) region.rg_t = SECTION; \ |
| bogdanm | 0:9b334a45a8ff | 795 | region.domain = 0x0; \ |
| bogdanm | 0:9b334a45a8ff | 796 | region.e_t = ECC_DISABLED; \ |
| bogdanm | 0:9b334a45a8ff | 797 | region.g_t = GLOBAL; \ |
| bogdanm | 0:9b334a45a8ff | 798 | region.inner_norm_t = NON_CACHEABLE; \ |
| bogdanm | 0:9b334a45a8ff | 799 | region.outer_norm_t = NON_CACHEABLE; \ |
| bogdanm | 0:9b334a45a8ff | 800 | region.mem_t = STRONGLY_ORDERED; \ |
| bogdanm | 0:9b334a45a8ff | 801 | region.sec_t = SECURE; \ |
| bogdanm | 0:9b334a45a8ff | 802 | region.xn_t = NON_EXECUTE; \ |
| bogdanm | 0:9b334a45a8ff | 803 | region.priv_t = RW; \ |
| bogdanm | 0:9b334a45a8ff | 804 | region.user_t = RW; \ |
| bogdanm | 0:9b334a45a8ff | 805 | region.sh_t = NON_SHARED; \ |
| bogdanm | 0:9b334a45a8ff | 806 | __get_section_descriptor(&descriptor_l1, region); |
| bogdanm | 0:9b334a45a8ff | 807 | //Page_4k_Device_RW. Shared device, not executable, rw, domain 0 |
| bogdanm | 0:9b334a45a8ff | 808 | #define page4k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_4k; \ |
| bogdanm | 0:9b334a45a8ff | 809 | region.domain = 0x0; \ |
| bogdanm | 0:9b334a45a8ff | 810 | region.e_t = ECC_DISABLED; \ |
| bogdanm | 0:9b334a45a8ff | 811 | region.g_t = GLOBAL; \ |
| bogdanm | 0:9b334a45a8ff | 812 | region.inner_norm_t = NON_CACHEABLE; \ |
| bogdanm | 0:9b334a45a8ff | 813 | region.outer_norm_t = NON_CACHEABLE; \ |
| bogdanm | 0:9b334a45a8ff | 814 | region.mem_t = SHARED_DEVICE; \ |
| bogdanm | 0:9b334a45a8ff | 815 | region.sec_t = SECURE; \ |
| bogdanm | 0:9b334a45a8ff | 816 | region.xn_t = NON_EXECUTE; \ |
| bogdanm | 0:9b334a45a8ff | 817 | region.priv_t = RW; \ |
| bogdanm | 0:9b334a45a8ff | 818 | region.user_t = RW; \ |
| bogdanm | 0:9b334a45a8ff | 819 | region.sh_t = NON_SHARED; \ |
| bogdanm | 0:9b334a45a8ff | 820 | __get_page_descriptor(&descriptor_l1, &descriptor_l2, region); |
| bogdanm | 0:9b334a45a8ff | 821 | |
| bogdanm | 0:9b334a45a8ff | 822 | //Page_64k_Device_RW. Shared device, not executable, rw, domain 0 |
| bogdanm | 0:9b334a45a8ff | 823 | #define page64k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_64k; \ |
| bogdanm | 0:9b334a45a8ff | 824 | region.domain = 0x0; \ |
| bogdanm | 0:9b334a45a8ff | 825 | region.e_t = ECC_DISABLED; \ |
| bogdanm | 0:9b334a45a8ff | 826 | region.g_t = GLOBAL; \ |
| bogdanm | 0:9b334a45a8ff | 827 | region.inner_norm_t = NON_CACHEABLE; \ |
| bogdanm | 0:9b334a45a8ff | 828 | region.outer_norm_t = NON_CACHEABLE; \ |
| bogdanm | 0:9b334a45a8ff | 829 | region.mem_t = SHARED_DEVICE; \ |
| bogdanm | 0:9b334a45a8ff | 830 | region.sec_t = SECURE; \ |
| bogdanm | 0:9b334a45a8ff | 831 | region.xn_t = NON_EXECUTE; \ |
| bogdanm | 0:9b334a45a8ff | 832 | region.priv_t = RW; \ |
| bogdanm | 0:9b334a45a8ff | 833 | region.user_t = RW; \ |
| bogdanm | 0:9b334a45a8ff | 834 | region.sh_t = NON_SHARED; \ |
| bogdanm | 0:9b334a45a8ff | 835 | __get_page_descriptor(&descriptor_l1, &descriptor_l2, region); |
| mbed_official | 119:3921aeca8633 | 836 | |
| bogdanm | 0:9b334a45a8ff | 837 | |
| bogdanm | 0:9b334a45a8ff | 838 | /*@}*/ /* end of group Renesas_RZ_A1_MemoryMap */ |
| bogdanm | 0:9b334a45a8ff | 839 | |
| bogdanm | 0:9b334a45a8ff | 840 | /******************************************************************************/ |
| bogdanm | 0:9b334a45a8ff | 841 | /* Clock Settings */ |
| bogdanm | 0:9b334a45a8ff | 842 | /******************************************************************************/ |
| bogdanm | 0:9b334a45a8ff | 843 | /** @addtogroup Renesas_RZ_A1_H_Clocks Renesas_RZ_A1 Clock definitions |
| bogdanm | 0:9b334a45a8ff | 844 | @{ |
| bogdanm | 0:9b334a45a8ff | 845 | */ |
| bogdanm | 0:9b334a45a8ff | 846 | |
| bogdanm | 0:9b334a45a8ff | 847 | /* |
| bogdanm | 0:9b334a45a8ff | 848 | * Clock Mode 0 settings |
| bogdanm | 0:9b334a45a8ff | 849 | * SW1-4(MD_CLK):ON |
| bogdanm | 0:9b334a45a8ff | 850 | * SW1-5(MD_CLKS):ON |
| bogdanm | 0:9b334a45a8ff | 851 | * FRQCR=0x1035 |
| bogdanm | 0:9b334a45a8ff | 852 | * CLKEN2 = 0b - unstable |
| bogdanm | 0:9b334a45a8ff | 853 | * CLKEN[1:0]=01b - Output, Low, Low |
| bogdanm | 0:9b334a45a8ff | 854 | * IFC[1:0] =00b - CPU clock is 1/1 PLL clock |
| bogdanm | 0:9b334a45a8ff | 855 | * FRQCR2=0x0001 |
| bogdanm | 0:9b334a45a8ff | 856 | * GFC[1:0] =01b - Graphic clock is 2/3 bus clock |
| bogdanm | 0:9b334a45a8ff | 857 | */ |
| bogdanm | 0:9b334a45a8ff | 858 | #define CM0_RENESAS_RZ_A1_CLKIN ( 13333333u) |
| bogdanm | 0:9b334a45a8ff | 859 | #define CM0_RENESAS_RZ_A1_CLKO ( 66666666u) |
| bogdanm | 0:9b334a45a8ff | 860 | #define CM0_RENESAS_RZ_A1_I_CLK (400000000u) |
| bogdanm | 0:9b334a45a8ff | 861 | #define CM0_RENESAS_RZ_A1_G_CLK (266666666u) |
| bogdanm | 0:9b334a45a8ff | 862 | #define CM0_RENESAS_RZ_A1_B_CLK (133333333u) |
| bogdanm | 0:9b334a45a8ff | 863 | #define CM0_RENESAS_RZ_A1_P1_CLK ( 66666666u) |
| bogdanm | 0:9b334a45a8ff | 864 | #define CM0_RENESAS_RZ_A1_P0_CLK ( 33333333u) |
| bogdanm | 0:9b334a45a8ff | 865 | |
| bogdanm | 0:9b334a45a8ff | 866 | /* |
| bogdanm | 0:9b334a45a8ff | 867 | * Clock Mode 1 settings |
| bogdanm | 0:9b334a45a8ff | 868 | * SW1-4(MD_CLK):OFF |
| bogdanm | 0:9b334a45a8ff | 869 | * SW1-5(MD_CLKS):ON |
| bogdanm | 0:9b334a45a8ff | 870 | * FRQCR=0x1335 |
| bogdanm | 0:9b334a45a8ff | 871 | * CLKEN2 = 0b - unstable |
| bogdanm | 0:9b334a45a8ff | 872 | * CLKEN[1:0]=01b - Output, Low, Low |
| bogdanm | 0:9b334a45a8ff | 873 | * IFC[1:0] =11b - CPU clock is 1/3 PLL clock |
| bogdanm | 0:9b334a45a8ff | 874 | * FRQCR2=0x0003 |
| bogdanm | 0:9b334a45a8ff | 875 | * GFC[1:0] =11b - graphic clock is 1/3 bus clock |
| bogdanm | 0:9b334a45a8ff | 876 | */ |
| bogdanm | 0:9b334a45a8ff | 877 | #define CM1_RENESAS_RZ_A1_CLKIN ( 48000000u) |
| bogdanm | 0:9b334a45a8ff | 878 | #define CM1_RENESAS_RZ_A1_CLKO ( 64000000u) |
| bogdanm | 0:9b334a45a8ff | 879 | #define CM1_RENESAS_RZ_A1_I_CLK (128000000u) |
| bogdanm | 0:9b334a45a8ff | 880 | #define CM1_RENESAS_RZ_A1_G_CLK (128000000u) |
| bogdanm | 0:9b334a45a8ff | 881 | #define CM1_RENESAS_RZ_A1_B_CLK (128000000u) |
| bogdanm | 0:9b334a45a8ff | 882 | #define CM1_RENESAS_RZ_A1_P1_CLK ( 64000000u) |
| bogdanm | 0:9b334a45a8ff | 883 | #define CM1_RENESAS_RZ_A1_P0_CLK ( 32000000u) |
| bogdanm | 0:9b334a45a8ff | 884 | |
| bogdanm | 0:9b334a45a8ff | 885 | /*@}*/ /* end of group Renesas_RZ_A1_Clocks */ |
| bogdanm | 0:9b334a45a8ff | 886 | |
| bogdanm | 0:9b334a45a8ff | 887 | /******************************************************************************/ |
| bogdanm | 0:9b334a45a8ff | 888 | /* CPG Settings */ |
| bogdanm | 0:9b334a45a8ff | 889 | /******************************************************************************/ |
| bogdanm | 0:9b334a45a8ff | 890 | /** @addtogroup Renesas_RZ_A1_H_CPG Renesas_RZ_A1 CPG Bit definitions |
| bogdanm | 0:9b334a45a8ff | 891 | @{ |
| bogdanm | 0:9b334a45a8ff | 892 | */ |
| bogdanm | 0:9b334a45a8ff | 893 | |
| bogdanm | 0:9b334a45a8ff | 894 | #define CPG_FRQCR_SHIFT_CKOEN2 (14) |
| bogdanm | 0:9b334a45a8ff | 895 | #define CPG_FRQCR_BIT_CKOEN2 (0x1 << CPG_FRQCR_SHIFT_CKOEN2) |
| bogdanm | 0:9b334a45a8ff | 896 | #define CPG_FRQCR_SHIFT_CKOEN0 (12) |
| bogdanm | 0:9b334a45a8ff | 897 | #define CPG_FRQCR_BITS_CKOEN0 (0x3 << CPG_FRQCR_SHIFT_CKOEN0) |
| bogdanm | 0:9b334a45a8ff | 898 | #define CPG_FRQCR_SHIFT_IFC (8) |
| bogdanm | 0:9b334a45a8ff | 899 | #define CPG_FRQCR_BITS_IFC (0x3 << CPG_FRQCR_SHIFT_IFC) |
| bogdanm | 0:9b334a45a8ff | 900 | |
| bogdanm | 0:9b334a45a8ff | 901 | #define CPG_FRQCR2_SHIFT_GFC (0) |
| bogdanm | 0:9b334a45a8ff | 902 | #define CPG_FRQCR2_BITS_GFC (0x3 << CPG_FRQCR2_SHIFT_GFC) |
| bogdanm | 0:9b334a45a8ff | 903 | |
| bogdanm | 0:9b334a45a8ff | 904 | |
| bogdanm | 0:9b334a45a8ff | 905 | #define CPG_STBCR1_BIT_STBY (0x80u) |
| bogdanm | 0:9b334a45a8ff | 906 | #define CPG_STBCR1_BIT_DEEP (0x40u) |
| bogdanm | 0:9b334a45a8ff | 907 | #define CPG_STBCR2_BIT_HIZ (0x80u) |
| bogdanm | 0:9b334a45a8ff | 908 | #define CPG_STBCR2_BIT_MSTP20 (0x01u) /* CoreSight */ |
| bogdanm | 0:9b334a45a8ff | 909 | #define CPG_STBCR3_BIT_MSTP37 (0x80u) /* IEBus */ |
| bogdanm | 0:9b334a45a8ff | 910 | #define CPG_STBCR3_BIT_MSTP36 (0x40u) /* IrDA */ |
| bogdanm | 0:9b334a45a8ff | 911 | #define CPG_STBCR3_BIT_MSTP35 (0x20u) /* LIN0 */ |
| bogdanm | 0:9b334a45a8ff | 912 | #define CPG_STBCR3_BIT_MSTP34 (0x10u) /* LIN1 */ |
| bogdanm | 0:9b334a45a8ff | 913 | #define CPG_STBCR3_BIT_MSTP33 (0x08u) /* Multi-Function Timer */ |
| bogdanm | 0:9b334a45a8ff | 914 | #define CPG_STBCR3_BIT_MSTP32 (0x04u) /* CAN */ |
| bogdanm | 0:9b334a45a8ff | 915 | #define CPG_STBCR3_BIT_MSTP30 (0x01u) /* Motor Control PWM Timer */ |
| bogdanm | 0:9b334a45a8ff | 916 | #define CPG_STBCR4_BIT_MSTP47 (0x80u) /* SCIF0 */ |
| bogdanm | 0:9b334a45a8ff | 917 | #define CPG_STBCR4_BIT_MSTP46 (0x40u) /* SCIF1 */ |
| bogdanm | 0:9b334a45a8ff | 918 | #define CPG_STBCR4_BIT_MSTP45 (0x20u) /* SCIF2 */ |
| bogdanm | 0:9b334a45a8ff | 919 | #define CPG_STBCR4_BIT_MSTP44 (0x10u) /* SCIF3 */ |
| bogdanm | 0:9b334a45a8ff | 920 | #define CPG_STBCR4_BIT_MSTP43 (0x08u) /* SCIF4 */ |
| bogdanm | 0:9b334a45a8ff | 921 | #define CPG_STBCR4_BIT_MSTP42 (0x04u) /* SCIF5 */ |
| bogdanm | 0:9b334a45a8ff | 922 | #define CPG_STBCR4_BIT_MSTP41 (0x02u) /* SCIF6 */ |
| bogdanm | 0:9b334a45a8ff | 923 | #define CPG_STBCR4_BIT_MSTP40 (0x01u) /* SCIF7 */ |
| bogdanm | 0:9b334a45a8ff | 924 | #define CPG_STBCR5_BIT_MSTP57 (0x80u) /* SCI0 */ |
| bogdanm | 0:9b334a45a8ff | 925 | #define CPG_STBCR5_BIT_MSTP56 (0x40u) /* SCI1 */ |
| bogdanm | 0:9b334a45a8ff | 926 | #define CPG_STBCR5_BIT_MSTP55 (0x20u) /* Sound Generator0 */ |
| bogdanm | 0:9b334a45a8ff | 927 | #define CPG_STBCR5_BIT_MSTP54 (0x10u) /* Sound Generator1 */ |
| bogdanm | 0:9b334a45a8ff | 928 | #define CPG_STBCR5_BIT_MSTP53 (0x08u) /* Sound Generator2 */ |
| bogdanm | 0:9b334a45a8ff | 929 | #define CPG_STBCR5_BIT_MSTP52 (0x04u) /* Sound Generator3 */ |
| bogdanm | 0:9b334a45a8ff | 930 | #define CPG_STBCR5_BIT_MSTP51 (0x02u) /* OSTM0 */ |
| bogdanm | 0:9b334a45a8ff | 931 | #define CPG_STBCR5_BIT_MSTP50 (0x01u) /* OSTM1 */ |
| bogdanm | 0:9b334a45a8ff | 932 | #define CPG_STBCR6_BIT_MSTP67 (0x80u) /* General A/D Comvertor */ |
| bogdanm | 0:9b334a45a8ff | 933 | #define CPG_STBCR6_BIT_MSTP66 (0x40u) /* Capture Engine */ |
| bogdanm | 0:9b334a45a8ff | 934 | #define CPG_STBCR6_BIT_MSTP65 (0x20u) /* Display out comparison0 */ |
| bogdanm | 0:9b334a45a8ff | 935 | #define CPG_STBCR6_BIT_MSTP64 (0x10u) /* Display out comparison1 */ |
| bogdanm | 0:9b334a45a8ff | 936 | #define CPG_STBCR6_BIT_MSTP63 (0x08u) /* Dynamic Range Compalator0 */ |
| bogdanm | 0:9b334a45a8ff | 937 | #define CPG_STBCR6_BIT_MSTP62 (0x04u) /* Dynamic Range Compalator1 */ |
| bogdanm | 0:9b334a45a8ff | 938 | #define CPG_STBCR6_BIT_MSTP61 (0x02u) /* JPEG Decoder */ |
| bogdanm | 0:9b334a45a8ff | 939 | #define CPG_STBCR6_BIT_MSTP60 (0x01u) /* Realtime Clock */ |
| bogdanm | 0:9b334a45a8ff | 940 | #define CPG_STBCR7_BIT_MSTP77 (0x80u) /* Video Decoder0 */ |
| bogdanm | 0:9b334a45a8ff | 941 | #define CPG_STBCR7_BIT_MSTP76 (0x40u) /* Video Decoder1 */ |
| bogdanm | 0:9b334a45a8ff | 942 | #define CPG_STBCR7_BIT_MSTP74 (0x10u) /* Ether */ |
| bogdanm | 0:9b334a45a8ff | 943 | #define CPG_STBCR7_BIT_MSTP73 (0x04u) /* NAND Flash Memory Controller */ |
| bogdanm | 0:9b334a45a8ff | 944 | #define CPG_STBCR7_BIT_MSTP71 (0x02u) /* USB0 */ |
| bogdanm | 0:9b334a45a8ff | 945 | #define CPG_STBCR7_BIT_MSTP70 (0x01u) /* USB1 */ |
| bogdanm | 0:9b334a45a8ff | 946 | #define CPG_STBCR8_BIT_MSTP87 (0x80u) /* IMR-LS2_0 */ |
| bogdanm | 0:9b334a45a8ff | 947 | #define CPG_STBCR8_BIT_MSTP86 (0x40u) /* IMR-LS2_1 */ |
| bogdanm | 0:9b334a45a8ff | 948 | #define CPG_STBCR8_BIT_MSTP85 (0x20u) /* IMR-LSD */ |
| bogdanm | 0:9b334a45a8ff | 949 | #define CPG_STBCR8_BIT_MSTP84 (0x10u) /* MMC Host Interface */ |
| bogdanm | 0:9b334a45a8ff | 950 | #define CPG_STBCR8_BIT_MSTP83 (0x08u) /* MediaLB */ |
| bogdanm | 0:9b334a45a8ff | 951 | #define CPG_STBCR8_BIT_MSTP81 (0x02u) /* SCUX */ |
| bogdanm | 0:9b334a45a8ff | 952 | #define CPG_STBCR9_BIT_MSTP97 (0x80u) /* RIIC0 */ |
| bogdanm | 0:9b334a45a8ff | 953 | #define CPG_STBCR9_BIT_MSTP96 (0x40u) /* RIIC1 */ |
| bogdanm | 0:9b334a45a8ff | 954 | #define CPG_STBCR9_BIT_MSTP95 (0x20u) /* RIIC2 */ |
| bogdanm | 0:9b334a45a8ff | 955 | #define CPG_STBCR9_BIT_MSTP94 (0x10u) /* RIIC3 */ |
| bogdanm | 0:9b334a45a8ff | 956 | #define CPG_STBCR9_BIT_MSTP93 (0x08u) /* SPI Multi I/O Bus Controller0 */ |
| bogdanm | 0:9b334a45a8ff | 957 | #define CPG_STBCR9_BIT_MSTP92 (0x04u) /* SPI Multi I/O Bus Controller1 */ |
| bogdanm | 0:9b334a45a8ff | 958 | #define CPG_STBCR9_BIT_MSTP91 (0x02u) /* VDC5_0 */ |
| bogdanm | 0:9b334a45a8ff | 959 | #define CPG_STBCR9_BIT_MSTP90 (0x01u) /* VDC5_1 */ |
| bogdanm | 0:9b334a45a8ff | 960 | #define CPG_STBCR10_BIT_MSTP107 (0x80u) /* RSPI0 */ |
| bogdanm | 0:9b334a45a8ff | 961 | #define CPG_STBCR10_BIT_MSTP106 (0x40u) /* RSPI1 */ |
| bogdanm | 0:9b334a45a8ff | 962 | #define CPG_STBCR10_BIT_MSTP105 (0x20u) /* RSPI2 */ |
| bogdanm | 0:9b334a45a8ff | 963 | #define CPG_STBCR10_BIT_MSTP104 (0x10u) /* RSPI3 */ |
| bogdanm | 0:9b334a45a8ff | 964 | #define CPG_STBCR10_BIT_MSTP103 (0x08u) /* RSPI4 */ |
| bogdanm | 0:9b334a45a8ff | 965 | #define CPG_STBCR10_BIT_MSTP102 (0x04u) /* ROMDEC */ |
| bogdanm | 0:9b334a45a8ff | 966 | #define CPG_STBCR10_BIT_MSTP101 (0x02u) /* SPIDF */ |
| bogdanm | 0:9b334a45a8ff | 967 | #define CPG_STBCR10_BIT_MSTP100 (0x01u) /* OpenVG */ |
| bogdanm | 0:9b334a45a8ff | 968 | #define CPG_STBCR11_BIT_MSTP115 (0x20u) /* SSIF0 */ |
| bogdanm | 0:9b334a45a8ff | 969 | #define CPG_STBCR11_BIT_MSTP114 (0x10u) /* SSIF1 */ |
| bogdanm | 0:9b334a45a8ff | 970 | #define CPG_STBCR11_BIT_MSTP113 (0x08u) /* SSIF2 */ |
| bogdanm | 0:9b334a45a8ff | 971 | #define CPG_STBCR11_BIT_MSTP112 (0x04u) /* SSIF3 */ |
| bogdanm | 0:9b334a45a8ff | 972 | #define CPG_STBCR11_BIT_MSTP111 (0x02u) /* SSIF4 */ |
| bogdanm | 0:9b334a45a8ff | 973 | #define CPG_STBCR11_BIT_MSTP110 (0x01u) /* SSIF5 */ |
| bogdanm | 0:9b334a45a8ff | 974 | #define CPG_STBCR12_BIT_MSTP123 (0x08u) /* SD Host Interface00 */ |
| bogdanm | 0:9b334a45a8ff | 975 | #define CPG_STBCR12_BIT_MSTP122 (0x04u) /* SD Host Interface01 */ |
| bogdanm | 0:9b334a45a8ff | 976 | #define CPG_STBCR12_BIT_MSTP121 (0x02u) /* SD Host Interface10 */ |
| bogdanm | 0:9b334a45a8ff | 977 | #define CPG_STBCR12_BIT_MSTP120 (0x01u) /* SD Host Interface11 */ |
| bogdanm | 0:9b334a45a8ff | 978 | #define CPG_CSTBCR1_BIT_CMSTP11 (0x02u) /* PFV */ |
| bogdanm | 0:9b334a45a8ff | 979 | #define CPG_SWRSTCR1_BIT_AXTALE (0x80u) /* AUDIO_X1 */ |
| bogdanm | 0:9b334a45a8ff | 980 | #define CPG_SWRSTCR1_BIT_SRST16 (0x40u) /* SSIF0 */ |
| bogdanm | 0:9b334a45a8ff | 981 | #define CPG_SWRSTCR1_BIT_SRST15 (0x20u) /* SSIF1 */ |
| bogdanm | 0:9b334a45a8ff | 982 | #define CPG_SWRSTCR1_BIT_SRST14 (0x10u) /* SSIF2 */ |
| bogdanm | 0:9b334a45a8ff | 983 | #define CPG_SWRSTCR1_BIT_SRST13 (0x08u) /* SSIF3 */ |
| bogdanm | 0:9b334a45a8ff | 984 | #define CPG_SWRSTCR1_BIT_SRST12 (0x04u) /* SSIF4 */ |
| bogdanm | 0:9b334a45a8ff | 985 | #define CPG_SWRSTCR1_BIT_SRST11 (0x02u) /* SSIF5 */ |
| bogdanm | 0:9b334a45a8ff | 986 | #define CPG_SWRSTCR2_BIT_SRST27 (0x80u) /* Display out comparison0 */ |
| bogdanm | 0:9b334a45a8ff | 987 | #define CPG_SWRSTCR2_BIT_SRST26 (0x40u) /* Display out comparison1 */ |
| bogdanm | 0:9b334a45a8ff | 988 | #define CPG_SWRSTCR2_BIT_SRST25 (0x20u) /* Dynamic Range Compalator0 */ |
| bogdanm | 0:9b334a45a8ff | 989 | #define CPG_SWRSTCR2_BIT_SRST24 (0x10u) /* Dynamic Range Compalator1 */ |
| bogdanm | 0:9b334a45a8ff | 990 | #define CPG_SWRSTCR2_BIT_SRST23 (0x08u) /* VDC5_0 */ |
| bogdanm | 0:9b334a45a8ff | 991 | #define CPG_SWRSTCR2_BIT_SRST22 (0x04u) /* VDC5_1 */ |
| bogdanm | 0:9b334a45a8ff | 992 | #define CPG_SWRSTCR2_BIT_SRST21 (0x02u) /* JPEG Decoder */ |
| bogdanm | 0:9b334a45a8ff | 993 | #define CPG_SWRSTCR3_BIT_SRST36 (0x40u) /* DMA */ |
| bogdanm | 0:9b334a45a8ff | 994 | #define CPG_SWRSTCR3_BIT_SRST35 (0x20u) /* IMR-LS2_0 */ |
| bogdanm | 0:9b334a45a8ff | 995 | #define CPG_SWRSTCR3_BIT_SRST34 (0x10u) /* IMR-LS2_1 */ |
| bogdanm | 0:9b334a45a8ff | 996 | #define CPG_SWRSTCR3_BIT_SRST33 (0x08u) /* IMR-LSD? */ |
| bogdanm | 0:9b334a45a8ff | 997 | #define CPG_SWRSTCR3_BIT_SRST32 (0x04u) /* OpenVG */ |
| bogdanm | 0:9b334a45a8ff | 998 | #define CPG_SWRSTCR3_BIT_SRST31 (0x02u) /* Capture Engine */ |
| bogdanm | 0:9b334a45a8ff | 999 | #define CPG_SWRSTCR4_BIT_SRST41 (0x02u) /* Video Decoder0 */ |
| bogdanm | 0:9b334a45a8ff | 1000 | #define CPG_SWRSTCR4_BIT_SRST40 (0x01u) /* Video Decoder1 */ |
| bogdanm | 0:9b334a45a8ff | 1001 | #define CPG_SYSCR1_BIT_VRAME4 (0x10u) /* VRAM E Page4 */ |
| bogdanm | 0:9b334a45a8ff | 1002 | #define CPG_SYSCR1_BIT_VRAME3 (0x08u) /* VRAM E Page3 */ |
| bogdanm | 0:9b334a45a8ff | 1003 | #define CPG_SYSCR1_BIT_VRAME2 (0x04u) /* VRAM E Page2 */ |
| bogdanm | 0:9b334a45a8ff | 1004 | #define CPG_SYSCR1_BIT_VRAME1 (0x02u) /* VRAM E Page1 */ |
| bogdanm | 0:9b334a45a8ff | 1005 | #define CPG_SYSCR1_BIT_VRAME0 (0x01u) /* VRAM E Page0 */ |
| bogdanm | 0:9b334a45a8ff | 1006 | #define CPG_SYSCR2_BIT_VRAMWE4 (0x10u) /* VRAM WE Page4 */ |
| bogdanm | 0:9b334a45a8ff | 1007 | #define CPG_SYSCR2_BIT_VRAMWE3 (0x08u) /* VRAM WE Page3 */ |
| bogdanm | 0:9b334a45a8ff | 1008 | #define CPG_SYSCR2_BIT_VRAMWE2 (0x04u) /* VRAM WE Page2 */ |
| bogdanm | 0:9b334a45a8ff | 1009 | #define CPG_SYSCR2_BIT_VRAMWE1 (0x02u) /* VRAM WE Page1 */ |
| bogdanm | 0:9b334a45a8ff | 1010 | #define CPG_SYSCR2_BIT_VRAMWE0 (0x01u) /* VRAM WE Page0 */ |
| bogdanm | 0:9b334a45a8ff | 1011 | #define CPG_SYSCR3_BIT_RRAMWE3 (0x08u) /* RRAM WE Page3 */ |
| bogdanm | 0:9b334a45a8ff | 1012 | #define CPG_SYSCR3_BIT_RRAMWE2 (0x04u) /* RRAM WE Page2 */ |
| bogdanm | 0:9b334a45a8ff | 1013 | #define CPG_SYSCR3_BIT_RRAMWE1 (0x02u) /* RRAM WE Page1 */ |
| bogdanm | 0:9b334a45a8ff | 1014 | #define CPG_SYSCR3_BIT_RRAMWE0 (0x01u) /* RRAM WE Page0 */ |
| bogdanm | 0:9b334a45a8ff | 1015 | |
| bogdanm | 0:9b334a45a8ff | 1016 | /*@}*/ /* end of group Renesas_RZ_A1_CPG */ |
| bogdanm | 0:9b334a45a8ff | 1017 | |
| bogdanm | 0:9b334a45a8ff | 1018 | /******************************************************************************/ |
| bogdanm | 0:9b334a45a8ff | 1019 | /* GPIO Settings */ |
| bogdanm | 0:9b334a45a8ff | 1020 | /******************************************************************************/ |
| bogdanm | 0:9b334a45a8ff | 1021 | /** @addtogroup Renesas_RZ_A1_H_GPIO Renesas_RZ_A1 GPIO Bit definitions |
| bogdanm | 0:9b334a45a8ff | 1022 | @{ |
| bogdanm | 0:9b334a45a8ff | 1023 | */ |
| bogdanm | 0:9b334a45a8ff | 1024 | |
| bogdanm | 0:9b334a45a8ff | 1025 | #define GPIO_BIT_N0 (1u << 0) |
| bogdanm | 0:9b334a45a8ff | 1026 | #define GPIO_BIT_N1 (1u << 1) |
| bogdanm | 0:9b334a45a8ff | 1027 | #define GPIO_BIT_N2 (1u << 2) |
| bogdanm | 0:9b334a45a8ff | 1028 | #define GPIO_BIT_N3 (1u << 3) |
| bogdanm | 0:9b334a45a8ff | 1029 | #define GPIO_BIT_N4 (1u << 4) |
| bogdanm | 0:9b334a45a8ff | 1030 | #define GPIO_BIT_N5 (1u << 5) |
| bogdanm | 0:9b334a45a8ff | 1031 | #define GPIO_BIT_N6 (1u << 6) |
| bogdanm | 0:9b334a45a8ff | 1032 | #define GPIO_BIT_N7 (1u << 7) |
| bogdanm | 0:9b334a45a8ff | 1033 | #define GPIO_BIT_N8 (1u << 8) |
| bogdanm | 0:9b334a45a8ff | 1034 | #define GPIO_BIT_N9 (1u << 9) |
| bogdanm | 0:9b334a45a8ff | 1035 | #define GPIO_BIT_N10 (1u << 10) |
| bogdanm | 0:9b334a45a8ff | 1036 | #define GPIO_BIT_N11 (1u << 11) |
| bogdanm | 0:9b334a45a8ff | 1037 | #define GPIO_BIT_N12 (1u << 12) |
| bogdanm | 0:9b334a45a8ff | 1038 | #define GPIO_BIT_N13 (1u << 13) |
| bogdanm | 0:9b334a45a8ff | 1039 | #define GPIO_BIT_N14 (1u << 14) |
| bogdanm | 0:9b334a45a8ff | 1040 | #define GPIO_BIT_N15 (1u << 15) |
| bogdanm | 0:9b334a45a8ff | 1041 | |
| bogdanm | 0:9b334a45a8ff | 1042 | |
| bogdanm | 0:9b334a45a8ff | 1043 | #define MD_BOOT10_MASK (0x3) |
| bogdanm | 0:9b334a45a8ff | 1044 | |
| bogdanm | 0:9b334a45a8ff | 1045 | #define MD_BOOT10_BM0 (0x0) |
| bogdanm | 0:9b334a45a8ff | 1046 | #define MD_BOOT10_BM1 (0x2) |
| bogdanm | 0:9b334a45a8ff | 1047 | #define MD_BOOT10_BM3 (0x1) |
| bogdanm | 0:9b334a45a8ff | 1048 | #define MD_BOOT10_BM4_5 (0x3) |
| bogdanm | 0:9b334a45a8ff | 1049 | |
| bogdanm | 0:9b334a45a8ff | 1050 | #define MD_CLK (1u << 2) |
| bogdanm | 0:9b334a45a8ff | 1051 | #define MD_CLKS (1u << 3) |
| bogdanm | 0:9b334a45a8ff | 1052 | |
| bogdanm | 0:9b334a45a8ff | 1053 | /*@}*/ /* end of group Renesas_RZ_A1_GPIO */ |
| bogdanm | 0:9b334a45a8ff | 1054 | |
| bogdanm | 0:9b334a45a8ff | 1055 | #ifdef __cplusplus |
| bogdanm | 0:9b334a45a8ff | 1056 | } |
| bogdanm | 0:9b334a45a8ff | 1057 | #endif |
| bogdanm | 0:9b334a45a8ff | 1058 | |
| bogdanm | 0:9b334a45a8ff | 1059 | #endif // __MBRZA1H_H__ |