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core_cm0.h
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00001 /**************************************************************************//** 00002 * @file core_cm0.h 00003 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File 00004 * @version V4.10 00005 * @date 18. March 2015 00006 * 00007 * @note 00008 * 00009 ******************************************************************************/ 00010 /* Copyright (c) 2009 - 2015 ARM LIMITED 00011 00012 All rights reserved. 00013 Redistribution and use in source and binary forms, with or without 00014 modification, are permitted provided that the following conditions are met: 00015 - Redistributions of source code must retain the above copyright 00016 notice, this list of conditions and the following disclaimer. 00017 - Redistributions in binary form must reproduce the above copyright 00018 notice, this list of conditions and the following disclaimer in the 00019 documentation and/or other materials provided with the distribution. 00020 - Neither the name of ARM nor the names of its contributors may be used 00021 to endorse or promote products derived from this software without 00022 specific prior written permission. 00023 * 00024 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00025 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00026 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 00027 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE 00028 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 00029 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 00030 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 00031 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 00032 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 00033 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 00034 POSSIBILITY OF SUCH DAMAGE. 00035 ---------------------------------------------------------------------------*/ 00036 00037 00038 #if defined ( __ICCARM__ ) 00039 #pragma system_include /* treat file as system include file for MISRA check */ 00040 #endif 00041 00042 #ifndef __CORE_CM0_H_GENERIC 00043 #define __CORE_CM0_H_GENERIC 00044 00045 #ifdef __cplusplus 00046 extern "C" { 00047 #endif 00048 00049 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 00050 CMSIS violates the following MISRA-C:2004 rules: 00051 00052 \li Required Rule 8.5, object/function definition in header file.<br> 00053 Function definitions in header files are used to allow 'inlining'. 00054 00055 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> 00056 Unions are used for effective representation of core registers. 00057 00058 \li Advisory Rule 19.7, Function-like macro defined.<br> 00059 Function-like macros are used to allow more efficient code. 00060 */ 00061 00062 00063 /******************************************************************************* 00064 * CMSIS definitions 00065 ******************************************************************************/ 00066 /** \ingroup Cortex_M0 00067 @{ 00068 */ 00069 00070 /* CMSIS CM0 definitions */ 00071 #define __CM0_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ 00072 #define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ 00073 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \ 00074 __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ 00075 00076 #define __CORTEX_M (0x00) /*!< Cortex-M Core */ 00077 00078 00079 #if defined ( __CC_ARM ) 00080 #define __ASM __asm /*!< asm keyword for ARM Compiler */ 00081 #define __INLINE __inline /*!< inline keyword for ARM Compiler */ 00082 #define __STATIC_INLINE static __inline 00083 00084 #elif defined ( __GNUC__ ) 00085 #define __ASM __asm /*!< asm keyword for GNU Compiler */ 00086 #define __INLINE inline /*!< inline keyword for GNU Compiler */ 00087 #define __STATIC_INLINE static inline 00088 00089 #elif defined ( __ICCARM__ ) 00090 #define __ASM __asm /*!< asm keyword for IAR Compiler */ 00091 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ 00092 #define __STATIC_INLINE static inline 00093 00094 #elif defined ( __TMS470__ ) 00095 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ 00096 #define __STATIC_INLINE static inline 00097 00098 #elif defined ( __TASKING__ ) 00099 #define __ASM __asm /*!< asm keyword for TASKING Compiler */ 00100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */ 00101 #define __STATIC_INLINE static inline 00102 00103 #elif defined ( __CSMC__ ) 00104 #define __packed 00105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ 00106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ 00107 #define __STATIC_INLINE static inline 00108 00109 #endif 00110 00111 /** __FPU_USED indicates whether an FPU is used or not. 00112 This core does not support an FPU at all 00113 */ 00114 #define __FPU_USED 0 00115 00116 #if defined ( __CC_ARM ) 00117 #if defined __TARGET_FPU_VFP 00118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00119 #endif 00120 00121 #elif defined ( __GNUC__ ) 00122 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 00123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00124 #endif 00125 00126 #elif defined ( __ICCARM__ ) 00127 #if defined __ARMVFP__ 00128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00129 #endif 00130 00131 #elif defined ( __TMS470__ ) 00132 #if defined __TI__VFP_SUPPORT____ 00133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00134 #endif 00135 00136 #elif defined ( __TASKING__ ) 00137 #if defined __FPU_VFP__ 00138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00139 #endif 00140 00141 #elif defined ( __CSMC__ ) /* Cosmic */ 00142 #if ( __CSMC__ & 0x400) // FPU present for parser 00143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00144 #endif 00145 #endif 00146 00147 #include <stdint.h> /* standard types definitions */ 00148 #include <core_cmInstr.h> /* Core Instruction Access */ 00149 #include <core_cmFunc.h> /* Core Function Access */ 00150 00151 #ifdef __cplusplus 00152 } 00153 #endif 00154 00155 #endif /* __CORE_CM0_H_GENERIC */ 00156 00157 #ifndef __CMSIS_GENERIC 00158 00159 #ifndef __CORE_CM0_H_DEPENDANT 00160 #define __CORE_CM0_H_DEPENDANT 00161 00162 #ifdef __cplusplus 00163 extern "C" { 00164 #endif 00165 00166 /* check device defines and use defaults */ 00167 #if defined __CHECK_DEVICE_DEFINES 00168 #ifndef __CM0_REV 00169 #define __CM0_REV 0x0000 00170 #warning "__CM0_REV not defined in device header file; using default!" 00171 #endif 00172 00173 #ifndef __NVIC_PRIO_BITS 00174 #define __NVIC_PRIO_BITS 2 00175 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 00176 #endif 00177 00178 #ifndef __Vendor_SysTickConfig 00179 #define __Vendor_SysTickConfig 0 00180 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 00181 #endif 00182 #endif 00183 00184 /* IO definitions (access restrictions to peripheral registers) */ 00185 /** 00186 \defgroup CMSIS_glob_defs CMSIS Global Defines 00187 00188 <strong>IO Type Qualifiers</strong> are used 00189 \li to specify the access to peripheral variables. 00190 \li for automatic generation of peripheral register debug information. 00191 */ 00192 #ifdef __cplusplus 00193 #define __I volatile /*!< Defines 'read only' permissions */ 00194 #else 00195 #define __I volatile const /*!< Defines 'read only' permissions */ 00196 #endif 00197 #define __O volatile /*!< Defines 'write only' permissions */ 00198 #define __IO volatile /*!< Defines 'read / write' permissions */ 00199 00200 #ifdef __cplusplus 00201 #define __IM volatile /*!< Defines 'read only' permissions */ 00202 #else 00203 #define __IM volatile const /*!< Defines 'read only' permissions */ 00204 #endif 00205 #define __OM volatile /*!< Defines 'write only' permissions */ 00206 #define __IOM volatile /*!< Defines 'read / write' permissions */ 00207 00208 /*@} end of group Cortex_M0 */ 00209 00210 00211 00212 /******************************************************************************* 00213 * Register Abstraction 00214 Core Register contain: 00215 - Core Register 00216 - Core NVIC Register 00217 - Core SCB Register 00218 - Core SysTick Register 00219 ******************************************************************************/ 00220 /** \defgroup CMSIS_core_register Defines and Type Definitions 00221 \brief Type definitions and defines for Cortex-M processor based devices. 00222 */ 00223 00224 /** \ingroup CMSIS_core_register 00225 \defgroup CMSIS_CORE Status and Control Registers 00226 \brief Core Register type definitions. 00227 @{ 00228 */ 00229 00230 /** \brief Union type to access the Application Program Status Register (APSR). 00231 */ 00232 typedef union 00233 { 00234 struct 00235 { 00236 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ 00237 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00238 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00239 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00240 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00241 } b; /*!< Structure used for bit access */ 00242 uint32_t w; /*!< Type used for word access */ 00243 } APSR_Type; 00244 00245 /* APSR Register Definitions */ 00246 #define APSR_N_Pos 31 /*!< APSR: N Position */ 00247 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ 00248 00249 #define APSR_Z_Pos 30 /*!< APSR: Z Position */ 00250 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ 00251 00252 #define APSR_C_Pos 29 /*!< APSR: C Position */ 00253 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ 00254 00255 #define APSR_V_Pos 28 /*!< APSR: V Position */ 00256 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ 00257 00258 00259 /** \brief Union type to access the Interrupt Program Status Register (IPSR). 00260 */ 00261 typedef union 00262 { 00263 struct 00264 { 00265 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00266 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ 00267 } b; /*!< Structure used for bit access */ 00268 uint32_t w; /*!< Type used for word access */ 00269 } IPSR_Type; 00270 00271 /* IPSR Register Definitions */ 00272 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */ 00273 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ 00274 00275 00276 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 00277 */ 00278 typedef union 00279 { 00280 struct 00281 { 00282 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00283 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ 00284 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ 00285 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ 00286 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00287 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00288 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00289 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00290 } b; /*!< Structure used for bit access */ 00291 uint32_t w; /*!< Type used for word access */ 00292 } xPSR_Type; 00293 00294 /* xPSR Register Definitions */ 00295 #define xPSR_N_Pos 31 /*!< xPSR: N Position */ 00296 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ 00297 00298 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */ 00299 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ 00300 00301 #define xPSR_C_Pos 29 /*!< xPSR: C Position */ 00302 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ 00303 00304 #define xPSR_V_Pos 28 /*!< xPSR: V Position */ 00305 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ 00306 00307 #define xPSR_T_Pos 24 /*!< xPSR: T Position */ 00308 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ 00309 00310 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */ 00311 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ 00312 00313 00314 /** \brief Union type to access the Control Registers (CONTROL). 00315 */ 00316 typedef union 00317 { 00318 struct 00319 { 00320 uint32_t _reserved0:1; /*!< bit: 0 Reserved */ 00321 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ 00322 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ 00323 } b; /*!< Structure used for bit access */ 00324 uint32_t w; /*!< Type used for word access */ 00325 } CONTROL_Type; 00326 00327 /* CONTROL Register Definitions */ 00328 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */ 00329 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ 00330 00331 /*@} end of group CMSIS_CORE */ 00332 00333 00334 /** \ingroup CMSIS_core_register 00335 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 00336 \brief Type definitions for the NVIC Registers 00337 @{ 00338 */ 00339 00340 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 00341 */ 00342 typedef struct 00343 { 00344 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 00345 uint32_t RESERVED0[31]; 00346 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ 00347 uint32_t RSERVED1[31]; 00348 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ 00349 uint32_t RESERVED2[31]; 00350 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ 00351 uint32_t RESERVED3[31]; 00352 uint32_t RESERVED4[64]; 00353 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ 00354 } NVIC_Type; 00355 00356 /*@} end of group CMSIS_NVIC */ 00357 00358 00359 /** \ingroup CMSIS_core_register 00360 \defgroup CMSIS_SCB System Control Block (SCB) 00361 \brief Type definitions for the System Control Block Registers 00362 @{ 00363 */ 00364 00365 /** \brief Structure type to access the System Control Block (SCB). 00366 */ 00367 typedef struct 00368 { 00369 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 00370 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ 00371 uint32_t RESERVED0; 00372 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ 00373 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ 00374 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ 00375 uint32_t RESERVED1; 00376 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ 00377 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ 00378 } SCB_Type; 00379 00380 /* SCB CPUID Register Definitions */ 00381 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ 00382 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ 00383 00384 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ 00385 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ 00386 00387 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ 00388 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ 00389 00390 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ 00391 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ 00392 00393 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ 00394 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ 00395 00396 /* SCB Interrupt Control State Register Definitions */ 00397 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ 00398 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ 00399 00400 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ 00401 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ 00402 00403 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ 00404 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ 00405 00406 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ 00407 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ 00408 00409 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ 00410 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ 00411 00412 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ 00413 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ 00414 00415 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ 00416 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ 00417 00418 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ 00419 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ 00420 00421 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ 00422 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ 00423 00424 /* SCB Application Interrupt and Reset Control Register Definitions */ 00425 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ 00426 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ 00427 00428 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ 00429 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ 00430 00431 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ 00432 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ 00433 00434 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ 00435 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ 00436 00437 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ 00438 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ 00439 00440 /* SCB System Control Register Definitions */ 00441 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ 00442 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ 00443 00444 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ 00445 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ 00446 00447 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ 00448 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ 00449 00450 /* SCB Configuration Control Register Definitions */ 00451 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ 00452 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ 00453 00454 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ 00455 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ 00456 00457 /* SCB System Handler Control and State Register Definitions */ 00458 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ 00459 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ 00460 00461 /*@} end of group CMSIS_SCB */ 00462 00463 00464 /** \ingroup CMSIS_core_register 00465 \defgroup CMSIS_SysTick System Tick Timer (SysTick) 00466 \brief Type definitions for the System Timer Registers. 00467 @{ 00468 */ 00469 00470 /** \brief Structure type to access the System Timer (SysTick). 00471 */ 00472 typedef struct 00473 { 00474 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ 00475 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 00476 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ 00477 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 00478 } SysTick_Type; 00479 00480 /* SysTick Control / Status Register Definitions */ 00481 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ 00482 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ 00483 00484 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ 00485 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ 00486 00487 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ 00488 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ 00489 00490 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ 00491 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ 00492 00493 /* SysTick Reload Register Definitions */ 00494 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ 00495 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ 00496 00497 /* SysTick Current Register Definitions */ 00498 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ 00499 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ 00500 00501 /* SysTick Calibration Register Definitions */ 00502 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ 00503 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ 00504 00505 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ 00506 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ 00507 00508 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ 00509 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ 00510 00511 /*@} end of group CMSIS_SysTick */ 00512 00513 00514 /** \ingroup CMSIS_core_register 00515 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 00516 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) 00517 are only accessible over DAP and not via processor. Therefore 00518 they are not covered by the Cortex-M0 header file. 00519 @{ 00520 */ 00521 /*@} end of group CMSIS_CoreDebug */ 00522 00523 00524 /** \ingroup CMSIS_core_register 00525 \defgroup CMSIS_core_base Core Definitions 00526 \brief Definitions for base addresses, unions, and structures. 00527 @{ 00528 */ 00529 00530 /* Memory mapping of Cortex-M0 Hardware */ 00531 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ 00532 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 00533 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 00534 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ 00535 00536 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ 00537 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ 00538 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ 00539 00540 00541 /*@} */ 00542 00543 00544 00545 /******************************************************************************* 00546 * Hardware Abstraction Layer 00547 Core Function Interface contains: 00548 - Core NVIC Functions 00549 - Core SysTick Functions 00550 - Core Register Access Functions 00551 ******************************************************************************/ 00552 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 00553 */ 00554 00555 00556 00557 /* ########################## NVIC functions #################################### */ 00558 /** \ingroup CMSIS_Core_FunctionInterface 00559 \defgroup CMSIS_Core_NVICFunctions NVIC Functions 00560 \brief Functions that manage interrupts and exceptions via the NVIC. 00561 @{ 00562 */ 00563 00564 /* Interrupt Priorities are WORD accessible only under ARMv6M */ 00565 /* The following MACROS handle generation of the register offset and byte masks */ 00566 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) 00567 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) 00568 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) 00569 00570 00571 /** \brief Enable External Interrupt 00572 00573 The function enables a device-specific interrupt in the NVIC interrupt controller. 00574 00575 \param [in] IRQn External interrupt number. Value cannot be negative. 00576 */ 00577 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) 00578 { 00579 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); 00580 } 00581 00582 00583 /** \brief Disable External Interrupt 00584 00585 The function disables a device-specific interrupt in the NVIC interrupt controller. 00586 00587 \param [in] IRQn External interrupt number. Value cannot be negative. 00588 */ 00589 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) 00590 { 00591 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); 00592 __DSB(); 00593 __ISB(); 00594 } 00595 00596 00597 /** \brief Get Pending Interrupt 00598 00599 The function reads the pending register in the NVIC and returns the pending bit 00600 for the specified interrupt. 00601 00602 \param [in] IRQn Interrupt number. 00603 00604 \return 0 Interrupt status is not pending. 00605 \return 1 Interrupt status is pending. 00606 */ 00607 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) 00608 { 00609 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 00610 } 00611 00612 00613 /** \brief Set Pending Interrupt 00614 00615 The function sets the pending bit of an external interrupt. 00616 00617 \param [in] IRQn Interrupt number. Value cannot be negative. 00618 */ 00619 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) 00620 { 00621 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); 00622 } 00623 00624 00625 /** \brief Clear Pending Interrupt 00626 00627 The function clears the pending bit of an external interrupt. 00628 00629 \param [in] IRQn External interrupt number. Value cannot be negative. 00630 */ 00631 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) 00632 { 00633 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); 00634 } 00635 00636 00637 /** \brief Set Interrupt Priority 00638 00639 The function sets the priority of an interrupt. 00640 00641 \note The priority cannot be set for every core interrupt. 00642 00643 \param [in] IRQn Interrupt number. 00644 \param [in] priority Priority to set. 00645 */ 00646 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 00647 { 00648 if((int32_t)(IRQn) < 0) { 00649 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 00650 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 00651 } 00652 else { 00653 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 00654 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 00655 } 00656 } 00657 00658 00659 /** \brief Get Interrupt Priority 00660 00661 The function reads the priority of an interrupt. The interrupt 00662 number can be positive to specify an external (device specific) 00663 interrupt, or negative to specify an internal (core) interrupt. 00664 00665 00666 \param [in] IRQn Interrupt number. 00667 \return Interrupt Priority. Value is aligned automatically to the implemented 00668 priority bits of the microcontroller. 00669 */ 00670 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) 00671 { 00672 00673 if((int32_t)(IRQn) < 0) { 00674 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS))); 00675 } 00676 else { 00677 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS))); 00678 } 00679 } 00680 00681 00682 /** \brief System Reset 00683 00684 The function initiates a system reset request to reset the MCU. 00685 */ 00686 __STATIC_INLINE void NVIC_SystemReset(void) 00687 { 00688 __DSB(); /* Ensure all outstanding memory accesses included 00689 buffered write are completed before reset */ 00690 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 00691 SCB_AIRCR_SYSRESETREQ_Msk); 00692 __DSB(); /* Ensure completion of memory access */ 00693 while(1) { __NOP(); } /* wait until reset */ 00694 } 00695 00696 /*@} end of CMSIS_Core_NVICFunctions */ 00697 00698 00699 00700 /* ################################## SysTick function ############################################ */ 00701 /** \ingroup CMSIS_Core_FunctionInterface 00702 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions 00703 \brief Functions that configure the System. 00704 @{ 00705 */ 00706 00707 #if (__Vendor_SysTickConfig == 0) 00708 00709 /** \brief System Tick Configuration 00710 00711 The function initializes the System Timer and its interrupt, and starts the System Tick Timer. 00712 Counter is in free running mode to generate periodic interrupts. 00713 00714 \param [in] ticks Number of ticks between two interrupts. 00715 00716 \return 0 Function succeeded. 00717 \return 1 Function failed. 00718 00719 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 00720 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> 00721 must contain a vendor-specific implementation of this function. 00722 00723 */ 00724 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) 00725 { 00726 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */ 00727 00728 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 00729 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 00730 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 00731 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 00732 SysTick_CTRL_TICKINT_Msk | 00733 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 00734 return (0UL); /* Function successful */ 00735 } 00736 00737 #endif 00738 00739 /*@} end of CMSIS_Core_SysTickFunctions */ 00740 00741 00742 00743 00744 #ifdef __cplusplus 00745 } 00746 #endif 00747 00748 #endif /* __CORE_CM0_H_DEPENDANT */ 00749 00750 #endif /* __CMSIS_GENERIC */
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