Fawwaz Nadzmy / mbed-dev

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
124:6a4a5b7d7324 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f1xx_hal.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.0.4
<> 144:ef7eb2e8f9f7 6 * @date 29-April-2016
<> 144:ef7eb2e8f9f7 7 * @brief This file contains all the functions prototypes for the HAL
<> 144:ef7eb2e8f9f7 8 * module driver.
<> 144:ef7eb2e8f9f7 9 ******************************************************************************
<> 144:ef7eb2e8f9f7 10 * @attention
<> 144:ef7eb2e8f9f7 11 *
<> 144:ef7eb2e8f9f7 12 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 15 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 16 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 17 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 19 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 20 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 22 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 23 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 24 *
<> 144:ef7eb2e8f9f7 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 35 *
<> 144:ef7eb2e8f9f7 36 ******************************************************************************
<> 144:ef7eb2e8f9f7 37 */
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 40 #ifndef __STM32F1xx_HAL_H
<> 144:ef7eb2e8f9f7 41 #define __STM32F1xx_HAL_H
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 44 extern "C" {
<> 144:ef7eb2e8f9f7 45 #endif
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 48 #include "stm32f1xx_hal_conf.h"
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 /** @addtogroup STM32F1xx_HAL_Driver
<> 144:ef7eb2e8f9f7 51 * @{
<> 144:ef7eb2e8f9f7 52 */
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 /** @addtogroup HAL
<> 144:ef7eb2e8f9f7 55 * @{
<> 144:ef7eb2e8f9f7 56 */
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 59 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 /** @defgroup HAL_Exported_Macros HAL Exported Macros
<> 144:ef7eb2e8f9f7 64 * @{
<> 144:ef7eb2e8f9f7 65 */
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 /** @defgroup DBGMCU_Freeze_Unfreeze Freeze Unfreeze Peripherals in Debug mode
<> 144:ef7eb2e8f9f7 68 * @brief Freeze/Unfreeze Peripherals in Debug mode
<> 144:ef7eb2e8f9f7 69 * Note: On devices STM32F10xx8 and STM32F10xxB,
<> 144:ef7eb2e8f9f7 70 * STM32F101xC/D/E and STM32F103xC/D/E,
<> 144:ef7eb2e8f9f7 71 * STM32F101xF/G and STM32F103xF/G
<> 144:ef7eb2e8f9f7 72 * STM32F10xx4 and STM32F10xx6
<> 144:ef7eb2e8f9f7 73 * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
<> 144:ef7eb2e8f9f7 74 * debug mode (not accessible by the user software in normal mode).
<> 144:ef7eb2e8f9f7 75 * Refer to errata sheet of these devices for more details.
<> 144:ef7eb2e8f9f7 76 * @{
<> 144:ef7eb2e8f9f7 77 */
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 /* Peripherals on APB1 */
<> 144:ef7eb2e8f9f7 80 /**
<> 144:ef7eb2e8f9f7 81 * @brief TIM2 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 82 */
<> 144:ef7eb2e8f9f7 83 #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP)
<> 144:ef7eb2e8f9f7 84 #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP)
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 /**
<> 144:ef7eb2e8f9f7 87 * @brief TIM3 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 88 */
<> 144:ef7eb2e8f9f7 89 #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)
<> 144:ef7eb2e8f9f7 90 #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 #if defined (DBGMCU_CR_DBG_TIM4_STOP)
<> 144:ef7eb2e8f9f7 93 /**
<> 144:ef7eb2e8f9f7 94 * @brief TIM4 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 95 */
<> 144:ef7eb2e8f9f7 96 #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP)
<> 144:ef7eb2e8f9f7 97 #define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP)
<> 144:ef7eb2e8f9f7 98 #endif
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 #if defined (DBGMCU_CR_DBG_TIM5_STOP)
<> 144:ef7eb2e8f9f7 101 /**
<> 144:ef7eb2e8f9f7 102 * @brief TIM5 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 103 */
<> 144:ef7eb2e8f9f7 104 #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP)
<> 144:ef7eb2e8f9f7 105 #define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP)
<> 144:ef7eb2e8f9f7 106 #endif
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 #if defined (DBGMCU_CR_DBG_TIM6_STOP)
<> 144:ef7eb2e8f9f7 109 /**
<> 144:ef7eb2e8f9f7 110 * @brief TIM6 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 111 */
<> 144:ef7eb2e8f9f7 112 #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP)
<> 144:ef7eb2e8f9f7 113 #define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP)
<> 144:ef7eb2e8f9f7 114 #endif
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 #if defined (DBGMCU_CR_DBG_TIM7_STOP)
<> 144:ef7eb2e8f9f7 117 /**
<> 144:ef7eb2e8f9f7 118 * @brief TIM7 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 119 */
<> 144:ef7eb2e8f9f7 120 #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP)
<> 144:ef7eb2e8f9f7 121 #define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP)
<> 144:ef7eb2e8f9f7 122 #endif
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 #if defined (DBGMCU_CR_DBG_TIM12_STOP)
<> 144:ef7eb2e8f9f7 125 /**
<> 144:ef7eb2e8f9f7 126 * @brief TIM12 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 127 */
<> 144:ef7eb2e8f9f7 128 #define __HAL_DBGMCU_FREEZE_TIM12() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP)
<> 144:ef7eb2e8f9f7 129 #define __HAL_DBGMCU_UNFREEZE_TIM12() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP)
<> 144:ef7eb2e8f9f7 130 #endif
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 #if defined (DBGMCU_CR_DBG_TIM13_STOP)
<> 144:ef7eb2e8f9f7 133 /**
<> 144:ef7eb2e8f9f7 134 * @brief TIM13 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 135 */
<> 144:ef7eb2e8f9f7 136 #define __HAL_DBGMCU_FREEZE_TIM13() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP)
<> 144:ef7eb2e8f9f7 137 #define __HAL_DBGMCU_UNFREEZE_TIM13() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP)
<> 144:ef7eb2e8f9f7 138 #endif
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 #if defined (DBGMCU_CR_DBG_TIM14_STOP)
<> 144:ef7eb2e8f9f7 141 /**
<> 144:ef7eb2e8f9f7 142 * @brief TIM14 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 143 */
<> 144:ef7eb2e8f9f7 144 #define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP)
<> 144:ef7eb2e8f9f7 145 #define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP)
<> 144:ef7eb2e8f9f7 146 #endif
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 /**
<> 144:ef7eb2e8f9f7 149 * @brief WWDG Peripherals Debug mode
<> 144:ef7eb2e8f9f7 150 */
<> 144:ef7eb2e8f9f7 151 #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP)
<> 144:ef7eb2e8f9f7 152 #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP)
<> 144:ef7eb2e8f9f7 153
<> 144:ef7eb2e8f9f7 154 /**
<> 144:ef7eb2e8f9f7 155 * @brief IWDG Peripherals Debug mode
<> 144:ef7eb2e8f9f7 156 */
<> 144:ef7eb2e8f9f7 157 #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP)
<> 144:ef7eb2e8f9f7 158 #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP)
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 /**
<> 144:ef7eb2e8f9f7 161 * @brief I2C1 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 162 */
<> 144:ef7eb2e8f9f7 163 #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)
<> 144:ef7eb2e8f9f7 164 #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 #if defined (DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
<> 144:ef7eb2e8f9f7 167 /**
<> 144:ef7eb2e8f9f7 168 * @brief I2C2 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 169 */
<> 144:ef7eb2e8f9f7 170 #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
<> 144:ef7eb2e8f9f7 171 #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
<> 144:ef7eb2e8f9f7 172 #endif
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 #if defined (DBGMCU_CR_DBG_CAN1_STOP)
<> 144:ef7eb2e8f9f7 175 /**
<> 144:ef7eb2e8f9f7 176 * @brief CAN1 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 177 */
<> 144:ef7eb2e8f9f7 178 #define __HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP)
<> 144:ef7eb2e8f9f7 179 #define __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP)
<> 144:ef7eb2e8f9f7 180 #endif
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 #if defined (DBGMCU_CR_DBG_CAN2_STOP)
<> 144:ef7eb2e8f9f7 183 /**
<> 144:ef7eb2e8f9f7 184 * @brief CAN2 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 185 */
<> 144:ef7eb2e8f9f7 186 #define __HAL_DBGMCU_FREEZE_CAN2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP)
<> 144:ef7eb2e8f9f7 187 #define __HAL_DBGMCU_UNFREEZE_CAN2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP)
<> 144:ef7eb2e8f9f7 188 #endif
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190 /* Peripherals on APB2 */
<> 144:ef7eb2e8f9f7 191 #if defined (DBGMCU_CR_DBG_TIM1_STOP)
<> 144:ef7eb2e8f9f7 192 /**
<> 144:ef7eb2e8f9f7 193 * @brief TIM1 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 194 */
<> 144:ef7eb2e8f9f7 195 #define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP)
<> 144:ef7eb2e8f9f7 196 #define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP)
<> 144:ef7eb2e8f9f7 197 #endif
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 #if defined (DBGMCU_CR_DBG_TIM8_STOP)
<> 144:ef7eb2e8f9f7 200 /**
<> 144:ef7eb2e8f9f7 201 * @brief TIM8 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 202 */
<> 144:ef7eb2e8f9f7 203 #define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP)
<> 144:ef7eb2e8f9f7 204 #define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP)
<> 144:ef7eb2e8f9f7 205 #endif
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 #if defined (DBGMCU_CR_DBG_TIM9_STOP)
<> 144:ef7eb2e8f9f7 208 /**
<> 144:ef7eb2e8f9f7 209 * @brief TIM9 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 210 */
<> 144:ef7eb2e8f9f7 211 #define __HAL_DBGMCU_FREEZE_TIM9() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP)
<> 144:ef7eb2e8f9f7 212 #define __HAL_DBGMCU_UNFREEZE_TIM9() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP)
<> 144:ef7eb2e8f9f7 213 #endif
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 #if defined (DBGMCU_CR_DBG_TIM10_STOP)
<> 144:ef7eb2e8f9f7 216 /**
<> 144:ef7eb2e8f9f7 217 * @brief TIM10 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 218 */
<> 144:ef7eb2e8f9f7 219 #define __HAL_DBGMCU_FREEZE_TIM10() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP)
<> 144:ef7eb2e8f9f7 220 #define __HAL_DBGMCU_UNFREEZE_TIM10() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP)
<> 144:ef7eb2e8f9f7 221 #endif
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 #if defined (DBGMCU_CR_DBG_TIM11_STOP)
<> 144:ef7eb2e8f9f7 224 /**
<> 144:ef7eb2e8f9f7 225 * @brief TIM11 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 226 */
<> 144:ef7eb2e8f9f7 227 #define __HAL_DBGMCU_FREEZE_TIM11() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP)
<> 144:ef7eb2e8f9f7 228 #define __HAL_DBGMCU_UNFREEZE_TIM11() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP)
<> 144:ef7eb2e8f9f7 229 #endif
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232 #if defined (DBGMCU_CR_DBG_TIM15_STOP)
<> 144:ef7eb2e8f9f7 233 /**
<> 144:ef7eb2e8f9f7 234 * @brief TIM15 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 235 */
<> 144:ef7eb2e8f9f7 236 #define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP)
<> 144:ef7eb2e8f9f7 237 #define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP)
<> 144:ef7eb2e8f9f7 238 #endif
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 #if defined (DBGMCU_CR_DBG_TIM16_STOP)
<> 144:ef7eb2e8f9f7 241 /**
<> 144:ef7eb2e8f9f7 242 * @brief TIM16 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 243 */
<> 144:ef7eb2e8f9f7 244 #define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP)
<> 144:ef7eb2e8f9f7 245 #define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP)
<> 144:ef7eb2e8f9f7 246 #endif
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 #if defined (DBGMCU_CR_DBG_TIM17_STOP)
<> 144:ef7eb2e8f9f7 249 /**
<> 144:ef7eb2e8f9f7 250 * @brief TIM17 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 251 */
<> 144:ef7eb2e8f9f7 252 #define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP)
<> 144:ef7eb2e8f9f7 253 #define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP)
<> 144:ef7eb2e8f9f7 254 #endif
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 /**
<> 144:ef7eb2e8f9f7 257 * @}
<> 144:ef7eb2e8f9f7 258 */
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260 /**
<> 144:ef7eb2e8f9f7 261 * @}
<> 144:ef7eb2e8f9f7 262 */
<> 144:ef7eb2e8f9f7 263
<> 144:ef7eb2e8f9f7 264 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 265
<> 144:ef7eb2e8f9f7 266 /** @addtogroup HAL_Exported_Functions
<> 144:ef7eb2e8f9f7 267 * @{
<> 144:ef7eb2e8f9f7 268 */
<> 144:ef7eb2e8f9f7 269
<> 144:ef7eb2e8f9f7 270 /** @addtogroup HAL_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 271 * @{
<> 144:ef7eb2e8f9f7 272 */
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274 /* Initialization and de-initialization functions ******************************/
<> 144:ef7eb2e8f9f7 275 HAL_StatusTypeDef HAL_Init(void);
<> 144:ef7eb2e8f9f7 276 HAL_StatusTypeDef HAL_DeInit(void);
<> 144:ef7eb2e8f9f7 277 void HAL_MspInit(void);
<> 144:ef7eb2e8f9f7 278 void HAL_MspDeInit(void);
<> 144:ef7eb2e8f9f7 279 HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
<> 144:ef7eb2e8f9f7 280
<> 144:ef7eb2e8f9f7 281 /**
<> 144:ef7eb2e8f9f7 282 * @}
<> 144:ef7eb2e8f9f7 283 */
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285 /** @addtogroup HAL_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 286 * @{
<> 144:ef7eb2e8f9f7 287 */
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289 /* Peripheral Control functions ************************************************/
<> 144:ef7eb2e8f9f7 290 void HAL_IncTick(void);
<> 144:ef7eb2e8f9f7 291 void HAL_Delay(__IO uint32_t Delay);
<> 144:ef7eb2e8f9f7 292 uint32_t HAL_GetTick(void);
<> 144:ef7eb2e8f9f7 293 void HAL_SuspendTick(void);
<> 144:ef7eb2e8f9f7 294 void HAL_ResumeTick(void);
<> 144:ef7eb2e8f9f7 295 uint32_t HAL_GetHalVersion(void);
<> 144:ef7eb2e8f9f7 296 uint32_t HAL_GetREVID(void);
<> 144:ef7eb2e8f9f7 297 uint32_t HAL_GetDEVID(void);
<> 144:ef7eb2e8f9f7 298 void HAL_DBGMCU_EnableDBGSleepMode(void);
<> 144:ef7eb2e8f9f7 299 void HAL_DBGMCU_DisableDBGSleepMode(void);
<> 144:ef7eb2e8f9f7 300 void HAL_DBGMCU_EnableDBGStopMode(void);
<> 144:ef7eb2e8f9f7 301 void HAL_DBGMCU_DisableDBGStopMode(void);
<> 144:ef7eb2e8f9f7 302 void HAL_DBGMCU_EnableDBGStandbyMode(void);
<> 144:ef7eb2e8f9f7 303 void HAL_DBGMCU_DisableDBGStandbyMode(void);
<> 144:ef7eb2e8f9f7 304
<> 144:ef7eb2e8f9f7 305 /**
<> 144:ef7eb2e8f9f7 306 * @}
<> 144:ef7eb2e8f9f7 307 */
<> 144:ef7eb2e8f9f7 308
<> 144:ef7eb2e8f9f7 309 /**
<> 144:ef7eb2e8f9f7 310 * @}
<> 144:ef7eb2e8f9f7 311 */
<> 144:ef7eb2e8f9f7 312
<> 144:ef7eb2e8f9f7 313
<> 144:ef7eb2e8f9f7 314 /**
<> 144:ef7eb2e8f9f7 315 * @}
<> 144:ef7eb2e8f9f7 316 */
<> 144:ef7eb2e8f9f7 317
<> 144:ef7eb2e8f9f7 318 /**
<> 144:ef7eb2e8f9f7 319 * @}
<> 144:ef7eb2e8f9f7 320 */
<> 144:ef7eb2e8f9f7 321
<> 144:ef7eb2e8f9f7 322 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 323 }
<> 144:ef7eb2e8f9f7 324 #endif
<> 144:ef7eb2e8f9f7 325
<> 144:ef7eb2e8f9f7 326 #endif /* __STM32F1xx_HAL_H */
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/