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targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_flash_ramfunc.c@153:da99e106a1c2, 2016-12-21 (annotated)

Committer:
fwndz
Date:
Wed Dec 21 13:29:33 2016 +0000
Revision:
153:da99e106a1c2
Parent:
151:5eaa88a5bcc7 
init

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l0xx_hal_flash_ramfunc.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 151:5eaa88a5bcc7 5 * @version V1.7.0
<> 151:5eaa88a5bcc7 6 * @date 31-May-2016
<> 144:ef7eb2e8f9f7 7 * @brief FLASH RAMFUNC driver.
<> 144:ef7eb2e8f9f7 8 * This file provides a Flash firmware functions which should be
<> 144:ef7eb2e8f9f7 9 * executed from internal SRAM
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * @verbatim
<> 144:ef7eb2e8f9f7 12
<> 144:ef7eb2e8f9f7 13 *** ARM Compiler ***
<> 144:ef7eb2e8f9f7 14 --------------------
<> 144:ef7eb2e8f9f7 15 [..] RAM functions are defined using the toolchain options.
<> 144:ef7eb2e8f9f7 16 Functions that are be executed in RAM should reside in a separate
<> 144:ef7eb2e8f9f7 17 source module. Using the 'Options for File' dialog you can simply change
<> 144:ef7eb2e8f9f7 18 the 'Code / Const' area of a module to a memory space in physical RAM.
<> 144:ef7eb2e8f9f7 19 Available memory areas are declared in the 'Target' tab of the
<> 144:ef7eb2e8f9f7 20 Options for Target' dialog.
<> 144:ef7eb2e8f9f7 21
<> 144:ef7eb2e8f9f7 22 *** ICCARM Compiler ***
<> 144:ef7eb2e8f9f7 23 -----------------------
<> 144:ef7eb2e8f9f7 24 [..] RAM functions are defined using a specific toolchain keyword "__ramfunc".
<> 144:ef7eb2e8f9f7 25
<> 144:ef7eb2e8f9f7 26 *** GNU Compiler ***
<> 144:ef7eb2e8f9f7 27 --------------------
<> 144:ef7eb2e8f9f7 28 [..] RAM functions are defined using a specific toolchain attribute
<> 144:ef7eb2e8f9f7 29 "__attribute__((section(".RamFunc")))".
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 @endverbatim
<> 144:ef7eb2e8f9f7 32 ******************************************************************************
<> 144:ef7eb2e8f9f7 33 * @attention
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 36 *
<> 144:ef7eb2e8f9f7 37 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 38 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 39 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 40 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 41 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 42 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 43 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 44 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 45 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 46 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 47 *
<> 144:ef7eb2e8f9f7 48 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 49 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 51 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 54 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 55 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 56 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 57 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 58 *
<> 144:ef7eb2e8f9f7 59 ******************************************************************************
<> 144:ef7eb2e8f9f7 60 */
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 63 #include "stm32l0xx_hal.h"
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65 /** @addtogroup STM32L0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 66 * @{
<> 144:ef7eb2e8f9f7 67 */
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 #ifdef HAL_FLASH_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 /** @addtogroup FLASH_RAMFUNC
<> 144:ef7eb2e8f9f7 73 * @brief FLASH functions executed from RAM
<> 144:ef7eb2e8f9f7 74 * @{
<> 144:ef7eb2e8f9f7 75 */
<> 144:ef7eb2e8f9f7 76 /** @addtogroup FLASH_RAMFUNC_Private
<> 144:ef7eb2e8f9f7 77 * @{
<> 144:ef7eb2e8f9f7 78 */
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 81 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 82 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 83 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 84 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 85 static __RAM_FUNC FLASHRAM_WaitForLastOperation(uint32_t Timeout);
<> 144:ef7eb2e8f9f7 86 static __RAM_FUNC FLASHRAM_SetErrorCode(void);
<> 144:ef7eb2e8f9f7 87 /**
<> 144:ef7eb2e8f9f7 88 * @}
<> 144:ef7eb2e8f9f7 89 */
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 /** @addtogroup FLASH_RAMFUNC_Exported_Functions
<> 144:ef7eb2e8f9f7 93 *
<> 144:ef7eb2e8f9f7 94 @verbatim
<> 144:ef7eb2e8f9f7 95 ===============================================================================
<> 144:ef7eb2e8f9f7 96 ##### ramfunc functions #####
<> 144:ef7eb2e8f9f7 97 ===============================================================================
<> 144:ef7eb2e8f9f7 98 [..]
<> 144:ef7eb2e8f9f7 99 This subsection provides a set of functions that should be executed from RAM
<> 144:ef7eb2e8f9f7 100 transfers.
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 @endverbatim
<> 144:ef7eb2e8f9f7 103 * @{
<> 144:ef7eb2e8f9f7 104 */
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 /** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 107 * @{
<> 144:ef7eb2e8f9f7 108 */
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 /**
<> 144:ef7eb2e8f9f7 111 * @brief Enable the power down mode during RUN mode.
<> 144:ef7eb2e8f9f7 112 * @note This function can be used only when the user code is running from Internal SRAM.
<> 144:ef7eb2e8f9f7 113 * @retval HAL Status
<> 144:ef7eb2e8f9f7 114 */
<> 144:ef7eb2e8f9f7 115 __RAM_FUNC HAL_FLASHEx_EnableRunPowerDown(void)
<> 144:ef7eb2e8f9f7 116 {
<> 144:ef7eb2e8f9f7 117 /* Enable the Power Down in Run mode*/
<> 144:ef7eb2e8f9f7 118 __HAL_FLASH_POWER_DOWN_ENABLE();
<> 144:ef7eb2e8f9f7 119 return HAL_OK;
<> 144:ef7eb2e8f9f7 120 }
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 /**
<> 144:ef7eb2e8f9f7 123 * @brief Disable the power down mode during RUN mode.
<> 144:ef7eb2e8f9f7 124 * @note This function can be used only when the user code is running from Internal SRAM.
<> 144:ef7eb2e8f9f7 125 * @retval HAL Status
<> 144:ef7eb2e8f9f7 126 */
<> 144:ef7eb2e8f9f7 127 __RAM_FUNC HAL_FLASHEx_DisableRunPowerDown(void)
<> 144:ef7eb2e8f9f7 128 {
<> 144:ef7eb2e8f9f7 129 /* Disable the Power Down in Run mode*/
<> 144:ef7eb2e8f9f7 130 __HAL_FLASH_POWER_DOWN_DISABLE();
<> 144:ef7eb2e8f9f7 131 return HAL_OK;
<> 144:ef7eb2e8f9f7 132 }
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 /**
<> 144:ef7eb2e8f9f7 135 * @}
<> 144:ef7eb2e8f9f7 136 */
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 #if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx)
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 /** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 141 *
<> 144:ef7eb2e8f9f7 142 @verbatim
<> 144:ef7eb2e8f9f7 143 @endverbatim
<> 144:ef7eb2e8f9f7 144 * @{
<> 144:ef7eb2e8f9f7 145 */
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 /**
<> 144:ef7eb2e8f9f7 148 * @brief Erases a specified 2 pages in program memory in parallel.
<> 144:ef7eb2e8f9f7 149 * @note This function can be used only for STM32L07xxx/STM32L08xxx devices.
<> 144:ef7eb2e8f9f7 150 * To correctly run this function, the HAL_FLASH_Unlock() function
<> 144:ef7eb2e8f9f7 151 * must be called before.
<> 144:ef7eb2e8f9f7 152 * Call the HAL_FLASH_Lock() to disable the flash memory access
<> 144:ef7eb2e8f9f7 153 * (recommended to protect the FLASH memory against possible unwanted operation).
<> 144:ef7eb2e8f9f7 154 * @param Page_Address1: The page address in program memory to be erased in
<> 144:ef7eb2e8f9f7 155 * the first Bank (BANK1). This parameter should be between FLASH_BASE
<> 144:ef7eb2e8f9f7 156 * and FLASH_BANK1_END.
<> 144:ef7eb2e8f9f7 157 * @param Page_Address2: The page address in program memory to be erased in
<> 144:ef7eb2e8f9f7 158 * the second Bank (BANK2). This parameter should be between FLASH_BANK2_BASE
<> 144:ef7eb2e8f9f7 159 * and FLASH_BANK2_END.
<> 144:ef7eb2e8f9f7 160 * @note A Page is erased in the Program memory only if the address to load
<> 144:ef7eb2e8f9f7 161 * is the start address of a page (multiple of 128 bytes).
<> 144:ef7eb2e8f9f7 162 * @retval HAL Status: The returned value can be:
<> 144:ef7eb2e8f9f7 163 * HAL_ERROR, HAL_OK or HAL_TIMEOUT.
<> 144:ef7eb2e8f9f7 164 */
<> 144:ef7eb2e8f9f7 165 __RAM_FUNC HAL_FLASHEx_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_Address2)
<> 144:ef7eb2e8f9f7 166 {
<> 144:ef7eb2e8f9f7 167 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 168
<> 144:ef7eb2e8f9f7 169 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 170 status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 if(status == HAL_OK)
<> 144:ef7eb2e8f9f7 173 {
<> 144:ef7eb2e8f9f7 174 /* Proceed to erase the page */
<> 144:ef7eb2e8f9f7 175 SET_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK);
<> 144:ef7eb2e8f9f7 176 SET_BIT(FLASH->PECR, FLASH_PECR_ERASE);
<> 144:ef7eb2e8f9f7 177 SET_BIT(FLASH->PECR, FLASH_PECR_PROG);
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 /* Write 00000000h to the first word of the first program page to erase */
<> 151:5eaa88a5bcc7 180 *(__IO uint32_t *)Page_Address1 = 0x00000000U;
<> 144:ef7eb2e8f9f7 181 /* Write 00000000h to the first word of the second program page to erase */
<> 151:5eaa88a5bcc7 182 *(__IO uint32_t *)Page_Address2 = 0x00000000U;
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 185 status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 /* If the erase operation is completed, disable the ERASE, PROG and PARALLBANK bits */
<> 144:ef7eb2e8f9f7 188 CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG);
<> 144:ef7eb2e8f9f7 189 CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE);
<> 144:ef7eb2e8f9f7 190 CLEAR_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK);
<> 144:ef7eb2e8f9f7 191 }
<> 144:ef7eb2e8f9f7 192 /* Return the erasesStatus */
<> 144:ef7eb2e8f9f7 193 return status;
<> 144:ef7eb2e8f9f7 194 }
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 /**
<> 144:ef7eb2e8f9f7 197 * @brief Programs 2 half pages in program memory in parallel. The half page size is 16 Words.
<> 144:ef7eb2e8f9f7 198 * @note This function can be used only for STM32L07xxx/STM32L08xxx devices.
<> 144:ef7eb2e8f9f7 199 * @param Address1: specifies the first address to be written in the first bank
<> 144:ef7eb2e8f9f7 200 * (BANK1). This parameter should be between FLASH_BASE and (FLASH_BANK1_END - FLASH_PAGE_SIZE).
<> 144:ef7eb2e8f9f7 201 * @param pBuffer1: pointer to the buffer containing the data to be written
<> 144:ef7eb2e8f9f7 202 * to the first half page in the first bank.
<> 144:ef7eb2e8f9f7 203 * @param Address2: specifies the second address to be written in the second bank
<> 144:ef7eb2e8f9f7 204 * (BANK2). This parameter should be between FLASH_BANK2_BASE and (FLASH_BANK2_END - FLASH_PAGE_SIZE).
<> 144:ef7eb2e8f9f7 205 * @param pBuffer2: pointer to the buffer containing the data to be written
<> 144:ef7eb2e8f9f7 206 * to the second half page in the second bank.
<> 144:ef7eb2e8f9f7 207 * @note To correctly run this function, the HAL_FLASH_Unlock() function
<> 144:ef7eb2e8f9f7 208 * must be called before.
<> 144:ef7eb2e8f9f7 209 * Call the HAL_FLASH_Lock() to disable the flash memory access
<> 144:ef7eb2e8f9f7 210 * (recommended to protect the FLASH memory against possible unwanted operation).
<> 144:ef7eb2e8f9f7 211 * @note Half page write is possible only from SRAM.
<> 144:ef7eb2e8f9f7 212 * @note A half page is written to the program memory only if the first
<> 144:ef7eb2e8f9f7 213 * address to load is the start address of a half page (multiple of 64
<> 144:ef7eb2e8f9f7 214 * bytes) and the 15 remaining words to load are in the same half page.
<> 144:ef7eb2e8f9f7 215 * @note During the Program memory half page write all read operations are
<> 144:ef7eb2e8f9f7 216 * forbidden (this includes DMA read operations and debugger read
<> 144:ef7eb2e8f9f7 217 * operations such as breakpoints, periodic updates, etc.).
<> 144:ef7eb2e8f9f7 218 * @note If a PGAERR is set during a Program memory half page write, the
<> 144:ef7eb2e8f9f7 219 * complete write operation is aborted. Software should then reset the
<> 144:ef7eb2e8f9f7 220 * FPRG and PROG/DATA bits and restart the write operation from the
<> 144:ef7eb2e8f9f7 221 * beginning.
<> 144:ef7eb2e8f9f7 222 * @retval HAL Status: The returned value can be:
<> 144:ef7eb2e8f9f7 223 * HAL_ERROR, HAL_OK or HAL_TIMEOUT.
<> 144:ef7eb2e8f9f7 224 */
<> 144:ef7eb2e8f9f7 225 __RAM_FUNC HAL_FLASHEx_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuffer1, uint32_t Address2, uint32_t* pBuffer2)
<> 144:ef7eb2e8f9f7 226 {
<> 144:ef7eb2e8f9f7 227 uint32_t count;
<> 144:ef7eb2e8f9f7 228 HAL_StatusTypeDef status;
<> 144:ef7eb2e8f9f7 229
<> 144:ef7eb2e8f9f7 230 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 231 status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 232
<> 144:ef7eb2e8f9f7 233 if(status == HAL_OK)
<> 144:ef7eb2e8f9f7 234 {
<> 144:ef7eb2e8f9f7 235 /* Proceed to program the new half page */
<> 144:ef7eb2e8f9f7 236 SET_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK);
<> 144:ef7eb2e8f9f7 237 SET_BIT(FLASH->PECR, FLASH_PECR_FPRG);
<> 144:ef7eb2e8f9f7 238 SET_BIT(FLASH->PECR, FLASH_PECR_PROG);
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 242 status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 243
<> 144:ef7eb2e8f9f7 244 if(status == HAL_OK)
<> 144:ef7eb2e8f9f7 245 {
<> 144:ef7eb2e8f9f7 246 /* Write one half page,
<> 144:ef7eb2e8f9f7 247 Address1 doesn't need to be increased */
<> 151:5eaa88a5bcc7 248 count = 0U;
<> 144:ef7eb2e8f9f7 249
<> 144:ef7eb2e8f9f7 250 /* Disable all IRQs */
<> 144:ef7eb2e8f9f7 251 __disable_irq();
<> 144:ef7eb2e8f9f7 252
<> 151:5eaa88a5bcc7 253 while(count < 16U)
<> 144:ef7eb2e8f9f7 254 {
<> 144:ef7eb2e8f9f7 255 *(__IO uint32_t*) Address1 = *pBuffer1;
<> 144:ef7eb2e8f9f7 256 pBuffer1++;
<> 144:ef7eb2e8f9f7 257 count++;
<> 144:ef7eb2e8f9f7 258 }
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260 /* Write the second half page,
<> 144:ef7eb2e8f9f7 261 Address2 doesn't need to be increased */
<> 151:5eaa88a5bcc7 262 count = 0U;
<> 151:5eaa88a5bcc7 263 while(count < 16U)
<> 144:ef7eb2e8f9f7 264 {
<> 144:ef7eb2e8f9f7 265 *(__IO uint32_t*) Address2 = *pBuffer2;
<> 144:ef7eb2e8f9f7 266 pBuffer2++;
<> 144:ef7eb2e8f9f7 267 count++;
<> 144:ef7eb2e8f9f7 268 }
<> 144:ef7eb2e8f9f7 269
<> 144:ef7eb2e8f9f7 270 /* Enable IRQs */
<> 144:ef7eb2e8f9f7 271 __enable_irq();
<> 144:ef7eb2e8f9f7 272
<> 144:ef7eb2e8f9f7 273 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 274 status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 275 }
<> 144:ef7eb2e8f9f7 276 /* if the write operation is completed, disable the PROG, FPRG and PARALLBANK bits */
<> 144:ef7eb2e8f9f7 277 CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG);
<> 144:ef7eb2e8f9f7 278 CLEAR_BIT(FLASH->PECR, FLASH_PECR_FPRG);
<> 144:ef7eb2e8f9f7 279 CLEAR_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK);
<> 144:ef7eb2e8f9f7 280 }
<> 144:ef7eb2e8f9f7 281 /* Return the Write Status */
<> 144:ef7eb2e8f9f7 282 return status;
<> 144:ef7eb2e8f9f7 283 }
<> 144:ef7eb2e8f9f7 284 /**
<> 144:ef7eb2e8f9f7 285 * @}
<> 144:ef7eb2e8f9f7 286 */
<> 144:ef7eb2e8f9f7 287 #endif /* STM32L071xx || STM32L072xx || STM32L073xx || STM32L081xx || STM32L082xx || STM32L083xx */
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289 /** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 290 *
<> 144:ef7eb2e8f9f7 291 * @{
<> 144:ef7eb2e8f9f7 292 */
<> 144:ef7eb2e8f9f7 293 /**
<> 144:ef7eb2e8f9f7 294 * @brief Program a half page in program memory.
<> 144:ef7eb2e8f9f7 295 * @param Address: specifies the address to be written.
<> 144:ef7eb2e8f9f7 296 * @param pBuffer: pointer to the buffer containing the data to be written to
<> 144:ef7eb2e8f9f7 297 * the half page.
<> 144:ef7eb2e8f9f7 298 * @note To correctly run this function, the HAL_FLASH_Unlock() function
<> 144:ef7eb2e8f9f7 299 * must be called before.
<> 144:ef7eb2e8f9f7 300 * Call the HAL_FLASH_Lock() to disable the flash memory access
<> 144:ef7eb2e8f9f7 301 * (recommended to protect the FLASH memory against possible unwanted operation)
<> 144:ef7eb2e8f9f7 302 * @note Half page write is possible only from SRAM.
<> 144:ef7eb2e8f9f7 303 * @note A half page is written to the program memory only if the first
<> 144:ef7eb2e8f9f7 304 * address to load is the start address of a half page (multiple of 64
<> 144:ef7eb2e8f9f7 305 * bytes) and the 15 remaining words to load are in the same half page.
<> 144:ef7eb2e8f9f7 306 * @note During the Program memory half page write all read operations are
<> 144:ef7eb2e8f9f7 307 * forbidden (this includes DMA read operations and debugger read
<> 144:ef7eb2e8f9f7 308 * operations such as breakpoints, periodic updates, etc.).
<> 144:ef7eb2e8f9f7 309 * @note If a PGAERR is set during a Program memory half page write, the
<> 144:ef7eb2e8f9f7 310 * complete write operation is aborted. Software should then reset the
<> 144:ef7eb2e8f9f7 311 * FPRG and PROG/DATA bits and restart the write operation from the
<> 144:ef7eb2e8f9f7 312 * beginning.
<> 144:ef7eb2e8f9f7 313 * @retval HAL Status: The returned value can be:
<> 144:ef7eb2e8f9f7 314 * HAL_ERROR, HAL_OK or HAL_TIMEOUT.
<> 144:ef7eb2e8f9f7 315 */
<> 144:ef7eb2e8f9f7 316 __RAM_FUNC HAL_FLASHEx_HalfPageProgram(uint32_t Address, uint32_t *pBuffer)
<> 144:ef7eb2e8f9f7 317 {
<> 144:ef7eb2e8f9f7 318 uint32_t count;
<> 144:ef7eb2e8f9f7 319 HAL_StatusTypeDef status;
<> 144:ef7eb2e8f9f7 320
<> 144:ef7eb2e8f9f7 321 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 322 status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 323
<> 144:ef7eb2e8f9f7 324 if(status == HAL_OK)
<> 144:ef7eb2e8f9f7 325 {
<> 144:ef7eb2e8f9f7 326 /* Proceed to program the new half page */
<> 144:ef7eb2e8f9f7 327 SET_BIT(FLASH->PECR, FLASH_PECR_FPRG);
<> 144:ef7eb2e8f9f7 328 SET_BIT(FLASH->PECR, FLASH_PECR_PROG);
<> 144:ef7eb2e8f9f7 329
<> 144:ef7eb2e8f9f7 330
<> 151:5eaa88a5bcc7 331 count = 0U;
<> 144:ef7eb2e8f9f7 332 /* Write one half page,
<> 144:ef7eb2e8f9f7 333 Address doesn't need to be increased */
<> 144:ef7eb2e8f9f7 334
<> 144:ef7eb2e8f9f7 335 /* Disable all IRQs */
<> 144:ef7eb2e8f9f7 336 __disable_irq();
<> 144:ef7eb2e8f9f7 337
<> 151:5eaa88a5bcc7 338 while(count < 16U)
<> 144:ef7eb2e8f9f7 339 {
<> 144:ef7eb2e8f9f7 340 *(__IO uint32_t*) Address = *pBuffer;
<> 144:ef7eb2e8f9f7 341 pBuffer++;
<> 144:ef7eb2e8f9f7 342 count++;
<> 144:ef7eb2e8f9f7 343 }
<> 144:ef7eb2e8f9f7 344
<> 144:ef7eb2e8f9f7 345 /* Enable IRQs */
<> 144:ef7eb2e8f9f7 346 __enable_irq();
<> 144:ef7eb2e8f9f7 347
<> 144:ef7eb2e8f9f7 348 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 349 status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 350
<> 144:ef7eb2e8f9f7 351 /* If the write operation is completed, disable the PROG and FPRG bits */
<> 144:ef7eb2e8f9f7 352 CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG);
<> 144:ef7eb2e8f9f7 353 CLEAR_BIT(FLASH->PECR, FLASH_PECR_FPRG);
<> 144:ef7eb2e8f9f7 354 }
<> 144:ef7eb2e8f9f7 355 /* Return the write status */
<> 144:ef7eb2e8f9f7 356 return status;
<> 144:ef7eb2e8f9f7 357 }
<> 144:ef7eb2e8f9f7 358
<> 144:ef7eb2e8f9f7 359 /**
<> 144:ef7eb2e8f9f7 360 * @brief Get the specific FLASH errors flag.
<> 144:ef7eb2e8f9f7 361 * @param error pointer is the error value. It can be a mixed of :
<> 144:ef7eb2e8f9f7 362 * @arg HAL_FLASH_ERROR_RD: FLASH Read Protection error flag (PCROP)
<> 144:ef7eb2e8f9f7 363 * @arg HAL_FLASH_ERROR_SIZE: FLASH Programming Parallelism error flag
<> 144:ef7eb2e8f9f7 364 * @arg HAL_FLASH_ERROR_PGA: FLASH Programming Alignment error flag
<> 144:ef7eb2e8f9f7 365 * @arg HAL_FLASH_ERROR_WRP: FLASH Write protected error flag
<> 144:ef7eb2e8f9f7 366 * @arg HAL_FLASH_ERROR_OPTV: FLASH Option valid error flag
<> 144:ef7eb2e8f9f7 367 * @arg HAL_FLASH_ERROR_FWWERR: FLASH Write or Errase operation aborted
<> 144:ef7eb2e8f9f7 368 * @arg HAL_FLASH_ERROR_NOTZERO: FLASH Write operation is done in a not-erased region
<> 144:ef7eb2e8f9f7 369 * @retval HAL Status
<> 144:ef7eb2e8f9f7 370 */
<> 144:ef7eb2e8f9f7 371 __RAM_FUNC HAL_FLASHRAM_GetError(uint32_t * error)
<> 144:ef7eb2e8f9f7 372 {
<> 144:ef7eb2e8f9f7 373 *error = ProcFlash.ErrorCode;
<> 144:ef7eb2e8f9f7 374 return HAL_OK;
<> 144:ef7eb2e8f9f7 375 }
<> 144:ef7eb2e8f9f7 376
<> 144:ef7eb2e8f9f7 377 /**
<> 144:ef7eb2e8f9f7 378 * @}
<> 144:ef7eb2e8f9f7 379 */
<> 144:ef7eb2e8f9f7 380
<> 144:ef7eb2e8f9f7 381 /**
<> 144:ef7eb2e8f9f7 382 * @}
<> 144:ef7eb2e8f9f7 383 */
<> 144:ef7eb2e8f9f7 384
<> 144:ef7eb2e8f9f7 385 /** @addtogroup FLASH_RAMFUNC_Private
<> 144:ef7eb2e8f9f7 386 * @{
<> 144:ef7eb2e8f9f7 387 */
<> 144:ef7eb2e8f9f7 388
<> 144:ef7eb2e8f9f7 389 /**
<> 144:ef7eb2e8f9f7 390 * @brief Set the specific FLASH error flag.
<> 144:ef7eb2e8f9f7 391 * @retval HAL Status
<> 144:ef7eb2e8f9f7 392 */
<> 144:ef7eb2e8f9f7 393 static __RAM_FUNC FLASHRAM_SetErrorCode(void)
<> 144:ef7eb2e8f9f7 394 {
<> 144:ef7eb2e8f9f7 395 if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
<> 144:ef7eb2e8f9f7 396 {
<> 144:ef7eb2e8f9f7 397 ProcFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
<> 144:ef7eb2e8f9f7 398 }
<> 144:ef7eb2e8f9f7 399 if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR))
<> 144:ef7eb2e8f9f7 400 {
<> 144:ef7eb2e8f9f7 401 ProcFlash.ErrorCode |= HAL_FLASH_ERROR_PGA;
<> 144:ef7eb2e8f9f7 402 }
<> 144:ef7eb2e8f9f7 403 if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR))
<> 144:ef7eb2e8f9f7 404 {
<> 144:ef7eb2e8f9f7 405 ProcFlash.ErrorCode |= HAL_FLASH_ERROR_SIZE;
<> 144:ef7eb2e8f9f7 406 }
<> 144:ef7eb2e8f9f7 407 if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR))
<> 144:ef7eb2e8f9f7 408 {
<> 144:ef7eb2e8f9f7 409 /* WARNING : On the first cut of STM32L031xx and STM32L041xx devices,
<> 151:5eaa88a5bcc7 410 * (RefID = 0x1000) the FLASH_FLAG_OPTVERR bit was not behaving
<> 144:ef7eb2e8f9f7 411 * as expected. If the user run an application using the first
<> 144:ef7eb2e8f9f7 412 * cut of the STM32L031xx device or the first cut of the STM32L041xx
<> 151:5eaa88a5bcc7 413 * device, this error should be ignored. The revId of the device
<> 144:ef7eb2e8f9f7 414 * can be retrieved via the HAL_GetREVID() function.
<> 144:ef7eb2e8f9f7 415 *
<> 144:ef7eb2e8f9f7 416 */
<> 144:ef7eb2e8f9f7 417 ProcFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV;
<> 144:ef7eb2e8f9f7 418 }
<> 144:ef7eb2e8f9f7 419 if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR))
<> 144:ef7eb2e8f9f7 420 {
<> 144:ef7eb2e8f9f7 421 ProcFlash.ErrorCode |= HAL_FLASH_ERROR_RD;
<> 144:ef7eb2e8f9f7 422 }
<> 144:ef7eb2e8f9f7 423 if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_FWWERR))
<> 144:ef7eb2e8f9f7 424 {
<> 144:ef7eb2e8f9f7 425 ProcFlash.ErrorCode |= HAL_FLASH_ERROR_FWWERR;
<> 144:ef7eb2e8f9f7 426 }
<> 144:ef7eb2e8f9f7 427 if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_NOTZEROERR))
<> 144:ef7eb2e8f9f7 428 {
<> 144:ef7eb2e8f9f7 429 ProcFlash.ErrorCode |= HAL_FLASH_ERROR_NOTZERO;
<> 144:ef7eb2e8f9f7 430 }
<> 144:ef7eb2e8f9f7 431
<> 144:ef7eb2e8f9f7 432 /* Errors are now stored, clear errors flags */
<> 144:ef7eb2e8f9f7 433
<> 144:ef7eb2e8f9f7 434 __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR |
<> 144:ef7eb2e8f9f7 435 FLASH_FLAG_OPTVERR | FLASH_FLAG_RDERR | FLASH_FLAG_FWWERR |
<> 144:ef7eb2e8f9f7 436 FLASH_FLAG_NOTZEROERR);
<> 144:ef7eb2e8f9f7 437 return HAL_OK;
<> 144:ef7eb2e8f9f7 438 }
<> 144:ef7eb2e8f9f7 439
<> 144:ef7eb2e8f9f7 440
<> 144:ef7eb2e8f9f7 441 /**
<> 144:ef7eb2e8f9f7 442 * @brief Wait for a FLASH operation to complete.
<> 144:ef7eb2e8f9f7 443 * @param Timeout: maximum flash operationtimeout
<> 144:ef7eb2e8f9f7 444 * @retval HAL status
<> 144:ef7eb2e8f9f7 445 */
<> 144:ef7eb2e8f9f7 446 static __RAM_FUNC FLASHRAM_WaitForLastOperation(uint32_t Timeout)
<> 144:ef7eb2e8f9f7 447 {
<> 144:ef7eb2e8f9f7 448 /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
<> 144:ef7eb2e8f9f7 449 Even if the FLASH operation fails, the BUSY flag will be reset and an error
<> 144:ef7eb2e8f9f7 450 flag will be set */
<> 144:ef7eb2e8f9f7 451
<> 151:5eaa88a5bcc7 452 while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) && (Timeout != 0x00U))
<> 144:ef7eb2e8f9f7 453 {
<> 144:ef7eb2e8f9f7 454 Timeout--;
<> 144:ef7eb2e8f9f7 455 }
<> 144:ef7eb2e8f9f7 456
<> 151:5eaa88a5bcc7 457 if(Timeout == 0x00U )
<> 144:ef7eb2e8f9f7 458 {
<> 144:ef7eb2e8f9f7 459 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 460 }
<> 144:ef7eb2e8f9f7 461
<> 144:ef7eb2e8f9f7 462 if( (__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET) ||
<> 144:ef7eb2e8f9f7 463 (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET) ||
<> 144:ef7eb2e8f9f7 464 (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET) ||
<> 144:ef7eb2e8f9f7 465 (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) != RESET) ||
<> 144:ef7eb2e8f9f7 466 (__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR) != RESET) ||
<> 144:ef7eb2e8f9f7 467 (__HAL_FLASH_GET_FLAG(FLASH_FLAG_FWWERR) != RESET) ||
<> 144:ef7eb2e8f9f7 468 (__HAL_FLASH_GET_FLAG(FLASH_FLAG_NOTZEROERR) != RESET) )
<> 144:ef7eb2e8f9f7 469 {
<> 144:ef7eb2e8f9f7 470 /*Save the error code*/
<> 144:ef7eb2e8f9f7 471
<> 144:ef7eb2e8f9f7 472 /* WARNING : On the first cut of STM32L031xx and STM32L041xx devices,
<> 144:ef7eb2e8f9f7 473 * (RefID = 0x1000) the FLASH_FLAG_OPTVERR bit was not behaving
<> 144:ef7eb2e8f9f7 474 * as expected. If the user run an application using the first
<> 144:ef7eb2e8f9f7 475 * cut of the STM32L031xx device or the first cut of the STM32L041xx
<> 144:ef7eb2e8f9f7 476 * device, this error should be ignored. The revId of the device
<> 144:ef7eb2e8f9f7 477 * can be retrieved via the HAL_GetREVID() function.
<> 144:ef7eb2e8f9f7 478 *
<> 144:ef7eb2e8f9f7 479 */
<> 144:ef7eb2e8f9f7 480
<> 144:ef7eb2e8f9f7 481 FLASHRAM_SetErrorCode();
<> 144:ef7eb2e8f9f7 482 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 483 }
<> 144:ef7eb2e8f9f7 484
<> 144:ef7eb2e8f9f7 485 /* If there is an error flag set */
<> 144:ef7eb2e8f9f7 486 return HAL_OK;
<> 144:ef7eb2e8f9f7 487 }
<> 144:ef7eb2e8f9f7 488
<> 144:ef7eb2e8f9f7 489 /**
<> 144:ef7eb2e8f9f7 490 * @}
<> 144:ef7eb2e8f9f7 491 */
<> 144:ef7eb2e8f9f7 492
<> 144:ef7eb2e8f9f7 493 /**
<> 144:ef7eb2e8f9f7 494 * @}
<> 144:ef7eb2e8f9f7 495 */
<> 144:ef7eb2e8f9f7 496
<> 144:ef7eb2e8f9f7 497 #endif /* HAL_FLASH_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 498
<> 144:ef7eb2e8f9f7 499 /**
<> 144:ef7eb2e8f9f7 500 * @}
<> 144:ef7eb2e8f9f7 501 */
<> 144:ef7eb2e8f9f7 502
<> 144:ef7eb2e8f9f7 503
<> 144:ef7eb2e8f9f7 504 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 144:ef7eb2e8f9f7 505