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targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_spi.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:: bogdanm
Date:: Thu Oct 01 15:25:22 2015 +0300
Revision:: 0:9b334a45a8ff
Child:: 124:6a4a5b7d7324

Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32f1xx_hal_spi.c
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
bogdanm	0:9b334a45a8ff	5	* @version V1.0.0
bogdanm	0:9b334a45a8ff	6	* @date 15-December-2014
bogdanm	0:9b334a45a8ff	7	* @brief SPI HAL module driver.
bogdanm	0:9b334a45a8ff	8	*
bogdanm	0:9b334a45a8ff	9	* This file provides firmware functions to manage the following
bogdanm	0:9b334a45a8ff	10	* functionalities of the Serial Peripheral Interface (SPI) peripheral:
bogdanm	0:9b334a45a8ff	11	* + Initialization and de-initialization functions
bogdanm	0:9b334a45a8ff	12	* + IO operation functions
bogdanm	0:9b334a45a8ff	13	* + Peripheral Control functions
bogdanm	0:9b334a45a8ff	14	* + Peripheral State functions
bogdanm	0:9b334a45a8ff	15	@verbatim
bogdanm	0:9b334a45a8ff	16	==============================================================================
bogdanm	0:9b334a45a8ff	17	##### How to use this driver #####
bogdanm	0:9b334a45a8ff	18	==============================================================================
bogdanm	0:9b334a45a8ff	19	[..]
bogdanm	0:9b334a45a8ff	20	The SPI HAL driver can be used as follows:
bogdanm	0:9b334a45a8ff	21
bogdanm	0:9b334a45a8ff	22	(#) Declare a SPI_HandleTypeDef handle structure, for example:
bogdanm	0:9b334a45a8ff	23	SPI_HandleTypeDef hspi;
bogdanm	0:9b334a45a8ff	24
bogdanm	0:9b334a45a8ff	25	(#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit ()API:
bogdanm	0:9b334a45a8ff	26	(##) Enable the SPIx interface clock
bogdanm	0:9b334a45a8ff	27	(##) SPI pins configuration
bogdanm	0:9b334a45a8ff	28	(+++) Enable the clock for the SPI GPIOs
bogdanm	0:9b334a45a8ff	29	(+++) Configure these SPI pins as alternate function push-pull
bogdanm	0:9b334a45a8ff	30	(##) NVIC configuration if you need to use interrupt process
bogdanm	0:9b334a45a8ff	31	(+++) Configure the SPIx interrupt priority
bogdanm	0:9b334a45a8ff	32	(+++) Enable the NVIC SPI IRQ handle
bogdanm	0:9b334a45a8ff	33	(##) DMA Configuration if you need to use DMA process
bogdanm	0:9b334a45a8ff	34	(+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Channel
bogdanm	0:9b334a45a8ff	35	(+++) Enable the DMAx clock
bogdanm	0:9b334a45a8ff	36	(+++) Configure the DMA handle parameters
bogdanm	0:9b334a45a8ff	37	(+++) Configure the DMA Tx or Rx Channel
bogdanm	0:9b334a45a8ff	38	(+++) Associate the initilalized hdma_tx(or _rx) handle to the hspi DMA Tx (or Rx) handle
bogdanm	0:9b334a45a8ff	39	(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Channel
bogdanm	0:9b334a45a8ff	40
bogdanm	0:9b334a45a8ff	41	(#) Program the Mode, Direction , Data size, Baudrate Prescaler, NSS
bogdanm	0:9b334a45a8ff	42	management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
bogdanm	0:9b334a45a8ff	43
bogdanm	0:9b334a45a8ff	44	(#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
bogdanm	0:9b334a45a8ff	45	(++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
bogdanm	0:9b334a45a8ff	46	by calling the customed HAL_SPI_MspInit() API.
bogdanm	0:9b334a45a8ff	47	[..]
bogdanm	0:9b334a45a8ff	48	Circular mode restriction:
bogdanm	0:9b334a45a8ff	49	(#) The DMA circular mode cannot be used when the SPI is configured in these modes:
bogdanm	0:9b334a45a8ff	50	(##) Master 2Lines RxOnly
bogdanm	0:9b334a45a8ff	51	(##) Master 1Line Rx
bogdanm	0:9b334a45a8ff	52	(#) The CRC feature is not managed when the DMA circular mode is enabled
bogdanm	0:9b334a45a8ff	53	(#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
bogdanm	0:9b334a45a8ff	54	the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
bogdanm	0:9b334a45a8ff	55
bogdanm	0:9b334a45a8ff	56	[..]
bogdanm	0:9b334a45a8ff	57	Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes,
bogdanm	0:9b334a45a8ff	58	the following table resume the max SPI frequency reached with data size 8bits/16bits,
bogdanm	0:9b334a45a8ff	59	according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance :
bogdanm	0:9b334a45a8ff	60
bogdanm	0:9b334a45a8ff	61	For 8 bits SPI data size transfers :
bogdanm	0:9b334a45a8ff	62	+--------------------------------------------------------------------------------------------------+
bogdanm	0:9b334a45a8ff	63	\| \| \| 2Lines Fullduplex \| 2Lines RxOnly \| 1Line \|
bogdanm	0:9b334a45a8ff	64	\| Process \| Tranfert mode \|-----------------------\|-----------------------\|-----------------------\|
bogdanm	0:9b334a45a8ff	65	\| \| \| Master \| Slave \| Master \| Slave \| Master \| Slave \|
bogdanm	0:9b334a45a8ff	66	\|==================================================================================================\|
bogdanm	0:9b334a45a8ff	67	\| T \| Polling \| fPCLK/8 \| fPCLK/8 \| NA \| NA \| NA \| NA \|
bogdanm	0:9b334a45a8ff	68	\| X \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
bogdanm	0:9b334a45a8ff	69	\| / \| Interrupt \| fPCLK/32 \| fPCLK/32 \| NA \| NA \| NA \| NA \|
bogdanm	0:9b334a45a8ff	70	\| R \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
bogdanm	0:9b334a45a8ff	71	\| X \| DMA \| fPCLK/2 \| fPCLK/4 \| NA \| NA \| NA \| NA \|
bogdanm	0:9b334a45a8ff	72	\|=========\|================\|===========\|===========\|===========\|===========\|===========\|===========\|
bogdanm	0:9b334a45a8ff	73	\| \| Polling \| fPCLK/4 \| fPCLK/8 \| fPCLK/128 \| fPCLK/16 \| fPCLK/128 \| fPCLK/8 \|
bogdanm	0:9b334a45a8ff	74	\| \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
bogdanm	0:9b334a45a8ff	75	\| R \| Interrupt \| fPCLK/32 \| fPCLK/16 \| fPCLK/128 \| fPCLK/16 \| fPCLK/128 \| fPCLK/16 \|
bogdanm	0:9b334a45a8ff	76	\| X \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
bogdanm	0:9b334a45a8ff	77	\| \| DMA \| fPCLK/2 \| fPCLK/2 \| fPCLK/128 \| fPCLK/16 \| fPCLK/128 \| fPCLK/2 \|
bogdanm	0:9b334a45a8ff	78	\|=========\|================\|===========\|===========\|===========\|===========\|===========\|===========\|
bogdanm	0:9b334a45a8ff	79	\| \| Polling \| fPCLK/4 \| fPCLK/4 \| NA \| NA \| fPCLK/4 \| fPCLK/64 \|
bogdanm	0:9b334a45a8ff	80	\| \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
bogdanm	0:9b334a45a8ff	81	\| T \| Interrupt \| fPCLK/8 \| fPCLK/16 \| NA \| NA \| fPCLK/8 \| fPCLK/128 \|
bogdanm	0:9b334a45a8ff	82	\| X \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
bogdanm	0:9b334a45a8ff	83	\| \| DMA \| fPCLK/2 \| fPCLK/4 \| NA \| NA \| fPCLK/2 \| fPCLK/64 \|
bogdanm	0:9b334a45a8ff	84	+--------------------------------------------------------------------------------------------------+
bogdanm	0:9b334a45a8ff	85
bogdanm	0:9b334a45a8ff	86	For 16 bits SPI data size transfers :
bogdanm	0:9b334a45a8ff	87	+--------------------------------------------------------------------------------------------------+
bogdanm	0:9b334a45a8ff	88	\| \| \| 2Lines Fullduplex \| 2Lines RxOnly \| 1Line \|
bogdanm	0:9b334a45a8ff	89	\| Process \| Tranfert mode \|-----------------------\|-----------------------\|-----------------------\|
bogdanm	0:9b334a45a8ff	90	\| \| \| Master \| Slave \| Master \| Slave \| Master \| Slave \|
bogdanm	0:9b334a45a8ff	91	\|==================================================================================================\|
bogdanm	0:9b334a45a8ff	92	\| T \| Polling \| fPCLK/2 \| fPCLK/4 \| NA \| NA \| NA \| NA \|
bogdanm	0:9b334a45a8ff	93	\| X \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
bogdanm	0:9b334a45a8ff	94	\| / \| Interrupt \| fPCLK/16 \| fPCLK/16 \| NA \| NA \| NA \| NA \|
bogdanm	0:9b334a45a8ff	95	\| R \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
bogdanm	0:9b334a45a8ff	96	\| X \| DMA \| fPCLK/2 \| fPCLK/4 \| NA \| NA \| NA \| NA \|
bogdanm	0:9b334a45a8ff	97	\|=========\|================\|===========\|===========\|===========\|===========\|===========\|===========\|
bogdanm	0:9b334a45a8ff	98	\| \| Polling \| fPCLK/2 \| fPCLK/4 \| fPCLK/64 \| fPCLK/8 \| fPCLK/64 \| fPCLK/4 \|
bogdanm	0:9b334a45a8ff	99	\| \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
bogdanm	0:9b334a45a8ff	100	\| R \| Interrupt \| fPCLK/16 \| fPCLK/8 \| fPCLK/128 \| fPCLK/8 \| fPCLK/128 \| fPCLK/8 \|
bogdanm	0:9b334a45a8ff	101	\| X \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
bogdanm	0:9b334a45a8ff	102	\| \| DMA \| fPCLK/2 \| fPCLK/2 \| fPCLK/128 \| fPCLK/8 \| fPCLK/128 \| fPCLK/2 \|
bogdanm	0:9b334a45a8ff	103	\|=========\|================\|===========\|===========\|===========\|===========\|===========\|===========\|
bogdanm	0:9b334a45a8ff	104	\| \| Polling \| fPCLK/2 \| fPCLK/4 \| NA \| NA \| fPCLK/2 \| fPCLK/64 \|
bogdanm	0:9b334a45a8ff	105	\| \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
bogdanm	0:9b334a45a8ff	106	\| T \| Interrupt \| fPCLK/4 \| fPCLK/8 \| NA \| NA \| fPCLK/4 \| fPCLK/256 \|
bogdanm	0:9b334a45a8ff	107	\| X \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
bogdanm	0:9b334a45a8ff	108	\| \| DMA \| fPCLK/2 \| fPCLK/4 \| NA \| NA \| fPCLK/2 \| fPCLK/32 \|
bogdanm	0:9b334a45a8ff	109	+--------------------------------------------------------------------------------------------------+
bogdanm	0:9b334a45a8ff	110
bogdanm	0:9b334a45a8ff	111	@note The max SPI frequency depend on SPI data size (8bits, 16bits),
bogdanm	0:9b334a45a8ff	112	SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
bogdanm	0:9b334a45a8ff	113	@note
bogdanm	0:9b334a45a8ff	114	(#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
bogdanm	0:9b334a45a8ff	115	(#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
bogdanm	0:9b334a45a8ff	116	(#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
bogdanm	0:9b334a45a8ff	117
bogdanm	0:9b334a45a8ff	118	@endverbatim
bogdanm	0:9b334a45a8ff	119	******************************************************************************
bogdanm	0:9b334a45a8ff	120	* @attention
bogdanm	0:9b334a45a8ff	121	*
bogdanm	0:9b334a45a8ff	122	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	123	*
bogdanm	0:9b334a45a8ff	124	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	125	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	126	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	127	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	128	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	129	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	130	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	131	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	132	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	133	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	134	*
bogdanm	0:9b334a45a8ff	135	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	136	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	137	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	138	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	139	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	140	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	141	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	142	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	143	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	144	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	145	*
bogdanm	0:9b334a45a8ff	146	******************************************************************************
bogdanm	0:9b334a45a8ff	147	*/
bogdanm	0:9b334a45a8ff	148
bogdanm	0:9b334a45a8ff	149	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	150	#include "stm32f1xx_hal.h"
bogdanm	0:9b334a45a8ff	151
bogdanm	0:9b334a45a8ff	152	/** @addtogroup STM32F1xx_HAL_Driver
bogdanm	0:9b334a45a8ff	153	* @{
bogdanm	0:9b334a45a8ff	154	*/
bogdanm	0:9b334a45a8ff	155
bogdanm	0:9b334a45a8ff	156	/** @defgroup SPI SPI
bogdanm	0:9b334a45a8ff	157	* @brief SPI HAL module driver
bogdanm	0:9b334a45a8ff	158	* @{
bogdanm	0:9b334a45a8ff	159	*/
bogdanm	0:9b334a45a8ff	160
bogdanm	0:9b334a45a8ff	161	#ifdef HAL_SPI_MODULE_ENABLED
bogdanm	0:9b334a45a8ff	162
bogdanm	0:9b334a45a8ff	163	/* Private typedef -----------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	164	/* Private define ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	165	/** @defgroup SPI_Private_Constants SPI Private Constants
bogdanm	0:9b334a45a8ff	166	* @{
bogdanm	0:9b334a45a8ff	167	*/
bogdanm	0:9b334a45a8ff	168	#define SPI_TIMEOUT_VALUE 10
bogdanm	0:9b334a45a8ff	169	/**
bogdanm	0:9b334a45a8ff	170	* @}
bogdanm	0:9b334a45a8ff	171	*/
bogdanm	0:9b334a45a8ff	172
bogdanm	0:9b334a45a8ff	173	/* Private macro -------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	174	/* Private variables ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	175	/* Private function prototypes -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	176	/** @defgroup SPI_Private_Functions SPI Private Functions
bogdanm	0:9b334a45a8ff	177	* @{
bogdanm	0:9b334a45a8ff	178	*/
bogdanm	0:9b334a45a8ff	179	static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	180	static void SPI_TxISR(SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	181	static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	182	static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	183	static void SPI_RxISR(SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	184	static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	185	static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	186	static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	187	static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	188	static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	189	static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	190	static void SPI_DMAError(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	191	static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
bogdanm	0:9b334a45a8ff	192	/**
bogdanm	0:9b334a45a8ff	193	* @}
bogdanm	0:9b334a45a8ff	194	*/
bogdanm	0:9b334a45a8ff	195
bogdanm	0:9b334a45a8ff	196	/* Exported functions ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	197
bogdanm	0:9b334a45a8ff	198	/** @defgroup SPI_Exported_Functions SPI Exported Functions
bogdanm	0:9b334a45a8ff	199	* @{
bogdanm	0:9b334a45a8ff	200	*/
bogdanm	0:9b334a45a8ff	201
bogdanm	0:9b334a45a8ff	202	/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm	0:9b334a45a8ff	203	* @brief Initialization and Configuration functions
bogdanm	0:9b334a45a8ff	204	*
bogdanm	0:9b334a45a8ff	205	@verbatim
bogdanm	0:9b334a45a8ff	206	===============================================================================
bogdanm	0:9b334a45a8ff	207	##### Initialization and de-initialization functions #####
bogdanm	0:9b334a45a8ff	208	===============================================================================
bogdanm	0:9b334a45a8ff	209	[..] This subsection provides a set of functions allowing to initialize and
bogdanm	0:9b334a45a8ff	210	de-initialiaze the SPIx peripheral:
bogdanm	0:9b334a45a8ff	211
bogdanm	0:9b334a45a8ff	212	(+) User must implement HAL_SPI_MspInit() function in which he configures
bogdanm	0:9b334a45a8ff	213	all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
bogdanm	0:9b334a45a8ff	214
bogdanm	0:9b334a45a8ff	215	(+) Call the function HAL_SPI_Init() to configure the selected device with
bogdanm	0:9b334a45a8ff	216	the selected configuration:
bogdanm	0:9b334a45a8ff	217	(++) Mode
bogdanm	0:9b334a45a8ff	218	(++) Direction
bogdanm	0:9b334a45a8ff	219	(++) Data Size
bogdanm	0:9b334a45a8ff	220	(++) Clock Polarity and Phase
bogdanm	0:9b334a45a8ff	221	(++) NSS Management
bogdanm	0:9b334a45a8ff	222	(++) BaudRate Prescaler
bogdanm	0:9b334a45a8ff	223	(++) FirstBit
bogdanm	0:9b334a45a8ff	224	(++) TIMode
bogdanm	0:9b334a45a8ff	225	(++) CRC Calculation
bogdanm	0:9b334a45a8ff	226	(++) CRC Polynomial if CRC enabled
bogdanm	0:9b334a45a8ff	227
bogdanm	0:9b334a45a8ff	228	(+) Call the function HAL_SPI_DeInit() to restore the default configuration
bogdanm	0:9b334a45a8ff	229	of the selected SPIx periperal.
bogdanm	0:9b334a45a8ff	230
bogdanm	0:9b334a45a8ff	231	@endverbatim
bogdanm	0:9b334a45a8ff	232	* @{
bogdanm	0:9b334a45a8ff	233	*/
bogdanm	0:9b334a45a8ff	234
bogdanm	0:9b334a45a8ff	235	/**
bogdanm	0:9b334a45a8ff	236	* @brief Initializes the SPI according to the specified parameters
bogdanm	0:9b334a45a8ff	237	* in the SPI_InitTypeDef and create the associated handle.
bogdanm	0:9b334a45a8ff	238	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	239	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	240	* @retval HAL status
bogdanm	0:9b334a45a8ff	241	*/
bogdanm	0:9b334a45a8ff	242	__weak HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	243	{
bogdanm	0:9b334a45a8ff	244	/* Check the SPI handle allocation */
bogdanm	0:9b334a45a8ff	245	if(hspi == NULL)
bogdanm	0:9b334a45a8ff	246	{
bogdanm	0:9b334a45a8ff	247	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	248	}
bogdanm	0:9b334a45a8ff	249
bogdanm	0:9b334a45a8ff	250	/* Check the parameters */
bogdanm	0:9b334a45a8ff	251	assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
bogdanm	0:9b334a45a8ff	252	assert_param(IS_SPI_MODE(hspi->Init.Mode));
bogdanm	0:9b334a45a8ff	253	assert_param(IS_SPI_DIRECTION_MODE(hspi->Init.Direction));
bogdanm	0:9b334a45a8ff	254	assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
bogdanm	0:9b334a45a8ff	255	assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
bogdanm	0:9b334a45a8ff	256	assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
bogdanm	0:9b334a45a8ff	257	assert_param(IS_SPI_NSS(hspi->Init.NSS));
bogdanm	0:9b334a45a8ff	258	assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
bogdanm	0:9b334a45a8ff	259	assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
bogdanm	0:9b334a45a8ff	260	assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
bogdanm	0:9b334a45a8ff	261	assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
bogdanm	0:9b334a45a8ff	262	assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
bogdanm	0:9b334a45a8ff	263
bogdanm	0:9b334a45a8ff	264	if(hspi->State == HAL_SPI_STATE_RESET)
bogdanm	0:9b334a45a8ff	265	{
bogdanm	0:9b334a45a8ff	266	/* Allocate lock resource and initialize it */
bogdanm	0:9b334a45a8ff	267	hspi-> Lock = HAL_UNLOCKED;
bogdanm	0:9b334a45a8ff	268
bogdanm	0:9b334a45a8ff	269	/* Init the low level hardware : GPIO, CLOCK, NVIC... */
bogdanm	0:9b334a45a8ff	270	HAL_SPI_MspInit(hspi);
bogdanm	0:9b334a45a8ff	271	}
bogdanm	0:9b334a45a8ff	272
bogdanm	0:9b334a45a8ff	273	hspi->State = HAL_SPI_STATE_BUSY;
bogdanm	0:9b334a45a8ff	274
bogdanm	0:9b334a45a8ff	275	/* Disble the selected SPI peripheral */
bogdanm	0:9b334a45a8ff	276	__HAL_SPI_DISABLE(hspi);
bogdanm	0:9b334a45a8ff	277
bogdanm	0:9b334a45a8ff	278	/----------------------- SPIx CR1 & CR2 Configuration ---------------------/
bogdanm	0:9b334a45a8ff	279	/* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
bogdanm	0:9b334a45a8ff	280	Communication speed, First bit and CRC calculation state */
bogdanm	0:9b334a45a8ff	281	WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode \| hspi->Init.Direction \| hspi->Init.DataSize \|
bogdanm	0:9b334a45a8ff	282	hspi->Init.CLKPolarity \| hspi->Init.CLKPhase \| (hspi->Init.NSS & SPI_CR1_SSM) \|
bogdanm	0:9b334a45a8ff	283	hspi->Init.BaudRatePrescaler \| hspi->Init.FirstBit \| hspi->Init.CRCCalculation) );
bogdanm	0:9b334a45a8ff	284
bogdanm	0:9b334a45a8ff	285	/* Configure : NSS management */
bogdanm	0:9b334a45a8ff	286	WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) \| hspi->Init.TIMode));
bogdanm	0:9b334a45a8ff	287
bogdanm	0:9b334a45a8ff	288	/---------------------------- SPIx CRCPOLY Configuration ------------------/
bogdanm	0:9b334a45a8ff	289	/* Configure : CRC Polynomial */
bogdanm	0:9b334a45a8ff	290	WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
bogdanm	0:9b334a45a8ff	291
bogdanm	0:9b334a45a8ff	292	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	293	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	294
bogdanm	0:9b334a45a8ff	295	return HAL_OK;
bogdanm	0:9b334a45a8ff	296	}
bogdanm	0:9b334a45a8ff	297
bogdanm	0:9b334a45a8ff	298	/**
bogdanm	0:9b334a45a8ff	299	* @brief DeInitializes the SPI peripheral
bogdanm	0:9b334a45a8ff	300	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	301	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	302	* @retval HAL status
bogdanm	0:9b334a45a8ff	303	*/
bogdanm	0:9b334a45a8ff	304	HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	305	{
bogdanm	0:9b334a45a8ff	306	/* Check the SPI handle allocation */
bogdanm	0:9b334a45a8ff	307	if(hspi == NULL)
bogdanm	0:9b334a45a8ff	308	{
bogdanm	0:9b334a45a8ff	309	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	310	}
bogdanm	0:9b334a45a8ff	311
bogdanm	0:9b334a45a8ff	312	hspi->State = HAL_SPI_STATE_BUSY;
bogdanm	0:9b334a45a8ff	313
bogdanm	0:9b334a45a8ff	314	/* Disable the SPI Peripheral Clock */
bogdanm	0:9b334a45a8ff	315	__HAL_SPI_DISABLE(hspi);
bogdanm	0:9b334a45a8ff	316
bogdanm	0:9b334a45a8ff	317	/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
bogdanm	0:9b334a45a8ff	318	HAL_SPI_MspDeInit(hspi);
bogdanm	0:9b334a45a8ff	319
bogdanm	0:9b334a45a8ff	320	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	321	hspi->State = HAL_SPI_STATE_RESET;
bogdanm	0:9b334a45a8ff	322
bogdanm	0:9b334a45a8ff	323	/* Release Lock */
bogdanm	0:9b334a45a8ff	324	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	325
bogdanm	0:9b334a45a8ff	326	return HAL_OK;
bogdanm	0:9b334a45a8ff	327	}
bogdanm	0:9b334a45a8ff	328
bogdanm	0:9b334a45a8ff	329	/**
bogdanm	0:9b334a45a8ff	330	* @brief SPI MSP Init
bogdanm	0:9b334a45a8ff	331	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	332	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	333	* @retval None
bogdanm	0:9b334a45a8ff	334	*/
bogdanm	0:9b334a45a8ff	335	__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	336	{
bogdanm	0:9b334a45a8ff	337	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	338	the HAL_SPI_MspInit could be implenetd in the user file
bogdanm	0:9b334a45a8ff	339	*/
bogdanm	0:9b334a45a8ff	340	}
bogdanm	0:9b334a45a8ff	341
bogdanm	0:9b334a45a8ff	342	/**
bogdanm	0:9b334a45a8ff	343	* @brief SPI MSP DeInit
bogdanm	0:9b334a45a8ff	344	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	345	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	346	* @retval None
bogdanm	0:9b334a45a8ff	347	*/
bogdanm	0:9b334a45a8ff	348	__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	349	{
bogdanm	0:9b334a45a8ff	350	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	351	the HAL_SPI_MspDeInit could be implenetd in the user file
bogdanm	0:9b334a45a8ff	352	*/
bogdanm	0:9b334a45a8ff	353	}
bogdanm	0:9b334a45a8ff	354
bogdanm	0:9b334a45a8ff	355	/**
bogdanm	0:9b334a45a8ff	356	* @}
bogdanm	0:9b334a45a8ff	357	*/
bogdanm	0:9b334a45a8ff	358
bogdanm	0:9b334a45a8ff	359	/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
bogdanm	0:9b334a45a8ff	360	* @brief Data transfers functions
bogdanm	0:9b334a45a8ff	361	*
bogdanm	0:9b334a45a8ff	362	@verbatim
bogdanm	0:9b334a45a8ff	363	==============================================================================
bogdanm	0:9b334a45a8ff	364	##### IO operation functions #####
bogdanm	0:9b334a45a8ff	365	===============================================================================
bogdanm	0:9b334a45a8ff	366	This subsection provides a set of functions allowing to manage the SPI
bogdanm	0:9b334a45a8ff	367	data transfers.
bogdanm	0:9b334a45a8ff	368
bogdanm	0:9b334a45a8ff	369	[..] The SPI supports master and slave mode :
bogdanm	0:9b334a45a8ff	370
bogdanm	0:9b334a45a8ff	371	(#) There are two modes of transfer:
bogdanm	0:9b334a45a8ff	372	(++) Blocking mode: The communication is performed in polling mode.
bogdanm	0:9b334a45a8ff	373	The HAL status of all data processing is returned by the same function
bogdanm	0:9b334a45a8ff	374	after finishing transfer.
bogdanm	0:9b334a45a8ff	375	(++) No-Blocking mode: The communication is performed using Interrupts
bogdanm	0:9b334a45a8ff	376	or DMA, These APIs return the HAL status.
bogdanm	0:9b334a45a8ff	377	The end of the data processing will be indicated through the
bogdanm	0:9b334a45a8ff	378	dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
bogdanm	0:9b334a45a8ff	379	using DMA mode.
bogdanm	0:9b334a45a8ff	380	The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
bogdanm	0:9b334a45a8ff	381	will be executed respectivelly at the end of the transmit or Receive process
bogdanm	0:9b334a45a8ff	382	The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
bogdanm	0:9b334a45a8ff	383
bogdanm	0:9b334a45a8ff	384	(#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
bogdanm	0:9b334a45a8ff	385	exist for 1Line (simplex) and 2Lines (full duplex) modes.
bogdanm	0:9b334a45a8ff	386
bogdanm	0:9b334a45a8ff	387	@endverbatim
bogdanm	0:9b334a45a8ff	388	* @{
bogdanm	0:9b334a45a8ff	389	*/
bogdanm	0:9b334a45a8ff	390
bogdanm	0:9b334a45a8ff	391	/**
bogdanm	0:9b334a45a8ff	392	* @brief Transmit an amount of data in blocking mode
bogdanm	0:9b334a45a8ff	393	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	394	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	395	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	396	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	397	* @param Timeout: Timeout duration
bogdanm	0:9b334a45a8ff	398	* @retval HAL status
bogdanm	0:9b334a45a8ff	399	*/
bogdanm	0:9b334a45a8ff	400	HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	401	{
bogdanm	0:9b334a45a8ff	402
bogdanm	0:9b334a45a8ff	403	if(hspi->State == HAL_SPI_STATE_READY)
bogdanm	0:9b334a45a8ff	404	{
bogdanm	0:9b334a45a8ff	405	if((pData == NULL ) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	406	{
bogdanm	0:9b334a45a8ff	407	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	408	}
bogdanm	0:9b334a45a8ff	409
bogdanm	0:9b334a45a8ff	410	/* Check the parameters */
bogdanm	0:9b334a45a8ff	411	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
bogdanm	0:9b334a45a8ff	412
bogdanm	0:9b334a45a8ff	413	/* Process Locked */
bogdanm	0:9b334a45a8ff	414	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	415
bogdanm	0:9b334a45a8ff	416	/* Configure communication */
bogdanm	0:9b334a45a8ff	417	hspi->State = HAL_SPI_STATE_BUSY_TX;
bogdanm	0:9b334a45a8ff	418	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	419
bogdanm	0:9b334a45a8ff	420	hspi->pTxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	421	hspi->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	422	hspi->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	423
bogdanm	0:9b334a45a8ff	424	/Init field not used in handle to zero /
bogdanm	0:9b334a45a8ff	425	hspi->TxISR = 0;
bogdanm	0:9b334a45a8ff	426	hspi->RxISR = 0;
bogdanm	0:9b334a45a8ff	427	hspi->pRxBuffPtr = NULL;
bogdanm	0:9b334a45a8ff	428	hspi->RxXferSize = 0;
bogdanm	0:9b334a45a8ff	429	hspi->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	430
bogdanm	0:9b334a45a8ff	431	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	432	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	433	{
bogdanm	0:9b334a45a8ff	434	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	435	}
bogdanm	0:9b334a45a8ff	436
bogdanm	0:9b334a45a8ff	437	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
bogdanm	0:9b334a45a8ff	438	{
bogdanm	0:9b334a45a8ff	439	/* Configure communication direction : 1Line */
bogdanm	0:9b334a45a8ff	440	SPI_1LINE_TX(hspi);
bogdanm	0:9b334a45a8ff	441	}
bogdanm	0:9b334a45a8ff	442
bogdanm	0:9b334a45a8ff	443	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	444	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	445	{
bogdanm	0:9b334a45a8ff	446	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	447	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	448	}
bogdanm	0:9b334a45a8ff	449
bogdanm	0:9b334a45a8ff	450	/* Transmit data in 8 Bit mode */
bogdanm	0:9b334a45a8ff	451	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	452	{
bogdanm	0:9b334a45a8ff	453	if((hspi->Init.Mode == SPI_MODE_SLAVE)\|\| (hspi->TxXferCount == 0x01))
bogdanm	0:9b334a45a8ff	454	{
bogdanm	0:9b334a45a8ff	455	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
bogdanm	0:9b334a45a8ff	456	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	457	}
bogdanm	0:9b334a45a8ff	458
bogdanm	0:9b334a45a8ff	459	while(hspi->TxXferCount > 0)
bogdanm	0:9b334a45a8ff	460	{
bogdanm	0:9b334a45a8ff	461	/* Wait until TXE flag is set to send data */
bogdanm	0:9b334a45a8ff	462	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	463	{
bogdanm	0:9b334a45a8ff	464	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	465	}
bogdanm	0:9b334a45a8ff	466	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
bogdanm	0:9b334a45a8ff	467	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	468	}
bogdanm	0:9b334a45a8ff	469	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	470	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	471	{
bogdanm	0:9b334a45a8ff	472	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
bogdanm	0:9b334a45a8ff	473	}
bogdanm	0:9b334a45a8ff	474	}
bogdanm	0:9b334a45a8ff	475	/* Transmit data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	476	else
bogdanm	0:9b334a45a8ff	477	{
bogdanm	0:9b334a45a8ff	478	if((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| (hspi->TxXferCount == 0x01))
bogdanm	0:9b334a45a8ff	479	{
bogdanm	0:9b334a45a8ff	480	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
bogdanm	0:9b334a45a8ff	481	hspi->pTxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	482	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	483	}
bogdanm	0:9b334a45a8ff	484
bogdanm	0:9b334a45a8ff	485	while(hspi->TxXferCount > 0)
bogdanm	0:9b334a45a8ff	486	{
bogdanm	0:9b334a45a8ff	487	/* Wait until TXE flag is set to send data */
bogdanm	0:9b334a45a8ff	488	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	489	{
bogdanm	0:9b334a45a8ff	490	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	491	}
bogdanm	0:9b334a45a8ff	492	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
bogdanm	0:9b334a45a8ff	493	hspi->pTxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	494	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	495	}
bogdanm	0:9b334a45a8ff	496	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	497	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	498	{
bogdanm	0:9b334a45a8ff	499	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
bogdanm	0:9b334a45a8ff	500	}
bogdanm	0:9b334a45a8ff	501	}
bogdanm	0:9b334a45a8ff	502
bogdanm	0:9b334a45a8ff	503	/* Wait until TXE flag is set to send data */
bogdanm	0:9b334a45a8ff	504	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	505	{
bogdanm	0:9b334a45a8ff	506	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
bogdanm	0:9b334a45a8ff	507	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	508	}
bogdanm	0:9b334a45a8ff	509
bogdanm	0:9b334a45a8ff	510	/* Wait until Busy flag is reset before disabling SPI */
bogdanm	0:9b334a45a8ff	511	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	512	{
bogdanm	0:9b334a45a8ff	513	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
bogdanm	0:9b334a45a8ff	514	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	515	}
bogdanm	0:9b334a45a8ff	516
bogdanm	0:9b334a45a8ff	517	/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
bogdanm	0:9b334a45a8ff	518	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
bogdanm	0:9b334a45a8ff	519	{
bogdanm	0:9b334a45a8ff	520	__HAL_SPI_CLEAR_OVRFLAG(hspi);
bogdanm	0:9b334a45a8ff	521	}
bogdanm	0:9b334a45a8ff	522
bogdanm	0:9b334a45a8ff	523	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	524
bogdanm	0:9b334a45a8ff	525	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	526	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	527
bogdanm	0:9b334a45a8ff	528	return HAL_OK;
bogdanm	0:9b334a45a8ff	529	}
bogdanm	0:9b334a45a8ff	530	else
bogdanm	0:9b334a45a8ff	531	{
bogdanm	0:9b334a45a8ff	532	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	533	}
bogdanm	0:9b334a45a8ff	534	}
bogdanm	0:9b334a45a8ff	535
bogdanm	0:9b334a45a8ff	536	/**
bogdanm	0:9b334a45a8ff	537	* @brief Receive an amount of data in blocking mode
bogdanm	0:9b334a45a8ff	538	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	539	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	540	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	541	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	542	* @param Timeout: Timeout duration
bogdanm	0:9b334a45a8ff	543	* @retval HAL status
bogdanm	0:9b334a45a8ff	544	*/
bogdanm	0:9b334a45a8ff	545	HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	546	{
bogdanm	0:9b334a45a8ff	547	__IO uint16_t tmpreg = 0;
bogdanm	0:9b334a45a8ff	548
bogdanm	0:9b334a45a8ff	549	if(hspi->State == HAL_SPI_STATE_READY)
bogdanm	0:9b334a45a8ff	550	{
bogdanm	0:9b334a45a8ff	551	if((pData == NULL ) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	552	{
bogdanm	0:9b334a45a8ff	553	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	554	}
bogdanm	0:9b334a45a8ff	555
bogdanm	0:9b334a45a8ff	556	/* Process Locked */
bogdanm	0:9b334a45a8ff	557	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	558
bogdanm	0:9b334a45a8ff	559	/* Configure communication */
bogdanm	0:9b334a45a8ff	560	hspi->State = HAL_SPI_STATE_BUSY_RX;
bogdanm	0:9b334a45a8ff	561	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	562
bogdanm	0:9b334a45a8ff	563	hspi->pRxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	564	hspi->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	565	hspi->RxXferCount = Size;
bogdanm	0:9b334a45a8ff	566
bogdanm	0:9b334a45a8ff	567	/Init field not used in handle to zero /
bogdanm	0:9b334a45a8ff	568	hspi->RxISR = 0;
bogdanm	0:9b334a45a8ff	569	hspi->TxISR = 0;
bogdanm	0:9b334a45a8ff	570	hspi->pTxBuffPtr = NULL;
bogdanm	0:9b334a45a8ff	571	hspi->TxXferSize = 0;
bogdanm	0:9b334a45a8ff	572	hspi->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	573
bogdanm	0:9b334a45a8ff	574	/* Configure communication direction : 1Line */
bogdanm	0:9b334a45a8ff	575	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
bogdanm	0:9b334a45a8ff	576	{
bogdanm	0:9b334a45a8ff	577	SPI_1LINE_RX(hspi);
bogdanm	0:9b334a45a8ff	578	}
bogdanm	0:9b334a45a8ff	579
bogdanm	0:9b334a45a8ff	580	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	581	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	582	{
bogdanm	0:9b334a45a8ff	583	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	584	}
bogdanm	0:9b334a45a8ff	585
bogdanm	0:9b334a45a8ff	586	if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
bogdanm	0:9b334a45a8ff	587	{
bogdanm	0:9b334a45a8ff	588	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	589	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	590
bogdanm	0:9b334a45a8ff	591	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
bogdanm	0:9b334a45a8ff	592	return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
bogdanm	0:9b334a45a8ff	593	}
bogdanm	0:9b334a45a8ff	594
bogdanm	0:9b334a45a8ff	595	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	596	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	597	{
bogdanm	0:9b334a45a8ff	598	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	599	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	600	}
bogdanm	0:9b334a45a8ff	601
bogdanm	0:9b334a45a8ff	602	/* Receive data in 8 Bit mode */
bogdanm	0:9b334a45a8ff	603	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	604	{
bogdanm	0:9b334a45a8ff	605	while(hspi->RxXferCount > 1)
bogdanm	0:9b334a45a8ff	606	{
bogdanm	0:9b334a45a8ff	607	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	608	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	609	{
bogdanm	0:9b334a45a8ff	610	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	611	}
bogdanm	0:9b334a45a8ff	612
bogdanm	0:9b334a45a8ff	613	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	614	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	615	}
bogdanm	0:9b334a45a8ff	616	/* Enable CRC Reception */
bogdanm	0:9b334a45a8ff	617	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	618	{
bogdanm	0:9b334a45a8ff	619	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
bogdanm	0:9b334a45a8ff	620	}
bogdanm	0:9b334a45a8ff	621	}
bogdanm	0:9b334a45a8ff	622	/* Receive data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	623	else
bogdanm	0:9b334a45a8ff	624	{
bogdanm	0:9b334a45a8ff	625	while(hspi->RxXferCount > 1)
bogdanm	0:9b334a45a8ff	626	{
bogdanm	0:9b334a45a8ff	627	/* Wait until RXNE flag is set to read data */
bogdanm	0:9b334a45a8ff	628	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	629	{
bogdanm	0:9b334a45a8ff	630	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	631	}
bogdanm	0:9b334a45a8ff	632
bogdanm	0:9b334a45a8ff	633	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	634	hspi->pRxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	635	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	636	}
bogdanm	0:9b334a45a8ff	637	/* Enable CRC Reception */
bogdanm	0:9b334a45a8ff	638	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	639	{
bogdanm	0:9b334a45a8ff	640	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
bogdanm	0:9b334a45a8ff	641	}
bogdanm	0:9b334a45a8ff	642	}
bogdanm	0:9b334a45a8ff	643
bogdanm	0:9b334a45a8ff	644	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	645	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	646	{
bogdanm	0:9b334a45a8ff	647	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	648	}
bogdanm	0:9b334a45a8ff	649
bogdanm	0:9b334a45a8ff	650	/* Receive last data in 8 Bit mode */
bogdanm	0:9b334a45a8ff	651	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	652	{
bogdanm	0:9b334a45a8ff	653	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	654	}
bogdanm	0:9b334a45a8ff	655	/* Receive last data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	656	else
bogdanm	0:9b334a45a8ff	657	{
bogdanm	0:9b334a45a8ff	658	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	659	hspi->pRxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	660	}
bogdanm	0:9b334a45a8ff	661	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	662
bogdanm	0:9b334a45a8ff	663	/* If CRC computation is enabled */
bogdanm	0:9b334a45a8ff	664	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	665	{
bogdanm	0:9b334a45a8ff	666	/* Wait until RXNE flag is set: CRC Received */
bogdanm	0:9b334a45a8ff	667	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	668	{
bogdanm	0:9b334a45a8ff	669	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
bogdanm	0:9b334a45a8ff	670	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	671	}
bogdanm	0:9b334a45a8ff	672
bogdanm	0:9b334a45a8ff	673	/* Read CRC to clear RXNE flag */
bogdanm	0:9b334a45a8ff	674	tmpreg = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	675	UNUSED(tmpreg);
bogdanm	0:9b334a45a8ff	676	}
bogdanm	0:9b334a45a8ff	677
bogdanm	0:9b334a45a8ff	678	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
bogdanm	0:9b334a45a8ff	679	{
bogdanm	0:9b334a45a8ff	680	/* Disable SPI peripheral */
bogdanm	0:9b334a45a8ff	681	__HAL_SPI_DISABLE(hspi);
bogdanm	0:9b334a45a8ff	682	}
bogdanm	0:9b334a45a8ff	683
bogdanm	0:9b334a45a8ff	684	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	685
bogdanm	0:9b334a45a8ff	686	/* Check if CRC error occurred */
bogdanm	0:9b334a45a8ff	687	if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET))
bogdanm	0:9b334a45a8ff	688	{
bogdanm	0:9b334a45a8ff	689	/* Check if CRC error is valid or not (workaround to be applied or not) */
bogdanm	0:9b334a45a8ff	690	if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
bogdanm	0:9b334a45a8ff	691	{
bogdanm	0:9b334a45a8ff	692	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
bogdanm	0:9b334a45a8ff	693
bogdanm	0:9b334a45a8ff	694	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	695	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	696
bogdanm	0:9b334a45a8ff	697	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	698	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	699
bogdanm	0:9b334a45a8ff	700	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	701	}
bogdanm	0:9b334a45a8ff	702	else
bogdanm	0:9b334a45a8ff	703	{
bogdanm	0:9b334a45a8ff	704	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
bogdanm	0:9b334a45a8ff	705	}
bogdanm	0:9b334a45a8ff	706	}
bogdanm	0:9b334a45a8ff	707
bogdanm	0:9b334a45a8ff	708	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	709	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	710
bogdanm	0:9b334a45a8ff	711	return HAL_OK;
bogdanm	0:9b334a45a8ff	712	}
bogdanm	0:9b334a45a8ff	713	else
bogdanm	0:9b334a45a8ff	714	{
bogdanm	0:9b334a45a8ff	715	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	716	}
bogdanm	0:9b334a45a8ff	717	}
bogdanm	0:9b334a45a8ff	718
bogdanm	0:9b334a45a8ff	719	/**
bogdanm	0:9b334a45a8ff	720	* @brief Transmit and Receive an amount of data in blocking mode
bogdanm	0:9b334a45a8ff	721	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	722	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	723	* @param pTxData: pointer to transmission data buffer
bogdanm	0:9b334a45a8ff	724	* @param pRxData: pointer to reception data buffer to be
bogdanm	0:9b334a45a8ff	725	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	726	* @param Timeout: Timeout duration
bogdanm	0:9b334a45a8ff	727	* @retval HAL status
bogdanm	0:9b334a45a8ff	728	*/
bogdanm	0:9b334a45a8ff	729	HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	730	{
bogdanm	0:9b334a45a8ff	731	__IO uint16_t tmpreg = 0;
bogdanm	0:9b334a45a8ff	732
bogdanm	0:9b334a45a8ff	733	if((hspi->State == HAL_SPI_STATE_READY) \|\| (hspi->State == HAL_SPI_STATE_BUSY_RX))
bogdanm	0:9b334a45a8ff	734	{
bogdanm	0:9b334a45a8ff	735	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	736	{
bogdanm	0:9b334a45a8ff	737	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	738	}
bogdanm	0:9b334a45a8ff	739
bogdanm	0:9b334a45a8ff	740	/* Check the parameters */
bogdanm	0:9b334a45a8ff	741	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
bogdanm	0:9b334a45a8ff	742
bogdanm	0:9b334a45a8ff	743	/* Process Locked */
bogdanm	0:9b334a45a8ff	744	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	745
bogdanm	0:9b334a45a8ff	746	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
bogdanm	0:9b334a45a8ff	747	if(hspi->State == HAL_SPI_STATE_READY)
bogdanm	0:9b334a45a8ff	748	{
bogdanm	0:9b334a45a8ff	749	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
bogdanm	0:9b334a45a8ff	750	}
bogdanm	0:9b334a45a8ff	751
bogdanm	0:9b334a45a8ff	752	/* Configure communication */
bogdanm	0:9b334a45a8ff	753	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	754
bogdanm	0:9b334a45a8ff	755	hspi->pRxBuffPtr = pRxData;
bogdanm	0:9b334a45a8ff	756	hspi->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	757	hspi->RxXferCount = Size;
bogdanm	0:9b334a45a8ff	758
bogdanm	0:9b334a45a8ff	759	hspi->pTxBuffPtr = pTxData;
bogdanm	0:9b334a45a8ff	760	hspi->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	761	hspi->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	762
bogdanm	0:9b334a45a8ff	763	/Init field not used in handle to zero /
bogdanm	0:9b334a45a8ff	764	hspi->RxISR = 0;
bogdanm	0:9b334a45a8ff	765	hspi->TxISR = 0;
bogdanm	0:9b334a45a8ff	766
bogdanm	0:9b334a45a8ff	767	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	768	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	769	{
bogdanm	0:9b334a45a8ff	770	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	771	}
bogdanm	0:9b334a45a8ff	772
bogdanm	0:9b334a45a8ff	773	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	774	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	775	{
bogdanm	0:9b334a45a8ff	776	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	777	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	778	}
bogdanm	0:9b334a45a8ff	779
bogdanm	0:9b334a45a8ff	780	/* Transmit and Receive data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	781	if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
bogdanm	0:9b334a45a8ff	782	{
bogdanm	0:9b334a45a8ff	783	if((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01)))
bogdanm	0:9b334a45a8ff	784	{
bogdanm	0:9b334a45a8ff	785	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
bogdanm	0:9b334a45a8ff	786	hspi->pTxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	787	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	788	}
bogdanm	0:9b334a45a8ff	789	if(hspi->TxXferCount == 0)
bogdanm	0:9b334a45a8ff	790	{
bogdanm	0:9b334a45a8ff	791	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	792	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	793	{
bogdanm	0:9b334a45a8ff	794	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
bogdanm	0:9b334a45a8ff	795	}
bogdanm	0:9b334a45a8ff	796
bogdanm	0:9b334a45a8ff	797	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	798	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	799	{
bogdanm	0:9b334a45a8ff	800	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	801	}
bogdanm	0:9b334a45a8ff	802
bogdanm	0:9b334a45a8ff	803	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	804	hspi->pRxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	805	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	806	}
bogdanm	0:9b334a45a8ff	807	else
bogdanm	0:9b334a45a8ff	808	{
bogdanm	0:9b334a45a8ff	809	while(hspi->TxXferCount > 0)
bogdanm	0:9b334a45a8ff	810	{
bogdanm	0:9b334a45a8ff	811	/* Wait until TXE flag is set to send data */
bogdanm	0:9b334a45a8ff	812	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	813	{
bogdanm	0:9b334a45a8ff	814	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	815	}
bogdanm	0:9b334a45a8ff	816
bogdanm	0:9b334a45a8ff	817	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
bogdanm	0:9b334a45a8ff	818	hspi->pTxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	819	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	820
bogdanm	0:9b334a45a8ff	821	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	822	if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
bogdanm	0:9b334a45a8ff	823	{
bogdanm	0:9b334a45a8ff	824	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
bogdanm	0:9b334a45a8ff	825	}
bogdanm	0:9b334a45a8ff	826
bogdanm	0:9b334a45a8ff	827	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	828	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	829	{
bogdanm	0:9b334a45a8ff	830	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	831	}
bogdanm	0:9b334a45a8ff	832
bogdanm	0:9b334a45a8ff	833	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	834	hspi->pRxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	835	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	836	}
bogdanm	0:9b334a45a8ff	837	/* Receive the last byte */
bogdanm	0:9b334a45a8ff	838	if(hspi->Init.Mode == SPI_MODE_SLAVE)
bogdanm	0:9b334a45a8ff	839	{
bogdanm	0:9b334a45a8ff	840	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	841	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	842	{
bogdanm	0:9b334a45a8ff	843	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	844	}
bogdanm	0:9b334a45a8ff	845
bogdanm	0:9b334a45a8ff	846	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	847	hspi->pRxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	848	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	849	}
bogdanm	0:9b334a45a8ff	850	}
bogdanm	0:9b334a45a8ff	851	}
bogdanm	0:9b334a45a8ff	852	/* Transmit and Receive data in 8 Bit mode */
bogdanm	0:9b334a45a8ff	853	else
bogdanm	0:9b334a45a8ff	854	{
bogdanm	0:9b334a45a8ff	855	if((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01)))
bogdanm	0:9b334a45a8ff	856	{
bogdanm	0:9b334a45a8ff	857	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
bogdanm	0:9b334a45a8ff	858	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	859	}
bogdanm	0:9b334a45a8ff	860	if(hspi->TxXferCount == 0)
bogdanm	0:9b334a45a8ff	861	{
bogdanm	0:9b334a45a8ff	862	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	863	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	864	{
bogdanm	0:9b334a45a8ff	865	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
bogdanm	0:9b334a45a8ff	866	}
bogdanm	0:9b334a45a8ff	867
bogdanm	0:9b334a45a8ff	868	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	869	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	870	{
bogdanm	0:9b334a45a8ff	871	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	872	}
bogdanm	0:9b334a45a8ff	873
bogdanm	0:9b334a45a8ff	874	(*hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	875	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	876	}
bogdanm	0:9b334a45a8ff	877	else
bogdanm	0:9b334a45a8ff	878	{
bogdanm	0:9b334a45a8ff	879	while(hspi->TxXferCount > 0)
bogdanm	0:9b334a45a8ff	880	{
bogdanm	0:9b334a45a8ff	881	/* Wait until TXE flag is set to send data */
bogdanm	0:9b334a45a8ff	882	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	883	{
bogdanm	0:9b334a45a8ff	884	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	885	}
bogdanm	0:9b334a45a8ff	886
bogdanm	0:9b334a45a8ff	887	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
bogdanm	0:9b334a45a8ff	888	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	889
bogdanm	0:9b334a45a8ff	890	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	891	if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
bogdanm	0:9b334a45a8ff	892	{
bogdanm	0:9b334a45a8ff	893	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
bogdanm	0:9b334a45a8ff	894	}
bogdanm	0:9b334a45a8ff	895
bogdanm	0:9b334a45a8ff	896	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	897	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	898	{
bogdanm	0:9b334a45a8ff	899	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	900	}
bogdanm	0:9b334a45a8ff	901
bogdanm	0:9b334a45a8ff	902	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	903	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	904	}
bogdanm	0:9b334a45a8ff	905	if(hspi->Init.Mode == SPI_MODE_SLAVE)
bogdanm	0:9b334a45a8ff	906	{
bogdanm	0:9b334a45a8ff	907	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	908	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	909	{
bogdanm	0:9b334a45a8ff	910	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	911	}
bogdanm	0:9b334a45a8ff	912
bogdanm	0:9b334a45a8ff	913	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	914	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	915	}
bogdanm	0:9b334a45a8ff	916	}
bogdanm	0:9b334a45a8ff	917	}
bogdanm	0:9b334a45a8ff	918
bogdanm	0:9b334a45a8ff	919	/* Read CRC from DR to close CRC calculation process */
bogdanm	0:9b334a45a8ff	920	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	921	{
bogdanm	0:9b334a45a8ff	922	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	923	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	924	{
bogdanm	0:9b334a45a8ff	925	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
bogdanm	0:9b334a45a8ff	926	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	927	}
bogdanm	0:9b334a45a8ff	928	/* Read CRC */
bogdanm	0:9b334a45a8ff	929	tmpreg = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	930	UNUSED(tmpreg);
bogdanm	0:9b334a45a8ff	931	}
bogdanm	0:9b334a45a8ff	932
bogdanm	0:9b334a45a8ff	933	/* Wait until Busy flag is reset before disabling SPI */
bogdanm	0:9b334a45a8ff	934	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	935	{
bogdanm	0:9b334a45a8ff	936	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
bogdanm	0:9b334a45a8ff	937	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	938	}
bogdanm	0:9b334a45a8ff	939
bogdanm	0:9b334a45a8ff	940	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	941
bogdanm	0:9b334a45a8ff	942	/* Check if CRC error occurred */
bogdanm	0:9b334a45a8ff	943	if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET))
bogdanm	0:9b334a45a8ff	944	{
bogdanm	0:9b334a45a8ff	945	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
bogdanm	0:9b334a45a8ff	946
bogdanm	0:9b334a45a8ff	947	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	948
bogdanm	0:9b334a45a8ff	949	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	950	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	951
bogdanm	0:9b334a45a8ff	952	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	953	}
bogdanm	0:9b334a45a8ff	954
bogdanm	0:9b334a45a8ff	955	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	956	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	957
bogdanm	0:9b334a45a8ff	958	return HAL_OK;
bogdanm	0:9b334a45a8ff	959	}
bogdanm	0:9b334a45a8ff	960	else
bogdanm	0:9b334a45a8ff	961	{
bogdanm	0:9b334a45a8ff	962	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	963	}
bogdanm	0:9b334a45a8ff	964	}
bogdanm	0:9b334a45a8ff	965
bogdanm	0:9b334a45a8ff	966	/**
bogdanm	0:9b334a45a8ff	967	* @brief Transmit an amount of data in no-blocking mode with Interrupt
bogdanm	0:9b334a45a8ff	968	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	969	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	970	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	971	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	972	* @retval HAL status
bogdanm	0:9b334a45a8ff	973	*/
bogdanm	0:9b334a45a8ff	974	HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
bogdanm	0:9b334a45a8ff	975	{
bogdanm	0:9b334a45a8ff	976	if(hspi->State == HAL_SPI_STATE_READY)
bogdanm	0:9b334a45a8ff	977	{
bogdanm	0:9b334a45a8ff	978	if((pData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	979	{
bogdanm	0:9b334a45a8ff	980	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	981	}
bogdanm	0:9b334a45a8ff	982
bogdanm	0:9b334a45a8ff	983	/* Check the parameters */
bogdanm	0:9b334a45a8ff	984	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
bogdanm	0:9b334a45a8ff	985
bogdanm	0:9b334a45a8ff	986	/* Process Locked */
bogdanm	0:9b334a45a8ff	987	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	988
bogdanm	0:9b334a45a8ff	989	/* Configure communication */
bogdanm	0:9b334a45a8ff	990	hspi->State = HAL_SPI_STATE_BUSY_TX;
bogdanm	0:9b334a45a8ff	991	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	992
bogdanm	0:9b334a45a8ff	993	hspi->TxISR = &SPI_TxISR;
bogdanm	0:9b334a45a8ff	994	hspi->pTxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	995	hspi->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	996	hspi->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	997
bogdanm	0:9b334a45a8ff	998	/Init field not used in handle to zero /
bogdanm	0:9b334a45a8ff	999	hspi->RxISR = 0;
bogdanm	0:9b334a45a8ff	1000	hspi->pRxBuffPtr = NULL;
bogdanm	0:9b334a45a8ff	1001	hspi->RxXferSize = 0;
bogdanm	0:9b334a45a8ff	1002	hspi->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	1003
bogdanm	0:9b334a45a8ff	1004	/* Configure communication direction : 1Line */
bogdanm	0:9b334a45a8ff	1005	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
bogdanm	0:9b334a45a8ff	1006	{
bogdanm	0:9b334a45a8ff	1007	SPI_1LINE_TX(hspi);
bogdanm	0:9b334a45a8ff	1008	}
bogdanm	0:9b334a45a8ff	1009
bogdanm	0:9b334a45a8ff	1010	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	1011	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1012	{
bogdanm	0:9b334a45a8ff	1013	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	1014	}
bogdanm	0:9b334a45a8ff	1015
bogdanm	0:9b334a45a8ff	1016	if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
bogdanm	0:9b334a45a8ff	1017	{
bogdanm	0:9b334a45a8ff	1018	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE));
bogdanm	0:9b334a45a8ff	1019	}
bogdanm	0:9b334a45a8ff	1020	else
bogdanm	0:9b334a45a8ff	1021	{
bogdanm	0:9b334a45a8ff	1022	/* Enable TXE and ERR interrupt */
bogdanm	0:9b334a45a8ff	1023	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_ERR));
bogdanm	0:9b334a45a8ff	1024	}
bogdanm	0:9b334a45a8ff	1025	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1026	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1027
bogdanm	0:9b334a45a8ff	1028	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	1029	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	1030	{
bogdanm	0:9b334a45a8ff	1031	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	1032	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	1033	}
bogdanm	0:9b334a45a8ff	1034
bogdanm	0:9b334a45a8ff	1035	return HAL_OK;
bogdanm	0:9b334a45a8ff	1036	}
bogdanm	0:9b334a45a8ff	1037	else
bogdanm	0:9b334a45a8ff	1038	{
bogdanm	0:9b334a45a8ff	1039	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1040	}
bogdanm	0:9b334a45a8ff	1041	}
bogdanm	0:9b334a45a8ff	1042
bogdanm	0:9b334a45a8ff	1043	/**
bogdanm	0:9b334a45a8ff	1044	* @brief Receive an amount of data in no-blocking mode with Interrupt
bogdanm	0:9b334a45a8ff	1045	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1046	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1047	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	1048	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	1049	* @retval HAL status
bogdanm	0:9b334a45a8ff	1050	*/
bogdanm	0:9b334a45a8ff	1051	HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
bogdanm	0:9b334a45a8ff	1052	{
bogdanm	0:9b334a45a8ff	1053	if(hspi->State == HAL_SPI_STATE_READY)
bogdanm	0:9b334a45a8ff	1054	{
bogdanm	0:9b334a45a8ff	1055	if((pData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	1056	{
bogdanm	0:9b334a45a8ff	1057	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1058	}
bogdanm	0:9b334a45a8ff	1059
bogdanm	0:9b334a45a8ff	1060	/* Process Locked */
bogdanm	0:9b334a45a8ff	1061	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	1062
bogdanm	0:9b334a45a8ff	1063	/* Configure communication */
bogdanm	0:9b334a45a8ff	1064	hspi->State = HAL_SPI_STATE_BUSY_RX;
bogdanm	0:9b334a45a8ff	1065	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1066
bogdanm	0:9b334a45a8ff	1067	hspi->RxISR = &SPI_RxISR;
bogdanm	0:9b334a45a8ff	1068	hspi->pRxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	1069	hspi->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	1070	hspi->RxXferCount = Size ;
bogdanm	0:9b334a45a8ff	1071
bogdanm	0:9b334a45a8ff	1072	/Init field not used in handle to zero /
bogdanm	0:9b334a45a8ff	1073	hspi->TxISR = 0;
bogdanm	0:9b334a45a8ff	1074	hspi->pTxBuffPtr = NULL;
bogdanm	0:9b334a45a8ff	1075	hspi->TxXferSize = 0;
bogdanm	0:9b334a45a8ff	1076	hspi->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	1077
bogdanm	0:9b334a45a8ff	1078	/* Configure communication direction : 1Line */
bogdanm	0:9b334a45a8ff	1079	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
bogdanm	0:9b334a45a8ff	1080	{
bogdanm	0:9b334a45a8ff	1081	SPI_1LINE_RX(hspi);
bogdanm	0:9b334a45a8ff	1082	}
bogdanm	0:9b334a45a8ff	1083	else if((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
bogdanm	0:9b334a45a8ff	1084	{
bogdanm	0:9b334a45a8ff	1085	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1086	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1087
bogdanm	0:9b334a45a8ff	1088	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
bogdanm	0:9b334a45a8ff	1089	return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
bogdanm	0:9b334a45a8ff	1090	}
bogdanm	0:9b334a45a8ff	1091
bogdanm	0:9b334a45a8ff	1092	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	1093	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1094	{
bogdanm	0:9b334a45a8ff	1095	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	1096	}
bogdanm	0:9b334a45a8ff	1097
bogdanm	0:9b334a45a8ff	1098	/* Enable TXE and ERR interrupt */
bogdanm	0:9b334a45a8ff	1099	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
bogdanm	0:9b334a45a8ff	1100
bogdanm	0:9b334a45a8ff	1101	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1102	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1103
bogdanm	0:9b334a45a8ff	1104	/* Note : The SPI must be enabled after unlocking current process
bogdanm	0:9b334a45a8ff	1105	to avoid the risk of SPI interrupt handle execution before current
bogdanm	0:9b334a45a8ff	1106	process unlock */
bogdanm	0:9b334a45a8ff	1107
bogdanm	0:9b334a45a8ff	1108	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	1109	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	1110	{
bogdanm	0:9b334a45a8ff	1111	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	1112	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	1113	}
bogdanm	0:9b334a45a8ff	1114
bogdanm	0:9b334a45a8ff	1115	return HAL_OK;
bogdanm	0:9b334a45a8ff	1116	}
bogdanm	0:9b334a45a8ff	1117	else
bogdanm	0:9b334a45a8ff	1118	{
bogdanm	0:9b334a45a8ff	1119	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1120	}
bogdanm	0:9b334a45a8ff	1121	}
bogdanm	0:9b334a45a8ff	1122
bogdanm	0:9b334a45a8ff	1123	/**
bogdanm	0:9b334a45a8ff	1124	* @brief Transmit and Receive an amount of data in no-blocking mode with Interrupt
bogdanm	0:9b334a45a8ff	1125	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1126	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1127	* @param pTxData: pointer to transmission data buffer
bogdanm	0:9b334a45a8ff	1128	* @param pRxData: pointer to reception data buffer to be
bogdanm	0:9b334a45a8ff	1129	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	1130	* @retval HAL status
bogdanm	0:9b334a45a8ff	1131	*/
bogdanm	0:9b334a45a8ff	1132	HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
bogdanm	0:9b334a45a8ff	1133	{
bogdanm	0:9b334a45a8ff	1134
bogdanm	0:9b334a45a8ff	1135	if((hspi->State == HAL_SPI_STATE_READY) \|\| \
bogdanm	0:9b334a45a8ff	1136	((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
bogdanm	0:9b334a45a8ff	1137	{
bogdanm	0:9b334a45a8ff	1138	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	1139	{
bogdanm	0:9b334a45a8ff	1140	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1141	}
bogdanm	0:9b334a45a8ff	1142
bogdanm	0:9b334a45a8ff	1143	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1144	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
bogdanm	0:9b334a45a8ff	1145
bogdanm	0:9b334a45a8ff	1146	/* Process locked */
bogdanm	0:9b334a45a8ff	1147	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	1148
bogdanm	0:9b334a45a8ff	1149	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
bogdanm	0:9b334a45a8ff	1150	if(hspi->State != HAL_SPI_STATE_BUSY_RX)
bogdanm	0:9b334a45a8ff	1151	{
bogdanm	0:9b334a45a8ff	1152	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
bogdanm	0:9b334a45a8ff	1153	}
bogdanm	0:9b334a45a8ff	1154
bogdanm	0:9b334a45a8ff	1155	/* Configure communication */
bogdanm	0:9b334a45a8ff	1156	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1157
bogdanm	0:9b334a45a8ff	1158	hspi->TxISR = &SPI_TxISR;
bogdanm	0:9b334a45a8ff	1159	hspi->pTxBuffPtr = pTxData;
bogdanm	0:9b334a45a8ff	1160	hspi->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	1161	hspi->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	1162
bogdanm	0:9b334a45a8ff	1163	hspi->RxISR = &SPI_2LinesRxISR;
bogdanm	0:9b334a45a8ff	1164	hspi->pRxBuffPtr = pRxData;
bogdanm	0:9b334a45a8ff	1165	hspi->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	1166	hspi->RxXferCount = Size;
bogdanm	0:9b334a45a8ff	1167
bogdanm	0:9b334a45a8ff	1168	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	1169	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1170	{
bogdanm	0:9b334a45a8ff	1171	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	1172	}
bogdanm	0:9b334a45a8ff	1173
bogdanm	0:9b334a45a8ff	1174	/* Enable TXE, RXNE and ERR interrupt */
bogdanm	0:9b334a45a8ff	1175	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
bogdanm	0:9b334a45a8ff	1176
bogdanm	0:9b334a45a8ff	1177	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1178	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1179
bogdanm	0:9b334a45a8ff	1180	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	1181	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	1182	{
bogdanm	0:9b334a45a8ff	1183	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	1184	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	1185	}
bogdanm	0:9b334a45a8ff	1186
bogdanm	0:9b334a45a8ff	1187	return HAL_OK;
bogdanm	0:9b334a45a8ff	1188	}
bogdanm	0:9b334a45a8ff	1189	else
bogdanm	0:9b334a45a8ff	1190	{
bogdanm	0:9b334a45a8ff	1191	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1192	}
bogdanm	0:9b334a45a8ff	1193	}
bogdanm	0:9b334a45a8ff	1194
bogdanm	0:9b334a45a8ff	1195	/**
bogdanm	0:9b334a45a8ff	1196	* @brief Transmit an amount of data in no-blocking mode with DMA
bogdanm	0:9b334a45a8ff	1197	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1198	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1199	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	1200	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	1201	* @retval HAL status
bogdanm	0:9b334a45a8ff	1202	*/
bogdanm	0:9b334a45a8ff	1203	HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
bogdanm	0:9b334a45a8ff	1204	{
bogdanm	0:9b334a45a8ff	1205	if(hspi->State == HAL_SPI_STATE_READY)
bogdanm	0:9b334a45a8ff	1206	{
bogdanm	0:9b334a45a8ff	1207	if((pData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	1208	{
bogdanm	0:9b334a45a8ff	1209	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1210	}
bogdanm	0:9b334a45a8ff	1211
bogdanm	0:9b334a45a8ff	1212	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1213	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
bogdanm	0:9b334a45a8ff	1214
bogdanm	0:9b334a45a8ff	1215	/* Process Locked */
bogdanm	0:9b334a45a8ff	1216	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	1217
bogdanm	0:9b334a45a8ff	1218	/* Configure communication */
bogdanm	0:9b334a45a8ff	1219	hspi->State = HAL_SPI_STATE_BUSY_TX;
bogdanm	0:9b334a45a8ff	1220	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1221
bogdanm	0:9b334a45a8ff	1222	hspi->pTxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	1223	hspi->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	1224	hspi->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	1225
bogdanm	0:9b334a45a8ff	1226	/Init field not used in handle to zero /
bogdanm	0:9b334a45a8ff	1227	hspi->TxISR = 0;
bogdanm	0:9b334a45a8ff	1228	hspi->RxISR = 0;
bogdanm	0:9b334a45a8ff	1229	hspi->pRxBuffPtr = NULL;
bogdanm	0:9b334a45a8ff	1230	hspi->RxXferSize = 0;
bogdanm	0:9b334a45a8ff	1231	hspi->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	1232
bogdanm	0:9b334a45a8ff	1233	/* Configure communication direction : 1Line */
bogdanm	0:9b334a45a8ff	1234	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
bogdanm	0:9b334a45a8ff	1235	{
bogdanm	0:9b334a45a8ff	1236	SPI_1LINE_TX(hspi);
bogdanm	0:9b334a45a8ff	1237	}
bogdanm	0:9b334a45a8ff	1238
bogdanm	0:9b334a45a8ff	1239	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	1240	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1241	{
bogdanm	0:9b334a45a8ff	1242	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	1243	}
bogdanm	0:9b334a45a8ff	1244
bogdanm	0:9b334a45a8ff	1245	/* Set the SPI TxDMA Half transfer complete callback */
bogdanm	0:9b334a45a8ff	1246	hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
bogdanm	0:9b334a45a8ff	1247
bogdanm	0:9b334a45a8ff	1248	/* Set the SPI TxDMA transfer complete callback */
bogdanm	0:9b334a45a8ff	1249	hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
bogdanm	0:9b334a45a8ff	1250
bogdanm	0:9b334a45a8ff	1251	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1252	hspi->hdmatx->XferErrorCallback = SPI_DMAError;
bogdanm	0:9b334a45a8ff	1253
bogdanm	0:9b334a45a8ff	1254	/* Reset content of SPI RxDMA descriptor */
bogdanm	0:9b334a45a8ff	1255	hspi->hdmarx->XferHalfCpltCallback = 0;
bogdanm	0:9b334a45a8ff	1256	hspi->hdmarx->XferCpltCallback = 0;
bogdanm	0:9b334a45a8ff	1257	hspi->hdmarx->XferErrorCallback = 0;
bogdanm	0:9b334a45a8ff	1258
bogdanm	0:9b334a45a8ff	1259	/* Enable the Tx DMA Channel */
bogdanm	0:9b334a45a8ff	1260	HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
bogdanm	0:9b334a45a8ff	1261
bogdanm	0:9b334a45a8ff	1262	/* Enable Tx DMA Request */
bogdanm	0:9b334a45a8ff	1263	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	1264
bogdanm	0:9b334a45a8ff	1265	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1266	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1267
bogdanm	0:9b334a45a8ff	1268	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	1269	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	1270	{
bogdanm	0:9b334a45a8ff	1271	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	1272	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	1273	}
bogdanm	0:9b334a45a8ff	1274
bogdanm	0:9b334a45a8ff	1275	return HAL_OK;
bogdanm	0:9b334a45a8ff	1276	}
bogdanm	0:9b334a45a8ff	1277	else
bogdanm	0:9b334a45a8ff	1278	{
bogdanm	0:9b334a45a8ff	1279	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1280	}
bogdanm	0:9b334a45a8ff	1281	}
bogdanm	0:9b334a45a8ff	1282
bogdanm	0:9b334a45a8ff	1283	/**
bogdanm	0:9b334a45a8ff	1284	* @brief Receive an amount of data in no-blocking mode with DMA
bogdanm	0:9b334a45a8ff	1285	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1286	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1287	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	1288	* @note When the CRC feature is enabled the pData Length must be Size + 1.
bogdanm	0:9b334a45a8ff	1289	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	1290	* @retval HAL status
bogdanm	0:9b334a45a8ff	1291	*/
bogdanm	0:9b334a45a8ff	1292	HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
bogdanm	0:9b334a45a8ff	1293	{
bogdanm	0:9b334a45a8ff	1294	if(hspi->State == HAL_SPI_STATE_READY)
bogdanm	0:9b334a45a8ff	1295	{
bogdanm	0:9b334a45a8ff	1296	if((pData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	1297	{
bogdanm	0:9b334a45a8ff	1298	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1299	}
bogdanm	0:9b334a45a8ff	1300
bogdanm	0:9b334a45a8ff	1301	/* Process Locked */
bogdanm	0:9b334a45a8ff	1302	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	1303
bogdanm	0:9b334a45a8ff	1304	/* Configure communication */
bogdanm	0:9b334a45a8ff	1305	hspi->State = HAL_SPI_STATE_BUSY_RX;
bogdanm	0:9b334a45a8ff	1306	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1307
bogdanm	0:9b334a45a8ff	1308	hspi->pRxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	1309	hspi->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	1310	hspi->RxXferCount = Size;
bogdanm	0:9b334a45a8ff	1311
bogdanm	0:9b334a45a8ff	1312	/Init field not used in handle to zero /
bogdanm	0:9b334a45a8ff	1313	hspi->RxISR = 0;
bogdanm	0:9b334a45a8ff	1314	hspi->TxISR = 0;
bogdanm	0:9b334a45a8ff	1315	hspi->pTxBuffPtr = NULL;
bogdanm	0:9b334a45a8ff	1316	hspi->TxXferSize = 0;
bogdanm	0:9b334a45a8ff	1317	hspi->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	1318
bogdanm	0:9b334a45a8ff	1319	/* Configure communication direction : 1Line */
bogdanm	0:9b334a45a8ff	1320	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
bogdanm	0:9b334a45a8ff	1321	{
bogdanm	0:9b334a45a8ff	1322	SPI_1LINE_RX(hspi);
bogdanm	0:9b334a45a8ff	1323	}
bogdanm	0:9b334a45a8ff	1324	else if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER))
bogdanm	0:9b334a45a8ff	1325	{
bogdanm	0:9b334a45a8ff	1326	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1327	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1328
bogdanm	0:9b334a45a8ff	1329	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
bogdanm	0:9b334a45a8ff	1330	return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
bogdanm	0:9b334a45a8ff	1331	}
bogdanm	0:9b334a45a8ff	1332
bogdanm	0:9b334a45a8ff	1333	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	1334	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1335	{
bogdanm	0:9b334a45a8ff	1336	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	1337	}
bogdanm	0:9b334a45a8ff	1338
bogdanm	0:9b334a45a8ff	1339	/* Set the SPI RxDMA Half transfer complete callback */
bogdanm	0:9b334a45a8ff	1340	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
bogdanm	0:9b334a45a8ff	1341
bogdanm	0:9b334a45a8ff	1342	/* Set the SPI Rx DMA transfer complete callback */
bogdanm	0:9b334a45a8ff	1343	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
bogdanm	0:9b334a45a8ff	1344
bogdanm	0:9b334a45a8ff	1345	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1346	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
bogdanm	0:9b334a45a8ff	1347
bogdanm	0:9b334a45a8ff	1348	/* Reset content of SPI TxDMA descriptor */
bogdanm	0:9b334a45a8ff	1349	hspi->hdmatx->XferHalfCpltCallback = 0;
bogdanm	0:9b334a45a8ff	1350	hspi->hdmatx->XferCpltCallback = 0;
bogdanm	0:9b334a45a8ff	1351	hspi->hdmatx->XferErrorCallback = 0;
bogdanm	0:9b334a45a8ff	1352
bogdanm	0:9b334a45a8ff	1353	/* Enable the Rx DMA Channel */
bogdanm	0:9b334a45a8ff	1354	HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
bogdanm	0:9b334a45a8ff	1355
bogdanm	0:9b334a45a8ff	1356	/* Enable Rx DMA Request */
bogdanm	0:9b334a45a8ff	1357	SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	1358
bogdanm	0:9b334a45a8ff	1359	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1360	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1361
bogdanm	0:9b334a45a8ff	1362	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	1363	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	1364	{
bogdanm	0:9b334a45a8ff	1365	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	1366	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	1367	}
bogdanm	0:9b334a45a8ff	1368
bogdanm	0:9b334a45a8ff	1369	return HAL_OK;
bogdanm	0:9b334a45a8ff	1370	}
bogdanm	0:9b334a45a8ff	1371	else
bogdanm	0:9b334a45a8ff	1372	{
bogdanm	0:9b334a45a8ff	1373	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1374	}
bogdanm	0:9b334a45a8ff	1375	}
bogdanm	0:9b334a45a8ff	1376
bogdanm	0:9b334a45a8ff	1377	/**
bogdanm	0:9b334a45a8ff	1378	* @brief Transmit and Receive an amount of data in no-blocking mode with DMA
bogdanm	0:9b334a45a8ff	1379	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1380	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1381	* @param pTxData: pointer to transmission data buffer
bogdanm	0:9b334a45a8ff	1382	* @param pRxData: pointer to reception data buffer
bogdanm	0:9b334a45a8ff	1383	* @note When the CRC feature is enabled the pRxData Length must be Size + 1
bogdanm	0:9b334a45a8ff	1384	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	1385	* @retval HAL status
bogdanm	0:9b334a45a8ff	1386	*/
bogdanm	0:9b334a45a8ff	1387	HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
bogdanm	0:9b334a45a8ff	1388	{
bogdanm	0:9b334a45a8ff	1389	if((hspi->State == HAL_SPI_STATE_READY) \|\| \
bogdanm	0:9b334a45a8ff	1390	((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
bogdanm	0:9b334a45a8ff	1391	{
bogdanm	0:9b334a45a8ff	1392	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	1393	{
bogdanm	0:9b334a45a8ff	1394	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1395	}
bogdanm	0:9b334a45a8ff	1396
bogdanm	0:9b334a45a8ff	1397	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1398	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
bogdanm	0:9b334a45a8ff	1399
bogdanm	0:9b334a45a8ff	1400	/* Process locked */
bogdanm	0:9b334a45a8ff	1401	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	1402
bogdanm	0:9b334a45a8ff	1403	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
bogdanm	0:9b334a45a8ff	1404	if(hspi->State != HAL_SPI_STATE_BUSY_RX)
bogdanm	0:9b334a45a8ff	1405	{
bogdanm	0:9b334a45a8ff	1406	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
bogdanm	0:9b334a45a8ff	1407	}
bogdanm	0:9b334a45a8ff	1408
bogdanm	0:9b334a45a8ff	1409	/* Configure communication */
bogdanm	0:9b334a45a8ff	1410	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1411
bogdanm	0:9b334a45a8ff	1412	hspi->pTxBuffPtr = (uint8_t*)pTxData;
bogdanm	0:9b334a45a8ff	1413	hspi->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	1414	hspi->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	1415
bogdanm	0:9b334a45a8ff	1416	hspi->pRxBuffPtr = (uint8_t*)pRxData;
bogdanm	0:9b334a45a8ff	1417	hspi->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	1418	hspi->RxXferCount = Size;
bogdanm	0:9b334a45a8ff	1419
bogdanm	0:9b334a45a8ff	1420	/Init field not used in handle to zero /
bogdanm	0:9b334a45a8ff	1421	hspi->RxISR = 0;
bogdanm	0:9b334a45a8ff	1422	hspi->TxISR = 0;
bogdanm	0:9b334a45a8ff	1423
bogdanm	0:9b334a45a8ff	1424	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	1425	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1426	{
bogdanm	0:9b334a45a8ff	1427	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	1428	}
bogdanm	0:9b334a45a8ff	1429
bogdanm	0:9b334a45a8ff	1430	/* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
bogdanm	0:9b334a45a8ff	1431	if(hspi->State == HAL_SPI_STATE_BUSY_RX)
bogdanm	0:9b334a45a8ff	1432	{
bogdanm	0:9b334a45a8ff	1433	/* Set the SPI Rx DMA Half transfer complete callback */
bogdanm	0:9b334a45a8ff	1434	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
bogdanm	0:9b334a45a8ff	1435
bogdanm	0:9b334a45a8ff	1436	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
bogdanm	0:9b334a45a8ff	1437	}
bogdanm	0:9b334a45a8ff	1438	else
bogdanm	0:9b334a45a8ff	1439	{
bogdanm	0:9b334a45a8ff	1440	/* Set the SPI Tx/Rx DMA Half transfer complete callback */
bogdanm	0:9b334a45a8ff	1441	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
bogdanm	0:9b334a45a8ff	1442
bogdanm	0:9b334a45a8ff	1443	hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
bogdanm	0:9b334a45a8ff	1444	}
bogdanm	0:9b334a45a8ff	1445
bogdanm	0:9b334a45a8ff	1446	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1447	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
bogdanm	0:9b334a45a8ff	1448
bogdanm	0:9b334a45a8ff	1449	/* Enable the Rx DMA Channel */
bogdanm	0:9b334a45a8ff	1450	HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
bogdanm	0:9b334a45a8ff	1451
bogdanm	0:9b334a45a8ff	1452	/* Enable Rx DMA Request */
bogdanm	0:9b334a45a8ff	1453	SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	1454
bogdanm	0:9b334a45a8ff	1455	/* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
bogdanm	0:9b334a45a8ff	1456	is performed in DMA reception complete callback */
bogdanm	0:9b334a45a8ff	1457	if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
bogdanm	0:9b334a45a8ff	1458	{
bogdanm	0:9b334a45a8ff	1459	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1460	hspi->hdmatx->XferErrorCallback = SPI_DMAError;
bogdanm	0:9b334a45a8ff	1461	}
bogdanm	0:9b334a45a8ff	1462	else
bogdanm	0:9b334a45a8ff	1463	{
bogdanm	0:9b334a45a8ff	1464	hspi->hdmatx->XferErrorCallback = NULL;
bogdanm	0:9b334a45a8ff	1465	}
bogdanm	0:9b334a45a8ff	1466
bogdanm	0:9b334a45a8ff	1467	/* Enable the Tx DMA Channel */
bogdanm	0:9b334a45a8ff	1468	HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
bogdanm	0:9b334a45a8ff	1469
bogdanm	0:9b334a45a8ff	1470	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	1471	if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	1472	{
bogdanm	0:9b334a45a8ff	1473	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	1474	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	1475	}
bogdanm	0:9b334a45a8ff	1476
bogdanm	0:9b334a45a8ff	1477	/* Enable Tx DMA Request */
bogdanm	0:9b334a45a8ff	1478	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	1479
bogdanm	0:9b334a45a8ff	1480	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1481	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1482
bogdanm	0:9b334a45a8ff	1483	return HAL_OK;
bogdanm	0:9b334a45a8ff	1484	}
bogdanm	0:9b334a45a8ff	1485	else
bogdanm	0:9b334a45a8ff	1486	{
bogdanm	0:9b334a45a8ff	1487	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1488	}
bogdanm	0:9b334a45a8ff	1489	}
bogdanm	0:9b334a45a8ff	1490
bogdanm	0:9b334a45a8ff	1491
bogdanm	0:9b334a45a8ff	1492	/**
bogdanm	0:9b334a45a8ff	1493	* @brief Pauses the DMA Transfer.
bogdanm	0:9b334a45a8ff	1494	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1495	* the configuration information for the specified SPI module.
bogdanm	0:9b334a45a8ff	1496	* @retval HAL status
bogdanm	0:9b334a45a8ff	1497	*/
bogdanm	0:9b334a45a8ff	1498	HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1499	{
bogdanm	0:9b334a45a8ff	1500	/* Process Locked */
bogdanm	0:9b334a45a8ff	1501	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	1502
bogdanm	0:9b334a45a8ff	1503	/* Disable the SPI DMA Tx & Rx requests */
bogdanm	0:9b334a45a8ff	1504	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	1505	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	1506
bogdanm	0:9b334a45a8ff	1507	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1508	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1509
bogdanm	0:9b334a45a8ff	1510	return HAL_OK;
bogdanm	0:9b334a45a8ff	1511	}
bogdanm	0:9b334a45a8ff	1512
bogdanm	0:9b334a45a8ff	1513	/**
bogdanm	0:9b334a45a8ff	1514	* @brief Resumes the DMA Transfer.
bogdanm	0:9b334a45a8ff	1515	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1516	* the configuration information for the specified SPI module.
bogdanm	0:9b334a45a8ff	1517	* @retval HAL status
bogdanm	0:9b334a45a8ff	1518	*/
bogdanm	0:9b334a45a8ff	1519	HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1520	{
bogdanm	0:9b334a45a8ff	1521	/* Process Locked */
bogdanm	0:9b334a45a8ff	1522	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	1523
bogdanm	0:9b334a45a8ff	1524	/* Enable the SPI DMA Tx & Rx requests */
bogdanm	0:9b334a45a8ff	1525	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	1526	SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	1527
bogdanm	0:9b334a45a8ff	1528	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1529	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1530
bogdanm	0:9b334a45a8ff	1531	return HAL_OK;
bogdanm	0:9b334a45a8ff	1532	}
bogdanm	0:9b334a45a8ff	1533
bogdanm	0:9b334a45a8ff	1534	/**
bogdanm	0:9b334a45a8ff	1535	* @brief Stops the DMA Transfer.
bogdanm	0:9b334a45a8ff	1536	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1537	* the configuration information for the specified SPI module.
bogdanm	0:9b334a45a8ff	1538	* @retval HAL status
bogdanm	0:9b334a45a8ff	1539	*/
bogdanm	0:9b334a45a8ff	1540	HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1541	{
bogdanm	0:9b334a45a8ff	1542	/* The Lock is not implemented on this API to allow the user application
bogdanm	0:9b334a45a8ff	1543	to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
bogdanm	0:9b334a45a8ff	1544	when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
bogdanm	0:9b334a45a8ff	1545	and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
bogdanm	0:9b334a45a8ff	1546	*/
bogdanm	0:9b334a45a8ff	1547
bogdanm	0:9b334a45a8ff	1548	/* Abort the SPI DMA tx Channel */
bogdanm	0:9b334a45a8ff	1549	if(hspi->hdmatx != NULL)
bogdanm	0:9b334a45a8ff	1550	{
bogdanm	0:9b334a45a8ff	1551	HAL_DMA_Abort(hspi->hdmatx);
bogdanm	0:9b334a45a8ff	1552	}
bogdanm	0:9b334a45a8ff	1553	/* Abort the SPI DMA rx Channel */
bogdanm	0:9b334a45a8ff	1554	if(hspi->hdmarx != NULL)
bogdanm	0:9b334a45a8ff	1555	{
bogdanm	0:9b334a45a8ff	1556	HAL_DMA_Abort(hspi->hdmarx);
bogdanm	0:9b334a45a8ff	1557	}
bogdanm	0:9b334a45a8ff	1558
bogdanm	0:9b334a45a8ff	1559	/* Disable the SPI DMA Tx & Rx requests */
bogdanm	0:9b334a45a8ff	1560	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	1561	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	1562
bogdanm	0:9b334a45a8ff	1563	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1564
bogdanm	0:9b334a45a8ff	1565	return HAL_OK;
bogdanm	0:9b334a45a8ff	1566	}
bogdanm	0:9b334a45a8ff	1567
bogdanm	0:9b334a45a8ff	1568	/**
bogdanm	0:9b334a45a8ff	1569	* @brief This function handles SPI interrupt request.
bogdanm	0:9b334a45a8ff	1570	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1571	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1572	* @retval None
bogdanm	0:9b334a45a8ff	1573	*/
bogdanm	0:9b334a45a8ff	1574	void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1575	{
bogdanm	0:9b334a45a8ff	1576	/* SPI in mode Receiver and Overrun not occurred ---------------------------*/
bogdanm	0:9b334a45a8ff	1577	if((__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) == RESET))
bogdanm	0:9b334a45a8ff	1578	{
bogdanm	0:9b334a45a8ff	1579	hspi->RxISR(hspi);
bogdanm	0:9b334a45a8ff	1580	return;
bogdanm	0:9b334a45a8ff	1581	}
bogdanm	0:9b334a45a8ff	1582
bogdanm	0:9b334a45a8ff	1583	/* SPI in mode Tramitter ---------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1584	if((__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE) != RESET))
bogdanm	0:9b334a45a8ff	1585	{
bogdanm	0:9b334a45a8ff	1586	hspi->TxISR(hspi);
bogdanm	0:9b334a45a8ff	1587	return;
bogdanm	0:9b334a45a8ff	1588	}
bogdanm	0:9b334a45a8ff	1589
bogdanm	0:9b334a45a8ff	1590	if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_ERR) != RESET)
bogdanm	0:9b334a45a8ff	1591	{
bogdanm	0:9b334a45a8ff	1592	/* SPI CRC error interrupt occurred ---------------------------------------*/
bogdanm	0:9b334a45a8ff	1593	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
bogdanm	0:9b334a45a8ff	1594	{
bogdanm	0:9b334a45a8ff	1595	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
bogdanm	0:9b334a45a8ff	1596	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
bogdanm	0:9b334a45a8ff	1597	}
bogdanm	0:9b334a45a8ff	1598	/* SPI Mode Fault error interrupt occurred --------------------------------*/
bogdanm	0:9b334a45a8ff	1599	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET)
bogdanm	0:9b334a45a8ff	1600	{
bogdanm	0:9b334a45a8ff	1601	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
bogdanm	0:9b334a45a8ff	1602	__HAL_SPI_CLEAR_MODFFLAG(hspi);
bogdanm	0:9b334a45a8ff	1603	}
bogdanm	0:9b334a45a8ff	1604
bogdanm	0:9b334a45a8ff	1605	/* SPI Overrun error interrupt occurred -----------------------------------*/
bogdanm	0:9b334a45a8ff	1606	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET)
bogdanm	0:9b334a45a8ff	1607	{
bogdanm	0:9b334a45a8ff	1608	if(hspi->State != HAL_SPI_STATE_BUSY_TX)
bogdanm	0:9b334a45a8ff	1609	{
bogdanm	0:9b334a45a8ff	1610	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
bogdanm	0:9b334a45a8ff	1611	__HAL_SPI_CLEAR_OVRFLAG(hspi);
bogdanm	0:9b334a45a8ff	1612	}
bogdanm	0:9b334a45a8ff	1613	}
bogdanm	0:9b334a45a8ff	1614
bogdanm	0:9b334a45a8ff	1615	/* Call the Error call Back in case of Errors */
bogdanm	0:9b334a45a8ff	1616	if(hspi->ErrorCode!=HAL_SPI_ERROR_NONE)
bogdanm	0:9b334a45a8ff	1617	{
bogdanm	0:9b334a45a8ff	1618	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE \| SPI_IT_TXE \| SPI_IT_ERR);
bogdanm	0:9b334a45a8ff	1619	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1620	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	1621	}
bogdanm	0:9b334a45a8ff	1622	}
bogdanm	0:9b334a45a8ff	1623	}
bogdanm	0:9b334a45a8ff	1624
bogdanm	0:9b334a45a8ff	1625	/**
bogdanm	0:9b334a45a8ff	1626	* @brief Tx Transfer completed callbacks
bogdanm	0:9b334a45a8ff	1627	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1628	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1629	* @retval None
bogdanm	0:9b334a45a8ff	1630	*/
bogdanm	0:9b334a45a8ff	1631	__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1632	{
bogdanm	0:9b334a45a8ff	1633	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1634	the HAL_SPI_TxCpltCallback could be implenetd in the user file
bogdanm	0:9b334a45a8ff	1635	*/
bogdanm	0:9b334a45a8ff	1636	}
bogdanm	0:9b334a45a8ff	1637
bogdanm	0:9b334a45a8ff	1638	/**
bogdanm	0:9b334a45a8ff	1639	* @brief Rx Transfer completed callbacks
bogdanm	0:9b334a45a8ff	1640	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1641	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1642	* @retval None
bogdanm	0:9b334a45a8ff	1643	*/
bogdanm	0:9b334a45a8ff	1644	__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1645	{
bogdanm	0:9b334a45a8ff	1646	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1647	the HAL_SPI_RxCpltCallback() could be implenetd in the user file
bogdanm	0:9b334a45a8ff	1648	*/
bogdanm	0:9b334a45a8ff	1649	}
bogdanm	0:9b334a45a8ff	1650
bogdanm	0:9b334a45a8ff	1651	/**
bogdanm	0:9b334a45a8ff	1652	* @brief Tx and Rx Transfer completed callbacks
bogdanm	0:9b334a45a8ff	1653	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1654	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1655	* @retval None
bogdanm	0:9b334a45a8ff	1656	*/
bogdanm	0:9b334a45a8ff	1657	__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1658	{
bogdanm	0:9b334a45a8ff	1659	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1660	the HAL_SPI_TxRxCpltCallback() could be implenetd in the user file
bogdanm	0:9b334a45a8ff	1661	*/
bogdanm	0:9b334a45a8ff	1662	}
bogdanm	0:9b334a45a8ff	1663
bogdanm	0:9b334a45a8ff	1664	/**
bogdanm	0:9b334a45a8ff	1665	* @brief Tx Half Transfer completed callbacks
bogdanm	0:9b334a45a8ff	1666	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1667	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1668	* @retval None
bogdanm	0:9b334a45a8ff	1669	*/
bogdanm	0:9b334a45a8ff	1670	__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1671	{
bogdanm	0:9b334a45a8ff	1672	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1673	the HAL_SPI_TxHalfCpltCallback could be implenetd in the user file
bogdanm	0:9b334a45a8ff	1674	*/
bogdanm	0:9b334a45a8ff	1675	}
bogdanm	0:9b334a45a8ff	1676
bogdanm	0:9b334a45a8ff	1677	/**
bogdanm	0:9b334a45a8ff	1678	* @brief Rx Half Transfer completed callbacks
bogdanm	0:9b334a45a8ff	1679	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1680	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1681	* @retval None
bogdanm	0:9b334a45a8ff	1682	*/
bogdanm	0:9b334a45a8ff	1683	__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1684	{
bogdanm	0:9b334a45a8ff	1685	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1686	the HAL_SPI_RxHalfCpltCallback() could be implenetd in the user file
bogdanm	0:9b334a45a8ff	1687	*/
bogdanm	0:9b334a45a8ff	1688	}
bogdanm	0:9b334a45a8ff	1689
bogdanm	0:9b334a45a8ff	1690	/**
bogdanm	0:9b334a45a8ff	1691	* @brief Tx and Rx Transfer completed callbacks
bogdanm	0:9b334a45a8ff	1692	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1693	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1694	* @retval None
bogdanm	0:9b334a45a8ff	1695	*/
bogdanm	0:9b334a45a8ff	1696	__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1697	{
bogdanm	0:9b334a45a8ff	1698	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1699	the HAL_SPI_TxRxHalfCpltCallback() could be implenetd in the user file
bogdanm	0:9b334a45a8ff	1700	*/
bogdanm	0:9b334a45a8ff	1701	}
bogdanm	0:9b334a45a8ff	1702
bogdanm	0:9b334a45a8ff	1703	/**
bogdanm	0:9b334a45a8ff	1704	* @brief SPI error callbacks
bogdanm	0:9b334a45a8ff	1705	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1706	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1707	* @retval None
bogdanm	0:9b334a45a8ff	1708	*/
bogdanm	0:9b334a45a8ff	1709	__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1710	{
bogdanm	0:9b334a45a8ff	1711	/* NOTE : - This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1712	the HAL_SPI_ErrorCallback() could be implenetd in the user file.
bogdanm	0:9b334a45a8ff	1713	- The ErrorCode parameter in the hspi handle is updated by the SPI processes
bogdanm	0:9b334a45a8ff	1714	and user can use HAL_SPI_GetError() API to check the latest error occurred.
bogdanm	0:9b334a45a8ff	1715	*/
bogdanm	0:9b334a45a8ff	1716	}
bogdanm	0:9b334a45a8ff	1717
bogdanm	0:9b334a45a8ff	1718	/**
bogdanm	0:9b334a45a8ff	1719	* @}
bogdanm	0:9b334a45a8ff	1720	*/
bogdanm	0:9b334a45a8ff	1721
bogdanm	0:9b334a45a8ff	1722	/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
bogdanm	0:9b334a45a8ff	1723	* @brief SPI control functions
bogdanm	0:9b334a45a8ff	1724	*
bogdanm	0:9b334a45a8ff	1725	@verbatim
bogdanm	0:9b334a45a8ff	1726	===============================================================================
bogdanm	0:9b334a45a8ff	1727	##### Peripheral State and Errors functions #####
bogdanm	0:9b334a45a8ff	1728	===============================================================================
bogdanm	0:9b334a45a8ff	1729	[..]
bogdanm	0:9b334a45a8ff	1730	This subsection provides a set of functions allowing to control the SPI.
bogdanm	0:9b334a45a8ff	1731	(+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
bogdanm	0:9b334a45a8ff	1732	(+) HAL_SPI_GetError() check in run-time Errors occurring during communication
bogdanm	0:9b334a45a8ff	1733	@endverbatim
bogdanm	0:9b334a45a8ff	1734	* @{
bogdanm	0:9b334a45a8ff	1735	*/
bogdanm	0:9b334a45a8ff	1736
bogdanm	0:9b334a45a8ff	1737	/**
bogdanm	0:9b334a45a8ff	1738	* @brief Return the SPI state
bogdanm	0:9b334a45a8ff	1739	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1740	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1741	* @retval SPI state
bogdanm	0:9b334a45a8ff	1742	*/
bogdanm	0:9b334a45a8ff	1743	HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1744	{
bogdanm	0:9b334a45a8ff	1745	return hspi->State;
bogdanm	0:9b334a45a8ff	1746	}
bogdanm	0:9b334a45a8ff	1747
bogdanm	0:9b334a45a8ff	1748	/**
bogdanm	0:9b334a45a8ff	1749	* @brief Return the SPI error code
bogdanm	0:9b334a45a8ff	1750	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1751	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1752	* @retval SPI Error Code
bogdanm	0:9b334a45a8ff	1753	*/
bogdanm	0:9b334a45a8ff	1754	uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1755	{
bogdanm	0:9b334a45a8ff	1756	return hspi->ErrorCode;
bogdanm	0:9b334a45a8ff	1757	}
bogdanm	0:9b334a45a8ff	1758
bogdanm	0:9b334a45a8ff	1759	/**
bogdanm	0:9b334a45a8ff	1760	* @}
bogdanm	0:9b334a45a8ff	1761	*/
bogdanm	0:9b334a45a8ff	1762
bogdanm	0:9b334a45a8ff	1763	/**
bogdanm	0:9b334a45a8ff	1764	* @}
bogdanm	0:9b334a45a8ff	1765	*/
bogdanm	0:9b334a45a8ff	1766
bogdanm	0:9b334a45a8ff	1767
bogdanm	0:9b334a45a8ff	1768
bogdanm	0:9b334a45a8ff	1769	/** @addtogroup SPI_Private_Functions
bogdanm	0:9b334a45a8ff	1770	* @{
bogdanm	0:9b334a45a8ff	1771	*/
bogdanm	0:9b334a45a8ff	1772
bogdanm	0:9b334a45a8ff	1773
bogdanm	0:9b334a45a8ff	1774	/**
bogdanm	0:9b334a45a8ff	1775	* @brief Interrupt Handler to close Tx transfer
bogdanm	0:9b334a45a8ff	1776	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1777	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1778	* @retval None
bogdanm	0:9b334a45a8ff	1779	*/
bogdanm	0:9b334a45a8ff	1780	static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1781	{
bogdanm	0:9b334a45a8ff	1782	/* Wait until TXE flag is set to send data */
bogdanm	0:9b334a45a8ff	1783	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
bogdanm	0:9b334a45a8ff	1784	{
bogdanm	0:9b334a45a8ff	1785	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
bogdanm	0:9b334a45a8ff	1786	}
bogdanm	0:9b334a45a8ff	1787
bogdanm	0:9b334a45a8ff	1788	/* Disable TXE interrupt */
bogdanm	0:9b334a45a8ff	1789	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE));
bogdanm	0:9b334a45a8ff	1790
bogdanm	0:9b334a45a8ff	1791	/* Disable ERR interrupt if Receive process is finished */
bogdanm	0:9b334a45a8ff	1792	if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) == RESET)
bogdanm	0:9b334a45a8ff	1793	{
bogdanm	0:9b334a45a8ff	1794	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR));
bogdanm	0:9b334a45a8ff	1795
bogdanm	0:9b334a45a8ff	1796	/* Wait until Busy flag is reset before disabling SPI */
bogdanm	0:9b334a45a8ff	1797	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
bogdanm	0:9b334a45a8ff	1798	{
bogdanm	0:9b334a45a8ff	1799	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
bogdanm	0:9b334a45a8ff	1800	}
bogdanm	0:9b334a45a8ff	1801
bogdanm	0:9b334a45a8ff	1802	/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
bogdanm	0:9b334a45a8ff	1803	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
bogdanm	0:9b334a45a8ff	1804	{
bogdanm	0:9b334a45a8ff	1805	__HAL_SPI_CLEAR_OVRFLAG(hspi);
bogdanm	0:9b334a45a8ff	1806	}
bogdanm	0:9b334a45a8ff	1807
bogdanm	0:9b334a45a8ff	1808	/* Check if Errors has been detected during transfer */
bogdanm	0:9b334a45a8ff	1809	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
bogdanm	0:9b334a45a8ff	1810	{
bogdanm	0:9b334a45a8ff	1811	/* Check if we are in Tx or in Rx/Tx Mode */
bogdanm	0:9b334a45a8ff	1812	if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
bogdanm	0:9b334a45a8ff	1813	{
bogdanm	0:9b334a45a8ff	1814	/* Set state to READY before run the Callback Complete */
bogdanm	0:9b334a45a8ff	1815	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1816	HAL_SPI_TxRxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	1817	}
bogdanm	0:9b334a45a8ff	1818	else
bogdanm	0:9b334a45a8ff	1819	{
bogdanm	0:9b334a45a8ff	1820	/* Set state to READY before run the Callback Complete */
bogdanm	0:9b334a45a8ff	1821	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1822	HAL_SPI_TxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	1823	}
bogdanm	0:9b334a45a8ff	1824	}
bogdanm	0:9b334a45a8ff	1825	else
bogdanm	0:9b334a45a8ff	1826	{
bogdanm	0:9b334a45a8ff	1827	/* Set state to READY before run the Callback Complete */
bogdanm	0:9b334a45a8ff	1828	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1829	/* Call Error call back in case of Error */
bogdanm	0:9b334a45a8ff	1830	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	1831	}
bogdanm	0:9b334a45a8ff	1832	}
bogdanm	0:9b334a45a8ff	1833	}
bogdanm	0:9b334a45a8ff	1834
bogdanm	0:9b334a45a8ff	1835	/**
bogdanm	0:9b334a45a8ff	1836	* @brief Interrupt Handler to transmit amount of data in no-blocking mode
bogdanm	0:9b334a45a8ff	1837	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1838	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1839	* @retval None
bogdanm	0:9b334a45a8ff	1840	*/
bogdanm	0:9b334a45a8ff	1841	static void SPI_TxISR(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1842	{
bogdanm	0:9b334a45a8ff	1843	/* Transmit data in 8 Bit mode */
bogdanm	0:9b334a45a8ff	1844	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	1845	{
bogdanm	0:9b334a45a8ff	1846	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
bogdanm	0:9b334a45a8ff	1847	}
bogdanm	0:9b334a45a8ff	1848	/* Transmit data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	1849	else
bogdanm	0:9b334a45a8ff	1850	{
bogdanm	0:9b334a45a8ff	1851	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
bogdanm	0:9b334a45a8ff	1852	hspi->pTxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	1853	}
bogdanm	0:9b334a45a8ff	1854	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	1855
bogdanm	0:9b334a45a8ff	1856	if(hspi->TxXferCount == 0)
bogdanm	0:9b334a45a8ff	1857	{
bogdanm	0:9b334a45a8ff	1858	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1859	{
bogdanm	0:9b334a45a8ff	1860	/* calculate and transfer CRC on Tx line */
bogdanm	0:9b334a45a8ff	1861	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
bogdanm	0:9b334a45a8ff	1862	}
bogdanm	0:9b334a45a8ff	1863	SPI_TxCloseIRQHandler(hspi);
bogdanm	0:9b334a45a8ff	1864	}
bogdanm	0:9b334a45a8ff	1865	}
bogdanm	0:9b334a45a8ff	1866
bogdanm	0:9b334a45a8ff	1867	/**
bogdanm	0:9b334a45a8ff	1868	* @brief Interrupt Handler to close Rx transfer
bogdanm	0:9b334a45a8ff	1869	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1870	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1871	* @retval None
bogdanm	0:9b334a45a8ff	1872	*/
bogdanm	0:9b334a45a8ff	1873	static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1874	{
bogdanm	0:9b334a45a8ff	1875	__IO uint16_t tmpreg = 0;
bogdanm	0:9b334a45a8ff	1876
bogdanm	0:9b334a45a8ff	1877	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1878	{
bogdanm	0:9b334a45a8ff	1879	/* Wait until RXNE flag is set to read CRC data */
bogdanm	0:9b334a45a8ff	1880	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
bogdanm	0:9b334a45a8ff	1881	{
bogdanm	0:9b334a45a8ff	1882	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
bogdanm	0:9b334a45a8ff	1883	}
bogdanm	0:9b334a45a8ff	1884
bogdanm	0:9b334a45a8ff	1885	/* Read CRC to reset RXNE flag */
bogdanm	0:9b334a45a8ff	1886	tmpreg = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	1887	UNUSED(tmpreg);
bogdanm	0:9b334a45a8ff	1888
bogdanm	0:9b334a45a8ff	1889	/* Wait until RXNE flag is reset */
bogdanm	0:9b334a45a8ff	1890	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
bogdanm	0:9b334a45a8ff	1891	{
bogdanm	0:9b334a45a8ff	1892	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
bogdanm	0:9b334a45a8ff	1893	}
bogdanm	0:9b334a45a8ff	1894
bogdanm	0:9b334a45a8ff	1895	/* Check if CRC error occurred */
bogdanm	0:9b334a45a8ff	1896	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
bogdanm	0:9b334a45a8ff	1897	{
bogdanm	0:9b334a45a8ff	1898	/* Check if CRC error is valid or not (workaround to be applied or not) */
bogdanm	0:9b334a45a8ff	1899	if ( (hspi->State != HAL_SPI_STATE_BUSY_RX)
bogdanm	0:9b334a45a8ff	1900	\|\| (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR) )
bogdanm	0:9b334a45a8ff	1901	{
bogdanm	0:9b334a45a8ff	1902	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
bogdanm	0:9b334a45a8ff	1903
bogdanm	0:9b334a45a8ff	1904	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	1905	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	1906	}
bogdanm	0:9b334a45a8ff	1907	else
bogdanm	0:9b334a45a8ff	1908	{
bogdanm	0:9b334a45a8ff	1909	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
bogdanm	0:9b334a45a8ff	1910	}
bogdanm	0:9b334a45a8ff	1911	}
bogdanm	0:9b334a45a8ff	1912	}
bogdanm	0:9b334a45a8ff	1913
bogdanm	0:9b334a45a8ff	1914	/* Disable RXNE interrupt */
bogdanm	0:9b334a45a8ff	1915	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE));
bogdanm	0:9b334a45a8ff	1916
bogdanm	0:9b334a45a8ff	1917	/* if Transmit process is finished */
bogdanm	0:9b334a45a8ff	1918	if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) == RESET)
bogdanm	0:9b334a45a8ff	1919	{
bogdanm	0:9b334a45a8ff	1920	/* Disable ERR interrupt */
bogdanm	0:9b334a45a8ff	1921	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR));
bogdanm	0:9b334a45a8ff	1922
bogdanm	0:9b334a45a8ff	1923	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
bogdanm	0:9b334a45a8ff	1924	{
bogdanm	0:9b334a45a8ff	1925	/* Disable SPI peripheral */
bogdanm	0:9b334a45a8ff	1926	__HAL_SPI_DISABLE(hspi);
bogdanm	0:9b334a45a8ff	1927	}
bogdanm	0:9b334a45a8ff	1928
bogdanm	0:9b334a45a8ff	1929	/* Check if Errors has been detected during transfer */
bogdanm	0:9b334a45a8ff	1930	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
bogdanm	0:9b334a45a8ff	1931	{
bogdanm	0:9b334a45a8ff	1932	/* Check if we are in Rx or in Rx/Tx Mode */
bogdanm	0:9b334a45a8ff	1933	if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
bogdanm	0:9b334a45a8ff	1934	{
bogdanm	0:9b334a45a8ff	1935	/* Set state to READY before run the Callback Complete */
bogdanm	0:9b334a45a8ff	1936	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1937	HAL_SPI_TxRxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	1938	}
bogdanm	0:9b334a45a8ff	1939	else
bogdanm	0:9b334a45a8ff	1940	{
bogdanm	0:9b334a45a8ff	1941	/* Set state to READY before run the Callback Complete */
bogdanm	0:9b334a45a8ff	1942	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1943	HAL_SPI_RxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	1944	}
bogdanm	0:9b334a45a8ff	1945	}
bogdanm	0:9b334a45a8ff	1946	else
bogdanm	0:9b334a45a8ff	1947	{
bogdanm	0:9b334a45a8ff	1948	/* Set state to READY before run the Callback Complete */
bogdanm	0:9b334a45a8ff	1949	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1950	/* Call Error call back in case of Error */
bogdanm	0:9b334a45a8ff	1951	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	1952	}
bogdanm	0:9b334a45a8ff	1953	}
bogdanm	0:9b334a45a8ff	1954	}
bogdanm	0:9b334a45a8ff	1955
bogdanm	0:9b334a45a8ff	1956	/**
bogdanm	0:9b334a45a8ff	1957	* @brief Interrupt Handler to receive amount of data in 2Lines mode
bogdanm	0:9b334a45a8ff	1958	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1959	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1960	* @retval None
bogdanm	0:9b334a45a8ff	1961	*/
bogdanm	0:9b334a45a8ff	1962	static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1963	{
bogdanm	0:9b334a45a8ff	1964	/* Receive data in 8 Bit mode */
bogdanm	0:9b334a45a8ff	1965	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	1966	{
bogdanm	0:9b334a45a8ff	1967	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	1968	}
bogdanm	0:9b334a45a8ff	1969	/* Receive data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	1970	else
bogdanm	0:9b334a45a8ff	1971	{
bogdanm	0:9b334a45a8ff	1972	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	1973	hspi->pRxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	1974	}
bogdanm	0:9b334a45a8ff	1975	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	1976
bogdanm	0:9b334a45a8ff	1977	if(hspi->RxXferCount==0)
bogdanm	0:9b334a45a8ff	1978	{
bogdanm	0:9b334a45a8ff	1979	SPI_RxCloseIRQHandler(hspi);
bogdanm	0:9b334a45a8ff	1980	}
bogdanm	0:9b334a45a8ff	1981	}
bogdanm	0:9b334a45a8ff	1982
bogdanm	0:9b334a45a8ff	1983	/**
bogdanm	0:9b334a45a8ff	1984	* @brief Interrupt Handler to receive amount of data in no-blocking mode
bogdanm	0:9b334a45a8ff	1985	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1986	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1987	* @retval None
bogdanm	0:9b334a45a8ff	1988	*/
bogdanm	0:9b334a45a8ff	1989	static void SPI_RxISR(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1990	{
bogdanm	0:9b334a45a8ff	1991	/* Receive data in 8 Bit mode */
bogdanm	0:9b334a45a8ff	1992	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	1993	{
bogdanm	0:9b334a45a8ff	1994	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	1995	}
bogdanm	0:9b334a45a8ff	1996	/* Receive data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	1997	else
bogdanm	0:9b334a45a8ff	1998	{
bogdanm	0:9b334a45a8ff	1999	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	2000	hspi->pRxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	2001	}
bogdanm	0:9b334a45a8ff	2002	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	2003
bogdanm	0:9b334a45a8ff	2004	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	2005	if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
bogdanm	0:9b334a45a8ff	2006	{
bogdanm	0:9b334a45a8ff	2007	/* Set CRC Next to calculate CRC on Rx side */
bogdanm	0:9b334a45a8ff	2008	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
bogdanm	0:9b334a45a8ff	2009	}
bogdanm	0:9b334a45a8ff	2010
bogdanm	0:9b334a45a8ff	2011	if(hspi->RxXferCount == 0)
bogdanm	0:9b334a45a8ff	2012	{
bogdanm	0:9b334a45a8ff	2013	SPI_RxCloseIRQHandler(hspi);
bogdanm	0:9b334a45a8ff	2014	}
bogdanm	0:9b334a45a8ff	2015	}
bogdanm	0:9b334a45a8ff	2016
bogdanm	0:9b334a45a8ff	2017	/**
bogdanm	0:9b334a45a8ff	2018	* @brief DMA SPI transmit process complete callback
bogdanm	0:9b334a45a8ff	2019	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2020	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	2021	* @retval None
bogdanm	0:9b334a45a8ff	2022	*/
bogdanm	0:9b334a45a8ff	2023	static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	2024	{
bogdanm	0:9b334a45a8ff	2025	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	2026
bogdanm	0:9b334a45a8ff	2027	/* DMA Normal Mode */
bogdanm	0:9b334a45a8ff	2028	if((hdma->Instance->CCR & DMA_CIRCULAR) == 0)
bogdanm	0:9b334a45a8ff	2029	{
bogdanm	0:9b334a45a8ff	2030	/* Wait until TXE flag is set to send data */
bogdanm	0:9b334a45a8ff	2031	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
bogdanm	0:9b334a45a8ff	2032	{
bogdanm	0:9b334a45a8ff	2033	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
bogdanm	0:9b334a45a8ff	2034	}
bogdanm	0:9b334a45a8ff	2035
bogdanm	0:9b334a45a8ff	2036	/* Disable Tx DMA Request */
bogdanm	0:9b334a45a8ff	2037	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	2038
bogdanm	0:9b334a45a8ff	2039	/* Wait until Busy flag is reset before disabling SPI */
bogdanm	0:9b334a45a8ff	2040	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
bogdanm	0:9b334a45a8ff	2041	{
bogdanm	0:9b334a45a8ff	2042	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
bogdanm	0:9b334a45a8ff	2043	}
bogdanm	0:9b334a45a8ff	2044
bogdanm	0:9b334a45a8ff	2045	hspi->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	2046	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2047	}
bogdanm	0:9b334a45a8ff	2048
bogdanm	0:9b334a45a8ff	2049	/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
bogdanm	0:9b334a45a8ff	2050	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
bogdanm	0:9b334a45a8ff	2051	{
bogdanm	0:9b334a45a8ff	2052	__HAL_SPI_CLEAR_OVRFLAG(hspi);
bogdanm	0:9b334a45a8ff	2053	}
bogdanm	0:9b334a45a8ff	2054
bogdanm	0:9b334a45a8ff	2055	/* Check if Errors has been detected during transfer */
bogdanm	0:9b334a45a8ff	2056	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
bogdanm	0:9b334a45a8ff	2057	{
bogdanm	0:9b334a45a8ff	2058	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	2059	}
bogdanm	0:9b334a45a8ff	2060	else
bogdanm	0:9b334a45a8ff	2061	{
bogdanm	0:9b334a45a8ff	2062	HAL_SPI_TxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2063	}
bogdanm	0:9b334a45a8ff	2064	}
bogdanm	0:9b334a45a8ff	2065
bogdanm	0:9b334a45a8ff	2066	/**
bogdanm	0:9b334a45a8ff	2067	* @brief DMA SPI receive process complete callback
bogdanm	0:9b334a45a8ff	2068	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2069	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	2070	* @retval None
bogdanm	0:9b334a45a8ff	2071	*/
bogdanm	0:9b334a45a8ff	2072	static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	2073	{
bogdanm	0:9b334a45a8ff	2074	__IO uint16_t tmpreg = 0;
bogdanm	0:9b334a45a8ff	2075	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	2076
bogdanm	0:9b334a45a8ff	2077	/* DMA Normal mode */
bogdanm	0:9b334a45a8ff	2078	if((hdma->Instance->CCR & DMA_CIRCULAR) == 0)
bogdanm	0:9b334a45a8ff	2079	{
bogdanm	0:9b334a45a8ff	2080	/* Disable Rx DMA Request */
bogdanm	0:9b334a45a8ff	2081	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	2082
bogdanm	0:9b334a45a8ff	2083	/* Disable Tx DMA Request (done by default to handle the case Master RX direction 2 lines) */
bogdanm	0:9b334a45a8ff	2084	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	2085
bogdanm	0:9b334a45a8ff	2086	/* CRC Calculation handling */
bogdanm	0:9b334a45a8ff	2087	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	2088	{
bogdanm	0:9b334a45a8ff	2089	/* Wait until RXNE flag is set (CRC ready) */
bogdanm	0:9b334a45a8ff	2090	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
bogdanm	0:9b334a45a8ff	2091	{
bogdanm	0:9b334a45a8ff	2092	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
bogdanm	0:9b334a45a8ff	2093	}
bogdanm	0:9b334a45a8ff	2094
bogdanm	0:9b334a45a8ff	2095	/* Read CRC */
bogdanm	0:9b334a45a8ff	2096	tmpreg = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	2097	UNUSED(tmpreg);
bogdanm	0:9b334a45a8ff	2098
bogdanm	0:9b334a45a8ff	2099	/* Wait until RXNE flag is reset */
bogdanm	0:9b334a45a8ff	2100	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
bogdanm	0:9b334a45a8ff	2101	{
bogdanm	0:9b334a45a8ff	2102	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
bogdanm	0:9b334a45a8ff	2103	}
bogdanm	0:9b334a45a8ff	2104
bogdanm	0:9b334a45a8ff	2105	/* Check if CRC error occurred */
bogdanm	0:9b334a45a8ff	2106	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
bogdanm	0:9b334a45a8ff	2107	{
bogdanm	0:9b334a45a8ff	2108	/* Check if CRC error is valid or not (workaround to be applied or not) */
bogdanm	0:9b334a45a8ff	2109	if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
bogdanm	0:9b334a45a8ff	2110	{
bogdanm	0:9b334a45a8ff	2111	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
bogdanm	0:9b334a45a8ff	2112
bogdanm	0:9b334a45a8ff	2113	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	2114	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	2115	}
bogdanm	0:9b334a45a8ff	2116	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
bogdanm	0:9b334a45a8ff	2117	}
bogdanm	0:9b334a45a8ff	2118	}
bogdanm	0:9b334a45a8ff	2119
bogdanm	0:9b334a45a8ff	2120	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
bogdanm	0:9b334a45a8ff	2121	{
bogdanm	0:9b334a45a8ff	2122	/* Disable SPI peripheral */
bogdanm	0:9b334a45a8ff	2123	__HAL_SPI_DISABLE(hspi);
bogdanm	0:9b334a45a8ff	2124	}
bogdanm	0:9b334a45a8ff	2125
bogdanm	0:9b334a45a8ff	2126	hspi->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	2127	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2128
bogdanm	0:9b334a45a8ff	2129	/* Check if Errors has been detected during transfer */
bogdanm	0:9b334a45a8ff	2130	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
bogdanm	0:9b334a45a8ff	2131	{
bogdanm	0:9b334a45a8ff	2132	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	2133	}
bogdanm	0:9b334a45a8ff	2134	else
bogdanm	0:9b334a45a8ff	2135	{
bogdanm	0:9b334a45a8ff	2136	HAL_SPI_RxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2137	}
bogdanm	0:9b334a45a8ff	2138	}
bogdanm	0:9b334a45a8ff	2139	else
bogdanm	0:9b334a45a8ff	2140	{
bogdanm	0:9b334a45a8ff	2141	HAL_SPI_RxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2142	}
bogdanm	0:9b334a45a8ff	2143	}
bogdanm	0:9b334a45a8ff	2144
bogdanm	0:9b334a45a8ff	2145	/**
bogdanm	0:9b334a45a8ff	2146	* @brief DMA SPI transmit receive process complete callback
bogdanm	0:9b334a45a8ff	2147	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2148	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	2149	* @retval None
bogdanm	0:9b334a45a8ff	2150	*/
bogdanm	0:9b334a45a8ff	2151	static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	2152	{
bogdanm	0:9b334a45a8ff	2153	__IO uint16_t tmpreg = 0;
bogdanm	0:9b334a45a8ff	2154
bogdanm	0:9b334a45a8ff	2155	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	2156
bogdanm	0:9b334a45a8ff	2157	if((hdma->Instance->CCR & DMA_CIRCULAR) == 0)
bogdanm	0:9b334a45a8ff	2158	{
bogdanm	0:9b334a45a8ff	2159	/* CRC Calculation handling */
bogdanm	0:9b334a45a8ff	2160	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	2161	{
bogdanm	0:9b334a45a8ff	2162	/* Check if CRC is done on going (RXNE flag set) */
bogdanm	0:9b334a45a8ff	2163	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) == HAL_OK)
bogdanm	0:9b334a45a8ff	2164	{
bogdanm	0:9b334a45a8ff	2165	/* Wait until RXNE flag is set to send data */
bogdanm	0:9b334a45a8ff	2166	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
bogdanm	0:9b334a45a8ff	2167	{
bogdanm	0:9b334a45a8ff	2168	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
bogdanm	0:9b334a45a8ff	2169	}
bogdanm	0:9b334a45a8ff	2170	}
bogdanm	0:9b334a45a8ff	2171	/* Read CRC */
bogdanm	0:9b334a45a8ff	2172	tmpreg = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	2173	UNUSED(tmpreg);
bogdanm	0:9b334a45a8ff	2174
bogdanm	0:9b334a45a8ff	2175	/* Check if CRC error occurred */
bogdanm	0:9b334a45a8ff	2176	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
bogdanm	0:9b334a45a8ff	2177	{
bogdanm	0:9b334a45a8ff	2178	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
bogdanm	0:9b334a45a8ff	2179	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
bogdanm	0:9b334a45a8ff	2180	}
bogdanm	0:9b334a45a8ff	2181	}
bogdanm	0:9b334a45a8ff	2182
bogdanm	0:9b334a45a8ff	2183	/* Wait until TXE flag is set to send data */
bogdanm	0:9b334a45a8ff	2184	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
bogdanm	0:9b334a45a8ff	2185	{
bogdanm	0:9b334a45a8ff	2186	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
bogdanm	0:9b334a45a8ff	2187	}
bogdanm	0:9b334a45a8ff	2188
bogdanm	0:9b334a45a8ff	2189	/* Disable Tx DMA Request */
bogdanm	0:9b334a45a8ff	2190	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	2191
bogdanm	0:9b334a45a8ff	2192	/* Wait until Busy flag is reset before disabling SPI */
bogdanm	0:9b334a45a8ff	2193	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
bogdanm	0:9b334a45a8ff	2194	{
bogdanm	0:9b334a45a8ff	2195	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
bogdanm	0:9b334a45a8ff	2196	}
bogdanm	0:9b334a45a8ff	2197
bogdanm	0:9b334a45a8ff	2198	/* Disable Rx DMA Request */
bogdanm	0:9b334a45a8ff	2199	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	2200
bogdanm	0:9b334a45a8ff	2201	hspi->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	2202	hspi->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	2203
bogdanm	0:9b334a45a8ff	2204	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2205
bogdanm	0:9b334a45a8ff	2206	/* Check if Errors has been detected during transfer */
bogdanm	0:9b334a45a8ff	2207	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
bogdanm	0:9b334a45a8ff	2208	{
bogdanm	0:9b334a45a8ff	2209	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	2210	}
bogdanm	0:9b334a45a8ff	2211	else
bogdanm	0:9b334a45a8ff	2212	{
bogdanm	0:9b334a45a8ff	2213	HAL_SPI_TxRxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2214	}
bogdanm	0:9b334a45a8ff	2215	}
bogdanm	0:9b334a45a8ff	2216	else
bogdanm	0:9b334a45a8ff	2217	{
bogdanm	0:9b334a45a8ff	2218	HAL_SPI_TxRxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2219	}
bogdanm	0:9b334a45a8ff	2220	}
bogdanm	0:9b334a45a8ff	2221
bogdanm	0:9b334a45a8ff	2222	/**
bogdanm	0:9b334a45a8ff	2223	* @brief DMA SPI half transmit process complete callback
bogdanm	0:9b334a45a8ff	2224	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2225	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	2226	* @retval None
bogdanm	0:9b334a45a8ff	2227	*/
bogdanm	0:9b334a45a8ff	2228	static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	2229	{
bogdanm	0:9b334a45a8ff	2230	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	2231
bogdanm	0:9b334a45a8ff	2232	HAL_SPI_TxHalfCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2233	}
bogdanm	0:9b334a45a8ff	2234
bogdanm	0:9b334a45a8ff	2235	/**
bogdanm	0:9b334a45a8ff	2236	* @brief DMA SPI half receive process complete callback
bogdanm	0:9b334a45a8ff	2237	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2238	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	2239	* @retval None
bogdanm	0:9b334a45a8ff	2240	*/
bogdanm	0:9b334a45a8ff	2241	static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	2242	{
bogdanm	0:9b334a45a8ff	2243	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	2244
bogdanm	0:9b334a45a8ff	2245	HAL_SPI_RxHalfCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2246	}
bogdanm	0:9b334a45a8ff	2247
bogdanm	0:9b334a45a8ff	2248	/**
bogdanm	0:9b334a45a8ff	2249	* @brief DMA SPI Half transmit receive process complete callback
bogdanm	0:9b334a45a8ff	2250	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2251	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	2252	* @retval None
bogdanm	0:9b334a45a8ff	2253	*/
bogdanm	0:9b334a45a8ff	2254	static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	2255	{
bogdanm	0:9b334a45a8ff	2256	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	2257
bogdanm	0:9b334a45a8ff	2258	HAL_SPI_TxRxHalfCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2259	}
bogdanm	0:9b334a45a8ff	2260
bogdanm	0:9b334a45a8ff	2261	/**
bogdanm	0:9b334a45a8ff	2262	* @brief DMA SPI communication error callback
bogdanm	0:9b334a45a8ff	2263	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2264	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	2265	* @retval None
bogdanm	0:9b334a45a8ff	2266	*/
bogdanm	0:9b334a45a8ff	2267	static void SPI_DMAError(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	2268	{
bogdanm	0:9b334a45a8ff	2269	SPI_HandleTypeDef* hspi = (SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	2270	hspi->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	2271	hspi->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	2272	hspi->State= HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2273	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
bogdanm	0:9b334a45a8ff	2274	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	2275	}
bogdanm	0:9b334a45a8ff	2276
bogdanm	0:9b334a45a8ff	2277	/**
bogdanm	0:9b334a45a8ff	2278	* @brief This function handles SPI Communication Timeout.
bogdanm	0:9b334a45a8ff	2279	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2280	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2281	* @param Flag: SPI flag to check
bogdanm	0:9b334a45a8ff	2282	* @param Status: Flag status to check: RESET or set
bogdanm	0:9b334a45a8ff	2283	* @param Timeout: Timeout duration
bogdanm	0:9b334a45a8ff	2284	* @retval HAL status
bogdanm	0:9b334a45a8ff	2285	*/
bogdanm	0:9b334a45a8ff	2286	static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	2287	{
bogdanm	0:9b334a45a8ff	2288	uint32_t tickstart = 0;
bogdanm	0:9b334a45a8ff	2289
bogdanm	0:9b334a45a8ff	2290	/* Get tick */
bogdanm	0:9b334a45a8ff	2291	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	2292
bogdanm	0:9b334a45a8ff	2293	/* Wait until flag is set */
bogdanm	0:9b334a45a8ff	2294	if(Status == RESET)
bogdanm	0:9b334a45a8ff	2295	{
bogdanm	0:9b334a45a8ff	2296	while(__HAL_SPI_GET_FLAG(hspi, Flag) == RESET)
bogdanm	0:9b334a45a8ff	2297	{
bogdanm	0:9b334a45a8ff	2298	if(Timeout != HAL_MAX_DELAY)
bogdanm	0:9b334a45a8ff	2299	{
bogdanm	0:9b334a45a8ff	2300	if((Timeout == 0) \|\| ((HAL_GetTick() - tickstart ) > Timeout))
bogdanm	0:9b334a45a8ff	2301	{
bogdanm	0:9b334a45a8ff	2302	/* Disable the SPI and reset the CRC: the CRC value should be cleared
bogdanm	0:9b334a45a8ff	2303	on both master and slave sides in order to resynchronize the master
bogdanm	0:9b334a45a8ff	2304	and slave for their respective CRC calculation */
bogdanm	0:9b334a45a8ff	2305
bogdanm	0:9b334a45a8ff	2306	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
bogdanm	0:9b334a45a8ff	2307	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
bogdanm	0:9b334a45a8ff	2308
bogdanm	0:9b334a45a8ff	2309	/* Disable SPI peripheral */
bogdanm	0:9b334a45a8ff	2310	__HAL_SPI_DISABLE(hspi);
bogdanm	0:9b334a45a8ff	2311
bogdanm	0:9b334a45a8ff	2312	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	2313	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	2314	{
bogdanm	0:9b334a45a8ff	2315	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	2316	}
bogdanm	0:9b334a45a8ff	2317
bogdanm	0:9b334a45a8ff	2318	hspi->State= HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2319
bogdanm	0:9b334a45a8ff	2320	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	2321	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	2322
bogdanm	0:9b334a45a8ff	2323	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	2324	}
bogdanm	0:9b334a45a8ff	2325	}
bogdanm	0:9b334a45a8ff	2326	}
bogdanm	0:9b334a45a8ff	2327	}
bogdanm	0:9b334a45a8ff	2328	else
bogdanm	0:9b334a45a8ff	2329	{
bogdanm	0:9b334a45a8ff	2330	while(__HAL_SPI_GET_FLAG(hspi, Flag) != RESET)
bogdanm	0:9b334a45a8ff	2331	{
bogdanm	0:9b334a45a8ff	2332	if(Timeout != HAL_MAX_DELAY)
bogdanm	0:9b334a45a8ff	2333	{
bogdanm	0:9b334a45a8ff	2334	if((Timeout == 0) \|\| ((HAL_GetTick() - tickstart ) > Timeout))
bogdanm	0:9b334a45a8ff	2335	{
bogdanm	0:9b334a45a8ff	2336	/* Disable the SPI and reset the CRC: the CRC value should be cleared
bogdanm	0:9b334a45a8ff	2337	on both master and slave sides in order to resynchronize the master
bogdanm	0:9b334a45a8ff	2338	and slave for their respective CRC calculation */
bogdanm	0:9b334a45a8ff	2339
bogdanm	0:9b334a45a8ff	2340	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
bogdanm	0:9b334a45a8ff	2341	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
bogdanm	0:9b334a45a8ff	2342
bogdanm	0:9b334a45a8ff	2343	/* Disable SPI peripheral */
bogdanm	0:9b334a45a8ff	2344	__HAL_SPI_DISABLE(hspi);
bogdanm	0:9b334a45a8ff	2345
bogdanm	0:9b334a45a8ff	2346	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	2347	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	2348	{
bogdanm	0:9b334a45a8ff	2349	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	2350	}
bogdanm	0:9b334a45a8ff	2351
bogdanm	0:9b334a45a8ff	2352	hspi->State= HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2353
bogdanm	0:9b334a45a8ff	2354	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	2355	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	2356
bogdanm	0:9b334a45a8ff	2357	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	2358	}
bogdanm	0:9b334a45a8ff	2359	}
bogdanm	0:9b334a45a8ff	2360	}
bogdanm	0:9b334a45a8ff	2361	}
bogdanm	0:9b334a45a8ff	2362	return HAL_OK;
bogdanm	0:9b334a45a8ff	2363	}
bogdanm	0:9b334a45a8ff	2364
bogdanm	0:9b334a45a8ff	2365	/**
bogdanm	0:9b334a45a8ff	2366	* @}
bogdanm	0:9b334a45a8ff	2367	*/
bogdanm	0:9b334a45a8ff	2368
bogdanm	0:9b334a45a8ff	2369	/** @addtogroup SPI_Private_Functions
bogdanm	0:9b334a45a8ff	2370	* @{
bogdanm	0:9b334a45a8ff	2371	*/
bogdanm	0:9b334a45a8ff	2372
bogdanm	0:9b334a45a8ff	2373	/**
bogdanm	0:9b334a45a8ff	2374	* @brief Checks if encountered CRC error could be corresponding to wrongly detected errors
bogdanm	0:9b334a45a8ff	2375	* according to SPI instance, Device type, and revision ID.
bogdanm	0:9b334a45a8ff	2376	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2377	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2378	* @retval CRC error validity (SPI_INVALID_CRC_ERROR or SPI_VALID_CRC_ERROR).
bogdanm	0:9b334a45a8ff	2379	*/
bogdanm	0:9b334a45a8ff	2380	__weak uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	2381	{
bogdanm	0:9b334a45a8ff	2382	return (SPI_VALID_CRC_ERROR);
bogdanm	0:9b334a45a8ff	2383	}
bogdanm	0:9b334a45a8ff	2384	/**
bogdanm	0:9b334a45a8ff	2385	* @}
bogdanm	0:9b334a45a8ff	2386	*/
bogdanm	0:9b334a45a8ff	2387
bogdanm	0:9b334a45a8ff	2388
bogdanm	0:9b334a45a8ff	2389	#endif /* HAL_SPI_MODULE_ENABLED */
bogdanm	0:9b334a45a8ff	2390	/**
bogdanm	0:9b334a45a8ff	2391	* @}
bogdanm	0:9b334a45a8ff	2392	*/
bogdanm	0:9b334a45a8ff	2393
bogdanm	0:9b334a45a8ff	2394	/**
bogdanm	0:9b334a45a8ff	2395	* @}
bogdanm	0:9b334a45a8ff	2396	*/
bogdanm	0:9b334a45a8ff	2397
bogdanm	0:9b334a45a8ff	2398	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	21 Dec 2016
Imports:	1
Forks:	0
Commits:	154
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targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_spi.c@0:9b334a45a8ff, 2015-10-01 (annotated)

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