Fawwaz Nadzmy / mbed-dev

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targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_pwm.h@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/hal/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_pwm.h@144:ef7eb2e8f9f7 
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file
<> 144:ef7eb2e8f9f7 4 * @author
<> 144:ef7eb2e8f9f7 5 * @version
<> 144:ef7eb2e8f9f7 6 * @date
<> 144:ef7eb2e8f9f7 7 * @brief This file contains all the functions prototypes for the UART
<> 144:ef7eb2e8f9f7 8 * firmware library.
<> 144:ef7eb2e8f9f7 9 ******************************************************************************
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 ******************************************************************************
<> 144:ef7eb2e8f9f7 12 */
<> 144:ef7eb2e8f9f7 13
<> 144:ef7eb2e8f9f7 14 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 15 #ifndef __W7500X_PWM_H
<> 144:ef7eb2e8f9f7 16 #define __W7500X_PWM_H
<> 144:ef7eb2e8f9f7 17
<> 144:ef7eb2e8f9f7 18 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 19 extern "C" {
<> 144:ef7eb2e8f9f7 20 #endif
<> 144:ef7eb2e8f9f7 21
<> 144:ef7eb2e8f9f7 22 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 23 #include "W7500x.h"
<> 144:ef7eb2e8f9f7 24
<> 144:ef7eb2e8f9f7 25 /**********************************************************************************************/
<> 144:ef7eb2e8f9f7 26 /**********************************************************************************************/
<> 144:ef7eb2e8f9f7 27 // This structure and define must be in W7500x.h
<> 144:ef7eb2e8f9f7 28 /**********************************************************************************************/
<> 144:ef7eb2e8f9f7 29 /**********************************************************************************************/
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 typedef struct
<> 144:ef7eb2e8f9f7 32 {
<> 144:ef7eb2e8f9f7 33 uint32_t PWM_CHn_PEEER;
<> 144:ef7eb2e8f9f7 34 }PWM_CtrlPWMOutputTypeDef;
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 typedef struct
<> 144:ef7eb2e8f9f7 37 {
<> 144:ef7eb2e8f9f7 38 uint32_t PWM_CHn_PR;
<> 144:ef7eb2e8f9f7 39 uint32_t PWM_CHn_MR;
<> 144:ef7eb2e8f9f7 40 uint32_t PWM_CHn_LR;
<> 144:ef7eb2e8f9f7 41 uint32_t PWM_CHn_UDMR;
<> 144:ef7eb2e8f9f7 42 uint32_t PWM_CHn_PDMR;
<> 144:ef7eb2e8f9f7 43 uint32_t PWM_CHn_DZCR;
<> 144:ef7eb2e8f9f7 44 }PWM_DeadzoneModeInitTypDef;
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 #define IS_PWM_ALL_CH(CHn) ((CHn == PWM_CH0) || \
<> 144:ef7eb2e8f9f7 47 (CHn == PWM_CH1) || \
<> 144:ef7eb2e8f9f7 48 (CHn == PWM_CH2) || \
<> 144:ef7eb2e8f9f7 49 (CHn == PWM_CH3) || \
<> 144:ef7eb2e8f9f7 50 (CHn == PWM_CH4) || \
<> 144:ef7eb2e8f9f7 51 (CHn == PWM_CH5) || \
<> 144:ef7eb2e8f9f7 52 (CHn == PWM_CH6) || \
<> 144:ef7eb2e8f9f7 53 (CHn == PWM_CH7))
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 #define PWM_IER_IE0_Enable (0x1ul << 0)
<> 144:ef7eb2e8f9f7 56 #define PWM_IER_IE1_Enable (0x1ul << 1)
<> 144:ef7eb2e8f9f7 57 #define PWM_IER_IE2_Enable (0x1ul << 2)
<> 144:ef7eb2e8f9f7 58 #define PWM_IER_IE3_Enable (0x1ul << 3)
<> 144:ef7eb2e8f9f7 59 #define PWM_IER_IE4_Enable (0x1ul << 4)
<> 144:ef7eb2e8f9f7 60 #define PWM_IER_IE5_Enable (0x1ul << 5)
<> 144:ef7eb2e8f9f7 61 #define PWM_IER_IE6_Enable (0x1ul << 6)
<> 144:ef7eb2e8f9f7 62 #define PWM_IER_IE7_Enable (0x1ul << 7)
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 #define PWM_IER_IE0_Disable ~PWM_IER_IE0_Enable
<> 144:ef7eb2e8f9f7 65 #define PWM_IER_IE1_Disable ~PWM_IER_IE1_Enable
<> 144:ef7eb2e8f9f7 66 #define PWM_IER_IE2_Disable ~PWM_IER_IE2_Enable
<> 144:ef7eb2e8f9f7 67 #define PWM_IER_IE3_Disable ~PWM_IER_IE3_Enable
<> 144:ef7eb2e8f9f7 68 #define PWM_IER_IE4_Disable ~PWM_IER_IE4_Enable
<> 144:ef7eb2e8f9f7 69 #define PWM_IER_IE5_Disable ~PWM_IER_IE5_Enable
<> 144:ef7eb2e8f9f7 70 #define PWM_IER_IE6_Disable ~PWM_IER_IE6_Enable
<> 144:ef7eb2e8f9f7 71 #define PWM_IER_IE7_Disable ~PWM_IER_IE7_Enable
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 #define PWM_SSR_SS0_Start (0x1ul << 0)
<> 144:ef7eb2e8f9f7 74 #define PWM_SSR_SS1_Start (0x1ul << 1)
<> 144:ef7eb2e8f9f7 75 #define PWM_SSR_SS2_Start (0x1ul << 2)
<> 144:ef7eb2e8f9f7 76 #define PWM_SSR_SS3_Start (0x1ul << 3)
<> 144:ef7eb2e8f9f7 77 #define PWM_SSR_SS4_Start (0x1ul << 4)
<> 144:ef7eb2e8f9f7 78 #define PWM_SSR_SS5_Start (0x1ul << 5)
<> 144:ef7eb2e8f9f7 79 #define PWM_SSR_SS6_Start (0x1ul << 6)
<> 144:ef7eb2e8f9f7 80 #define PWM_SSR_SS7_Start (0x1ul << 7)
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 #define PWM_SSR_SS0_Stop ~PWM_SSR_SS0_Start
<> 144:ef7eb2e8f9f7 83 #define PWM_SSR_SS1_Stop ~PWM_SSR_SS1_Start
<> 144:ef7eb2e8f9f7 84 #define PWM_SSR_SS2_Stop ~PWM_SSR_SS2_Start
<> 144:ef7eb2e8f9f7 85 #define PWM_SSR_SS3_Stop ~PWM_SSR_SS3_Start
<> 144:ef7eb2e8f9f7 86 #define PWM_SSR_SS4_Stop ~PWM_SSR_SS4_Start
<> 144:ef7eb2e8f9f7 87 #define PWM_SSR_SS5_Stop ~PWM_SSR_SS5_Start
<> 144:ef7eb2e8f9f7 88 #define PWM_SSR_SS6_Stop ~PWM_SSR_SS6_Start
<> 144:ef7eb2e8f9f7 89 #define PWM_SSR_SS7_Stop ~PWM_SSR_SS7_Start
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 #define IS_SSR_BIT_FLAG(FLAG) (FLAG <= 0xFF)
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 #define PWM_PSR_PS0_Pause (0x1ul << 0)
<> 144:ef7eb2e8f9f7 94 #define PWM_PSR_PS1_Pause (0x1ul << 1)
<> 144:ef7eb2e8f9f7 95 #define PWM_PSR_PS2_Pause (0x1ul << 2)
<> 144:ef7eb2e8f9f7 96 #define PWM_PSR_PS3_Pause (0x1ul << 3)
<> 144:ef7eb2e8f9f7 97 #define PWM_PSR_PS4_Pause (0x1ul << 4)
<> 144:ef7eb2e8f9f7 98 #define PWM_PSR_PS5_Pause (0x1ul << 5)
<> 144:ef7eb2e8f9f7 99 #define PWM_PSR_PS6_Pause (0x1ul << 6)
<> 144:ef7eb2e8f9f7 100 #define PWM_PSR_PS7_Pause (0x1ul << 7)
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 #define PWM_PSR_PS0_Restart ~PWM_PSR_PS0_Pause
<> 144:ef7eb2e8f9f7 103 #define PWM_PSR_PS1_Restart ~PWM_PSR_PS1_Pause
<> 144:ef7eb2e8f9f7 104 #define PWM_PSR_PS2_Restart ~PWM_PSR_PS2_Pause
<> 144:ef7eb2e8f9f7 105 #define PWM_PSR_PS3_Restart ~PWM_PSR_PS3_Pause
<> 144:ef7eb2e8f9f7 106 #define PWM_PSR_PS4_Restart ~PWM_PSR_PS4_Pause
<> 144:ef7eb2e8f9f7 107 #define PWM_PSR_PS5_Restart ~PWM_PSR_PS5_Pause
<> 144:ef7eb2e8f9f7 108 #define PWM_PSR_PS6_Restart ~PWM_PSR_PS6_Pause
<> 144:ef7eb2e8f9f7 109 #define PWM_PSR_PS7_Restart ~PWM_PSR_PS7_Pause
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 #define IS_PWM_PSR_BIT_FLAG(FLAG) (FLAG <= 0xFF)
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 #define PWM_CHn_IER_MIE (0x1ul << 0) ///< Match Interrupt Enable
<> 144:ef7eb2e8f9f7 114 #define PWM_CHn_IER_OIE (0x1ul << 1) ///< Overflow Interrupt Enable
<> 144:ef7eb2e8f9f7 115 #define PWM_CHn_IER_CIE (0x1ul << 2) ///< Capture Interrupt Enable
<> 144:ef7eb2e8f9f7 116 #define IS_PWM_CHn_IER(FLAG) (FLAG <= 0x7)
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 #define PWM_CHn_IER_MI_Msk (0x1ul << 0) ///< Match Interrupt Enable Mask
<> 144:ef7eb2e8f9f7 119 #define PWM_CHn_IER_OI_Msk (0x1ul << 1) ///< Overflow Interrupt Enable Mask
<> 144:ef7eb2e8f9f7 120 #define PWM_CHn_IER_CI_Msk (0x1ul << 2) ///< Capture Interrupt Enable Mask
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 #define PWM_CHn_ICR_MatchInterruptClear (0x1ul << 0)
<> 144:ef7eb2e8f9f7 123 #define PWM_CHn_ICR_OverflowInterruptClear (0x1ul << 1)
<> 144:ef7eb2e8f9f7 124 #define PWM_CHn_ICR_CaptureInterruptClear (0x1ul << 2)
<> 144:ef7eb2e8f9f7 125 #define IS_PWM_CHn_IntClearFlag(FLAG) FLAG <= 0x7
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 /*
<> 144:ef7eb2e8f9f7 128 #define IS_PWM_STOP(CHn) (((CHn == PWM_CH0) && (PWM->SSR & PWM_SSR_SS0)) || \
<> 144:ef7eb2e8f9f7 129 ((CHn == PWM_CH1) && (PWM->SSR & PWM_SSR_SS1)) || \
<> 144:ef7eb2e8f9f7 130 ((CHn == PWM_CH2) && (PWM->SSR & PWM_SSR_SS2)) || \
<> 144:ef7eb2e8f9f7 131 ((CHn == PWM_CH3) && (PWM->SSR & PWM_SSR_SS3)) || \
<> 144:ef7eb2e8f9f7 132 ((CHn == PWM_CH4) && (PWM->SSR & PWM_SSR_SS4)) || \
<> 144:ef7eb2e8f9f7 133 ((CHn == PWM_CH5) && (PWM->SSR & PWM_SSR_SS5)) || \
<> 144:ef7eb2e8f9f7 134 ((CHn == PWM_CH6) && (PWM->SSR & PWM_SSR_SS6)) || \
<> 144:ef7eb2e8f9f7 135 ((CHn == PWM_CH7) && (PWM->SSR & PWM_SSR_SS7)))
<> 144:ef7eb2e8f9f7 136 */
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 #define IS_PWM_PR_FILTER(MAXVAL) (MAXVAL <= 0x1F)
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 #define PWM_CHn_UDMR_UpCount (0x0ul)
<> 144:ef7eb2e8f9f7 143 #define PWM_CHn_UDMR_DownCount (0x1ul)
<> 144:ef7eb2e8f9f7 144 #define IS_PWM_CHn_UDMR(MODE) ((MODE == PWM_CHn_UDMR_UpCount) || \
<> 144:ef7eb2e8f9f7 145 (MODE == PWM_CHn_UDMR_DownCount))
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 #define PWM_CHn_TCMR_TimerMode (0x0ul)
<> 144:ef7eb2e8f9f7 148 #define PWM_CHn_TCMR_RisingCounterMode (0x1ul)
<> 144:ef7eb2e8f9f7 149 #define PWM_CHn_TCMR_FallingCounterMode (0x2ul)
<> 144:ef7eb2e8f9f7 150 #define PWM_CHn_TCMR_BothCounterMode (0x3ul)
<> 144:ef7eb2e8f9f7 151 #define IS_PWM_CHn_TCMR(MODE) ((MODE == PWM_CHn_TCMR_RisingCounterMode) || \
<> 144:ef7eb2e8f9f7 152 (MODE == PWM_CHn_TCMR_FallingCounterMode) || \
<> 144:ef7eb2e8f9f7 153 (MODE == PWM_CHn_TCMR_BothCounterMode))
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 #define PWM_CHn_PEEER_Disable (0x0ul)
<> 144:ef7eb2e8f9f7 156 #define PWM_CHn_PEEER_ExtEnable (0x1ul)
<> 144:ef7eb2e8f9f7 157 #define PWM_CHn_PEEER_PWMEnable (0x2ul)
<> 144:ef7eb2e8f9f7 158 #define IS_PWM_CHn_PEEER(ENABLE) ((ENABLE == PWM_CHn_PEEER_Disable) || \
<> 144:ef7eb2e8f9f7 159 (ENABLE == PWM_CHn_PEEER_ExtEnable) || \
<> 144:ef7eb2e8f9f7 160 (ENABLE == PWM_CHn_PEEER_PWMEnable))
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 #define IS_PWM_Output(ENABLE) ((ENABLE == PWM_CHn_PEEER_Disable) || \
<> 144:ef7eb2e8f9f7 163 (ENABLE == PWM_CHn_PEEER_PWMEnable))
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 #define PWM_CHn_CMR_RisingEdge 0x0ul
<> 144:ef7eb2e8f9f7 166 #define PWM_CHn_CMR_FallingEdge 0x1ul
<> 144:ef7eb2e8f9f7 167 #define IS_PWM_CHn_CMR(MODE) ((MODE == PWM_CHn_CMR_RisingEdge) || \
<> 144:ef7eb2e8f9f7 168 (MODE == PWM_CHn_CMR_FallingEdge))
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 #define PWM_CHn_PDMR_Oneshot (0x0ul)
<> 144:ef7eb2e8f9f7 171 #define PWM_CHn_PDMR_Periodic (0x1ul)
<> 144:ef7eb2e8f9f7 172 #define IS_PWM_CHn_PDMR(MODE) ((MODE == PWM_CHn_PDMR_Periodic) || \
<> 144:ef7eb2e8f9f7 173 (MODE == PWM_CHn_PDMR_Oneshot))
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 #define PWM_CHn_DZER_Enable (0x1ul)
<> 144:ef7eb2e8f9f7 176 #define PWM_CHn_DZER_Disable (0x0ul)
<> 144:ef7eb2e8f9f7 177 #define PWM_CHn_DZER(ENABLE) ((ENABLE == PWM_CHn_DZER_Enable) || \
<> 144:ef7eb2e8f9f7 178 (ENABLE == PWM_CHn_DZER_Disable))
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 #define IS_PWM_Deadznoe(CHn) (((CHn == PWM_CH0) && (PWM_CH1->DZER == PWM_CHn_DZER_Disable)) || \
<> 144:ef7eb2e8f9f7 181 ((CHn == PWM_CH1) && (PWM_CH0->DZER == PWM_CHn_DZER_Disable)) || \
<> 144:ef7eb2e8f9f7 182 ((CHn == PWM_CH2) && (PWM_CH3->DZER == PWM_CHn_DZER_Disable)) || \
<> 144:ef7eb2e8f9f7 183 ((CHn == PWM_CH3) && (PWM_CH2->DZER == PWM_CHn_DZER_Disable)) || \
<> 144:ef7eb2e8f9f7 184 ((CHn == PWM_CH4) && (PWM_CH5->DZER == PWM_CHn_DZER_Disable)) || \
<> 144:ef7eb2e8f9f7 185 ((CHn == PWM_CH5) && (PWM_CH4->DZER == PWM_CHn_DZER_Disable)) || \
<> 144:ef7eb2e8f9f7 186 ((CHn == PWM_CH6) && (PWM_CH7->DZER == PWM_CHn_DZER_Disable)) || \
<> 144:ef7eb2e8f9f7 187 ((CHn == PWM_CH7) && (PWM_CH6->DZER == PWM_CHn_DZER_Disable)))
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 #define IS_PWM_CHn_DZCR_FILTER(MAXVAL) (MAXVAL <= 0x3FF)
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 void PWM_DeInit(PWM_CHn_TypeDef* PWM_CHn);
<> 144:ef7eb2e8f9f7 197 void PWM_TimerModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_TimerModeInitTypeDef* PWM_TimerModeInitStruct);
<> 144:ef7eb2e8f9f7 198 void PWM_CaptureModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_CaptureModeInitTypeDef* PWM_CaptureModeInitStruct);
<> 144:ef7eb2e8f9f7 199 void PWM_CounterModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_CounterModeInitTypeDef* PWM_CounterModeInitStruct);
<> 144:ef7eb2e8f9f7 200 void PWM_DeadzoneModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_DeadzoneModeInitTypDef* PWM_DeadzoneModeInitStruct);
<> 144:ef7eb2e8f9f7 201 void PWM_CtrlPWMOutput(PWM_CHn_TypeDef* PWM_CHn, uint32_t outputEnDisable );
<> 144:ef7eb2e8f9f7 202 void PWM_CtrlPWMOutputEnable(PWM_CHn_TypeDef* PWM_CHn) ;
<> 144:ef7eb2e8f9f7 203 void PWM_CtrlPWMOutputDisable(PWM_CHn_TypeDef* PWM_CHn) ;
<> 144:ef7eb2e8f9f7 204 void PWM_IntConfig(PWM_CHn_TypeDef* PWM_CHn, FunctionalState state);
<> 144:ef7eb2e8f9f7 205 FlagStatus PWM_GetIntEnableStatus(PWM_CHn_TypeDef* PWM_CHn);
<> 144:ef7eb2e8f9f7 206 void PWM_CHn_IntConfig(PWM_CHn_TypeDef* PWM_CHn, uint32_t PWM_CHn_IER, FunctionalState state);
<> 144:ef7eb2e8f9f7 207 void PWM_CHn_Start(PWM_CHn_TypeDef* PWM_CHn);
<> 144:ef7eb2e8f9f7 208 void PWM_Multi_Start(uint32_t ssr_bit_flag);
<> 144:ef7eb2e8f9f7 209 void PWM_CHn_Stop(PWM_CHn_TypeDef* PWM_CHn);
<> 144:ef7eb2e8f9f7 210 void PWM_Multi_Stop(uint32_t ssr_bit_flag);
<> 144:ef7eb2e8f9f7 211 void PWM_CHn_Pause(PWM_CHn_TypeDef* PWM_CHn);
<> 144:ef7eb2e8f9f7 212 void PWM_Multi_Pause(uint32_t psr_bit_flag);
<> 144:ef7eb2e8f9f7 213 void PWM_CHn_Restart(PWM_CHn_TypeDef* PWM_CHn);
<> 144:ef7eb2e8f9f7 214 void PWM_Multi_Restart(uint32_t psr_bit_flag);
<> 144:ef7eb2e8f9f7 215 uint32_t PWM_CHn_GetIntEnableStatus(PWM_CHn_TypeDef* PWM_CHn);
<> 144:ef7eb2e8f9f7 216 uint32_t PWM_CHn_GetIntFlagStatus(PWM_CHn_TypeDef* PWM_CHn);
<> 144:ef7eb2e8f9f7 217 void PWM_CHn_ClearInt(PWM_CHn_TypeDef* PWM_CHn, uint32_t PWM_CHn_ICR);
<> 144:ef7eb2e8f9f7 218 uint32_t PWM_CHn_GetTCR(PWM_CHn_TypeDef* PWM_CHn);
<> 144:ef7eb2e8f9f7 219 uint32_t PWM_CHn_GetPCR(PWM_CHn_TypeDef* PWM_CHn);
<> 144:ef7eb2e8f9f7 220 uint32_t PWM_CHn_GetPR(PWM_CHn_TypeDef* PWM_CHn);
<> 144:ef7eb2e8f9f7 221 void PWM_CHn_SetPR(PWM_CHn_TypeDef* PWM_CHn, uint32_t PR);
<> 144:ef7eb2e8f9f7 222 uint32_t PWM_CHn_GetMR(PWM_CHn_TypeDef* PWM_CHn);
<> 144:ef7eb2e8f9f7 223 void PWM_CHn_SetMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t MR);
<> 144:ef7eb2e8f9f7 224 uint32_t PWM_CHn_GetLR(PWM_CHn_TypeDef* PWM_CHn);
<> 144:ef7eb2e8f9f7 225 void PWM_CHn_SetLR(PWM_CHn_TypeDef* PWM_CHn, uint32_t LR);
<> 144:ef7eb2e8f9f7 226 uint32_t PWM_CHn_GetUDMR(PWM_CHn_TypeDef* PWM_CHn);
<> 144:ef7eb2e8f9f7 227 void PWM_CHn_SetUDMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t UDMR);
<> 144:ef7eb2e8f9f7 228 uint32_t PWM_CHn_GetTCMR(PWM_CHn_TypeDef* PWM_CHn);
<> 144:ef7eb2e8f9f7 229 void PWM_CHn_SetTCMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t TCMR);
<> 144:ef7eb2e8f9f7 230 uint32_t PWM_CHn_GetPEEER(PWM_CHn_TypeDef* PWM_CHn);
<> 144:ef7eb2e8f9f7 231 void PWM_CHn_SetPEEER(PWM_CHn_TypeDef* PWM_CHn, uint32_t PEEER);
<> 144:ef7eb2e8f9f7 232 uint32_t PWM_CHn_GetCMR(PWM_CHn_TypeDef* PWM_CHn);
<> 144:ef7eb2e8f9f7 233 void PWM_CHn_SetCMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t CMR);
<> 144:ef7eb2e8f9f7 234 uint32_t PWM_CHn_GetCR(PWM_CHn_TypeDef* PWM_CHn);
<> 144:ef7eb2e8f9f7 235 uint32_t PWM_CHn_GetPDMR(PWM_CHn_TypeDef* PWM_CHn);
<> 144:ef7eb2e8f9f7 236 void PWM_CHn_SetPDMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t PDMR);
<> 144:ef7eb2e8f9f7 237 void PWM_CHn_SetDZER(PWM_CHn_TypeDef* PWM_CHn, uint32_t DZER);
<> 144:ef7eb2e8f9f7 238 uint32_t PWM_CHn_GetDZCR(PWM_CHn_TypeDef* PWM_CHn);
<> 144:ef7eb2e8f9f7 239 void PWM_CHn_SetDZCR(PWM_CHn_TypeDef* PWM_CHn, uint32_t DZCR);
<> 144:ef7eb2e8f9f7 240 void PWM_CH0_ClearMatchInt(void);
<> 144:ef7eb2e8f9f7 241 void PWM_CH0_ClearOverflowInt(void);
<> 144:ef7eb2e8f9f7 242 void PWM_CH0_ClearCaptureInt(void);
<> 144:ef7eb2e8f9f7 243 void PWM_CH1_ClearMatchInt(void);
<> 144:ef7eb2e8f9f7 244 void PWM_CH1_ClearOverflowInt(void);
<> 144:ef7eb2e8f9f7 245 void PWM_CH1_ClearCaptureInt(void);
<> 144:ef7eb2e8f9f7 246 void PWM_CH2_ClearMatchInt(void);
<> 144:ef7eb2e8f9f7 247 void PWM_CH2_ClearOverflowInt(void);
<> 144:ef7eb2e8f9f7 248 void PWM_CH2_ClearCaptureInt(void);
<> 144:ef7eb2e8f9f7 249 void PWM_CH3_ClearMatchInt(void);
<> 144:ef7eb2e8f9f7 250 void PWM_CH3_ClearOverflowInt(void);
<> 144:ef7eb2e8f9f7 251 void PWM_CH3_ClearCaptureInt(void);
<> 144:ef7eb2e8f9f7 252 void PWM_CH4_ClearMatchInt(void);
<> 144:ef7eb2e8f9f7 253 void PWM_CH4_ClearOverflowInt(void);
<> 144:ef7eb2e8f9f7 254 void PWM_CH4_ClearCaptureInt(void);
<> 144:ef7eb2e8f9f7 255 void PWM_CH5_ClearMatchInt(void);
<> 144:ef7eb2e8f9f7 256 void PWM_CH5_ClearOverflowInt(void);
<> 144:ef7eb2e8f9f7 257 void PWM_CH5_ClearCaptureInt(void);
<> 144:ef7eb2e8f9f7 258 void PWM_CH6_ClearMatchInt(void);
<> 144:ef7eb2e8f9f7 259 void PWM_CH6_ClearOverflowInt(void);
<> 144:ef7eb2e8f9f7 260 void PWM_CH6_ClearCaptureInt(void);
<> 144:ef7eb2e8f9f7 261 void PWM_CH7_ClearMatchInt(void);
<> 144:ef7eb2e8f9f7 262 void PWM_CH7_ClearOverflowInt(void);
<> 144:ef7eb2e8f9f7 263 void PWM_CH7_ClearCaptureInt(void);
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265
<> 144:ef7eb2e8f9f7 266 void PWM0_Handler(void);
<> 144:ef7eb2e8f9f7 267 void PWM1_Handler(void);
<> 144:ef7eb2e8f9f7 268 void PWM2_Handler(void);
<> 144:ef7eb2e8f9f7 269 void PWM3_Handler(void);
<> 144:ef7eb2e8f9f7 270 void PWM4_Handler(void);
<> 144:ef7eb2e8f9f7 271 void PWM5_Handler(void);
<> 144:ef7eb2e8f9f7 272 void PWM6_Handler(void);
<> 144:ef7eb2e8f9f7 273 void PWM7_Handler(void);
<> 144:ef7eb2e8f9f7 274
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276
<> 144:ef7eb2e8f9f7 277
<> 144:ef7eb2e8f9f7 278 //Temporary macro=======
<> 144:ef7eb2e8f9f7 279 #define PWM_CH(N) ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + (N * 0x100UL)))
<> 144:ef7eb2e8f9f7 280 //======================
<> 144:ef7eb2e8f9f7 281
<> 144:ef7eb2e8f9f7 282
<> 144:ef7eb2e8f9f7 283 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 284 }
<> 144:ef7eb2e8f9f7 285 #endif
<> 144:ef7eb2e8f9f7 286
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 #endif //__W7500X_PWM_H
<> 144:ef7eb2e8f9f7 289