Fawwaz Nadzmy / mbed-STM

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_gpio.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
124:6a4a5b7d7324
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32f1xx_hal_gpio.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
bogdanm 0:9b334a45a8ff 5 * @version V1.0.0
bogdanm 0:9b334a45a8ff 6 * @date 15-December-2014
bogdanm 0:9b334a45a8ff 7 * @brief GPIO HAL module driver.
bogdanm 0:9b334a45a8ff 8 * This file provides firmware functions to manage the following
bogdanm 0:9b334a45a8ff 9 * functionalities of the General Purpose Input/Output (GPIO) peripheral:
bogdanm 0:9b334a45a8ff 10 * + Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 11 * + IO operation functions
bogdanm 0:9b334a45a8ff 12 *
bogdanm 0:9b334a45a8ff 13 @verbatim
bogdanm 0:9b334a45a8ff 14 ==============================================================================
bogdanm 0:9b334a45a8ff 15 ##### GPIO Peripheral features #####
bogdanm 0:9b334a45a8ff 16 ==============================================================================
bogdanm 0:9b334a45a8ff 17 [..]
bogdanm 0:9b334a45a8ff 18 Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
bogdanm 0:9b334a45a8ff 19 port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software
bogdanm 0:9b334a45a8ff 20 in several modes:
bogdanm 0:9b334a45a8ff 21 (+) Input mode
bogdanm 0:9b334a45a8ff 22 (+) Analog mode
bogdanm 0:9b334a45a8ff 23 (+) Output mode
bogdanm 0:9b334a45a8ff 24 (+) Alternate function mode
bogdanm 0:9b334a45a8ff 25 (+) External interrupt/event lines
bogdanm 0:9b334a45a8ff 26
bogdanm 0:9b334a45a8ff 27 [..]
bogdanm 0:9b334a45a8ff 28 During and just after reset, the alternate functions and external interrupt
bogdanm 0:9b334a45a8ff 29 lines are not active and the I/O ports are configured in input floating mode.
bogdanm 0:9b334a45a8ff 30
bogdanm 0:9b334a45a8ff 31 [..]
bogdanm 0:9b334a45a8ff 32 All GPIO pins have weak internal pull-up and pull-down resistors, which can be
bogdanm 0:9b334a45a8ff 33 activated or not.
bogdanm 0:9b334a45a8ff 34
bogdanm 0:9b334a45a8ff 35 [..]
bogdanm 0:9b334a45a8ff 36 In Output or Alternate mode, each IO can be configured on open-drain or push-pull
bogdanm 0:9b334a45a8ff 37 type and the IO speed can be selected depending on the VDD value.
bogdanm 0:9b334a45a8ff 38
bogdanm 0:9b334a45a8ff 39 [..]
bogdanm 0:9b334a45a8ff 40 All ports have external interrupt/event capability. To use external interrupt
bogdanm 0:9b334a45a8ff 41 lines, the port must be configured in input mode. All available GPIO pins are
bogdanm 0:9b334a45a8ff 42 connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
bogdanm 0:9b334a45a8ff 43
bogdanm 0:9b334a45a8ff 44 [..]
bogdanm 0:9b334a45a8ff 45 The external interrupt/event controller consists of up to 20 edge detectors in connectivity
bogdanm 0:9b334a45a8ff 46 line devices, or 19 edge detectors in other devices for generating event/interrupt requests.
bogdanm 0:9b334a45a8ff 47 Each input line can be independently configured to select the type (event or interrupt) and
bogdanm 0:9b334a45a8ff 48 the corresponding trigger event (rising or falling or both). Each line can also masked
bogdanm 0:9b334a45a8ff 49 independently. A pending register maintains the status line of the interrupt requests
bogdanm 0:9b334a45a8ff 50
bogdanm 0:9b334a45a8ff 51 ##### How to use this driver #####
bogdanm 0:9b334a45a8ff 52 ==============================================================================
bogdanm 0:9b334a45a8ff 53 [..]
bogdanm 0:9b334a45a8ff 54 (#) Enable the GPIO APB2 clock using the following function : __HAL_GPIOx_CLK_ENABLE().
bogdanm 0:9b334a45a8ff 55
bogdanm 0:9b334a45a8ff 56 (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
bogdanm 0:9b334a45a8ff 57 (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
bogdanm 0:9b334a45a8ff 58 (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
bogdanm 0:9b334a45a8ff 59 structure.
bogdanm 0:9b334a45a8ff 60 (++) In case of Output or alternate function mode selection: the speed is
bogdanm 0:9b334a45a8ff 61 configured through "Speed" member from GPIO_InitTypeDef structure
bogdanm 0:9b334a45a8ff 62 (++) Analog mode is required when a pin is to be used as ADC channel
bogdanm 0:9b334a45a8ff 63 or DAC output.
bogdanm 0:9b334a45a8ff 64 (++) In case of external interrupt/event selection the "Mode" member from
bogdanm 0:9b334a45a8ff 65 GPIO_InitTypeDef structure select the type (interrupt or event) and
bogdanm 0:9b334a45a8ff 66 the corresponding trigger event (rising or falling or both).
bogdanm 0:9b334a45a8ff 67
bogdanm 0:9b334a45a8ff 68 (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
bogdanm 0:9b334a45a8ff 69 mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
bogdanm 0:9b334a45a8ff 70 HAL_NVIC_EnableIRQ().
bogdanm 0:9b334a45a8ff 71
bogdanm 0:9b334a45a8ff 72 (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
bogdanm 0:9b334a45a8ff 73
bogdanm 0:9b334a45a8ff 74 (#) To set/reset the level of a pin configured in output mode use
bogdanm 0:9b334a45a8ff 75 HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
bogdanm 0:9b334a45a8ff 76
bogdanm 0:9b334a45a8ff 77 (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
bogdanm 0:9b334a45a8ff 78
bogdanm 0:9b334a45a8ff 79 (#) During and just after reset, the alternate functions are not
bogdanm 0:9b334a45a8ff 80 active and the GPIO pins are configured in input floating mode (except JTAG
bogdanm 0:9b334a45a8ff 81 pins).
bogdanm 0:9b334a45a8ff 82
bogdanm 0:9b334a45a8ff 83 (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
bogdanm 0:9b334a45a8ff 84 (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
bogdanm 0:9b334a45a8ff 85 priority over the GPIO function.
bogdanm 0:9b334a45a8ff 86
bogdanm 0:9b334a45a8ff 87 (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
bogdanm 0:9b334a45a8ff 88 general purpose PD0 and PD1, respectively, when the HSE oscillator is off.
bogdanm 0:9b334a45a8ff 89 The HSE has priority over the GPIO function.
bogdanm 0:9b334a45a8ff 90
bogdanm 0:9b334a45a8ff 91 @endverbatim
bogdanm 0:9b334a45a8ff 92 ******************************************************************************
bogdanm 0:9b334a45a8ff 93 * @attention
bogdanm 0:9b334a45a8ff 94 *
bogdanm 0:9b334a45a8ff 95 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 96 *
bogdanm 0:9b334a45a8ff 97 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 98 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 99 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 100 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 101 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 102 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 103 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 104 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 105 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 106 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 107 *
bogdanm 0:9b334a45a8ff 108 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 109 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 110 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 111 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 112 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 113 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 114 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 115 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 116 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 117 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 118 *
bogdanm 0:9b334a45a8ff 119 ******************************************************************************
bogdanm 0:9b334a45a8ff 120 */
bogdanm 0:9b334a45a8ff 121
bogdanm 0:9b334a45a8ff 122 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 123 #include "stm32f1xx_hal.h"
bogdanm 0:9b334a45a8ff 124
bogdanm 0:9b334a45a8ff 125 /** @addtogroup STM32F1xx_HAL_Driver
bogdanm 0:9b334a45a8ff 126 * @{
bogdanm 0:9b334a45a8ff 127 */
bogdanm 0:9b334a45a8ff 128
bogdanm 0:9b334a45a8ff 129 /** @defgroup GPIO GPIO
bogdanm 0:9b334a45a8ff 130 * @brief GPIO HAL module driver
bogdanm 0:9b334a45a8ff 131 * @{
bogdanm 0:9b334a45a8ff 132 */
bogdanm 0:9b334a45a8ff 133
bogdanm 0:9b334a45a8ff 134 #ifdef HAL_GPIO_MODULE_ENABLED
bogdanm 0:9b334a45a8ff 135
bogdanm 0:9b334a45a8ff 136 /* Private typedef -----------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 137 /* Private define ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 138 /** @defgroup GPIO_Private_Constants GPIO Private Constants
bogdanm 0:9b334a45a8ff 139 * @{
bogdanm 0:9b334a45a8ff 140 */
bogdanm 0:9b334a45a8ff 141
bogdanm 0:9b334a45a8ff 142 #define GPIO_MODE ((uint32_t)0x00000003)
bogdanm 0:9b334a45a8ff 143 #define EXTI_MODE ((uint32_t)0x10000000)
bogdanm 0:9b334a45a8ff 144 #define GPIO_MODE_IT ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 145 #define GPIO_MODE_EVT ((uint32_t)0x00020000)
bogdanm 0:9b334a45a8ff 146 #define RISING_EDGE ((uint32_t)0x00100000)
bogdanm 0:9b334a45a8ff 147 #define FALLING_EDGE ((uint32_t)0x00200000)
bogdanm 0:9b334a45a8ff 148 #define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 149 #define GPIO_NUMBER ((uint32_t)16)
bogdanm 0:9b334a45a8ff 150
bogdanm 0:9b334a45a8ff 151 /* Definitions for bit manipulation of CRL and CRH register */
bogdanm 0:9b334a45a8ff 152 #define GPIO_CR_MODE_INPUT ((uint32_t)0x00000000) /*!< 00: Input mode (reset state) */
bogdanm 0:9b334a45a8ff 153 #define GPIO_CR_CNF_ANALOG ((uint32_t)0x00000000) /*!< 00: Analog mode */
bogdanm 0:9b334a45a8ff 154 #define GPIO_CR_CNF_INPUT_FLOATING ((uint32_t)0x00000004) /*!< 01: Floating input (reset state) */
bogdanm 0:9b334a45a8ff 155 #define GPIO_CR_CNF_INPUT_PU_PD ((uint32_t)0x00000008) /*!< 10: Input with pull-up / pull-down */
bogdanm 0:9b334a45a8ff 156 #define GPIO_CR_CNF_GP_OUTPUT_PP ((uint32_t)0x00000000) /*!< 00: General purpose output push-pull */
bogdanm 0:9b334a45a8ff 157 #define GPIO_CR_CNF_GP_OUTPUT_OD ((uint32_t)0x00000004) /*!< 01: General purpose output Open-drain */
bogdanm 0:9b334a45a8ff 158 #define GPIO_CR_CNF_AF_OUTPUT_PP ((uint32_t)0x00000008) /*!< 10: Alternate function output Push-pull */
bogdanm 0:9b334a45a8ff 159 #define GPIO_CR_CNF_AF_OUTPUT_OD ((uint32_t)0x0000000C) /*!< 11: Alternate function output Open-drain */
bogdanm 0:9b334a45a8ff 160
bogdanm 0:9b334a45a8ff 161 /**
bogdanm 0:9b334a45a8ff 162 * @}
bogdanm 0:9b334a45a8ff 163 */
bogdanm 0:9b334a45a8ff 164
bogdanm 0:9b334a45a8ff 165 /* Private macro -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 166 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 167 /* Private function prototypes -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 168 /* Private functions ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 169
bogdanm 0:9b334a45a8ff 170 /** @defgroup GPIO_Exported_Functions GPIO Exported Functions
bogdanm 0:9b334a45a8ff 171 * @{
bogdanm 0:9b334a45a8ff 172 */
bogdanm 0:9b334a45a8ff 173
bogdanm 0:9b334a45a8ff 174 /** @defgroup GPIO_Exported_Functions_Group1 Initialization and deinitialization functions
bogdanm 0:9b334a45a8ff 175 * @brief Initialization and Configuration functions
bogdanm 0:9b334a45a8ff 176 *
bogdanm 0:9b334a45a8ff 177 @verbatim
bogdanm 0:9b334a45a8ff 178 ===============================================================================
bogdanm 0:9b334a45a8ff 179 ##### Initialization and deinitialization functions #####
bogdanm 0:9b334a45a8ff 180 ===============================================================================
bogdanm 0:9b334a45a8ff 181 [..]
bogdanm 0:9b334a45a8ff 182 This section provides functions allowing to initialize and de-initialize the GPIOs
bogdanm 0:9b334a45a8ff 183 to be ready for use.
bogdanm 0:9b334a45a8ff 184
bogdanm 0:9b334a45a8ff 185 @endverbatim
bogdanm 0:9b334a45a8ff 186 * @{
bogdanm 0:9b334a45a8ff 187 */
bogdanm 0:9b334a45a8ff 188
bogdanm 0:9b334a45a8ff 189 /**
bogdanm 0:9b334a45a8ff 190 * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
bogdanm 0:9b334a45a8ff 191 * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
bogdanm 0:9b334a45a8ff 192 * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
bogdanm 0:9b334a45a8ff 193 * the configuration information for the specified GPIO peripheral.
bogdanm 0:9b334a45a8ff 194 * @retval None
bogdanm 0:9b334a45a8ff 195 */
bogdanm 0:9b334a45a8ff 196 void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
bogdanm 0:9b334a45a8ff 197 {
bogdanm 0:9b334a45a8ff 198 uint32_t position;
bogdanm 0:9b334a45a8ff 199 uint32_t ioposition = 0x00;
bogdanm 0:9b334a45a8ff 200 uint32_t iocurrent = 0x00;
bogdanm 0:9b334a45a8ff 201 uint32_t temp = 0x00;
bogdanm 0:9b334a45a8ff 202 uint32_t config = 0x00;
bogdanm 0:9b334a45a8ff 203 __IO uint32_t *configregister; /* Store the address of CRL or CRH register based on pin number */
bogdanm 0:9b334a45a8ff 204 uint32_t registeroffset = 0; /* offset used during computation of CNF and MODE bits placement inside CRL or CRH register */
bogdanm 0:9b334a45a8ff 205
bogdanm 0:9b334a45a8ff 206 /* Check the parameters */
bogdanm 0:9b334a45a8ff 207 assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
bogdanm 0:9b334a45a8ff 208 assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
bogdanm 0:9b334a45a8ff 209 assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
bogdanm 0:9b334a45a8ff 210 assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
bogdanm 0:9b334a45a8ff 211
bogdanm 0:9b334a45a8ff 212 /* Configure the port pins */
bogdanm 0:9b334a45a8ff 213 for (position = 0; position < GPIO_NUMBER; position++)
bogdanm 0:9b334a45a8ff 214 {
bogdanm 0:9b334a45a8ff 215 /* Get the IO position */
bogdanm 0:9b334a45a8ff 216 ioposition = ((uint32_t)0x01) << position;
bogdanm 0:9b334a45a8ff 217
bogdanm 0:9b334a45a8ff 218 /* Get the current IO position */
bogdanm 0:9b334a45a8ff 219 iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
bogdanm 0:9b334a45a8ff 220
bogdanm 0:9b334a45a8ff 221 if (iocurrent == ioposition)
bogdanm 0:9b334a45a8ff 222 {
bogdanm 0:9b334a45a8ff 223 /* Check the Alternate function parameters */
bogdanm 0:9b334a45a8ff 224 assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
bogdanm 0:9b334a45a8ff 225
bogdanm 0:9b334a45a8ff 226 /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */
bogdanm 0:9b334a45a8ff 227 switch (GPIO_Init->Mode)
bogdanm 0:9b334a45a8ff 228 {
bogdanm 0:9b334a45a8ff 229 /* If we are configuring the pin in OUTPUT push-pull mode */
bogdanm 0:9b334a45a8ff 230 case GPIO_MODE_OUTPUT_PP:
bogdanm 0:9b334a45a8ff 231 /* Check the GPIO speed parameter */
bogdanm 0:9b334a45a8ff 232 assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
bogdanm 0:9b334a45a8ff 233 config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP;
bogdanm 0:9b334a45a8ff 234 break;
bogdanm 0:9b334a45a8ff 235
bogdanm 0:9b334a45a8ff 236 /* If we are configuring the pin in OUTPUT open-drain mode */
bogdanm 0:9b334a45a8ff 237 case GPIO_MODE_OUTPUT_OD:
bogdanm 0:9b334a45a8ff 238 /* Check the GPIO speed parameter */
bogdanm 0:9b334a45a8ff 239 assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
bogdanm 0:9b334a45a8ff 240 config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD;
bogdanm 0:9b334a45a8ff 241 break;
bogdanm 0:9b334a45a8ff 242
bogdanm 0:9b334a45a8ff 243 /* If we are configuring the pin in ALTERNATE FUNCTION push-pull mode */
bogdanm 0:9b334a45a8ff 244 case GPIO_MODE_AF_PP:
bogdanm 0:9b334a45a8ff 245 /* Check the GPIO speed parameter */
bogdanm 0:9b334a45a8ff 246 assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
bogdanm 0:9b334a45a8ff 247 config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP;
bogdanm 0:9b334a45a8ff 248 break;
bogdanm 0:9b334a45a8ff 249
bogdanm 0:9b334a45a8ff 250 /* If we are configuring the pin in ALTERNATE FUNCTION open-drain mode */
bogdanm 0:9b334a45a8ff 251 case GPIO_MODE_AF_OD:
bogdanm 0:9b334a45a8ff 252 /* Check the GPIO speed parameter */
bogdanm 0:9b334a45a8ff 253 assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
bogdanm 0:9b334a45a8ff 254 config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD;
bogdanm 0:9b334a45a8ff 255 break;
bogdanm 0:9b334a45a8ff 256
bogdanm 0:9b334a45a8ff 257 /* If we are configuring the pin in INPUT (also applicable to EVENT and IT mode) */
bogdanm 0:9b334a45a8ff 258 case GPIO_MODE_INPUT:
bogdanm 0:9b334a45a8ff 259 case GPIO_MODE_IT_RISING:
bogdanm 0:9b334a45a8ff 260 case GPIO_MODE_IT_FALLING:
bogdanm 0:9b334a45a8ff 261 case GPIO_MODE_IT_RISING_FALLING:
bogdanm 0:9b334a45a8ff 262 case GPIO_MODE_EVT_RISING:
bogdanm 0:9b334a45a8ff 263 case GPIO_MODE_EVT_FALLING:
bogdanm 0:9b334a45a8ff 264 case GPIO_MODE_EVT_RISING_FALLING:
bogdanm 0:9b334a45a8ff 265 /* Check the GPIO pull parameter */
bogdanm 0:9b334a45a8ff 266 assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
bogdanm 0:9b334a45a8ff 267 if(GPIO_Init->Pull == GPIO_NOPULL)
bogdanm 0:9b334a45a8ff 268 {
bogdanm 0:9b334a45a8ff 269 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING;
bogdanm 0:9b334a45a8ff 270 }
bogdanm 0:9b334a45a8ff 271 else if(GPIO_Init->Pull == GPIO_PULLUP)
bogdanm 0:9b334a45a8ff 272 {
bogdanm 0:9b334a45a8ff 273 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
bogdanm 0:9b334a45a8ff 274
bogdanm 0:9b334a45a8ff 275 /* Set the corresponding ODR bit */
bogdanm 0:9b334a45a8ff 276 GPIOx->BSRR = ioposition;
bogdanm 0:9b334a45a8ff 277 }
bogdanm 0:9b334a45a8ff 278 else /* GPIO_PULLDOWN */
bogdanm 0:9b334a45a8ff 279 {
bogdanm 0:9b334a45a8ff 280 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
bogdanm 0:9b334a45a8ff 281
bogdanm 0:9b334a45a8ff 282 /* Reset the corresponding ODR bit */
bogdanm 0:9b334a45a8ff 283 GPIOx->BRR = ioposition;
bogdanm 0:9b334a45a8ff 284 }
bogdanm 0:9b334a45a8ff 285 break;
bogdanm 0:9b334a45a8ff 286
bogdanm 0:9b334a45a8ff 287 /* If we are configuring the pin in INPUT analog mode */
bogdanm 0:9b334a45a8ff 288 case GPIO_MODE_ANALOG:
bogdanm 0:9b334a45a8ff 289 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
bogdanm 0:9b334a45a8ff 290 break;
bogdanm 0:9b334a45a8ff 291
bogdanm 0:9b334a45a8ff 292 /* Parameters are checked with assert_param */
bogdanm 0:9b334a45a8ff 293 default:
bogdanm 0:9b334a45a8ff 294 break;
bogdanm 0:9b334a45a8ff 295 }
bogdanm 0:9b334a45a8ff 296
bogdanm 0:9b334a45a8ff 297 /* Check if the current bit belongs to first half or last half of the pin count number
bogdanm 0:9b334a45a8ff 298 in order to address CRH or CRL register*/
bogdanm 0:9b334a45a8ff 299 configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH;
bogdanm 0:9b334a45a8ff 300 registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2) : ((position - 8) << 2);
bogdanm 0:9b334a45a8ff 301
bogdanm 0:9b334a45a8ff 302 /* Apply the new configuration of the pin to the register */
bogdanm 0:9b334a45a8ff 303 MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset ), (config << registeroffset));
bogdanm 0:9b334a45a8ff 304
bogdanm 0:9b334a45a8ff 305 /*--------------------- EXTI Mode Configuration ------------------------*/
bogdanm 0:9b334a45a8ff 306 /* Configure the External Interrupt or event for the current IO */
bogdanm 0:9b334a45a8ff 307 if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
bogdanm 0:9b334a45a8ff 308 {
bogdanm 0:9b334a45a8ff 309 /* Enable AFIO Clock */
bogdanm 0:9b334a45a8ff 310 __HAL_RCC_AFIO_CLK_ENABLE();
bogdanm 0:9b334a45a8ff 311 temp = AFIO->EXTICR[position >> 2];
bogdanm 0:9b334a45a8ff 312 CLEAR_BIT(temp, ((uint32_t)0x0F) << (4 * (position & 0x03)));
bogdanm 0:9b334a45a8ff 313 SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
bogdanm 0:9b334a45a8ff 314 AFIO->EXTICR[position >> 2] = temp;
bogdanm 0:9b334a45a8ff 315
bogdanm 0:9b334a45a8ff 316
bogdanm 0:9b334a45a8ff 317 /* Configure the interrupt mask */
bogdanm 0:9b334a45a8ff 318 if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
bogdanm 0:9b334a45a8ff 319 {
bogdanm 0:9b334a45a8ff 320 SET_BIT(EXTI->IMR, iocurrent);
bogdanm 0:9b334a45a8ff 321 }
bogdanm 0:9b334a45a8ff 322 else
bogdanm 0:9b334a45a8ff 323 {
bogdanm 0:9b334a45a8ff 324 CLEAR_BIT(EXTI->IMR, iocurrent);
bogdanm 0:9b334a45a8ff 325 }
bogdanm 0:9b334a45a8ff 326
bogdanm 0:9b334a45a8ff 327 /* Configure the event mask */
bogdanm 0:9b334a45a8ff 328 if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
bogdanm 0:9b334a45a8ff 329 {
bogdanm 0:9b334a45a8ff 330 SET_BIT(EXTI->EMR, iocurrent);
bogdanm 0:9b334a45a8ff 331 }
bogdanm 0:9b334a45a8ff 332 else
bogdanm 0:9b334a45a8ff 333 {
bogdanm 0:9b334a45a8ff 334 CLEAR_BIT(EXTI->EMR, iocurrent);
bogdanm 0:9b334a45a8ff 335 }
bogdanm 0:9b334a45a8ff 336
bogdanm 0:9b334a45a8ff 337 /* Enable or disable the rising trigger */
bogdanm 0:9b334a45a8ff 338 if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
bogdanm 0:9b334a45a8ff 339 {
bogdanm 0:9b334a45a8ff 340 SET_BIT(EXTI->RTSR, iocurrent);
bogdanm 0:9b334a45a8ff 341 }
bogdanm 0:9b334a45a8ff 342 else
bogdanm 0:9b334a45a8ff 343 {
bogdanm 0:9b334a45a8ff 344 CLEAR_BIT(EXTI->RTSR, iocurrent);
bogdanm 0:9b334a45a8ff 345 }
bogdanm 0:9b334a45a8ff 346
bogdanm 0:9b334a45a8ff 347 /* Enable or disable the falling trigger */
bogdanm 0:9b334a45a8ff 348 if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
bogdanm 0:9b334a45a8ff 349 {
bogdanm 0:9b334a45a8ff 350 SET_BIT(EXTI->FTSR, iocurrent);
bogdanm 0:9b334a45a8ff 351 }
bogdanm 0:9b334a45a8ff 352 else
bogdanm 0:9b334a45a8ff 353 {
bogdanm 0:9b334a45a8ff 354 CLEAR_BIT(EXTI->FTSR, iocurrent);
bogdanm 0:9b334a45a8ff 355 }
bogdanm 0:9b334a45a8ff 356 }
bogdanm 0:9b334a45a8ff 357 }
bogdanm 0:9b334a45a8ff 358 }
bogdanm 0:9b334a45a8ff 359 }
bogdanm 0:9b334a45a8ff 360
bogdanm 0:9b334a45a8ff 361 /**
bogdanm 0:9b334a45a8ff 362 * @brief De-initializes the GPIOx peripheral registers to their default reset values.
bogdanm 0:9b334a45a8ff 363 * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
bogdanm 0:9b334a45a8ff 364 * @param GPIO_Pin: specifies the port bit to be written.
bogdanm 0:9b334a45a8ff 365 * This parameter can be one of GPIO_PIN_x where x can be (0..15).
bogdanm 0:9b334a45a8ff 366 * @retval None
bogdanm 0:9b334a45a8ff 367 */
bogdanm 0:9b334a45a8ff 368 void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
bogdanm 0:9b334a45a8ff 369 {
bogdanm 0:9b334a45a8ff 370 uint32_t position = 0x00;
bogdanm 0:9b334a45a8ff 371 uint32_t iocurrent = 0x00;
bogdanm 0:9b334a45a8ff 372 uint32_t tmp = 0x00;
bogdanm 0:9b334a45a8ff 373 __IO uint32_t *configregister; /* Store the address of CRL or CRH register based on pin number */
bogdanm 0:9b334a45a8ff 374 uint32_t registeroffset = 0;
bogdanm 0:9b334a45a8ff 375
bogdanm 0:9b334a45a8ff 376 /* Check the parameters */
bogdanm 0:9b334a45a8ff 377 assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
bogdanm 0:9b334a45a8ff 378 assert_param(IS_GPIO_PIN(GPIO_Pin));
bogdanm 0:9b334a45a8ff 379
bogdanm 0:9b334a45a8ff 380 /* Configure the port pins */
bogdanm 0:9b334a45a8ff 381 while ((GPIO_Pin >> position) != 0)
bogdanm 0:9b334a45a8ff 382 {
bogdanm 0:9b334a45a8ff 383 /* Get current io position */
bogdanm 0:9b334a45a8ff 384 iocurrent = (GPIO_Pin) & ((uint32_t)1 << position);
bogdanm 0:9b334a45a8ff 385
bogdanm 0:9b334a45a8ff 386 if (iocurrent)
bogdanm 0:9b334a45a8ff 387 {
bogdanm 0:9b334a45a8ff 388 /*------------------------- GPIO Mode Configuration --------------------*/
bogdanm 0:9b334a45a8ff 389 /* Check if the current bit belongs to first half or last half of the pin count number
bogdanm 0:9b334a45a8ff 390 in order to address CRH or CRL register */
bogdanm 0:9b334a45a8ff 391 configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH;
bogdanm 0:9b334a45a8ff 392 registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2) : ((position - 8) << 2);
bogdanm 0:9b334a45a8ff 393
bogdanm 0:9b334a45a8ff 394 /* CRL/CRH default value is floating input(0x04) shifted to correct position */
bogdanm 0:9b334a45a8ff 395 MODIFY_REG(*configregister, ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset ), GPIO_CRL_CNF0_0 << registeroffset);
bogdanm 0:9b334a45a8ff 396
bogdanm 0:9b334a45a8ff 397 /* ODR default value is 0 */
bogdanm 0:9b334a45a8ff 398 CLEAR_BIT(GPIOx->ODR, iocurrent);
bogdanm 0:9b334a45a8ff 399
bogdanm 0:9b334a45a8ff 400 /*------------------------- EXTI Mode Configuration --------------------*/
bogdanm 0:9b334a45a8ff 401 /* Clear the External Interrupt or Event for the current IO */
bogdanm 0:9b334a45a8ff 402
bogdanm 0:9b334a45a8ff 403 tmp = AFIO->EXTICR[position >> 2];
bogdanm 0:9b334a45a8ff 404 tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03)));
bogdanm 0:9b334a45a8ff 405 if(tmp == (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03))))
bogdanm 0:9b334a45a8ff 406 {
bogdanm 0:9b334a45a8ff 407 tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));
bogdanm 0:9b334a45a8ff 408 CLEAR_BIT(AFIO->EXTICR[position >> 2], tmp);
bogdanm 0:9b334a45a8ff 409
bogdanm 0:9b334a45a8ff 410 /* Clear EXTI line configuration */
bogdanm 0:9b334a45a8ff 411 CLEAR_BIT(EXTI->IMR, (uint32_t)iocurrent);
bogdanm 0:9b334a45a8ff 412 CLEAR_BIT(EXTI->EMR, (uint32_t)iocurrent);
bogdanm 0:9b334a45a8ff 413
bogdanm 0:9b334a45a8ff 414 /* Clear Rising Falling edge configuration */
bogdanm 0:9b334a45a8ff 415 CLEAR_BIT(EXTI->RTSR, (uint32_t)iocurrent);
bogdanm 0:9b334a45a8ff 416 CLEAR_BIT(EXTI->FTSR, (uint32_t)iocurrent);
bogdanm 0:9b334a45a8ff 417 }
bogdanm 0:9b334a45a8ff 418 }
bogdanm 0:9b334a45a8ff 419
bogdanm 0:9b334a45a8ff 420 position++;
bogdanm 0:9b334a45a8ff 421 }
bogdanm 0:9b334a45a8ff 422 }
bogdanm 0:9b334a45a8ff 423
bogdanm 0:9b334a45a8ff 424 /**
bogdanm 0:9b334a45a8ff 425 * @}
bogdanm 0:9b334a45a8ff 426 */
bogdanm 0:9b334a45a8ff 427
bogdanm 0:9b334a45a8ff 428 /** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
bogdanm 0:9b334a45a8ff 429 * @brief GPIO Read and Write
bogdanm 0:9b334a45a8ff 430 *
bogdanm 0:9b334a45a8ff 431 @verbatim
bogdanm 0:9b334a45a8ff 432 ===============================================================================
bogdanm 0:9b334a45a8ff 433 ##### IO operation functions #####
bogdanm 0:9b334a45a8ff 434 ===============================================================================
bogdanm 0:9b334a45a8ff 435 [..]
bogdanm 0:9b334a45a8ff 436 This subsection provides a set of functions allowing to manage the GPIOs.
bogdanm 0:9b334a45a8ff 437
bogdanm 0:9b334a45a8ff 438 @endverbatim
bogdanm 0:9b334a45a8ff 439 * @{
bogdanm 0:9b334a45a8ff 440 */
bogdanm 0:9b334a45a8ff 441 /**
bogdanm 0:9b334a45a8ff 442 * @brief Reads the specified input port pin.
bogdanm 0:9b334a45a8ff 443 * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
bogdanm 0:9b334a45a8ff 444 * @param GPIO_Pin: specifies the port bit to read.
bogdanm 0:9b334a45a8ff 445 * This parameter can be GPIO_PIN_x where x can be (0..15).
bogdanm 0:9b334a45a8ff 446 * @retval The input port pin value.
bogdanm 0:9b334a45a8ff 447 */
bogdanm 0:9b334a45a8ff 448 GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
bogdanm 0:9b334a45a8ff 449 {
bogdanm 0:9b334a45a8ff 450 GPIO_PinState bitstatus;
bogdanm 0:9b334a45a8ff 451
bogdanm 0:9b334a45a8ff 452 /* Check the parameters */
bogdanm 0:9b334a45a8ff 453 assert_param(IS_GPIO_PIN(GPIO_Pin));
bogdanm 0:9b334a45a8ff 454
bogdanm 0:9b334a45a8ff 455 if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
bogdanm 0:9b334a45a8ff 456 {
bogdanm 0:9b334a45a8ff 457 bitstatus = GPIO_PIN_SET;
bogdanm 0:9b334a45a8ff 458 }
bogdanm 0:9b334a45a8ff 459 else
bogdanm 0:9b334a45a8ff 460 {
bogdanm 0:9b334a45a8ff 461 bitstatus = GPIO_PIN_RESET;
bogdanm 0:9b334a45a8ff 462 }
bogdanm 0:9b334a45a8ff 463 return bitstatus;
bogdanm 0:9b334a45a8ff 464 }
bogdanm 0:9b334a45a8ff 465
bogdanm 0:9b334a45a8ff 466 /**
bogdanm 0:9b334a45a8ff 467 * @brief Sets or clears the selected data port bit.
bogdanm 0:9b334a45a8ff 468 *
bogdanm 0:9b334a45a8ff 469 * @note This function uses GPIOx_BSRR register to allow atomic read/modify
bogdanm 0:9b334a45a8ff 470 * accesses. In this way, there is no risk of an IRQ occurring between
bogdanm 0:9b334a45a8ff 471 * the read and the modify access.
bogdanm 0:9b334a45a8ff 472 *
bogdanm 0:9b334a45a8ff 473 * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
bogdanm 0:9b334a45a8ff 474 * @param GPIO_Pin: specifies the port bit to be written.
bogdanm 0:9b334a45a8ff 475 * This parameter can be one of GPIO_PIN_x where x can be (0..15).
bogdanm 0:9b334a45a8ff 476 * @param PinState: specifies the value to be written to the selected bit.
bogdanm 0:9b334a45a8ff 477 * This parameter can be one of the GPIO_PinState enum values:
bogdanm 0:9b334a45a8ff 478 * @arg GPIO_BIT_RESET: to clear the port pin
bogdanm 0:9b334a45a8ff 479 * @arg GPIO_BIT_SET: to set the port pin
bogdanm 0:9b334a45a8ff 480 * @retval None
bogdanm 0:9b334a45a8ff 481 */
bogdanm 0:9b334a45a8ff 482 void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
bogdanm 0:9b334a45a8ff 483 {
bogdanm 0:9b334a45a8ff 484 /* Check the parameters */
bogdanm 0:9b334a45a8ff 485 assert_param(IS_GPIO_PIN(GPIO_Pin));
bogdanm 0:9b334a45a8ff 486 assert_param(IS_GPIO_PIN_ACTION(PinState));
bogdanm 0:9b334a45a8ff 487
bogdanm 0:9b334a45a8ff 488 if(PinState != GPIO_PIN_RESET)
bogdanm 0:9b334a45a8ff 489 {
bogdanm 0:9b334a45a8ff 490 GPIOx->BSRR = GPIO_Pin;
bogdanm 0:9b334a45a8ff 491 }
bogdanm 0:9b334a45a8ff 492 else
bogdanm 0:9b334a45a8ff 493 {
bogdanm 0:9b334a45a8ff 494 GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;
bogdanm 0:9b334a45a8ff 495 }
bogdanm 0:9b334a45a8ff 496 }
bogdanm 0:9b334a45a8ff 497
bogdanm 0:9b334a45a8ff 498 /**
bogdanm 0:9b334a45a8ff 499 * @brief Toggles the specified GPIO pin
bogdanm 0:9b334a45a8ff 500 * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
bogdanm 0:9b334a45a8ff 501 * @param GPIO_Pin: Specifies the pins to be toggled.
bogdanm 0:9b334a45a8ff 502 * @retval None
bogdanm 0:9b334a45a8ff 503 */
bogdanm 0:9b334a45a8ff 504 void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
bogdanm 0:9b334a45a8ff 505 {
bogdanm 0:9b334a45a8ff 506 /* Check the parameters */
bogdanm 0:9b334a45a8ff 507 assert_param(IS_GPIO_PIN(GPIO_Pin));
bogdanm 0:9b334a45a8ff 508
bogdanm 0:9b334a45a8ff 509 GPIOx->ODR ^= GPIO_Pin;
bogdanm 0:9b334a45a8ff 510 }
bogdanm 0:9b334a45a8ff 511
bogdanm 0:9b334a45a8ff 512 /**
bogdanm 0:9b334a45a8ff 513 * @brief Locks GPIO Pins configuration registers.
bogdanm 0:9b334a45a8ff 514 * @note The locking mechanism allows the IO configuration to be frozen. When the LOCK sequence
bogdanm 0:9b334a45a8ff 515 * has been applied on a port bit, it is no longer possible to modify the value of the port bit until
bogdanm 0:9b334a45a8ff 516 * the next reset.
bogdanm 0:9b334a45a8ff 517 * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
bogdanm 0:9b334a45a8ff 518 * @param GPIO_Pin: specifies the port bit to be locked.
bogdanm 0:9b334a45a8ff 519 * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
bogdanm 0:9b334a45a8ff 520 * @retval None
bogdanm 0:9b334a45a8ff 521 */
bogdanm 0:9b334a45a8ff 522 HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
bogdanm 0:9b334a45a8ff 523 {
bogdanm 0:9b334a45a8ff 524 __IO uint32_t tmp = GPIO_LCKR_LCKK;
bogdanm 0:9b334a45a8ff 525
bogdanm 0:9b334a45a8ff 526 /* Check the parameters */
bogdanm 0:9b334a45a8ff 527 assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
bogdanm 0:9b334a45a8ff 528 assert_param(IS_GPIO_PIN(GPIO_Pin));
bogdanm 0:9b334a45a8ff 529
bogdanm 0:9b334a45a8ff 530 /* Apply lock key write sequence */
bogdanm 0:9b334a45a8ff 531 SET_BIT(tmp, GPIO_Pin);
bogdanm 0:9b334a45a8ff 532 /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
bogdanm 0:9b334a45a8ff 533 GPIOx->LCKR = tmp;
bogdanm 0:9b334a45a8ff 534 /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
bogdanm 0:9b334a45a8ff 535 GPIOx->LCKR = GPIO_Pin;
bogdanm 0:9b334a45a8ff 536 /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
bogdanm 0:9b334a45a8ff 537 GPIOx->LCKR = tmp;
bogdanm 0:9b334a45a8ff 538 /* Read LCKK bit*/
bogdanm 0:9b334a45a8ff 539 tmp = GPIOx->LCKR;
bogdanm 0:9b334a45a8ff 540
bogdanm 0:9b334a45a8ff 541 if((uint32_t)(GPIOx->LCKR & GPIO_LCKR_LCKK))
bogdanm 0:9b334a45a8ff 542 {
bogdanm 0:9b334a45a8ff 543 return HAL_OK;
bogdanm 0:9b334a45a8ff 544 }
bogdanm 0:9b334a45a8ff 545 else
bogdanm 0:9b334a45a8ff 546 {
bogdanm 0:9b334a45a8ff 547 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 548 }
bogdanm 0:9b334a45a8ff 549 }
bogdanm 0:9b334a45a8ff 550
bogdanm 0:9b334a45a8ff 551 /**
bogdanm 0:9b334a45a8ff 552 * @brief This function handles EXTI interrupt request.
bogdanm 0:9b334a45a8ff 553 * @param GPIO_Pin: Specifies the pins connected EXTI line
bogdanm 0:9b334a45a8ff 554 * @retval None
bogdanm 0:9b334a45a8ff 555 */
bogdanm 0:9b334a45a8ff 556 void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
bogdanm 0:9b334a45a8ff 557 {
bogdanm 0:9b334a45a8ff 558 /* EXTI line interrupt detected */
bogdanm 0:9b334a45a8ff 559 if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
bogdanm 0:9b334a45a8ff 560 {
bogdanm 0:9b334a45a8ff 561 __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
bogdanm 0:9b334a45a8ff 562 HAL_GPIO_EXTI_Callback(GPIO_Pin);
bogdanm 0:9b334a45a8ff 563 }
bogdanm 0:9b334a45a8ff 564 }
bogdanm 0:9b334a45a8ff 565
bogdanm 0:9b334a45a8ff 566 /**
bogdanm 0:9b334a45a8ff 567 * @brief EXTI line detection callback
bogdanm 0:9b334a45a8ff 568 * @param GPIO_Pin: Specifies the pins connected EXTI line
bogdanm 0:9b334a45a8ff 569 * @retval None
bogdanm 0:9b334a45a8ff 570 */
bogdanm 0:9b334a45a8ff 571 __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
bogdanm 0:9b334a45a8ff 572 {
bogdanm 0:9b334a45a8ff 573 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 574 the HAL_GPIO_EXTI_Callback could be implemented in the user file
bogdanm 0:9b334a45a8ff 575 */
bogdanm 0:9b334a45a8ff 576 }
bogdanm 0:9b334a45a8ff 577
bogdanm 0:9b334a45a8ff 578 /**
bogdanm 0:9b334a45a8ff 579 * @}
bogdanm 0:9b334a45a8ff 580 */
bogdanm 0:9b334a45a8ff 581
bogdanm 0:9b334a45a8ff 582
bogdanm 0:9b334a45a8ff 583 /**
bogdanm 0:9b334a45a8ff 584 * @}
bogdanm 0:9b334a45a8ff 585 */
bogdanm 0:9b334a45a8ff 586
bogdanm 0:9b334a45a8ff 587 #endif /* HAL_GPIO_MODULE_ENABLED */
bogdanm 0:9b334a45a8ff 588 /**
bogdanm 0:9b334a45a8ff 589 * @}
bogdanm 0:9b334a45a8ff 590 */
bogdanm 0:9b334a45a8ff 591
bogdanm 0:9b334a45a8ff 592 /**
bogdanm 0:9b334a45a8ff 593 * @}
bogdanm 0:9b334a45a8ff 594 */
bogdanm 0:9b334a45a8ff 595
bogdanm 0:9b334a45a8ff 596 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/