Fawwaz Nadzmy / mbed-STM

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targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_tsc.h@153:9398a535854b, 2016-12-22 (annotated)

Committer:
fwndz
Date:
Thu Dec 22 05:12:40 2016 +0000
Revision:
153:9398a535854b
Parent:
151:5eaa88a5bcc7 
device target maximize

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l0xx_hal_tsc.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 151:5eaa88a5bcc7 5 * @version V1.7.0
<> 151:5eaa88a5bcc7 6 * @date 31-May-2016
<> 144:ef7eb2e8f9f7 7 * @brief This file contains all the functions prototypes for the TSC firmware
<> 144:ef7eb2e8f9f7 8 * library.
<> 144:ef7eb2e8f9f7 9 ******************************************************************************
<> 144:ef7eb2e8f9f7 10 * @attention
<> 144:ef7eb2e8f9f7 11 *
<> 144:ef7eb2e8f9f7 12 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 15 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 16 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 17 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 19 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 20 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 22 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 23 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 24 *
<> 144:ef7eb2e8f9f7 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 35 *
<> 144:ef7eb2e8f9f7 36 ******************************************************************************
<> 144:ef7eb2e8f9f7 37 */
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 #if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx)
<> 144:ef7eb2e8f9f7 40 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 41 #ifndef __STM32L0xx_TSC_H
<> 144:ef7eb2e8f9f7 42 #define __STM32L0xx_TSC_H
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 45 extern "C" {
<> 144:ef7eb2e8f9f7 46 #endif
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 49 #include "stm32l0xx_hal_def.h"
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 /** @addtogroup STM32L0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 52 * @{
<> 144:ef7eb2e8f9f7 53 */
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 /** @defgroup TSC TSC
<> 144:ef7eb2e8f9f7 56 * @{
<> 144:ef7eb2e8f9f7 57 */
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 /** @defgroup TSC_Exported_Types TSC Exported Types
<> 144:ef7eb2e8f9f7 60 * @{
<> 144:ef7eb2e8f9f7 61 */
<> 144:ef7eb2e8f9f7 62 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 /**
<> 144:ef7eb2e8f9f7 65 * @brief TSC state structure definition
<> 144:ef7eb2e8f9f7 66 */
<> 144:ef7eb2e8f9f7 67 typedef enum
<> 144:ef7eb2e8f9f7 68 {
<> 151:5eaa88a5bcc7 69 HAL_TSC_STATE_RESET = 0x00U, /*!< TSC registers have their reset value */
<> 151:5eaa88a5bcc7 70 HAL_TSC_STATE_READY = 0x01U, /*!< TSC registers are initialized or acquisition is completed with success */
<> 151:5eaa88a5bcc7 71 HAL_TSC_STATE_BUSY = 0x02U, /*!< TSC initialization or acquisition is on-going */
<> 151:5eaa88a5bcc7 72 HAL_TSC_STATE_ERROR = 0x03U /*!< Acquisition is completed with max count error */
<> 144:ef7eb2e8f9f7 73 } HAL_TSC_StateTypeDef;
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 /**
<> 144:ef7eb2e8f9f7 76 * @brief TSC group status structure definition
<> 144:ef7eb2e8f9f7 77 */
<> 144:ef7eb2e8f9f7 78 typedef enum
<> 144:ef7eb2e8f9f7 79 {
<> 151:5eaa88a5bcc7 80 TSC_GROUP_ONGOING = 0x00U, /*!< Acquisition on group is on-going or not started */
<> 151:5eaa88a5bcc7 81 TSC_GROUP_COMPLETED = 0x01U /*!< Acquisition on group is completed with success (no max count error) */
<> 144:ef7eb2e8f9f7 82 } TSC_GroupStatusTypeDef;
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 /**
<> 144:ef7eb2e8f9f7 85 * @brief TSC init structure definition
<> 144:ef7eb2e8f9f7 86 */
<> 144:ef7eb2e8f9f7 87 typedef struct
<> 144:ef7eb2e8f9f7 88 {
<> 144:ef7eb2e8f9f7 89 uint32_t CTPulseHighLength; /*!< Charge-transfer high pulse length */
<> 144:ef7eb2e8f9f7 90 uint32_t CTPulseLowLength; /*!< Charge-transfer low pulse length */
<> 144:ef7eb2e8f9f7 91 uint32_t SpreadSpectrum; /*!< Spread spectrum activation */
<> 144:ef7eb2e8f9f7 92 uint32_t SpreadSpectrumDeviation; /*!< Spread spectrum deviation */
<> 144:ef7eb2e8f9f7 93 uint32_t SpreadSpectrumPrescaler; /*!< Spread spectrum prescaler */
<> 144:ef7eb2e8f9f7 94 uint32_t PulseGeneratorPrescaler; /*!< Pulse generator prescaler */
<> 144:ef7eb2e8f9f7 95 uint32_t MaxCountValue; /*!< Max count value */
<> 144:ef7eb2e8f9f7 96 uint32_t IODefaultMode; /*!< IO default mode */
<> 144:ef7eb2e8f9f7 97 uint32_t SynchroPinPolarity; /*!< Synchro pin polarity */
<> 144:ef7eb2e8f9f7 98 uint32_t AcquisitionMode; /*!< Acquisition mode */
<> 144:ef7eb2e8f9f7 99 uint32_t MaxCountInterrupt; /*!< Max count interrupt activation */
<> 144:ef7eb2e8f9f7 100 uint32_t ChannelIOs; /*!< Channel IOs mask */
<> 144:ef7eb2e8f9f7 101 uint32_t ShieldIOs; /*!< Shield IOs mask */
<> 144:ef7eb2e8f9f7 102 uint32_t SamplingIOs; /*!< Sampling IOs mask */
<> 144:ef7eb2e8f9f7 103 } TSC_InitTypeDef;
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 /**
<> 144:ef7eb2e8f9f7 106 * @brief TSC IOs configuration structure definition
<> 144:ef7eb2e8f9f7 107 */
<> 144:ef7eb2e8f9f7 108 typedef struct
<> 144:ef7eb2e8f9f7 109 {
<> 144:ef7eb2e8f9f7 110 uint32_t ChannelIOs; /*!< Channel IOs mask */
<> 144:ef7eb2e8f9f7 111 uint32_t ShieldIOs; /*!< Shield IOs mask */
<> 144:ef7eb2e8f9f7 112 uint32_t SamplingIOs; /*!< Sampling IOs mask */
<> 144:ef7eb2e8f9f7 113 } TSC_IOConfigTypeDef;
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 /**
<> 144:ef7eb2e8f9f7 116 * @brief TSC handle Structure definition
<> 144:ef7eb2e8f9f7 117 */
<> 144:ef7eb2e8f9f7 118 typedef struct
<> 144:ef7eb2e8f9f7 119 {
<> 144:ef7eb2e8f9f7 120 TSC_TypeDef *Instance; /*!< Register base address */
<> 144:ef7eb2e8f9f7 121 TSC_InitTypeDef Init; /*!< Initialization parameters */
<> 144:ef7eb2e8f9f7 122 __IO HAL_TSC_StateTypeDef State; /*!< Peripheral state */
<> 144:ef7eb2e8f9f7 123 HAL_LockTypeDef Lock; /*!< Lock feature */
<> 144:ef7eb2e8f9f7 124 } TSC_HandleTypeDef;
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 /**
<> 144:ef7eb2e8f9f7 128 * @}
<> 144:ef7eb2e8f9f7 129 */
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 /** @defgroup TSC_Exported_Constants TSC Exported Constants
<> 144:ef7eb2e8f9f7 134 * @{
<> 144:ef7eb2e8f9f7 135 */
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137
<> 151:5eaa88a5bcc7 138 #define TSC_CTPH_1CYCLE ((uint32_t)((uint32_t) 0U << 28U))
<> 151:5eaa88a5bcc7 139 #define TSC_CTPH_2CYCLES ((uint32_t)((uint32_t) 1U << 28U))
<> 151:5eaa88a5bcc7 140 #define TSC_CTPH_3CYCLES ((uint32_t)((uint32_t) 2U << 28U))
<> 151:5eaa88a5bcc7 141 #define TSC_CTPH_4CYCLES ((uint32_t)((uint32_t) 3U << 28U))
<> 151:5eaa88a5bcc7 142 #define TSC_CTPH_5CYCLES ((uint32_t)((uint32_t) 4U << 28U))
<> 151:5eaa88a5bcc7 143 #define TSC_CTPH_6CYCLES ((uint32_t)((uint32_t) 5U << 28U))
<> 151:5eaa88a5bcc7 144 #define TSC_CTPH_7CYCLES ((uint32_t)((uint32_t) 6U << 28U))
<> 151:5eaa88a5bcc7 145 #define TSC_CTPH_8CYCLES ((uint32_t)((uint32_t) 7U << 28U))
<> 151:5eaa88a5bcc7 146 #define TSC_CTPH_9CYCLES ((uint32_t)((uint32_t) 8U << 28U))
<> 151:5eaa88a5bcc7 147 #define TSC_CTPH_10CYCLES ((uint32_t)((uint32_t) 9U << 28U))
<> 151:5eaa88a5bcc7 148 #define TSC_CTPH_11CYCLES ((uint32_t)((uint32_t)10U << 28U))
<> 151:5eaa88a5bcc7 149 #define TSC_CTPH_12CYCLES ((uint32_t)((uint32_t)11U << 28U))
<> 151:5eaa88a5bcc7 150 #define TSC_CTPH_13CYCLES ((uint32_t)((uint32_t)12U << 28U))
<> 151:5eaa88a5bcc7 151 #define TSC_CTPH_14CYCLES ((uint32_t)((uint32_t)13U << 28U))
<> 151:5eaa88a5bcc7 152 #define TSC_CTPH_15CYCLES ((uint32_t)((uint32_t)14U << 28U))
<> 151:5eaa88a5bcc7 153 #define TSC_CTPH_16CYCLES ((uint32_t)((uint32_t)15U << 28U))
<> 144:ef7eb2e8f9f7 154
<> 151:5eaa88a5bcc7 155 #define TSC_CTPL_1CYCLE ((uint32_t)((uint32_t) 0U << 24U))
<> 151:5eaa88a5bcc7 156 #define TSC_CTPL_2CYCLES ((uint32_t)((uint32_t) 1U << 24U))
<> 151:5eaa88a5bcc7 157 #define TSC_CTPL_3CYCLES ((uint32_t)((uint32_t) 2U << 24U))
<> 151:5eaa88a5bcc7 158 #define TSC_CTPL_4CYCLES ((uint32_t)((uint32_t) 3U << 24U))
<> 151:5eaa88a5bcc7 159 #define TSC_CTPL_5CYCLES ((uint32_t)((uint32_t) 4U << 24U))
<> 151:5eaa88a5bcc7 160 #define TSC_CTPL_6CYCLES ((uint32_t)((uint32_t) 5U << 24U))
<> 151:5eaa88a5bcc7 161 #define TSC_CTPL_7CYCLES ((uint32_t)((uint32_t) 6U << 24U))
<> 151:5eaa88a5bcc7 162 #define TSC_CTPL_8CYCLES ((uint32_t)((uint32_t) 7U << 24U))
<> 151:5eaa88a5bcc7 163 #define TSC_CTPL_9CYCLES ((uint32_t)((uint32_t) 8U << 24U))
<> 151:5eaa88a5bcc7 164 #define TSC_CTPL_10CYCLES ((uint32_t)((uint32_t) 9U << 24U))
<> 151:5eaa88a5bcc7 165 #define TSC_CTPL_11CYCLES ((uint32_t)((uint32_t)10U << 24U))
<> 151:5eaa88a5bcc7 166 #define TSC_CTPL_12CYCLES ((uint32_t)((uint32_t)11U << 24U))
<> 151:5eaa88a5bcc7 167 #define TSC_CTPL_13CYCLES ((uint32_t)((uint32_t)12U << 24U))
<> 151:5eaa88a5bcc7 168 #define TSC_CTPL_14CYCLES ((uint32_t)((uint32_t)13U << 24U))
<> 151:5eaa88a5bcc7 169 #define TSC_CTPL_15CYCLES ((uint32_t)((uint32_t)14U << 24U))
<> 151:5eaa88a5bcc7 170 #define TSC_CTPL_16CYCLES ((uint32_t)((uint32_t)15U << 24U))
<> 144:ef7eb2e8f9f7 171
<> 151:5eaa88a5bcc7 172 #define TSC_SS_PRESC_DIV1 ((uint32_t)0U)
<> 144:ef7eb2e8f9f7 173 #define TSC_SS_PRESC_DIV2 (TSC_CR_SSPSC)
<> 144:ef7eb2e8f9f7 174
<> 151:5eaa88a5bcc7 175 #define TSC_PG_PRESC_DIV1 ((uint32_t)(0U << 12U))
<> 151:5eaa88a5bcc7 176 #define TSC_PG_PRESC_DIV2 ((uint32_t)(1U << 12U))
<> 151:5eaa88a5bcc7 177 #define TSC_PG_PRESC_DIV4 ((uint32_t)(2U << 12U))
<> 151:5eaa88a5bcc7 178 #define TSC_PG_PRESC_DIV8 ((uint32_t)(3U << 12U))
<> 151:5eaa88a5bcc7 179 #define TSC_PG_PRESC_DIV16 ((uint32_t)(4U << 12U))
<> 151:5eaa88a5bcc7 180 #define TSC_PG_PRESC_DIV32 ((uint32_t)(5U << 12U))
<> 151:5eaa88a5bcc7 181 #define TSC_PG_PRESC_DIV64 ((uint32_t)(6U << 12U))
<> 151:5eaa88a5bcc7 182 #define TSC_PG_PRESC_DIV128 ((uint32_t)(7U << 12U))
<> 151:5eaa88a5bcc7 183 #define TSC_MCV_255 ((uint32_t)(0U << 5U))
<> 151:5eaa88a5bcc7 184 #define TSC_MCV_511 ((uint32_t)(1U << 5U))
<> 151:5eaa88a5bcc7 185 #define TSC_MCV_1023 ((uint32_t)(2U << 5U))
<> 151:5eaa88a5bcc7 186 #define TSC_MCV_2047 ((uint32_t)(3U << 5U))
<> 151:5eaa88a5bcc7 187 #define TSC_MCV_4095 ((uint32_t)(4U << 5U))
<> 151:5eaa88a5bcc7 188 #define TSC_MCV_8191 ((uint32_t)(5U << 5U))
<> 151:5eaa88a5bcc7 189 #define TSC_MCV_16383 ((uint32_t)(6U << 5U))
<> 144:ef7eb2e8f9f7 190
<> 151:5eaa88a5bcc7 191 #define TSC_IODEF_OUT_PP_LOW ((uint32_t)0U)
<> 144:ef7eb2e8f9f7 192 #define TSC_IODEF_IN_FLOAT (TSC_CR_IODEF)
<> 144:ef7eb2e8f9f7 193
<> 151:5eaa88a5bcc7 194 #define TSC_SYNC_POLARITY_FALLING ((uint32_t)0U)
<> 144:ef7eb2e8f9f7 195 #define TSC_SYNC_POLARITY_RISING (TSC_CR_SYNCPOL)
<> 144:ef7eb2e8f9f7 196
<> 151:5eaa88a5bcc7 197 #define TSC_ACQ_MODE_NORMAL ((uint32_t)0U)
<> 144:ef7eb2e8f9f7 198 #define TSC_ACQ_MODE_SYNCHRO (TSC_CR_AM)
<> 144:ef7eb2e8f9f7 199
<> 151:5eaa88a5bcc7 200 #define TSC_IOMODE_UNUSED ((uint32_t)0U)
<> 151:5eaa88a5bcc7 201 #define TSC_IOMODE_CHANNEL ((uint32_t)1U)
<> 151:5eaa88a5bcc7 202 #define TSC_IOMODE_SHIELD ((uint32_t)2U)
<> 151:5eaa88a5bcc7 203 #define TSC_IOMODE_SAMPLING ((uint32_t)3U)
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 /** @defgroup TSC_interrupts_definition TSC Interrupts Definition
<> 144:ef7eb2e8f9f7 206 * @{
<> 144:ef7eb2e8f9f7 207 */
<> 144:ef7eb2e8f9f7 208 #define TSC_IT_EOA ((uint32_t)TSC_IER_EOAIE)
<> 144:ef7eb2e8f9f7 209 #define TSC_IT_MCE ((uint32_t)TSC_IER_MCEIE)
<> 144:ef7eb2e8f9f7 210 /**
<> 144:ef7eb2e8f9f7 211 * @}
<> 144:ef7eb2e8f9f7 212 */
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 /** @defgroup TSC_flags_definition TSC Flags Definition
<> 144:ef7eb2e8f9f7 215 * @{
<> 144:ef7eb2e8f9f7 216 */
<> 144:ef7eb2e8f9f7 217 #define TSC_FLAG_EOA ((uint32_t)TSC_ISR_EOAF)
<> 144:ef7eb2e8f9f7 218 #define TSC_FLAG_MCE ((uint32_t)TSC_ISR_MCEF)
<> 144:ef7eb2e8f9f7 219 /**
<> 144:ef7eb2e8f9f7 220 * @}
<> 144:ef7eb2e8f9f7 221 */
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 #define TSC_NB_OF_GROUPS (8)
<> 144:ef7eb2e8f9f7 224
<> 151:5eaa88a5bcc7 225 #define TSC_GROUP1 ((uint32_t)0x00000001U)
<> 151:5eaa88a5bcc7 226 #define TSC_GROUP2 ((uint32_t)0x00000002U)
<> 151:5eaa88a5bcc7 227 #define TSC_GROUP3 ((uint32_t)0x00000004U)
<> 151:5eaa88a5bcc7 228 #define TSC_GROUP4 ((uint32_t)0x00000008U)
<> 151:5eaa88a5bcc7 229 #define TSC_GROUP5 ((uint32_t)0x00000010U)
<> 151:5eaa88a5bcc7 230 #define TSC_GROUP6 ((uint32_t)0x00000020U)
<> 151:5eaa88a5bcc7 231 #define TSC_GROUP7 ((uint32_t)0x00000040U)
<> 151:5eaa88a5bcc7 232 #define TSC_GROUP8 ((uint32_t)0x00000080U)
<> 151:5eaa88a5bcc7 233 #define TSC_ALL_GROUPS ((uint32_t)0x000000FFU)
<> 144:ef7eb2e8f9f7 234
<> 151:5eaa88a5bcc7 235 #define TSC_GROUP1_IDX ((uint32_t)0U)
<> 151:5eaa88a5bcc7 236 #define TSC_GROUP2_IDX ((uint32_t)1U)
<> 151:5eaa88a5bcc7 237 #define TSC_GROUP3_IDX ((uint32_t)2U)
<> 151:5eaa88a5bcc7 238 #define TSC_GROUP4_IDX ((uint32_t)3U)
<> 151:5eaa88a5bcc7 239 #define TSC_GROUP5_IDX ((uint32_t)4U)
<> 151:5eaa88a5bcc7 240 #define TSC_GROUP6_IDX ((uint32_t)5U)
<> 151:5eaa88a5bcc7 241 #define TSC_GROUP7_IDX ((uint32_t)6U)
<> 151:5eaa88a5bcc7 242 #define TSC_GROUP8_IDX ((uint32_t)7U)
<> 144:ef7eb2e8f9f7 243
<> 151:5eaa88a5bcc7 244 #define TSC_GROUP1_IO1 ((uint32_t)0x00000001U)
<> 151:5eaa88a5bcc7 245 #define TSC_GROUP1_IO2 ((uint32_t)0x00000002U)
<> 151:5eaa88a5bcc7 246 #define TSC_GROUP1_IO3 ((uint32_t)0x00000004U)
<> 151:5eaa88a5bcc7 247 #define TSC_GROUP1_IO4 ((uint32_t)0x00000008U)
<> 151:5eaa88a5bcc7 248 #define TSC_GROUP1_ALL_IOS ((uint32_t)0x0000000FU)
<> 144:ef7eb2e8f9f7 249
<> 151:5eaa88a5bcc7 250 #define TSC_GROUP2_IO1 ((uint32_t)0x00000010U)
<> 151:5eaa88a5bcc7 251 #define TSC_GROUP2_IO2 ((uint32_t)0x00000020U)
<> 151:5eaa88a5bcc7 252 #define TSC_GROUP2_IO3 ((uint32_t)0x00000040U)
<> 151:5eaa88a5bcc7 253 #define TSC_GROUP2_IO4 ((uint32_t)0x00000080U)
<> 151:5eaa88a5bcc7 254 #define TSC_GROUP2_ALL_IOS ((uint32_t)0x000000F0U)
<> 144:ef7eb2e8f9f7 255
<> 151:5eaa88a5bcc7 256 #define TSC_GROUP3_IO1 ((uint32_t)0x00000100U)
<> 151:5eaa88a5bcc7 257 #define TSC_GROUP3_IO2 ((uint32_t)0x00000200U)
<> 151:5eaa88a5bcc7 258 #define TSC_GROUP3_IO3 ((uint32_t)0x00000400U)
<> 151:5eaa88a5bcc7 259 #define TSC_GROUP3_IO4 ((uint32_t)0x00000800U)
<> 151:5eaa88a5bcc7 260 #define TSC_GROUP3_ALL_IOS ((uint32_t)0x00000F00U)
<> 144:ef7eb2e8f9f7 261
<> 151:5eaa88a5bcc7 262 #define TSC_GROUP4_IO1 ((uint32_t)0x00001000U)
<> 151:5eaa88a5bcc7 263 #define TSC_GROUP4_IO2 ((uint32_t)0x00002000U)
<> 151:5eaa88a5bcc7 264 #define TSC_GROUP4_IO3 ((uint32_t)0x00004000U)
<> 151:5eaa88a5bcc7 265 #define TSC_GROUP4_IO4 ((uint32_t)0x00008000U)
<> 151:5eaa88a5bcc7 266 #define TSC_GROUP4_ALL_IOS ((uint32_t)0x0000F000U)
<> 144:ef7eb2e8f9f7 267
<> 151:5eaa88a5bcc7 268 #define TSC_GROUP5_IO1 ((uint32_t)0x00010000U)
<> 151:5eaa88a5bcc7 269 #define TSC_GROUP5_IO2 ((uint32_t)0x00020000U)
<> 151:5eaa88a5bcc7 270 #define TSC_GROUP5_IO3 ((uint32_t)0x00040000U)
<> 151:5eaa88a5bcc7 271 #define TSC_GROUP5_IO4 ((uint32_t)0x00080000U)
<> 151:5eaa88a5bcc7 272 #define TSC_GROUP5_ALL_IOS ((uint32_t)0x000F0000U)
<> 144:ef7eb2e8f9f7 273
<> 151:5eaa88a5bcc7 274 #define TSC_GROUP6_IO1 ((uint32_t)0x00100000U)
<> 151:5eaa88a5bcc7 275 #define TSC_GROUP6_IO2 ((uint32_t)0x00200000U)
<> 151:5eaa88a5bcc7 276 #define TSC_GROUP6_IO3 ((uint32_t)0x00400000U)
<> 151:5eaa88a5bcc7 277 #define TSC_GROUP6_IO4 ((uint32_t)0x00800000U)
<> 151:5eaa88a5bcc7 278 #define TSC_GROUP6_ALL_IOS ((uint32_t)0x00F00000U)
<> 144:ef7eb2e8f9f7 279
<> 151:5eaa88a5bcc7 280 #define TSC_GROUP7_IO1 ((uint32_t)0x01000000U)
<> 151:5eaa88a5bcc7 281 #define TSC_GROUP7_IO2 ((uint32_t)0x02000000U)
<> 151:5eaa88a5bcc7 282 #define TSC_GROUP7_IO3 ((uint32_t)0x04000000U)
<> 151:5eaa88a5bcc7 283 #define TSC_GROUP7_IO4 ((uint32_t)0x08000000U)
<> 151:5eaa88a5bcc7 284 #define TSC_GROUP7_ALL_IOS ((uint32_t)0x0F000000U)
<> 144:ef7eb2e8f9f7 285
<> 151:5eaa88a5bcc7 286 #define TSC_GROUP8_IO1 ((uint32_t)0x10000000U)
<> 151:5eaa88a5bcc7 287 #define TSC_GROUP8_IO2 ((uint32_t)0x20000000U)
<> 151:5eaa88a5bcc7 288 #define TSC_GROUP8_IO3 ((uint32_t)0x40000000U)
<> 151:5eaa88a5bcc7 289 #define TSC_GROUP8_IO4 ((uint32_t)0x80000000U)
<> 151:5eaa88a5bcc7 290 #define TSC_GROUP8_ALL_IOS ((uint32_t)0xF0000000U)
<> 144:ef7eb2e8f9f7 291
<> 151:5eaa88a5bcc7 292 #define TSC_ALL_GROUPS_ALL_IOS ((uint32_t)0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 293
<> 144:ef7eb2e8f9f7 294 /**
<> 144:ef7eb2e8f9f7 295 * @}
<> 144:ef7eb2e8f9f7 296 */
<> 144:ef7eb2e8f9f7 297
<> 144:ef7eb2e8f9f7 298 /* Exported macros -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300 /** @defgroup TSC_Exported_Macros TSC Exported Macros
<> 144:ef7eb2e8f9f7 301 * @{
<> 144:ef7eb2e8f9f7 302 */
<> 144:ef7eb2e8f9f7 303
<> 144:ef7eb2e8f9f7 304 /** @brief Reset TSC handle state
<> 144:ef7eb2e8f9f7 305 * @param __HANDLE__: TSC handle
<> 144:ef7eb2e8f9f7 306 * @retval None
<> 144:ef7eb2e8f9f7 307 */
<> 144:ef7eb2e8f9f7 308 #define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TSC_STATE_RESET)
<> 144:ef7eb2e8f9f7 309
<> 144:ef7eb2e8f9f7 310 /**
<> 144:ef7eb2e8f9f7 311 * @brief Enable the TSC peripheral.
<> 144:ef7eb2e8f9f7 312 * @param __HANDLE__: TSC handle
<> 144:ef7eb2e8f9f7 313 * @retval None
<> 144:ef7eb2e8f9f7 314 */
<> 144:ef7eb2e8f9f7 315 #define __HAL_TSC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE)
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 /**
<> 144:ef7eb2e8f9f7 318 * @brief Disable the TSC peripheral.
<> 144:ef7eb2e8f9f7 319 * @param __HANDLE__: TSC handle
<> 144:ef7eb2e8f9f7 320 * @retval None
<> 144:ef7eb2e8f9f7 321 */
<> 144:ef7eb2e8f9f7 322 #define __HAL_TSC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_TSCE))
<> 144:ef7eb2e8f9f7 323
<> 144:ef7eb2e8f9f7 324 /**
<> 144:ef7eb2e8f9f7 325 * @brief Start acquisition
<> 144:ef7eb2e8f9f7 326 * @param __HANDLE__: TSC handle
<> 144:ef7eb2e8f9f7 327 * @retval None
<> 144:ef7eb2e8f9f7 328 */
<> 144:ef7eb2e8f9f7 329 #define __HAL_TSC_START_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_START)
<> 144:ef7eb2e8f9f7 330
<> 144:ef7eb2e8f9f7 331 /**
<> 144:ef7eb2e8f9f7 332 * @brief Stop acquisition
<> 144:ef7eb2e8f9f7 333 * @param __HANDLE__: TSC handle
<> 144:ef7eb2e8f9f7 334 * @retval None
<> 144:ef7eb2e8f9f7 335 */
<> 144:ef7eb2e8f9f7 336 #define __HAL_TSC_STOP_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_START))
<> 144:ef7eb2e8f9f7 337
<> 144:ef7eb2e8f9f7 338 /**
<> 144:ef7eb2e8f9f7 339 * @brief Set IO default mode to output push-pull low
<> 144:ef7eb2e8f9f7 340 * @param __HANDLE__: TSC handle
<> 144:ef7eb2e8f9f7 341 * @retval None
<> 144:ef7eb2e8f9f7 342 */
<> 144:ef7eb2e8f9f7 343 #define __HAL_TSC_SET_IODEF_OUTPPLOW(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_IODEF))
<> 144:ef7eb2e8f9f7 344
<> 144:ef7eb2e8f9f7 345 /**
<> 144:ef7eb2e8f9f7 346 * @brief Set IO default mode to input floating
<> 144:ef7eb2e8f9f7 347 * @param __HANDLE__: TSC handle
<> 144:ef7eb2e8f9f7 348 * @retval None
<> 144:ef7eb2e8f9f7 349 */
<> 144:ef7eb2e8f9f7 350 #define __HAL_TSC_SET_IODEF_INFLOAT(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF)
<> 144:ef7eb2e8f9f7 351
<> 144:ef7eb2e8f9f7 352 /**
<> 144:ef7eb2e8f9f7 353 * @brief Set synchronization polarity to falling edge
<> 144:ef7eb2e8f9f7 354 * @param __HANDLE__: TSC handle
<> 144:ef7eb2e8f9f7 355 * @retval None
<> 144:ef7eb2e8f9f7 356 */
<> 144:ef7eb2e8f9f7 357 #define __HAL_TSC_SET_SYNC_POL_FALL(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_SYNCPOL))
<> 144:ef7eb2e8f9f7 358
<> 144:ef7eb2e8f9f7 359 /**
<> 144:ef7eb2e8f9f7 360 * @brief Set synchronization polarity to rising edge and high level
<> 144:ef7eb2e8f9f7 361 * @param __HANDLE__: TSC handle
<> 144:ef7eb2e8f9f7 362 * @retval None
<> 144:ef7eb2e8f9f7 363 */
<> 144:ef7eb2e8f9f7 364 #define __HAL_TSC_SET_SYNC_POL_RISE_HIGH(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL)
<> 144:ef7eb2e8f9f7 365
<> 144:ef7eb2e8f9f7 366 /**
<> 144:ef7eb2e8f9f7 367 * @brief Enable TSC interrupt.
<> 144:ef7eb2e8f9f7 368 * @param __HANDLE__: TSC handle
<> 144:ef7eb2e8f9f7 369 * @param __INTERRUPT__: TSC interrupt
<> 144:ef7eb2e8f9f7 370 * @retval None
<> 144:ef7eb2e8f9f7 371 */
<> 144:ef7eb2e8f9f7 372 #define __HAL_TSC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374 /**
<> 144:ef7eb2e8f9f7 375 * @brief Disable TSC interrupt.
<> 144:ef7eb2e8f9f7 376 * @param __HANDLE__: TSC handle
<> 144:ef7eb2e8f9f7 377 * @param __INTERRUPT__: TSC interrupt
<> 144:ef7eb2e8f9f7 378 * @retval None
<> 144:ef7eb2e8f9f7 379 */
<> 144:ef7eb2e8f9f7 380 #define __HAL_TSC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (uint32_t)(~(__INTERRUPT__)))
<> 144:ef7eb2e8f9f7 381
<> 144:ef7eb2e8f9f7 382 /** @brief Check if the specified TSC interrupt source is enabled or disabled.
<> 144:ef7eb2e8f9f7 383 * @param __HANDLE__: TSC Handle
<> 144:ef7eb2e8f9f7 384 * @param __INTERRUPT__: TSC interrupt
<> 144:ef7eb2e8f9f7 385 * @retval SET or RESET
<> 144:ef7eb2e8f9f7 386 */
<> 144:ef7eb2e8f9f7 387 #define __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
<> 144:ef7eb2e8f9f7 388
<> 144:ef7eb2e8f9f7 389 /**
<> 144:ef7eb2e8f9f7 390 * @brief Get the selected TSC's flag status.
<> 144:ef7eb2e8f9f7 391 * @param __HANDLE__: TSC handle
<> 144:ef7eb2e8f9f7 392 * @param __FLAG__: TSC flag
<> 144:ef7eb2e8f9f7 393 * @retval SET or RESET
<> 144:ef7eb2e8f9f7 394 */
<> 144:ef7eb2e8f9f7 395 #define __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
<> 144:ef7eb2e8f9f7 396
<> 144:ef7eb2e8f9f7 397 /**
<> 144:ef7eb2e8f9f7 398 * @brief Clear the TSC's pending flag.
<> 144:ef7eb2e8f9f7 399 * @param __HANDLE__: TSC handle
<> 144:ef7eb2e8f9f7 400 * @param __FLAG__: TSC flag
<> 144:ef7eb2e8f9f7 401 * @retval None
<> 144:ef7eb2e8f9f7 402 */
<> 144:ef7eb2e8f9f7 403 #define __HAL_TSC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
<> 144:ef7eb2e8f9f7 404
<> 144:ef7eb2e8f9f7 405 /**
<> 144:ef7eb2e8f9f7 406 * @brief Enable schmitt trigger hysteresis on a group of IOs
<> 144:ef7eb2e8f9f7 407 * @param __HANDLE__: TSC handle
<> 144:ef7eb2e8f9f7 408 * @param __GX_IOY_MASK__: IOs mask
<> 144:ef7eb2e8f9f7 409 * @retval None
<> 144:ef7eb2e8f9f7 410 */
<> 144:ef7eb2e8f9f7 411 #define __HAL_TSC_ENABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__))
<> 144:ef7eb2e8f9f7 412
<> 144:ef7eb2e8f9f7 413 /**
<> 144:ef7eb2e8f9f7 414 * @brief Disable schmitt trigger hysteresis on a group of IOs
<> 144:ef7eb2e8f9f7 415 * @param __HANDLE__: TSC handle
<> 144:ef7eb2e8f9f7 416 * @param __GX_IOY_MASK__: IOs mask
<> 144:ef7eb2e8f9f7 417 * @retval None
<> 144:ef7eb2e8f9f7 418 */
<> 144:ef7eb2e8f9f7 419 #define __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR &= (uint32_t)(~(__GX_IOY_MASK__)))
<> 144:ef7eb2e8f9f7 420
<> 144:ef7eb2e8f9f7 421 /**
<> 144:ef7eb2e8f9f7 422 * @brief Open analog switch on a group of IOs
<> 144:ef7eb2e8f9f7 423 * @param __HANDLE__: TSC handle
<> 144:ef7eb2e8f9f7 424 * @param __GX_IOY_MASK__: IOs mask
<> 144:ef7eb2e8f9f7 425 * @retval None
<> 144:ef7eb2e8f9f7 426 */
<> 144:ef7eb2e8f9f7 427 #define __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR &= (uint32_t)(~(__GX_IOY_MASK__)))
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429 /**
<> 144:ef7eb2e8f9f7 430 * @brief Close analog switch on a group of IOs
<> 144:ef7eb2e8f9f7 431 * @param __HANDLE__: TSC handle
<> 144:ef7eb2e8f9f7 432 * @param __GX_IOY_MASK__: IOs mask
<> 144:ef7eb2e8f9f7 433 * @retval None
<> 144:ef7eb2e8f9f7 434 */
<> 144:ef7eb2e8f9f7 435 #define __HAL_TSC_CLOSE_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR |= (__GX_IOY_MASK__))
<> 144:ef7eb2e8f9f7 436
<> 144:ef7eb2e8f9f7 437 /**
<> 144:ef7eb2e8f9f7 438 * @brief Enable a group of IOs in channel mode
<> 144:ef7eb2e8f9f7 439 * @param __HANDLE__: TSC handle
<> 144:ef7eb2e8f9f7 440 * @param __GX_IOY_MASK__: IOs mask
<> 144:ef7eb2e8f9f7 441 * @retval None
<> 144:ef7eb2e8f9f7 442 */
<> 144:ef7eb2e8f9f7 443 #define __HAL_TSC_ENABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__))
<> 144:ef7eb2e8f9f7 444
<> 144:ef7eb2e8f9f7 445 /**
<> 144:ef7eb2e8f9f7 446 * @brief Disable a group of channel IOs
<> 144:ef7eb2e8f9f7 447 * @param __HANDLE__: TSC handle
<> 144:ef7eb2e8f9f7 448 * @param __GX_IOY_MASK__: IOs mask
<> 144:ef7eb2e8f9f7 449 * @retval None
<> 144:ef7eb2e8f9f7 450 */
<> 144:ef7eb2e8f9f7 451 #define __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR &= (uint32_t)(~(__GX_IOY_MASK__)))
<> 144:ef7eb2e8f9f7 452
<> 144:ef7eb2e8f9f7 453 /**
<> 144:ef7eb2e8f9f7 454 * @brief Enable a group of IOs in sampling mode
<> 144:ef7eb2e8f9f7 455 * @param __HANDLE__: TSC handle
<> 144:ef7eb2e8f9f7 456 * @param __GX_IOY_MASK__: IOs mask
<> 144:ef7eb2e8f9f7 457 * @retval None
<> 144:ef7eb2e8f9f7 458 */
<> 144:ef7eb2e8f9f7 459 #define __HAL_TSC_ENABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__))
<> 144:ef7eb2e8f9f7 460
<> 144:ef7eb2e8f9f7 461 /**
<> 144:ef7eb2e8f9f7 462 * @brief Disable a group of sampling IOs
<> 144:ef7eb2e8f9f7 463 * @param __HANDLE__: TSC handle
<> 144:ef7eb2e8f9f7 464 * @param __GX_IOY_MASK__: IOs mask
<> 144:ef7eb2e8f9f7 465 * @retval None
<> 144:ef7eb2e8f9f7 466 */
<> 144:ef7eb2e8f9f7 467 #define __HAL_TSC_DISABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR &= (uint32_t)(~(__GX_IOY_MASK__)))
<> 144:ef7eb2e8f9f7 468
<> 144:ef7eb2e8f9f7 469 /**
<> 144:ef7eb2e8f9f7 470 * @brief Enable acquisition groups
<> 144:ef7eb2e8f9f7 471 * @param __HANDLE__: TSC handle
<> 144:ef7eb2e8f9f7 472 * @param __GX_MASK__: Groups mask
<> 144:ef7eb2e8f9f7 473 * @retval None
<> 144:ef7eb2e8f9f7 474 */
<> 144:ef7eb2e8f9f7 475 #define __HAL_TSC_ENABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR |= (__GX_MASK__))
<> 144:ef7eb2e8f9f7 476
<> 144:ef7eb2e8f9f7 477 /**
<> 144:ef7eb2e8f9f7 478 * @brief Disable acquisition groups
<> 144:ef7eb2e8f9f7 479 * @param __HANDLE__: TSC handle
<> 144:ef7eb2e8f9f7 480 * @param __GX_MASK__: Groups mask
<> 144:ef7eb2e8f9f7 481 * @retval None
<> 144:ef7eb2e8f9f7 482 */
<> 144:ef7eb2e8f9f7 483 #define __HAL_TSC_DISABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR &= (uint32_t)(~(__GX_MASK__)))
<> 144:ef7eb2e8f9f7 484
<> 144:ef7eb2e8f9f7 485 /** @brief Gets acquisition group status
<> 144:ef7eb2e8f9f7 486 * @param __HANDLE__: TSC Handle
<> 144:ef7eb2e8f9f7 487 * @param __GX_INDEX__: Group index
<> 144:ef7eb2e8f9f7 488 * @retval SET or RESET
<> 144:ef7eb2e8f9f7 489 */
<> 144:ef7eb2e8f9f7 490 #define __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) \
<> 151:5eaa88a5bcc7 491 ((((__HANDLE__)->Instance->IOGCSR & (uint32_t)((uint32_t)1U << ((__GX_INDEX__) + (uint32_t)16U))) == (uint32_t)((uint32_t)1U << ((__GX_INDEX__) + (uint32_t)16U))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING)
<> 144:ef7eb2e8f9f7 492
<> 144:ef7eb2e8f9f7 493 /**
<> 144:ef7eb2e8f9f7 494 * @}
<> 144:ef7eb2e8f9f7 495 */
<> 144:ef7eb2e8f9f7 496
<> 144:ef7eb2e8f9f7 497 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 498
<> 144:ef7eb2e8f9f7 499 /** @defgroup TSC_Private_Macros TSC Private Macros
<> 144:ef7eb2e8f9f7 500 * @{
<> 144:ef7eb2e8f9f7 501 */
<> 144:ef7eb2e8f9f7 502 #define IS_TSC_ALL_INSTANCE(PERIPH) ((PERIPH) == TSC)
<> 144:ef7eb2e8f9f7 503
<> 144:ef7eb2e8f9f7 504 #define IS_TSC_CTPH(VAL) (((VAL) == TSC_CTPH_1CYCLE) || \
<> 144:ef7eb2e8f9f7 505 ((VAL) == TSC_CTPH_2CYCLES) || \
<> 144:ef7eb2e8f9f7 506 ((VAL) == TSC_CTPH_3CYCLES) || \
<> 144:ef7eb2e8f9f7 507 ((VAL) == TSC_CTPH_4CYCLES) || \
<> 144:ef7eb2e8f9f7 508 ((VAL) == TSC_CTPH_5CYCLES) || \
<> 144:ef7eb2e8f9f7 509 ((VAL) == TSC_CTPH_6CYCLES) || \
<> 144:ef7eb2e8f9f7 510 ((VAL) == TSC_CTPH_7CYCLES) || \
<> 144:ef7eb2e8f9f7 511 ((VAL) == TSC_CTPH_8CYCLES) || \
<> 144:ef7eb2e8f9f7 512 ((VAL) == TSC_CTPH_9CYCLES) || \
<> 144:ef7eb2e8f9f7 513 ((VAL) == TSC_CTPH_10CYCLES) || \
<> 144:ef7eb2e8f9f7 514 ((VAL) == TSC_CTPH_11CYCLES) || \
<> 144:ef7eb2e8f9f7 515 ((VAL) == TSC_CTPH_12CYCLES) || \
<> 144:ef7eb2e8f9f7 516 ((VAL) == TSC_CTPH_13CYCLES) || \
<> 144:ef7eb2e8f9f7 517 ((VAL) == TSC_CTPH_14CYCLES) || \
<> 144:ef7eb2e8f9f7 518 ((VAL) == TSC_CTPH_15CYCLES) || \
<> 144:ef7eb2e8f9f7 519 ((VAL) == TSC_CTPH_16CYCLES))
<> 144:ef7eb2e8f9f7 520 #define IS_TSC_CTPL(VAL) (((VAL) == TSC_CTPL_1CYCLE) || \
<> 144:ef7eb2e8f9f7 521 ((VAL) == TSC_CTPL_2CYCLES) || \
<> 144:ef7eb2e8f9f7 522 ((VAL) == TSC_CTPL_3CYCLES) || \
<> 144:ef7eb2e8f9f7 523 ((VAL) == TSC_CTPL_4CYCLES) || \
<> 144:ef7eb2e8f9f7 524 ((VAL) == TSC_CTPL_5CYCLES) || \
<> 144:ef7eb2e8f9f7 525 ((VAL) == TSC_CTPL_6CYCLES) || \
<> 144:ef7eb2e8f9f7 526 ((VAL) == TSC_CTPL_7CYCLES) || \
<> 144:ef7eb2e8f9f7 527 ((VAL) == TSC_CTPL_8CYCLES) || \
<> 144:ef7eb2e8f9f7 528 ((VAL) == TSC_CTPL_9CYCLES) || \
<> 144:ef7eb2e8f9f7 529 ((VAL) == TSC_CTPL_10CYCLES) || \
<> 144:ef7eb2e8f9f7 530 ((VAL) == TSC_CTPL_11CYCLES) || \
<> 144:ef7eb2e8f9f7 531 ((VAL) == TSC_CTPL_12CYCLES) || \
<> 144:ef7eb2e8f9f7 532 ((VAL) == TSC_CTPL_13CYCLES) || \
<> 144:ef7eb2e8f9f7 533 ((VAL) == TSC_CTPL_14CYCLES) || \
<> 144:ef7eb2e8f9f7 534 ((VAL) == TSC_CTPL_15CYCLES) || \
<> 144:ef7eb2e8f9f7 535 ((VAL) == TSC_CTPL_16CYCLES))
<> 144:ef7eb2e8f9f7 536
<> 144:ef7eb2e8f9f7 537 #define IS_TSC_SS(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE))
<> 144:ef7eb2e8f9f7 538
<> 151:5eaa88a5bcc7 539 #define IS_TSC_SSD(VAL) (((VAL) == 0U) || (((VAL) > 0U) && ((VAL) < 128U)))
<> 144:ef7eb2e8f9f7 540 #define IS_TSC_SS_PRESC(VAL) (((VAL) == TSC_SS_PRESC_DIV1) || ((VAL) == TSC_SS_PRESC_DIV2))
<> 144:ef7eb2e8f9f7 541 #define IS_TSC_PG_PRESC(VAL) (((VAL) == TSC_PG_PRESC_DIV1) || \
<> 144:ef7eb2e8f9f7 542 ((VAL) == TSC_PG_PRESC_DIV2) || \
<> 144:ef7eb2e8f9f7 543 ((VAL) == TSC_PG_PRESC_DIV4) || \
<> 144:ef7eb2e8f9f7 544 ((VAL) == TSC_PG_PRESC_DIV8) || \
<> 144:ef7eb2e8f9f7 545 ((VAL) == TSC_PG_PRESC_DIV16) || \
<> 144:ef7eb2e8f9f7 546 ((VAL) == TSC_PG_PRESC_DIV32) || \
<> 144:ef7eb2e8f9f7 547 ((VAL) == TSC_PG_PRESC_DIV64) || \
<> 144:ef7eb2e8f9f7 548 ((VAL) == TSC_PG_PRESC_DIV128))
<> 144:ef7eb2e8f9f7 549
<> 144:ef7eb2e8f9f7 550 #define IS_TSC_MCV(VAL) (((VAL) == TSC_MCV_255) || \
<> 144:ef7eb2e8f9f7 551 ((VAL) == TSC_MCV_511) || \
<> 144:ef7eb2e8f9f7 552 ((VAL) == TSC_MCV_1023) || \
<> 144:ef7eb2e8f9f7 553 ((VAL) == TSC_MCV_2047) || \
<> 144:ef7eb2e8f9f7 554 ((VAL) == TSC_MCV_4095) || \
<> 144:ef7eb2e8f9f7 555 ((VAL) == TSC_MCV_8191) || \
<> 144:ef7eb2e8f9f7 556 ((VAL) == TSC_MCV_16383))
<> 144:ef7eb2e8f9f7 557 #define IS_TSC_IODEF(VAL) (((VAL) == TSC_IODEF_OUT_PP_LOW) || ((VAL) == TSC_IODEF_IN_FLOAT))
<> 144:ef7eb2e8f9f7 558 #define IS_TSC_SYNC_POL(VAL) (((VAL) == TSC_SYNC_POLARITY_FALLING) || ((VAL) == TSC_SYNC_POLARITY_RISING))
<> 144:ef7eb2e8f9f7 559 #define IS_TSC_ACQ_MODE(VAL) (((VAL) == TSC_ACQ_MODE_NORMAL) || ((VAL) == TSC_ACQ_MODE_SYNCHRO))
<> 144:ef7eb2e8f9f7 560 #define IS_TSC_IOMODE(VAL) (((VAL) == TSC_IOMODE_UNUSED) || \
<> 144:ef7eb2e8f9f7 561 ((VAL) == TSC_IOMODE_CHANNEL) || \
<> 144:ef7eb2e8f9f7 562 ((VAL) == TSC_IOMODE_SHIELD) || \
<> 144:ef7eb2e8f9f7 563 ((VAL) == TSC_IOMODE_SAMPLING))
<> 144:ef7eb2e8f9f7 564 #define IS_TSC_MCE_IT(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE))
<> 144:ef7eb2e8f9f7 565
<> 151:5eaa88a5bcc7 566 #define IS_TSC_GROUP_INDEX(VAL) (((VAL) == 0U) || (((VAL) > 0U) && ((VAL) < TSC_NB_OF_GROUPS)))
<> 144:ef7eb2e8f9f7 567
<> 144:ef7eb2e8f9f7 568 /**
<> 144:ef7eb2e8f9f7 569 * @}
<> 144:ef7eb2e8f9f7 570 */
<> 144:ef7eb2e8f9f7 571
<> 144:ef7eb2e8f9f7 572 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 573
<> 144:ef7eb2e8f9f7 574 /** @defgroup TSC_Exported_Functions TSC Exported Functions
<> 144:ef7eb2e8f9f7 575 * @{
<> 144:ef7eb2e8f9f7 576 */
<> 144:ef7eb2e8f9f7 577
<> 144:ef7eb2e8f9f7 578 /** @defgroup TSC_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 579 * @{
<> 144:ef7eb2e8f9f7 580 */
<> 144:ef7eb2e8f9f7 581 /* Initialization and de-initialization functions *****************************/
<> 144:ef7eb2e8f9f7 582 HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef* htsc);
<> 144:ef7eb2e8f9f7 583 HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef *htsc);
<> 144:ef7eb2e8f9f7 584 void HAL_TSC_MspInit(TSC_HandleTypeDef* htsc);
<> 144:ef7eb2e8f9f7 585 void HAL_TSC_MspDeInit(TSC_HandleTypeDef* htsc);
<> 144:ef7eb2e8f9f7 586 /**
<> 144:ef7eb2e8f9f7 587 * @}
<> 144:ef7eb2e8f9f7 588 */
<> 144:ef7eb2e8f9f7 589
<> 144:ef7eb2e8f9f7 590 /** @defgroup HAL_TSC_Exported_Functions_Group2 IO operation functions
<> 144:ef7eb2e8f9f7 591 * @{
<> 144:ef7eb2e8f9f7 592 */
<> 144:ef7eb2e8f9f7 593 /* IO operation functions *****************************************************/
<> 144:ef7eb2e8f9f7 594 HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef* htsc);
<> 144:ef7eb2e8f9f7 595 HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef* htsc);
<> 144:ef7eb2e8f9f7 596 HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef* htsc);
<> 144:ef7eb2e8f9f7 597 HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef* htsc);
<> 144:ef7eb2e8f9f7 598 HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef* htsc);
<> 144:ef7eb2e8f9f7 599 TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef* htsc, uint32_t gx_index);
<> 144:ef7eb2e8f9f7 600 uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef* htsc, uint32_t gx_index);
<> 144:ef7eb2e8f9f7 601
<> 144:ef7eb2e8f9f7 602 /**
<> 144:ef7eb2e8f9f7 603 * @}
<> 144:ef7eb2e8f9f7 604 */
<> 144:ef7eb2e8f9f7 605 /** @defgroup HAL_TSC_Exported_Functions_Group3 Peripheral Control functions
<> 144:ef7eb2e8f9f7 606 * @{
<> 144:ef7eb2e8f9f7 607 */
<> 144:ef7eb2e8f9f7 608 /* Peripheral Control functions ***********************************************/
<> 144:ef7eb2e8f9f7 609 HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef* htsc, TSC_IOConfigTypeDef* config);
<> 144:ef7eb2e8f9f7 610 HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef* htsc, uint32_t choice);
<> 144:ef7eb2e8f9f7 611
<> 144:ef7eb2e8f9f7 612 /**
<> 144:ef7eb2e8f9f7 613 * @}
<> 144:ef7eb2e8f9f7 614 */
<> 144:ef7eb2e8f9f7 615 /** @defgroup HAL_TSC_Exported_Functions_Group4 State callback and error Functions
<> 144:ef7eb2e8f9f7 616 * @{
<> 144:ef7eb2e8f9f7 617 */
<> 144:ef7eb2e8f9f7 618 /* Peripheral State and Error functions ***************************************/
<> 144:ef7eb2e8f9f7 619 HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef* htsc);
<> 144:ef7eb2e8f9f7 620 void HAL_TSC_IRQHandler(TSC_HandleTypeDef* htsc);
<> 144:ef7eb2e8f9f7 621
<> 144:ef7eb2e8f9f7 622 /* Callback functions *********************************************************/
<> 144:ef7eb2e8f9f7 623 void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef* htsc);
<> 144:ef7eb2e8f9f7 624 void HAL_TSC_ErrorCallback(TSC_HandleTypeDef* htsc);
<> 144:ef7eb2e8f9f7 625
<> 144:ef7eb2e8f9f7 626 /**
<> 144:ef7eb2e8f9f7 627 * @}
<> 144:ef7eb2e8f9f7 628 */
<> 144:ef7eb2e8f9f7 629
<> 144:ef7eb2e8f9f7 630 /**
<> 144:ef7eb2e8f9f7 631 * @}
<> 144:ef7eb2e8f9f7 632 */
<> 144:ef7eb2e8f9f7 633
<> 144:ef7eb2e8f9f7 634 /* Define the private group ***********************************/
<> 144:ef7eb2e8f9f7 635 /**************************************************************/
<> 144:ef7eb2e8f9f7 636 /** @defgroup TSC_Private TSC Private
<> 144:ef7eb2e8f9f7 637 * @{
<> 144:ef7eb2e8f9f7 638 */
<> 144:ef7eb2e8f9f7 639 /**
<> 144:ef7eb2e8f9f7 640 * @}
<> 144:ef7eb2e8f9f7 641 */
<> 144:ef7eb2e8f9f7 642 /**************************************************************/
<> 144:ef7eb2e8f9f7 643
<> 144:ef7eb2e8f9f7 644 /**
<> 144:ef7eb2e8f9f7 645 * @}
<> 144:ef7eb2e8f9f7 646 */
<> 144:ef7eb2e8f9f7 647
<> 144:ef7eb2e8f9f7 648 /**
<> 144:ef7eb2e8f9f7 649 * @}
<> 144:ef7eb2e8f9f7 650 */
<> 144:ef7eb2e8f9f7 651
<> 144:ef7eb2e8f9f7 652 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 653 }
<> 144:ef7eb2e8f9f7 654 #endif
<> 144:ef7eb2e8f9f7 655
<> 144:ef7eb2e8f9f7 656 #endif /*__STM32L0xx_TSC_H */
<> 144:ef7eb2e8f9f7 657 #endif /* #if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx) */
<> 144:ef7eb2e8f9f7 658
<> 144:ef7eb2e8f9f7 659 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 144:ef7eb2e8f9f7 660