Fawwaz Nadzmy / mbed-STM

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targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_tim_ex.c@153:9398a535854b, 2016-12-22 (annotated)

Committer:
fwndz
Date:
Thu Dec 22 05:12:40 2016 +0000
Revision:
153:9398a535854b
Parent:
149:156823d33999 
device target maximize

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f7xx_hal_tim_ex.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.1.0
<> 144:ef7eb2e8f9f7 6 * @date 22-April-2016
<> 144:ef7eb2e8f9f7 7 * @brief TIM HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the Timer extension peripheral:
<> 144:ef7eb2e8f9f7 10 * + Time Hall Sensor Interface Initialization
<> 144:ef7eb2e8f9f7 11 * + Time Hall Sensor Interface Start
<> 144:ef7eb2e8f9f7 12 * + Time Complementary signal bread and dead time configuration
<> 144:ef7eb2e8f9f7 13 * + Time Master and Slave synchronization configuration
<> 144:ef7eb2e8f9f7 14 * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
<> 144:ef7eb2e8f9f7 15 * + Time OCRef clear configuration
<> 144:ef7eb2e8f9f7 16 * + Timer remapping capabilities configuration
<> 144:ef7eb2e8f9f7 17 @verbatim
<> 144:ef7eb2e8f9f7 18 ==============================================================================
<> 144:ef7eb2e8f9f7 19 ##### TIMER Extended features #####
<> 144:ef7eb2e8f9f7 20 ==============================================================================
<> 144:ef7eb2e8f9f7 21 [..]
<> 144:ef7eb2e8f9f7 22 The Timer Extension features include:
<> 144:ef7eb2e8f9f7 23 (#) Complementary outputs with programmable dead-time for :
<> 144:ef7eb2e8f9f7 24 (++) Input Capture
<> 144:ef7eb2e8f9f7 25 (++) Output Compare
<> 144:ef7eb2e8f9f7 26 (++) PWM generation (Edge and Center-aligned Mode)
<> 144:ef7eb2e8f9f7 27 (++) One-pulse mode output
<> 144:ef7eb2e8f9f7 28 (#) Synchronization circuit to control the timer with external signals and to
<> 144:ef7eb2e8f9f7 29 interconnect several timers together.
<> 144:ef7eb2e8f9f7 30 (#) Break input to put the timer output signals in reset state or in a known state.
<> 144:ef7eb2e8f9f7 31 (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
<> 144:ef7eb2e8f9f7 32 positioning purposes
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 35 ==============================================================================
<> 144:ef7eb2e8f9f7 36 [..]
<> 144:ef7eb2e8f9f7 37 (#) Initialize the TIM low level resources by implementing the following functions
<> 144:ef7eb2e8f9f7 38 depending from feature used :
<> 144:ef7eb2e8f9f7 39 (++) Complementary Output Compare : HAL_TIM_OC_MspInit()
<> 144:ef7eb2e8f9f7 40 (++) Complementary PWM generation : HAL_TIM_PWM_MspInit()
<> 144:ef7eb2e8f9f7 41 (++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit()
<> 144:ef7eb2e8f9f7 42 (++) Hall Sensor output : HAL_TIM_HallSensor_MspInit()
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 (#) Initialize the TIM low level resources :
<> 144:ef7eb2e8f9f7 45 (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 46 (##) TIM pins configuration
<> 144:ef7eb2e8f9f7 47 (+++) Enable the clock for the TIM GPIOs using the following function:
<> 144:ef7eb2e8f9f7 48 __GPIOx_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 49 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 (#) The external Clock can be configured, if needed (the default clock is the
<> 144:ef7eb2e8f9f7 52 internal clock from the APBx), using the following function:
<> 144:ef7eb2e8f9f7 53 HAL_TIM_ConfigClockSource, the clock configuration should be done before
<> 144:ef7eb2e8f9f7 54 any start function.
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 (#) Configure the TIM in the desired functioning mode using one of the
<> 144:ef7eb2e8f9f7 57 initialization function of this driver:
<> 144:ef7eb2e8f9f7 58 (++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the
<> 144:ef7eb2e8f9f7 59 Timer Hall Sensor Interface and the commutation event with the corresponding
<> 144:ef7eb2e8f9f7 60 Interrupt and DMA request if needed (Note that One Timer is used to interface
<> 144:ef7eb2e8f9f7 61 with the Hall sensor Interface and another Timer should be used to use
<> 144:ef7eb2e8f9f7 62 the commutation event).
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 (#) Activate the TIM peripheral using one of the start functions:
<> 144:ef7eb2e8f9f7 65 (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT()
<> 144:ef7eb2e8f9f7 66 (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
<> 144:ef7eb2e8f9f7 67 (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
<> 144:ef7eb2e8f9f7 68 (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 @endverbatim
<> 144:ef7eb2e8f9f7 72 ******************************************************************************
<> 144:ef7eb2e8f9f7 73 * @attention
<> 144:ef7eb2e8f9f7 74 *
<> 144:ef7eb2e8f9f7 75 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 76 *
<> 144:ef7eb2e8f9f7 77 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 78 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 79 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 80 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 81 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 82 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 83 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 84 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 85 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 86 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 87 *
<> 144:ef7eb2e8f9f7 88 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 89 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 90 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 91 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 92 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 93 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 94 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 95 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 96 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 97 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 98 *
<> 144:ef7eb2e8f9f7 99 ******************************************************************************
<> 144:ef7eb2e8f9f7 100 */
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 103 #include "stm32f7xx_hal.h"
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 /** @addtogroup STM32F7xx_HAL_Driver
<> 144:ef7eb2e8f9f7 106 * @{
<> 144:ef7eb2e8f9f7 107 */
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 /** @defgroup TIMEx TIMEx
<> 144:ef7eb2e8f9f7 110 * @brief TIM Extended HAL module driver
<> 144:ef7eb2e8f9f7 111 * @{
<> 144:ef7eb2e8f9f7 112 */
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 #ifdef HAL_TIM_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 117 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 118 #define BDTR_BKF_SHIFT (16)
<> 144:ef7eb2e8f9f7 119 #define BDTR_BK2F_SHIFT (20)
<> 144:ef7eb2e8f9f7 120 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 121 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 122 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 123 /** @addtogroup TIMEx_Private_Functions
<> 144:ef7eb2e8f9f7 124 * @{
<> 144:ef7eb2e8f9f7 125 */
<> 144:ef7eb2e8f9f7 126 static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState);
<> 144:ef7eb2e8f9f7 127 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
<> 144:ef7eb2e8f9f7 128 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
<> 144:ef7eb2e8f9f7 129 /**
<> 144:ef7eb2e8f9f7 130 * @}
<> 144:ef7eb2e8f9f7 131 */
<> 144:ef7eb2e8f9f7 132 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 /** @defgroup TIMEx_Exported_Functions TIMEx Exported Functions
<> 144:ef7eb2e8f9f7 135 * @{
<> 144:ef7eb2e8f9f7 136 */
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 /** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
<> 144:ef7eb2e8f9f7 139 * @brief Timer Hall Sensor functions
<> 144:ef7eb2e8f9f7 140 *
<> 144:ef7eb2e8f9f7 141 @verbatim
<> 144:ef7eb2e8f9f7 142 ==============================================================================
<> 144:ef7eb2e8f9f7 143 ##### Timer Hall Sensor functions #####
<> 144:ef7eb2e8f9f7 144 ==============================================================================
<> 144:ef7eb2e8f9f7 145 [..]
<> 144:ef7eb2e8f9f7 146 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 147 (+) Initialize and configure TIM HAL Sensor.
<> 144:ef7eb2e8f9f7 148 (+) De-initialize TIM HAL Sensor.
<> 144:ef7eb2e8f9f7 149 (+) Start the Hall Sensor Interface.
<> 144:ef7eb2e8f9f7 150 (+) Stop the Hall Sensor Interface.
<> 144:ef7eb2e8f9f7 151 (+) Start the Hall Sensor Interface and enable interrupts.
<> 144:ef7eb2e8f9f7 152 (+) Stop the Hall Sensor Interface and disable interrupts.
<> 144:ef7eb2e8f9f7 153 (+) Start the Hall Sensor Interface and enable DMA transfers.
<> 144:ef7eb2e8f9f7 154 (+) Stop the Hall Sensor Interface and disable DMA transfers.
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 @endverbatim
<> 144:ef7eb2e8f9f7 157 * @{
<> 144:ef7eb2e8f9f7 158 */
<> 144:ef7eb2e8f9f7 159 /**
<> 144:ef7eb2e8f9f7 160 * @brief Initializes the TIM Hall Sensor Interface and create the associated handle.
<> 144:ef7eb2e8f9f7 161 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 162 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 163 * @param sConfig: TIM Hall Sensor configuration structure
<> 144:ef7eb2e8f9f7 164 * @retval HAL status
<> 144:ef7eb2e8f9f7 165 */
<> 144:ef7eb2e8f9f7 166 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig)
<> 144:ef7eb2e8f9f7 167 {
<> 144:ef7eb2e8f9f7 168 TIM_OC_InitTypeDef OC_Config;
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 /* Check the TIM handle allocation */
<> 144:ef7eb2e8f9f7 171 if(htim == NULL)
<> 144:ef7eb2e8f9f7 172 {
<> 144:ef7eb2e8f9f7 173 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 174 }
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 177 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<> 144:ef7eb2e8f9f7 178 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
<> 144:ef7eb2e8f9f7 179 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
<> 144:ef7eb2e8f9f7 180 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
<> 144:ef7eb2e8f9f7 181 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 184 htim->State= HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<> 144:ef7eb2e8f9f7 187 HAL_TIMEx_HallSensor_MspInit(htim);
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 /* Configure the Time base in the Encoder Mode */
<> 144:ef7eb2e8f9f7 190 TIM_Base_SetConfig(htim->Instance, &htim->Init);
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */
<> 144:ef7eb2e8f9f7 193 TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 /* Reset the IC1PSC Bits */
<> 144:ef7eb2e8f9f7 196 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
<> 144:ef7eb2e8f9f7 197 /* Set the IC1PSC value */
<> 144:ef7eb2e8f9f7 198 htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200 /* Enable the Hall sensor interface (XOR function of the three inputs) */
<> 144:ef7eb2e8f9f7 201 htim->Instance->CR2 |= TIM_CR2_TI1S;
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
<> 144:ef7eb2e8f9f7 204 htim->Instance->SMCR &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 205 htim->Instance->SMCR |= TIM_TS_TI1F_ED;
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
<> 144:ef7eb2e8f9f7 208 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
<> 144:ef7eb2e8f9f7 209 htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
<> 144:ef7eb2e8f9f7 210
<> 144:ef7eb2e8f9f7 211 /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
<> 144:ef7eb2e8f9f7 212 OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
<> 144:ef7eb2e8f9f7 213 OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
<> 144:ef7eb2e8f9f7 214 OC_Config.OCMode = TIM_OCMODE_PWM2;
<> 144:ef7eb2e8f9f7 215 OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
<> 144:ef7eb2e8f9f7 216 OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
<> 144:ef7eb2e8f9f7 217 OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
<> 144:ef7eb2e8f9f7 218 OC_Config.Pulse = sConfig->Commutation_Delay;
<> 144:ef7eb2e8f9f7 219
<> 144:ef7eb2e8f9f7 220 TIM_OC2_SetConfig(htim->Instance, &OC_Config);
<> 144:ef7eb2e8f9f7 221
<> 144:ef7eb2e8f9f7 222 /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
<> 144:ef7eb2e8f9f7 223 register to 101 */
<> 144:ef7eb2e8f9f7 224 htim->Instance->CR2 &= ~TIM_CR2_MMS;
<> 144:ef7eb2e8f9f7 225 htim->Instance->CR2 |= TIM_TRGO_OC2REF;
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 /* Initialize the TIM state*/
<> 144:ef7eb2e8f9f7 228 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 229
<> 144:ef7eb2e8f9f7 230 return HAL_OK;
<> 144:ef7eb2e8f9f7 231 }
<> 144:ef7eb2e8f9f7 232
<> 144:ef7eb2e8f9f7 233 /**
<> 144:ef7eb2e8f9f7 234 * @brief DeInitializes the TIM Hall Sensor interface
<> 144:ef7eb2e8f9f7 235 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 236 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 237 * @retval HAL status
<> 144:ef7eb2e8f9f7 238 */
<> 144:ef7eb2e8f9f7 239 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 240 {
<> 144:ef7eb2e8f9f7 241 /* Check the parameters */
<> 144:ef7eb2e8f9f7 242 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 243
<> 144:ef7eb2e8f9f7 244 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 /* Disable the TIM Peripheral Clock */
<> 144:ef7eb2e8f9f7 247 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
<> 144:ef7eb2e8f9f7 250 HAL_TIMEx_HallSensor_MspDeInit(htim);
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 /* Change TIM state */
<> 144:ef7eb2e8f9f7 253 htim->State = HAL_TIM_STATE_RESET;
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 /* Release Lock */
<> 144:ef7eb2e8f9f7 256 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 return HAL_OK;
<> 144:ef7eb2e8f9f7 259 }
<> 144:ef7eb2e8f9f7 260
<> 144:ef7eb2e8f9f7 261 /**
<> 144:ef7eb2e8f9f7 262 * @brief Initializes the TIM Hall Sensor MSP.
<> 144:ef7eb2e8f9f7 263 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 264 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 265 * @retval None
<> 144:ef7eb2e8f9f7 266 */
<> 144:ef7eb2e8f9f7 267 __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 268 {
<> 144:ef7eb2e8f9f7 269 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 270 UNUSED(htim);
<> 144:ef7eb2e8f9f7 271
<> 144:ef7eb2e8f9f7 272 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 273 the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 274 */
<> 144:ef7eb2e8f9f7 275 }
<> 144:ef7eb2e8f9f7 276
<> 144:ef7eb2e8f9f7 277 /**
<> 144:ef7eb2e8f9f7 278 * @brief DeInitializes TIM Hall Sensor MSP.
<> 144:ef7eb2e8f9f7 279 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 280 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 281 * @retval None
<> 144:ef7eb2e8f9f7 282 */
<> 144:ef7eb2e8f9f7 283 __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 284 {
<> 144:ef7eb2e8f9f7 285 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 286 UNUSED(htim);
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 289 the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 290 */
<> 144:ef7eb2e8f9f7 291 }
<> 144:ef7eb2e8f9f7 292
<> 144:ef7eb2e8f9f7 293 /**
<> 144:ef7eb2e8f9f7 294 * @brief Starts the TIM Hall Sensor Interface.
<> 144:ef7eb2e8f9f7 295 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 296 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 297 * @retval HAL status
<> 144:ef7eb2e8f9f7 298 */
<> 144:ef7eb2e8f9f7 299 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 300 {
<> 144:ef7eb2e8f9f7 301 /* Check the parameters */
<> 144:ef7eb2e8f9f7 302 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 303
<> 144:ef7eb2e8f9f7 304 /* Enable the Input Capture channels 1
<> 144:ef7eb2e8f9f7 305 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 306 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 307
<> 144:ef7eb2e8f9f7 308 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 309 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 310
<> 144:ef7eb2e8f9f7 311 /* Return function status */
<> 144:ef7eb2e8f9f7 312 return HAL_OK;
<> 144:ef7eb2e8f9f7 313 }
<> 144:ef7eb2e8f9f7 314
<> 144:ef7eb2e8f9f7 315 /**
<> 144:ef7eb2e8f9f7 316 * @brief Stops the TIM Hall sensor Interface.
<> 144:ef7eb2e8f9f7 317 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 318 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 319 * @retval HAL status
<> 144:ef7eb2e8f9f7 320 */
<> 144:ef7eb2e8f9f7 321 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 322 {
<> 144:ef7eb2e8f9f7 323 /* Check the parameters */
<> 144:ef7eb2e8f9f7 324 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 325
<> 144:ef7eb2e8f9f7 326 /* Disable the Input Capture channels 1, 2 and 3
<> 144:ef7eb2e8f9f7 327 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 328 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 329
<> 144:ef7eb2e8f9f7 330 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 331 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 332
<> 144:ef7eb2e8f9f7 333 /* Return function status */
<> 144:ef7eb2e8f9f7 334 return HAL_OK;
<> 144:ef7eb2e8f9f7 335 }
<> 144:ef7eb2e8f9f7 336
<> 144:ef7eb2e8f9f7 337 /**
<> 144:ef7eb2e8f9f7 338 * @brief Starts the TIM Hall Sensor Interface in interrupt mode.
<> 144:ef7eb2e8f9f7 339 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 340 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 341 * @retval HAL status
<> 144:ef7eb2e8f9f7 342 */
<> 144:ef7eb2e8f9f7 343 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 344 {
<> 144:ef7eb2e8f9f7 345 /* Check the parameters */
<> 144:ef7eb2e8f9f7 346 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 347
<> 144:ef7eb2e8f9f7 348 /* Enable the capture compare Interrupts 1 event */
<> 144:ef7eb2e8f9f7 349 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 350
<> 144:ef7eb2e8f9f7 351 /* Enable the Input Capture channels 1
<> 144:ef7eb2e8f9f7 352 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 353 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 354
<> 144:ef7eb2e8f9f7 355 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 356 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 357
<> 144:ef7eb2e8f9f7 358 /* Return function status */
<> 144:ef7eb2e8f9f7 359 return HAL_OK;
<> 144:ef7eb2e8f9f7 360 }
<> 144:ef7eb2e8f9f7 361
<> 144:ef7eb2e8f9f7 362 /**
<> 144:ef7eb2e8f9f7 363 * @brief Stops the TIM Hall Sensor Interface in interrupt mode.
<> 144:ef7eb2e8f9f7 364 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 365 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 366 * @retval HAL status
<> 144:ef7eb2e8f9f7 367 */
<> 144:ef7eb2e8f9f7 368 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 369 {
<> 144:ef7eb2e8f9f7 370 /* Check the parameters */
<> 144:ef7eb2e8f9f7 371 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 372
<> 144:ef7eb2e8f9f7 373 /* Disable the Input Capture channels 1
<> 144:ef7eb2e8f9f7 374 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 375 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 376
<> 144:ef7eb2e8f9f7 377 /* Disable the capture compare Interrupts event */
<> 144:ef7eb2e8f9f7 378 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 379
<> 144:ef7eb2e8f9f7 380 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 381 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 382
<> 144:ef7eb2e8f9f7 383 /* Return function status */
<> 144:ef7eb2e8f9f7 384 return HAL_OK;
<> 144:ef7eb2e8f9f7 385 }
<> 144:ef7eb2e8f9f7 386
<> 144:ef7eb2e8f9f7 387 /**
<> 144:ef7eb2e8f9f7 388 * @brief Starts the TIM Hall Sensor Interface in DMA mode.
<> 144:ef7eb2e8f9f7 389 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 390 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 391 * @param pData: The destination Buffer address.
<> 144:ef7eb2e8f9f7 392 * @param Length: The length of data to be transferred from TIM peripheral to memory.
<> 144:ef7eb2e8f9f7 393 * @retval HAL status
<> 144:ef7eb2e8f9f7 394 */
<> 144:ef7eb2e8f9f7 395 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
<> 144:ef7eb2e8f9f7 396 {
<> 144:ef7eb2e8f9f7 397 /* Check the parameters */
<> 144:ef7eb2e8f9f7 398 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 399
<> 144:ef7eb2e8f9f7 400 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 401 {
<> 144:ef7eb2e8f9f7 402 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 403 }
<> 144:ef7eb2e8f9f7 404 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 405 {
<> 144:ef7eb2e8f9f7 406 if(((uint32_t)pData == 0 ) && (Length > 0))
<> 144:ef7eb2e8f9f7 407 {
<> 144:ef7eb2e8f9f7 408 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 409 }
<> 144:ef7eb2e8f9f7 410 else
<> 144:ef7eb2e8f9f7 411 {
<> 144:ef7eb2e8f9f7 412 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 413 }
<> 144:ef7eb2e8f9f7 414 }
<> 144:ef7eb2e8f9f7 415 /* Enable the Input Capture channels 1
<> 144:ef7eb2e8f9f7 416 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 417 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419 /* Set the DMA Input Capture 1 Callback */
<> 144:ef7eb2e8f9f7 420 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 421 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 422 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
<> 144:ef7eb2e8f9f7 423
<> 144:ef7eb2e8f9f7 424 /* Enable the DMA Stream for Capture 1*/
<> 144:ef7eb2e8f9f7 425 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
<> 144:ef7eb2e8f9f7 426
<> 144:ef7eb2e8f9f7 427 /* Enable the capture compare 1 Interrupt */
<> 144:ef7eb2e8f9f7 428 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 429
<> 144:ef7eb2e8f9f7 430 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 431 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 432
<> 144:ef7eb2e8f9f7 433 /* Return function status */
<> 144:ef7eb2e8f9f7 434 return HAL_OK;
<> 144:ef7eb2e8f9f7 435 }
<> 144:ef7eb2e8f9f7 436
<> 144:ef7eb2e8f9f7 437 /**
<> 144:ef7eb2e8f9f7 438 * @brief Stops the TIM Hall Sensor Interface in DMA mode.
<> 144:ef7eb2e8f9f7 439 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 440 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 441 * @retval HAL status
<> 144:ef7eb2e8f9f7 442 */
<> 144:ef7eb2e8f9f7 443 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 444 {
<> 144:ef7eb2e8f9f7 445 /* Check the parameters */
<> 144:ef7eb2e8f9f7 446 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 447
<> 144:ef7eb2e8f9f7 448 /* Disable the Input Capture channels 1
<> 144:ef7eb2e8f9f7 449 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 450 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 451
<> 144:ef7eb2e8f9f7 452
<> 144:ef7eb2e8f9f7 453 /* Disable the capture compare Interrupts 1 event */
<> 144:ef7eb2e8f9f7 454 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 455
<> 144:ef7eb2e8f9f7 456 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 457 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 458
<> 144:ef7eb2e8f9f7 459 /* Return function status */
<> 144:ef7eb2e8f9f7 460 return HAL_OK;
<> 144:ef7eb2e8f9f7 461 }
<> 144:ef7eb2e8f9f7 462
<> 144:ef7eb2e8f9f7 463 /**
<> 144:ef7eb2e8f9f7 464 * @}
<> 144:ef7eb2e8f9f7 465 */
<> 144:ef7eb2e8f9f7 466
<> 144:ef7eb2e8f9f7 467 /** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
<> 144:ef7eb2e8f9f7 468 * @brief Timer Complementary Output Compare functions
<> 144:ef7eb2e8f9f7 469 *
<> 144:ef7eb2e8f9f7 470 @verbatim
<> 144:ef7eb2e8f9f7 471 ==============================================================================
<> 144:ef7eb2e8f9f7 472 ##### Timer Complementary Output Compare functions #####
<> 144:ef7eb2e8f9f7 473 ==============================================================================
<> 144:ef7eb2e8f9f7 474 [..]
<> 144:ef7eb2e8f9f7 475 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 476 (+) Start the Complementary Output Compare/PWM.
<> 144:ef7eb2e8f9f7 477 (+) Stop the Complementary Output Compare/PWM.
<> 144:ef7eb2e8f9f7 478 (+) Start the Complementary Output Compare/PWM and enable interrupts.
<> 144:ef7eb2e8f9f7 479 (+) Stop the Complementary Output Compare/PWM and disable interrupts.
<> 144:ef7eb2e8f9f7 480 (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
<> 144:ef7eb2e8f9f7 481 (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
<> 144:ef7eb2e8f9f7 482
<> 144:ef7eb2e8f9f7 483 @endverbatim
<> 144:ef7eb2e8f9f7 484 * @{
<> 144:ef7eb2e8f9f7 485 */
<> 144:ef7eb2e8f9f7 486
<> 144:ef7eb2e8f9f7 487 /**
<> 144:ef7eb2e8f9f7 488 * @brief Starts the TIM Output Compare signal generation on the complementary
<> 144:ef7eb2e8f9f7 489 * output.
<> 144:ef7eb2e8f9f7 490 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 491 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 492 * @param Channel: TIM Channel to be enabled.
<> 144:ef7eb2e8f9f7 493 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 494 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 495 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 496 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 497 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 498 * @retval HAL status
<> 144:ef7eb2e8f9f7 499 */
<> 144:ef7eb2e8f9f7 500 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 501 {
<> 144:ef7eb2e8f9f7 502 /* Check the parameters */
<> 144:ef7eb2e8f9f7 503 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 504
<> 144:ef7eb2e8f9f7 505 /* Enable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 506 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 507
<> 144:ef7eb2e8f9f7 508 /* Enable the Main Output */
<> 144:ef7eb2e8f9f7 509 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 510
<> 144:ef7eb2e8f9f7 511 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 512 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 513
<> 144:ef7eb2e8f9f7 514 /* Return function status */
<> 144:ef7eb2e8f9f7 515 return HAL_OK;
<> 144:ef7eb2e8f9f7 516 }
<> 144:ef7eb2e8f9f7 517
<> 144:ef7eb2e8f9f7 518 /**
<> 144:ef7eb2e8f9f7 519 * @brief Stops the TIM Output Compare signal generation on the complementary
<> 144:ef7eb2e8f9f7 520 * output.
<> 144:ef7eb2e8f9f7 521 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 522 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 523 * @param Channel: TIM Channel to be disabled.
<> 144:ef7eb2e8f9f7 524 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 525 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 526 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 527 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 528 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 529 * @retval HAL status
<> 144:ef7eb2e8f9f7 530 */
<> 144:ef7eb2e8f9f7 531 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 532 {
<> 144:ef7eb2e8f9f7 533 /* Check the parameters */
<> 144:ef7eb2e8f9f7 534 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 535
<> 144:ef7eb2e8f9f7 536 /* Disable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 537 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 538
<> 144:ef7eb2e8f9f7 539 /* Disable the Main Output */
<> 144:ef7eb2e8f9f7 540 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 541
<> 144:ef7eb2e8f9f7 542 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 543 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 544
<> 144:ef7eb2e8f9f7 545 /* Return function status */
<> 144:ef7eb2e8f9f7 546 return HAL_OK;
<> 144:ef7eb2e8f9f7 547 }
<> 144:ef7eb2e8f9f7 548
<> 144:ef7eb2e8f9f7 549 /**
<> 144:ef7eb2e8f9f7 550 * @brief Starts the TIM Output Compare signal generation in interrupt mode
<> 144:ef7eb2e8f9f7 551 * on the complementary output.
<> 144:ef7eb2e8f9f7 552 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 553 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 554 * @param Channel: TIM Channel to be enabled.
<> 144:ef7eb2e8f9f7 555 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 556 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 557 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 558 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 559 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 560 * @retval HAL status
<> 144:ef7eb2e8f9f7 561 */
<> 144:ef7eb2e8f9f7 562 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 563 {
<> 144:ef7eb2e8f9f7 564 /* Check the parameters */
<> 144:ef7eb2e8f9f7 565 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 566
<> 144:ef7eb2e8f9f7 567 switch (Channel)
<> 144:ef7eb2e8f9f7 568 {
<> 144:ef7eb2e8f9f7 569 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 570 {
<> 144:ef7eb2e8f9f7 571 /* Enable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 572 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 573 }
<> 144:ef7eb2e8f9f7 574 break;
<> 144:ef7eb2e8f9f7 575
<> 144:ef7eb2e8f9f7 576 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 577 {
<> 144:ef7eb2e8f9f7 578 /* Enable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 579 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 580 }
<> 144:ef7eb2e8f9f7 581 break;
<> 144:ef7eb2e8f9f7 582
<> 144:ef7eb2e8f9f7 583 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 584 {
<> 144:ef7eb2e8f9f7 585 /* Enable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 586 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 587 }
<> 144:ef7eb2e8f9f7 588 break;
<> 144:ef7eb2e8f9f7 589
<> 144:ef7eb2e8f9f7 590 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 591 {
<> 144:ef7eb2e8f9f7 592 /* Enable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 593 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 594 }
<> 144:ef7eb2e8f9f7 595 break;
<> 144:ef7eb2e8f9f7 596
<> 144:ef7eb2e8f9f7 597 default:
<> 144:ef7eb2e8f9f7 598 break;
<> 144:ef7eb2e8f9f7 599 }
<> 144:ef7eb2e8f9f7 600
<> 144:ef7eb2e8f9f7 601 /* Enable the TIM Break interrupt */
<> 144:ef7eb2e8f9f7 602 __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
<> 144:ef7eb2e8f9f7 603
<> 144:ef7eb2e8f9f7 604 /* Enable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 605 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 606
<> 144:ef7eb2e8f9f7 607 /* Enable the Main Output */
<> 144:ef7eb2e8f9f7 608 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 609
<> 144:ef7eb2e8f9f7 610 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 611 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 612
<> 144:ef7eb2e8f9f7 613 /* Return function status */
<> 144:ef7eb2e8f9f7 614 return HAL_OK;
<> 144:ef7eb2e8f9f7 615 }
<> 144:ef7eb2e8f9f7 616
<> 144:ef7eb2e8f9f7 617 /**
<> 144:ef7eb2e8f9f7 618 * @brief Stops the TIM Output Compare signal generation in interrupt mode
<> 144:ef7eb2e8f9f7 619 * on the complementary output.
<> 144:ef7eb2e8f9f7 620 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 621 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 622 * @param Channel: TIM Channel to be disabled.
<> 144:ef7eb2e8f9f7 623 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 624 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 625 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 626 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 627 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 628 * @retval HAL status
<> 144:ef7eb2e8f9f7 629 */
<> 144:ef7eb2e8f9f7 630 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 631 {
<> 144:ef7eb2e8f9f7 632 uint32_t tmpccer = 0;
<> 144:ef7eb2e8f9f7 633
<> 144:ef7eb2e8f9f7 634 /* Check the parameters */
<> 144:ef7eb2e8f9f7 635 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 636
<> 144:ef7eb2e8f9f7 637 switch (Channel)
<> 144:ef7eb2e8f9f7 638 {
<> 144:ef7eb2e8f9f7 639 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 640 {
<> 144:ef7eb2e8f9f7 641 /* Disable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 642 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 643 }
<> 144:ef7eb2e8f9f7 644 break;
<> 144:ef7eb2e8f9f7 645
<> 144:ef7eb2e8f9f7 646 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 647 {
<> 144:ef7eb2e8f9f7 648 /* Disable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 649 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 650 }
<> 144:ef7eb2e8f9f7 651 break;
<> 144:ef7eb2e8f9f7 652
<> 144:ef7eb2e8f9f7 653 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 654 {
<> 144:ef7eb2e8f9f7 655 /* Disable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 656 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 657 }
<> 144:ef7eb2e8f9f7 658 break;
<> 144:ef7eb2e8f9f7 659
<> 144:ef7eb2e8f9f7 660 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 661 {
<> 144:ef7eb2e8f9f7 662 /* Disable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 663 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 664 }
<> 144:ef7eb2e8f9f7 665 break;
<> 144:ef7eb2e8f9f7 666
<> 144:ef7eb2e8f9f7 667 default:
<> 144:ef7eb2e8f9f7 668 break;
<> 144:ef7eb2e8f9f7 669 }
<> 144:ef7eb2e8f9f7 670
<> 144:ef7eb2e8f9f7 671 /* Disable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 672 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 673
<> 144:ef7eb2e8f9f7 674 /* Disable the TIM Break interrupt (only if no more channel is active) */
<> 144:ef7eb2e8f9f7 675 tmpccer = htim->Instance->CCER;
<> 144:ef7eb2e8f9f7 676 if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
<> 144:ef7eb2e8f9f7 677 {
<> 144:ef7eb2e8f9f7 678 __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
<> 144:ef7eb2e8f9f7 679 }
<> 144:ef7eb2e8f9f7 680
<> 144:ef7eb2e8f9f7 681 /* Disable the Main Output */
<> 144:ef7eb2e8f9f7 682 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 683
<> 144:ef7eb2e8f9f7 684 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 685 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 686
<> 144:ef7eb2e8f9f7 687 /* Return function status */
<> 144:ef7eb2e8f9f7 688 return HAL_OK;
<> 144:ef7eb2e8f9f7 689 }
<> 144:ef7eb2e8f9f7 690
<> 144:ef7eb2e8f9f7 691 /**
<> 144:ef7eb2e8f9f7 692 * @brief Starts the TIM Output Compare signal generation in DMA mode
<> 144:ef7eb2e8f9f7 693 * on the complementary output.
<> 144:ef7eb2e8f9f7 694 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 695 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 696 * @param Channel: TIM Channel to be enabled.
<> 144:ef7eb2e8f9f7 697 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 698 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 699 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 700 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 701 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 702 * @param pData: The source Buffer address.
<> 144:ef7eb2e8f9f7 703 * @param Length: The length of data to be transferred from memory to TIM peripheral
<> 144:ef7eb2e8f9f7 704 * @retval HAL status
<> 144:ef7eb2e8f9f7 705 */
<> 144:ef7eb2e8f9f7 706 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
<> 144:ef7eb2e8f9f7 707 {
<> 144:ef7eb2e8f9f7 708 /* Check the parameters */
<> 144:ef7eb2e8f9f7 709 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 710
<> 144:ef7eb2e8f9f7 711 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 712 {
<> 144:ef7eb2e8f9f7 713 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 714 }
<> 144:ef7eb2e8f9f7 715 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 716 {
<> 144:ef7eb2e8f9f7 717 if(((uint32_t)pData == 0 ) && (Length > 0))
<> 144:ef7eb2e8f9f7 718 {
<> 144:ef7eb2e8f9f7 719 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 720 }
<> 144:ef7eb2e8f9f7 721 else
<> 144:ef7eb2e8f9f7 722 {
<> 144:ef7eb2e8f9f7 723 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 724 }
<> 144:ef7eb2e8f9f7 725 }
<> 144:ef7eb2e8f9f7 726 switch (Channel)
<> 144:ef7eb2e8f9f7 727 {
<> 144:ef7eb2e8f9f7 728 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 729 {
<> 144:ef7eb2e8f9f7 730 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 731 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 732
<> 144:ef7eb2e8f9f7 733 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 734 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
<> 144:ef7eb2e8f9f7 735
<> 144:ef7eb2e8f9f7 736 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 737 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
<> 144:ef7eb2e8f9f7 738
<> 144:ef7eb2e8f9f7 739 /* Enable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 740 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 741 }
<> 144:ef7eb2e8f9f7 742 break;
<> 144:ef7eb2e8f9f7 743
<> 144:ef7eb2e8f9f7 744 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 745 {
<> 144:ef7eb2e8f9f7 746 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 747 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 748
<> 144:ef7eb2e8f9f7 749 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 750 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
<> 144:ef7eb2e8f9f7 751
<> 144:ef7eb2e8f9f7 752 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 753 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
<> 144:ef7eb2e8f9f7 754
<> 144:ef7eb2e8f9f7 755 /* Enable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 756 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 757 }
<> 144:ef7eb2e8f9f7 758 break;
<> 144:ef7eb2e8f9f7 759
<> 144:ef7eb2e8f9f7 760 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 761 {
<> 144:ef7eb2e8f9f7 762 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 763 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 764
<> 144:ef7eb2e8f9f7 765 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 766 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
<> 144:ef7eb2e8f9f7 767
<> 144:ef7eb2e8f9f7 768 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 769 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
<> 144:ef7eb2e8f9f7 770
<> 144:ef7eb2e8f9f7 771 /* Enable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 772 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 773 }
<> 144:ef7eb2e8f9f7 774 break;
<> 144:ef7eb2e8f9f7 775
<> 144:ef7eb2e8f9f7 776 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 777 {
<> 144:ef7eb2e8f9f7 778 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 779 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 780
<> 144:ef7eb2e8f9f7 781 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 782 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
<> 144:ef7eb2e8f9f7 783
<> 144:ef7eb2e8f9f7 784 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 785 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
<> 144:ef7eb2e8f9f7 786
<> 144:ef7eb2e8f9f7 787 /* Enable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 788 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 789 }
<> 144:ef7eb2e8f9f7 790 break;
<> 144:ef7eb2e8f9f7 791
<> 144:ef7eb2e8f9f7 792 default:
<> 144:ef7eb2e8f9f7 793 break;
<> 144:ef7eb2e8f9f7 794 }
<> 144:ef7eb2e8f9f7 795
<> 144:ef7eb2e8f9f7 796 /* Enable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 797 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 798
<> 144:ef7eb2e8f9f7 799 /* Enable the Main Output */
<> 144:ef7eb2e8f9f7 800 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 801
<> 144:ef7eb2e8f9f7 802 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 803 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 804
<> 144:ef7eb2e8f9f7 805 /* Return function status */
<> 144:ef7eb2e8f9f7 806 return HAL_OK;
<> 144:ef7eb2e8f9f7 807 }
<> 144:ef7eb2e8f9f7 808
<> 144:ef7eb2e8f9f7 809 /**
<> 144:ef7eb2e8f9f7 810 * @brief Stops the TIM Output Compare signal generation in DMA mode
<> 144:ef7eb2e8f9f7 811 * on the complementary output.
<> 144:ef7eb2e8f9f7 812 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 813 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 814 * @param Channel: TIM Channel to be disabled.
<> 144:ef7eb2e8f9f7 815 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 816 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 817 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 818 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 819 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 820 * @retval HAL status
<> 144:ef7eb2e8f9f7 821 */
<> 144:ef7eb2e8f9f7 822 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 823 {
<> 144:ef7eb2e8f9f7 824 /* Check the parameters */
<> 144:ef7eb2e8f9f7 825 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 826
<> 144:ef7eb2e8f9f7 827 switch (Channel)
<> 144:ef7eb2e8f9f7 828 {
<> 144:ef7eb2e8f9f7 829 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 830 {
<> 144:ef7eb2e8f9f7 831 /* Disable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 832 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 833 }
<> 144:ef7eb2e8f9f7 834 break;
<> 144:ef7eb2e8f9f7 835
<> 144:ef7eb2e8f9f7 836 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 837 {
<> 144:ef7eb2e8f9f7 838 /* Disable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 839 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 840 }
<> 144:ef7eb2e8f9f7 841 break;
<> 144:ef7eb2e8f9f7 842
<> 144:ef7eb2e8f9f7 843 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 844 {
<> 144:ef7eb2e8f9f7 845 /* Disable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 846 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 847 }
<> 144:ef7eb2e8f9f7 848 break;
<> 144:ef7eb2e8f9f7 849
<> 144:ef7eb2e8f9f7 850 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 851 {
<> 144:ef7eb2e8f9f7 852 /* Disable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 853 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 854 }
<> 144:ef7eb2e8f9f7 855 break;
<> 144:ef7eb2e8f9f7 856
<> 144:ef7eb2e8f9f7 857 default:
<> 144:ef7eb2e8f9f7 858 break;
<> 144:ef7eb2e8f9f7 859 }
<> 144:ef7eb2e8f9f7 860
<> 144:ef7eb2e8f9f7 861 /* Disable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 862 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 863
<> 144:ef7eb2e8f9f7 864 /* Disable the Main Output */
<> 144:ef7eb2e8f9f7 865 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 866
<> 144:ef7eb2e8f9f7 867 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 868 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 869
<> 144:ef7eb2e8f9f7 870 /* Change the htim state */
<> 144:ef7eb2e8f9f7 871 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 872
<> 144:ef7eb2e8f9f7 873 /* Return function status */
<> 144:ef7eb2e8f9f7 874 return HAL_OK;
<> 144:ef7eb2e8f9f7 875 }
<> 144:ef7eb2e8f9f7 876
<> 144:ef7eb2e8f9f7 877 /**
<> 144:ef7eb2e8f9f7 878 * @}
<> 144:ef7eb2e8f9f7 879 */
<> 144:ef7eb2e8f9f7 880
<> 144:ef7eb2e8f9f7 881 /** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
<> 144:ef7eb2e8f9f7 882 * @brief Timer Complementary PWM functions
<> 144:ef7eb2e8f9f7 883 *
<> 144:ef7eb2e8f9f7 884 @verbatim
<> 144:ef7eb2e8f9f7 885 ==============================================================================
<> 144:ef7eb2e8f9f7 886 ##### Timer Complementary PWM functions #####
<> 144:ef7eb2e8f9f7 887 ==============================================================================
<> 144:ef7eb2e8f9f7 888 [..]
<> 144:ef7eb2e8f9f7 889 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 890 (+) Start the Complementary PWM.
<> 144:ef7eb2e8f9f7 891 (+) Stop the Complementary PWM.
<> 144:ef7eb2e8f9f7 892 (+) Start the Complementary PWM and enable interrupts.
<> 144:ef7eb2e8f9f7 893 (+) Stop the Complementary PWM and disable interrupts.
<> 144:ef7eb2e8f9f7 894 (+) Start the Complementary PWM and enable DMA transfers.
<> 144:ef7eb2e8f9f7 895 (+) Stop the Complementary PWM and disable DMA transfers.
<> 144:ef7eb2e8f9f7 896 (+) Start the Complementary Input Capture measurement.
<> 144:ef7eb2e8f9f7 897 (+) Stop the Complementary Input Capture.
<> 144:ef7eb2e8f9f7 898 (+) Start the Complementary Input Capture and enable interrupts.
<> 144:ef7eb2e8f9f7 899 (+) Stop the Complementary Input Capture and disable interrupts.
<> 144:ef7eb2e8f9f7 900 (+) Start the Complementary Input Capture and enable DMA transfers.
<> 144:ef7eb2e8f9f7 901 (+) Stop the Complementary Input Capture and disable DMA transfers.
<> 144:ef7eb2e8f9f7 902 (+) Start the Complementary One Pulse generation.
<> 144:ef7eb2e8f9f7 903 (+) Stop the Complementary One Pulse.
<> 144:ef7eb2e8f9f7 904 (+) Start the Complementary One Pulse and enable interrupts.
<> 144:ef7eb2e8f9f7 905 (+) Stop the Complementary One Pulse and disable interrupts.
<> 144:ef7eb2e8f9f7 906
<> 144:ef7eb2e8f9f7 907 @endverbatim
<> 144:ef7eb2e8f9f7 908 * @{
<> 144:ef7eb2e8f9f7 909 */
<> 144:ef7eb2e8f9f7 910
<> 144:ef7eb2e8f9f7 911 /**
<> 144:ef7eb2e8f9f7 912 * @brief Starts the PWM signal generation on the complementary output.
<> 144:ef7eb2e8f9f7 913 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 914 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 915 * @param Channel: TIM Channel to be enabled.
<> 144:ef7eb2e8f9f7 916 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 917 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 918 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 919 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 920 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 921 * @retval HAL status
<> 144:ef7eb2e8f9f7 922 */
<> 144:ef7eb2e8f9f7 923 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 924 {
<> 144:ef7eb2e8f9f7 925 /* Check the parameters */
<> 144:ef7eb2e8f9f7 926 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 927
<> 144:ef7eb2e8f9f7 928 /* Enable the complementary PWM output */
<> 144:ef7eb2e8f9f7 929 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 930
<> 144:ef7eb2e8f9f7 931 /* Enable the Main Output */
<> 144:ef7eb2e8f9f7 932 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 933
<> 144:ef7eb2e8f9f7 934 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 935 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 936
<> 144:ef7eb2e8f9f7 937 /* Return function status */
<> 144:ef7eb2e8f9f7 938 return HAL_OK;
<> 144:ef7eb2e8f9f7 939 }
<> 144:ef7eb2e8f9f7 940
<> 144:ef7eb2e8f9f7 941 /**
<> 144:ef7eb2e8f9f7 942 * @brief Stops the PWM signal generation on the complementary output.
<> 144:ef7eb2e8f9f7 943 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 944 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 945 * @param Channel: TIM Channel to be disabled.
<> 144:ef7eb2e8f9f7 946 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 947 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 948 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 949 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 950 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 951 * @retval HAL status
<> 144:ef7eb2e8f9f7 952 */
<> 144:ef7eb2e8f9f7 953 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 954 {
<> 144:ef7eb2e8f9f7 955 /* Check the parameters */
<> 144:ef7eb2e8f9f7 956 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 957
<> 144:ef7eb2e8f9f7 958 /* Disable the complementary PWM output */
<> 144:ef7eb2e8f9f7 959 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 960
<> 144:ef7eb2e8f9f7 961 /* Disable the Main Output */
<> 144:ef7eb2e8f9f7 962 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 963
<> 144:ef7eb2e8f9f7 964 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 965 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 966
<> 144:ef7eb2e8f9f7 967 /* Return function status */
<> 144:ef7eb2e8f9f7 968 return HAL_OK;
<> 144:ef7eb2e8f9f7 969 }
<> 144:ef7eb2e8f9f7 970
<> 144:ef7eb2e8f9f7 971 /**
<> 144:ef7eb2e8f9f7 972 * @brief Starts the PWM signal generation in interrupt mode on the
<> 144:ef7eb2e8f9f7 973 * complementary output.
<> 144:ef7eb2e8f9f7 974 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 975 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 976 * @param Channel: TIM Channel to be disabled.
<> 144:ef7eb2e8f9f7 977 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 978 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 979 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 980 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 981 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 982 * @retval HAL status
<> 144:ef7eb2e8f9f7 983 */
<> 144:ef7eb2e8f9f7 984 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 985 {
<> 144:ef7eb2e8f9f7 986 /* Check the parameters */
<> 144:ef7eb2e8f9f7 987 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 988
<> 144:ef7eb2e8f9f7 989 switch (Channel)
<> 144:ef7eb2e8f9f7 990 {
<> 144:ef7eb2e8f9f7 991 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 992 {
<> 144:ef7eb2e8f9f7 993 /* Enable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 994 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 995 }
<> 144:ef7eb2e8f9f7 996 break;
<> 144:ef7eb2e8f9f7 997
<> 144:ef7eb2e8f9f7 998 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 999 {
<> 144:ef7eb2e8f9f7 1000 /* Enable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 1001 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 1002 }
<> 144:ef7eb2e8f9f7 1003 break;
<> 144:ef7eb2e8f9f7 1004
<> 144:ef7eb2e8f9f7 1005 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1006 {
<> 144:ef7eb2e8f9f7 1007 /* Enable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 1008 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 1009 }
<> 144:ef7eb2e8f9f7 1010 break;
<> 144:ef7eb2e8f9f7 1011
<> 144:ef7eb2e8f9f7 1012 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1013 {
<> 144:ef7eb2e8f9f7 1014 /* Enable the TIM Capture/Compare 4 interrupt */
<> 144:ef7eb2e8f9f7 1015 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 1016 }
<> 144:ef7eb2e8f9f7 1017 break;
<> 144:ef7eb2e8f9f7 1018
<> 144:ef7eb2e8f9f7 1019 default:
<> 144:ef7eb2e8f9f7 1020 break;
<> 144:ef7eb2e8f9f7 1021 }
<> 144:ef7eb2e8f9f7 1022
<> 144:ef7eb2e8f9f7 1023 /* Enable the TIM Break interrupt */
<> 144:ef7eb2e8f9f7 1024 __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
<> 144:ef7eb2e8f9f7 1025
<> 144:ef7eb2e8f9f7 1026 /* Enable the complementary PWM output */
<> 144:ef7eb2e8f9f7 1027 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 1028
<> 144:ef7eb2e8f9f7 1029 /* Enable the Main Output */
<> 144:ef7eb2e8f9f7 1030 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1031
<> 144:ef7eb2e8f9f7 1032 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1033 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1034
<> 144:ef7eb2e8f9f7 1035 /* Return function status */
<> 144:ef7eb2e8f9f7 1036 return HAL_OK;
<> 144:ef7eb2e8f9f7 1037 }
<> 144:ef7eb2e8f9f7 1038
<> 144:ef7eb2e8f9f7 1039 /**
<> 144:ef7eb2e8f9f7 1040 * @brief Stops the PWM signal generation in interrupt mode on the
<> 144:ef7eb2e8f9f7 1041 * complementary output.
<> 144:ef7eb2e8f9f7 1042 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1043 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1044 * @param Channel: TIM Channel to be disabled.
<> 144:ef7eb2e8f9f7 1045 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1046 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1047 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1048 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1049 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1050 * @retval HAL status
<> 144:ef7eb2e8f9f7 1051 */
<> 144:ef7eb2e8f9f7 1052 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1053 {
<> 144:ef7eb2e8f9f7 1054 uint32_t tmpccer = 0;
<> 144:ef7eb2e8f9f7 1055
<> 144:ef7eb2e8f9f7 1056 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1057 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1058
<> 144:ef7eb2e8f9f7 1059 switch (Channel)
<> 144:ef7eb2e8f9f7 1060 {
<> 144:ef7eb2e8f9f7 1061 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1062 {
<> 144:ef7eb2e8f9f7 1063 /* Disable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 1064 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 1065 }
<> 144:ef7eb2e8f9f7 1066 break;
<> 144:ef7eb2e8f9f7 1067
<> 144:ef7eb2e8f9f7 1068 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1069 {
<> 144:ef7eb2e8f9f7 1070 /* Disable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 1071 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 1072 }
<> 144:ef7eb2e8f9f7 1073 break;
<> 144:ef7eb2e8f9f7 1074
<> 144:ef7eb2e8f9f7 1075 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1076 {
<> 144:ef7eb2e8f9f7 1077 /* Disable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 1078 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 1079 }
<> 144:ef7eb2e8f9f7 1080 break;
<> 144:ef7eb2e8f9f7 1081
<> 144:ef7eb2e8f9f7 1082 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1083 {
<> 144:ef7eb2e8f9f7 1084 /* Disable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 1085 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 1086 }
<> 144:ef7eb2e8f9f7 1087 break;
<> 144:ef7eb2e8f9f7 1088
<> 144:ef7eb2e8f9f7 1089 default:
<> 144:ef7eb2e8f9f7 1090 break;
<> 144:ef7eb2e8f9f7 1091 }
<> 144:ef7eb2e8f9f7 1092
<> 144:ef7eb2e8f9f7 1093 /* Disable the complementary PWM output */
<> 144:ef7eb2e8f9f7 1094 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 1095
<> 144:ef7eb2e8f9f7 1096 /* Disable the TIM Break interrupt (only if no more channel is active) */
<> 144:ef7eb2e8f9f7 1097 tmpccer = htim->Instance->CCER;
<> 144:ef7eb2e8f9f7 1098 if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
<> 144:ef7eb2e8f9f7 1099 {
<> 144:ef7eb2e8f9f7 1100 __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
<> 144:ef7eb2e8f9f7 1101 }
<> 144:ef7eb2e8f9f7 1102
<> 144:ef7eb2e8f9f7 1103 /* Disable the Main Output */
<> 144:ef7eb2e8f9f7 1104 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1105
<> 144:ef7eb2e8f9f7 1106 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1107 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1108
<> 144:ef7eb2e8f9f7 1109 /* Return function status */
<> 144:ef7eb2e8f9f7 1110 return HAL_OK;
<> 144:ef7eb2e8f9f7 1111 }
<> 144:ef7eb2e8f9f7 1112
<> 144:ef7eb2e8f9f7 1113 /**
<> 144:ef7eb2e8f9f7 1114 * @brief Starts the TIM PWM signal generation in DMA mode on the
<> 144:ef7eb2e8f9f7 1115 * complementary output
<> 144:ef7eb2e8f9f7 1116 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1117 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1118 * @param Channel: TIM Channel to be enabled.
<> 144:ef7eb2e8f9f7 1119 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1120 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1121 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1122 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1123 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1124 * @param pData: The source Buffer address.
<> 144:ef7eb2e8f9f7 1125 * @param Length: The length of data to be transferred from memory to TIM peripheral
<> 144:ef7eb2e8f9f7 1126 * @retval HAL status
<> 144:ef7eb2e8f9f7 1127 */
<> 144:ef7eb2e8f9f7 1128 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
<> 144:ef7eb2e8f9f7 1129 {
<> 144:ef7eb2e8f9f7 1130 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1131 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1132
<> 144:ef7eb2e8f9f7 1133 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 1134 {
<> 144:ef7eb2e8f9f7 1135 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1136 }
<> 144:ef7eb2e8f9f7 1137 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 1138 {
<> 144:ef7eb2e8f9f7 1139 if(((uint32_t)pData == 0 ) && (Length > 0))
<> 144:ef7eb2e8f9f7 1140 {
<> 144:ef7eb2e8f9f7 1141 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1142 }
<> 144:ef7eb2e8f9f7 1143 else
<> 144:ef7eb2e8f9f7 1144 {
<> 144:ef7eb2e8f9f7 1145 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1146 }
<> 144:ef7eb2e8f9f7 1147 }
<> 144:ef7eb2e8f9f7 1148 switch (Channel)
<> 144:ef7eb2e8f9f7 1149 {
<> 144:ef7eb2e8f9f7 1150 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1151 {
<> 144:ef7eb2e8f9f7 1152 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1153 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1154
<> 144:ef7eb2e8f9f7 1155 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1156 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1157
<> 144:ef7eb2e8f9f7 1158 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 1159 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
<> 144:ef7eb2e8f9f7 1160
<> 144:ef7eb2e8f9f7 1161 /* Enable the TIM Capture/Compare 1 DMA request */
<> 144:ef7eb2e8f9f7 1162 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 1163 }
<> 144:ef7eb2e8f9f7 1164 break;
<> 144:ef7eb2e8f9f7 1165
<> 144:ef7eb2e8f9f7 1166 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1167 {
<> 144:ef7eb2e8f9f7 1168 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1169 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1170
<> 144:ef7eb2e8f9f7 1171 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1172 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1173
<> 144:ef7eb2e8f9f7 1174 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 1175 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
<> 144:ef7eb2e8f9f7 1176
<> 144:ef7eb2e8f9f7 1177 /* Enable the TIM Capture/Compare 2 DMA request */
<> 144:ef7eb2e8f9f7 1178 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 1179 }
<> 144:ef7eb2e8f9f7 1180 break;
<> 144:ef7eb2e8f9f7 1181
<> 144:ef7eb2e8f9f7 1182 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1183 {
<> 144:ef7eb2e8f9f7 1184 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1185 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1186
<> 144:ef7eb2e8f9f7 1187 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1188 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1189
<> 144:ef7eb2e8f9f7 1190 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 1191 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
<> 144:ef7eb2e8f9f7 1192
<> 144:ef7eb2e8f9f7 1193 /* Enable the TIM Capture/Compare 3 DMA request */
<> 144:ef7eb2e8f9f7 1194 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 1195 }
<> 144:ef7eb2e8f9f7 1196 break;
<> 144:ef7eb2e8f9f7 1197
<> 144:ef7eb2e8f9f7 1198 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1199 {
<> 144:ef7eb2e8f9f7 1200 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1201 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1202
<> 144:ef7eb2e8f9f7 1203 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1204 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1205
<> 144:ef7eb2e8f9f7 1206 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 1207 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
<> 144:ef7eb2e8f9f7 1208
<> 144:ef7eb2e8f9f7 1209 /* Enable the TIM Capture/Compare 4 DMA request */
<> 144:ef7eb2e8f9f7 1210 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 1211 }
<> 144:ef7eb2e8f9f7 1212 break;
<> 144:ef7eb2e8f9f7 1213
<> 144:ef7eb2e8f9f7 1214 default:
<> 144:ef7eb2e8f9f7 1215 break;
<> 144:ef7eb2e8f9f7 1216 }
<> 144:ef7eb2e8f9f7 1217
<> 144:ef7eb2e8f9f7 1218 /* Enable the complementary PWM output */
<> 144:ef7eb2e8f9f7 1219 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 1220
<> 144:ef7eb2e8f9f7 1221 /* Enable the Main Output */
<> 144:ef7eb2e8f9f7 1222 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1223
<> 144:ef7eb2e8f9f7 1224 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1225 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1226
<> 144:ef7eb2e8f9f7 1227 /* Return function status */
<> 144:ef7eb2e8f9f7 1228 return HAL_OK;
<> 144:ef7eb2e8f9f7 1229 }
<> 144:ef7eb2e8f9f7 1230
<> 144:ef7eb2e8f9f7 1231 /**
<> 144:ef7eb2e8f9f7 1232 * @brief Stops the TIM PWM signal generation in DMA mode on the complementary
<> 144:ef7eb2e8f9f7 1233 * output
<> 144:ef7eb2e8f9f7 1234 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1235 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1236 * @param Channel: TIM Channel to be disabled.
<> 144:ef7eb2e8f9f7 1237 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1238 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1239 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1240 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1241 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1242 * @retval HAL status
<> 144:ef7eb2e8f9f7 1243 */
<> 144:ef7eb2e8f9f7 1244 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1245 {
<> 144:ef7eb2e8f9f7 1246 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1247 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1248
<> 144:ef7eb2e8f9f7 1249 switch (Channel)
<> 144:ef7eb2e8f9f7 1250 {
<> 144:ef7eb2e8f9f7 1251 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1252 {
<> 144:ef7eb2e8f9f7 1253 /* Disable the TIM Capture/Compare 1 DMA request */
<> 144:ef7eb2e8f9f7 1254 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 1255 }
<> 144:ef7eb2e8f9f7 1256 break;
<> 144:ef7eb2e8f9f7 1257
<> 144:ef7eb2e8f9f7 1258 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1259 {
<> 144:ef7eb2e8f9f7 1260 /* Disable the TIM Capture/Compare 2 DMA request */
<> 144:ef7eb2e8f9f7 1261 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 1262 }
<> 144:ef7eb2e8f9f7 1263 break;
<> 144:ef7eb2e8f9f7 1264
<> 144:ef7eb2e8f9f7 1265 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1266 {
<> 144:ef7eb2e8f9f7 1267 /* Disable the TIM Capture/Compare 3 DMA request */
<> 144:ef7eb2e8f9f7 1268 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 1269 }
<> 144:ef7eb2e8f9f7 1270 break;
<> 144:ef7eb2e8f9f7 1271
<> 144:ef7eb2e8f9f7 1272 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1273 {
<> 144:ef7eb2e8f9f7 1274 /* Disable the TIM Capture/Compare 4 DMA request */
<> 144:ef7eb2e8f9f7 1275 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 1276 }
<> 144:ef7eb2e8f9f7 1277 break;
<> 144:ef7eb2e8f9f7 1278
<> 144:ef7eb2e8f9f7 1279 default:
<> 144:ef7eb2e8f9f7 1280 break;
<> 144:ef7eb2e8f9f7 1281 }
<> 144:ef7eb2e8f9f7 1282
<> 144:ef7eb2e8f9f7 1283 /* Disable the complementary PWM output */
<> 144:ef7eb2e8f9f7 1284 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 1285
<> 144:ef7eb2e8f9f7 1286 /* Disable the Main Output */
<> 144:ef7eb2e8f9f7 1287 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1288
<> 144:ef7eb2e8f9f7 1289 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1290 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1291
<> 144:ef7eb2e8f9f7 1292 /* Change the htim state */
<> 144:ef7eb2e8f9f7 1293 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1294
<> 144:ef7eb2e8f9f7 1295 /* Return function status */
<> 144:ef7eb2e8f9f7 1296 return HAL_OK;
<> 144:ef7eb2e8f9f7 1297 }
<> 144:ef7eb2e8f9f7 1298
<> 144:ef7eb2e8f9f7 1299 /**
<> 144:ef7eb2e8f9f7 1300 * @}
<> 144:ef7eb2e8f9f7 1301 */
<> 144:ef7eb2e8f9f7 1302
<> 144:ef7eb2e8f9f7 1303 /** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
<> 144:ef7eb2e8f9f7 1304 * @brief Timer Complementary One Pulse functions
<> 144:ef7eb2e8f9f7 1305 *
<> 144:ef7eb2e8f9f7 1306 @verbatim
<> 144:ef7eb2e8f9f7 1307 ==============================================================================
<> 144:ef7eb2e8f9f7 1308 ##### Timer Complementary One Pulse functions #####
<> 144:ef7eb2e8f9f7 1309 ==============================================================================
<> 144:ef7eb2e8f9f7 1310 [..]
<> 144:ef7eb2e8f9f7 1311 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 1312 (+) Start the Complementary One Pulse generation.
<> 144:ef7eb2e8f9f7 1313 (+) Stop the Complementary One Pulse.
<> 144:ef7eb2e8f9f7 1314 (+) Start the Complementary One Pulse and enable interrupts.
<> 144:ef7eb2e8f9f7 1315 (+) Stop the Complementary One Pulse and disable interrupts.
<> 144:ef7eb2e8f9f7 1316
<> 144:ef7eb2e8f9f7 1317 @endverbatim
<> 144:ef7eb2e8f9f7 1318 * @{
<> 144:ef7eb2e8f9f7 1319 */
<> 144:ef7eb2e8f9f7 1320
<> 144:ef7eb2e8f9f7 1321 /**
<> 144:ef7eb2e8f9f7 1322 * @brief Starts the TIM One Pulse signal generation on the complemetary
<> 144:ef7eb2e8f9f7 1323 * output.
<> 144:ef7eb2e8f9f7 1324 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1325 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1326 * @param OutputChannel: TIM Channel to be enabled.
<> 144:ef7eb2e8f9f7 1327 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1328 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1329 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1330 * @retval HAL status
<> 144:ef7eb2e8f9f7 1331 */
<> 144:ef7eb2e8f9f7 1332 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 1333 {
<> 144:ef7eb2e8f9f7 1334 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1335 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
<> 144:ef7eb2e8f9f7 1336
<> 144:ef7eb2e8f9f7 1337 /* Enable the complementary One Pulse output */
<> 144:ef7eb2e8f9f7 1338 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 1339
<> 144:ef7eb2e8f9f7 1340 /* Enable the Main Output */
<> 144:ef7eb2e8f9f7 1341 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1342
<> 144:ef7eb2e8f9f7 1343 /* Return function status */
<> 144:ef7eb2e8f9f7 1344 return HAL_OK;
<> 144:ef7eb2e8f9f7 1345 }
<> 144:ef7eb2e8f9f7 1346
<> 144:ef7eb2e8f9f7 1347 /**
<> 144:ef7eb2e8f9f7 1348 * @brief Stops the TIM One Pulse signal generation on the complementary
<> 144:ef7eb2e8f9f7 1349 * output.
<> 144:ef7eb2e8f9f7 1350 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1351 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1352 * @param OutputChannel: TIM Channel to be disabled.
<> 144:ef7eb2e8f9f7 1353 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1354 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1355 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1356 * @retval HAL status
<> 144:ef7eb2e8f9f7 1357 */
<> 144:ef7eb2e8f9f7 1358 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 1359 {
<> 144:ef7eb2e8f9f7 1360
<> 144:ef7eb2e8f9f7 1361 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1362 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
<> 144:ef7eb2e8f9f7 1363
<> 144:ef7eb2e8f9f7 1364 /* Disable the complementary One Pulse output */
<> 144:ef7eb2e8f9f7 1365 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 1366
<> 144:ef7eb2e8f9f7 1367 /* Disable the Main Output */
<> 144:ef7eb2e8f9f7 1368 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1369
<> 144:ef7eb2e8f9f7 1370 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1371 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1372
<> 144:ef7eb2e8f9f7 1373 /* Return function status */
<> 144:ef7eb2e8f9f7 1374 return HAL_OK;
<> 144:ef7eb2e8f9f7 1375 }
<> 144:ef7eb2e8f9f7 1376
<> 144:ef7eb2e8f9f7 1377 /**
<> 144:ef7eb2e8f9f7 1378 * @brief Starts the TIM One Pulse signal generation in interrupt mode on the
<> 144:ef7eb2e8f9f7 1379 * complementary channel.
<> 144:ef7eb2e8f9f7 1380 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1381 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1382 * @param OutputChannel: TIM Channel to be enabled.
<> 144:ef7eb2e8f9f7 1383 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1384 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1385 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1386 * @retval HAL status
<> 144:ef7eb2e8f9f7 1387 */
<> 144:ef7eb2e8f9f7 1388 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 1389 {
<> 144:ef7eb2e8f9f7 1390 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1391 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
<> 144:ef7eb2e8f9f7 1392
<> 144:ef7eb2e8f9f7 1393 /* Enable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 1394 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 1395
<> 144:ef7eb2e8f9f7 1396 /* Enable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 1397 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 1398
<> 144:ef7eb2e8f9f7 1399 /* Enable the complementary One Pulse output */
<> 144:ef7eb2e8f9f7 1400 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 1401
<> 144:ef7eb2e8f9f7 1402 /* Enable the Main Output */
<> 144:ef7eb2e8f9f7 1403 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1404
<> 144:ef7eb2e8f9f7 1405 /* Return function status */
<> 144:ef7eb2e8f9f7 1406 return HAL_OK;
<> 144:ef7eb2e8f9f7 1407 }
<> 144:ef7eb2e8f9f7 1408
<> 144:ef7eb2e8f9f7 1409 /**
<> 144:ef7eb2e8f9f7 1410 * @brief Stops the TIM One Pulse signal generation in interrupt mode on the
<> 144:ef7eb2e8f9f7 1411 * complementary channel.
<> 144:ef7eb2e8f9f7 1412 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1413 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1414 * @param OutputChannel: TIM Channel to be disabled.
<> 144:ef7eb2e8f9f7 1415 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1416 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1417 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1418 * @retval HAL status
<> 144:ef7eb2e8f9f7 1419 */
<> 144:ef7eb2e8f9f7 1420 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 1421 {
<> 144:ef7eb2e8f9f7 1422 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1423 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
<> 144:ef7eb2e8f9f7 1424
<> 144:ef7eb2e8f9f7 1425 /* Disable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 1426 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 1427
<> 144:ef7eb2e8f9f7 1428 /* Disable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 1429 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 1430
<> 144:ef7eb2e8f9f7 1431 /* Disable the complementary One Pulse output */
<> 144:ef7eb2e8f9f7 1432 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 1433
<> 144:ef7eb2e8f9f7 1434 /* Disable the Main Output */
<> 144:ef7eb2e8f9f7 1435 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1436
<> 144:ef7eb2e8f9f7 1437 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1438 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1439
<> 144:ef7eb2e8f9f7 1440 /* Return function status */
<> 144:ef7eb2e8f9f7 1441 return HAL_OK;
<> 144:ef7eb2e8f9f7 1442 }
<> 144:ef7eb2e8f9f7 1443
<> 144:ef7eb2e8f9f7 1444 /**
<> 144:ef7eb2e8f9f7 1445 * @}
<> 144:ef7eb2e8f9f7 1446 */
<> 144:ef7eb2e8f9f7 1447
<> 144:ef7eb2e8f9f7 1448 /** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
<> 144:ef7eb2e8f9f7 1449 * @brief Peripheral Control functions
<> 144:ef7eb2e8f9f7 1450 *
<> 144:ef7eb2e8f9f7 1451 @verbatim
<> 144:ef7eb2e8f9f7 1452 ==============================================================================
<> 144:ef7eb2e8f9f7 1453 ##### Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 1454 ==============================================================================
<> 144:ef7eb2e8f9f7 1455 [..]
<> 144:ef7eb2e8f9f7 1456 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 1457 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
<> 144:ef7eb2e8f9f7 1458 (+) Configure External Clock source.
<> 144:ef7eb2e8f9f7 1459 (+) Configure Complementary channels, break features and dead time.
<> 144:ef7eb2e8f9f7 1460 (+) Configure Master and the Slave synchronization.
<> 144:ef7eb2e8f9f7 1461 (+) Configure the commutation event in case of use of the Hall sensor interface.
<> 144:ef7eb2e8f9f7 1462 (+) Configure the DMA Burst Mode.
<> 144:ef7eb2e8f9f7 1463
<> 144:ef7eb2e8f9f7 1464 @endverbatim
<> 144:ef7eb2e8f9f7 1465 * @{
<> 144:ef7eb2e8f9f7 1466 */
<> 144:ef7eb2e8f9f7 1467 /**
<> 144:ef7eb2e8f9f7 1468 * @brief Configure the TIM commutation event sequence.
<> 144:ef7eb2e8f9f7 1469 * @note This function is mandatory to use the commutation event in order to
<> 144:ef7eb2e8f9f7 1470 * update the configuration at each commutation detection on the TRGI input of the Timer,
<> 144:ef7eb2e8f9f7 1471 * the typical use of this feature is with the use of another Timer(interface Timer)
<> 144:ef7eb2e8f9f7 1472 * configured in Hall sensor interface, this interface Timer will generate the
<> 144:ef7eb2e8f9f7 1473 * commutation at its TRGO output (connected to Timer used in this function) each time
<> 144:ef7eb2e8f9f7 1474 * the TI1 of the Interface Timer detect a commutation at its input TI1.
<> 144:ef7eb2e8f9f7 1475 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1476 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1477 * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
<> 144:ef7eb2e8f9f7 1478 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1479 * @arg TIM_TS_ITR0: Internal trigger 0 selected
<> 144:ef7eb2e8f9f7 1480 * @arg TIM_TS_ITR1: Internal trigger 1 selected
<> 144:ef7eb2e8f9f7 1481 * @arg TIM_TS_ITR2: Internal trigger 2 selected
<> 144:ef7eb2e8f9f7 1482 * @arg TIM_TS_ITR3: Internal trigger 3 selected
<> 144:ef7eb2e8f9f7 1483 * @arg TIM_TS_NONE: No trigger is needed
<> 144:ef7eb2e8f9f7 1484 * @param CommutationSource: the Commutation Event source.
<> 144:ef7eb2e8f9f7 1485 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1486 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
<> 144:ef7eb2e8f9f7 1487 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
<> 144:ef7eb2e8f9f7 1488 * @retval HAL status
<> 144:ef7eb2e8f9f7 1489 */
<> 144:ef7eb2e8f9f7 1490 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
<> 144:ef7eb2e8f9f7 1491 {
<> 144:ef7eb2e8f9f7 1492 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1493 assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1494 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
<> 144:ef7eb2e8f9f7 1495
<> 144:ef7eb2e8f9f7 1496 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 1497
<> 144:ef7eb2e8f9f7 1498 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
<> 144:ef7eb2e8f9f7 1499 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
<> 144:ef7eb2e8f9f7 1500 {
<> 144:ef7eb2e8f9f7 1501 /* Select the Input trigger */
<> 144:ef7eb2e8f9f7 1502 htim->Instance->SMCR &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 1503 htim->Instance->SMCR |= InputTrigger;
<> 144:ef7eb2e8f9f7 1504 }
<> 144:ef7eb2e8f9f7 1505
<> 144:ef7eb2e8f9f7 1506 /* Select the Capture Compare preload feature */
<> 144:ef7eb2e8f9f7 1507 htim->Instance->CR2 |= TIM_CR2_CCPC;
<> 144:ef7eb2e8f9f7 1508 /* Select the Commutation event source */
<> 144:ef7eb2e8f9f7 1509 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
<> 144:ef7eb2e8f9f7 1510 htim->Instance->CR2 |= CommutationSource;
<> 144:ef7eb2e8f9f7 1511
<> 144:ef7eb2e8f9f7 1512 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1513
<> 144:ef7eb2e8f9f7 1514 return HAL_OK;
<> 144:ef7eb2e8f9f7 1515 }
<> 144:ef7eb2e8f9f7 1516
<> 144:ef7eb2e8f9f7 1517 /**
<> 144:ef7eb2e8f9f7 1518 * @brief Configure the TIM commutation event sequence with interrupt.
<> 144:ef7eb2e8f9f7 1519 * @note This function is mandatory to use the commutation event in order to
<> 144:ef7eb2e8f9f7 1520 * update the configuration at each commutation detection on the TRGI input of the Timer,
<> 144:ef7eb2e8f9f7 1521 * the typical use of this feature is with the use of another Timer(interface Timer)
<> 144:ef7eb2e8f9f7 1522 * configured in Hall sensor interface, this interface Timer will generate the
<> 144:ef7eb2e8f9f7 1523 * commutation at its TRGO output (connected to Timer used in this function) each time
<> 144:ef7eb2e8f9f7 1524 * the TI1 of the Interface Timer detect a commutation at its input TI1.
<> 144:ef7eb2e8f9f7 1525 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1526 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1527 * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
<> 144:ef7eb2e8f9f7 1528 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1529 * @arg TIM_TS_ITR0: Internal trigger 0 selected
<> 144:ef7eb2e8f9f7 1530 * @arg TIM_TS_ITR1: Internal trigger 1 selected
<> 144:ef7eb2e8f9f7 1531 * @arg TIM_TS_ITR2: Internal trigger 2 selected
<> 144:ef7eb2e8f9f7 1532 * @arg TIM_TS_ITR3: Internal trigger 3 selected
<> 144:ef7eb2e8f9f7 1533 * @arg TIM_TS_NONE: No trigger is needed
<> 144:ef7eb2e8f9f7 1534 * @param CommutationSource: the Commutation Event source.
<> 144:ef7eb2e8f9f7 1535 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1536 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
<> 144:ef7eb2e8f9f7 1537 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
<> 144:ef7eb2e8f9f7 1538 * @retval HAL status
<> 144:ef7eb2e8f9f7 1539 */
<> 144:ef7eb2e8f9f7 1540 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
<> 144:ef7eb2e8f9f7 1541 {
<> 144:ef7eb2e8f9f7 1542 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1543 assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1544 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
<> 144:ef7eb2e8f9f7 1545
<> 144:ef7eb2e8f9f7 1546 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 1547
<> 144:ef7eb2e8f9f7 1548 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
<> 144:ef7eb2e8f9f7 1549 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
<> 144:ef7eb2e8f9f7 1550 {
<> 144:ef7eb2e8f9f7 1551 /* Select the Input trigger */
<> 144:ef7eb2e8f9f7 1552 htim->Instance->SMCR &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 1553 htim->Instance->SMCR |= InputTrigger;
<> 144:ef7eb2e8f9f7 1554 }
<> 144:ef7eb2e8f9f7 1555
<> 144:ef7eb2e8f9f7 1556 /* Select the Capture Compare preload feature */
<> 144:ef7eb2e8f9f7 1557 htim->Instance->CR2 |= TIM_CR2_CCPC;
<> 144:ef7eb2e8f9f7 1558 /* Select the Commutation event source */
<> 144:ef7eb2e8f9f7 1559 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
<> 144:ef7eb2e8f9f7 1560 htim->Instance->CR2 |= CommutationSource;
<> 144:ef7eb2e8f9f7 1561
<> 144:ef7eb2e8f9f7 1562 /* Enable the Commutation Interrupt Request */
<> 144:ef7eb2e8f9f7 1563 __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
<> 144:ef7eb2e8f9f7 1564
<> 144:ef7eb2e8f9f7 1565 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1566
<> 144:ef7eb2e8f9f7 1567 return HAL_OK;
<> 144:ef7eb2e8f9f7 1568 }
<> 144:ef7eb2e8f9f7 1569
<> 144:ef7eb2e8f9f7 1570 /**
<> 144:ef7eb2e8f9f7 1571 * @brief Configure the TIM commutation event sequence with DMA.
<> 144:ef7eb2e8f9f7 1572 * @note This function is mandatory to use the commutation event in order to
<> 144:ef7eb2e8f9f7 1573 * update the configuration at each commutation detection on the TRGI input of the Timer,
<> 144:ef7eb2e8f9f7 1574 * the typical use of this feature is with the use of another Timer(interface Timer)
<> 144:ef7eb2e8f9f7 1575 * configured in Hall sensor interface, this interface Timer will generate the
<> 144:ef7eb2e8f9f7 1576 * commutation at its TRGO output (connected to Timer used in this function) each time
<> 144:ef7eb2e8f9f7 1577 * the TI1 of the Interface Timer detect a commutation at its input TI1.
<> 144:ef7eb2e8f9f7 1578 * @note: The user should configure the DMA in his own software, in This function only the COMDE bit is set
<> 144:ef7eb2e8f9f7 1579 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1580 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1581 * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
<> 144:ef7eb2e8f9f7 1582 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1583 * @arg TIM_TS_ITR0: Internal trigger 0 selected
<> 144:ef7eb2e8f9f7 1584 * @arg TIM_TS_ITR1: Internal trigger 1 selected
<> 144:ef7eb2e8f9f7 1585 * @arg TIM_TS_ITR2: Internal trigger 2 selected
<> 144:ef7eb2e8f9f7 1586 * @arg TIM_TS_ITR3: Internal trigger 3 selected
<> 144:ef7eb2e8f9f7 1587 * @arg TIM_TS_NONE: No trigger is needed
<> 144:ef7eb2e8f9f7 1588 * @param CommutationSource: the Commutation Event source.
<> 144:ef7eb2e8f9f7 1589 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1590 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
<> 144:ef7eb2e8f9f7 1591 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
<> 144:ef7eb2e8f9f7 1592 * @retval HAL status
<> 144:ef7eb2e8f9f7 1593 */
<> 144:ef7eb2e8f9f7 1594 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
<> 144:ef7eb2e8f9f7 1595 {
<> 144:ef7eb2e8f9f7 1596 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1597 assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1598 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
<> 144:ef7eb2e8f9f7 1599
<> 144:ef7eb2e8f9f7 1600 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 1601
<> 144:ef7eb2e8f9f7 1602 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
<> 144:ef7eb2e8f9f7 1603 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
<> 144:ef7eb2e8f9f7 1604 {
<> 144:ef7eb2e8f9f7 1605 /* Select the Input trigger */
<> 144:ef7eb2e8f9f7 1606 htim->Instance->SMCR &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 1607 htim->Instance->SMCR |= InputTrigger;
<> 144:ef7eb2e8f9f7 1608 }
<> 144:ef7eb2e8f9f7 1609
<> 144:ef7eb2e8f9f7 1610 /* Select the Capture Compare preload feature */
<> 144:ef7eb2e8f9f7 1611 htim->Instance->CR2 |= TIM_CR2_CCPC;
<> 144:ef7eb2e8f9f7 1612 /* Select the Commutation event source */
<> 144:ef7eb2e8f9f7 1613 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
<> 144:ef7eb2e8f9f7 1614 htim->Instance->CR2 |= CommutationSource;
<> 144:ef7eb2e8f9f7 1615
<> 144:ef7eb2e8f9f7 1616 /* Enable the Commutation DMA Request */
<> 144:ef7eb2e8f9f7 1617 /* Set the DMA Commutation Callback */
<> 144:ef7eb2e8f9f7 1618 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
<> 144:ef7eb2e8f9f7 1619 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1620 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError;
<> 144:ef7eb2e8f9f7 1621
<> 144:ef7eb2e8f9f7 1622 /* Enable the Commutation DMA Request */
<> 144:ef7eb2e8f9f7 1623 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
<> 144:ef7eb2e8f9f7 1624
<> 144:ef7eb2e8f9f7 1625 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1626
<> 144:ef7eb2e8f9f7 1627 return HAL_OK;
<> 144:ef7eb2e8f9f7 1628 }
<> 144:ef7eb2e8f9f7 1629
<> 144:ef7eb2e8f9f7 1630 /**
<> 144:ef7eb2e8f9f7 1631 * @brief Initializes the TIM Output Compare Channels according to the specified
<> 144:ef7eb2e8f9f7 1632 * parameters in the TIM_OC_InitTypeDef.
<> 144:ef7eb2e8f9f7 1633 * @param htim: TIM Output Compare handle
<> 144:ef7eb2e8f9f7 1634 * @param sConfig: TIM Output Compare configuration structure
<> 144:ef7eb2e8f9f7 1635 * @param Channel : TIM Channels to configure
<> 144:ef7eb2e8f9f7 1636 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1637 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1638 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1639 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1640 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1641 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
<> 144:ef7eb2e8f9f7 1642 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
<> 144:ef7eb2e8f9f7 1643 * @retval HAL status
<> 144:ef7eb2e8f9f7 1644 */
<> 144:ef7eb2e8f9f7 1645 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1646 {
<> 144:ef7eb2e8f9f7 1647 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1648 assert_param(IS_TIM_CHANNELS(Channel));
<> 144:ef7eb2e8f9f7 1649 assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
<> 144:ef7eb2e8f9f7 1650 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
<> 144:ef7eb2e8f9f7 1651
<> 144:ef7eb2e8f9f7 1652 /* Check input state */
<> 144:ef7eb2e8f9f7 1653 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 1654
<> 144:ef7eb2e8f9f7 1655 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1656
<> 144:ef7eb2e8f9f7 1657 switch (Channel)
<> 144:ef7eb2e8f9f7 1658 {
<> 144:ef7eb2e8f9f7 1659 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1660 {
<> 144:ef7eb2e8f9f7 1661 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1662 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1663
<> 144:ef7eb2e8f9f7 1664 /* Configure the TIM Channel 1 in Output Compare */
<> 144:ef7eb2e8f9f7 1665 TIM_OC1_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 1666 }
<> 144:ef7eb2e8f9f7 1667 break;
<> 144:ef7eb2e8f9f7 1668
<> 144:ef7eb2e8f9f7 1669 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1670 {
<> 144:ef7eb2e8f9f7 1671 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1672 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1673
<> 144:ef7eb2e8f9f7 1674 /* Configure the TIM Channel 2 in Output Compare */
<> 144:ef7eb2e8f9f7 1675 TIM_OC2_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 1676 }
<> 144:ef7eb2e8f9f7 1677 break;
<> 144:ef7eb2e8f9f7 1678
<> 144:ef7eb2e8f9f7 1679 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1680 {
<> 144:ef7eb2e8f9f7 1681 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1682 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1683
<> 144:ef7eb2e8f9f7 1684 /* Configure the TIM Channel 3 in Output Compare */
<> 144:ef7eb2e8f9f7 1685 TIM_OC3_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 1686 }
<> 144:ef7eb2e8f9f7 1687 break;
<> 144:ef7eb2e8f9f7 1688
<> 144:ef7eb2e8f9f7 1689 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1690 {
<> 144:ef7eb2e8f9f7 1691 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1692 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1693
<> 144:ef7eb2e8f9f7 1694 /* Configure the TIM Channel 4 in Output Compare */
<> 144:ef7eb2e8f9f7 1695 TIM_OC4_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 1696 }
<> 144:ef7eb2e8f9f7 1697 break;
<> 144:ef7eb2e8f9f7 1698
<> 144:ef7eb2e8f9f7 1699 case TIM_CHANNEL_5:
<> 144:ef7eb2e8f9f7 1700 {
<> 144:ef7eb2e8f9f7 1701 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1702 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1703
<> 144:ef7eb2e8f9f7 1704 /* Configure the TIM Channel 5 in Output Compare */
<> 144:ef7eb2e8f9f7 1705 TIM_OC5_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 1706 }
<> 144:ef7eb2e8f9f7 1707 break;
<> 144:ef7eb2e8f9f7 1708
<> 144:ef7eb2e8f9f7 1709 case TIM_CHANNEL_6:
<> 144:ef7eb2e8f9f7 1710 {
<> 144:ef7eb2e8f9f7 1711 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1712 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1713
<> 144:ef7eb2e8f9f7 1714 /* Configure the TIM Channel 6 in Output Compare */
<> 144:ef7eb2e8f9f7 1715 TIM_OC6_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 1716 }
<> 144:ef7eb2e8f9f7 1717 break;
<> 144:ef7eb2e8f9f7 1718
<> 144:ef7eb2e8f9f7 1719 default:
<> 144:ef7eb2e8f9f7 1720 break;
<> 144:ef7eb2e8f9f7 1721 }
<> 144:ef7eb2e8f9f7 1722
<> 144:ef7eb2e8f9f7 1723 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1724
<> 144:ef7eb2e8f9f7 1725 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1726
<> 144:ef7eb2e8f9f7 1727 return HAL_OK;
<> 144:ef7eb2e8f9f7 1728 }
<> 144:ef7eb2e8f9f7 1729
<> 144:ef7eb2e8f9f7 1730 /**
<> 144:ef7eb2e8f9f7 1731 * @brief Initializes the TIM PWM channels according to the specified
<> 144:ef7eb2e8f9f7 1732 * parameters in the TIM_OC_InitTypeDef.
<> 144:ef7eb2e8f9f7 1733 * @param htim: TIM PWM handle
<> 144:ef7eb2e8f9f7 1734 * @param sConfig: TIM PWM configuration structure
<> 144:ef7eb2e8f9f7 1735 * @param Channel : TIM Channels to be configured
<> 144:ef7eb2e8f9f7 1736 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1737 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1738 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1739 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1740 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1741 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
<> 144:ef7eb2e8f9f7 1742 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
<> 144:ef7eb2e8f9f7 1743 * @retval HAL status
<> 144:ef7eb2e8f9f7 1744 */
<> 144:ef7eb2e8f9f7 1745 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
<> 144:ef7eb2e8f9f7 1746 TIM_OC_InitTypeDef* sConfig,
<> 144:ef7eb2e8f9f7 1747 uint32_t Channel)
<> 144:ef7eb2e8f9f7 1748 {
<> 144:ef7eb2e8f9f7 1749 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1750 assert_param(IS_TIM_CHANNELS(Channel));
<> 144:ef7eb2e8f9f7 1751 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
<> 144:ef7eb2e8f9f7 1752 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
<> 144:ef7eb2e8f9f7 1753 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
<> 144:ef7eb2e8f9f7 1754
<> 144:ef7eb2e8f9f7 1755 /* Check input state */
<> 144:ef7eb2e8f9f7 1756 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 1757
<> 144:ef7eb2e8f9f7 1758 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1759
<> 144:ef7eb2e8f9f7 1760 switch (Channel)
<> 144:ef7eb2e8f9f7 1761 {
<> 144:ef7eb2e8f9f7 1762 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1763 {
<> 144:ef7eb2e8f9f7 1764 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1765 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1766
<> 144:ef7eb2e8f9f7 1767 /* Configure the Channel 1 in PWM mode */
<> 144:ef7eb2e8f9f7 1768 TIM_OC1_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 1769
<> 144:ef7eb2e8f9f7 1770 /* Set the Preload enable bit for channel1 */
<> 144:ef7eb2e8f9f7 1771 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
<> 144:ef7eb2e8f9f7 1772
<> 144:ef7eb2e8f9f7 1773 /* Configure the Output Fast mode */
<> 144:ef7eb2e8f9f7 1774 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
<> 144:ef7eb2e8f9f7 1775 htim->Instance->CCMR1 |= sConfig->OCFastMode;
<> 144:ef7eb2e8f9f7 1776 }
<> 144:ef7eb2e8f9f7 1777 break;
<> 144:ef7eb2e8f9f7 1778
<> 144:ef7eb2e8f9f7 1779 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1780 {
<> 144:ef7eb2e8f9f7 1781 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1782 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1783
<> 144:ef7eb2e8f9f7 1784 /* Configure the Channel 2 in PWM mode */
<> 144:ef7eb2e8f9f7 1785 TIM_OC2_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 1786
<> 144:ef7eb2e8f9f7 1787 /* Set the Preload enable bit for channel2 */
<> 144:ef7eb2e8f9f7 1788 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
<> 144:ef7eb2e8f9f7 1789
<> 144:ef7eb2e8f9f7 1790 /* Configure the Output Fast mode */
<> 144:ef7eb2e8f9f7 1791 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
<> 144:ef7eb2e8f9f7 1792 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;
<> 144:ef7eb2e8f9f7 1793 }
<> 144:ef7eb2e8f9f7 1794 break;
<> 144:ef7eb2e8f9f7 1795
<> 144:ef7eb2e8f9f7 1796 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1797 {
<> 144:ef7eb2e8f9f7 1798 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1799 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1800
<> 144:ef7eb2e8f9f7 1801 /* Configure the Channel 3 in PWM mode */
<> 144:ef7eb2e8f9f7 1802 TIM_OC3_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 1803
<> 144:ef7eb2e8f9f7 1804 /* Set the Preload enable bit for channel3 */
<> 144:ef7eb2e8f9f7 1805 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
<> 144:ef7eb2e8f9f7 1806
<> 144:ef7eb2e8f9f7 1807 /* Configure the Output Fast mode */
<> 144:ef7eb2e8f9f7 1808 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
<> 144:ef7eb2e8f9f7 1809 htim->Instance->CCMR2 |= sConfig->OCFastMode;
<> 144:ef7eb2e8f9f7 1810 }
<> 144:ef7eb2e8f9f7 1811 break;
<> 144:ef7eb2e8f9f7 1812
<> 144:ef7eb2e8f9f7 1813 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1814 {
<> 144:ef7eb2e8f9f7 1815 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1816 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1817
<> 144:ef7eb2e8f9f7 1818 /* Configure the Channel 4 in PWM mode */
<> 144:ef7eb2e8f9f7 1819 TIM_OC4_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 1820
<> 144:ef7eb2e8f9f7 1821 /* Set the Preload enable bit for channel4 */
<> 144:ef7eb2e8f9f7 1822 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
<> 144:ef7eb2e8f9f7 1823
<> 144:ef7eb2e8f9f7 1824 /* Configure the Output Fast mode */
<> 144:ef7eb2e8f9f7 1825 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
<> 144:ef7eb2e8f9f7 1826 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;
<> 144:ef7eb2e8f9f7 1827 }
<> 144:ef7eb2e8f9f7 1828 break;
<> 144:ef7eb2e8f9f7 1829
<> 144:ef7eb2e8f9f7 1830 case TIM_CHANNEL_5:
<> 144:ef7eb2e8f9f7 1831 {
<> 144:ef7eb2e8f9f7 1832 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1833 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1834
<> 144:ef7eb2e8f9f7 1835 /* Configure the Channel 5 in PWM mode */
<> 144:ef7eb2e8f9f7 1836 TIM_OC5_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 1837
<> 144:ef7eb2e8f9f7 1838 /* Set the Preload enable bit for channel5*/
<> 144:ef7eb2e8f9f7 1839 htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
<> 144:ef7eb2e8f9f7 1840
<> 144:ef7eb2e8f9f7 1841 /* Configure the Output Fast mode */
<> 144:ef7eb2e8f9f7 1842 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
<> 144:ef7eb2e8f9f7 1843 htim->Instance->CCMR3 |= sConfig->OCFastMode;
<> 144:ef7eb2e8f9f7 1844 }
<> 144:ef7eb2e8f9f7 1845 break;
<> 144:ef7eb2e8f9f7 1846
<> 144:ef7eb2e8f9f7 1847 case TIM_CHANNEL_6:
<> 144:ef7eb2e8f9f7 1848 {
<> 144:ef7eb2e8f9f7 1849 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1850 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1851
<> 144:ef7eb2e8f9f7 1852 /* Configure the Channel 5 in PWM mode */
<> 144:ef7eb2e8f9f7 1853 TIM_OC6_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 1854
<> 144:ef7eb2e8f9f7 1855 /* Set the Preload enable bit for channel6 */
<> 144:ef7eb2e8f9f7 1856 htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
<> 144:ef7eb2e8f9f7 1857
<> 144:ef7eb2e8f9f7 1858 /* Configure the Output Fast mode */
<> 144:ef7eb2e8f9f7 1859 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
<> 144:ef7eb2e8f9f7 1860 htim->Instance->CCMR3 |= sConfig->OCFastMode << 8;
<> 144:ef7eb2e8f9f7 1861 }
<> 144:ef7eb2e8f9f7 1862 break;
<> 144:ef7eb2e8f9f7 1863
<> 144:ef7eb2e8f9f7 1864 default:
<> 144:ef7eb2e8f9f7 1865 break;
<> 144:ef7eb2e8f9f7 1866 }
<> 144:ef7eb2e8f9f7 1867
<> 144:ef7eb2e8f9f7 1868 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1869
<> 144:ef7eb2e8f9f7 1870 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1871
<> 144:ef7eb2e8f9f7 1872 return HAL_OK;
<> 144:ef7eb2e8f9f7 1873 }
<> 144:ef7eb2e8f9f7 1874
<> 144:ef7eb2e8f9f7 1875 /**
<> 144:ef7eb2e8f9f7 1876 * @brief Configures the OCRef clear feature
<> 144:ef7eb2e8f9f7 1877 * @param htim: TIM handle
<> 144:ef7eb2e8f9f7 1878 * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
<> 144:ef7eb2e8f9f7 1879 * contains the OCREF clear feature and parameters for the TIM peripheral.
<> 144:ef7eb2e8f9f7 1880 * @param Channel: specifies the TIM Channel
<> 144:ef7eb2e8f9f7 1881 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1882 * @arg TIM_Channel_1: TIM Channel 1
<> 144:ef7eb2e8f9f7 1883 * @arg TIM_Channel_2: TIM Channel 2
<> 144:ef7eb2e8f9f7 1884 * @arg TIM_Channel_3: TIM Channel 3
<> 144:ef7eb2e8f9f7 1885 * @arg TIM_Channel_4: TIM Channel 4
<> 144:ef7eb2e8f9f7 1886 * @arg TIM_Channel_5: TIM Channel 5
<> 144:ef7eb2e8f9f7 1887 * @arg TIM_Channel_6: TIM Channel 6
<> 144:ef7eb2e8f9f7 1888 * @retval None
<> 144:ef7eb2e8f9f7 1889 */
<> 144:ef7eb2e8f9f7 1890 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
<> 144:ef7eb2e8f9f7 1891 TIM_ClearInputConfigTypeDef *sClearInputConfig,
<> 144:ef7eb2e8f9f7 1892 uint32_t Channel)
<> 144:ef7eb2e8f9f7 1893 {
<> 144:ef7eb2e8f9f7 1894 uint32_t tmpsmcr = 0;
<> 144:ef7eb2e8f9f7 1895
<> 144:ef7eb2e8f9f7 1896 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1897 assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1898 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
<> 144:ef7eb2e8f9f7 1899
<> 144:ef7eb2e8f9f7 1900 /* Check input state */
<> 144:ef7eb2e8f9f7 1901 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 1902
<> 144:ef7eb2e8f9f7 1903 switch (sClearInputConfig->ClearInputSource)
<> 144:ef7eb2e8f9f7 1904 {
<> 144:ef7eb2e8f9f7 1905 case TIM_CLEARINPUTSOURCE_NONE:
<> 144:ef7eb2e8f9f7 1906 {
<> 144:ef7eb2e8f9f7 1907 /* Get the TIMx SMCR register value */
<> 144:ef7eb2e8f9f7 1908 tmpsmcr = htim->Instance->SMCR;
<> 144:ef7eb2e8f9f7 1909
<> 144:ef7eb2e8f9f7 1910 /* Clear the OCREF clear selection bit */
<> 144:ef7eb2e8f9f7 1911 tmpsmcr &= ~TIM_SMCR_OCCS;
<> 144:ef7eb2e8f9f7 1912
<> 144:ef7eb2e8f9f7 1913 /* Clear the ETR Bits */
<> 144:ef7eb2e8f9f7 1914 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
<> 144:ef7eb2e8f9f7 1915
<> 144:ef7eb2e8f9f7 1916 /* Set TIMx_SMCR */
<> 144:ef7eb2e8f9f7 1917 htim->Instance->SMCR = tmpsmcr;
<> 144:ef7eb2e8f9f7 1918 }
<> 144:ef7eb2e8f9f7 1919 break;
<> 144:ef7eb2e8f9f7 1920
<> 144:ef7eb2e8f9f7 1921 case TIM_CLEARINPUTSOURCE_OCREFCLR:
<> 144:ef7eb2e8f9f7 1922 {
<> 144:ef7eb2e8f9f7 1923 /* Clear the OCREF clear selection bit */
<> 144:ef7eb2e8f9f7 1924 htim->Instance->SMCR &= ~TIM_SMCR_OCCS;
<> 144:ef7eb2e8f9f7 1925 }
<> 144:ef7eb2e8f9f7 1926 break;
<> 144:ef7eb2e8f9f7 1927
<> 144:ef7eb2e8f9f7 1928 case TIM_CLEARINPUTSOURCE_ETR:
<> 144:ef7eb2e8f9f7 1929 {
<> 144:ef7eb2e8f9f7 1930 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1931 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
<> 144:ef7eb2e8f9f7 1932 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
<> 144:ef7eb2e8f9f7 1933 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
<> 144:ef7eb2e8f9f7 1934
<> 144:ef7eb2e8f9f7 1935 TIM_ETR_SetConfig(htim->Instance,
<> 144:ef7eb2e8f9f7 1936 sClearInputConfig->ClearInputPrescaler,
<> 144:ef7eb2e8f9f7 1937 sClearInputConfig->ClearInputPolarity,
<> 144:ef7eb2e8f9f7 1938 sClearInputConfig->ClearInputFilter);
<> 144:ef7eb2e8f9f7 1939
<> 144:ef7eb2e8f9f7 1940 /* Set the OCREF clear selection bit */
<> 144:ef7eb2e8f9f7 1941 htim->Instance->SMCR |= TIM_SMCR_OCCS;
<> 144:ef7eb2e8f9f7 1942 }
<> 144:ef7eb2e8f9f7 1943 break;
<> 144:ef7eb2e8f9f7 1944 default:
<> 144:ef7eb2e8f9f7 1945 break;
<> 144:ef7eb2e8f9f7 1946 }
<> 144:ef7eb2e8f9f7 1947
<> 144:ef7eb2e8f9f7 1948 switch (Channel)
<> 144:ef7eb2e8f9f7 1949 {
<> 144:ef7eb2e8f9f7 1950 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1951 {
<> 144:ef7eb2e8f9f7 1952 if(sClearInputConfig->ClearInputState != RESET)
<> 144:ef7eb2e8f9f7 1953 {
<> 144:ef7eb2e8f9f7 1954 /* Enable the Ocref clear feature for Channel 1 */
<> 144:ef7eb2e8f9f7 1955 htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
<> 144:ef7eb2e8f9f7 1956 }
<> 144:ef7eb2e8f9f7 1957 else
<> 144:ef7eb2e8f9f7 1958 {
<> 144:ef7eb2e8f9f7 1959 /* Disable the Ocref clear feature for Channel 1 */
<> 144:ef7eb2e8f9f7 1960 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
<> 144:ef7eb2e8f9f7 1961 }
<> 144:ef7eb2e8f9f7 1962 }
<> 144:ef7eb2e8f9f7 1963 break;
<> 144:ef7eb2e8f9f7 1964 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1965 {
<> 144:ef7eb2e8f9f7 1966 if(sClearInputConfig->ClearInputState != RESET)
<> 144:ef7eb2e8f9f7 1967 {
<> 144:ef7eb2e8f9f7 1968 /* Enable the Ocref clear feature for Channel 2 */
<> 144:ef7eb2e8f9f7 1969 htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
<> 144:ef7eb2e8f9f7 1970 }
<> 144:ef7eb2e8f9f7 1971 else
<> 144:ef7eb2e8f9f7 1972 {
<> 144:ef7eb2e8f9f7 1973 /* Disable the Ocref clear feature for Channel 2 */
<> 144:ef7eb2e8f9f7 1974 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
<> 144:ef7eb2e8f9f7 1975 }
<> 144:ef7eb2e8f9f7 1976 }
<> 144:ef7eb2e8f9f7 1977 break;
<> 144:ef7eb2e8f9f7 1978 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1979 {
<> 144:ef7eb2e8f9f7 1980 if(sClearInputConfig->ClearInputState != RESET)
<> 144:ef7eb2e8f9f7 1981 {
<> 144:ef7eb2e8f9f7 1982 /* Enable the Ocref clear feature for Channel 3 */
<> 144:ef7eb2e8f9f7 1983 htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
<> 144:ef7eb2e8f9f7 1984 }
<> 144:ef7eb2e8f9f7 1985 else
<> 144:ef7eb2e8f9f7 1986 {
<> 144:ef7eb2e8f9f7 1987 /* Disable the Ocref clear feature for Channel 3 */
<> 144:ef7eb2e8f9f7 1988 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
<> 144:ef7eb2e8f9f7 1989 }
<> 144:ef7eb2e8f9f7 1990 }
<> 144:ef7eb2e8f9f7 1991 break;
<> 144:ef7eb2e8f9f7 1992 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1993 {
<> 144:ef7eb2e8f9f7 1994 if(sClearInputConfig->ClearInputState != RESET)
<> 144:ef7eb2e8f9f7 1995 {
<> 144:ef7eb2e8f9f7 1996 /* Enable the Ocref clear feature for Channel 4 */
<> 144:ef7eb2e8f9f7 1997 htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
<> 144:ef7eb2e8f9f7 1998 }
<> 144:ef7eb2e8f9f7 1999 else
<> 144:ef7eb2e8f9f7 2000 {
<> 144:ef7eb2e8f9f7 2001 /* Disable the Ocref clear feature for Channel 4 */
<> 144:ef7eb2e8f9f7 2002 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
<> 144:ef7eb2e8f9f7 2003 }
<> 144:ef7eb2e8f9f7 2004 }
<> 144:ef7eb2e8f9f7 2005 break;
<> 144:ef7eb2e8f9f7 2006 case TIM_CHANNEL_5:
<> 144:ef7eb2e8f9f7 2007 {
<> 144:ef7eb2e8f9f7 2008 if(sClearInputConfig->ClearInputState != RESET)
<> 144:ef7eb2e8f9f7 2009 {
<> 144:ef7eb2e8f9f7 2010 /* Enable the Ocref clear feature for Channel 1 */
<> 144:ef7eb2e8f9f7 2011 htim->Instance->CCMR3 |= TIM_CCMR3_OC5CE;
<> 144:ef7eb2e8f9f7 2012 }
<> 144:ef7eb2e8f9f7 2013 else
<> 144:ef7eb2e8f9f7 2014 {
<> 144:ef7eb2e8f9f7 2015 /* Disable the Ocref clear feature for Channel 1 */
<> 144:ef7eb2e8f9f7 2016 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5CE;
<> 144:ef7eb2e8f9f7 2017 }
<> 144:ef7eb2e8f9f7 2018 }
<> 144:ef7eb2e8f9f7 2019 break;
<> 144:ef7eb2e8f9f7 2020 case TIM_CHANNEL_6:
<> 144:ef7eb2e8f9f7 2021 {
<> 144:ef7eb2e8f9f7 2022 if(sClearInputConfig->ClearInputState != RESET)
<> 144:ef7eb2e8f9f7 2023 {
<> 144:ef7eb2e8f9f7 2024 /* Enable the Ocref clear feature for Channel 1 */
<> 144:ef7eb2e8f9f7 2025 htim->Instance->CCMR3 |= TIM_CCMR3_OC6CE;
<> 144:ef7eb2e8f9f7 2026 }
<> 144:ef7eb2e8f9f7 2027 else
<> 144:ef7eb2e8f9f7 2028 {
<> 144:ef7eb2e8f9f7 2029 /* Disable the Ocref clear feature for Channel 1 */
<> 144:ef7eb2e8f9f7 2030 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6CE;
<> 144:ef7eb2e8f9f7 2031 }
<> 144:ef7eb2e8f9f7 2032 }
<> 144:ef7eb2e8f9f7 2033 break;
<> 144:ef7eb2e8f9f7 2034 default:
<> 144:ef7eb2e8f9f7 2035 break;
<> 144:ef7eb2e8f9f7 2036 }
<> 144:ef7eb2e8f9f7 2037
<> 144:ef7eb2e8f9f7 2038 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 2039
<> 144:ef7eb2e8f9f7 2040 return HAL_OK;
<> 144:ef7eb2e8f9f7 2041 }
<> 144:ef7eb2e8f9f7 2042
<> 144:ef7eb2e8f9f7 2043 /**
<> 144:ef7eb2e8f9f7 2044 * @brief Configures the TIM in master mode.
<> 144:ef7eb2e8f9f7 2045 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2046 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 2047 * @param sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that
<> 144:ef7eb2e8f9f7 2048 * contains the selected trigger output (TRGO) and the Master/Slave
<> 144:ef7eb2e8f9f7 2049 * mode.
<> 144:ef7eb2e8f9f7 2050 * @retval HAL status
<> 144:ef7eb2e8f9f7 2051 */
<> 144:ef7eb2e8f9f7 2052 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig)
<> 144:ef7eb2e8f9f7 2053 {
<> 144:ef7eb2e8f9f7 2054 uint32_t tmpcr2;
<> 144:ef7eb2e8f9f7 2055 uint32_t tmpsmcr;
<> 144:ef7eb2e8f9f7 2056
<> 144:ef7eb2e8f9f7 2057 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2058 assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2059 assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
<> 144:ef7eb2e8f9f7 2060 assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
<> 144:ef7eb2e8f9f7 2061
<> 144:ef7eb2e8f9f7 2062 /* Check input state */
<> 144:ef7eb2e8f9f7 2063 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 2064
<> 144:ef7eb2e8f9f7 2065 /* Get the TIMx CR2 register value */
<> 144:ef7eb2e8f9f7 2066 tmpcr2 = htim->Instance->CR2;
<> 144:ef7eb2e8f9f7 2067
<> 144:ef7eb2e8f9f7 2068 /* Get the TIMx SMCR register value */
<> 144:ef7eb2e8f9f7 2069 tmpsmcr = htim->Instance->SMCR;
<> 144:ef7eb2e8f9f7 2070
<> 144:ef7eb2e8f9f7 2071 /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
<> 144:ef7eb2e8f9f7 2072 if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
<> 144:ef7eb2e8f9f7 2073 {
<> 144:ef7eb2e8f9f7 2074 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2075 assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
<> 144:ef7eb2e8f9f7 2076
<> 144:ef7eb2e8f9f7 2077 /* Clear the MMS2 bits */
<> 144:ef7eb2e8f9f7 2078 tmpcr2 &= ~TIM_CR2_MMS2;
<> 144:ef7eb2e8f9f7 2079 /* Select the TRGO2 source*/
<> 144:ef7eb2e8f9f7 2080 tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
<> 144:ef7eb2e8f9f7 2081 }
<> 144:ef7eb2e8f9f7 2082
<> 144:ef7eb2e8f9f7 2083 /* Reset the MMS Bits */
<> 144:ef7eb2e8f9f7 2084 tmpcr2 &= ~TIM_CR2_MMS;
<> 144:ef7eb2e8f9f7 2085 /* Select the TRGO source */
<> 144:ef7eb2e8f9f7 2086 tmpcr2 |= sMasterConfig->MasterOutputTrigger;
<> 144:ef7eb2e8f9f7 2087
<> 144:ef7eb2e8f9f7 2088 /* Reset the MSM Bit */
<> 144:ef7eb2e8f9f7 2089 tmpsmcr &= ~TIM_SMCR_MSM;
<> 144:ef7eb2e8f9f7 2090 /* Set master mode */
<> 144:ef7eb2e8f9f7 2091 tmpsmcr |= sMasterConfig->MasterSlaveMode;
<> 144:ef7eb2e8f9f7 2092
<> 144:ef7eb2e8f9f7 2093 /* Update TIMx CR2 */
<> 144:ef7eb2e8f9f7 2094 htim->Instance->CR2 = tmpcr2;
<> 144:ef7eb2e8f9f7 2095
<> 144:ef7eb2e8f9f7 2096 /* Update TIMx SMCR */
<> 144:ef7eb2e8f9f7 2097 htim->Instance->SMCR = tmpsmcr;
<> 144:ef7eb2e8f9f7 2098
<> 144:ef7eb2e8f9f7 2099 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 2100
<> 144:ef7eb2e8f9f7 2101 return HAL_OK;
<> 144:ef7eb2e8f9f7 2102 }
<> 144:ef7eb2e8f9f7 2103
<> 144:ef7eb2e8f9f7 2104 /**
<> 144:ef7eb2e8f9f7 2105 * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
<> 144:ef7eb2e8f9f7 2106 * and the AOE(automatic output enable).
<> 144:ef7eb2e8f9f7 2107 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2108 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 2109 * @param sBreakDeadTimeConfig: pointer to a TIM_ConfigBreakDeadConfig_TypeDef structure that
<> 144:ef7eb2e8f9f7 2110 * contains the BDTR Register configuration information for the TIM peripheral.
<> 144:ef7eb2e8f9f7 2111 * @retval HAL status
<> 144:ef7eb2e8f9f7 2112 */
<> 144:ef7eb2e8f9f7 2113 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
<> 144:ef7eb2e8f9f7 2114 TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig)
<> 144:ef7eb2e8f9f7 2115 {
<> 144:ef7eb2e8f9f7 2116 uint32_t tmpbdtr = 0;
<> 144:ef7eb2e8f9f7 2117
<> 144:ef7eb2e8f9f7 2118 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2119 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2120 assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
<> 144:ef7eb2e8f9f7 2121 assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
<> 144:ef7eb2e8f9f7 2122 assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
<> 144:ef7eb2e8f9f7 2123 assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
<> 144:ef7eb2e8f9f7 2124 assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
<> 144:ef7eb2e8f9f7 2125 assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
<> 144:ef7eb2e8f9f7 2126 assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
<> 144:ef7eb2e8f9f7 2127 assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
<> 144:ef7eb2e8f9f7 2128 assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
<> 144:ef7eb2e8f9f7 2129 assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
<> 144:ef7eb2e8f9f7 2130 assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
<> 144:ef7eb2e8f9f7 2131
<> 144:ef7eb2e8f9f7 2132 /* Check input state */
<> 144:ef7eb2e8f9f7 2133 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 2134
<> 144:ef7eb2e8f9f7 2135 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 2136
<> 144:ef7eb2e8f9f7 2137 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
<> 144:ef7eb2e8f9f7 2138 the OSSI State, the dead time value and the Automatic Output Enable Bit */
<> 144:ef7eb2e8f9f7 2139
<> 144:ef7eb2e8f9f7 2140 /* Clear the BDTR bits */
<> 144:ef7eb2e8f9f7 2141 tmpbdtr &= ~(TIM_BDTR_DTG | TIM_BDTR_LOCK | TIM_BDTR_OSSI |
<> 144:ef7eb2e8f9f7 2142 TIM_BDTR_OSSR | TIM_BDTR_BKE | TIM_BDTR_BKP |
<> 144:ef7eb2e8f9f7 2143 TIM_BDTR_AOE | TIM_BDTR_MOE | TIM_BDTR_BKF |
<> 144:ef7eb2e8f9f7 2144 TIM_BDTR_BK2F | TIM_BDTR_BK2E | TIM_BDTR_BK2P);
<> 144:ef7eb2e8f9f7 2145
<> 144:ef7eb2e8f9f7 2146 /* Set the BDTR bits */
<> 144:ef7eb2e8f9f7 2147 tmpbdtr |= sBreakDeadTimeConfig->DeadTime;
<> 144:ef7eb2e8f9f7 2148 tmpbdtr |= sBreakDeadTimeConfig->LockLevel;
<> 144:ef7eb2e8f9f7 2149 tmpbdtr |= sBreakDeadTimeConfig->OffStateIDLEMode;
<> 144:ef7eb2e8f9f7 2150 tmpbdtr |= sBreakDeadTimeConfig->OffStateRunMode;
<> 144:ef7eb2e8f9f7 2151 tmpbdtr |= sBreakDeadTimeConfig->BreakState;
<> 144:ef7eb2e8f9f7 2152 tmpbdtr |= sBreakDeadTimeConfig->BreakPolarity;
<> 144:ef7eb2e8f9f7 2153 tmpbdtr |= sBreakDeadTimeConfig->AutomaticOutput;
<> 144:ef7eb2e8f9f7 2154 tmpbdtr |= (sBreakDeadTimeConfig->BreakFilter << BDTR_BKF_SHIFT);
<> 144:ef7eb2e8f9f7 2155 tmpbdtr |= (sBreakDeadTimeConfig->Break2Filter << BDTR_BK2F_SHIFT);
<> 144:ef7eb2e8f9f7 2156 tmpbdtr |= sBreakDeadTimeConfig->Break2State;
<> 144:ef7eb2e8f9f7 2157 tmpbdtr |= sBreakDeadTimeConfig->Break2Polarity;
<> 144:ef7eb2e8f9f7 2158
<> 144:ef7eb2e8f9f7 2159 /* Set TIMx_BDTR */
<> 144:ef7eb2e8f9f7 2160 htim->Instance->BDTR = tmpbdtr;
<> 144:ef7eb2e8f9f7 2161
<> 144:ef7eb2e8f9f7 2162 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 2163
<> 144:ef7eb2e8f9f7 2164 return HAL_OK;
<> 144:ef7eb2e8f9f7 2165 }
<> 144:ef7eb2e8f9f7 2166 #if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
<> 144:ef7eb2e8f9f7 2167 /**
<> 144:ef7eb2e8f9f7 2168 * @brief Configures the break input source.
<> 144:ef7eb2e8f9f7 2169 * @param htim: TIM handle.
<> 144:ef7eb2e8f9f7 2170 * @param BreakInput: Break input to configure
<> 144:ef7eb2e8f9f7 2171 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2172 * @arg TIM_BREAKINPUT_BRK: Timer break input
<> 144:ef7eb2e8f9f7 2173 * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
<> 144:ef7eb2e8f9f7 2174 * @param sBreakInputConfig: Break input source configuration
<> 144:ef7eb2e8f9f7 2175 * @retval HAL status
<> 144:ef7eb2e8f9f7 2176 */
<> 144:ef7eb2e8f9f7 2177 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
<> 144:ef7eb2e8f9f7 2178 uint32_t BreakInput,
<> 144:ef7eb2e8f9f7 2179 TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
<> 144:ef7eb2e8f9f7 2180
<> 144:ef7eb2e8f9f7 2181 {
<> 144:ef7eb2e8f9f7 2182 uint32_t tmporx = 0;
<> 144:ef7eb2e8f9f7 2183 uint32_t bkin_enable_mask = 0;
<> 144:ef7eb2e8f9f7 2184 uint32_t bkin_enable_bitpos = 0;
<> 144:ef7eb2e8f9f7 2185
<> 144:ef7eb2e8f9f7 2186 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2187 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2188 assert_param(IS_TIM_BREAKINPUT(BreakInput));
<> 144:ef7eb2e8f9f7 2189 assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source));
<> 144:ef7eb2e8f9f7 2190 assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable));
<> 144:ef7eb2e8f9f7 2191
<> 144:ef7eb2e8f9f7 2192 /* Check input state */
<> 144:ef7eb2e8f9f7 2193 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 2194
<> 144:ef7eb2e8f9f7 2195 switch(sBreakInputConfig->Source)
<> 144:ef7eb2e8f9f7 2196 {
<> 144:ef7eb2e8f9f7 2197 case TIM_BREAKINPUTSOURCE_BKIN:
<> 144:ef7eb2e8f9f7 2198 {
<> 144:ef7eb2e8f9f7 2199 bkin_enable_mask = TIM1_AF1_BKINE;
<> 144:ef7eb2e8f9f7 2200 bkin_enable_bitpos = 0;
<> 144:ef7eb2e8f9f7 2201 }
<> 144:ef7eb2e8f9f7 2202 break;
<> 144:ef7eb2e8f9f7 2203
<> 144:ef7eb2e8f9f7 2204 case TIM_BREAKINPUTSOURCE_DFSDM1:
<> 144:ef7eb2e8f9f7 2205 {
<> 144:ef7eb2e8f9f7 2206 bkin_enable_mask = TIM1_AF1_BKDF1BKE;
<> 144:ef7eb2e8f9f7 2207 bkin_enable_bitpos = 8;
<> 144:ef7eb2e8f9f7 2208 }
<> 144:ef7eb2e8f9f7 2209 break;
<> 144:ef7eb2e8f9f7 2210
<> 144:ef7eb2e8f9f7 2211 default:
<> 144:ef7eb2e8f9f7 2212 break;
<> 144:ef7eb2e8f9f7 2213 }
<> 144:ef7eb2e8f9f7 2214
<> 144:ef7eb2e8f9f7 2215 switch(BreakInput)
<> 144:ef7eb2e8f9f7 2216 {
<> 144:ef7eb2e8f9f7 2217 case TIM_BREAKINPUT_BRK:
<> 144:ef7eb2e8f9f7 2218 {
<> 144:ef7eb2e8f9f7 2219 /* Get the TIMx_AF1 register value */
<> 144:ef7eb2e8f9f7 2220 tmporx = htim->Instance->AF1;
<> 144:ef7eb2e8f9f7 2221
<> 144:ef7eb2e8f9f7 2222 /* Enable the break input */
<> 144:ef7eb2e8f9f7 2223 tmporx &= ~bkin_enable_mask;
<> 144:ef7eb2e8f9f7 2224 tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
<> 144:ef7eb2e8f9f7 2225
<> 144:ef7eb2e8f9f7 2226 /* Set TIMx_AF1 */
<> 144:ef7eb2e8f9f7 2227 htim->Instance->AF1 = tmporx;
<> 144:ef7eb2e8f9f7 2228 }
<> 144:ef7eb2e8f9f7 2229 break;
<> 144:ef7eb2e8f9f7 2230 case TIM_BREAKINPUT_BRK2:
<> 144:ef7eb2e8f9f7 2231 {
<> 144:ef7eb2e8f9f7 2232 /* Get the TIMx_AF2 register value */
<> 144:ef7eb2e8f9f7 2233 tmporx = htim->Instance->AF2;
<> 144:ef7eb2e8f9f7 2234
<> 144:ef7eb2e8f9f7 2235 /* Enable the break input */
<> 144:ef7eb2e8f9f7 2236 tmporx &= ~bkin_enable_mask;
<> 144:ef7eb2e8f9f7 2237 tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
<> 144:ef7eb2e8f9f7 2238
<> 144:ef7eb2e8f9f7 2239 /* Set TIMx_AF2 */
<> 144:ef7eb2e8f9f7 2240 htim->Instance->AF2 = tmporx;
<> 144:ef7eb2e8f9f7 2241 }
<> 144:ef7eb2e8f9f7 2242 break;
<> 144:ef7eb2e8f9f7 2243 default:
<> 144:ef7eb2e8f9f7 2244 break;
<> 144:ef7eb2e8f9f7 2245 }
<> 144:ef7eb2e8f9f7 2246
<> 144:ef7eb2e8f9f7 2247 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 2248
<> 144:ef7eb2e8f9f7 2249 return HAL_OK;
<> 144:ef7eb2e8f9f7 2250 }
<> 144:ef7eb2e8f9f7 2251 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 2252
<> 144:ef7eb2e8f9f7 2253 /**
<> 144:ef7eb2e8f9f7 2254 * @brief Configures the TIM2, TIM5 and TIM11 Remapping input capabilities.
<> 144:ef7eb2e8f9f7 2255 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2256 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 2257 * @param Remap: specifies the TIM input remapping source.
<> 144:ef7eb2e8f9f7 2258 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2259 * @arg TIM_TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default)
<> 144:ef7eb2e8f9f7 2260 * @arg TIM_TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trigger output.
<> 144:ef7eb2e8f9f7 2261 * @arg TIM_TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF.
<> 144:ef7eb2e8f9f7 2262 * @arg TIM_TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF.
<> 144:ef7eb2e8f9f7 2263 * @arg TIM_TIM5_GPIO: TIM5 CH4 input is connected to dedicated Timer pin(default)
<> 144:ef7eb2e8f9f7 2264 * @arg TIM_TIM5_LSI: TIM5 CH4 input is connected to LSI clock.
<> 144:ef7eb2e8f9f7 2265 * @arg TIM_TIM5_LSE: TIM5 CH4 input is connected to LSE clock.
<> 144:ef7eb2e8f9f7 2266 * @arg TIM_TIM5_RTC: TIM5 CH4 input is connected to RTC Output event.
<> 144:ef7eb2e8f9f7 2267 * @arg TIM_TIM11_GPIO: TIM11 CH4 input is connected to dedicated Timer pin(default)
<> 144:ef7eb2e8f9f7 2268 * @arg TIM_TIM11_SPDIF: SPDIF Frame synchronous
<> 144:ef7eb2e8f9f7 2269 * @arg TIM_TIM11_HSE: TIM11 CH4 input is connected to HSE_RTC clock
<> 144:ef7eb2e8f9f7 2270 * (HSE divided by a programmable prescaler)
<> 144:ef7eb2e8f9f7 2271 * @arg TIM_TIM11_MCO1: TIM11 CH1 input is connected to MCO1
<> 144:ef7eb2e8f9f7 2272 * @retval HAL status
<> 144:ef7eb2e8f9f7 2273 */
<> 144:ef7eb2e8f9f7 2274 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
<> 144:ef7eb2e8f9f7 2275 {
<> 144:ef7eb2e8f9f7 2276 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 2277
<> 144:ef7eb2e8f9f7 2278 /* Check parameters */
<> 144:ef7eb2e8f9f7 2279 assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2280 assert_param(IS_TIM_REMAP(Remap));
<> 144:ef7eb2e8f9f7 2281
<> 144:ef7eb2e8f9f7 2282 /* Set the Timer remapping configuration */
<> 144:ef7eb2e8f9f7 2283 htim->Instance->OR = Remap;
<> 144:ef7eb2e8f9f7 2284
<> 144:ef7eb2e8f9f7 2285 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 2286
<> 144:ef7eb2e8f9f7 2287 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 2288
<> 144:ef7eb2e8f9f7 2289 return HAL_OK;
<> 144:ef7eb2e8f9f7 2290 }
<> 144:ef7eb2e8f9f7 2291
<> 144:ef7eb2e8f9f7 2292 /**
<> 144:ef7eb2e8f9f7 2293 * @brief Group channel 5 and channel 1, 2 or 3
<> 144:ef7eb2e8f9f7 2294 * @param htim: TIM handle.
<> 144:ef7eb2e8f9f7 2295 * @param OCRef: specifies the reference signal(s) the OC5REF is combined with.
<> 144:ef7eb2e8f9f7 2296 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 2297 * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC
<> 144:ef7eb2e8f9f7 2298 * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF
<> 144:ef7eb2e8f9f7 2299 * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF
<> 144:ef7eb2e8f9f7 2300 * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
<> 144:ef7eb2e8f9f7 2301 * @retval HAL status
<> 144:ef7eb2e8f9f7 2302 */
<> 144:ef7eb2e8f9f7 2303 HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t OCRef)
<> 144:ef7eb2e8f9f7 2304 {
<> 144:ef7eb2e8f9f7 2305 /* Check parameters */
<> 144:ef7eb2e8f9f7 2306 assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2307 assert_param(IS_TIM_GROUPCH5(OCRef));
<> 144:ef7eb2e8f9f7 2308
<> 144:ef7eb2e8f9f7 2309 /* Process Locked */
<> 144:ef7eb2e8f9f7 2310 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 2311
<> 144:ef7eb2e8f9f7 2312 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 2313
<> 144:ef7eb2e8f9f7 2314 /* Clear GC5Cx bit fields */
<> 144:ef7eb2e8f9f7 2315 htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3|TIM_CCR5_GC5C2|TIM_CCR5_GC5C1);
<> 144:ef7eb2e8f9f7 2316
<> 144:ef7eb2e8f9f7 2317 /* Set GC5Cx bit fields */
<> 144:ef7eb2e8f9f7 2318 htim->Instance->CCR5 |= OCRef;
<> 144:ef7eb2e8f9f7 2319
<> 144:ef7eb2e8f9f7 2320 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 2321
<> 144:ef7eb2e8f9f7 2322 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 2323
<> 144:ef7eb2e8f9f7 2324 return HAL_OK;
<> 144:ef7eb2e8f9f7 2325 }
<> 144:ef7eb2e8f9f7 2326
<> 144:ef7eb2e8f9f7 2327 /**
<> 144:ef7eb2e8f9f7 2328 * @}
<> 144:ef7eb2e8f9f7 2329 */
<> 144:ef7eb2e8f9f7 2330
<> 144:ef7eb2e8f9f7 2331 /** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
<> 144:ef7eb2e8f9f7 2332 * @brief Extended Callbacks functions
<> 144:ef7eb2e8f9f7 2333 *
<> 144:ef7eb2e8f9f7 2334 @verbatim
<> 144:ef7eb2e8f9f7 2335 ==============================================================================
<> 144:ef7eb2e8f9f7 2336 ##### Extension Callbacks functions #####
<> 144:ef7eb2e8f9f7 2337 ==============================================================================
<> 144:ef7eb2e8f9f7 2338 [..]
<> 144:ef7eb2e8f9f7 2339 This section provides Extension TIM callback functions:
<> 144:ef7eb2e8f9f7 2340 (+) Timer Commutation callback
<> 144:ef7eb2e8f9f7 2341 (+) Timer Break callback
<> 144:ef7eb2e8f9f7 2342
<> 144:ef7eb2e8f9f7 2343 @endverbatim
<> 144:ef7eb2e8f9f7 2344 * @{
<> 144:ef7eb2e8f9f7 2345 */
<> 144:ef7eb2e8f9f7 2346
<> 144:ef7eb2e8f9f7 2347 /**
<> 144:ef7eb2e8f9f7 2348 * @brief Hall commutation changed callback in non blocking mode
<> 144:ef7eb2e8f9f7 2349 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2350 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 2351 * @retval None
<> 144:ef7eb2e8f9f7 2352 */
<> 144:ef7eb2e8f9f7 2353 __weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 2354 {
<> 144:ef7eb2e8f9f7 2355 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2356 UNUSED(htim);
<> 144:ef7eb2e8f9f7 2357
<> 144:ef7eb2e8f9f7 2358 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2359 the HAL_TIMEx_CommutationCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 2360 */
<> 144:ef7eb2e8f9f7 2361 }
<> 144:ef7eb2e8f9f7 2362
<> 144:ef7eb2e8f9f7 2363 /**
<> 144:ef7eb2e8f9f7 2364 * @brief Hall Break detection callback in non blocking mode
<> 144:ef7eb2e8f9f7 2365 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2366 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 2367 * @retval None
<> 144:ef7eb2e8f9f7 2368 */
<> 144:ef7eb2e8f9f7 2369 __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 2370 {
<> 144:ef7eb2e8f9f7 2371 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2372 UNUSED(htim);
<> 144:ef7eb2e8f9f7 2373
<> 144:ef7eb2e8f9f7 2374 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2375 the HAL_TIMEx_BreakCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 2376 */
<> 144:ef7eb2e8f9f7 2377 }
<> 144:ef7eb2e8f9f7 2378
<> 144:ef7eb2e8f9f7 2379 /**
<> 144:ef7eb2e8f9f7 2380 * @}
<> 144:ef7eb2e8f9f7 2381 */
<> 144:ef7eb2e8f9f7 2382
<> 144:ef7eb2e8f9f7 2383 /** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
<> 144:ef7eb2e8f9f7 2384 * @brief Extended Peripheral State functions
<> 144:ef7eb2e8f9f7 2385 *
<> 144:ef7eb2e8f9f7 2386 @verbatim
<> 144:ef7eb2e8f9f7 2387 ==============================================================================
<> 144:ef7eb2e8f9f7 2388 ##### Extension Peripheral State functions #####
<> 144:ef7eb2e8f9f7 2389 ==============================================================================
<> 144:ef7eb2e8f9f7 2390 [..]
<> 144:ef7eb2e8f9f7 2391 This subsection permits to get in run-time the status of the peripheral
<> 144:ef7eb2e8f9f7 2392 and the data flow.
<> 144:ef7eb2e8f9f7 2393
<> 144:ef7eb2e8f9f7 2394 @endverbatim
<> 144:ef7eb2e8f9f7 2395 * @{
<> 144:ef7eb2e8f9f7 2396 */
<> 144:ef7eb2e8f9f7 2397
<> 144:ef7eb2e8f9f7 2398 /**
<> 144:ef7eb2e8f9f7 2399 * @brief Return the TIM Hall Sensor interface state
<> 144:ef7eb2e8f9f7 2400 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2401 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 2402 * @retval HAL state
<> 144:ef7eb2e8f9f7 2403 */
<> 144:ef7eb2e8f9f7 2404 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 2405 {
<> 144:ef7eb2e8f9f7 2406 return htim->State;
<> 144:ef7eb2e8f9f7 2407 }
<> 144:ef7eb2e8f9f7 2408
<> 144:ef7eb2e8f9f7 2409 /**
<> 144:ef7eb2e8f9f7 2410 * @}
<> 144:ef7eb2e8f9f7 2411 */
<> 144:ef7eb2e8f9f7 2412
<> 144:ef7eb2e8f9f7 2413 /**
<> 144:ef7eb2e8f9f7 2414 * @brief TIM DMA Commutation callback.
<> 144:ef7eb2e8f9f7 2415 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2416 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 2417 * @retval None
<> 144:ef7eb2e8f9f7 2418 */
<> 144:ef7eb2e8f9f7 2419 void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2420 {
<> 144:ef7eb2e8f9f7 2421 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 2422
<> 144:ef7eb2e8f9f7 2423 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 2424
<> 144:ef7eb2e8f9f7 2425 HAL_TIMEx_CommutationCallback(htim);
<> 144:ef7eb2e8f9f7 2426 }
<> 144:ef7eb2e8f9f7 2427
<> 144:ef7eb2e8f9f7 2428 /**
<> 144:ef7eb2e8f9f7 2429 * @brief Enables or disables the TIM Capture Compare Channel xN.
<> 144:ef7eb2e8f9f7 2430 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 2431 * @param Channel: specifies the TIM Channel
<> 144:ef7eb2e8f9f7 2432 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2433 * @arg TIM_Channel_1: TIM Channel 1
<> 144:ef7eb2e8f9f7 2434 * @arg TIM_Channel_2: TIM Channel 2
<> 144:ef7eb2e8f9f7 2435 * @arg TIM_Channel_3: TIM Channel 3
<> 144:ef7eb2e8f9f7 2436 * @param ChannelNState: specifies the TIM Channel CCxNE bit new state.
<> 144:ef7eb2e8f9f7 2437 * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
<> 144:ef7eb2e8f9f7 2438 * @retval None
<> 144:ef7eb2e8f9f7 2439 */
<> 144:ef7eb2e8f9f7 2440 static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState)
<> 144:ef7eb2e8f9f7 2441 {
<> 144:ef7eb2e8f9f7 2442 uint32_t tmp = 0;
<> 144:ef7eb2e8f9f7 2443
<> 144:ef7eb2e8f9f7 2444 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2445 assert_param(IS_TIM_ADVANCED_INSTANCE(TIMx));
<> 144:ef7eb2e8f9f7 2446 assert_param(IS_TIM_COMPLEMENTARY_CHANNELS(Channel));
<> 144:ef7eb2e8f9f7 2447
<> 144:ef7eb2e8f9f7 2448 tmp = TIM_CCER_CC1NE << Channel;
<> 144:ef7eb2e8f9f7 2449
<> 144:ef7eb2e8f9f7 2450 /* Reset the CCxNE Bit */
<> 144:ef7eb2e8f9f7 2451 TIMx->CCER &= ~tmp;
<> 144:ef7eb2e8f9f7 2452
<> 144:ef7eb2e8f9f7 2453 /* Set or reset the CCxNE Bit */
<> 144:ef7eb2e8f9f7 2454 TIMx->CCER |= (uint32_t)(ChannelNState << Channel);
<> 144:ef7eb2e8f9f7 2455 }
<> 144:ef7eb2e8f9f7 2456
<> 144:ef7eb2e8f9f7 2457 /**
<> 144:ef7eb2e8f9f7 2458 * @brief Timer Output Compare 5 configuration
<> 144:ef7eb2e8f9f7 2459 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 2460 * @param OC_Config: The output configuration structure
<> 144:ef7eb2e8f9f7 2461 * @retval None
<> 144:ef7eb2e8f9f7 2462 */
<> 144:ef7eb2e8f9f7 2463 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
<> 144:ef7eb2e8f9f7 2464 {
<> 144:ef7eb2e8f9f7 2465 uint32_t tmpccmrx = 0;
<> 144:ef7eb2e8f9f7 2466 uint32_t tmpccer = 0;
<> 144:ef7eb2e8f9f7 2467 uint32_t tmpcr2 = 0;
<> 144:ef7eb2e8f9f7 2468
<> 144:ef7eb2e8f9f7 2469 /* Disable the output: Reset the CCxE Bit */
<> 144:ef7eb2e8f9f7 2470 TIMx->CCER &= ~TIM_CCER_CC5E;
<> 144:ef7eb2e8f9f7 2471
<> 144:ef7eb2e8f9f7 2472 /* Get the TIMx CCER register value */
<> 144:ef7eb2e8f9f7 2473 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 2474 /* Get the TIMx CR2 register value */
<> 144:ef7eb2e8f9f7 2475 tmpcr2 = TIMx->CR2;
<> 144:ef7eb2e8f9f7 2476 /* Get the TIMx CCMR1 register value */
<> 144:ef7eb2e8f9f7 2477 tmpccmrx = TIMx->CCMR3;
<> 144:ef7eb2e8f9f7 2478
<> 144:ef7eb2e8f9f7 2479 /* Reset the Output Compare Mode Bits */
<> 144:ef7eb2e8f9f7 2480 tmpccmrx &= ~(TIM_CCMR3_OC5M);
<> 144:ef7eb2e8f9f7 2481 /* Select the Output Compare Mode */
<> 144:ef7eb2e8f9f7 2482 tmpccmrx |= OC_Config->OCMode;
<> 144:ef7eb2e8f9f7 2483
<> 144:ef7eb2e8f9f7 2484 /* Reset the Output Polarity level */
<> 144:ef7eb2e8f9f7 2485 tmpccer &= ~TIM_CCER_CC5P;
<> 144:ef7eb2e8f9f7 2486 /* Set the Output Compare Polarity */
<> 144:ef7eb2e8f9f7 2487 tmpccer |= (OC_Config->OCPolarity << 16);
<> 144:ef7eb2e8f9f7 2488
<> 144:ef7eb2e8f9f7 2489 if(IS_TIM_BREAK_INSTANCE(TIMx))
<> 144:ef7eb2e8f9f7 2490 {
<> 144:ef7eb2e8f9f7 2491 /* Reset the Output Compare IDLE State */
<> 144:ef7eb2e8f9f7 2492 tmpcr2 &= ~TIM_CR2_OIS5;
<> 144:ef7eb2e8f9f7 2493 /* Set the Output Idle state */
<> 144:ef7eb2e8f9f7 2494 tmpcr2 |= (OC_Config->OCIdleState << 8);
<> 144:ef7eb2e8f9f7 2495 }
<> 144:ef7eb2e8f9f7 2496 /* Write to TIMx CR2 */
<> 144:ef7eb2e8f9f7 2497 TIMx->CR2 = tmpcr2;
<> 144:ef7eb2e8f9f7 2498
<> 144:ef7eb2e8f9f7 2499 /* Write to TIMx CCMR3 */
<> 144:ef7eb2e8f9f7 2500 TIMx->CCMR3 = tmpccmrx;
<> 144:ef7eb2e8f9f7 2501
<> 144:ef7eb2e8f9f7 2502 /* Set the Capture Compare Register value */
<> 144:ef7eb2e8f9f7 2503 TIMx->CCR5 = OC_Config->Pulse;
<> 144:ef7eb2e8f9f7 2504
<> 144:ef7eb2e8f9f7 2505 /* Write to TIMx CCER */
<> 144:ef7eb2e8f9f7 2506 TIMx->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 2507 }
<> 144:ef7eb2e8f9f7 2508
<> 144:ef7eb2e8f9f7 2509 /**
<> 144:ef7eb2e8f9f7 2510 * @brief Timer Output Compare 6 configuration
<> 144:ef7eb2e8f9f7 2511 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 2512 * @param OC_Config: The output configuration structure
<> 144:ef7eb2e8f9f7 2513 * @retval None
<> 144:ef7eb2e8f9f7 2514 */
<> 144:ef7eb2e8f9f7 2515 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
<> 144:ef7eb2e8f9f7 2516 {
<> 144:ef7eb2e8f9f7 2517 uint32_t tmpccmrx = 0;
<> 144:ef7eb2e8f9f7 2518 uint32_t tmpccer = 0;
<> 144:ef7eb2e8f9f7 2519 uint32_t tmpcr2 = 0;
<> 144:ef7eb2e8f9f7 2520
<> 144:ef7eb2e8f9f7 2521 /* Disable the output: Reset the CCxE Bit */
<> 144:ef7eb2e8f9f7 2522 TIMx->CCER &= ~TIM_CCER_CC6E;
<> 144:ef7eb2e8f9f7 2523
<> 144:ef7eb2e8f9f7 2524 /* Get the TIMx CCER register value */
<> 144:ef7eb2e8f9f7 2525 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 2526 /* Get the TIMx CR2 register value */
<> 144:ef7eb2e8f9f7 2527 tmpcr2 = TIMx->CR2;
<> 144:ef7eb2e8f9f7 2528 /* Get the TIMx CCMR1 register value */
<> 144:ef7eb2e8f9f7 2529 tmpccmrx = TIMx->CCMR3;
<> 144:ef7eb2e8f9f7 2530
<> 144:ef7eb2e8f9f7 2531 /* Reset the Output Compare Mode Bits */
<> 144:ef7eb2e8f9f7 2532 tmpccmrx &= ~(TIM_CCMR3_OC6M);
<> 144:ef7eb2e8f9f7 2533 /* Select the Output Compare Mode */
<> 144:ef7eb2e8f9f7 2534 tmpccmrx |= (OC_Config->OCMode << 8);
<> 144:ef7eb2e8f9f7 2535
<> 144:ef7eb2e8f9f7 2536 /* Reset the Output Polarity level */
<> 144:ef7eb2e8f9f7 2537 tmpccer &= (uint32_t)~TIM_CCER_CC6P;
<> 144:ef7eb2e8f9f7 2538 /* Set the Output Compare Polarity */
<> 144:ef7eb2e8f9f7 2539 tmpccer |= (OC_Config->OCPolarity << 20);
<> 144:ef7eb2e8f9f7 2540
<> 144:ef7eb2e8f9f7 2541 if(IS_TIM_BREAK_INSTANCE(TIMx))
<> 144:ef7eb2e8f9f7 2542 {
<> 144:ef7eb2e8f9f7 2543 /* Reset the Output Compare IDLE State */
<> 144:ef7eb2e8f9f7 2544 tmpcr2 &= ~TIM_CR2_OIS6;
<> 144:ef7eb2e8f9f7 2545 /* Set the Output Idle state */
<> 144:ef7eb2e8f9f7 2546 tmpcr2 |= (OC_Config->OCIdleState << 10);
<> 144:ef7eb2e8f9f7 2547 }
<> 144:ef7eb2e8f9f7 2548
<> 144:ef7eb2e8f9f7 2549 /* Write to TIMx CR2 */
<> 144:ef7eb2e8f9f7 2550 TIMx->CR2 = tmpcr2;
<> 144:ef7eb2e8f9f7 2551
<> 144:ef7eb2e8f9f7 2552 /* Write to TIMx CCMR3 */
<> 144:ef7eb2e8f9f7 2553 TIMx->CCMR3 = tmpccmrx;
<> 144:ef7eb2e8f9f7 2554
<> 144:ef7eb2e8f9f7 2555 /* Set the Capture Compare Register value */
<> 144:ef7eb2e8f9f7 2556 TIMx->CCR6 = OC_Config->Pulse;
<> 144:ef7eb2e8f9f7 2557
<> 144:ef7eb2e8f9f7 2558 /* Write to TIMx CCER */
<> 144:ef7eb2e8f9f7 2559 TIMx->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 2560 }
<> 144:ef7eb2e8f9f7 2561
<> 144:ef7eb2e8f9f7 2562 /**
<> 144:ef7eb2e8f9f7 2563 * @}
<> 144:ef7eb2e8f9f7 2564 */
<> 144:ef7eb2e8f9f7 2565
<> 144:ef7eb2e8f9f7 2566 #endif /* HAL_TIM_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 2567 /**
<> 144:ef7eb2e8f9f7 2568 * @}
<> 144:ef7eb2e8f9f7 2569 */
<> 144:ef7eb2e8f9f7 2570
<> 144:ef7eb2e8f9f7 2571 /**
<> 144:ef7eb2e8f9f7 2572 * @}
<> 144:ef7eb2e8f9f7 2573 */
<> 144:ef7eb2e8f9f7 2574 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/