Fawwaz Nadzmy / mbed-STM

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

Fork of mbed-dev by mbed official

targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/device/efm32lg_usart.h@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_usart.h@144:ef7eb2e8f9f7 
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 2 * @file efm32lg_usart.h
<> 144:ef7eb2e8f9f7 3 * @brief EFM32LG_USART register and bit field definitions
<> 144:ef7eb2e8f9f7 4 * @version 4.2.0
<> 144:ef7eb2e8f9f7 5 ******************************************************************************
<> 144:ef7eb2e8f9f7 6 * @section License
<> 144:ef7eb2e8f9f7 7 * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Permission is granted to anyone to use this software for any purpose,
<> 144:ef7eb2e8f9f7 11 * including commercial applications, and to alter it and redistribute it
<> 144:ef7eb2e8f9f7 12 * freely, subject to the following restrictions:
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * 1. The origin of this software must not be misrepresented; you must not
<> 144:ef7eb2e8f9f7 15 * claim that you wrote the original software.@n
<> 144:ef7eb2e8f9f7 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 144:ef7eb2e8f9f7 17 * misrepresented as being the original software.@n
<> 144:ef7eb2e8f9f7 18 * 3. This notice may not be removed or altered from any source distribution.
<> 144:ef7eb2e8f9f7 19 *
<> 144:ef7eb2e8f9f7 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 144:ef7eb2e8f9f7 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 144:ef7eb2e8f9f7 22 * providing the Software "AS IS", with no express or implied warranties of any
<> 144:ef7eb2e8f9f7 23 * kind, including, but not limited to, any implied warranties of
<> 144:ef7eb2e8f9f7 24 * merchantability or fitness for any particular purpose or warranties against
<> 144:ef7eb2e8f9f7 25 * infringement of any proprietary rights of a third party.
<> 144:ef7eb2e8f9f7 26 *
<> 144:ef7eb2e8f9f7 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 144:ef7eb2e8f9f7 28 * incidental, or special damages, or any other relief, or for any claim by
<> 144:ef7eb2e8f9f7 29 * any third party, arising from your use of this Software.
<> 144:ef7eb2e8f9f7 30 *
<> 144:ef7eb2e8f9f7 31 *****************************************************************************/
<> 144:ef7eb2e8f9f7 32 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 33 * @addtogroup Parts
<> 144:ef7eb2e8f9f7 34 * @{
<> 144:ef7eb2e8f9f7 35 ******************************************************************************/
<> 144:ef7eb2e8f9f7 36 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 37 * @defgroup EFM32LG_USART
<> 144:ef7eb2e8f9f7 38 * @{
<> 144:ef7eb2e8f9f7 39 * @brief EFM32LG_USART Register Declaration
<> 144:ef7eb2e8f9f7 40 *****************************************************************************/
<> 144:ef7eb2e8f9f7 41 typedef struct
<> 144:ef7eb2e8f9f7 42 {
<> 144:ef7eb2e8f9f7 43 __IO uint32_t CTRL; /**< Control Register */
<> 144:ef7eb2e8f9f7 44 __IO uint32_t FRAME; /**< USART Frame Format Register */
<> 144:ef7eb2e8f9f7 45 __IO uint32_t TRIGCTRL; /**< USART Trigger Control register */
<> 144:ef7eb2e8f9f7 46 __IO uint32_t CMD; /**< Command Register */
<> 144:ef7eb2e8f9f7 47 __I uint32_t STATUS; /**< USART Status Register */
<> 144:ef7eb2e8f9f7 48 __IO uint32_t CLKDIV; /**< Clock Control Register */
<> 144:ef7eb2e8f9f7 49 __I uint32_t RXDATAX; /**< RX Buffer Data Extended Register */
<> 144:ef7eb2e8f9f7 50 __I uint32_t RXDATA; /**< RX Buffer Data Register */
<> 144:ef7eb2e8f9f7 51 __I uint32_t RXDOUBLEX; /**< RX Buffer Double Data Extended Register */
<> 144:ef7eb2e8f9f7 52 __I uint32_t RXDOUBLE; /**< RX FIFO Double Data Register */
<> 144:ef7eb2e8f9f7 53 __I uint32_t RXDATAXP; /**< RX Buffer Data Extended Peek Register */
<> 144:ef7eb2e8f9f7 54 __I uint32_t RXDOUBLEXP; /**< RX Buffer Double Data Extended Peek Register */
<> 144:ef7eb2e8f9f7 55 __IO uint32_t TXDATAX; /**< TX Buffer Data Extended Register */
<> 144:ef7eb2e8f9f7 56 __IO uint32_t TXDATA; /**< TX Buffer Data Register */
<> 144:ef7eb2e8f9f7 57 __IO uint32_t TXDOUBLEX; /**< TX Buffer Double Data Extended Register */
<> 144:ef7eb2e8f9f7 58 __IO uint32_t TXDOUBLE; /**< TX Buffer Double Data Register */
<> 144:ef7eb2e8f9f7 59 __I uint32_t IF; /**< Interrupt Flag Register */
<> 144:ef7eb2e8f9f7 60 __IO uint32_t IFS; /**< Interrupt Flag Set Register */
<> 144:ef7eb2e8f9f7 61 __IO uint32_t IFC; /**< Interrupt Flag Clear Register */
<> 144:ef7eb2e8f9f7 62 __IO uint32_t IEN; /**< Interrupt Enable Register */
<> 144:ef7eb2e8f9f7 63 __IO uint32_t IRCTRL; /**< IrDA Control Register */
<> 144:ef7eb2e8f9f7 64 __IO uint32_t ROUTE; /**< I/O Routing Register */
<> 144:ef7eb2e8f9f7 65 __IO uint32_t INPUT; /**< USART Input Register */
<> 144:ef7eb2e8f9f7 66 __IO uint32_t I2SCTRL; /**< I2S Control Register */
<> 144:ef7eb2e8f9f7 67 } USART_TypeDef; /** @} */
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 70 * @defgroup EFM32LG_USART_BitFields
<> 144:ef7eb2e8f9f7 71 * @{
<> 144:ef7eb2e8f9f7 72 *****************************************************************************/
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 /* Bit fields for USART CTRL */
<> 144:ef7eb2e8f9f7 75 #define _USART_CTRL_RESETVALUE 0x00000000UL /**< Default value for USART_CTRL */
<> 144:ef7eb2e8f9f7 76 #define _USART_CTRL_MASK 0xFFFFFF7FUL /**< Mask for USART_CTRL */
<> 144:ef7eb2e8f9f7 77 #define USART_CTRL_SYNC (0x1UL << 0) /**< USART Synchronous Mode */
<> 144:ef7eb2e8f9f7 78 #define _USART_CTRL_SYNC_SHIFT 0 /**< Shift value for USART_SYNC */
<> 144:ef7eb2e8f9f7 79 #define _USART_CTRL_SYNC_MASK 0x1UL /**< Bit mask for USART_SYNC */
<> 144:ef7eb2e8f9f7 80 #define _USART_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 81 #define USART_CTRL_SYNC_DEFAULT (_USART_CTRL_SYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 82 #define USART_CTRL_LOOPBK (0x1UL << 1) /**< Loopback Enable */
<> 144:ef7eb2e8f9f7 83 #define _USART_CTRL_LOOPBK_SHIFT 1 /**< Shift value for USART_LOOPBK */
<> 144:ef7eb2e8f9f7 84 #define _USART_CTRL_LOOPBK_MASK 0x2UL /**< Bit mask for USART_LOOPBK */
<> 144:ef7eb2e8f9f7 85 #define _USART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 86 #define USART_CTRL_LOOPBK_DEFAULT (_USART_CTRL_LOOPBK_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 87 #define USART_CTRL_CCEN (0x1UL << 2) /**< Collision Check Enable */
<> 144:ef7eb2e8f9f7 88 #define _USART_CTRL_CCEN_SHIFT 2 /**< Shift value for USART_CCEN */
<> 144:ef7eb2e8f9f7 89 #define _USART_CTRL_CCEN_MASK 0x4UL /**< Bit mask for USART_CCEN */
<> 144:ef7eb2e8f9f7 90 #define _USART_CTRL_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 91 #define USART_CTRL_CCEN_DEFAULT (_USART_CTRL_CCEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 92 #define USART_CTRL_MPM (0x1UL << 3) /**< Multi-Processor Mode */
<> 144:ef7eb2e8f9f7 93 #define _USART_CTRL_MPM_SHIFT 3 /**< Shift value for USART_MPM */
<> 144:ef7eb2e8f9f7 94 #define _USART_CTRL_MPM_MASK 0x8UL /**< Bit mask for USART_MPM */
<> 144:ef7eb2e8f9f7 95 #define _USART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 96 #define USART_CTRL_MPM_DEFAULT (_USART_CTRL_MPM_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 97 #define USART_CTRL_MPAB (0x1UL << 4) /**< Multi-Processor Address-Bit */
<> 144:ef7eb2e8f9f7 98 #define _USART_CTRL_MPAB_SHIFT 4 /**< Shift value for USART_MPAB */
<> 144:ef7eb2e8f9f7 99 #define _USART_CTRL_MPAB_MASK 0x10UL /**< Bit mask for USART_MPAB */
<> 144:ef7eb2e8f9f7 100 #define _USART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 101 #define USART_CTRL_MPAB_DEFAULT (_USART_CTRL_MPAB_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 102 #define _USART_CTRL_OVS_SHIFT 5 /**< Shift value for USART_OVS */
<> 144:ef7eb2e8f9f7 103 #define _USART_CTRL_OVS_MASK 0x60UL /**< Bit mask for USART_OVS */
<> 144:ef7eb2e8f9f7 104 #define _USART_CTRL_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 105 #define _USART_CTRL_OVS_X16 0x00000000UL /**< Mode X16 for USART_CTRL */
<> 144:ef7eb2e8f9f7 106 #define _USART_CTRL_OVS_X8 0x00000001UL /**< Mode X8 for USART_CTRL */
<> 144:ef7eb2e8f9f7 107 #define _USART_CTRL_OVS_X6 0x00000002UL /**< Mode X6 for USART_CTRL */
<> 144:ef7eb2e8f9f7 108 #define _USART_CTRL_OVS_X4 0x00000003UL /**< Mode X4 for USART_CTRL */
<> 144:ef7eb2e8f9f7 109 #define USART_CTRL_OVS_DEFAULT (_USART_CTRL_OVS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 110 #define USART_CTRL_OVS_X16 (_USART_CTRL_OVS_X16 << 5) /**< Shifted mode X16 for USART_CTRL */
<> 144:ef7eb2e8f9f7 111 #define USART_CTRL_OVS_X8 (_USART_CTRL_OVS_X8 << 5) /**< Shifted mode X8 for USART_CTRL */
<> 144:ef7eb2e8f9f7 112 #define USART_CTRL_OVS_X6 (_USART_CTRL_OVS_X6 << 5) /**< Shifted mode X6 for USART_CTRL */
<> 144:ef7eb2e8f9f7 113 #define USART_CTRL_OVS_X4 (_USART_CTRL_OVS_X4 << 5) /**< Shifted mode X4 for USART_CTRL */
<> 144:ef7eb2e8f9f7 114 #define USART_CTRL_CLKPOL (0x1UL << 8) /**< Clock Polarity */
<> 144:ef7eb2e8f9f7 115 #define _USART_CTRL_CLKPOL_SHIFT 8 /**< Shift value for USART_CLKPOL */
<> 144:ef7eb2e8f9f7 116 #define _USART_CTRL_CLKPOL_MASK 0x100UL /**< Bit mask for USART_CLKPOL */
<> 144:ef7eb2e8f9f7 117 #define _USART_CTRL_CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 118 #define _USART_CTRL_CLKPOL_IDLELOW 0x00000000UL /**< Mode IDLELOW for USART_CTRL */
<> 144:ef7eb2e8f9f7 119 #define _USART_CTRL_CLKPOL_IDLEHIGH 0x00000001UL /**< Mode IDLEHIGH for USART_CTRL */
<> 144:ef7eb2e8f9f7 120 #define USART_CTRL_CLKPOL_DEFAULT (_USART_CTRL_CLKPOL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 121 #define USART_CTRL_CLKPOL_IDLELOW (_USART_CTRL_CLKPOL_IDLELOW << 8) /**< Shifted mode IDLELOW for USART_CTRL */
<> 144:ef7eb2e8f9f7 122 #define USART_CTRL_CLKPOL_IDLEHIGH (_USART_CTRL_CLKPOL_IDLEHIGH << 8) /**< Shifted mode IDLEHIGH for USART_CTRL */
<> 144:ef7eb2e8f9f7 123 #define USART_CTRL_CLKPHA (0x1UL << 9) /**< Clock Edge For Setup/Sample */
<> 144:ef7eb2e8f9f7 124 #define _USART_CTRL_CLKPHA_SHIFT 9 /**< Shift value for USART_CLKPHA */
<> 144:ef7eb2e8f9f7 125 #define _USART_CTRL_CLKPHA_MASK 0x200UL /**< Bit mask for USART_CLKPHA */
<> 144:ef7eb2e8f9f7 126 #define _USART_CTRL_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 127 #define _USART_CTRL_CLKPHA_SAMPLELEADING 0x00000000UL /**< Mode SAMPLELEADING for USART_CTRL */
<> 144:ef7eb2e8f9f7 128 #define _USART_CTRL_CLKPHA_SAMPLETRAILING 0x00000001UL /**< Mode SAMPLETRAILING for USART_CTRL */
<> 144:ef7eb2e8f9f7 129 #define USART_CTRL_CLKPHA_DEFAULT (_USART_CTRL_CLKPHA_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 130 #define USART_CTRL_CLKPHA_SAMPLELEADING (_USART_CTRL_CLKPHA_SAMPLELEADING << 9) /**< Shifted mode SAMPLELEADING for USART_CTRL */
<> 144:ef7eb2e8f9f7 131 #define USART_CTRL_CLKPHA_SAMPLETRAILING (_USART_CTRL_CLKPHA_SAMPLETRAILING << 9) /**< Shifted mode SAMPLETRAILING for USART_CTRL */
<> 144:ef7eb2e8f9f7 132 #define USART_CTRL_MSBF (0x1UL << 10) /**< Most Significant Bit First */
<> 144:ef7eb2e8f9f7 133 #define _USART_CTRL_MSBF_SHIFT 10 /**< Shift value for USART_MSBF */
<> 144:ef7eb2e8f9f7 134 #define _USART_CTRL_MSBF_MASK 0x400UL /**< Bit mask for USART_MSBF */
<> 144:ef7eb2e8f9f7 135 #define _USART_CTRL_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 136 #define USART_CTRL_MSBF_DEFAULT (_USART_CTRL_MSBF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 137 #define USART_CTRL_CSMA (0x1UL << 11) /**< Action On Slave-Select In Master Mode */
<> 144:ef7eb2e8f9f7 138 #define _USART_CTRL_CSMA_SHIFT 11 /**< Shift value for USART_CSMA */
<> 144:ef7eb2e8f9f7 139 #define _USART_CTRL_CSMA_MASK 0x800UL /**< Bit mask for USART_CSMA */
<> 144:ef7eb2e8f9f7 140 #define _USART_CTRL_CSMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 141 #define _USART_CTRL_CSMA_NOACTION 0x00000000UL /**< Mode NOACTION for USART_CTRL */
<> 144:ef7eb2e8f9f7 142 #define _USART_CTRL_CSMA_GOTOSLAVEMODE 0x00000001UL /**< Mode GOTOSLAVEMODE for USART_CTRL */
<> 144:ef7eb2e8f9f7 143 #define USART_CTRL_CSMA_DEFAULT (_USART_CTRL_CSMA_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 144 #define USART_CTRL_CSMA_NOACTION (_USART_CTRL_CSMA_NOACTION << 11) /**< Shifted mode NOACTION for USART_CTRL */
<> 144:ef7eb2e8f9f7 145 #define USART_CTRL_CSMA_GOTOSLAVEMODE (_USART_CTRL_CSMA_GOTOSLAVEMODE << 11) /**< Shifted mode GOTOSLAVEMODE for USART_CTRL */
<> 144:ef7eb2e8f9f7 146 #define USART_CTRL_TXBIL (0x1UL << 12) /**< TX Buffer Interrupt Level */
<> 144:ef7eb2e8f9f7 147 #define _USART_CTRL_TXBIL_SHIFT 12 /**< Shift value for USART_TXBIL */
<> 144:ef7eb2e8f9f7 148 #define _USART_CTRL_TXBIL_MASK 0x1000UL /**< Bit mask for USART_TXBIL */
<> 144:ef7eb2e8f9f7 149 #define _USART_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 150 #define _USART_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for USART_CTRL */
<> 144:ef7eb2e8f9f7 151 #define _USART_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for USART_CTRL */
<> 144:ef7eb2e8f9f7 152 #define USART_CTRL_TXBIL_DEFAULT (_USART_CTRL_TXBIL_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 153 #define USART_CTRL_TXBIL_EMPTY (_USART_CTRL_TXBIL_EMPTY << 12) /**< Shifted mode EMPTY for USART_CTRL */
<> 144:ef7eb2e8f9f7 154 #define USART_CTRL_TXBIL_HALFFULL (_USART_CTRL_TXBIL_HALFFULL << 12) /**< Shifted mode HALFFULL for USART_CTRL */
<> 144:ef7eb2e8f9f7 155 #define USART_CTRL_RXINV (0x1UL << 13) /**< Receiver Input Invert */
<> 144:ef7eb2e8f9f7 156 #define _USART_CTRL_RXINV_SHIFT 13 /**< Shift value for USART_RXINV */
<> 144:ef7eb2e8f9f7 157 #define _USART_CTRL_RXINV_MASK 0x2000UL /**< Bit mask for USART_RXINV */
<> 144:ef7eb2e8f9f7 158 #define _USART_CTRL_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 159 #define USART_CTRL_RXINV_DEFAULT (_USART_CTRL_RXINV_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 160 #define USART_CTRL_TXINV (0x1UL << 14) /**< Transmitter output Invert */
<> 144:ef7eb2e8f9f7 161 #define _USART_CTRL_TXINV_SHIFT 14 /**< Shift value for USART_TXINV */
<> 144:ef7eb2e8f9f7 162 #define _USART_CTRL_TXINV_MASK 0x4000UL /**< Bit mask for USART_TXINV */
<> 144:ef7eb2e8f9f7 163 #define _USART_CTRL_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 164 #define USART_CTRL_TXINV_DEFAULT (_USART_CTRL_TXINV_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 165 #define USART_CTRL_CSINV (0x1UL << 15) /**< Chip Select Invert */
<> 144:ef7eb2e8f9f7 166 #define _USART_CTRL_CSINV_SHIFT 15 /**< Shift value for USART_CSINV */
<> 144:ef7eb2e8f9f7 167 #define _USART_CTRL_CSINV_MASK 0x8000UL /**< Bit mask for USART_CSINV */
<> 144:ef7eb2e8f9f7 168 #define _USART_CTRL_CSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 169 #define USART_CTRL_CSINV_DEFAULT (_USART_CTRL_CSINV_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 170 #define USART_CTRL_AUTOCS (0x1UL << 16) /**< Automatic Chip Select */
<> 144:ef7eb2e8f9f7 171 #define _USART_CTRL_AUTOCS_SHIFT 16 /**< Shift value for USART_AUTOCS */
<> 144:ef7eb2e8f9f7 172 #define _USART_CTRL_AUTOCS_MASK 0x10000UL /**< Bit mask for USART_AUTOCS */
<> 144:ef7eb2e8f9f7 173 #define _USART_CTRL_AUTOCS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 174 #define USART_CTRL_AUTOCS_DEFAULT (_USART_CTRL_AUTOCS_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 175 #define USART_CTRL_AUTOTRI (0x1UL << 17) /**< Automatic TX Tristate */
<> 144:ef7eb2e8f9f7 176 #define _USART_CTRL_AUTOTRI_SHIFT 17 /**< Shift value for USART_AUTOTRI */
<> 144:ef7eb2e8f9f7 177 #define _USART_CTRL_AUTOTRI_MASK 0x20000UL /**< Bit mask for USART_AUTOTRI */
<> 144:ef7eb2e8f9f7 178 #define _USART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 179 #define USART_CTRL_AUTOTRI_DEFAULT (_USART_CTRL_AUTOTRI_DEFAULT << 17) /**< Shifted mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 180 #define USART_CTRL_SCMODE (0x1UL << 18) /**< SmartCard Mode */
<> 144:ef7eb2e8f9f7 181 #define _USART_CTRL_SCMODE_SHIFT 18 /**< Shift value for USART_SCMODE */
<> 144:ef7eb2e8f9f7 182 #define _USART_CTRL_SCMODE_MASK 0x40000UL /**< Bit mask for USART_SCMODE */
<> 144:ef7eb2e8f9f7 183 #define _USART_CTRL_SCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 184 #define USART_CTRL_SCMODE_DEFAULT (_USART_CTRL_SCMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 185 #define USART_CTRL_SCRETRANS (0x1UL << 19) /**< SmartCard Retransmit */
<> 144:ef7eb2e8f9f7 186 #define _USART_CTRL_SCRETRANS_SHIFT 19 /**< Shift value for USART_SCRETRANS */
<> 144:ef7eb2e8f9f7 187 #define _USART_CTRL_SCRETRANS_MASK 0x80000UL /**< Bit mask for USART_SCRETRANS */
<> 144:ef7eb2e8f9f7 188 #define _USART_CTRL_SCRETRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 189 #define USART_CTRL_SCRETRANS_DEFAULT (_USART_CTRL_SCRETRANS_DEFAULT << 19) /**< Shifted mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 190 #define USART_CTRL_SKIPPERRF (0x1UL << 20) /**< Skip Parity Error Frames */
<> 144:ef7eb2e8f9f7 191 #define _USART_CTRL_SKIPPERRF_SHIFT 20 /**< Shift value for USART_SKIPPERRF */
<> 144:ef7eb2e8f9f7 192 #define _USART_CTRL_SKIPPERRF_MASK 0x100000UL /**< Bit mask for USART_SKIPPERRF */
<> 144:ef7eb2e8f9f7 193 #define _USART_CTRL_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 194 #define USART_CTRL_SKIPPERRF_DEFAULT (_USART_CTRL_SKIPPERRF_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 195 #define USART_CTRL_BIT8DV (0x1UL << 21) /**< Bit 8 Default Value */
<> 144:ef7eb2e8f9f7 196 #define _USART_CTRL_BIT8DV_SHIFT 21 /**< Shift value for USART_BIT8DV */
<> 144:ef7eb2e8f9f7 197 #define _USART_CTRL_BIT8DV_MASK 0x200000UL /**< Bit mask for USART_BIT8DV */
<> 144:ef7eb2e8f9f7 198 #define _USART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 199 #define USART_CTRL_BIT8DV_DEFAULT (_USART_CTRL_BIT8DV_DEFAULT << 21) /**< Shifted mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 200 #define USART_CTRL_ERRSDMA (0x1UL << 22) /**< Halt DMA On Error */
<> 144:ef7eb2e8f9f7 201 #define _USART_CTRL_ERRSDMA_SHIFT 22 /**< Shift value for USART_ERRSDMA */
<> 144:ef7eb2e8f9f7 202 #define _USART_CTRL_ERRSDMA_MASK 0x400000UL /**< Bit mask for USART_ERRSDMA */
<> 144:ef7eb2e8f9f7 203 #define _USART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 204 #define USART_CTRL_ERRSDMA_DEFAULT (_USART_CTRL_ERRSDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 205 #define USART_CTRL_ERRSRX (0x1UL << 23) /**< Disable RX On Error */
<> 144:ef7eb2e8f9f7 206 #define _USART_CTRL_ERRSRX_SHIFT 23 /**< Shift value for USART_ERRSRX */
<> 144:ef7eb2e8f9f7 207 #define _USART_CTRL_ERRSRX_MASK 0x800000UL /**< Bit mask for USART_ERRSRX */
<> 144:ef7eb2e8f9f7 208 #define _USART_CTRL_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 209 #define USART_CTRL_ERRSRX_DEFAULT (_USART_CTRL_ERRSRX_DEFAULT << 23) /**< Shifted mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 210 #define USART_CTRL_ERRSTX (0x1UL << 24) /**< Disable TX On Error */
<> 144:ef7eb2e8f9f7 211 #define _USART_CTRL_ERRSTX_SHIFT 24 /**< Shift value for USART_ERRSTX */
<> 144:ef7eb2e8f9f7 212 #define _USART_CTRL_ERRSTX_MASK 0x1000000UL /**< Bit mask for USART_ERRSTX */
<> 144:ef7eb2e8f9f7 213 #define _USART_CTRL_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 214 #define USART_CTRL_ERRSTX_DEFAULT (_USART_CTRL_ERRSTX_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 215 #define USART_CTRL_SSSEARLY (0x1UL << 25) /**< Synchronous Slave Setup Early */
<> 144:ef7eb2e8f9f7 216 #define _USART_CTRL_SSSEARLY_SHIFT 25 /**< Shift value for USART_SSSEARLY */
<> 144:ef7eb2e8f9f7 217 #define _USART_CTRL_SSSEARLY_MASK 0x2000000UL /**< Bit mask for USART_SSSEARLY */
<> 144:ef7eb2e8f9f7 218 #define _USART_CTRL_SSSEARLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 219 #define USART_CTRL_SSSEARLY_DEFAULT (_USART_CTRL_SSSEARLY_DEFAULT << 25) /**< Shifted mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 220 #define _USART_CTRL_TXDELAY_SHIFT 26 /**< Shift value for USART_TXDELAY */
<> 144:ef7eb2e8f9f7 221 #define _USART_CTRL_TXDELAY_MASK 0xC000000UL /**< Bit mask for USART_TXDELAY */
<> 144:ef7eb2e8f9f7 222 #define _USART_CTRL_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 223 #define _USART_CTRL_TXDELAY_NONE 0x00000000UL /**< Mode NONE for USART_CTRL */
<> 144:ef7eb2e8f9f7 224 #define _USART_CTRL_TXDELAY_SINGLE 0x00000001UL /**< Mode SINGLE for USART_CTRL */
<> 144:ef7eb2e8f9f7 225 #define _USART_CTRL_TXDELAY_DOUBLE 0x00000002UL /**< Mode DOUBLE for USART_CTRL */
<> 144:ef7eb2e8f9f7 226 #define _USART_CTRL_TXDELAY_TRIPLE 0x00000003UL /**< Mode TRIPLE for USART_CTRL */
<> 144:ef7eb2e8f9f7 227 #define USART_CTRL_TXDELAY_DEFAULT (_USART_CTRL_TXDELAY_DEFAULT << 26) /**< Shifted mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 228 #define USART_CTRL_TXDELAY_NONE (_USART_CTRL_TXDELAY_NONE << 26) /**< Shifted mode NONE for USART_CTRL */
<> 144:ef7eb2e8f9f7 229 #define USART_CTRL_TXDELAY_SINGLE (_USART_CTRL_TXDELAY_SINGLE << 26) /**< Shifted mode SINGLE for USART_CTRL */
<> 144:ef7eb2e8f9f7 230 #define USART_CTRL_TXDELAY_DOUBLE (_USART_CTRL_TXDELAY_DOUBLE << 26) /**< Shifted mode DOUBLE for USART_CTRL */
<> 144:ef7eb2e8f9f7 231 #define USART_CTRL_TXDELAY_TRIPLE (_USART_CTRL_TXDELAY_TRIPLE << 26) /**< Shifted mode TRIPLE for USART_CTRL */
<> 144:ef7eb2e8f9f7 232 #define USART_CTRL_BYTESWAP (0x1UL << 28) /**< Byteswap In Double Accesses */
<> 144:ef7eb2e8f9f7 233 #define _USART_CTRL_BYTESWAP_SHIFT 28 /**< Shift value for USART_BYTESWAP */
<> 144:ef7eb2e8f9f7 234 #define _USART_CTRL_BYTESWAP_MASK 0x10000000UL /**< Bit mask for USART_BYTESWAP */
<> 144:ef7eb2e8f9f7 235 #define _USART_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 236 #define USART_CTRL_BYTESWAP_DEFAULT (_USART_CTRL_BYTESWAP_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 237 #define USART_CTRL_AUTOTX (0x1UL << 29) /**< Always Transmit When RX Not Full */
<> 144:ef7eb2e8f9f7 238 #define _USART_CTRL_AUTOTX_SHIFT 29 /**< Shift value for USART_AUTOTX */
<> 144:ef7eb2e8f9f7 239 #define _USART_CTRL_AUTOTX_MASK 0x20000000UL /**< Bit mask for USART_AUTOTX */
<> 144:ef7eb2e8f9f7 240 #define _USART_CTRL_AUTOTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 241 #define USART_CTRL_AUTOTX_DEFAULT (_USART_CTRL_AUTOTX_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 242 #define USART_CTRL_MVDIS (0x1UL << 30) /**< Majority Vote Disable */
<> 144:ef7eb2e8f9f7 243 #define _USART_CTRL_MVDIS_SHIFT 30 /**< Shift value for USART_MVDIS */
<> 144:ef7eb2e8f9f7 244 #define _USART_CTRL_MVDIS_MASK 0x40000000UL /**< Bit mask for USART_MVDIS */
<> 144:ef7eb2e8f9f7 245 #define _USART_CTRL_MVDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 246 #define USART_CTRL_MVDIS_DEFAULT (_USART_CTRL_MVDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 247 #define USART_CTRL_SMSDELAY (0x1UL << 31) /**< Synchronous Master Sample Delay */
<> 144:ef7eb2e8f9f7 248 #define _USART_CTRL_SMSDELAY_SHIFT 31 /**< Shift value for USART_SMSDELAY */
<> 144:ef7eb2e8f9f7 249 #define _USART_CTRL_SMSDELAY_MASK 0x80000000UL /**< Bit mask for USART_SMSDELAY */
<> 144:ef7eb2e8f9f7 250 #define _USART_CTRL_SMSDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 251 #define USART_CTRL_SMSDELAY_DEFAULT (_USART_CTRL_SMSDELAY_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CTRL */
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 /* Bit fields for USART FRAME */
<> 144:ef7eb2e8f9f7 254 #define _USART_FRAME_RESETVALUE 0x00001005UL /**< Default value for USART_FRAME */
<> 144:ef7eb2e8f9f7 255 #define _USART_FRAME_MASK 0x0000330FUL /**< Mask for USART_FRAME */
<> 144:ef7eb2e8f9f7 256 #define _USART_FRAME_DATABITS_SHIFT 0 /**< Shift value for USART_DATABITS */
<> 144:ef7eb2e8f9f7 257 #define _USART_FRAME_DATABITS_MASK 0xFUL /**< Bit mask for USART_DATABITS */
<> 144:ef7eb2e8f9f7 258 #define _USART_FRAME_DATABITS_FOUR 0x00000001UL /**< Mode FOUR for USART_FRAME */
<> 144:ef7eb2e8f9f7 259 #define _USART_FRAME_DATABITS_FIVE 0x00000002UL /**< Mode FIVE for USART_FRAME */
<> 144:ef7eb2e8f9f7 260 #define _USART_FRAME_DATABITS_SIX 0x00000003UL /**< Mode SIX for USART_FRAME */
<> 144:ef7eb2e8f9f7 261 #define _USART_FRAME_DATABITS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_FRAME */
<> 144:ef7eb2e8f9f7 262 #define _USART_FRAME_DATABITS_DEFAULT 0x00000005UL /**< Mode DEFAULT for USART_FRAME */
<> 144:ef7eb2e8f9f7 263 #define _USART_FRAME_DATABITS_EIGHT 0x00000005UL /**< Mode EIGHT for USART_FRAME */
<> 144:ef7eb2e8f9f7 264 #define _USART_FRAME_DATABITS_NINE 0x00000006UL /**< Mode NINE for USART_FRAME */
<> 144:ef7eb2e8f9f7 265 #define _USART_FRAME_DATABITS_TEN 0x00000007UL /**< Mode TEN for USART_FRAME */
<> 144:ef7eb2e8f9f7 266 #define _USART_FRAME_DATABITS_ELEVEN 0x00000008UL /**< Mode ELEVEN for USART_FRAME */
<> 144:ef7eb2e8f9f7 267 #define _USART_FRAME_DATABITS_TWELVE 0x00000009UL /**< Mode TWELVE for USART_FRAME */
<> 144:ef7eb2e8f9f7 268 #define _USART_FRAME_DATABITS_THIRTEEN 0x0000000AUL /**< Mode THIRTEEN for USART_FRAME */
<> 144:ef7eb2e8f9f7 269 #define _USART_FRAME_DATABITS_FOURTEEN 0x0000000BUL /**< Mode FOURTEEN for USART_FRAME */
<> 144:ef7eb2e8f9f7 270 #define _USART_FRAME_DATABITS_FIFTEEN 0x0000000CUL /**< Mode FIFTEEN for USART_FRAME */
<> 144:ef7eb2e8f9f7 271 #define _USART_FRAME_DATABITS_SIXTEEN 0x0000000DUL /**< Mode SIXTEEN for USART_FRAME */
<> 144:ef7eb2e8f9f7 272 #define USART_FRAME_DATABITS_FOUR (_USART_FRAME_DATABITS_FOUR << 0) /**< Shifted mode FOUR for USART_FRAME */
<> 144:ef7eb2e8f9f7 273 #define USART_FRAME_DATABITS_FIVE (_USART_FRAME_DATABITS_FIVE << 0) /**< Shifted mode FIVE for USART_FRAME */
<> 144:ef7eb2e8f9f7 274 #define USART_FRAME_DATABITS_SIX (_USART_FRAME_DATABITS_SIX << 0) /**< Shifted mode SIX for USART_FRAME */
<> 144:ef7eb2e8f9f7 275 #define USART_FRAME_DATABITS_SEVEN (_USART_FRAME_DATABITS_SEVEN << 0) /**< Shifted mode SEVEN for USART_FRAME */
<> 144:ef7eb2e8f9f7 276 #define USART_FRAME_DATABITS_DEFAULT (_USART_FRAME_DATABITS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_FRAME */
<> 144:ef7eb2e8f9f7 277 #define USART_FRAME_DATABITS_EIGHT (_USART_FRAME_DATABITS_EIGHT << 0) /**< Shifted mode EIGHT for USART_FRAME */
<> 144:ef7eb2e8f9f7 278 #define USART_FRAME_DATABITS_NINE (_USART_FRAME_DATABITS_NINE << 0) /**< Shifted mode NINE for USART_FRAME */
<> 144:ef7eb2e8f9f7 279 #define USART_FRAME_DATABITS_TEN (_USART_FRAME_DATABITS_TEN << 0) /**< Shifted mode TEN for USART_FRAME */
<> 144:ef7eb2e8f9f7 280 #define USART_FRAME_DATABITS_ELEVEN (_USART_FRAME_DATABITS_ELEVEN << 0) /**< Shifted mode ELEVEN for USART_FRAME */
<> 144:ef7eb2e8f9f7 281 #define USART_FRAME_DATABITS_TWELVE (_USART_FRAME_DATABITS_TWELVE << 0) /**< Shifted mode TWELVE for USART_FRAME */
<> 144:ef7eb2e8f9f7 282 #define USART_FRAME_DATABITS_THIRTEEN (_USART_FRAME_DATABITS_THIRTEEN << 0) /**< Shifted mode THIRTEEN for USART_FRAME */
<> 144:ef7eb2e8f9f7 283 #define USART_FRAME_DATABITS_FOURTEEN (_USART_FRAME_DATABITS_FOURTEEN << 0) /**< Shifted mode FOURTEEN for USART_FRAME */
<> 144:ef7eb2e8f9f7 284 #define USART_FRAME_DATABITS_FIFTEEN (_USART_FRAME_DATABITS_FIFTEEN << 0) /**< Shifted mode FIFTEEN for USART_FRAME */
<> 144:ef7eb2e8f9f7 285 #define USART_FRAME_DATABITS_SIXTEEN (_USART_FRAME_DATABITS_SIXTEEN << 0) /**< Shifted mode SIXTEEN for USART_FRAME */
<> 144:ef7eb2e8f9f7 286 #define _USART_FRAME_PARITY_SHIFT 8 /**< Shift value for USART_PARITY */
<> 144:ef7eb2e8f9f7 287 #define _USART_FRAME_PARITY_MASK 0x300UL /**< Bit mask for USART_PARITY */
<> 144:ef7eb2e8f9f7 288 #define _USART_FRAME_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_FRAME */
<> 144:ef7eb2e8f9f7 289 #define _USART_FRAME_PARITY_NONE 0x00000000UL /**< Mode NONE for USART_FRAME */
<> 144:ef7eb2e8f9f7 290 #define _USART_FRAME_PARITY_EVEN 0x00000002UL /**< Mode EVEN for USART_FRAME */
<> 144:ef7eb2e8f9f7 291 #define _USART_FRAME_PARITY_ODD 0x00000003UL /**< Mode ODD for USART_FRAME */
<> 144:ef7eb2e8f9f7 292 #define USART_FRAME_PARITY_DEFAULT (_USART_FRAME_PARITY_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_FRAME */
<> 144:ef7eb2e8f9f7 293 #define USART_FRAME_PARITY_NONE (_USART_FRAME_PARITY_NONE << 8) /**< Shifted mode NONE for USART_FRAME */
<> 144:ef7eb2e8f9f7 294 #define USART_FRAME_PARITY_EVEN (_USART_FRAME_PARITY_EVEN << 8) /**< Shifted mode EVEN for USART_FRAME */
<> 144:ef7eb2e8f9f7 295 #define USART_FRAME_PARITY_ODD (_USART_FRAME_PARITY_ODD << 8) /**< Shifted mode ODD for USART_FRAME */
<> 144:ef7eb2e8f9f7 296 #define _USART_FRAME_STOPBITS_SHIFT 12 /**< Shift value for USART_STOPBITS */
<> 144:ef7eb2e8f9f7 297 #define _USART_FRAME_STOPBITS_MASK 0x3000UL /**< Bit mask for USART_STOPBITS */
<> 144:ef7eb2e8f9f7 298 #define _USART_FRAME_STOPBITS_HALF 0x00000000UL /**< Mode HALF for USART_FRAME */
<> 144:ef7eb2e8f9f7 299 #define _USART_FRAME_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_FRAME */
<> 144:ef7eb2e8f9f7 300 #define _USART_FRAME_STOPBITS_ONE 0x00000001UL /**< Mode ONE for USART_FRAME */
<> 144:ef7eb2e8f9f7 301 #define _USART_FRAME_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for USART_FRAME */
<> 144:ef7eb2e8f9f7 302 #define _USART_FRAME_STOPBITS_TWO 0x00000003UL /**< Mode TWO for USART_FRAME */
<> 144:ef7eb2e8f9f7 303 #define USART_FRAME_STOPBITS_HALF (_USART_FRAME_STOPBITS_HALF << 12) /**< Shifted mode HALF for USART_FRAME */
<> 144:ef7eb2e8f9f7 304 #define USART_FRAME_STOPBITS_DEFAULT (_USART_FRAME_STOPBITS_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_FRAME */
<> 144:ef7eb2e8f9f7 305 #define USART_FRAME_STOPBITS_ONE (_USART_FRAME_STOPBITS_ONE << 12) /**< Shifted mode ONE for USART_FRAME */
<> 144:ef7eb2e8f9f7 306 #define USART_FRAME_STOPBITS_ONEANDAHALF (_USART_FRAME_STOPBITS_ONEANDAHALF << 12) /**< Shifted mode ONEANDAHALF for USART_FRAME */
<> 144:ef7eb2e8f9f7 307 #define USART_FRAME_STOPBITS_TWO (_USART_FRAME_STOPBITS_TWO << 12) /**< Shifted mode TWO for USART_FRAME */
<> 144:ef7eb2e8f9f7 308
<> 144:ef7eb2e8f9f7 309 /* Bit fields for USART TRIGCTRL */
<> 144:ef7eb2e8f9f7 310 #define _USART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_TRIGCTRL */
<> 144:ef7eb2e8f9f7 311 #define _USART_TRIGCTRL_MASK 0x00000077UL /**< Mask for USART_TRIGCTRL */
<> 144:ef7eb2e8f9f7 312 #define _USART_TRIGCTRL_TSEL_SHIFT 0 /**< Shift value for USART_TSEL */
<> 144:ef7eb2e8f9f7 313 #define _USART_TRIGCTRL_TSEL_MASK 0x7UL /**< Bit mask for USART_TSEL */
<> 144:ef7eb2e8f9f7 314 #define _USART_TRIGCTRL_TSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
<> 144:ef7eb2e8f9f7 315 #define _USART_TRIGCTRL_TSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_TRIGCTRL */
<> 144:ef7eb2e8f9f7 316 #define _USART_TRIGCTRL_TSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_TRIGCTRL */
<> 144:ef7eb2e8f9f7 317 #define _USART_TRIGCTRL_TSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_TRIGCTRL */
<> 144:ef7eb2e8f9f7 318 #define _USART_TRIGCTRL_TSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_TRIGCTRL */
<> 144:ef7eb2e8f9f7 319 #define _USART_TRIGCTRL_TSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_TRIGCTRL */
<> 144:ef7eb2e8f9f7 320 #define _USART_TRIGCTRL_TSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_TRIGCTRL */
<> 144:ef7eb2e8f9f7 321 #define _USART_TRIGCTRL_TSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_TRIGCTRL */
<> 144:ef7eb2e8f9f7 322 #define _USART_TRIGCTRL_TSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_TRIGCTRL */
<> 144:ef7eb2e8f9f7 323 #define USART_TRIGCTRL_TSEL_DEFAULT (_USART_TRIGCTRL_TSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
<> 144:ef7eb2e8f9f7 324 #define USART_TRIGCTRL_TSEL_PRSCH0 (_USART_TRIGCTRL_TSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for USART_TRIGCTRL */
<> 144:ef7eb2e8f9f7 325 #define USART_TRIGCTRL_TSEL_PRSCH1 (_USART_TRIGCTRL_TSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for USART_TRIGCTRL */
<> 144:ef7eb2e8f9f7 326 #define USART_TRIGCTRL_TSEL_PRSCH2 (_USART_TRIGCTRL_TSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for USART_TRIGCTRL */
<> 144:ef7eb2e8f9f7 327 #define USART_TRIGCTRL_TSEL_PRSCH3 (_USART_TRIGCTRL_TSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for USART_TRIGCTRL */
<> 144:ef7eb2e8f9f7 328 #define USART_TRIGCTRL_TSEL_PRSCH4 (_USART_TRIGCTRL_TSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for USART_TRIGCTRL */
<> 144:ef7eb2e8f9f7 329 #define USART_TRIGCTRL_TSEL_PRSCH5 (_USART_TRIGCTRL_TSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for USART_TRIGCTRL */
<> 144:ef7eb2e8f9f7 330 #define USART_TRIGCTRL_TSEL_PRSCH6 (_USART_TRIGCTRL_TSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for USART_TRIGCTRL */
<> 144:ef7eb2e8f9f7 331 #define USART_TRIGCTRL_TSEL_PRSCH7 (_USART_TRIGCTRL_TSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for USART_TRIGCTRL */
<> 144:ef7eb2e8f9f7 332 #define USART_TRIGCTRL_RXTEN (0x1UL << 4) /**< Receive Trigger Enable */
<> 144:ef7eb2e8f9f7 333 #define _USART_TRIGCTRL_RXTEN_SHIFT 4 /**< Shift value for USART_RXTEN */
<> 144:ef7eb2e8f9f7 334 #define _USART_TRIGCTRL_RXTEN_MASK 0x10UL /**< Bit mask for USART_RXTEN */
<> 144:ef7eb2e8f9f7 335 #define _USART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
<> 144:ef7eb2e8f9f7 336 #define USART_TRIGCTRL_RXTEN_DEFAULT (_USART_TRIGCTRL_RXTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
<> 144:ef7eb2e8f9f7 337 #define USART_TRIGCTRL_TXTEN (0x1UL << 5) /**< Transmit Trigger Enable */
<> 144:ef7eb2e8f9f7 338 #define _USART_TRIGCTRL_TXTEN_SHIFT 5 /**< Shift value for USART_TXTEN */
<> 144:ef7eb2e8f9f7 339 #define _USART_TRIGCTRL_TXTEN_MASK 0x20UL /**< Bit mask for USART_TXTEN */
<> 144:ef7eb2e8f9f7 340 #define _USART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
<> 144:ef7eb2e8f9f7 341 #define USART_TRIGCTRL_TXTEN_DEFAULT (_USART_TRIGCTRL_TXTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
<> 144:ef7eb2e8f9f7 342 #define USART_TRIGCTRL_AUTOTXTEN (0x1UL << 6) /**< AUTOTX Trigger Enable */
<> 144:ef7eb2e8f9f7 343 #define _USART_TRIGCTRL_AUTOTXTEN_SHIFT 6 /**< Shift value for USART_AUTOTXTEN */
<> 144:ef7eb2e8f9f7 344 #define _USART_TRIGCTRL_AUTOTXTEN_MASK 0x40UL /**< Bit mask for USART_AUTOTXTEN */
<> 144:ef7eb2e8f9f7 345 #define _USART_TRIGCTRL_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
<> 144:ef7eb2e8f9f7 346 #define USART_TRIGCTRL_AUTOTXTEN_DEFAULT (_USART_TRIGCTRL_AUTOTXTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
<> 144:ef7eb2e8f9f7 347
<> 144:ef7eb2e8f9f7 348 /* Bit fields for USART CMD */
<> 144:ef7eb2e8f9f7 349 #define _USART_CMD_RESETVALUE 0x00000000UL /**< Default value for USART_CMD */
<> 144:ef7eb2e8f9f7 350 #define _USART_CMD_MASK 0x00000FFFUL /**< Mask for USART_CMD */
<> 144:ef7eb2e8f9f7 351 #define USART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */
<> 144:ef7eb2e8f9f7 352 #define _USART_CMD_RXEN_SHIFT 0 /**< Shift value for USART_RXEN */
<> 144:ef7eb2e8f9f7 353 #define _USART_CMD_RXEN_MASK 0x1UL /**< Bit mask for USART_RXEN */
<> 144:ef7eb2e8f9f7 354 #define _USART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
<> 144:ef7eb2e8f9f7 355 #define USART_CMD_RXEN_DEFAULT (_USART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CMD */
<> 144:ef7eb2e8f9f7 356 #define USART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */
<> 144:ef7eb2e8f9f7 357 #define _USART_CMD_RXDIS_SHIFT 1 /**< Shift value for USART_RXDIS */
<> 144:ef7eb2e8f9f7 358 #define _USART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for USART_RXDIS */
<> 144:ef7eb2e8f9f7 359 #define _USART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
<> 144:ef7eb2e8f9f7 360 #define USART_CMD_RXDIS_DEFAULT (_USART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CMD */
<> 144:ef7eb2e8f9f7 361 #define USART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */
<> 144:ef7eb2e8f9f7 362 #define _USART_CMD_TXEN_SHIFT 2 /**< Shift value for USART_TXEN */
<> 144:ef7eb2e8f9f7 363 #define _USART_CMD_TXEN_MASK 0x4UL /**< Bit mask for USART_TXEN */
<> 144:ef7eb2e8f9f7 364 #define _USART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
<> 144:ef7eb2e8f9f7 365 #define USART_CMD_TXEN_DEFAULT (_USART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CMD */
<> 144:ef7eb2e8f9f7 366 #define USART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */
<> 144:ef7eb2e8f9f7 367 #define _USART_CMD_TXDIS_SHIFT 3 /**< Shift value for USART_TXDIS */
<> 144:ef7eb2e8f9f7 368 #define _USART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for USART_TXDIS */
<> 144:ef7eb2e8f9f7 369 #define _USART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
<> 144:ef7eb2e8f9f7 370 #define USART_CMD_TXDIS_DEFAULT (_USART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CMD */
<> 144:ef7eb2e8f9f7 371 #define USART_CMD_MASTEREN (0x1UL << 4) /**< Master Enable */
<> 144:ef7eb2e8f9f7 372 #define _USART_CMD_MASTEREN_SHIFT 4 /**< Shift value for USART_MASTEREN */
<> 144:ef7eb2e8f9f7 373 #define _USART_CMD_MASTEREN_MASK 0x10UL /**< Bit mask for USART_MASTEREN */
<> 144:ef7eb2e8f9f7 374 #define _USART_CMD_MASTEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
<> 144:ef7eb2e8f9f7 375 #define USART_CMD_MASTEREN_DEFAULT (_USART_CMD_MASTEREN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CMD */
<> 144:ef7eb2e8f9f7 376 #define USART_CMD_MASTERDIS (0x1UL << 5) /**< Master Disable */
<> 144:ef7eb2e8f9f7 377 #define _USART_CMD_MASTERDIS_SHIFT 5 /**< Shift value for USART_MASTERDIS */
<> 144:ef7eb2e8f9f7 378 #define _USART_CMD_MASTERDIS_MASK 0x20UL /**< Bit mask for USART_MASTERDIS */
<> 144:ef7eb2e8f9f7 379 #define _USART_CMD_MASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
<> 144:ef7eb2e8f9f7 380 #define USART_CMD_MASTERDIS_DEFAULT (_USART_CMD_MASTERDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CMD */
<> 144:ef7eb2e8f9f7 381 #define USART_CMD_RXBLOCKEN (0x1UL << 6) /**< Receiver Block Enable */
<> 144:ef7eb2e8f9f7 382 #define _USART_CMD_RXBLOCKEN_SHIFT 6 /**< Shift value for USART_RXBLOCKEN */
<> 144:ef7eb2e8f9f7 383 #define _USART_CMD_RXBLOCKEN_MASK 0x40UL /**< Bit mask for USART_RXBLOCKEN */
<> 144:ef7eb2e8f9f7 384 #define _USART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
<> 144:ef7eb2e8f9f7 385 #define USART_CMD_RXBLOCKEN_DEFAULT (_USART_CMD_RXBLOCKEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_CMD */
<> 144:ef7eb2e8f9f7 386 #define USART_CMD_RXBLOCKDIS (0x1UL << 7) /**< Receiver Block Disable */
<> 144:ef7eb2e8f9f7 387 #define _USART_CMD_RXBLOCKDIS_SHIFT 7 /**< Shift value for USART_RXBLOCKDIS */
<> 144:ef7eb2e8f9f7 388 #define _USART_CMD_RXBLOCKDIS_MASK 0x80UL /**< Bit mask for USART_RXBLOCKDIS */
<> 144:ef7eb2e8f9f7 389 #define _USART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
<> 144:ef7eb2e8f9f7 390 #define USART_CMD_RXBLOCKDIS_DEFAULT (_USART_CMD_RXBLOCKDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_CMD */
<> 144:ef7eb2e8f9f7 391 #define USART_CMD_TXTRIEN (0x1UL << 8) /**< Transmitter Tristate Enable */
<> 144:ef7eb2e8f9f7 392 #define _USART_CMD_TXTRIEN_SHIFT 8 /**< Shift value for USART_TXTRIEN */
<> 144:ef7eb2e8f9f7 393 #define _USART_CMD_TXTRIEN_MASK 0x100UL /**< Bit mask for USART_TXTRIEN */
<> 144:ef7eb2e8f9f7 394 #define _USART_CMD_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
<> 144:ef7eb2e8f9f7 395 #define USART_CMD_TXTRIEN_DEFAULT (_USART_CMD_TXTRIEN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CMD */
<> 144:ef7eb2e8f9f7 396 #define USART_CMD_TXTRIDIS (0x1UL << 9) /**< Transmitter Tristate Disable */
<> 144:ef7eb2e8f9f7 397 #define _USART_CMD_TXTRIDIS_SHIFT 9 /**< Shift value for USART_TXTRIDIS */
<> 144:ef7eb2e8f9f7 398 #define _USART_CMD_TXTRIDIS_MASK 0x200UL /**< Bit mask for USART_TXTRIDIS */
<> 144:ef7eb2e8f9f7 399 #define _USART_CMD_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
<> 144:ef7eb2e8f9f7 400 #define USART_CMD_TXTRIDIS_DEFAULT (_USART_CMD_TXTRIDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CMD */
<> 144:ef7eb2e8f9f7 401 #define USART_CMD_CLEARTX (0x1UL << 10) /**< Clear TX */
<> 144:ef7eb2e8f9f7 402 #define _USART_CMD_CLEARTX_SHIFT 10 /**< Shift value for USART_CLEARTX */
<> 144:ef7eb2e8f9f7 403 #define _USART_CMD_CLEARTX_MASK 0x400UL /**< Bit mask for USART_CLEARTX */
<> 144:ef7eb2e8f9f7 404 #define _USART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
<> 144:ef7eb2e8f9f7 405 #define USART_CMD_CLEARTX_DEFAULT (_USART_CMD_CLEARTX_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CMD */
<> 144:ef7eb2e8f9f7 406 #define USART_CMD_CLEARRX (0x1UL << 11) /**< Clear RX */
<> 144:ef7eb2e8f9f7 407 #define _USART_CMD_CLEARRX_SHIFT 11 /**< Shift value for USART_CLEARRX */
<> 144:ef7eb2e8f9f7 408 #define _USART_CMD_CLEARRX_MASK 0x800UL /**< Bit mask for USART_CLEARRX */
<> 144:ef7eb2e8f9f7 409 #define _USART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
<> 144:ef7eb2e8f9f7 410 #define USART_CMD_CLEARRX_DEFAULT (_USART_CMD_CLEARRX_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CMD */
<> 144:ef7eb2e8f9f7 411
<> 144:ef7eb2e8f9f7 412 /* Bit fields for USART STATUS */
<> 144:ef7eb2e8f9f7 413 #define _USART_STATUS_RESETVALUE 0x00000040UL /**< Default value for USART_STATUS */
<> 144:ef7eb2e8f9f7 414 #define _USART_STATUS_MASK 0x00001FFFUL /**< Mask for USART_STATUS */
<> 144:ef7eb2e8f9f7 415 #define USART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */
<> 144:ef7eb2e8f9f7 416 #define _USART_STATUS_RXENS_SHIFT 0 /**< Shift value for USART_RXENS */
<> 144:ef7eb2e8f9f7 417 #define _USART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for USART_RXENS */
<> 144:ef7eb2e8f9f7 418 #define _USART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
<> 144:ef7eb2e8f9f7 419 #define USART_STATUS_RXENS_DEFAULT (_USART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_STATUS */
<> 144:ef7eb2e8f9f7 420 #define USART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */
<> 144:ef7eb2e8f9f7 421 #define _USART_STATUS_TXENS_SHIFT 1 /**< Shift value for USART_TXENS */
<> 144:ef7eb2e8f9f7 422 #define _USART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for USART_TXENS */
<> 144:ef7eb2e8f9f7 423 #define _USART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
<> 144:ef7eb2e8f9f7 424 #define USART_STATUS_TXENS_DEFAULT (_USART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_STATUS */
<> 144:ef7eb2e8f9f7 425 #define USART_STATUS_MASTER (0x1UL << 2) /**< SPI Master Mode */
<> 144:ef7eb2e8f9f7 426 #define _USART_STATUS_MASTER_SHIFT 2 /**< Shift value for USART_MASTER */
<> 144:ef7eb2e8f9f7 427 #define _USART_STATUS_MASTER_MASK 0x4UL /**< Bit mask for USART_MASTER */
<> 144:ef7eb2e8f9f7 428 #define _USART_STATUS_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
<> 144:ef7eb2e8f9f7 429 #define USART_STATUS_MASTER_DEFAULT (_USART_STATUS_MASTER_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_STATUS */
<> 144:ef7eb2e8f9f7 430 #define USART_STATUS_RXBLOCK (0x1UL << 3) /**< Block Incoming Data */
<> 144:ef7eb2e8f9f7 431 #define _USART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for USART_RXBLOCK */
<> 144:ef7eb2e8f9f7 432 #define _USART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for USART_RXBLOCK */
<> 144:ef7eb2e8f9f7 433 #define _USART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
<> 144:ef7eb2e8f9f7 434 #define USART_STATUS_RXBLOCK_DEFAULT (_USART_STATUS_RXBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_STATUS */
<> 144:ef7eb2e8f9f7 435 #define USART_STATUS_TXTRI (0x1UL << 4) /**< Transmitter Tristated */
<> 144:ef7eb2e8f9f7 436 #define _USART_STATUS_TXTRI_SHIFT 4 /**< Shift value for USART_TXTRI */
<> 144:ef7eb2e8f9f7 437 #define _USART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for USART_TXTRI */
<> 144:ef7eb2e8f9f7 438 #define _USART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
<> 144:ef7eb2e8f9f7 439 #define USART_STATUS_TXTRI_DEFAULT (_USART_STATUS_TXTRI_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_STATUS */
<> 144:ef7eb2e8f9f7 440 #define USART_STATUS_TXC (0x1UL << 5) /**< TX Complete */
<> 144:ef7eb2e8f9f7 441 #define _USART_STATUS_TXC_SHIFT 5 /**< Shift value for USART_TXC */
<> 144:ef7eb2e8f9f7 442 #define _USART_STATUS_TXC_MASK 0x20UL /**< Bit mask for USART_TXC */
<> 144:ef7eb2e8f9f7 443 #define _USART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
<> 144:ef7eb2e8f9f7 444 #define USART_STATUS_TXC_DEFAULT (_USART_STATUS_TXC_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_STATUS */
<> 144:ef7eb2e8f9f7 445 #define USART_STATUS_TXBL (0x1UL << 6) /**< TX Buffer Level */
<> 144:ef7eb2e8f9f7 446 #define _USART_STATUS_TXBL_SHIFT 6 /**< Shift value for USART_TXBL */
<> 144:ef7eb2e8f9f7 447 #define _USART_STATUS_TXBL_MASK 0x40UL /**< Bit mask for USART_TXBL */
<> 144:ef7eb2e8f9f7 448 #define _USART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */
<> 144:ef7eb2e8f9f7 449 #define USART_STATUS_TXBL_DEFAULT (_USART_STATUS_TXBL_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_STATUS */
<> 144:ef7eb2e8f9f7 450 #define USART_STATUS_RXDATAV (0x1UL << 7) /**< RX Data Valid */
<> 144:ef7eb2e8f9f7 451 #define _USART_STATUS_RXDATAV_SHIFT 7 /**< Shift value for USART_RXDATAV */
<> 144:ef7eb2e8f9f7 452 #define _USART_STATUS_RXDATAV_MASK 0x80UL /**< Bit mask for USART_RXDATAV */
<> 144:ef7eb2e8f9f7 453 #define _USART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
<> 144:ef7eb2e8f9f7 454 #define USART_STATUS_RXDATAV_DEFAULT (_USART_STATUS_RXDATAV_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_STATUS */
<> 144:ef7eb2e8f9f7 455 #define USART_STATUS_RXFULL (0x1UL << 8) /**< RX FIFO Full */
<> 144:ef7eb2e8f9f7 456 #define _USART_STATUS_RXFULL_SHIFT 8 /**< Shift value for USART_RXFULL */
<> 144:ef7eb2e8f9f7 457 #define _USART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for USART_RXFULL */
<> 144:ef7eb2e8f9f7 458 #define _USART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
<> 144:ef7eb2e8f9f7 459 #define USART_STATUS_RXFULL_DEFAULT (_USART_STATUS_RXFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_STATUS */
<> 144:ef7eb2e8f9f7 460 #define USART_STATUS_TXBDRIGHT (0x1UL << 9) /**< TX Buffer Expects Double Right Data */
<> 144:ef7eb2e8f9f7 461 #define _USART_STATUS_TXBDRIGHT_SHIFT 9 /**< Shift value for USART_TXBDRIGHT */
<> 144:ef7eb2e8f9f7 462 #define _USART_STATUS_TXBDRIGHT_MASK 0x200UL /**< Bit mask for USART_TXBDRIGHT */
<> 144:ef7eb2e8f9f7 463 #define _USART_STATUS_TXBDRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
<> 144:ef7eb2e8f9f7 464 #define USART_STATUS_TXBDRIGHT_DEFAULT (_USART_STATUS_TXBDRIGHT_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_STATUS */
<> 144:ef7eb2e8f9f7 465 #define USART_STATUS_TXBSRIGHT (0x1UL << 10) /**< TX Buffer Expects Single Right Data */
<> 144:ef7eb2e8f9f7 466 #define _USART_STATUS_TXBSRIGHT_SHIFT 10 /**< Shift value for USART_TXBSRIGHT */
<> 144:ef7eb2e8f9f7 467 #define _USART_STATUS_TXBSRIGHT_MASK 0x400UL /**< Bit mask for USART_TXBSRIGHT */
<> 144:ef7eb2e8f9f7 468 #define _USART_STATUS_TXBSRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
<> 144:ef7eb2e8f9f7 469 #define USART_STATUS_TXBSRIGHT_DEFAULT (_USART_STATUS_TXBSRIGHT_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_STATUS */
<> 144:ef7eb2e8f9f7 470 #define USART_STATUS_RXDATAVRIGHT (0x1UL << 11) /**< RX Data Right */
<> 144:ef7eb2e8f9f7 471 #define _USART_STATUS_RXDATAVRIGHT_SHIFT 11 /**< Shift value for USART_RXDATAVRIGHT */
<> 144:ef7eb2e8f9f7 472 #define _USART_STATUS_RXDATAVRIGHT_MASK 0x800UL /**< Bit mask for USART_RXDATAVRIGHT */
<> 144:ef7eb2e8f9f7 473 #define _USART_STATUS_RXDATAVRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
<> 144:ef7eb2e8f9f7 474 #define USART_STATUS_RXDATAVRIGHT_DEFAULT (_USART_STATUS_RXDATAVRIGHT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_STATUS */
<> 144:ef7eb2e8f9f7 475 #define USART_STATUS_RXFULLRIGHT (0x1UL << 12) /**< RX Full of Right Data */
<> 144:ef7eb2e8f9f7 476 #define _USART_STATUS_RXFULLRIGHT_SHIFT 12 /**< Shift value for USART_RXFULLRIGHT */
<> 144:ef7eb2e8f9f7 477 #define _USART_STATUS_RXFULLRIGHT_MASK 0x1000UL /**< Bit mask for USART_RXFULLRIGHT */
<> 144:ef7eb2e8f9f7 478 #define _USART_STATUS_RXFULLRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
<> 144:ef7eb2e8f9f7 479 #define USART_STATUS_RXFULLRIGHT_DEFAULT (_USART_STATUS_RXFULLRIGHT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_STATUS */
<> 144:ef7eb2e8f9f7 480
<> 144:ef7eb2e8f9f7 481 /* Bit fields for USART CLKDIV */
<> 144:ef7eb2e8f9f7 482 #define _USART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for USART_CLKDIV */
<> 144:ef7eb2e8f9f7 483 #define _USART_CLKDIV_MASK 0x001FFFC0UL /**< Mask for USART_CLKDIV */
<> 144:ef7eb2e8f9f7 484 #define _USART_CLKDIV_DIV_SHIFT 6 /**< Shift value for USART_DIV */
<> 144:ef7eb2e8f9f7 485 #define _USART_CLKDIV_DIV_MASK 0x1FFFC0UL /**< Bit mask for USART_DIV */
<> 144:ef7eb2e8f9f7 486 #define _USART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */
<> 144:ef7eb2e8f9f7 487 #define USART_CLKDIV_DIV_DEFAULT (_USART_CLKDIV_DIV_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_CLKDIV */
<> 144:ef7eb2e8f9f7 488
<> 144:ef7eb2e8f9f7 489 /* Bit fields for USART RXDATAX */
<> 144:ef7eb2e8f9f7 490 #define _USART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAX */
<> 144:ef7eb2e8f9f7 491 #define _USART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAX */
<> 144:ef7eb2e8f9f7 492 #define _USART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */
<> 144:ef7eb2e8f9f7 493 #define _USART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for USART_RXDATA */
<> 144:ef7eb2e8f9f7 494 #define _USART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */
<> 144:ef7eb2e8f9f7 495 #define USART_RXDATAX_RXDATA_DEFAULT (_USART_RXDATAX_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAX */
<> 144:ef7eb2e8f9f7 496 #define USART_RXDATAX_PERR (0x1UL << 14) /**< Data Parity Error */
<> 144:ef7eb2e8f9f7 497 #define _USART_RXDATAX_PERR_SHIFT 14 /**< Shift value for USART_PERR */
<> 144:ef7eb2e8f9f7 498 #define _USART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for USART_PERR */
<> 144:ef7eb2e8f9f7 499 #define _USART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */
<> 144:ef7eb2e8f9f7 500 #define USART_RXDATAX_PERR_DEFAULT (_USART_RXDATAX_PERR_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDATAX */
<> 144:ef7eb2e8f9f7 501 #define USART_RXDATAX_FERR (0x1UL << 15) /**< Data Framing Error */
<> 144:ef7eb2e8f9f7 502 #define _USART_RXDATAX_FERR_SHIFT 15 /**< Shift value for USART_FERR */
<> 144:ef7eb2e8f9f7 503 #define _USART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for USART_FERR */
<> 144:ef7eb2e8f9f7 504 #define _USART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */
<> 144:ef7eb2e8f9f7 505 #define USART_RXDATAX_FERR_DEFAULT (_USART_RXDATAX_FERR_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAX */
<> 144:ef7eb2e8f9f7 506
<> 144:ef7eb2e8f9f7 507 /* Bit fields for USART RXDATA */
<> 144:ef7eb2e8f9f7 508 #define _USART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATA */
<> 144:ef7eb2e8f9f7 509 #define _USART_RXDATA_MASK 0x000000FFUL /**< Mask for USART_RXDATA */
<> 144:ef7eb2e8f9f7 510 #define _USART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */
<> 144:ef7eb2e8f9f7 511 #define _USART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for USART_RXDATA */
<> 144:ef7eb2e8f9f7 512 #define _USART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATA */
<> 144:ef7eb2e8f9f7 513 #define USART_RXDATA_RXDATA_DEFAULT (_USART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATA */
<> 144:ef7eb2e8f9f7 514
<> 144:ef7eb2e8f9f7 515 /* Bit fields for USART RXDOUBLEX */
<> 144:ef7eb2e8f9f7 516 #define _USART_RXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEX */
<> 144:ef7eb2e8f9f7 517 #define _USART_RXDOUBLEX_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEX */
<> 144:ef7eb2e8f9f7 518 #define _USART_RXDOUBLEX_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */
<> 144:ef7eb2e8f9f7 519 #define _USART_RXDOUBLEX_RXDATA0_MASK 0x1FFUL /**< Bit mask for USART_RXDATA0 */
<> 144:ef7eb2e8f9f7 520 #define _USART_RXDOUBLEX_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */
<> 144:ef7eb2e8f9f7 521 #define USART_RXDOUBLEX_RXDATA0_DEFAULT (_USART_RXDOUBLEX_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
<> 144:ef7eb2e8f9f7 522 #define USART_RXDOUBLEX_PERR0 (0x1UL << 14) /**< Data Parity Error 0 */
<> 144:ef7eb2e8f9f7 523 #define _USART_RXDOUBLEX_PERR0_SHIFT 14 /**< Shift value for USART_PERR0 */
<> 144:ef7eb2e8f9f7 524 #define _USART_RXDOUBLEX_PERR0_MASK 0x4000UL /**< Bit mask for USART_PERR0 */
<> 144:ef7eb2e8f9f7 525 #define _USART_RXDOUBLEX_PERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */
<> 144:ef7eb2e8f9f7 526 #define USART_RXDOUBLEX_PERR0_DEFAULT (_USART_RXDOUBLEX_PERR0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
<> 144:ef7eb2e8f9f7 527 #define USART_RXDOUBLEX_FERR0 (0x1UL << 15) /**< Data Framing Error 0 */
<> 144:ef7eb2e8f9f7 528 #define _USART_RXDOUBLEX_FERR0_SHIFT 15 /**< Shift value for USART_FERR0 */
<> 144:ef7eb2e8f9f7 529 #define _USART_RXDOUBLEX_FERR0_MASK 0x8000UL /**< Bit mask for USART_FERR0 */
<> 144:ef7eb2e8f9f7 530 #define _USART_RXDOUBLEX_FERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */
<> 144:ef7eb2e8f9f7 531 #define USART_RXDOUBLEX_FERR0_DEFAULT (_USART_RXDOUBLEX_FERR0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
<> 144:ef7eb2e8f9f7 532 #define _USART_RXDOUBLEX_RXDATA1_SHIFT 16 /**< Shift value for USART_RXDATA1 */
<> 144:ef7eb2e8f9f7 533 #define _USART_RXDOUBLEX_RXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATA1 */
<> 144:ef7eb2e8f9f7 534 #define _USART_RXDOUBLEX_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */
<> 144:ef7eb2e8f9f7 535 #define USART_RXDOUBLEX_RXDATA1_DEFAULT (_USART_RXDOUBLEX_RXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
<> 144:ef7eb2e8f9f7 536 #define USART_RXDOUBLEX_PERR1 (0x1UL << 30) /**< Data Parity Error 1 */
<> 144:ef7eb2e8f9f7 537 #define _USART_RXDOUBLEX_PERR1_SHIFT 30 /**< Shift value for USART_PERR1 */
<> 144:ef7eb2e8f9f7 538 #define _USART_RXDOUBLEX_PERR1_MASK 0x40000000UL /**< Bit mask for USART_PERR1 */
<> 144:ef7eb2e8f9f7 539 #define _USART_RXDOUBLEX_PERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */
<> 144:ef7eb2e8f9f7 540 #define USART_RXDOUBLEX_PERR1_DEFAULT (_USART_RXDOUBLEX_PERR1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
<> 144:ef7eb2e8f9f7 541 #define USART_RXDOUBLEX_FERR1 (0x1UL << 31) /**< Data Framing Error 1 */
<> 144:ef7eb2e8f9f7 542 #define _USART_RXDOUBLEX_FERR1_SHIFT 31 /**< Shift value for USART_FERR1 */
<> 144:ef7eb2e8f9f7 543 #define _USART_RXDOUBLEX_FERR1_MASK 0x80000000UL /**< Bit mask for USART_FERR1 */
<> 144:ef7eb2e8f9f7 544 #define _USART_RXDOUBLEX_FERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */
<> 144:ef7eb2e8f9f7 545 #define USART_RXDOUBLEX_FERR1_DEFAULT (_USART_RXDOUBLEX_FERR1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
<> 144:ef7eb2e8f9f7 546
<> 144:ef7eb2e8f9f7 547 /* Bit fields for USART RXDOUBLE */
<> 144:ef7eb2e8f9f7 548 #define _USART_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLE */
<> 144:ef7eb2e8f9f7 549 #define _USART_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_RXDOUBLE */
<> 144:ef7eb2e8f9f7 550 #define _USART_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */
<> 144:ef7eb2e8f9f7 551 #define _USART_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for USART_RXDATA0 */
<> 144:ef7eb2e8f9f7 552 #define _USART_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */
<> 144:ef7eb2e8f9f7 553 #define USART_RXDOUBLE_RXDATA0_DEFAULT (_USART_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLE */
<> 144:ef7eb2e8f9f7 554 #define _USART_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for USART_RXDATA1 */
<> 144:ef7eb2e8f9f7 555 #define _USART_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for USART_RXDATA1 */
<> 144:ef7eb2e8f9f7 556 #define _USART_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */
<> 144:ef7eb2e8f9f7 557 #define USART_RXDOUBLE_RXDATA1_DEFAULT (_USART_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_RXDOUBLE */
<> 144:ef7eb2e8f9f7 558
<> 144:ef7eb2e8f9f7 559 /* Bit fields for USART RXDATAXP */
<> 144:ef7eb2e8f9f7 560 #define _USART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAXP */
<> 144:ef7eb2e8f9f7 561 #define _USART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAXP */
<> 144:ef7eb2e8f9f7 562 #define _USART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for USART_RXDATAP */
<> 144:ef7eb2e8f9f7 563 #define _USART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP */
<> 144:ef7eb2e8f9f7 564 #define _USART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */
<> 144:ef7eb2e8f9f7 565 #define USART_RXDATAXP_RXDATAP_DEFAULT (_USART_RXDATAXP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAXP */
<> 144:ef7eb2e8f9f7 566 #define USART_RXDATAXP_PERRP (0x1UL << 14) /**< Data Parity Error Peek */
<> 144:ef7eb2e8f9f7 567 #define _USART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for USART_PERRP */
<> 144:ef7eb2e8f9f7 568 #define _USART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for USART_PERRP */
<> 144:ef7eb2e8f9f7 569 #define _USART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */
<> 144:ef7eb2e8f9f7 570 #define USART_RXDATAXP_PERRP_DEFAULT (_USART_RXDATAXP_PERRP_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDATAXP */
<> 144:ef7eb2e8f9f7 571 #define USART_RXDATAXP_FERRP (0x1UL << 15) /**< Data Framing Error Peek */
<> 144:ef7eb2e8f9f7 572 #define _USART_RXDATAXP_FERRP_SHIFT 15 /**< Shift value for USART_FERRP */
<> 144:ef7eb2e8f9f7 573 #define _USART_RXDATAXP_FERRP_MASK 0x8000UL /**< Bit mask for USART_FERRP */
<> 144:ef7eb2e8f9f7 574 #define _USART_RXDATAXP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */
<> 144:ef7eb2e8f9f7 575 #define USART_RXDATAXP_FERRP_DEFAULT (_USART_RXDATAXP_FERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAXP */
<> 144:ef7eb2e8f9f7 576
<> 144:ef7eb2e8f9f7 577 /* Bit fields for USART RXDOUBLEXP */
<> 144:ef7eb2e8f9f7 578 #define _USART_RXDOUBLEXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEXP */
<> 144:ef7eb2e8f9f7 579 #define _USART_RXDOUBLEXP_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEXP */
<> 144:ef7eb2e8f9f7 580 #define _USART_RXDOUBLEXP_RXDATAP0_SHIFT 0 /**< Shift value for USART_RXDATAP0 */
<> 144:ef7eb2e8f9f7 581 #define _USART_RXDOUBLEXP_RXDATAP0_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP0 */
<> 144:ef7eb2e8f9f7 582 #define _USART_RXDOUBLEXP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */
<> 144:ef7eb2e8f9f7 583 #define USART_RXDOUBLEXP_RXDATAP0_DEFAULT (_USART_RXDOUBLEXP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */
<> 144:ef7eb2e8f9f7 584 #define USART_RXDOUBLEXP_PERRP0 (0x1UL << 14) /**< Data Parity Error 0 Peek */
<> 144:ef7eb2e8f9f7 585 #define _USART_RXDOUBLEXP_PERRP0_SHIFT 14 /**< Shift value for USART_PERRP0 */
<> 144:ef7eb2e8f9f7 586 #define _USART_RXDOUBLEXP_PERRP0_MASK 0x4000UL /**< Bit mask for USART_PERRP0 */
<> 144:ef7eb2e8f9f7 587 #define _USART_RXDOUBLEXP_PERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */
<> 144:ef7eb2e8f9f7 588 #define USART_RXDOUBLEXP_PERRP0_DEFAULT (_USART_RXDOUBLEXP_PERRP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */
<> 144:ef7eb2e8f9f7 589 #define USART_RXDOUBLEXP_FERRP0 (0x1UL << 15) /**< Data Framing Error 0 Peek */
<> 144:ef7eb2e8f9f7 590 #define _USART_RXDOUBLEXP_FERRP0_SHIFT 15 /**< Shift value for USART_FERRP0 */
<> 144:ef7eb2e8f9f7 591 #define _USART_RXDOUBLEXP_FERRP0_MASK 0x8000UL /**< Bit mask for USART_FERRP0 */
<> 144:ef7eb2e8f9f7 592 #define _USART_RXDOUBLEXP_FERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */
<> 144:ef7eb2e8f9f7 593 #define USART_RXDOUBLEXP_FERRP0_DEFAULT (_USART_RXDOUBLEXP_FERRP0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */
<> 144:ef7eb2e8f9f7 594 #define _USART_RXDOUBLEXP_RXDATAP1_SHIFT 16 /**< Shift value for USART_RXDATAP1 */
<> 144:ef7eb2e8f9f7 595 #define _USART_RXDOUBLEXP_RXDATAP1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATAP1 */
<> 144:ef7eb2e8f9f7 596 #define _USART_RXDOUBLEXP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */
<> 144:ef7eb2e8f9f7 597 #define USART_RXDOUBLEXP_RXDATAP1_DEFAULT (_USART_RXDOUBLEXP_RXDATAP1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */
<> 144:ef7eb2e8f9f7 598 #define USART_RXDOUBLEXP_PERRP1 (0x1UL << 30) /**< Data Parity Error 1 Peek */
<> 144:ef7eb2e8f9f7 599 #define _USART_RXDOUBLEXP_PERRP1_SHIFT 30 /**< Shift value for USART_PERRP1 */
<> 144:ef7eb2e8f9f7 600 #define _USART_RXDOUBLEXP_PERRP1_MASK 0x40000000UL /**< Bit mask for USART_PERRP1 */
<> 144:ef7eb2e8f9f7 601 #define _USART_RXDOUBLEXP_PERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */
<> 144:ef7eb2e8f9f7 602 #define USART_RXDOUBLEXP_PERRP1_DEFAULT (_USART_RXDOUBLEXP_PERRP1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */
<> 144:ef7eb2e8f9f7 603 #define USART_RXDOUBLEXP_FERRP1 (0x1UL << 31) /**< Data Framing Error 1 Peek */
<> 144:ef7eb2e8f9f7 604 #define _USART_RXDOUBLEXP_FERRP1_SHIFT 31 /**< Shift value for USART_FERRP1 */
<> 144:ef7eb2e8f9f7 605 #define _USART_RXDOUBLEXP_FERRP1_MASK 0x80000000UL /**< Bit mask for USART_FERRP1 */
<> 144:ef7eb2e8f9f7 606 #define _USART_RXDOUBLEXP_FERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */
<> 144:ef7eb2e8f9f7 607 #define USART_RXDOUBLEXP_FERRP1_DEFAULT (_USART_RXDOUBLEXP_FERRP1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */
<> 144:ef7eb2e8f9f7 608
<> 144:ef7eb2e8f9f7 609 /* Bit fields for USART TXDATAX */
<> 144:ef7eb2e8f9f7 610 #define _USART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATAX */
<> 144:ef7eb2e8f9f7 611 #define _USART_TXDATAX_MASK 0x0000F9FFUL /**< Mask for USART_TXDATAX */
<> 144:ef7eb2e8f9f7 612 #define _USART_TXDATAX_TXDATAX_SHIFT 0 /**< Shift value for USART_TXDATAX */
<> 144:ef7eb2e8f9f7 613 #define _USART_TXDATAX_TXDATAX_MASK 0x1FFUL /**< Bit mask for USART_TXDATAX */
<> 144:ef7eb2e8f9f7 614 #define _USART_TXDATAX_TXDATAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */
<> 144:ef7eb2e8f9f7 615 #define USART_TXDATAX_TXDATAX_DEFAULT (_USART_TXDATAX_TXDATAX_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATAX */
<> 144:ef7eb2e8f9f7 616 #define USART_TXDATAX_UBRXAT (0x1UL << 11) /**< Unblock RX After Transmission */
<> 144:ef7eb2e8f9f7 617 #define _USART_TXDATAX_UBRXAT_SHIFT 11 /**< Shift value for USART_UBRXAT */
<> 144:ef7eb2e8f9f7 618 #define _USART_TXDATAX_UBRXAT_MASK 0x800UL /**< Bit mask for USART_UBRXAT */
<> 144:ef7eb2e8f9f7 619 #define _USART_TXDATAX_UBRXAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */
<> 144:ef7eb2e8f9f7 620 #define USART_TXDATAX_UBRXAT_DEFAULT (_USART_TXDATAX_UBRXAT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDATAX */
<> 144:ef7eb2e8f9f7 621 #define USART_TXDATAX_TXTRIAT (0x1UL << 12) /**< Set TXTRI After Transmission */
<> 144:ef7eb2e8f9f7 622 #define _USART_TXDATAX_TXTRIAT_SHIFT 12 /**< Shift value for USART_TXTRIAT */
<> 144:ef7eb2e8f9f7 623 #define _USART_TXDATAX_TXTRIAT_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT */
<> 144:ef7eb2e8f9f7 624 #define _USART_TXDATAX_TXTRIAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */
<> 144:ef7eb2e8f9f7 625 #define USART_TXDATAX_TXTRIAT_DEFAULT (_USART_TXDATAX_TXTRIAT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDATAX */
<> 144:ef7eb2e8f9f7 626 #define USART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data As Break */
<> 144:ef7eb2e8f9f7 627 #define _USART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for USART_TXBREAK */
<> 144:ef7eb2e8f9f7 628 #define _USART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for USART_TXBREAK */
<> 144:ef7eb2e8f9f7 629 #define _USART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */
<> 144:ef7eb2e8f9f7 630 #define USART_TXDATAX_TXBREAK_DEFAULT (_USART_TXDATAX_TXBREAK_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDATAX */
<> 144:ef7eb2e8f9f7 631 #define USART_TXDATAX_TXDISAT (0x1UL << 14) /**< Clear TXEN After Transmission */
<> 144:ef7eb2e8f9f7 632 #define _USART_TXDATAX_TXDISAT_SHIFT 14 /**< Shift value for USART_TXDISAT */
<> 144:ef7eb2e8f9f7 633 #define _USART_TXDATAX_TXDISAT_MASK 0x4000UL /**< Bit mask for USART_TXDISAT */
<> 144:ef7eb2e8f9f7 634 #define _USART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */
<> 144:ef7eb2e8f9f7 635 #define USART_TXDATAX_TXDISAT_DEFAULT (_USART_TXDATAX_TXDISAT_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDATAX */
<> 144:ef7eb2e8f9f7 636 #define USART_TXDATAX_RXENAT (0x1UL << 15) /**< Enable RX After Transmission */
<> 144:ef7eb2e8f9f7 637 #define _USART_TXDATAX_RXENAT_SHIFT 15 /**< Shift value for USART_RXENAT */
<> 144:ef7eb2e8f9f7 638 #define _USART_TXDATAX_RXENAT_MASK 0x8000UL /**< Bit mask for USART_RXENAT */
<> 144:ef7eb2e8f9f7 639 #define _USART_TXDATAX_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */
<> 144:ef7eb2e8f9f7 640 #define USART_TXDATAX_RXENAT_DEFAULT (_USART_TXDATAX_RXENAT_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDATAX */
<> 144:ef7eb2e8f9f7 641
<> 144:ef7eb2e8f9f7 642 /* Bit fields for USART TXDATA */
<> 144:ef7eb2e8f9f7 643 #define _USART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATA */
<> 144:ef7eb2e8f9f7 644 #define _USART_TXDATA_MASK 0x000000FFUL /**< Mask for USART_TXDATA */
<> 144:ef7eb2e8f9f7 645 #define _USART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for USART_TXDATA */
<> 144:ef7eb2e8f9f7 646 #define _USART_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for USART_TXDATA */
<> 144:ef7eb2e8f9f7 647 #define _USART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATA */
<> 144:ef7eb2e8f9f7 648 #define USART_TXDATA_TXDATA_DEFAULT (_USART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATA */
<> 144:ef7eb2e8f9f7 649
<> 144:ef7eb2e8f9f7 650 /* Bit fields for USART TXDOUBLEX */
<> 144:ef7eb2e8f9f7 651 #define _USART_TXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLEX */
<> 144:ef7eb2e8f9f7 652 #define _USART_TXDOUBLEX_MASK 0xF9FFF9FFUL /**< Mask for USART_TXDOUBLEX */
<> 144:ef7eb2e8f9f7 653 #define _USART_TXDOUBLEX_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */
<> 144:ef7eb2e8f9f7 654 #define _USART_TXDOUBLEX_TXDATA0_MASK 0x1FFUL /**< Bit mask for USART_TXDATA0 */
<> 144:ef7eb2e8f9f7 655 #define _USART_TXDOUBLEX_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
<> 144:ef7eb2e8f9f7 656 #define USART_TXDOUBLEX_TXDATA0_DEFAULT (_USART_TXDOUBLEX_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
<> 144:ef7eb2e8f9f7 657 #define USART_TXDOUBLEX_UBRXAT0 (0x1UL << 11) /**< Unblock RX After Transmission */
<> 144:ef7eb2e8f9f7 658 #define _USART_TXDOUBLEX_UBRXAT0_SHIFT 11 /**< Shift value for USART_UBRXAT0 */
<> 144:ef7eb2e8f9f7 659 #define _USART_TXDOUBLEX_UBRXAT0_MASK 0x800UL /**< Bit mask for USART_UBRXAT0 */
<> 144:ef7eb2e8f9f7 660 #define _USART_TXDOUBLEX_UBRXAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
<> 144:ef7eb2e8f9f7 661 #define USART_TXDOUBLEX_UBRXAT0_DEFAULT (_USART_TXDOUBLEX_UBRXAT0_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
<> 144:ef7eb2e8f9f7 662 #define USART_TXDOUBLEX_TXTRIAT0 (0x1UL << 12) /**< Set TXTRI After Transmission */
<> 144:ef7eb2e8f9f7 663 #define _USART_TXDOUBLEX_TXTRIAT0_SHIFT 12 /**< Shift value for USART_TXTRIAT0 */
<> 144:ef7eb2e8f9f7 664 #define _USART_TXDOUBLEX_TXTRIAT0_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT0 */
<> 144:ef7eb2e8f9f7 665 #define _USART_TXDOUBLEX_TXTRIAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
<> 144:ef7eb2e8f9f7 666 #define USART_TXDOUBLEX_TXTRIAT0_DEFAULT (_USART_TXDOUBLEX_TXTRIAT0_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
<> 144:ef7eb2e8f9f7 667 #define USART_TXDOUBLEX_TXBREAK0 (0x1UL << 13) /**< Transmit Data As Break */
<> 144:ef7eb2e8f9f7 668 #define _USART_TXDOUBLEX_TXBREAK0_SHIFT 13 /**< Shift value for USART_TXBREAK0 */
<> 144:ef7eb2e8f9f7 669 #define _USART_TXDOUBLEX_TXBREAK0_MASK 0x2000UL /**< Bit mask for USART_TXBREAK0 */
<> 144:ef7eb2e8f9f7 670 #define _USART_TXDOUBLEX_TXBREAK0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
<> 144:ef7eb2e8f9f7 671 #define USART_TXDOUBLEX_TXBREAK0_DEFAULT (_USART_TXDOUBLEX_TXBREAK0_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
<> 144:ef7eb2e8f9f7 672 #define USART_TXDOUBLEX_TXDISAT0 (0x1UL << 14) /**< Clear TXEN After Transmission */
<> 144:ef7eb2e8f9f7 673 #define _USART_TXDOUBLEX_TXDISAT0_SHIFT 14 /**< Shift value for USART_TXDISAT0 */
<> 144:ef7eb2e8f9f7 674 #define _USART_TXDOUBLEX_TXDISAT0_MASK 0x4000UL /**< Bit mask for USART_TXDISAT0 */
<> 144:ef7eb2e8f9f7 675 #define _USART_TXDOUBLEX_TXDISAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
<> 144:ef7eb2e8f9f7 676 #define USART_TXDOUBLEX_TXDISAT0_DEFAULT (_USART_TXDOUBLEX_TXDISAT0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
<> 144:ef7eb2e8f9f7 677 #define USART_TXDOUBLEX_RXENAT0 (0x1UL << 15) /**< Enable RX After Transmission */
<> 144:ef7eb2e8f9f7 678 #define _USART_TXDOUBLEX_RXENAT0_SHIFT 15 /**< Shift value for USART_RXENAT0 */
<> 144:ef7eb2e8f9f7 679 #define _USART_TXDOUBLEX_RXENAT0_MASK 0x8000UL /**< Bit mask for USART_RXENAT0 */
<> 144:ef7eb2e8f9f7 680 #define _USART_TXDOUBLEX_RXENAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
<> 144:ef7eb2e8f9f7 681 #define USART_TXDOUBLEX_RXENAT0_DEFAULT (_USART_TXDOUBLEX_RXENAT0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
<> 144:ef7eb2e8f9f7 682 #define _USART_TXDOUBLEX_TXDATA1_SHIFT 16 /**< Shift value for USART_TXDATA1 */
<> 144:ef7eb2e8f9f7 683 #define _USART_TXDOUBLEX_TXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_TXDATA1 */
<> 144:ef7eb2e8f9f7 684 #define _USART_TXDOUBLEX_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
<> 144:ef7eb2e8f9f7 685 #define USART_TXDOUBLEX_TXDATA1_DEFAULT (_USART_TXDOUBLEX_TXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
<> 144:ef7eb2e8f9f7 686 #define USART_TXDOUBLEX_UBRXAT1 (0x1UL << 27) /**< Unblock RX After Transmission */
<> 144:ef7eb2e8f9f7 687 #define _USART_TXDOUBLEX_UBRXAT1_SHIFT 27 /**< Shift value for USART_UBRXAT1 */
<> 144:ef7eb2e8f9f7 688 #define _USART_TXDOUBLEX_UBRXAT1_MASK 0x8000000UL /**< Bit mask for USART_UBRXAT1 */
<> 144:ef7eb2e8f9f7 689 #define _USART_TXDOUBLEX_UBRXAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
<> 144:ef7eb2e8f9f7 690 #define USART_TXDOUBLEX_UBRXAT1_DEFAULT (_USART_TXDOUBLEX_UBRXAT1_DEFAULT << 27) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
<> 144:ef7eb2e8f9f7 691 #define USART_TXDOUBLEX_TXTRIAT1 (0x1UL << 28) /**< Set TXTRI After Transmission */
<> 144:ef7eb2e8f9f7 692 #define _USART_TXDOUBLEX_TXTRIAT1_SHIFT 28 /**< Shift value for USART_TXTRIAT1 */
<> 144:ef7eb2e8f9f7 693 #define _USART_TXDOUBLEX_TXTRIAT1_MASK 0x10000000UL /**< Bit mask for USART_TXTRIAT1 */
<> 144:ef7eb2e8f9f7 694 #define _USART_TXDOUBLEX_TXTRIAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
<> 144:ef7eb2e8f9f7 695 #define USART_TXDOUBLEX_TXTRIAT1_DEFAULT (_USART_TXDOUBLEX_TXTRIAT1_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
<> 144:ef7eb2e8f9f7 696 #define USART_TXDOUBLEX_TXBREAK1 (0x1UL << 29) /**< Transmit Data As Break */
<> 144:ef7eb2e8f9f7 697 #define _USART_TXDOUBLEX_TXBREAK1_SHIFT 29 /**< Shift value for USART_TXBREAK1 */
<> 144:ef7eb2e8f9f7 698 #define _USART_TXDOUBLEX_TXBREAK1_MASK 0x20000000UL /**< Bit mask for USART_TXBREAK1 */
<> 144:ef7eb2e8f9f7 699 #define _USART_TXDOUBLEX_TXBREAK1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
<> 144:ef7eb2e8f9f7 700 #define USART_TXDOUBLEX_TXBREAK1_DEFAULT (_USART_TXDOUBLEX_TXBREAK1_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
<> 144:ef7eb2e8f9f7 701 #define USART_TXDOUBLEX_TXDISAT1 (0x1UL << 30) /**< Clear TXEN After Transmission */
<> 144:ef7eb2e8f9f7 702 #define _USART_TXDOUBLEX_TXDISAT1_SHIFT 30 /**< Shift value for USART_TXDISAT1 */
<> 144:ef7eb2e8f9f7 703 #define _USART_TXDOUBLEX_TXDISAT1_MASK 0x40000000UL /**< Bit mask for USART_TXDISAT1 */
<> 144:ef7eb2e8f9f7 704 #define _USART_TXDOUBLEX_TXDISAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
<> 144:ef7eb2e8f9f7 705 #define USART_TXDOUBLEX_TXDISAT1_DEFAULT (_USART_TXDOUBLEX_TXDISAT1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
<> 144:ef7eb2e8f9f7 706 #define USART_TXDOUBLEX_RXENAT1 (0x1UL << 31) /**< Enable RX After Transmission */
<> 144:ef7eb2e8f9f7 707 #define _USART_TXDOUBLEX_RXENAT1_SHIFT 31 /**< Shift value for USART_RXENAT1 */
<> 144:ef7eb2e8f9f7 708 #define _USART_TXDOUBLEX_RXENAT1_MASK 0x80000000UL /**< Bit mask for USART_RXENAT1 */
<> 144:ef7eb2e8f9f7 709 #define _USART_TXDOUBLEX_RXENAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
<> 144:ef7eb2e8f9f7 710 #define USART_TXDOUBLEX_RXENAT1_DEFAULT (_USART_TXDOUBLEX_RXENAT1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
<> 144:ef7eb2e8f9f7 711
<> 144:ef7eb2e8f9f7 712 /* Bit fields for USART TXDOUBLE */
<> 144:ef7eb2e8f9f7 713 #define _USART_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLE */
<> 144:ef7eb2e8f9f7 714 #define _USART_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_TXDOUBLE */
<> 144:ef7eb2e8f9f7 715 #define _USART_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */
<> 144:ef7eb2e8f9f7 716 #define _USART_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for USART_TXDATA0 */
<> 144:ef7eb2e8f9f7 717 #define _USART_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */
<> 144:ef7eb2e8f9f7 718 #define USART_TXDOUBLE_TXDATA0_DEFAULT (_USART_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLE */
<> 144:ef7eb2e8f9f7 719 #define _USART_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for USART_TXDATA1 */
<> 144:ef7eb2e8f9f7 720 #define _USART_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for USART_TXDATA1 */
<> 144:ef7eb2e8f9f7 721 #define _USART_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */
<> 144:ef7eb2e8f9f7 722 #define USART_TXDOUBLE_TXDATA1_DEFAULT (_USART_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TXDOUBLE */
<> 144:ef7eb2e8f9f7 723
<> 144:ef7eb2e8f9f7 724 /* Bit fields for USART IF */
<> 144:ef7eb2e8f9f7 725 #define _USART_IF_RESETVALUE 0x00000002UL /**< Default value for USART_IF */
<> 144:ef7eb2e8f9f7 726 #define _USART_IF_MASK 0x00001FFFUL /**< Mask for USART_IF */
<> 144:ef7eb2e8f9f7 727 #define USART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */
<> 144:ef7eb2e8f9f7 728 #define _USART_IF_TXC_SHIFT 0 /**< Shift value for USART_TXC */
<> 144:ef7eb2e8f9f7 729 #define _USART_IF_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */
<> 144:ef7eb2e8f9f7 730 #define _USART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
<> 144:ef7eb2e8f9f7 731 #define USART_IF_TXC_DEFAULT (_USART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IF */
<> 144:ef7eb2e8f9f7 732 #define USART_IF_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Flag */
<> 144:ef7eb2e8f9f7 733 #define _USART_IF_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */
<> 144:ef7eb2e8f9f7 734 #define _USART_IF_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */
<> 144:ef7eb2e8f9f7 735 #define _USART_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_IF */
<> 144:ef7eb2e8f9f7 736 #define USART_IF_TXBL_DEFAULT (_USART_IF_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IF */
<> 144:ef7eb2e8f9f7 737 #define USART_IF_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Flag */
<> 144:ef7eb2e8f9f7 738 #define _USART_IF_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */
<> 144:ef7eb2e8f9f7 739 #define _USART_IF_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */
<> 144:ef7eb2e8f9f7 740 #define _USART_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
<> 144:ef7eb2e8f9f7 741 #define USART_IF_RXDATAV_DEFAULT (_USART_IF_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IF */
<> 144:ef7eb2e8f9f7 742 #define USART_IF_RXFULL (0x1UL << 3) /**< RX Buffer Full Interrupt Flag */
<> 144:ef7eb2e8f9f7 743 #define _USART_IF_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */
<> 144:ef7eb2e8f9f7 744 #define _USART_IF_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */
<> 144:ef7eb2e8f9f7 745 #define _USART_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
<> 144:ef7eb2e8f9f7 746 #define USART_IF_RXFULL_DEFAULT (_USART_IF_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IF */
<> 144:ef7eb2e8f9f7 747 #define USART_IF_RXOF (0x1UL << 4) /**< RX Overflow Interrupt Flag */
<> 144:ef7eb2e8f9f7 748 #define _USART_IF_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */
<> 144:ef7eb2e8f9f7 749 #define _USART_IF_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */
<> 144:ef7eb2e8f9f7 750 #define _USART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
<> 144:ef7eb2e8f9f7 751 #define USART_IF_RXOF_DEFAULT (_USART_IF_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IF */
<> 144:ef7eb2e8f9f7 752 #define USART_IF_RXUF (0x1UL << 5) /**< RX Underflow Interrupt Flag */
<> 144:ef7eb2e8f9f7 753 #define _USART_IF_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */
<> 144:ef7eb2e8f9f7 754 #define _USART_IF_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */
<> 144:ef7eb2e8f9f7 755 #define _USART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
<> 144:ef7eb2e8f9f7 756 #define USART_IF_RXUF_DEFAULT (_USART_IF_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IF */
<> 144:ef7eb2e8f9f7 757 #define USART_IF_TXOF (0x1UL << 6) /**< TX Overflow Interrupt Flag */
<> 144:ef7eb2e8f9f7 758 #define _USART_IF_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */
<> 144:ef7eb2e8f9f7 759 #define _USART_IF_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */
<> 144:ef7eb2e8f9f7 760 #define _USART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
<> 144:ef7eb2e8f9f7 761 #define USART_IF_TXOF_DEFAULT (_USART_IF_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IF */
<> 144:ef7eb2e8f9f7 762 #define USART_IF_TXUF (0x1UL << 7) /**< TX Underflow Interrupt Flag */
<> 144:ef7eb2e8f9f7 763 #define _USART_IF_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */
<> 144:ef7eb2e8f9f7 764 #define _USART_IF_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */
<> 144:ef7eb2e8f9f7 765 #define _USART_IF_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
<> 144:ef7eb2e8f9f7 766 #define USART_IF_TXUF_DEFAULT (_USART_IF_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IF */
<> 144:ef7eb2e8f9f7 767 #define USART_IF_PERR (0x1UL << 8) /**< Parity Error Interrupt Flag */
<> 144:ef7eb2e8f9f7 768 #define _USART_IF_PERR_SHIFT 8 /**< Shift value for USART_PERR */
<> 144:ef7eb2e8f9f7 769 #define _USART_IF_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */
<> 144:ef7eb2e8f9f7 770 #define _USART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
<> 144:ef7eb2e8f9f7 771 #define USART_IF_PERR_DEFAULT (_USART_IF_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IF */
<> 144:ef7eb2e8f9f7 772 #define USART_IF_FERR (0x1UL << 9) /**< Framing Error Interrupt Flag */
<> 144:ef7eb2e8f9f7 773 #define _USART_IF_FERR_SHIFT 9 /**< Shift value for USART_FERR */
<> 144:ef7eb2e8f9f7 774 #define _USART_IF_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */
<> 144:ef7eb2e8f9f7 775 #define _USART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
<> 144:ef7eb2e8f9f7 776 #define USART_IF_FERR_DEFAULT (_USART_IF_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IF */
<> 144:ef7eb2e8f9f7 777 #define USART_IF_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt Flag */
<> 144:ef7eb2e8f9f7 778 #define _USART_IF_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */
<> 144:ef7eb2e8f9f7 779 #define _USART_IF_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */
<> 144:ef7eb2e8f9f7 780 #define _USART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
<> 144:ef7eb2e8f9f7 781 #define USART_IF_MPAF_DEFAULT (_USART_IF_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IF */
<> 144:ef7eb2e8f9f7 782 #define USART_IF_SSM (0x1UL << 11) /**< Slave-Select In Master Mode Interrupt Flag */
<> 144:ef7eb2e8f9f7 783 #define _USART_IF_SSM_SHIFT 11 /**< Shift value for USART_SSM */
<> 144:ef7eb2e8f9f7 784 #define _USART_IF_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */
<> 144:ef7eb2e8f9f7 785 #define _USART_IF_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
<> 144:ef7eb2e8f9f7 786 #define USART_IF_SSM_DEFAULT (_USART_IF_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IF */
<> 144:ef7eb2e8f9f7 787 #define USART_IF_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Flag */
<> 144:ef7eb2e8f9f7 788 #define _USART_IF_CCF_SHIFT 12 /**< Shift value for USART_CCF */
<> 144:ef7eb2e8f9f7 789 #define _USART_IF_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */
<> 144:ef7eb2e8f9f7 790 #define _USART_IF_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
<> 144:ef7eb2e8f9f7 791 #define USART_IF_CCF_DEFAULT (_USART_IF_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IF */
<> 144:ef7eb2e8f9f7 792
<> 144:ef7eb2e8f9f7 793 /* Bit fields for USART IFS */
<> 144:ef7eb2e8f9f7 794 #define _USART_IFS_RESETVALUE 0x00000000UL /**< Default value for USART_IFS */
<> 144:ef7eb2e8f9f7 795 #define _USART_IFS_MASK 0x00001FF9UL /**< Mask for USART_IFS */
<> 144:ef7eb2e8f9f7 796 #define USART_IFS_TXC (0x1UL << 0) /**< Set TX Complete Interrupt Flag */
<> 144:ef7eb2e8f9f7 797 #define _USART_IFS_TXC_SHIFT 0 /**< Shift value for USART_TXC */
<> 144:ef7eb2e8f9f7 798 #define _USART_IFS_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */
<> 144:ef7eb2e8f9f7 799 #define _USART_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
<> 144:ef7eb2e8f9f7 800 #define USART_IFS_TXC_DEFAULT (_USART_IFS_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IFS */
<> 144:ef7eb2e8f9f7 801 #define USART_IFS_RXFULL (0x1UL << 3) /**< Set RX Buffer Full Interrupt Flag */
<> 144:ef7eb2e8f9f7 802 #define _USART_IFS_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */
<> 144:ef7eb2e8f9f7 803 #define _USART_IFS_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */
<> 144:ef7eb2e8f9f7 804 #define _USART_IFS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
<> 144:ef7eb2e8f9f7 805 #define USART_IFS_RXFULL_DEFAULT (_USART_IFS_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IFS */
<> 144:ef7eb2e8f9f7 806 #define USART_IFS_RXOF (0x1UL << 4) /**< Set RX Overflow Interrupt Flag */
<> 144:ef7eb2e8f9f7 807 #define _USART_IFS_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */
<> 144:ef7eb2e8f9f7 808 #define _USART_IFS_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */
<> 144:ef7eb2e8f9f7 809 #define _USART_IFS_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
<> 144:ef7eb2e8f9f7 810 #define USART_IFS_RXOF_DEFAULT (_USART_IFS_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IFS */
<> 144:ef7eb2e8f9f7 811 #define USART_IFS_RXUF (0x1UL << 5) /**< Set RX Underflow Interrupt Flag */
<> 144:ef7eb2e8f9f7 812 #define _USART_IFS_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */
<> 144:ef7eb2e8f9f7 813 #define _USART_IFS_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */
<> 144:ef7eb2e8f9f7 814 #define _USART_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
<> 144:ef7eb2e8f9f7 815 #define USART_IFS_RXUF_DEFAULT (_USART_IFS_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IFS */
<> 144:ef7eb2e8f9f7 816 #define USART_IFS_TXOF (0x1UL << 6) /**< Set TX Overflow Interrupt Flag */
<> 144:ef7eb2e8f9f7 817 #define _USART_IFS_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */
<> 144:ef7eb2e8f9f7 818 #define _USART_IFS_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */
<> 144:ef7eb2e8f9f7 819 #define _USART_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
<> 144:ef7eb2e8f9f7 820 #define USART_IFS_TXOF_DEFAULT (_USART_IFS_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IFS */
<> 144:ef7eb2e8f9f7 821 #define USART_IFS_TXUF (0x1UL << 7) /**< Set TX Underflow Interrupt Flag */
<> 144:ef7eb2e8f9f7 822 #define _USART_IFS_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */
<> 144:ef7eb2e8f9f7 823 #define _USART_IFS_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */
<> 144:ef7eb2e8f9f7 824 #define _USART_IFS_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
<> 144:ef7eb2e8f9f7 825 #define USART_IFS_TXUF_DEFAULT (_USART_IFS_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IFS */
<> 144:ef7eb2e8f9f7 826 #define USART_IFS_PERR (0x1UL << 8) /**< Set Parity Error Interrupt Flag */
<> 144:ef7eb2e8f9f7 827 #define _USART_IFS_PERR_SHIFT 8 /**< Shift value for USART_PERR */
<> 144:ef7eb2e8f9f7 828 #define _USART_IFS_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */
<> 144:ef7eb2e8f9f7 829 #define _USART_IFS_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
<> 144:ef7eb2e8f9f7 830 #define USART_IFS_PERR_DEFAULT (_USART_IFS_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IFS */
<> 144:ef7eb2e8f9f7 831 #define USART_IFS_FERR (0x1UL << 9) /**< Set Framing Error Interrupt Flag */
<> 144:ef7eb2e8f9f7 832 #define _USART_IFS_FERR_SHIFT 9 /**< Shift value for USART_FERR */
<> 144:ef7eb2e8f9f7 833 #define _USART_IFS_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */
<> 144:ef7eb2e8f9f7 834 #define _USART_IFS_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
<> 144:ef7eb2e8f9f7 835 #define USART_IFS_FERR_DEFAULT (_USART_IFS_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IFS */
<> 144:ef7eb2e8f9f7 836 #define USART_IFS_MPAF (0x1UL << 10) /**< Set Multi-Processor Address Frame Interrupt Flag */
<> 144:ef7eb2e8f9f7 837 #define _USART_IFS_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */
<> 144:ef7eb2e8f9f7 838 #define _USART_IFS_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */
<> 144:ef7eb2e8f9f7 839 #define _USART_IFS_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
<> 144:ef7eb2e8f9f7 840 #define USART_IFS_MPAF_DEFAULT (_USART_IFS_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IFS */
<> 144:ef7eb2e8f9f7 841 #define USART_IFS_SSM (0x1UL << 11) /**< Set Slave-Select in Master mode Interrupt Flag */
<> 144:ef7eb2e8f9f7 842 #define _USART_IFS_SSM_SHIFT 11 /**< Shift value for USART_SSM */
<> 144:ef7eb2e8f9f7 843 #define _USART_IFS_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */
<> 144:ef7eb2e8f9f7 844 #define _USART_IFS_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
<> 144:ef7eb2e8f9f7 845 #define USART_IFS_SSM_DEFAULT (_USART_IFS_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IFS */
<> 144:ef7eb2e8f9f7 846 #define USART_IFS_CCF (0x1UL << 12) /**< Set Collision Check Fail Interrupt Flag */
<> 144:ef7eb2e8f9f7 847 #define _USART_IFS_CCF_SHIFT 12 /**< Shift value for USART_CCF */
<> 144:ef7eb2e8f9f7 848 #define _USART_IFS_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */
<> 144:ef7eb2e8f9f7 849 #define _USART_IFS_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
<> 144:ef7eb2e8f9f7 850 #define USART_IFS_CCF_DEFAULT (_USART_IFS_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IFS */
<> 144:ef7eb2e8f9f7 851
<> 144:ef7eb2e8f9f7 852 /* Bit fields for USART IFC */
<> 144:ef7eb2e8f9f7 853 #define _USART_IFC_RESETVALUE 0x00000000UL /**< Default value for USART_IFC */
<> 144:ef7eb2e8f9f7 854 #define _USART_IFC_MASK 0x00001FF9UL /**< Mask for USART_IFC */
<> 144:ef7eb2e8f9f7 855 #define USART_IFC_TXC (0x1UL << 0) /**< Clear TX Complete Interrupt Flag */
<> 144:ef7eb2e8f9f7 856 #define _USART_IFC_TXC_SHIFT 0 /**< Shift value for USART_TXC */
<> 144:ef7eb2e8f9f7 857 #define _USART_IFC_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */
<> 144:ef7eb2e8f9f7 858 #define _USART_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
<> 144:ef7eb2e8f9f7 859 #define USART_IFC_TXC_DEFAULT (_USART_IFC_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IFC */
<> 144:ef7eb2e8f9f7 860 #define USART_IFC_RXFULL (0x1UL << 3) /**< Clear RX Buffer Full Interrupt Flag */
<> 144:ef7eb2e8f9f7 861 #define _USART_IFC_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */
<> 144:ef7eb2e8f9f7 862 #define _USART_IFC_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */
<> 144:ef7eb2e8f9f7 863 #define _USART_IFC_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
<> 144:ef7eb2e8f9f7 864 #define USART_IFC_RXFULL_DEFAULT (_USART_IFC_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IFC */
<> 144:ef7eb2e8f9f7 865 #define USART_IFC_RXOF (0x1UL << 4) /**< Clear RX Overflow Interrupt Flag */
<> 144:ef7eb2e8f9f7 866 #define _USART_IFC_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */
<> 144:ef7eb2e8f9f7 867 #define _USART_IFC_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */
<> 144:ef7eb2e8f9f7 868 #define _USART_IFC_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
<> 144:ef7eb2e8f9f7 869 #define USART_IFC_RXOF_DEFAULT (_USART_IFC_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IFC */
<> 144:ef7eb2e8f9f7 870 #define USART_IFC_RXUF (0x1UL << 5) /**< Clear RX Underflow Interrupt Flag */
<> 144:ef7eb2e8f9f7 871 #define _USART_IFC_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */
<> 144:ef7eb2e8f9f7 872 #define _USART_IFC_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */
<> 144:ef7eb2e8f9f7 873 #define _USART_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
<> 144:ef7eb2e8f9f7 874 #define USART_IFC_RXUF_DEFAULT (_USART_IFC_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IFC */
<> 144:ef7eb2e8f9f7 875 #define USART_IFC_TXOF (0x1UL << 6) /**< Clear TX Overflow Interrupt Flag */
<> 144:ef7eb2e8f9f7 876 #define _USART_IFC_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */
<> 144:ef7eb2e8f9f7 877 #define _USART_IFC_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */
<> 144:ef7eb2e8f9f7 878 #define _USART_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
<> 144:ef7eb2e8f9f7 879 #define USART_IFC_TXOF_DEFAULT (_USART_IFC_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IFC */
<> 144:ef7eb2e8f9f7 880 #define USART_IFC_TXUF (0x1UL << 7) /**< Clear TX Underflow Interrupt Flag */
<> 144:ef7eb2e8f9f7 881 #define _USART_IFC_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */
<> 144:ef7eb2e8f9f7 882 #define _USART_IFC_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */
<> 144:ef7eb2e8f9f7 883 #define _USART_IFC_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
<> 144:ef7eb2e8f9f7 884 #define USART_IFC_TXUF_DEFAULT (_USART_IFC_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IFC */
<> 144:ef7eb2e8f9f7 885 #define USART_IFC_PERR (0x1UL << 8) /**< Clear Parity Error Interrupt Flag */
<> 144:ef7eb2e8f9f7 886 #define _USART_IFC_PERR_SHIFT 8 /**< Shift value for USART_PERR */
<> 144:ef7eb2e8f9f7 887 #define _USART_IFC_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */
<> 144:ef7eb2e8f9f7 888 #define _USART_IFC_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
<> 144:ef7eb2e8f9f7 889 #define USART_IFC_PERR_DEFAULT (_USART_IFC_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IFC */
<> 144:ef7eb2e8f9f7 890 #define USART_IFC_FERR (0x1UL << 9) /**< Clear Framing Error Interrupt Flag */
<> 144:ef7eb2e8f9f7 891 #define _USART_IFC_FERR_SHIFT 9 /**< Shift value for USART_FERR */
<> 144:ef7eb2e8f9f7 892 #define _USART_IFC_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */
<> 144:ef7eb2e8f9f7 893 #define _USART_IFC_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
<> 144:ef7eb2e8f9f7 894 #define USART_IFC_FERR_DEFAULT (_USART_IFC_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IFC */
<> 144:ef7eb2e8f9f7 895 #define USART_IFC_MPAF (0x1UL << 10) /**< Clear Multi-Processor Address Frame Interrupt Flag */
<> 144:ef7eb2e8f9f7 896 #define _USART_IFC_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */
<> 144:ef7eb2e8f9f7 897 #define _USART_IFC_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */
<> 144:ef7eb2e8f9f7 898 #define _USART_IFC_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
<> 144:ef7eb2e8f9f7 899 #define USART_IFC_MPAF_DEFAULT (_USART_IFC_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IFC */
<> 144:ef7eb2e8f9f7 900 #define USART_IFC_SSM (0x1UL << 11) /**< Clear Slave-Select In Master Mode Interrupt Flag */
<> 144:ef7eb2e8f9f7 901 #define _USART_IFC_SSM_SHIFT 11 /**< Shift value for USART_SSM */
<> 144:ef7eb2e8f9f7 902 #define _USART_IFC_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */
<> 144:ef7eb2e8f9f7 903 #define _USART_IFC_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
<> 144:ef7eb2e8f9f7 904 #define USART_IFC_SSM_DEFAULT (_USART_IFC_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IFC */
<> 144:ef7eb2e8f9f7 905 #define USART_IFC_CCF (0x1UL << 12) /**< Clear Collision Check Fail Interrupt Flag */
<> 144:ef7eb2e8f9f7 906 #define _USART_IFC_CCF_SHIFT 12 /**< Shift value for USART_CCF */
<> 144:ef7eb2e8f9f7 907 #define _USART_IFC_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */
<> 144:ef7eb2e8f9f7 908 #define _USART_IFC_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
<> 144:ef7eb2e8f9f7 909 #define USART_IFC_CCF_DEFAULT (_USART_IFC_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IFC */
<> 144:ef7eb2e8f9f7 910
<> 144:ef7eb2e8f9f7 911 /* Bit fields for USART IEN */
<> 144:ef7eb2e8f9f7 912 #define _USART_IEN_RESETVALUE 0x00000000UL /**< Default value for USART_IEN */
<> 144:ef7eb2e8f9f7 913 #define _USART_IEN_MASK 0x00001FFFUL /**< Mask for USART_IEN */
<> 144:ef7eb2e8f9f7 914 #define USART_IEN_TXC (0x1UL << 0) /**< TX Complete Interrupt Enable */
<> 144:ef7eb2e8f9f7 915 #define _USART_IEN_TXC_SHIFT 0 /**< Shift value for USART_TXC */
<> 144:ef7eb2e8f9f7 916 #define _USART_IEN_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */
<> 144:ef7eb2e8f9f7 917 #define _USART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
<> 144:ef7eb2e8f9f7 918 #define USART_IEN_TXC_DEFAULT (_USART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IEN */
<> 144:ef7eb2e8f9f7 919 #define USART_IEN_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Enable */
<> 144:ef7eb2e8f9f7 920 #define _USART_IEN_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */
<> 144:ef7eb2e8f9f7 921 #define _USART_IEN_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */
<> 144:ef7eb2e8f9f7 922 #define _USART_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
<> 144:ef7eb2e8f9f7 923 #define USART_IEN_TXBL_DEFAULT (_USART_IEN_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IEN */
<> 144:ef7eb2e8f9f7 924 #define USART_IEN_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Enable */
<> 144:ef7eb2e8f9f7 925 #define _USART_IEN_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */
<> 144:ef7eb2e8f9f7 926 #define _USART_IEN_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */
<> 144:ef7eb2e8f9f7 927 #define _USART_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
<> 144:ef7eb2e8f9f7 928 #define USART_IEN_RXDATAV_DEFAULT (_USART_IEN_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IEN */
<> 144:ef7eb2e8f9f7 929 #define USART_IEN_RXFULL (0x1UL << 3) /**< RX Buffer Full Interrupt Enable */
<> 144:ef7eb2e8f9f7 930 #define _USART_IEN_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */
<> 144:ef7eb2e8f9f7 931 #define _USART_IEN_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */
<> 144:ef7eb2e8f9f7 932 #define _USART_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
<> 144:ef7eb2e8f9f7 933 #define USART_IEN_RXFULL_DEFAULT (_USART_IEN_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IEN */
<> 144:ef7eb2e8f9f7 934 #define USART_IEN_RXOF (0x1UL << 4) /**< RX Overflow Interrupt Enable */
<> 144:ef7eb2e8f9f7 935 #define _USART_IEN_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */
<> 144:ef7eb2e8f9f7 936 #define _USART_IEN_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */
<> 144:ef7eb2e8f9f7 937 #define _USART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
<> 144:ef7eb2e8f9f7 938 #define USART_IEN_RXOF_DEFAULT (_USART_IEN_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IEN */
<> 144:ef7eb2e8f9f7 939 #define USART_IEN_RXUF (0x1UL << 5) /**< RX Underflow Interrupt Enable */
<> 144:ef7eb2e8f9f7 940 #define _USART_IEN_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */
<> 144:ef7eb2e8f9f7 941 #define _USART_IEN_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */
<> 144:ef7eb2e8f9f7 942 #define _USART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
<> 144:ef7eb2e8f9f7 943 #define USART_IEN_RXUF_DEFAULT (_USART_IEN_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IEN */
<> 144:ef7eb2e8f9f7 944 #define USART_IEN_TXOF (0x1UL << 6) /**< TX Overflow Interrupt Enable */
<> 144:ef7eb2e8f9f7 945 #define _USART_IEN_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */
<> 144:ef7eb2e8f9f7 946 #define _USART_IEN_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */
<> 144:ef7eb2e8f9f7 947 #define _USART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
<> 144:ef7eb2e8f9f7 948 #define USART_IEN_TXOF_DEFAULT (_USART_IEN_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IEN */
<> 144:ef7eb2e8f9f7 949 #define USART_IEN_TXUF (0x1UL << 7) /**< TX Underflow Interrupt Enable */
<> 144:ef7eb2e8f9f7 950 #define _USART_IEN_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */
<> 144:ef7eb2e8f9f7 951 #define _USART_IEN_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */
<> 144:ef7eb2e8f9f7 952 #define _USART_IEN_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
<> 144:ef7eb2e8f9f7 953 #define USART_IEN_TXUF_DEFAULT (_USART_IEN_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IEN */
<> 144:ef7eb2e8f9f7 954 #define USART_IEN_PERR (0x1UL << 8) /**< Parity Error Interrupt Enable */
<> 144:ef7eb2e8f9f7 955 #define _USART_IEN_PERR_SHIFT 8 /**< Shift value for USART_PERR */
<> 144:ef7eb2e8f9f7 956 #define _USART_IEN_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */
<> 144:ef7eb2e8f9f7 957 #define _USART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
<> 144:ef7eb2e8f9f7 958 #define USART_IEN_PERR_DEFAULT (_USART_IEN_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IEN */
<> 144:ef7eb2e8f9f7 959 #define USART_IEN_FERR (0x1UL << 9) /**< Framing Error Interrupt Enable */
<> 144:ef7eb2e8f9f7 960 #define _USART_IEN_FERR_SHIFT 9 /**< Shift value for USART_FERR */
<> 144:ef7eb2e8f9f7 961 #define _USART_IEN_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */
<> 144:ef7eb2e8f9f7 962 #define _USART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
<> 144:ef7eb2e8f9f7 963 #define USART_IEN_FERR_DEFAULT (_USART_IEN_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IEN */
<> 144:ef7eb2e8f9f7 964 #define USART_IEN_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt Enable */
<> 144:ef7eb2e8f9f7 965 #define _USART_IEN_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */
<> 144:ef7eb2e8f9f7 966 #define _USART_IEN_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */
<> 144:ef7eb2e8f9f7 967 #define _USART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
<> 144:ef7eb2e8f9f7 968 #define USART_IEN_MPAF_DEFAULT (_USART_IEN_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IEN */
<> 144:ef7eb2e8f9f7 969 #define USART_IEN_SSM (0x1UL << 11) /**< Slave-Select In Master Mode Interrupt Enable */
<> 144:ef7eb2e8f9f7 970 #define _USART_IEN_SSM_SHIFT 11 /**< Shift value for USART_SSM */
<> 144:ef7eb2e8f9f7 971 #define _USART_IEN_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */
<> 144:ef7eb2e8f9f7 972 #define _USART_IEN_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
<> 144:ef7eb2e8f9f7 973 #define USART_IEN_SSM_DEFAULT (_USART_IEN_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IEN */
<> 144:ef7eb2e8f9f7 974 #define USART_IEN_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Enable */
<> 144:ef7eb2e8f9f7 975 #define _USART_IEN_CCF_SHIFT 12 /**< Shift value for USART_CCF */
<> 144:ef7eb2e8f9f7 976 #define _USART_IEN_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */
<> 144:ef7eb2e8f9f7 977 #define _USART_IEN_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
<> 144:ef7eb2e8f9f7 978 #define USART_IEN_CCF_DEFAULT (_USART_IEN_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IEN */
<> 144:ef7eb2e8f9f7 979
<> 144:ef7eb2e8f9f7 980 /* Bit fields for USART IRCTRL */
<> 144:ef7eb2e8f9f7 981 #define _USART_IRCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_IRCTRL */
<> 144:ef7eb2e8f9f7 982 #define _USART_IRCTRL_MASK 0x000000FFUL /**< Mask for USART_IRCTRL */
<> 144:ef7eb2e8f9f7 983 #define USART_IRCTRL_IREN (0x1UL << 0) /**< Enable IrDA Module */
<> 144:ef7eb2e8f9f7 984 #define _USART_IRCTRL_IREN_SHIFT 0 /**< Shift value for USART_IREN */
<> 144:ef7eb2e8f9f7 985 #define _USART_IRCTRL_IREN_MASK 0x1UL /**< Bit mask for USART_IREN */
<> 144:ef7eb2e8f9f7 986 #define _USART_IRCTRL_IREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */
<> 144:ef7eb2e8f9f7 987 #define USART_IRCTRL_IREN_DEFAULT (_USART_IRCTRL_IREN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IRCTRL */
<> 144:ef7eb2e8f9f7 988 #define _USART_IRCTRL_IRPW_SHIFT 1 /**< Shift value for USART_IRPW */
<> 144:ef7eb2e8f9f7 989 #define _USART_IRCTRL_IRPW_MASK 0x6UL /**< Bit mask for USART_IRPW */
<> 144:ef7eb2e8f9f7 990 #define _USART_IRCTRL_IRPW_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */
<> 144:ef7eb2e8f9f7 991 #define _USART_IRCTRL_IRPW_ONE 0x00000000UL /**< Mode ONE for USART_IRCTRL */
<> 144:ef7eb2e8f9f7 992 #define _USART_IRCTRL_IRPW_TWO 0x00000001UL /**< Mode TWO for USART_IRCTRL */
<> 144:ef7eb2e8f9f7 993 #define _USART_IRCTRL_IRPW_THREE 0x00000002UL /**< Mode THREE for USART_IRCTRL */
<> 144:ef7eb2e8f9f7 994 #define _USART_IRCTRL_IRPW_FOUR 0x00000003UL /**< Mode FOUR for USART_IRCTRL */
<> 144:ef7eb2e8f9f7 995 #define USART_IRCTRL_IRPW_DEFAULT (_USART_IRCTRL_IRPW_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IRCTRL */
<> 144:ef7eb2e8f9f7 996 #define USART_IRCTRL_IRPW_ONE (_USART_IRCTRL_IRPW_ONE << 1) /**< Shifted mode ONE for USART_IRCTRL */
<> 144:ef7eb2e8f9f7 997 #define USART_IRCTRL_IRPW_TWO (_USART_IRCTRL_IRPW_TWO << 1) /**< Shifted mode TWO for USART_IRCTRL */
<> 144:ef7eb2e8f9f7 998 #define USART_IRCTRL_IRPW_THREE (_USART_IRCTRL_IRPW_THREE << 1) /**< Shifted mode THREE for USART_IRCTRL */
<> 144:ef7eb2e8f9f7 999 #define USART_IRCTRL_IRPW_FOUR (_USART_IRCTRL_IRPW_FOUR << 1) /**< Shifted mode FOUR for USART_IRCTRL */
<> 144:ef7eb2e8f9f7 1000 #define USART_IRCTRL_IRFILT (0x1UL << 3) /**< IrDA RX Filter */
<> 144:ef7eb2e8f9f7 1001 #define _USART_IRCTRL_IRFILT_SHIFT 3 /**< Shift value for USART_IRFILT */
<> 144:ef7eb2e8f9f7 1002 #define _USART_IRCTRL_IRFILT_MASK 0x8UL /**< Bit mask for USART_IRFILT */
<> 144:ef7eb2e8f9f7 1003 #define _USART_IRCTRL_IRFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */
<> 144:ef7eb2e8f9f7 1004 #define USART_IRCTRL_IRFILT_DEFAULT (_USART_IRCTRL_IRFILT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IRCTRL */
<> 144:ef7eb2e8f9f7 1005 #define _USART_IRCTRL_IRPRSSEL_SHIFT 4 /**< Shift value for USART_IRPRSSEL */
<> 144:ef7eb2e8f9f7 1006 #define _USART_IRCTRL_IRPRSSEL_MASK 0x70UL /**< Bit mask for USART_IRPRSSEL */
<> 144:ef7eb2e8f9f7 1007 #define _USART_IRCTRL_IRPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */
<> 144:ef7eb2e8f9f7 1008 #define _USART_IRCTRL_IRPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_IRCTRL */
<> 144:ef7eb2e8f9f7 1009 #define _USART_IRCTRL_IRPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_IRCTRL */
<> 144:ef7eb2e8f9f7 1010 #define _USART_IRCTRL_IRPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_IRCTRL */
<> 144:ef7eb2e8f9f7 1011 #define _USART_IRCTRL_IRPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_IRCTRL */
<> 144:ef7eb2e8f9f7 1012 #define _USART_IRCTRL_IRPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_IRCTRL */
<> 144:ef7eb2e8f9f7 1013 #define _USART_IRCTRL_IRPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_IRCTRL */
<> 144:ef7eb2e8f9f7 1014 #define _USART_IRCTRL_IRPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_IRCTRL */
<> 144:ef7eb2e8f9f7 1015 #define _USART_IRCTRL_IRPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_IRCTRL */
<> 144:ef7eb2e8f9f7 1016 #define USART_IRCTRL_IRPRSSEL_DEFAULT (_USART_IRCTRL_IRPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IRCTRL */
<> 144:ef7eb2e8f9f7 1017 #define USART_IRCTRL_IRPRSSEL_PRSCH0 (_USART_IRCTRL_IRPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for USART_IRCTRL */
<> 144:ef7eb2e8f9f7 1018 #define USART_IRCTRL_IRPRSSEL_PRSCH1 (_USART_IRCTRL_IRPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for USART_IRCTRL */
<> 144:ef7eb2e8f9f7 1019 #define USART_IRCTRL_IRPRSSEL_PRSCH2 (_USART_IRCTRL_IRPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for USART_IRCTRL */
<> 144:ef7eb2e8f9f7 1020 #define USART_IRCTRL_IRPRSSEL_PRSCH3 (_USART_IRCTRL_IRPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for USART_IRCTRL */
<> 144:ef7eb2e8f9f7 1021 #define USART_IRCTRL_IRPRSSEL_PRSCH4 (_USART_IRCTRL_IRPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for USART_IRCTRL */
<> 144:ef7eb2e8f9f7 1022 #define USART_IRCTRL_IRPRSSEL_PRSCH5 (_USART_IRCTRL_IRPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for USART_IRCTRL */
<> 144:ef7eb2e8f9f7 1023 #define USART_IRCTRL_IRPRSSEL_PRSCH6 (_USART_IRCTRL_IRPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for USART_IRCTRL */
<> 144:ef7eb2e8f9f7 1024 #define USART_IRCTRL_IRPRSSEL_PRSCH7 (_USART_IRCTRL_IRPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for USART_IRCTRL */
<> 144:ef7eb2e8f9f7 1025 #define USART_IRCTRL_IRPRSEN (0x1UL << 7) /**< IrDA PRS Channel Enable */
<> 144:ef7eb2e8f9f7 1026 #define _USART_IRCTRL_IRPRSEN_SHIFT 7 /**< Shift value for USART_IRPRSEN */
<> 144:ef7eb2e8f9f7 1027 #define _USART_IRCTRL_IRPRSEN_MASK 0x80UL /**< Bit mask for USART_IRPRSEN */
<> 144:ef7eb2e8f9f7 1028 #define _USART_IRCTRL_IRPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */
<> 144:ef7eb2e8f9f7 1029 #define USART_IRCTRL_IRPRSEN_DEFAULT (_USART_IRCTRL_IRPRSEN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IRCTRL */
<> 144:ef7eb2e8f9f7 1030
<> 144:ef7eb2e8f9f7 1031 /* Bit fields for USART ROUTE */
<> 144:ef7eb2e8f9f7 1032 #define _USART_ROUTE_RESETVALUE 0x00000000UL /**< Default value for USART_ROUTE */
<> 144:ef7eb2e8f9f7 1033 #define _USART_ROUTE_MASK 0x0000070FUL /**< Mask for USART_ROUTE */
<> 144:ef7eb2e8f9f7 1034 #define USART_ROUTE_RXPEN (0x1UL << 0) /**< RX Pin Enable */
<> 144:ef7eb2e8f9f7 1035 #define _USART_ROUTE_RXPEN_SHIFT 0 /**< Shift value for USART_RXPEN */
<> 144:ef7eb2e8f9f7 1036 #define _USART_ROUTE_RXPEN_MASK 0x1UL /**< Bit mask for USART_RXPEN */
<> 144:ef7eb2e8f9f7 1037 #define _USART_ROUTE_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTE */
<> 144:ef7eb2e8f9f7 1038 #define USART_ROUTE_RXPEN_DEFAULT (_USART_ROUTE_RXPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_ROUTE */
<> 144:ef7eb2e8f9f7 1039 #define USART_ROUTE_TXPEN (0x1UL << 1) /**< TX Pin Enable */
<> 144:ef7eb2e8f9f7 1040 #define _USART_ROUTE_TXPEN_SHIFT 1 /**< Shift value for USART_TXPEN */
<> 144:ef7eb2e8f9f7 1041 #define _USART_ROUTE_TXPEN_MASK 0x2UL /**< Bit mask for USART_TXPEN */
<> 144:ef7eb2e8f9f7 1042 #define _USART_ROUTE_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTE */
<> 144:ef7eb2e8f9f7 1043 #define USART_ROUTE_TXPEN_DEFAULT (_USART_ROUTE_TXPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_ROUTE */
<> 144:ef7eb2e8f9f7 1044 #define USART_ROUTE_CSPEN (0x1UL << 2) /**< CS Pin Enable */
<> 144:ef7eb2e8f9f7 1045 #define _USART_ROUTE_CSPEN_SHIFT 2 /**< Shift value for USART_CSPEN */
<> 144:ef7eb2e8f9f7 1046 #define _USART_ROUTE_CSPEN_MASK 0x4UL /**< Bit mask for USART_CSPEN */
<> 144:ef7eb2e8f9f7 1047 #define _USART_ROUTE_CSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTE */
<> 144:ef7eb2e8f9f7 1048 #define USART_ROUTE_CSPEN_DEFAULT (_USART_ROUTE_CSPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_ROUTE */
<> 144:ef7eb2e8f9f7 1049 #define USART_ROUTE_CLKPEN (0x1UL << 3) /**< CLK Pin Enable */
<> 144:ef7eb2e8f9f7 1050 #define _USART_ROUTE_CLKPEN_SHIFT 3 /**< Shift value for USART_CLKPEN */
<> 144:ef7eb2e8f9f7 1051 #define _USART_ROUTE_CLKPEN_MASK 0x8UL /**< Bit mask for USART_CLKPEN */
<> 144:ef7eb2e8f9f7 1052 #define _USART_ROUTE_CLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTE */
<> 144:ef7eb2e8f9f7 1053 #define USART_ROUTE_CLKPEN_DEFAULT (_USART_ROUTE_CLKPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_ROUTE */
<> 144:ef7eb2e8f9f7 1054 #define _USART_ROUTE_LOCATION_SHIFT 8 /**< Shift value for USART_LOCATION */
<> 144:ef7eb2e8f9f7 1055 #define _USART_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for USART_LOCATION */
<> 144:ef7eb2e8f9f7 1056 #define _USART_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTE */
<> 144:ef7eb2e8f9f7 1057 #define _USART_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTE */
<> 144:ef7eb2e8f9f7 1058 #define _USART_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTE */
<> 144:ef7eb2e8f9f7 1059 #define _USART_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTE */
<> 144:ef7eb2e8f9f7 1060 #define _USART_ROUTE_LOCATION_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTE */
<> 144:ef7eb2e8f9f7 1061 #define _USART_ROUTE_LOCATION_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTE */
<> 144:ef7eb2e8f9f7 1062 #define _USART_ROUTE_LOCATION_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTE */
<> 144:ef7eb2e8f9f7 1063 #define USART_ROUTE_LOCATION_LOC0 (_USART_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for USART_ROUTE */
<> 144:ef7eb2e8f9f7 1064 #define USART_ROUTE_LOCATION_DEFAULT (_USART_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_ROUTE */
<> 144:ef7eb2e8f9f7 1065 #define USART_ROUTE_LOCATION_LOC1 (_USART_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for USART_ROUTE */
<> 144:ef7eb2e8f9f7 1066 #define USART_ROUTE_LOCATION_LOC2 (_USART_ROUTE_LOCATION_LOC2 << 8) /**< Shifted mode LOC2 for USART_ROUTE */
<> 144:ef7eb2e8f9f7 1067 #define USART_ROUTE_LOCATION_LOC3 (_USART_ROUTE_LOCATION_LOC3 << 8) /**< Shifted mode LOC3 for USART_ROUTE */
<> 144:ef7eb2e8f9f7 1068 #define USART_ROUTE_LOCATION_LOC4 (_USART_ROUTE_LOCATION_LOC4 << 8) /**< Shifted mode LOC4 for USART_ROUTE */
<> 144:ef7eb2e8f9f7 1069 #define USART_ROUTE_LOCATION_LOC5 (_USART_ROUTE_LOCATION_LOC5 << 8) /**< Shifted mode LOC5 for USART_ROUTE */
<> 144:ef7eb2e8f9f7 1070
<> 144:ef7eb2e8f9f7 1071 /* Bit fields for USART INPUT */
<> 144:ef7eb2e8f9f7 1072 #define _USART_INPUT_RESETVALUE 0x00000000UL /**< Default value for USART_INPUT */
<> 144:ef7eb2e8f9f7 1073 #define _USART_INPUT_MASK 0x0000001FUL /**< Mask for USART_INPUT */
<> 144:ef7eb2e8f9f7 1074 #define _USART_INPUT_RXPRSSEL_SHIFT 0 /**< Shift value for USART_RXPRSSEL */
<> 144:ef7eb2e8f9f7 1075 #define _USART_INPUT_RXPRSSEL_MASK 0xFUL /**< Bit mask for USART_RXPRSSEL */
<> 144:ef7eb2e8f9f7 1076 #define _USART_INPUT_RXPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */
<> 144:ef7eb2e8f9f7 1077 #define _USART_INPUT_RXPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_INPUT */
<> 144:ef7eb2e8f9f7 1078 #define _USART_INPUT_RXPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_INPUT */
<> 144:ef7eb2e8f9f7 1079 #define _USART_INPUT_RXPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_INPUT */
<> 144:ef7eb2e8f9f7 1080 #define _USART_INPUT_RXPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_INPUT */
<> 144:ef7eb2e8f9f7 1081 #define _USART_INPUT_RXPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_INPUT */
<> 144:ef7eb2e8f9f7 1082 #define _USART_INPUT_RXPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_INPUT */
<> 144:ef7eb2e8f9f7 1083 #define _USART_INPUT_RXPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_INPUT */
<> 144:ef7eb2e8f9f7 1084 #define _USART_INPUT_RXPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_INPUT */
<> 144:ef7eb2e8f9f7 1085 #define _USART_INPUT_RXPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_INPUT */
<> 144:ef7eb2e8f9f7 1086 #define _USART_INPUT_RXPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_INPUT */
<> 144:ef7eb2e8f9f7 1087 #define _USART_INPUT_RXPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_INPUT */
<> 144:ef7eb2e8f9f7 1088 #define _USART_INPUT_RXPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_INPUT */
<> 144:ef7eb2e8f9f7 1089 #define USART_INPUT_RXPRSSEL_DEFAULT (_USART_INPUT_RXPRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_INPUT */
<> 144:ef7eb2e8f9f7 1090 #define USART_INPUT_RXPRSSEL_PRSCH0 (_USART_INPUT_RXPRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for USART_INPUT */
<> 144:ef7eb2e8f9f7 1091 #define USART_INPUT_RXPRSSEL_PRSCH1 (_USART_INPUT_RXPRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for USART_INPUT */
<> 144:ef7eb2e8f9f7 1092 #define USART_INPUT_RXPRSSEL_PRSCH2 (_USART_INPUT_RXPRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for USART_INPUT */
<> 144:ef7eb2e8f9f7 1093 #define USART_INPUT_RXPRSSEL_PRSCH3 (_USART_INPUT_RXPRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for USART_INPUT */
<> 144:ef7eb2e8f9f7 1094 #define USART_INPUT_RXPRSSEL_PRSCH4 (_USART_INPUT_RXPRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for USART_INPUT */
<> 144:ef7eb2e8f9f7 1095 #define USART_INPUT_RXPRSSEL_PRSCH5 (_USART_INPUT_RXPRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for USART_INPUT */
<> 144:ef7eb2e8f9f7 1096 #define USART_INPUT_RXPRSSEL_PRSCH6 (_USART_INPUT_RXPRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for USART_INPUT */
<> 144:ef7eb2e8f9f7 1097 #define USART_INPUT_RXPRSSEL_PRSCH7 (_USART_INPUT_RXPRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for USART_INPUT */
<> 144:ef7eb2e8f9f7 1098 #define USART_INPUT_RXPRSSEL_PRSCH8 (_USART_INPUT_RXPRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for USART_INPUT */
<> 144:ef7eb2e8f9f7 1099 #define USART_INPUT_RXPRSSEL_PRSCH9 (_USART_INPUT_RXPRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for USART_INPUT */
<> 144:ef7eb2e8f9f7 1100 #define USART_INPUT_RXPRSSEL_PRSCH10 (_USART_INPUT_RXPRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for USART_INPUT */
<> 144:ef7eb2e8f9f7 1101 #define USART_INPUT_RXPRSSEL_PRSCH11 (_USART_INPUT_RXPRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for USART_INPUT */
<> 144:ef7eb2e8f9f7 1102 #define USART_INPUT_RXPRS (0x1UL << 4) /**< PRS RX Enable */
<> 144:ef7eb2e8f9f7 1103 #define _USART_INPUT_RXPRS_SHIFT 4 /**< Shift value for USART_RXPRS */
<> 144:ef7eb2e8f9f7 1104 #define _USART_INPUT_RXPRS_MASK 0x10UL /**< Bit mask for USART_RXPRS */
<> 144:ef7eb2e8f9f7 1105 #define _USART_INPUT_RXPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */
<> 144:ef7eb2e8f9f7 1106 #define USART_INPUT_RXPRS_DEFAULT (_USART_INPUT_RXPRS_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_INPUT */
<> 144:ef7eb2e8f9f7 1107
<> 144:ef7eb2e8f9f7 1108 /* Bit fields for USART I2SCTRL */
<> 144:ef7eb2e8f9f7 1109 #define _USART_I2SCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_I2SCTRL */
<> 144:ef7eb2e8f9f7 1110 #define _USART_I2SCTRL_MASK 0x0000071FUL /**< Mask for USART_I2SCTRL */
<> 144:ef7eb2e8f9f7 1111 #define USART_I2SCTRL_EN (0x1UL << 0) /**< Enable I2S Mode */
<> 144:ef7eb2e8f9f7 1112 #define _USART_I2SCTRL_EN_SHIFT 0 /**< Shift value for USART_EN */
<> 144:ef7eb2e8f9f7 1113 #define _USART_I2SCTRL_EN_MASK 0x1UL /**< Bit mask for USART_EN */
<> 144:ef7eb2e8f9f7 1114 #define _USART_I2SCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */
<> 144:ef7eb2e8f9f7 1115 #define USART_I2SCTRL_EN_DEFAULT (_USART_I2SCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_I2SCTRL */
<> 144:ef7eb2e8f9f7 1116 #define USART_I2SCTRL_MONO (0x1UL << 1) /**< Stero or Mono */
<> 144:ef7eb2e8f9f7 1117 #define _USART_I2SCTRL_MONO_SHIFT 1 /**< Shift value for USART_MONO */
<> 144:ef7eb2e8f9f7 1118 #define _USART_I2SCTRL_MONO_MASK 0x2UL /**< Bit mask for USART_MONO */
<> 144:ef7eb2e8f9f7 1119 #define _USART_I2SCTRL_MONO_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */
<> 144:ef7eb2e8f9f7 1120 #define USART_I2SCTRL_MONO_DEFAULT (_USART_I2SCTRL_MONO_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_I2SCTRL */
<> 144:ef7eb2e8f9f7 1121 #define USART_I2SCTRL_JUSTIFY (0x1UL << 2) /**< Justification of I2S Data */
<> 144:ef7eb2e8f9f7 1122 #define _USART_I2SCTRL_JUSTIFY_SHIFT 2 /**< Shift value for USART_JUSTIFY */
<> 144:ef7eb2e8f9f7 1123 #define _USART_I2SCTRL_JUSTIFY_MASK 0x4UL /**< Bit mask for USART_JUSTIFY */
<> 144:ef7eb2e8f9f7 1124 #define _USART_I2SCTRL_JUSTIFY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */
<> 144:ef7eb2e8f9f7 1125 #define _USART_I2SCTRL_JUSTIFY_LEFT 0x00000000UL /**< Mode LEFT for USART_I2SCTRL */
<> 144:ef7eb2e8f9f7 1126 #define _USART_I2SCTRL_JUSTIFY_RIGHT 0x00000001UL /**< Mode RIGHT for USART_I2SCTRL */
<> 144:ef7eb2e8f9f7 1127 #define USART_I2SCTRL_JUSTIFY_DEFAULT (_USART_I2SCTRL_JUSTIFY_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_I2SCTRL */
<> 144:ef7eb2e8f9f7 1128 #define USART_I2SCTRL_JUSTIFY_LEFT (_USART_I2SCTRL_JUSTIFY_LEFT << 2) /**< Shifted mode LEFT for USART_I2SCTRL */
<> 144:ef7eb2e8f9f7 1129 #define USART_I2SCTRL_JUSTIFY_RIGHT (_USART_I2SCTRL_JUSTIFY_RIGHT << 2) /**< Shifted mode RIGHT for USART_I2SCTRL */
<> 144:ef7eb2e8f9f7 1130 #define USART_I2SCTRL_DMASPLIT (0x1UL << 3) /**< Separate DMA Request For Left/Right Data */
<> 144:ef7eb2e8f9f7 1131 #define _USART_I2SCTRL_DMASPLIT_SHIFT 3 /**< Shift value for USART_DMASPLIT */
<> 144:ef7eb2e8f9f7 1132 #define _USART_I2SCTRL_DMASPLIT_MASK 0x8UL /**< Bit mask for USART_DMASPLIT */
<> 144:ef7eb2e8f9f7 1133 #define _USART_I2SCTRL_DMASPLIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */
<> 144:ef7eb2e8f9f7 1134 #define USART_I2SCTRL_DMASPLIT_DEFAULT (_USART_I2SCTRL_DMASPLIT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_I2SCTRL */
<> 144:ef7eb2e8f9f7 1135 #define USART_I2SCTRL_DELAY (0x1UL << 4) /**< Delay on I2S data */
<> 144:ef7eb2e8f9f7 1136 #define _USART_I2SCTRL_DELAY_SHIFT 4 /**< Shift value for USART_DELAY */
<> 144:ef7eb2e8f9f7 1137 #define _USART_I2SCTRL_DELAY_MASK 0x10UL /**< Bit mask for USART_DELAY */
<> 144:ef7eb2e8f9f7 1138 #define _USART_I2SCTRL_DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */
<> 144:ef7eb2e8f9f7 1139 #define USART_I2SCTRL_DELAY_DEFAULT (_USART_I2SCTRL_DELAY_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_I2SCTRL */
<> 144:ef7eb2e8f9f7 1140 #define _USART_I2SCTRL_FORMAT_SHIFT 8 /**< Shift value for USART_FORMAT */
<> 144:ef7eb2e8f9f7 1141 #define _USART_I2SCTRL_FORMAT_MASK 0x700UL /**< Bit mask for USART_FORMAT */
<> 144:ef7eb2e8f9f7 1142 #define _USART_I2SCTRL_FORMAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */
<> 144:ef7eb2e8f9f7 1143 #define _USART_I2SCTRL_FORMAT_W32D32 0x00000000UL /**< Mode W32D32 for USART_I2SCTRL */
<> 144:ef7eb2e8f9f7 1144 #define _USART_I2SCTRL_FORMAT_W32D24M 0x00000001UL /**< Mode W32D24M for USART_I2SCTRL */
<> 144:ef7eb2e8f9f7 1145 #define _USART_I2SCTRL_FORMAT_W32D24 0x00000002UL /**< Mode W32D24 for USART_I2SCTRL */
<> 144:ef7eb2e8f9f7 1146 #define _USART_I2SCTRL_FORMAT_W32D16 0x00000003UL /**< Mode W32D16 for USART_I2SCTRL */
<> 144:ef7eb2e8f9f7 1147 #define _USART_I2SCTRL_FORMAT_W32D8 0x00000004UL /**< Mode W32D8 for USART_I2SCTRL */
<> 144:ef7eb2e8f9f7 1148 #define _USART_I2SCTRL_FORMAT_W16D16 0x00000005UL /**< Mode W16D16 for USART_I2SCTRL */
<> 144:ef7eb2e8f9f7 1149 #define _USART_I2SCTRL_FORMAT_W16D8 0x00000006UL /**< Mode W16D8 for USART_I2SCTRL */
<> 144:ef7eb2e8f9f7 1150 #define _USART_I2SCTRL_FORMAT_W8D8 0x00000007UL /**< Mode W8D8 for USART_I2SCTRL */
<> 144:ef7eb2e8f9f7 1151 #define USART_I2SCTRL_FORMAT_DEFAULT (_USART_I2SCTRL_FORMAT_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_I2SCTRL */
<> 144:ef7eb2e8f9f7 1152 #define USART_I2SCTRL_FORMAT_W32D32 (_USART_I2SCTRL_FORMAT_W32D32 << 8) /**< Shifted mode W32D32 for USART_I2SCTRL */
<> 144:ef7eb2e8f9f7 1153 #define USART_I2SCTRL_FORMAT_W32D24M (_USART_I2SCTRL_FORMAT_W32D24M << 8) /**< Shifted mode W32D24M for USART_I2SCTRL */
<> 144:ef7eb2e8f9f7 1154 #define USART_I2SCTRL_FORMAT_W32D24 (_USART_I2SCTRL_FORMAT_W32D24 << 8) /**< Shifted mode W32D24 for USART_I2SCTRL */
<> 144:ef7eb2e8f9f7 1155 #define USART_I2SCTRL_FORMAT_W32D16 (_USART_I2SCTRL_FORMAT_W32D16 << 8) /**< Shifted mode W32D16 for USART_I2SCTRL */
<> 144:ef7eb2e8f9f7 1156 #define USART_I2SCTRL_FORMAT_W32D8 (_USART_I2SCTRL_FORMAT_W32D8 << 8) /**< Shifted mode W32D8 for USART_I2SCTRL */
<> 144:ef7eb2e8f9f7 1157 #define USART_I2SCTRL_FORMAT_W16D16 (_USART_I2SCTRL_FORMAT_W16D16 << 8) /**< Shifted mode W16D16 for USART_I2SCTRL */
<> 144:ef7eb2e8f9f7 1158 #define USART_I2SCTRL_FORMAT_W16D8 (_USART_I2SCTRL_FORMAT_W16D8 << 8) /**< Shifted mode W16D8 for USART_I2SCTRL */
<> 144:ef7eb2e8f9f7 1159 #define USART_I2SCTRL_FORMAT_W8D8 (_USART_I2SCTRL_FORMAT_W8D8 << 8) /**< Shifted mode W8D8 for USART_I2SCTRL */
<> 144:ef7eb2e8f9f7 1160
<> 144:ef7eb2e8f9f7 1161 /** @} End of group EFM32LG_USART */
<> 144:ef7eb2e8f9f7 1162 /** @} End of group Parts */
<> 144:ef7eb2e8f9f7 1163