Fawwaz Nadzmy / mbed-STM

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targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/TOOLCHAIN_GCC_ARM/startup_stm32f100xb.S@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
124:6a4a5b7d7324 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 *************** (C) COPYRIGHT 2016 STMicroelectronics ************************
<> 144:ef7eb2e8f9f7 3 * @file startup_stm32f100xb.s
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V4.1.0
<> 144:ef7eb2e8f9f7 6 * @date 29-April-2016
<> 144:ef7eb2e8f9f7 7 * @brief STM32F100xB Devices vector table for Atollic toolchain.
<> 144:ef7eb2e8f9f7 8 * This module performs:
<> 144:ef7eb2e8f9f7 9 * - Set the initial SP
<> 144:ef7eb2e8f9f7 10 * - Set the initial PC == Reset_Handler,
<> 144:ef7eb2e8f9f7 11 * - Set the vector table entries with the exceptions ISR address
<> 144:ef7eb2e8f9f7 12 * - Configure the clock system
<> 144:ef7eb2e8f9f7 13 * - Branches to main in the C library (which eventually
<> 144:ef7eb2e8f9f7 14 * calls main()).
<> 144:ef7eb2e8f9f7 15 * After Reset the Cortex-M3 processor is in Thread mode,
<> 144:ef7eb2e8f9f7 16 * priority is Privileged, and the Stack is set to Main.
<> 144:ef7eb2e8f9f7 17 ******************************************************************************
<> 144:ef7eb2e8f9f7 18 *
<> 144:ef7eb2e8f9f7 19 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 20 *
<> 144:ef7eb2e8f9f7 21 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 22 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 23 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 24 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 25 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 26 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 27 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 28 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 29 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 30 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 31 *
<> 144:ef7eb2e8f9f7 32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 33 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 35 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 38 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 39 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 40 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 42 *
<> 144:ef7eb2e8f9f7 43 ******************************************************************************
<> 144:ef7eb2e8f9f7 44 */
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 .syntax unified
<> 144:ef7eb2e8f9f7 47 .cpu cortex-m3
<> 144:ef7eb2e8f9f7 48 .fpu softvfp
<> 144:ef7eb2e8f9f7 49 .thumb
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 .global g_pfnVectors
<> 144:ef7eb2e8f9f7 52 .global Default_Handler
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 /* start address for the initialization values of the .data section.
<> 144:ef7eb2e8f9f7 55 defined in linker script */
<> 144:ef7eb2e8f9f7 56 .word _sidata
<> 144:ef7eb2e8f9f7 57 /* start address for the .data section. defined in linker script */
<> 144:ef7eb2e8f9f7 58 .word _sdata
<> 144:ef7eb2e8f9f7 59 /* end address for the .data section. defined in linker script */
<> 144:ef7eb2e8f9f7 60 .word _edata
<> 144:ef7eb2e8f9f7 61 /* start address for the .bss section. defined in linker script */
<> 144:ef7eb2e8f9f7 62 .word _sbss
<> 144:ef7eb2e8f9f7 63 /* end address for the .bss section. defined in linker script */
<> 144:ef7eb2e8f9f7 64 .word _ebss
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 .equ BootRAM, 0xF108F85F
<> 144:ef7eb2e8f9f7 67 /**
<> 144:ef7eb2e8f9f7 68 * @brief This is the code that gets called when the processor first
<> 144:ef7eb2e8f9f7 69 * starts execution following a reset event. Only the absolutely
<> 144:ef7eb2e8f9f7 70 * necessary set is performed, after which the application
<> 144:ef7eb2e8f9f7 71 * supplied main() routine is called.
<> 144:ef7eb2e8f9f7 72 * @param None
<> 144:ef7eb2e8f9f7 73 * @retval : None
<> 144:ef7eb2e8f9f7 74 */
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 .section .text.Reset_Handler
<> 144:ef7eb2e8f9f7 77 .weak Reset_Handler
<> 144:ef7eb2e8f9f7 78 .type Reset_Handler, %function
<> 144:ef7eb2e8f9f7 79 Reset_Handler:
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 /* Copy the data segment initializers from flash to SRAM */
<> 144:ef7eb2e8f9f7 82 movs r1, #0
<> 144:ef7eb2e8f9f7 83 b LoopCopyDataInit
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 CopyDataInit:
<> 144:ef7eb2e8f9f7 86 ldr r3, =_sidata
<> 144:ef7eb2e8f9f7 87 ldr r3, [r3, r1]
<> 144:ef7eb2e8f9f7 88 str r3, [r0, r1]
<> 144:ef7eb2e8f9f7 89 adds r1, r1, #4
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 LoopCopyDataInit:
<> 144:ef7eb2e8f9f7 92 ldr r0, =_sdata
<> 144:ef7eb2e8f9f7 93 ldr r3, =_edata
<> 144:ef7eb2e8f9f7 94 adds r2, r0, r1
<> 144:ef7eb2e8f9f7 95 cmp r2, r3
<> 144:ef7eb2e8f9f7 96 bcc CopyDataInit
<> 144:ef7eb2e8f9f7 97 ldr r2, =_sbss
<> 144:ef7eb2e8f9f7 98 b LoopFillZerobss
<> 144:ef7eb2e8f9f7 99 /* Zero fill the bss segment. */
<> 144:ef7eb2e8f9f7 100 FillZerobss:
<> 144:ef7eb2e8f9f7 101 movs r3, #0
<> 144:ef7eb2e8f9f7 102 str r3, [r2], #4
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104 LoopFillZerobss:
<> 144:ef7eb2e8f9f7 105 ldr r3, = _ebss
<> 144:ef7eb2e8f9f7 106 cmp r2, r3
<> 144:ef7eb2e8f9f7 107 bcc FillZerobss
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 /* Call the clock system intitialization function.*/
<> 144:ef7eb2e8f9f7 110 bl SystemInit
<> 144:ef7eb2e8f9f7 111 /* Call static constructors */
<> 144:ef7eb2e8f9f7 112 /* bl __libc_init_array */
<> 144:ef7eb2e8f9f7 113 /* Call the application's entry point.*/
<> 144:ef7eb2e8f9f7 114 /* bl main */
<> 144:ef7eb2e8f9f7 115 bl _start
<> 144:ef7eb2e8f9f7 116 bx lr
<> 144:ef7eb2e8f9f7 117 .size Reset_Handler, .-Reset_Handler
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 /**
<> 144:ef7eb2e8f9f7 120 * @brief This is the code that gets called when the processor receives an
<> 144:ef7eb2e8f9f7 121 * unexpected interrupt. This simply enters an infinite loop, preserving
<> 144:ef7eb2e8f9f7 122 * the system state for examination by a debugger.
<> 144:ef7eb2e8f9f7 123 *
<> 144:ef7eb2e8f9f7 124 * @param None
<> 144:ef7eb2e8f9f7 125 * @retval : None
<> 144:ef7eb2e8f9f7 126 */
<> 144:ef7eb2e8f9f7 127 .section .text.Default_Handler,"ax",%progbits
<> 144:ef7eb2e8f9f7 128 Default_Handler:
<> 144:ef7eb2e8f9f7 129 Infinite_Loop:
<> 144:ef7eb2e8f9f7 130 b Infinite_Loop
<> 144:ef7eb2e8f9f7 131 .size Default_Handler, .-Default_Handler
<> 144:ef7eb2e8f9f7 132 /******************************************************************************
<> 144:ef7eb2e8f9f7 133 *
<> 144:ef7eb2e8f9f7 134 * The minimal vector table for a Cortex M3. Note that the proper constructs
<> 144:ef7eb2e8f9f7 135 * must be placed on this to ensure that it ends up at physical address
<> 144:ef7eb2e8f9f7 136 * 0x0000.0000.
<> 144:ef7eb2e8f9f7 137 *
<> 144:ef7eb2e8f9f7 138 ******************************************************************************/
<> 144:ef7eb2e8f9f7 139 .section .isr_vector,"a",%progbits
<> 144:ef7eb2e8f9f7 140 .type g_pfnVectors, %object
<> 144:ef7eb2e8f9f7 141 .size g_pfnVectors, .-g_pfnVectors
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 g_pfnVectors:
<> 144:ef7eb2e8f9f7 145 .word _estack
<> 144:ef7eb2e8f9f7 146 .word Reset_Handler
<> 144:ef7eb2e8f9f7 147 .word NMI_Handler
<> 144:ef7eb2e8f9f7 148 .word HardFault_Handler
<> 144:ef7eb2e8f9f7 149 .word MemManage_Handler
<> 144:ef7eb2e8f9f7 150 .word BusFault_Handler
<> 144:ef7eb2e8f9f7 151 .word UsageFault_Handler
<> 144:ef7eb2e8f9f7 152 .word 0
<> 144:ef7eb2e8f9f7 153 .word 0
<> 144:ef7eb2e8f9f7 154 .word 0
<> 144:ef7eb2e8f9f7 155 .word 0
<> 144:ef7eb2e8f9f7 156 .word SVC_Handler
<> 144:ef7eb2e8f9f7 157 .word DebugMon_Handler
<> 144:ef7eb2e8f9f7 158 .word 0
<> 144:ef7eb2e8f9f7 159 .word PendSV_Handler
<> 144:ef7eb2e8f9f7 160 .word SysTick_Handler
<> 144:ef7eb2e8f9f7 161 .word WWDG_IRQHandler
<> 144:ef7eb2e8f9f7 162 .word PVD_IRQHandler
<> 144:ef7eb2e8f9f7 163 .word TAMPER_IRQHandler
<> 144:ef7eb2e8f9f7 164 .word RTC_IRQHandler
<> 144:ef7eb2e8f9f7 165 .word FLASH_IRQHandler
<> 144:ef7eb2e8f9f7 166 .word RCC_IRQHandler
<> 144:ef7eb2e8f9f7 167 .word EXTI0_IRQHandler
<> 144:ef7eb2e8f9f7 168 .word EXTI1_IRQHandler
<> 144:ef7eb2e8f9f7 169 .word EXTI2_IRQHandler
<> 144:ef7eb2e8f9f7 170 .word EXTI3_IRQHandler
<> 144:ef7eb2e8f9f7 171 .word EXTI4_IRQHandler
<> 144:ef7eb2e8f9f7 172 .word DMA1_Channel1_IRQHandler
<> 144:ef7eb2e8f9f7 173 .word DMA1_Channel2_IRQHandler
<> 144:ef7eb2e8f9f7 174 .word DMA1_Channel3_IRQHandler
<> 144:ef7eb2e8f9f7 175 .word DMA1_Channel4_IRQHandler
<> 144:ef7eb2e8f9f7 176 .word DMA1_Channel5_IRQHandler
<> 144:ef7eb2e8f9f7 177 .word DMA1_Channel6_IRQHandler
<> 144:ef7eb2e8f9f7 178 .word DMA1_Channel7_IRQHandler
<> 144:ef7eb2e8f9f7 179 .word ADC1_IRQHandler
<> 144:ef7eb2e8f9f7 180 .word 0
<> 144:ef7eb2e8f9f7 181 .word 0
<> 144:ef7eb2e8f9f7 182 .word 0
<> 144:ef7eb2e8f9f7 183 .word 0
<> 144:ef7eb2e8f9f7 184 .word EXTI9_5_IRQHandler
<> 144:ef7eb2e8f9f7 185 .word TIM1_BRK_TIM15_IRQHandler
<> 144:ef7eb2e8f9f7 186 .word TIM1_UP_TIM16_IRQHandler
<> 144:ef7eb2e8f9f7 187 .word TIM1_TRG_COM_TIM17_IRQHandler
<> 144:ef7eb2e8f9f7 188 .word TIM1_CC_IRQHandler
<> 144:ef7eb2e8f9f7 189 .word TIM2_IRQHandler
<> 144:ef7eb2e8f9f7 190 .word TIM3_IRQHandler
<> 144:ef7eb2e8f9f7 191 .word TIM4_IRQHandler
<> 144:ef7eb2e8f9f7 192 .word I2C1_EV_IRQHandler
<> 144:ef7eb2e8f9f7 193 .word I2C1_ER_IRQHandler
<> 144:ef7eb2e8f9f7 194 .word I2C2_EV_IRQHandler
<> 144:ef7eb2e8f9f7 195 .word I2C2_ER_IRQHandler
<> 144:ef7eb2e8f9f7 196 .word SPI1_IRQHandler
<> 144:ef7eb2e8f9f7 197 .word SPI2_IRQHandler
<> 144:ef7eb2e8f9f7 198 .word USART1_IRQHandler
<> 144:ef7eb2e8f9f7 199 .word USART2_IRQHandler
<> 144:ef7eb2e8f9f7 200 .word USART3_IRQHandler
<> 144:ef7eb2e8f9f7 201 .word EXTI15_10_IRQHandler
<> 144:ef7eb2e8f9f7 202 .word RTC_Alarm_IRQHandler
<> 144:ef7eb2e8f9f7 203 .word CEC_IRQHandler
<> 144:ef7eb2e8f9f7 204 .word 0
<> 144:ef7eb2e8f9f7 205 .word 0
<> 144:ef7eb2e8f9f7 206 .word 0
<> 144:ef7eb2e8f9f7 207 .word 0
<> 144:ef7eb2e8f9f7 208 .word 0
<> 144:ef7eb2e8f9f7 209 .word 0
<> 144:ef7eb2e8f9f7 210 .word 0
<> 144:ef7eb2e8f9f7 211 .word 0
<> 144:ef7eb2e8f9f7 212 .word 0
<> 144:ef7eb2e8f9f7 213 .word 0
<> 144:ef7eb2e8f9f7 214 .word 0
<> 144:ef7eb2e8f9f7 215 .word TIM6_DAC_IRQHandler
<> 144:ef7eb2e8f9f7 216 .word TIM7_IRQHandler
<> 144:ef7eb2e8f9f7 217 .word 0
<> 144:ef7eb2e8f9f7 218 .word 0
<> 144:ef7eb2e8f9f7 219 .word 0
<> 144:ef7eb2e8f9f7 220 .word 0
<> 144:ef7eb2e8f9f7 221 .word 0
<> 144:ef7eb2e8f9f7 222 .word 0
<> 144:ef7eb2e8f9f7 223 .word 0
<> 144:ef7eb2e8f9f7 224 .word 0
<> 144:ef7eb2e8f9f7 225 .word 0
<> 144:ef7eb2e8f9f7 226 .word 0
<> 144:ef7eb2e8f9f7 227 .word 0
<> 144:ef7eb2e8f9f7 228 .word 0
<> 144:ef7eb2e8f9f7 229 .word 0
<> 144:ef7eb2e8f9f7 230 .word 0
<> 144:ef7eb2e8f9f7 231 .word 0
<> 144:ef7eb2e8f9f7 232 .word 0
<> 144:ef7eb2e8f9f7 233 .word 0
<> 144:ef7eb2e8f9f7 234 .word 0
<> 144:ef7eb2e8f9f7 235 .word 0
<> 144:ef7eb2e8f9f7 236 .word 0
<> 144:ef7eb2e8f9f7 237 .word 0
<> 144:ef7eb2e8f9f7 238 .word 0
<> 144:ef7eb2e8f9f7 239 .word 0
<> 144:ef7eb2e8f9f7 240 .word 0
<> 144:ef7eb2e8f9f7 241 .word 0
<> 144:ef7eb2e8f9f7 242 .word 0
<> 144:ef7eb2e8f9f7 243 .word 0
<> 144:ef7eb2e8f9f7 244 .word 0
<> 144:ef7eb2e8f9f7 245 .word 0
<> 144:ef7eb2e8f9f7 246 .word 0
<> 144:ef7eb2e8f9f7 247 .word 0
<> 144:ef7eb2e8f9f7 248 .word 0
<> 144:ef7eb2e8f9f7 249 .word 0
<> 144:ef7eb2e8f9f7 250 .word 0
<> 144:ef7eb2e8f9f7 251 .word 0
<> 144:ef7eb2e8f9f7 252 .word 0
<> 144:ef7eb2e8f9f7 253 .word 0
<> 144:ef7eb2e8f9f7 254 .word 0
<> 144:ef7eb2e8f9f7 255 .word 0
<> 144:ef7eb2e8f9f7 256 .word 0
<> 144:ef7eb2e8f9f7 257 .word 0
<> 144:ef7eb2e8f9f7 258 .word 0
<> 144:ef7eb2e8f9f7 259 .word 0
<> 144:ef7eb2e8f9f7 260 .word BootRAM /* @0x01CC. This is for boot in RAM mode for
<> 144:ef7eb2e8f9f7 261 STM32F10xB Value Line devices. */
<> 144:ef7eb2e8f9f7 262
<> 144:ef7eb2e8f9f7 263 /*******************************************************************************
<> 144:ef7eb2e8f9f7 264 *
<> 144:ef7eb2e8f9f7 265 * Provide weak aliases for each Exception handler to the Default_Handler.
<> 144:ef7eb2e8f9f7 266 * As they are weak aliases, any function with the same name will override
<> 144:ef7eb2e8f9f7 267 * this definition.
<> 144:ef7eb2e8f9f7 268 *
<> 144:ef7eb2e8f9f7 269 *******************************************************************************/
<> 144:ef7eb2e8f9f7 270
<> 144:ef7eb2e8f9f7 271
<> 144:ef7eb2e8f9f7 272 .weak NMI_Handler
<> 144:ef7eb2e8f9f7 273 .thumb_set NMI_Handler,Default_Handler
<> 144:ef7eb2e8f9f7 274
<> 144:ef7eb2e8f9f7 275 .weak HardFault_Handler
<> 144:ef7eb2e8f9f7 276 .thumb_set HardFault_Handler,Default_Handler
<> 144:ef7eb2e8f9f7 277
<> 144:ef7eb2e8f9f7 278 .weak MemManage_Handler
<> 144:ef7eb2e8f9f7 279 .thumb_set MemManage_Handler,Default_Handler
<> 144:ef7eb2e8f9f7 280
<> 144:ef7eb2e8f9f7 281 .weak BusFault_Handler
<> 144:ef7eb2e8f9f7 282 .thumb_set BusFault_Handler,Default_Handler
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 .weak UsageFault_Handler
<> 144:ef7eb2e8f9f7 285 .thumb_set UsageFault_Handler,Default_Handler
<> 144:ef7eb2e8f9f7 286
<> 144:ef7eb2e8f9f7 287 .weak SVC_Handler
<> 144:ef7eb2e8f9f7 288 .thumb_set SVC_Handler,Default_Handler
<> 144:ef7eb2e8f9f7 289
<> 144:ef7eb2e8f9f7 290 .weak DebugMon_Handler
<> 144:ef7eb2e8f9f7 291 .thumb_set DebugMon_Handler,Default_Handler
<> 144:ef7eb2e8f9f7 292
<> 144:ef7eb2e8f9f7 293 .weak PendSV_Handler
<> 144:ef7eb2e8f9f7 294 .thumb_set PendSV_Handler,Default_Handler
<> 144:ef7eb2e8f9f7 295
<> 144:ef7eb2e8f9f7 296 .weak SysTick_Handler
<> 144:ef7eb2e8f9f7 297 .thumb_set SysTick_Handler,Default_Handler
<> 144:ef7eb2e8f9f7 298
<> 144:ef7eb2e8f9f7 299 .weak WWDG_IRQHandler
<> 144:ef7eb2e8f9f7 300 .thumb_set WWDG_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 301
<> 144:ef7eb2e8f9f7 302 .weak PVD_IRQHandler
<> 144:ef7eb2e8f9f7 303 .thumb_set PVD_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 304
<> 144:ef7eb2e8f9f7 305 .weak TAMPER_IRQHandler
<> 144:ef7eb2e8f9f7 306 .thumb_set TAMPER_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 307
<> 144:ef7eb2e8f9f7 308 .weak RTC_IRQHandler
<> 144:ef7eb2e8f9f7 309 .thumb_set RTC_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 310
<> 144:ef7eb2e8f9f7 311 .weak FLASH_IRQHandler
<> 144:ef7eb2e8f9f7 312 .thumb_set FLASH_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 313
<> 144:ef7eb2e8f9f7 314 .weak RCC_IRQHandler
<> 144:ef7eb2e8f9f7 315 .thumb_set RCC_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 .weak EXTI0_IRQHandler
<> 144:ef7eb2e8f9f7 318 .thumb_set EXTI0_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 319
<> 144:ef7eb2e8f9f7 320 .weak EXTI1_IRQHandler
<> 144:ef7eb2e8f9f7 321 .thumb_set EXTI1_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 322
<> 144:ef7eb2e8f9f7 323 .weak EXTI2_IRQHandler
<> 144:ef7eb2e8f9f7 324 .thumb_set EXTI2_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 325
<> 144:ef7eb2e8f9f7 326 .weak EXTI3_IRQHandler
<> 144:ef7eb2e8f9f7 327 .thumb_set EXTI3_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329 .weak EXTI4_IRQHandler
<> 144:ef7eb2e8f9f7 330 .thumb_set EXTI4_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 331
<> 144:ef7eb2e8f9f7 332 .weak DMA1_Channel1_IRQHandler
<> 144:ef7eb2e8f9f7 333 .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 334
<> 144:ef7eb2e8f9f7 335 .weak DMA1_Channel2_IRQHandler
<> 144:ef7eb2e8f9f7 336 .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 337
<> 144:ef7eb2e8f9f7 338 .weak DMA1_Channel3_IRQHandler
<> 144:ef7eb2e8f9f7 339 .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 340
<> 144:ef7eb2e8f9f7 341 .weak DMA1_Channel4_IRQHandler
<> 144:ef7eb2e8f9f7 342 .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 343
<> 144:ef7eb2e8f9f7 344 .weak DMA1_Channel5_IRQHandler
<> 144:ef7eb2e8f9f7 345 .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 346
<> 144:ef7eb2e8f9f7 347 .weak DMA1_Channel6_IRQHandler
<> 144:ef7eb2e8f9f7 348 .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 349
<> 144:ef7eb2e8f9f7 350 .weak DMA1_Channel7_IRQHandler
<> 144:ef7eb2e8f9f7 351 .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 352
<> 144:ef7eb2e8f9f7 353 .weak ADC1_IRQHandler
<> 144:ef7eb2e8f9f7 354 .thumb_set ADC1_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 355
<> 144:ef7eb2e8f9f7 356 .weak EXTI9_5_IRQHandler
<> 144:ef7eb2e8f9f7 357 .thumb_set EXTI9_5_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 358
<> 144:ef7eb2e8f9f7 359 .weak TIM1_BRK_TIM15_IRQHandler
<> 144:ef7eb2e8f9f7 360 .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 361
<> 144:ef7eb2e8f9f7 362 .weak TIM1_UP_TIM16_IRQHandler
<> 144:ef7eb2e8f9f7 363 .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 364
<> 144:ef7eb2e8f9f7 365 .weak TIM1_TRG_COM_TIM17_IRQHandler
<> 144:ef7eb2e8f9f7 366 .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 367
<> 144:ef7eb2e8f9f7 368 .weak TIM1_CC_IRQHandler
<> 144:ef7eb2e8f9f7 369 .thumb_set TIM1_CC_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 370
<> 144:ef7eb2e8f9f7 371 .weak TIM2_IRQHandler
<> 144:ef7eb2e8f9f7 372 .thumb_set TIM2_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374 .weak TIM3_IRQHandler
<> 144:ef7eb2e8f9f7 375 .thumb_set TIM3_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 376
<> 144:ef7eb2e8f9f7 377 .weak TIM4_IRQHandler
<> 144:ef7eb2e8f9f7 378 .thumb_set TIM4_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 379
<> 144:ef7eb2e8f9f7 380 .weak I2C1_EV_IRQHandler
<> 144:ef7eb2e8f9f7 381 .thumb_set I2C1_EV_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 382
<> 144:ef7eb2e8f9f7 383 .weak I2C1_ER_IRQHandler
<> 144:ef7eb2e8f9f7 384 .thumb_set I2C1_ER_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 385
<> 144:ef7eb2e8f9f7 386 .weak I2C2_EV_IRQHandler
<> 144:ef7eb2e8f9f7 387 .thumb_set I2C2_EV_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 388
<> 144:ef7eb2e8f9f7 389 .weak I2C2_ER_IRQHandler
<> 144:ef7eb2e8f9f7 390 .thumb_set I2C2_ER_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 391
<> 144:ef7eb2e8f9f7 392 .weak SPI1_IRQHandler
<> 144:ef7eb2e8f9f7 393 .thumb_set SPI1_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 394
<> 144:ef7eb2e8f9f7 395 .weak SPI2_IRQHandler
<> 144:ef7eb2e8f9f7 396 .thumb_set SPI2_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 397
<> 144:ef7eb2e8f9f7 398 .weak USART1_IRQHandler
<> 144:ef7eb2e8f9f7 399 .thumb_set USART1_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 400
<> 144:ef7eb2e8f9f7 401 .weak USART2_IRQHandler
<> 144:ef7eb2e8f9f7 402 .thumb_set USART2_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 403
<> 144:ef7eb2e8f9f7 404 .weak USART3_IRQHandler
<> 144:ef7eb2e8f9f7 405 .thumb_set USART3_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 406
<> 144:ef7eb2e8f9f7 407 .weak EXTI15_10_IRQHandler
<> 144:ef7eb2e8f9f7 408 .thumb_set EXTI15_10_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 409
<> 144:ef7eb2e8f9f7 410 .weak RTC_Alarm_IRQHandler
<> 144:ef7eb2e8f9f7 411 .thumb_set RTC_Alarm_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 412
<> 144:ef7eb2e8f9f7 413 .weak CEC_IRQHandler
<> 144:ef7eb2e8f9f7 414 .thumb_set CEC_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 415
<> 144:ef7eb2e8f9f7 416 .weak TIM6_DAC_IRQHandler
<> 144:ef7eb2e8f9f7 417 .thumb_set TIM6_DAC_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419 .weak TIM7_IRQHandler
<> 144:ef7eb2e8f9f7 420 .thumb_set TIM7_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 421
<> 144:ef7eb2e8f9f7 422 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 144:ef7eb2e8f9f7 423