Fawwaz Nadzmy / mbed-STM

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

Fork of mbed-dev by mbed official

targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/device/efm32pg1b_usart.h@153:9398a535854b, 2016-12-22 (annotated)

Committer:
fwndz
Date:
Thu Dec 22 05:12:40 2016 +0000
Revision:
153:9398a535854b
Parent:
149:156823d33999 
device target maximize

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 50:a417edff4437 1 /**************************************************************************//**
mbed_official 50:a417edff4437 2 * @file efm32pg1b_usart.h
mbed_official 50:a417edff4437 3 * @brief EFM32PG1B_USART register and bit field definitions
mbed_official 50:a417edff4437 4 * @version 4.2.0
mbed_official 50:a417edff4437 5 ******************************************************************************
mbed_official 50:a417edff4437 6 * @section License
mbed_official 50:a417edff4437 7 * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
mbed_official 50:a417edff4437 8 ******************************************************************************
mbed_official 50:a417edff4437 9 *
mbed_official 50:a417edff4437 10 * Permission is granted to anyone to use this software for any purpose,
mbed_official 50:a417edff4437 11 * including commercial applications, and to alter it and redistribute it
mbed_official 50:a417edff4437 12 * freely, subject to the following restrictions:
mbed_official 50:a417edff4437 13 *
mbed_official 50:a417edff4437 14 * 1. The origin of this software must not be misrepresented; you must not
mbed_official 50:a417edff4437 15 * claim that you wrote the original software.@n
mbed_official 50:a417edff4437 16 * 2. Altered source versions must be plainly marked as such, and must not be
mbed_official 50:a417edff4437 17 * misrepresented as being the original software.@n
mbed_official 50:a417edff4437 18 * 3. This notice may not be removed or altered from any source distribution.
mbed_official 50:a417edff4437 19 *
mbed_official 50:a417edff4437 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
mbed_official 50:a417edff4437 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
mbed_official 50:a417edff4437 22 * providing the Software "AS IS", with no express or implied warranties of any
mbed_official 50:a417edff4437 23 * kind, including, but not limited to, any implied warranties of
mbed_official 50:a417edff4437 24 * merchantability or fitness for any particular purpose or warranties against
mbed_official 50:a417edff4437 25 * infringement of any proprietary rights of a third party.
mbed_official 50:a417edff4437 26 *
mbed_official 50:a417edff4437 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
mbed_official 50:a417edff4437 28 * incidental, or special damages, or any other relief, or for any claim by
mbed_official 50:a417edff4437 29 * any third party, arising from your use of this Software.
mbed_official 50:a417edff4437 30 *
mbed_official 50:a417edff4437 31 *****************************************************************************/
mbed_official 50:a417edff4437 32 /**************************************************************************//**
mbed_official 50:a417edff4437 33 * @addtogroup Parts
mbed_official 50:a417edff4437 34 * @{
mbed_official 50:a417edff4437 35 ******************************************************************************/
mbed_official 50:a417edff4437 36 /**************************************************************************//**
mbed_official 50:a417edff4437 37 * @defgroup EFM32PG1B_USART
mbed_official 50:a417edff4437 38 * @{
mbed_official 50:a417edff4437 39 * @brief EFM32PG1B_USART Register Declaration
mbed_official 50:a417edff4437 40 *****************************************************************************/
mbed_official 50:a417edff4437 41 typedef struct
mbed_official 50:a417edff4437 42 {
mbed_official 50:a417edff4437 43 __IO uint32_t CTRL; /**< Control Register */
mbed_official 50:a417edff4437 44 __IO uint32_t FRAME; /**< USART Frame Format Register */
mbed_official 50:a417edff4437 45 __IO uint32_t TRIGCTRL; /**< USART Trigger Control register */
mbed_official 50:a417edff4437 46 __IO uint32_t CMD; /**< Command Register */
mbed_official 50:a417edff4437 47 __I uint32_t STATUS; /**< USART Status Register */
mbed_official 50:a417edff4437 48 __IO uint32_t CLKDIV; /**< Clock Control Register */
mbed_official 50:a417edff4437 49 __I uint32_t RXDATAX; /**< RX Buffer Data Extended Register */
mbed_official 50:a417edff4437 50 __I uint32_t RXDATA; /**< RX Buffer Data Register */
mbed_official 50:a417edff4437 51 __I uint32_t RXDOUBLEX; /**< RX Buffer Double Data Extended Register */
mbed_official 50:a417edff4437 52 __I uint32_t RXDOUBLE; /**< RX FIFO Double Data Register */
mbed_official 50:a417edff4437 53 __I uint32_t RXDATAXP; /**< RX Buffer Data Extended Peek Register */
mbed_official 50:a417edff4437 54 __I uint32_t RXDOUBLEXP; /**< RX Buffer Double Data Extended Peek Register */
mbed_official 50:a417edff4437 55 __IO uint32_t TXDATAX; /**< TX Buffer Data Extended Register */
mbed_official 50:a417edff4437 56 __IO uint32_t TXDATA; /**< TX Buffer Data Register */
mbed_official 50:a417edff4437 57 __IO uint32_t TXDOUBLEX; /**< TX Buffer Double Data Extended Register */
mbed_official 50:a417edff4437 58 __IO uint32_t TXDOUBLE; /**< TX Buffer Double Data Register */
mbed_official 50:a417edff4437 59 __I uint32_t IF; /**< Interrupt Flag Register */
mbed_official 50:a417edff4437 60 __IO uint32_t IFS; /**< Interrupt Flag Set Register */
mbed_official 50:a417edff4437 61 __IO uint32_t IFC; /**< Interrupt Flag Clear Register */
mbed_official 50:a417edff4437 62 __IO uint32_t IEN; /**< Interrupt Enable Register */
mbed_official 50:a417edff4437 63 __IO uint32_t IRCTRL; /**< IrDA Control Register */
mbed_official 50:a417edff4437 64 uint32_t RESERVED0[1]; /**< Reserved for future use **/
mbed_official 50:a417edff4437 65 __IO uint32_t INPUT; /**< USART Input Register */
mbed_official 50:a417edff4437 66 __IO uint32_t I2SCTRL; /**< I2S Control Register */
mbed_official 50:a417edff4437 67 __IO uint32_t TIMING; /**< Timing Register */
mbed_official 50:a417edff4437 68 __IO uint32_t CTRLX; /**< Control Register Extended */
mbed_official 50:a417edff4437 69 __IO uint32_t TIMECMP0; /**< Used to generate interrupts and various delays */
mbed_official 50:a417edff4437 70 __IO uint32_t TIMECMP1; /**< Used to generate interrupts and various delays */
mbed_official 50:a417edff4437 71 __IO uint32_t TIMECMP2; /**< Used to generate interrupts and various delays */
mbed_official 50:a417edff4437 72 __IO uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */
mbed_official 50:a417edff4437 73 __IO uint32_t ROUTELOC0; /**< I/O Routing Location Register */
mbed_official 50:a417edff4437 74 __IO uint32_t ROUTELOC1; /**< I/O Routing Location Register */
mbed_official 50:a417edff4437 75 } USART_TypeDef; /** @} */
mbed_official 50:a417edff4437 76
mbed_official 50:a417edff4437 77 /**************************************************************************//**
mbed_official 50:a417edff4437 78 * @defgroup EFM32PG1B_USART_BitFields
mbed_official 50:a417edff4437 79 * @{
mbed_official 50:a417edff4437 80 *****************************************************************************/
mbed_official 50:a417edff4437 81
mbed_official 50:a417edff4437 82 /* Bit fields for USART CTRL */
mbed_official 50:a417edff4437 83 #define _USART_CTRL_RESETVALUE 0x00000000UL /**< Default value for USART_CTRL */
mbed_official 50:a417edff4437 84 #define _USART_CTRL_MASK 0xF3FFFF7FUL /**< Mask for USART_CTRL */
mbed_official 50:a417edff4437 85 #define USART_CTRL_SYNC (0x1UL << 0) /**< USART Synchronous Mode */
mbed_official 50:a417edff4437 86 #define _USART_CTRL_SYNC_SHIFT 0 /**< Shift value for USART_SYNC */
mbed_official 50:a417edff4437 87 #define _USART_CTRL_SYNC_MASK 0x1UL /**< Bit mask for USART_SYNC */
mbed_official 50:a417edff4437 88 #define _USART_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
mbed_official 50:a417edff4437 89 #define USART_CTRL_SYNC_DEFAULT (_USART_CTRL_SYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CTRL */
mbed_official 50:a417edff4437 90 #define USART_CTRL_LOOPBK (0x1UL << 1) /**< Loopback Enable */
mbed_official 50:a417edff4437 91 #define _USART_CTRL_LOOPBK_SHIFT 1 /**< Shift value for USART_LOOPBK */
mbed_official 50:a417edff4437 92 #define _USART_CTRL_LOOPBK_MASK 0x2UL /**< Bit mask for USART_LOOPBK */
mbed_official 50:a417edff4437 93 #define _USART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
mbed_official 50:a417edff4437 94 #define USART_CTRL_LOOPBK_DEFAULT (_USART_CTRL_LOOPBK_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRL */
mbed_official 50:a417edff4437 95 #define USART_CTRL_CCEN (0x1UL << 2) /**< Collision Check Enable */
mbed_official 50:a417edff4437 96 #define _USART_CTRL_CCEN_SHIFT 2 /**< Shift value for USART_CCEN */
mbed_official 50:a417edff4437 97 #define _USART_CTRL_CCEN_MASK 0x4UL /**< Bit mask for USART_CCEN */
mbed_official 50:a417edff4437 98 #define _USART_CTRL_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
mbed_official 50:a417edff4437 99 #define USART_CTRL_CCEN_DEFAULT (_USART_CTRL_CCEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CTRL */
mbed_official 50:a417edff4437 100 #define USART_CTRL_MPM (0x1UL << 3) /**< Multi-Processor Mode */
mbed_official 50:a417edff4437 101 #define _USART_CTRL_MPM_SHIFT 3 /**< Shift value for USART_MPM */
mbed_official 50:a417edff4437 102 #define _USART_CTRL_MPM_MASK 0x8UL /**< Bit mask for USART_MPM */
mbed_official 50:a417edff4437 103 #define _USART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
mbed_official 50:a417edff4437 104 #define USART_CTRL_MPM_DEFAULT (_USART_CTRL_MPM_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CTRL */
mbed_official 50:a417edff4437 105 #define USART_CTRL_MPAB (0x1UL << 4) /**< Multi-Processor Address-Bit */
mbed_official 50:a417edff4437 106 #define _USART_CTRL_MPAB_SHIFT 4 /**< Shift value for USART_MPAB */
mbed_official 50:a417edff4437 107 #define _USART_CTRL_MPAB_MASK 0x10UL /**< Bit mask for USART_MPAB */
mbed_official 50:a417edff4437 108 #define _USART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
mbed_official 50:a417edff4437 109 #define USART_CTRL_MPAB_DEFAULT (_USART_CTRL_MPAB_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CTRL */
mbed_official 50:a417edff4437 110 #define _USART_CTRL_OVS_SHIFT 5 /**< Shift value for USART_OVS */
mbed_official 50:a417edff4437 111 #define _USART_CTRL_OVS_MASK 0x60UL /**< Bit mask for USART_OVS */
mbed_official 50:a417edff4437 112 #define _USART_CTRL_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
mbed_official 50:a417edff4437 113 #define _USART_CTRL_OVS_X16 0x00000000UL /**< Mode X16 for USART_CTRL */
mbed_official 50:a417edff4437 114 #define _USART_CTRL_OVS_X8 0x00000001UL /**< Mode X8 for USART_CTRL */
mbed_official 50:a417edff4437 115 #define _USART_CTRL_OVS_X6 0x00000002UL /**< Mode X6 for USART_CTRL */
mbed_official 50:a417edff4437 116 #define _USART_CTRL_OVS_X4 0x00000003UL /**< Mode X4 for USART_CTRL */
mbed_official 50:a417edff4437 117 #define USART_CTRL_OVS_DEFAULT (_USART_CTRL_OVS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CTRL */
mbed_official 50:a417edff4437 118 #define USART_CTRL_OVS_X16 (_USART_CTRL_OVS_X16 << 5) /**< Shifted mode X16 for USART_CTRL */
mbed_official 50:a417edff4437 119 #define USART_CTRL_OVS_X8 (_USART_CTRL_OVS_X8 << 5) /**< Shifted mode X8 for USART_CTRL */
mbed_official 50:a417edff4437 120 #define USART_CTRL_OVS_X6 (_USART_CTRL_OVS_X6 << 5) /**< Shifted mode X6 for USART_CTRL */
mbed_official 50:a417edff4437 121 #define USART_CTRL_OVS_X4 (_USART_CTRL_OVS_X4 << 5) /**< Shifted mode X4 for USART_CTRL */
mbed_official 50:a417edff4437 122 #define USART_CTRL_CLKPOL (0x1UL << 8) /**< Clock Polarity */
mbed_official 50:a417edff4437 123 #define _USART_CTRL_CLKPOL_SHIFT 8 /**< Shift value for USART_CLKPOL */
mbed_official 50:a417edff4437 124 #define _USART_CTRL_CLKPOL_MASK 0x100UL /**< Bit mask for USART_CLKPOL */
mbed_official 50:a417edff4437 125 #define _USART_CTRL_CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
mbed_official 50:a417edff4437 126 #define _USART_CTRL_CLKPOL_IDLELOW 0x00000000UL /**< Mode IDLELOW for USART_CTRL */
mbed_official 50:a417edff4437 127 #define _USART_CTRL_CLKPOL_IDLEHIGH 0x00000001UL /**< Mode IDLEHIGH for USART_CTRL */
mbed_official 50:a417edff4437 128 #define USART_CTRL_CLKPOL_DEFAULT (_USART_CTRL_CLKPOL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CTRL */
mbed_official 50:a417edff4437 129 #define USART_CTRL_CLKPOL_IDLELOW (_USART_CTRL_CLKPOL_IDLELOW << 8) /**< Shifted mode IDLELOW for USART_CTRL */
mbed_official 50:a417edff4437 130 #define USART_CTRL_CLKPOL_IDLEHIGH (_USART_CTRL_CLKPOL_IDLEHIGH << 8) /**< Shifted mode IDLEHIGH for USART_CTRL */
mbed_official 50:a417edff4437 131 #define USART_CTRL_CLKPHA (0x1UL << 9) /**< Clock Edge For Setup/Sample */
mbed_official 50:a417edff4437 132 #define _USART_CTRL_CLKPHA_SHIFT 9 /**< Shift value for USART_CLKPHA */
mbed_official 50:a417edff4437 133 #define _USART_CTRL_CLKPHA_MASK 0x200UL /**< Bit mask for USART_CLKPHA */
mbed_official 50:a417edff4437 134 #define _USART_CTRL_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
mbed_official 50:a417edff4437 135 #define _USART_CTRL_CLKPHA_SAMPLELEADING 0x00000000UL /**< Mode SAMPLELEADING for USART_CTRL */
mbed_official 50:a417edff4437 136 #define _USART_CTRL_CLKPHA_SAMPLETRAILING 0x00000001UL /**< Mode SAMPLETRAILING for USART_CTRL */
mbed_official 50:a417edff4437 137 #define USART_CTRL_CLKPHA_DEFAULT (_USART_CTRL_CLKPHA_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CTRL */
mbed_official 50:a417edff4437 138 #define USART_CTRL_CLKPHA_SAMPLELEADING (_USART_CTRL_CLKPHA_SAMPLELEADING << 9) /**< Shifted mode SAMPLELEADING for USART_CTRL */
mbed_official 50:a417edff4437 139 #define USART_CTRL_CLKPHA_SAMPLETRAILING (_USART_CTRL_CLKPHA_SAMPLETRAILING << 9) /**< Shifted mode SAMPLETRAILING for USART_CTRL */
mbed_official 50:a417edff4437 140 #define USART_CTRL_MSBF (0x1UL << 10) /**< Most Significant Bit First */
mbed_official 50:a417edff4437 141 #define _USART_CTRL_MSBF_SHIFT 10 /**< Shift value for USART_MSBF */
mbed_official 50:a417edff4437 142 #define _USART_CTRL_MSBF_MASK 0x400UL /**< Bit mask for USART_MSBF */
mbed_official 50:a417edff4437 143 #define _USART_CTRL_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
mbed_official 50:a417edff4437 144 #define USART_CTRL_MSBF_DEFAULT (_USART_CTRL_MSBF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CTRL */
mbed_official 50:a417edff4437 145 #define USART_CTRL_CSMA (0x1UL << 11) /**< Action On Slave-Select In Master Mode */
mbed_official 50:a417edff4437 146 #define _USART_CTRL_CSMA_SHIFT 11 /**< Shift value for USART_CSMA */
mbed_official 50:a417edff4437 147 #define _USART_CTRL_CSMA_MASK 0x800UL /**< Bit mask for USART_CSMA */
mbed_official 50:a417edff4437 148 #define _USART_CTRL_CSMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
mbed_official 50:a417edff4437 149 #define _USART_CTRL_CSMA_NOACTION 0x00000000UL /**< Mode NOACTION for USART_CTRL */
mbed_official 50:a417edff4437 150 #define _USART_CTRL_CSMA_GOTOSLAVEMODE 0x00000001UL /**< Mode GOTOSLAVEMODE for USART_CTRL */
mbed_official 50:a417edff4437 151 #define USART_CTRL_CSMA_DEFAULT (_USART_CTRL_CSMA_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CTRL */
mbed_official 50:a417edff4437 152 #define USART_CTRL_CSMA_NOACTION (_USART_CTRL_CSMA_NOACTION << 11) /**< Shifted mode NOACTION for USART_CTRL */
mbed_official 50:a417edff4437 153 #define USART_CTRL_CSMA_GOTOSLAVEMODE (_USART_CTRL_CSMA_GOTOSLAVEMODE << 11) /**< Shifted mode GOTOSLAVEMODE for USART_CTRL */
mbed_official 50:a417edff4437 154 #define USART_CTRL_TXBIL (0x1UL << 12) /**< TX Buffer Interrupt Level */
mbed_official 50:a417edff4437 155 #define _USART_CTRL_TXBIL_SHIFT 12 /**< Shift value for USART_TXBIL */
mbed_official 50:a417edff4437 156 #define _USART_CTRL_TXBIL_MASK 0x1000UL /**< Bit mask for USART_TXBIL */
mbed_official 50:a417edff4437 157 #define _USART_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
mbed_official 50:a417edff4437 158 #define _USART_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for USART_CTRL */
mbed_official 50:a417edff4437 159 #define _USART_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for USART_CTRL */
mbed_official 50:a417edff4437 160 #define USART_CTRL_TXBIL_DEFAULT (_USART_CTRL_TXBIL_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_CTRL */
mbed_official 50:a417edff4437 161 #define USART_CTRL_TXBIL_EMPTY (_USART_CTRL_TXBIL_EMPTY << 12) /**< Shifted mode EMPTY for USART_CTRL */
mbed_official 50:a417edff4437 162 #define USART_CTRL_TXBIL_HALFFULL (_USART_CTRL_TXBIL_HALFFULL << 12) /**< Shifted mode HALFFULL for USART_CTRL */
mbed_official 50:a417edff4437 163 #define USART_CTRL_RXINV (0x1UL << 13) /**< Receiver Input Invert */
mbed_official 50:a417edff4437 164 #define _USART_CTRL_RXINV_SHIFT 13 /**< Shift value for USART_RXINV */
mbed_official 50:a417edff4437 165 #define _USART_CTRL_RXINV_MASK 0x2000UL /**< Bit mask for USART_RXINV */
mbed_official 50:a417edff4437 166 #define _USART_CTRL_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
mbed_official 50:a417edff4437 167 #define USART_CTRL_RXINV_DEFAULT (_USART_CTRL_RXINV_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_CTRL */
mbed_official 50:a417edff4437 168 #define USART_CTRL_TXINV (0x1UL << 14) /**< Transmitter output Invert */
mbed_official 50:a417edff4437 169 #define _USART_CTRL_TXINV_SHIFT 14 /**< Shift value for USART_TXINV */
mbed_official 50:a417edff4437 170 #define _USART_CTRL_TXINV_MASK 0x4000UL /**< Bit mask for USART_TXINV */
mbed_official 50:a417edff4437 171 #define _USART_CTRL_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
mbed_official 50:a417edff4437 172 #define USART_CTRL_TXINV_DEFAULT (_USART_CTRL_TXINV_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_CTRL */
mbed_official 50:a417edff4437 173 #define USART_CTRL_CSINV (0x1UL << 15) /**< Chip Select Invert */
mbed_official 50:a417edff4437 174 #define _USART_CTRL_CSINV_SHIFT 15 /**< Shift value for USART_CSINV */
mbed_official 50:a417edff4437 175 #define _USART_CTRL_CSINV_MASK 0x8000UL /**< Bit mask for USART_CSINV */
mbed_official 50:a417edff4437 176 #define _USART_CTRL_CSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
mbed_official 50:a417edff4437 177 #define USART_CTRL_CSINV_DEFAULT (_USART_CTRL_CSINV_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_CTRL */
mbed_official 50:a417edff4437 178 #define USART_CTRL_AUTOCS (0x1UL << 16) /**< Automatic Chip Select */
mbed_official 50:a417edff4437 179 #define _USART_CTRL_AUTOCS_SHIFT 16 /**< Shift value for USART_AUTOCS */
mbed_official 50:a417edff4437 180 #define _USART_CTRL_AUTOCS_MASK 0x10000UL /**< Bit mask for USART_AUTOCS */
mbed_official 50:a417edff4437 181 #define _USART_CTRL_AUTOCS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
mbed_official 50:a417edff4437 182 #define USART_CTRL_AUTOCS_DEFAULT (_USART_CTRL_AUTOCS_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_CTRL */
mbed_official 50:a417edff4437 183 #define USART_CTRL_AUTOTRI (0x1UL << 17) /**< Automatic TX Tristate */
mbed_official 50:a417edff4437 184 #define _USART_CTRL_AUTOTRI_SHIFT 17 /**< Shift value for USART_AUTOTRI */
mbed_official 50:a417edff4437 185 #define _USART_CTRL_AUTOTRI_MASK 0x20000UL /**< Bit mask for USART_AUTOTRI */
mbed_official 50:a417edff4437 186 #define _USART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
mbed_official 50:a417edff4437 187 #define USART_CTRL_AUTOTRI_DEFAULT (_USART_CTRL_AUTOTRI_DEFAULT << 17) /**< Shifted mode DEFAULT for USART_CTRL */
mbed_official 50:a417edff4437 188 #define USART_CTRL_SCMODE (0x1UL << 18) /**< SmartCard Mode */
mbed_official 50:a417edff4437 189 #define _USART_CTRL_SCMODE_SHIFT 18 /**< Shift value for USART_SCMODE */
mbed_official 50:a417edff4437 190 #define _USART_CTRL_SCMODE_MASK 0x40000UL /**< Bit mask for USART_SCMODE */
mbed_official 50:a417edff4437 191 #define _USART_CTRL_SCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
mbed_official 50:a417edff4437 192 #define USART_CTRL_SCMODE_DEFAULT (_USART_CTRL_SCMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for USART_CTRL */
mbed_official 50:a417edff4437 193 #define USART_CTRL_SCRETRANS (0x1UL << 19) /**< SmartCard Retransmit */
mbed_official 50:a417edff4437 194 #define _USART_CTRL_SCRETRANS_SHIFT 19 /**< Shift value for USART_SCRETRANS */
mbed_official 50:a417edff4437 195 #define _USART_CTRL_SCRETRANS_MASK 0x80000UL /**< Bit mask for USART_SCRETRANS */
mbed_official 50:a417edff4437 196 #define _USART_CTRL_SCRETRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
mbed_official 50:a417edff4437 197 #define USART_CTRL_SCRETRANS_DEFAULT (_USART_CTRL_SCRETRANS_DEFAULT << 19) /**< Shifted mode DEFAULT for USART_CTRL */
mbed_official 50:a417edff4437 198 #define USART_CTRL_SKIPPERRF (0x1UL << 20) /**< Skip Parity Error Frames */
mbed_official 50:a417edff4437 199 #define _USART_CTRL_SKIPPERRF_SHIFT 20 /**< Shift value for USART_SKIPPERRF */
mbed_official 50:a417edff4437 200 #define _USART_CTRL_SKIPPERRF_MASK 0x100000UL /**< Bit mask for USART_SKIPPERRF */
mbed_official 50:a417edff4437 201 #define _USART_CTRL_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
mbed_official 50:a417edff4437 202 #define USART_CTRL_SKIPPERRF_DEFAULT (_USART_CTRL_SKIPPERRF_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_CTRL */
mbed_official 50:a417edff4437 203 #define USART_CTRL_BIT8DV (0x1UL << 21) /**< Bit 8 Default Value */
mbed_official 50:a417edff4437 204 #define _USART_CTRL_BIT8DV_SHIFT 21 /**< Shift value for USART_BIT8DV */
mbed_official 50:a417edff4437 205 #define _USART_CTRL_BIT8DV_MASK 0x200000UL /**< Bit mask for USART_BIT8DV */
mbed_official 50:a417edff4437 206 #define _USART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
mbed_official 50:a417edff4437 207 #define USART_CTRL_BIT8DV_DEFAULT (_USART_CTRL_BIT8DV_DEFAULT << 21) /**< Shifted mode DEFAULT for USART_CTRL */
mbed_official 50:a417edff4437 208 #define USART_CTRL_ERRSDMA (0x1UL << 22) /**< Halt DMA On Error */
mbed_official 50:a417edff4437 209 #define _USART_CTRL_ERRSDMA_SHIFT 22 /**< Shift value for USART_ERRSDMA */
mbed_official 50:a417edff4437 210 #define _USART_CTRL_ERRSDMA_MASK 0x400000UL /**< Bit mask for USART_ERRSDMA */
mbed_official 50:a417edff4437 211 #define _USART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
mbed_official 50:a417edff4437 212 #define USART_CTRL_ERRSDMA_DEFAULT (_USART_CTRL_ERRSDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for USART_CTRL */
mbed_official 50:a417edff4437 213 #define USART_CTRL_ERRSRX (0x1UL << 23) /**< Disable RX On Error */
mbed_official 50:a417edff4437 214 #define _USART_CTRL_ERRSRX_SHIFT 23 /**< Shift value for USART_ERRSRX */
mbed_official 50:a417edff4437 215 #define _USART_CTRL_ERRSRX_MASK 0x800000UL /**< Bit mask for USART_ERRSRX */
mbed_official 50:a417edff4437 216 #define _USART_CTRL_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
mbed_official 50:a417edff4437 217 #define USART_CTRL_ERRSRX_DEFAULT (_USART_CTRL_ERRSRX_DEFAULT << 23) /**< Shifted mode DEFAULT for USART_CTRL */
mbed_official 50:a417edff4437 218 #define USART_CTRL_ERRSTX (0x1UL << 24) /**< Disable TX On Error */
mbed_official 50:a417edff4437 219 #define _USART_CTRL_ERRSTX_SHIFT 24 /**< Shift value for USART_ERRSTX */
mbed_official 50:a417edff4437 220 #define _USART_CTRL_ERRSTX_MASK 0x1000000UL /**< Bit mask for USART_ERRSTX */
mbed_official 50:a417edff4437 221 #define _USART_CTRL_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
mbed_official 50:a417edff4437 222 #define USART_CTRL_ERRSTX_DEFAULT (_USART_CTRL_ERRSTX_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_CTRL */
mbed_official 50:a417edff4437 223 #define USART_CTRL_SSSEARLY (0x1UL << 25) /**< Synchronous Slave Setup Early */
mbed_official 50:a417edff4437 224 #define _USART_CTRL_SSSEARLY_SHIFT 25 /**< Shift value for USART_SSSEARLY */
mbed_official 50:a417edff4437 225 #define _USART_CTRL_SSSEARLY_MASK 0x2000000UL /**< Bit mask for USART_SSSEARLY */
mbed_official 50:a417edff4437 226 #define _USART_CTRL_SSSEARLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
mbed_official 50:a417edff4437 227 #define USART_CTRL_SSSEARLY_DEFAULT (_USART_CTRL_SSSEARLY_DEFAULT << 25) /**< Shifted mode DEFAULT for USART_CTRL */
mbed_official 50:a417edff4437 228 #define USART_CTRL_BYTESWAP (0x1UL << 28) /**< Byteswap In Double Accesses */
mbed_official 50:a417edff4437 229 #define _USART_CTRL_BYTESWAP_SHIFT 28 /**< Shift value for USART_BYTESWAP */
mbed_official 50:a417edff4437 230 #define _USART_CTRL_BYTESWAP_MASK 0x10000000UL /**< Bit mask for USART_BYTESWAP */
mbed_official 50:a417edff4437 231 #define _USART_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
mbed_official 50:a417edff4437 232 #define USART_CTRL_BYTESWAP_DEFAULT (_USART_CTRL_BYTESWAP_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_CTRL */
mbed_official 50:a417edff4437 233 #define USART_CTRL_AUTOTX (0x1UL << 29) /**< Always Transmit When RX Not Full */
mbed_official 50:a417edff4437 234 #define _USART_CTRL_AUTOTX_SHIFT 29 /**< Shift value for USART_AUTOTX */
mbed_official 50:a417edff4437 235 #define _USART_CTRL_AUTOTX_MASK 0x20000000UL /**< Bit mask for USART_AUTOTX */
mbed_official 50:a417edff4437 236 #define _USART_CTRL_AUTOTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
mbed_official 50:a417edff4437 237 #define USART_CTRL_AUTOTX_DEFAULT (_USART_CTRL_AUTOTX_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_CTRL */
mbed_official 50:a417edff4437 238 #define USART_CTRL_MVDIS (0x1UL << 30) /**< Majority Vote Disable */
mbed_official 50:a417edff4437 239 #define _USART_CTRL_MVDIS_SHIFT 30 /**< Shift value for USART_MVDIS */
mbed_official 50:a417edff4437 240 #define _USART_CTRL_MVDIS_MASK 0x40000000UL /**< Bit mask for USART_MVDIS */
mbed_official 50:a417edff4437 241 #define _USART_CTRL_MVDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
mbed_official 50:a417edff4437 242 #define USART_CTRL_MVDIS_DEFAULT (_USART_CTRL_MVDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_CTRL */
mbed_official 50:a417edff4437 243 #define USART_CTRL_SMSDELAY (0x1UL << 31) /**< Synchronous Master Sample Delay */
mbed_official 50:a417edff4437 244 #define _USART_CTRL_SMSDELAY_SHIFT 31 /**< Shift value for USART_SMSDELAY */
mbed_official 50:a417edff4437 245 #define _USART_CTRL_SMSDELAY_MASK 0x80000000UL /**< Bit mask for USART_SMSDELAY */
mbed_official 50:a417edff4437 246 #define _USART_CTRL_SMSDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
mbed_official 50:a417edff4437 247 #define USART_CTRL_SMSDELAY_DEFAULT (_USART_CTRL_SMSDELAY_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CTRL */
mbed_official 50:a417edff4437 248
mbed_official 50:a417edff4437 249 /* Bit fields for USART FRAME */
mbed_official 50:a417edff4437 250 #define _USART_FRAME_RESETVALUE 0x00001005UL /**< Default value for USART_FRAME */
mbed_official 50:a417edff4437 251 #define _USART_FRAME_MASK 0x0000330FUL /**< Mask for USART_FRAME */
mbed_official 50:a417edff4437 252 #define _USART_FRAME_DATABITS_SHIFT 0 /**< Shift value for USART_DATABITS */
mbed_official 50:a417edff4437 253 #define _USART_FRAME_DATABITS_MASK 0xFUL /**< Bit mask for USART_DATABITS */
mbed_official 50:a417edff4437 254 #define _USART_FRAME_DATABITS_FOUR 0x00000001UL /**< Mode FOUR for USART_FRAME */
mbed_official 50:a417edff4437 255 #define _USART_FRAME_DATABITS_FIVE 0x00000002UL /**< Mode FIVE for USART_FRAME */
mbed_official 50:a417edff4437 256 #define _USART_FRAME_DATABITS_SIX 0x00000003UL /**< Mode SIX for USART_FRAME */
mbed_official 50:a417edff4437 257 #define _USART_FRAME_DATABITS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_FRAME */
mbed_official 50:a417edff4437 258 #define _USART_FRAME_DATABITS_DEFAULT 0x00000005UL /**< Mode DEFAULT for USART_FRAME */
mbed_official 50:a417edff4437 259 #define _USART_FRAME_DATABITS_EIGHT 0x00000005UL /**< Mode EIGHT for USART_FRAME */
mbed_official 50:a417edff4437 260 #define _USART_FRAME_DATABITS_NINE 0x00000006UL /**< Mode NINE for USART_FRAME */
mbed_official 50:a417edff4437 261 #define _USART_FRAME_DATABITS_TEN 0x00000007UL /**< Mode TEN for USART_FRAME */
mbed_official 50:a417edff4437 262 #define _USART_FRAME_DATABITS_ELEVEN 0x00000008UL /**< Mode ELEVEN for USART_FRAME */
mbed_official 50:a417edff4437 263 #define _USART_FRAME_DATABITS_TWELVE 0x00000009UL /**< Mode TWELVE for USART_FRAME */
mbed_official 50:a417edff4437 264 #define _USART_FRAME_DATABITS_THIRTEEN 0x0000000AUL /**< Mode THIRTEEN for USART_FRAME */
mbed_official 50:a417edff4437 265 #define _USART_FRAME_DATABITS_FOURTEEN 0x0000000BUL /**< Mode FOURTEEN for USART_FRAME */
mbed_official 50:a417edff4437 266 #define _USART_FRAME_DATABITS_FIFTEEN 0x0000000CUL /**< Mode FIFTEEN for USART_FRAME */
mbed_official 50:a417edff4437 267 #define _USART_FRAME_DATABITS_SIXTEEN 0x0000000DUL /**< Mode SIXTEEN for USART_FRAME */
mbed_official 50:a417edff4437 268 #define USART_FRAME_DATABITS_FOUR (_USART_FRAME_DATABITS_FOUR << 0) /**< Shifted mode FOUR for USART_FRAME */
mbed_official 50:a417edff4437 269 #define USART_FRAME_DATABITS_FIVE (_USART_FRAME_DATABITS_FIVE << 0) /**< Shifted mode FIVE for USART_FRAME */
mbed_official 50:a417edff4437 270 #define USART_FRAME_DATABITS_SIX (_USART_FRAME_DATABITS_SIX << 0) /**< Shifted mode SIX for USART_FRAME */
mbed_official 50:a417edff4437 271 #define USART_FRAME_DATABITS_SEVEN (_USART_FRAME_DATABITS_SEVEN << 0) /**< Shifted mode SEVEN for USART_FRAME */
mbed_official 50:a417edff4437 272 #define USART_FRAME_DATABITS_DEFAULT (_USART_FRAME_DATABITS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_FRAME */
mbed_official 50:a417edff4437 273 #define USART_FRAME_DATABITS_EIGHT (_USART_FRAME_DATABITS_EIGHT << 0) /**< Shifted mode EIGHT for USART_FRAME */
mbed_official 50:a417edff4437 274 #define USART_FRAME_DATABITS_NINE (_USART_FRAME_DATABITS_NINE << 0) /**< Shifted mode NINE for USART_FRAME */
mbed_official 50:a417edff4437 275 #define USART_FRAME_DATABITS_TEN (_USART_FRAME_DATABITS_TEN << 0) /**< Shifted mode TEN for USART_FRAME */
mbed_official 50:a417edff4437 276 #define USART_FRAME_DATABITS_ELEVEN (_USART_FRAME_DATABITS_ELEVEN << 0) /**< Shifted mode ELEVEN for USART_FRAME */
mbed_official 50:a417edff4437 277 #define USART_FRAME_DATABITS_TWELVE (_USART_FRAME_DATABITS_TWELVE << 0) /**< Shifted mode TWELVE for USART_FRAME */
mbed_official 50:a417edff4437 278 #define USART_FRAME_DATABITS_THIRTEEN (_USART_FRAME_DATABITS_THIRTEEN << 0) /**< Shifted mode THIRTEEN for USART_FRAME */
mbed_official 50:a417edff4437 279 #define USART_FRAME_DATABITS_FOURTEEN (_USART_FRAME_DATABITS_FOURTEEN << 0) /**< Shifted mode FOURTEEN for USART_FRAME */
mbed_official 50:a417edff4437 280 #define USART_FRAME_DATABITS_FIFTEEN (_USART_FRAME_DATABITS_FIFTEEN << 0) /**< Shifted mode FIFTEEN for USART_FRAME */
mbed_official 50:a417edff4437 281 #define USART_FRAME_DATABITS_SIXTEEN (_USART_FRAME_DATABITS_SIXTEEN << 0) /**< Shifted mode SIXTEEN for USART_FRAME */
mbed_official 50:a417edff4437 282 #define _USART_FRAME_PARITY_SHIFT 8 /**< Shift value for USART_PARITY */
mbed_official 50:a417edff4437 283 #define _USART_FRAME_PARITY_MASK 0x300UL /**< Bit mask for USART_PARITY */
mbed_official 50:a417edff4437 284 #define _USART_FRAME_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_FRAME */
mbed_official 50:a417edff4437 285 #define _USART_FRAME_PARITY_NONE 0x00000000UL /**< Mode NONE for USART_FRAME */
mbed_official 50:a417edff4437 286 #define _USART_FRAME_PARITY_EVEN 0x00000002UL /**< Mode EVEN for USART_FRAME */
mbed_official 50:a417edff4437 287 #define _USART_FRAME_PARITY_ODD 0x00000003UL /**< Mode ODD for USART_FRAME */
mbed_official 50:a417edff4437 288 #define USART_FRAME_PARITY_DEFAULT (_USART_FRAME_PARITY_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_FRAME */
mbed_official 50:a417edff4437 289 #define USART_FRAME_PARITY_NONE (_USART_FRAME_PARITY_NONE << 8) /**< Shifted mode NONE for USART_FRAME */
mbed_official 50:a417edff4437 290 #define USART_FRAME_PARITY_EVEN (_USART_FRAME_PARITY_EVEN << 8) /**< Shifted mode EVEN for USART_FRAME */
mbed_official 50:a417edff4437 291 #define USART_FRAME_PARITY_ODD (_USART_FRAME_PARITY_ODD << 8) /**< Shifted mode ODD for USART_FRAME */
mbed_official 50:a417edff4437 292 #define _USART_FRAME_STOPBITS_SHIFT 12 /**< Shift value for USART_STOPBITS */
mbed_official 50:a417edff4437 293 #define _USART_FRAME_STOPBITS_MASK 0x3000UL /**< Bit mask for USART_STOPBITS */
mbed_official 50:a417edff4437 294 #define _USART_FRAME_STOPBITS_HALF 0x00000000UL /**< Mode HALF for USART_FRAME */
mbed_official 50:a417edff4437 295 #define _USART_FRAME_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_FRAME */
mbed_official 50:a417edff4437 296 #define _USART_FRAME_STOPBITS_ONE 0x00000001UL /**< Mode ONE for USART_FRAME */
mbed_official 50:a417edff4437 297 #define _USART_FRAME_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for USART_FRAME */
mbed_official 50:a417edff4437 298 #define _USART_FRAME_STOPBITS_TWO 0x00000003UL /**< Mode TWO for USART_FRAME */
mbed_official 50:a417edff4437 299 #define USART_FRAME_STOPBITS_HALF (_USART_FRAME_STOPBITS_HALF << 12) /**< Shifted mode HALF for USART_FRAME */
mbed_official 50:a417edff4437 300 #define USART_FRAME_STOPBITS_DEFAULT (_USART_FRAME_STOPBITS_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_FRAME */
mbed_official 50:a417edff4437 301 #define USART_FRAME_STOPBITS_ONE (_USART_FRAME_STOPBITS_ONE << 12) /**< Shifted mode ONE for USART_FRAME */
mbed_official 50:a417edff4437 302 #define USART_FRAME_STOPBITS_ONEANDAHALF (_USART_FRAME_STOPBITS_ONEANDAHALF << 12) /**< Shifted mode ONEANDAHALF for USART_FRAME */
mbed_official 50:a417edff4437 303 #define USART_FRAME_STOPBITS_TWO (_USART_FRAME_STOPBITS_TWO << 12) /**< Shifted mode TWO for USART_FRAME */
mbed_official 50:a417edff4437 304
mbed_official 50:a417edff4437 305 /* Bit fields for USART TRIGCTRL */
mbed_official 50:a417edff4437 306 #define _USART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_TRIGCTRL */
mbed_official 50:a417edff4437 307 #define _USART_TRIGCTRL_MASK 0x000F1FF0UL /**< Mask for USART_TRIGCTRL */
mbed_official 50:a417edff4437 308 #define USART_TRIGCTRL_RXTEN (0x1UL << 4) /**< Receive Trigger Enable */
mbed_official 50:a417edff4437 309 #define _USART_TRIGCTRL_RXTEN_SHIFT 4 /**< Shift value for USART_RXTEN */
mbed_official 50:a417edff4437 310 #define _USART_TRIGCTRL_RXTEN_MASK 0x10UL /**< Bit mask for USART_RXTEN */
mbed_official 50:a417edff4437 311 #define _USART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
mbed_official 50:a417edff4437 312 #define USART_TRIGCTRL_RXTEN_DEFAULT (_USART_TRIGCTRL_RXTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
mbed_official 50:a417edff4437 313 #define USART_TRIGCTRL_TXTEN (0x1UL << 5) /**< Transmit Trigger Enable */
mbed_official 50:a417edff4437 314 #define _USART_TRIGCTRL_TXTEN_SHIFT 5 /**< Shift value for USART_TXTEN */
mbed_official 50:a417edff4437 315 #define _USART_TRIGCTRL_TXTEN_MASK 0x20UL /**< Bit mask for USART_TXTEN */
mbed_official 50:a417edff4437 316 #define _USART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
mbed_official 50:a417edff4437 317 #define USART_TRIGCTRL_TXTEN_DEFAULT (_USART_TRIGCTRL_TXTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
mbed_official 50:a417edff4437 318 #define USART_TRIGCTRL_AUTOTXTEN (0x1UL << 6) /**< AUTOTX Trigger Enable */
mbed_official 50:a417edff4437 319 #define _USART_TRIGCTRL_AUTOTXTEN_SHIFT 6 /**< Shift value for USART_AUTOTXTEN */
mbed_official 50:a417edff4437 320 #define _USART_TRIGCTRL_AUTOTXTEN_MASK 0x40UL /**< Bit mask for USART_AUTOTXTEN */
mbed_official 50:a417edff4437 321 #define _USART_TRIGCTRL_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
mbed_official 50:a417edff4437 322 #define USART_TRIGCTRL_AUTOTXTEN_DEFAULT (_USART_TRIGCTRL_AUTOTXTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
mbed_official 50:a417edff4437 323 #define USART_TRIGCTRL_TXARX0EN (0x1UL << 7) /**< Enable Transmit Trigger after RX End of Frame plus TCMP0VAL */
mbed_official 50:a417edff4437 324 #define _USART_TRIGCTRL_TXARX0EN_SHIFT 7 /**< Shift value for USART_TXARX0EN */
mbed_official 50:a417edff4437 325 #define _USART_TRIGCTRL_TXARX0EN_MASK 0x80UL /**< Bit mask for USART_TXARX0EN */
mbed_official 50:a417edff4437 326 #define _USART_TRIGCTRL_TXARX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
mbed_official 50:a417edff4437 327 #define USART_TRIGCTRL_TXARX0EN_DEFAULT (_USART_TRIGCTRL_TXARX0EN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
mbed_official 50:a417edff4437 328 #define USART_TRIGCTRL_TXARX1EN (0x1UL << 8) /**< Enable Transmit Trigger after RX End of Frame plus TCMP1VAL */
mbed_official 50:a417edff4437 329 #define _USART_TRIGCTRL_TXARX1EN_SHIFT 8 /**< Shift value for USART_TXARX1EN */
mbed_official 50:a417edff4437 330 #define _USART_TRIGCTRL_TXARX1EN_MASK 0x100UL /**< Bit mask for USART_TXARX1EN */
mbed_official 50:a417edff4437 331 #define _USART_TRIGCTRL_TXARX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
mbed_official 50:a417edff4437 332 #define USART_TRIGCTRL_TXARX1EN_DEFAULT (_USART_TRIGCTRL_TXARX1EN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
mbed_official 50:a417edff4437 333 #define USART_TRIGCTRL_TXARX2EN (0x1UL << 9) /**< Enable Transmit Trigger after RX End of Frame plus TCMP2VAL */
mbed_official 50:a417edff4437 334 #define _USART_TRIGCTRL_TXARX2EN_SHIFT 9 /**< Shift value for USART_TXARX2EN */
mbed_official 50:a417edff4437 335 #define _USART_TRIGCTRL_TXARX2EN_MASK 0x200UL /**< Bit mask for USART_TXARX2EN */
mbed_official 50:a417edff4437 336 #define _USART_TRIGCTRL_TXARX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
mbed_official 50:a417edff4437 337 #define USART_TRIGCTRL_TXARX2EN_DEFAULT (_USART_TRIGCTRL_TXARX2EN_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
mbed_official 50:a417edff4437 338 #define USART_TRIGCTRL_RXATX0EN (0x1UL << 10) /**< Enable Receive Trigger after TX end of frame plus TCMPVAL0 baud-times */
mbed_official 50:a417edff4437 339 #define _USART_TRIGCTRL_RXATX0EN_SHIFT 10 /**< Shift value for USART_RXATX0EN */
mbed_official 50:a417edff4437 340 #define _USART_TRIGCTRL_RXATX0EN_MASK 0x400UL /**< Bit mask for USART_RXATX0EN */
mbed_official 50:a417edff4437 341 #define _USART_TRIGCTRL_RXATX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
mbed_official 50:a417edff4437 342 #define USART_TRIGCTRL_RXATX0EN_DEFAULT (_USART_TRIGCTRL_RXATX0EN_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
mbed_official 50:a417edff4437 343 #define USART_TRIGCTRL_RXATX1EN (0x1UL << 11) /**< Enable Receive Trigger after TX end of frame plus TCMPVAL1 baud-times */
mbed_official 50:a417edff4437 344 #define _USART_TRIGCTRL_RXATX1EN_SHIFT 11 /**< Shift value for USART_RXATX1EN */
mbed_official 50:a417edff4437 345 #define _USART_TRIGCTRL_RXATX1EN_MASK 0x800UL /**< Bit mask for USART_RXATX1EN */
mbed_official 50:a417edff4437 346 #define _USART_TRIGCTRL_RXATX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
mbed_official 50:a417edff4437 347 #define USART_TRIGCTRL_RXATX1EN_DEFAULT (_USART_TRIGCTRL_RXATX1EN_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
mbed_official 50:a417edff4437 348 #define USART_TRIGCTRL_RXATX2EN (0x1UL << 12) /**< Enable Receive Trigger after TX end of frame plus TCMPVAL2 baud-times */
mbed_official 50:a417edff4437 349 #define _USART_TRIGCTRL_RXATX2EN_SHIFT 12 /**< Shift value for USART_RXATX2EN */
mbed_official 50:a417edff4437 350 #define _USART_TRIGCTRL_RXATX2EN_MASK 0x1000UL /**< Bit mask for USART_RXATX2EN */
mbed_official 50:a417edff4437 351 #define _USART_TRIGCTRL_RXATX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
mbed_official 50:a417edff4437 352 #define USART_TRIGCTRL_RXATX2EN_DEFAULT (_USART_TRIGCTRL_RXATX2EN_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
mbed_official 50:a417edff4437 353 #define _USART_TRIGCTRL_TSEL_SHIFT 16 /**< Shift value for USART_TSEL */
mbed_official 50:a417edff4437 354 #define _USART_TRIGCTRL_TSEL_MASK 0xF0000UL /**< Bit mask for USART_TSEL */
mbed_official 50:a417edff4437 355 #define _USART_TRIGCTRL_TSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
mbed_official 50:a417edff4437 356 #define _USART_TRIGCTRL_TSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_TRIGCTRL */
mbed_official 50:a417edff4437 357 #define _USART_TRIGCTRL_TSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_TRIGCTRL */
mbed_official 50:a417edff4437 358 #define _USART_TRIGCTRL_TSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_TRIGCTRL */
mbed_official 50:a417edff4437 359 #define _USART_TRIGCTRL_TSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_TRIGCTRL */
mbed_official 50:a417edff4437 360 #define _USART_TRIGCTRL_TSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_TRIGCTRL */
mbed_official 50:a417edff4437 361 #define _USART_TRIGCTRL_TSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_TRIGCTRL */
mbed_official 50:a417edff4437 362 #define _USART_TRIGCTRL_TSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_TRIGCTRL */
mbed_official 50:a417edff4437 363 #define _USART_TRIGCTRL_TSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_TRIGCTRL */
mbed_official 50:a417edff4437 364 #define _USART_TRIGCTRL_TSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_TRIGCTRL */
mbed_official 50:a417edff4437 365 #define _USART_TRIGCTRL_TSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_TRIGCTRL */
mbed_official 50:a417edff4437 366 #define _USART_TRIGCTRL_TSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_TRIGCTRL */
mbed_official 50:a417edff4437 367 #define _USART_TRIGCTRL_TSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_TRIGCTRL */
mbed_official 50:a417edff4437 368 #define USART_TRIGCTRL_TSEL_DEFAULT (_USART_TRIGCTRL_TSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
mbed_official 50:a417edff4437 369 #define USART_TRIGCTRL_TSEL_PRSCH0 (_USART_TRIGCTRL_TSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for USART_TRIGCTRL */
mbed_official 50:a417edff4437 370 #define USART_TRIGCTRL_TSEL_PRSCH1 (_USART_TRIGCTRL_TSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for USART_TRIGCTRL */
mbed_official 50:a417edff4437 371 #define USART_TRIGCTRL_TSEL_PRSCH2 (_USART_TRIGCTRL_TSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for USART_TRIGCTRL */
mbed_official 50:a417edff4437 372 #define USART_TRIGCTRL_TSEL_PRSCH3 (_USART_TRIGCTRL_TSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for USART_TRIGCTRL */
mbed_official 50:a417edff4437 373 #define USART_TRIGCTRL_TSEL_PRSCH4 (_USART_TRIGCTRL_TSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for USART_TRIGCTRL */
mbed_official 50:a417edff4437 374 #define USART_TRIGCTRL_TSEL_PRSCH5 (_USART_TRIGCTRL_TSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for USART_TRIGCTRL */
mbed_official 50:a417edff4437 375 #define USART_TRIGCTRL_TSEL_PRSCH6 (_USART_TRIGCTRL_TSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for USART_TRIGCTRL */
mbed_official 50:a417edff4437 376 #define USART_TRIGCTRL_TSEL_PRSCH7 (_USART_TRIGCTRL_TSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for USART_TRIGCTRL */
mbed_official 50:a417edff4437 377 #define USART_TRIGCTRL_TSEL_PRSCH8 (_USART_TRIGCTRL_TSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for USART_TRIGCTRL */
mbed_official 50:a417edff4437 378 #define USART_TRIGCTRL_TSEL_PRSCH9 (_USART_TRIGCTRL_TSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for USART_TRIGCTRL */
mbed_official 50:a417edff4437 379 #define USART_TRIGCTRL_TSEL_PRSCH10 (_USART_TRIGCTRL_TSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for USART_TRIGCTRL */
mbed_official 50:a417edff4437 380 #define USART_TRIGCTRL_TSEL_PRSCH11 (_USART_TRIGCTRL_TSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for USART_TRIGCTRL */
mbed_official 50:a417edff4437 381
mbed_official 50:a417edff4437 382 /* Bit fields for USART CMD */
mbed_official 50:a417edff4437 383 #define _USART_CMD_RESETVALUE 0x00000000UL /**< Default value for USART_CMD */
mbed_official 50:a417edff4437 384 #define _USART_CMD_MASK 0x00000FFFUL /**< Mask for USART_CMD */
mbed_official 50:a417edff4437 385 #define USART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */
mbed_official 50:a417edff4437 386 #define _USART_CMD_RXEN_SHIFT 0 /**< Shift value for USART_RXEN */
mbed_official 50:a417edff4437 387 #define _USART_CMD_RXEN_MASK 0x1UL /**< Bit mask for USART_RXEN */
mbed_official 50:a417edff4437 388 #define _USART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
mbed_official 50:a417edff4437 389 #define USART_CMD_RXEN_DEFAULT (_USART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CMD */
mbed_official 50:a417edff4437 390 #define USART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */
mbed_official 50:a417edff4437 391 #define _USART_CMD_RXDIS_SHIFT 1 /**< Shift value for USART_RXDIS */
mbed_official 50:a417edff4437 392 #define _USART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for USART_RXDIS */
mbed_official 50:a417edff4437 393 #define _USART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
mbed_official 50:a417edff4437 394 #define USART_CMD_RXDIS_DEFAULT (_USART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CMD */
mbed_official 50:a417edff4437 395 #define USART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */
mbed_official 50:a417edff4437 396 #define _USART_CMD_TXEN_SHIFT 2 /**< Shift value for USART_TXEN */
mbed_official 50:a417edff4437 397 #define _USART_CMD_TXEN_MASK 0x4UL /**< Bit mask for USART_TXEN */
mbed_official 50:a417edff4437 398 #define _USART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
mbed_official 50:a417edff4437 399 #define USART_CMD_TXEN_DEFAULT (_USART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CMD */
mbed_official 50:a417edff4437 400 #define USART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */
mbed_official 50:a417edff4437 401 #define _USART_CMD_TXDIS_SHIFT 3 /**< Shift value for USART_TXDIS */
mbed_official 50:a417edff4437 402 #define _USART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for USART_TXDIS */
mbed_official 50:a417edff4437 403 #define _USART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
mbed_official 50:a417edff4437 404 #define USART_CMD_TXDIS_DEFAULT (_USART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CMD */
mbed_official 50:a417edff4437 405 #define USART_CMD_MASTEREN (0x1UL << 4) /**< Master Enable */
mbed_official 50:a417edff4437 406 #define _USART_CMD_MASTEREN_SHIFT 4 /**< Shift value for USART_MASTEREN */
mbed_official 50:a417edff4437 407 #define _USART_CMD_MASTEREN_MASK 0x10UL /**< Bit mask for USART_MASTEREN */
mbed_official 50:a417edff4437 408 #define _USART_CMD_MASTEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
mbed_official 50:a417edff4437 409 #define USART_CMD_MASTEREN_DEFAULT (_USART_CMD_MASTEREN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CMD */
mbed_official 50:a417edff4437 410 #define USART_CMD_MASTERDIS (0x1UL << 5) /**< Master Disable */
mbed_official 50:a417edff4437 411 #define _USART_CMD_MASTERDIS_SHIFT 5 /**< Shift value for USART_MASTERDIS */
mbed_official 50:a417edff4437 412 #define _USART_CMD_MASTERDIS_MASK 0x20UL /**< Bit mask for USART_MASTERDIS */
mbed_official 50:a417edff4437 413 #define _USART_CMD_MASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
mbed_official 50:a417edff4437 414 #define USART_CMD_MASTERDIS_DEFAULT (_USART_CMD_MASTERDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CMD */
mbed_official 50:a417edff4437 415 #define USART_CMD_RXBLOCKEN (0x1UL << 6) /**< Receiver Block Enable */
mbed_official 50:a417edff4437 416 #define _USART_CMD_RXBLOCKEN_SHIFT 6 /**< Shift value for USART_RXBLOCKEN */
mbed_official 50:a417edff4437 417 #define _USART_CMD_RXBLOCKEN_MASK 0x40UL /**< Bit mask for USART_RXBLOCKEN */
mbed_official 50:a417edff4437 418 #define _USART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
mbed_official 50:a417edff4437 419 #define USART_CMD_RXBLOCKEN_DEFAULT (_USART_CMD_RXBLOCKEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_CMD */
mbed_official 50:a417edff4437 420 #define USART_CMD_RXBLOCKDIS (0x1UL << 7) /**< Receiver Block Disable */
mbed_official 50:a417edff4437 421 #define _USART_CMD_RXBLOCKDIS_SHIFT 7 /**< Shift value for USART_RXBLOCKDIS */
mbed_official 50:a417edff4437 422 #define _USART_CMD_RXBLOCKDIS_MASK 0x80UL /**< Bit mask for USART_RXBLOCKDIS */
mbed_official 50:a417edff4437 423 #define _USART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
mbed_official 50:a417edff4437 424 #define USART_CMD_RXBLOCKDIS_DEFAULT (_USART_CMD_RXBLOCKDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_CMD */
mbed_official 50:a417edff4437 425 #define USART_CMD_TXTRIEN (0x1UL << 8) /**< Transmitter Tristate Enable */
mbed_official 50:a417edff4437 426 #define _USART_CMD_TXTRIEN_SHIFT 8 /**< Shift value for USART_TXTRIEN */
mbed_official 50:a417edff4437 427 #define _USART_CMD_TXTRIEN_MASK 0x100UL /**< Bit mask for USART_TXTRIEN */
mbed_official 50:a417edff4437 428 #define _USART_CMD_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
mbed_official 50:a417edff4437 429 #define USART_CMD_TXTRIEN_DEFAULT (_USART_CMD_TXTRIEN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CMD */
mbed_official 50:a417edff4437 430 #define USART_CMD_TXTRIDIS (0x1UL << 9) /**< Transmitter Tristate Disable */
mbed_official 50:a417edff4437 431 #define _USART_CMD_TXTRIDIS_SHIFT 9 /**< Shift value for USART_TXTRIDIS */
mbed_official 50:a417edff4437 432 #define _USART_CMD_TXTRIDIS_MASK 0x200UL /**< Bit mask for USART_TXTRIDIS */
mbed_official 50:a417edff4437 433 #define _USART_CMD_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
mbed_official 50:a417edff4437 434 #define USART_CMD_TXTRIDIS_DEFAULT (_USART_CMD_TXTRIDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CMD */
mbed_official 50:a417edff4437 435 #define USART_CMD_CLEARTX (0x1UL << 10) /**< Clear TX */
mbed_official 50:a417edff4437 436 #define _USART_CMD_CLEARTX_SHIFT 10 /**< Shift value for USART_CLEARTX */
mbed_official 50:a417edff4437 437 #define _USART_CMD_CLEARTX_MASK 0x400UL /**< Bit mask for USART_CLEARTX */
mbed_official 50:a417edff4437 438 #define _USART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
mbed_official 50:a417edff4437 439 #define USART_CMD_CLEARTX_DEFAULT (_USART_CMD_CLEARTX_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CMD */
mbed_official 50:a417edff4437 440 #define USART_CMD_CLEARRX (0x1UL << 11) /**< Clear RX */
mbed_official 50:a417edff4437 441 #define _USART_CMD_CLEARRX_SHIFT 11 /**< Shift value for USART_CLEARRX */
mbed_official 50:a417edff4437 442 #define _USART_CMD_CLEARRX_MASK 0x800UL /**< Bit mask for USART_CLEARRX */
mbed_official 50:a417edff4437 443 #define _USART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
mbed_official 50:a417edff4437 444 #define USART_CMD_CLEARRX_DEFAULT (_USART_CMD_CLEARRX_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CMD */
mbed_official 50:a417edff4437 445
mbed_official 50:a417edff4437 446 /* Bit fields for USART STATUS */
mbed_official 50:a417edff4437 447 #define _USART_STATUS_RESETVALUE 0x00002040UL /**< Default value for USART_STATUS */
mbed_official 50:a417edff4437 448 #define _USART_STATUS_MASK 0x00037FFFUL /**< Mask for USART_STATUS */
mbed_official 50:a417edff4437 449 #define USART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */
mbed_official 50:a417edff4437 450 #define _USART_STATUS_RXENS_SHIFT 0 /**< Shift value for USART_RXENS */
mbed_official 50:a417edff4437 451 #define _USART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for USART_RXENS */
mbed_official 50:a417edff4437 452 #define _USART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
mbed_official 50:a417edff4437 453 #define USART_STATUS_RXENS_DEFAULT (_USART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_STATUS */
mbed_official 50:a417edff4437 454 #define USART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */
mbed_official 50:a417edff4437 455 #define _USART_STATUS_TXENS_SHIFT 1 /**< Shift value for USART_TXENS */
mbed_official 50:a417edff4437 456 #define _USART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for USART_TXENS */
mbed_official 50:a417edff4437 457 #define _USART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
mbed_official 50:a417edff4437 458 #define USART_STATUS_TXENS_DEFAULT (_USART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_STATUS */
mbed_official 50:a417edff4437 459 #define USART_STATUS_MASTER (0x1UL << 2) /**< SPI Master Mode */
mbed_official 50:a417edff4437 460 #define _USART_STATUS_MASTER_SHIFT 2 /**< Shift value for USART_MASTER */
mbed_official 50:a417edff4437 461 #define _USART_STATUS_MASTER_MASK 0x4UL /**< Bit mask for USART_MASTER */
mbed_official 50:a417edff4437 462 #define _USART_STATUS_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
mbed_official 50:a417edff4437 463 #define USART_STATUS_MASTER_DEFAULT (_USART_STATUS_MASTER_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_STATUS */
mbed_official 50:a417edff4437 464 #define USART_STATUS_RXBLOCK (0x1UL << 3) /**< Block Incoming Data */
mbed_official 50:a417edff4437 465 #define _USART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for USART_RXBLOCK */
mbed_official 50:a417edff4437 466 #define _USART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for USART_RXBLOCK */
mbed_official 50:a417edff4437 467 #define _USART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
mbed_official 50:a417edff4437 468 #define USART_STATUS_RXBLOCK_DEFAULT (_USART_STATUS_RXBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_STATUS */
mbed_official 50:a417edff4437 469 #define USART_STATUS_TXTRI (0x1UL << 4) /**< Transmitter Tristated */
mbed_official 50:a417edff4437 470 #define _USART_STATUS_TXTRI_SHIFT 4 /**< Shift value for USART_TXTRI */
mbed_official 50:a417edff4437 471 #define _USART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for USART_TXTRI */
mbed_official 50:a417edff4437 472 #define _USART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
mbed_official 50:a417edff4437 473 #define USART_STATUS_TXTRI_DEFAULT (_USART_STATUS_TXTRI_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_STATUS */
mbed_official 50:a417edff4437 474 #define USART_STATUS_TXC (0x1UL << 5) /**< TX Complete */
mbed_official 50:a417edff4437 475 #define _USART_STATUS_TXC_SHIFT 5 /**< Shift value for USART_TXC */
mbed_official 50:a417edff4437 476 #define _USART_STATUS_TXC_MASK 0x20UL /**< Bit mask for USART_TXC */
mbed_official 50:a417edff4437 477 #define _USART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
mbed_official 50:a417edff4437 478 #define USART_STATUS_TXC_DEFAULT (_USART_STATUS_TXC_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_STATUS */
mbed_official 50:a417edff4437 479 #define USART_STATUS_TXBL (0x1UL << 6) /**< TX Buffer Level */
mbed_official 50:a417edff4437 480 #define _USART_STATUS_TXBL_SHIFT 6 /**< Shift value for USART_TXBL */
mbed_official 50:a417edff4437 481 #define _USART_STATUS_TXBL_MASK 0x40UL /**< Bit mask for USART_TXBL */
mbed_official 50:a417edff4437 482 #define _USART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */
mbed_official 50:a417edff4437 483 #define USART_STATUS_TXBL_DEFAULT (_USART_STATUS_TXBL_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_STATUS */
mbed_official 50:a417edff4437 484 #define USART_STATUS_RXDATAV (0x1UL << 7) /**< RX Data Valid */
mbed_official 50:a417edff4437 485 #define _USART_STATUS_RXDATAV_SHIFT 7 /**< Shift value for USART_RXDATAV */
mbed_official 50:a417edff4437 486 #define _USART_STATUS_RXDATAV_MASK 0x80UL /**< Bit mask for USART_RXDATAV */
mbed_official 50:a417edff4437 487 #define _USART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
mbed_official 50:a417edff4437 488 #define USART_STATUS_RXDATAV_DEFAULT (_USART_STATUS_RXDATAV_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_STATUS */
mbed_official 50:a417edff4437 489 #define USART_STATUS_RXFULL (0x1UL << 8) /**< RX FIFO Full */
mbed_official 50:a417edff4437 490 #define _USART_STATUS_RXFULL_SHIFT 8 /**< Shift value for USART_RXFULL */
mbed_official 50:a417edff4437 491 #define _USART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for USART_RXFULL */
mbed_official 50:a417edff4437 492 #define _USART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
mbed_official 50:a417edff4437 493 #define USART_STATUS_RXFULL_DEFAULT (_USART_STATUS_RXFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_STATUS */
mbed_official 50:a417edff4437 494 #define USART_STATUS_TXBDRIGHT (0x1UL << 9) /**< TX Buffer Expects Double Right Data */
mbed_official 50:a417edff4437 495 #define _USART_STATUS_TXBDRIGHT_SHIFT 9 /**< Shift value for USART_TXBDRIGHT */
mbed_official 50:a417edff4437 496 #define _USART_STATUS_TXBDRIGHT_MASK 0x200UL /**< Bit mask for USART_TXBDRIGHT */
mbed_official 50:a417edff4437 497 #define _USART_STATUS_TXBDRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
mbed_official 50:a417edff4437 498 #define USART_STATUS_TXBDRIGHT_DEFAULT (_USART_STATUS_TXBDRIGHT_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_STATUS */
mbed_official 50:a417edff4437 499 #define USART_STATUS_TXBSRIGHT (0x1UL << 10) /**< TX Buffer Expects Single Right Data */
mbed_official 50:a417edff4437 500 #define _USART_STATUS_TXBSRIGHT_SHIFT 10 /**< Shift value for USART_TXBSRIGHT */
mbed_official 50:a417edff4437 501 #define _USART_STATUS_TXBSRIGHT_MASK 0x400UL /**< Bit mask for USART_TXBSRIGHT */
mbed_official 50:a417edff4437 502 #define _USART_STATUS_TXBSRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
mbed_official 50:a417edff4437 503 #define USART_STATUS_TXBSRIGHT_DEFAULT (_USART_STATUS_TXBSRIGHT_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_STATUS */
mbed_official 50:a417edff4437 504 #define USART_STATUS_RXDATAVRIGHT (0x1UL << 11) /**< RX Data Right */
mbed_official 50:a417edff4437 505 #define _USART_STATUS_RXDATAVRIGHT_SHIFT 11 /**< Shift value for USART_RXDATAVRIGHT */
mbed_official 50:a417edff4437 506 #define _USART_STATUS_RXDATAVRIGHT_MASK 0x800UL /**< Bit mask for USART_RXDATAVRIGHT */
mbed_official 50:a417edff4437 507 #define _USART_STATUS_RXDATAVRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
mbed_official 50:a417edff4437 508 #define USART_STATUS_RXDATAVRIGHT_DEFAULT (_USART_STATUS_RXDATAVRIGHT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_STATUS */
mbed_official 50:a417edff4437 509 #define USART_STATUS_RXFULLRIGHT (0x1UL << 12) /**< RX Full of Right Data */
mbed_official 50:a417edff4437 510 #define _USART_STATUS_RXFULLRIGHT_SHIFT 12 /**< Shift value for USART_RXFULLRIGHT */
mbed_official 50:a417edff4437 511 #define _USART_STATUS_RXFULLRIGHT_MASK 0x1000UL /**< Bit mask for USART_RXFULLRIGHT */
mbed_official 50:a417edff4437 512 #define _USART_STATUS_RXFULLRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
mbed_official 50:a417edff4437 513 #define USART_STATUS_RXFULLRIGHT_DEFAULT (_USART_STATUS_RXFULLRIGHT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_STATUS */
mbed_official 50:a417edff4437 514 #define USART_STATUS_TXIDLE (0x1UL << 13) /**< TX Idle */
mbed_official 50:a417edff4437 515 #define _USART_STATUS_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */
mbed_official 50:a417edff4437 516 #define _USART_STATUS_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */
mbed_official 50:a417edff4437 517 #define _USART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */
mbed_official 50:a417edff4437 518 #define USART_STATUS_TXIDLE_DEFAULT (_USART_STATUS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_STATUS */
mbed_official 50:a417edff4437 519 #define USART_STATUS_TIMERRESTARTED (0x1UL << 14) /**< The USART Timer restarted itself */
mbed_official 50:a417edff4437 520 #define _USART_STATUS_TIMERRESTARTED_SHIFT 14 /**< Shift value for USART_TIMERRESTARTED */
mbed_official 50:a417edff4437 521 #define _USART_STATUS_TIMERRESTARTED_MASK 0x4000UL /**< Bit mask for USART_TIMERRESTARTED */
mbed_official 50:a417edff4437 522 #define _USART_STATUS_TIMERRESTARTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
mbed_official 50:a417edff4437 523 #define USART_STATUS_TIMERRESTARTED_DEFAULT (_USART_STATUS_TIMERRESTARTED_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_STATUS */
mbed_official 50:a417edff4437 524 #define _USART_STATUS_TXBUFCNT_SHIFT 16 /**< Shift value for USART_TXBUFCNT */
mbed_official 50:a417edff4437 525 #define _USART_STATUS_TXBUFCNT_MASK 0x30000UL /**< Bit mask for USART_TXBUFCNT */
mbed_official 50:a417edff4437 526 #define _USART_STATUS_TXBUFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
mbed_official 50:a417edff4437 527 #define USART_STATUS_TXBUFCNT_DEFAULT (_USART_STATUS_TXBUFCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_STATUS */
mbed_official 50:a417edff4437 528
mbed_official 50:a417edff4437 529 /* Bit fields for USART CLKDIV */
mbed_official 50:a417edff4437 530 #define _USART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for USART_CLKDIV */
mbed_official 50:a417edff4437 531 #define _USART_CLKDIV_MASK 0x807FFFF8UL /**< Mask for USART_CLKDIV */
mbed_official 50:a417edff4437 532 #define _USART_CLKDIV_DIV_SHIFT 3 /**< Shift value for USART_DIV */
mbed_official 50:a417edff4437 533 #define _USART_CLKDIV_DIV_MASK 0x7FFFF8UL /**< Bit mask for USART_DIV */
mbed_official 50:a417edff4437 534 #define _USART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */
mbed_official 50:a417edff4437 535 #define USART_CLKDIV_DIV_DEFAULT (_USART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CLKDIV */
mbed_official 50:a417edff4437 536 #define USART_CLKDIV_AUTOBAUDEN (0x1UL << 31) /**< AUTOBAUD detection enable */
mbed_official 50:a417edff4437 537 #define _USART_CLKDIV_AUTOBAUDEN_SHIFT 31 /**< Shift value for USART_AUTOBAUDEN */
mbed_official 50:a417edff4437 538 #define _USART_CLKDIV_AUTOBAUDEN_MASK 0x80000000UL /**< Bit mask for USART_AUTOBAUDEN */
mbed_official 50:a417edff4437 539 #define _USART_CLKDIV_AUTOBAUDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */
mbed_official 50:a417edff4437 540 #define USART_CLKDIV_AUTOBAUDEN_DEFAULT (_USART_CLKDIV_AUTOBAUDEN_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CLKDIV */
mbed_official 50:a417edff4437 541
mbed_official 50:a417edff4437 542 /* Bit fields for USART RXDATAX */
mbed_official 50:a417edff4437 543 #define _USART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAX */
mbed_official 50:a417edff4437 544 #define _USART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAX */
mbed_official 50:a417edff4437 545 #define _USART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */
mbed_official 50:a417edff4437 546 #define _USART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for USART_RXDATA */
mbed_official 50:a417edff4437 547 #define _USART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */
mbed_official 50:a417edff4437 548 #define USART_RXDATAX_RXDATA_DEFAULT (_USART_RXDATAX_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAX */
mbed_official 50:a417edff4437 549 #define USART_RXDATAX_PERR (0x1UL << 14) /**< Data Parity Error */
mbed_official 50:a417edff4437 550 #define _USART_RXDATAX_PERR_SHIFT 14 /**< Shift value for USART_PERR */
mbed_official 50:a417edff4437 551 #define _USART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for USART_PERR */
mbed_official 50:a417edff4437 552 #define _USART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */
mbed_official 50:a417edff4437 553 #define USART_RXDATAX_PERR_DEFAULT (_USART_RXDATAX_PERR_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDATAX */
mbed_official 50:a417edff4437 554 #define USART_RXDATAX_FERR (0x1UL << 15) /**< Data Framing Error */
mbed_official 50:a417edff4437 555 #define _USART_RXDATAX_FERR_SHIFT 15 /**< Shift value for USART_FERR */
mbed_official 50:a417edff4437 556 #define _USART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for USART_FERR */
mbed_official 50:a417edff4437 557 #define _USART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */
mbed_official 50:a417edff4437 558 #define USART_RXDATAX_FERR_DEFAULT (_USART_RXDATAX_FERR_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAX */
mbed_official 50:a417edff4437 559
mbed_official 50:a417edff4437 560 /* Bit fields for USART RXDATA */
mbed_official 50:a417edff4437 561 #define _USART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATA */
mbed_official 50:a417edff4437 562 #define _USART_RXDATA_MASK 0x000000FFUL /**< Mask for USART_RXDATA */
mbed_official 50:a417edff4437 563 #define _USART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */
mbed_official 50:a417edff4437 564 #define _USART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for USART_RXDATA */
mbed_official 50:a417edff4437 565 #define _USART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATA */
mbed_official 50:a417edff4437 566 #define USART_RXDATA_RXDATA_DEFAULT (_USART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATA */
mbed_official 50:a417edff4437 567
mbed_official 50:a417edff4437 568 /* Bit fields for USART RXDOUBLEX */
mbed_official 50:a417edff4437 569 #define _USART_RXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEX */
mbed_official 50:a417edff4437 570 #define _USART_RXDOUBLEX_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEX */
mbed_official 50:a417edff4437 571 #define _USART_RXDOUBLEX_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */
mbed_official 50:a417edff4437 572 #define _USART_RXDOUBLEX_RXDATA0_MASK 0x1FFUL /**< Bit mask for USART_RXDATA0 */
mbed_official 50:a417edff4437 573 #define _USART_RXDOUBLEX_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */
mbed_official 50:a417edff4437 574 #define USART_RXDOUBLEX_RXDATA0_DEFAULT (_USART_RXDOUBLEX_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
mbed_official 50:a417edff4437 575 #define USART_RXDOUBLEX_PERR0 (0x1UL << 14) /**< Data Parity Error 0 */
mbed_official 50:a417edff4437 576 #define _USART_RXDOUBLEX_PERR0_SHIFT 14 /**< Shift value for USART_PERR0 */
mbed_official 50:a417edff4437 577 #define _USART_RXDOUBLEX_PERR0_MASK 0x4000UL /**< Bit mask for USART_PERR0 */
mbed_official 50:a417edff4437 578 #define _USART_RXDOUBLEX_PERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */
mbed_official 50:a417edff4437 579 #define USART_RXDOUBLEX_PERR0_DEFAULT (_USART_RXDOUBLEX_PERR0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
mbed_official 50:a417edff4437 580 #define USART_RXDOUBLEX_FERR0 (0x1UL << 15) /**< Data Framing Error 0 */
mbed_official 50:a417edff4437 581 #define _USART_RXDOUBLEX_FERR0_SHIFT 15 /**< Shift value for USART_FERR0 */
mbed_official 50:a417edff4437 582 #define _USART_RXDOUBLEX_FERR0_MASK 0x8000UL /**< Bit mask for USART_FERR0 */
mbed_official 50:a417edff4437 583 #define _USART_RXDOUBLEX_FERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */
mbed_official 50:a417edff4437 584 #define USART_RXDOUBLEX_FERR0_DEFAULT (_USART_RXDOUBLEX_FERR0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
mbed_official 50:a417edff4437 585 #define _USART_RXDOUBLEX_RXDATA1_SHIFT 16 /**< Shift value for USART_RXDATA1 */
mbed_official 50:a417edff4437 586 #define _USART_RXDOUBLEX_RXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATA1 */
mbed_official 50:a417edff4437 587 #define _USART_RXDOUBLEX_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */
mbed_official 50:a417edff4437 588 #define USART_RXDOUBLEX_RXDATA1_DEFAULT (_USART_RXDOUBLEX_RXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
mbed_official 50:a417edff4437 589 #define USART_RXDOUBLEX_PERR1 (0x1UL << 30) /**< Data Parity Error 1 */
mbed_official 50:a417edff4437 590 #define _USART_RXDOUBLEX_PERR1_SHIFT 30 /**< Shift value for USART_PERR1 */
mbed_official 50:a417edff4437 591 #define _USART_RXDOUBLEX_PERR1_MASK 0x40000000UL /**< Bit mask for USART_PERR1 */
mbed_official 50:a417edff4437 592 #define _USART_RXDOUBLEX_PERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */
mbed_official 50:a417edff4437 593 #define USART_RXDOUBLEX_PERR1_DEFAULT (_USART_RXDOUBLEX_PERR1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
mbed_official 50:a417edff4437 594 #define USART_RXDOUBLEX_FERR1 (0x1UL << 31) /**< Data Framing Error 1 */
mbed_official 50:a417edff4437 595 #define _USART_RXDOUBLEX_FERR1_SHIFT 31 /**< Shift value for USART_FERR1 */
mbed_official 50:a417edff4437 596 #define _USART_RXDOUBLEX_FERR1_MASK 0x80000000UL /**< Bit mask for USART_FERR1 */
mbed_official 50:a417edff4437 597 #define _USART_RXDOUBLEX_FERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */
mbed_official 50:a417edff4437 598 #define USART_RXDOUBLEX_FERR1_DEFAULT (_USART_RXDOUBLEX_FERR1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
mbed_official 50:a417edff4437 599
mbed_official 50:a417edff4437 600 /* Bit fields for USART RXDOUBLE */
mbed_official 50:a417edff4437 601 #define _USART_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLE */
mbed_official 50:a417edff4437 602 #define _USART_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_RXDOUBLE */
mbed_official 50:a417edff4437 603 #define _USART_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */
mbed_official 50:a417edff4437 604 #define _USART_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for USART_RXDATA0 */
mbed_official 50:a417edff4437 605 #define _USART_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */
mbed_official 50:a417edff4437 606 #define USART_RXDOUBLE_RXDATA0_DEFAULT (_USART_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLE */
mbed_official 50:a417edff4437 607 #define _USART_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for USART_RXDATA1 */
mbed_official 50:a417edff4437 608 #define _USART_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for USART_RXDATA1 */
mbed_official 50:a417edff4437 609 #define _USART_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */
mbed_official 50:a417edff4437 610 #define USART_RXDOUBLE_RXDATA1_DEFAULT (_USART_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_RXDOUBLE */
mbed_official 50:a417edff4437 611
mbed_official 50:a417edff4437 612 /* Bit fields for USART RXDATAXP */
mbed_official 50:a417edff4437 613 #define _USART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAXP */
mbed_official 50:a417edff4437 614 #define _USART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAXP */
mbed_official 50:a417edff4437 615 #define _USART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for USART_RXDATAP */
mbed_official 50:a417edff4437 616 #define _USART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP */
mbed_official 50:a417edff4437 617 #define _USART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */
mbed_official 50:a417edff4437 618 #define USART_RXDATAXP_RXDATAP_DEFAULT (_USART_RXDATAXP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAXP */
mbed_official 50:a417edff4437 619 #define USART_RXDATAXP_PERRP (0x1UL << 14) /**< Data Parity Error Peek */
mbed_official 50:a417edff4437 620 #define _USART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for USART_PERRP */
mbed_official 50:a417edff4437 621 #define _USART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for USART_PERRP */
mbed_official 50:a417edff4437 622 #define _USART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */
mbed_official 50:a417edff4437 623 #define USART_RXDATAXP_PERRP_DEFAULT (_USART_RXDATAXP_PERRP_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDATAXP */
mbed_official 50:a417edff4437 624 #define USART_RXDATAXP_FERRP (0x1UL << 15) /**< Data Framing Error Peek */
mbed_official 50:a417edff4437 625 #define _USART_RXDATAXP_FERRP_SHIFT 15 /**< Shift value for USART_FERRP */
mbed_official 50:a417edff4437 626 #define _USART_RXDATAXP_FERRP_MASK 0x8000UL /**< Bit mask for USART_FERRP */
mbed_official 50:a417edff4437 627 #define _USART_RXDATAXP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */
mbed_official 50:a417edff4437 628 #define USART_RXDATAXP_FERRP_DEFAULT (_USART_RXDATAXP_FERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAXP */
mbed_official 50:a417edff4437 629
mbed_official 50:a417edff4437 630 /* Bit fields for USART RXDOUBLEXP */
mbed_official 50:a417edff4437 631 #define _USART_RXDOUBLEXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEXP */
mbed_official 50:a417edff4437 632 #define _USART_RXDOUBLEXP_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEXP */
mbed_official 50:a417edff4437 633 #define _USART_RXDOUBLEXP_RXDATAP0_SHIFT 0 /**< Shift value for USART_RXDATAP0 */
mbed_official 50:a417edff4437 634 #define _USART_RXDOUBLEXP_RXDATAP0_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP0 */
mbed_official 50:a417edff4437 635 #define _USART_RXDOUBLEXP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */
mbed_official 50:a417edff4437 636 #define USART_RXDOUBLEXP_RXDATAP0_DEFAULT (_USART_RXDOUBLEXP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */
mbed_official 50:a417edff4437 637 #define USART_RXDOUBLEXP_PERRP0 (0x1UL << 14) /**< Data Parity Error 0 Peek */
mbed_official 50:a417edff4437 638 #define _USART_RXDOUBLEXP_PERRP0_SHIFT 14 /**< Shift value for USART_PERRP0 */
mbed_official 50:a417edff4437 639 #define _USART_RXDOUBLEXP_PERRP0_MASK 0x4000UL /**< Bit mask for USART_PERRP0 */
mbed_official 50:a417edff4437 640 #define _USART_RXDOUBLEXP_PERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */
mbed_official 50:a417edff4437 641 #define USART_RXDOUBLEXP_PERRP0_DEFAULT (_USART_RXDOUBLEXP_PERRP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */
mbed_official 50:a417edff4437 642 #define USART_RXDOUBLEXP_FERRP0 (0x1UL << 15) /**< Data Framing Error 0 Peek */
mbed_official 50:a417edff4437 643 #define _USART_RXDOUBLEXP_FERRP0_SHIFT 15 /**< Shift value for USART_FERRP0 */
mbed_official 50:a417edff4437 644 #define _USART_RXDOUBLEXP_FERRP0_MASK 0x8000UL /**< Bit mask for USART_FERRP0 */
mbed_official 50:a417edff4437 645 #define _USART_RXDOUBLEXP_FERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */
mbed_official 50:a417edff4437 646 #define USART_RXDOUBLEXP_FERRP0_DEFAULT (_USART_RXDOUBLEXP_FERRP0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */
mbed_official 50:a417edff4437 647 #define _USART_RXDOUBLEXP_RXDATAP1_SHIFT 16 /**< Shift value for USART_RXDATAP1 */
mbed_official 50:a417edff4437 648 #define _USART_RXDOUBLEXP_RXDATAP1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATAP1 */
mbed_official 50:a417edff4437 649 #define _USART_RXDOUBLEXP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */
mbed_official 50:a417edff4437 650 #define USART_RXDOUBLEXP_RXDATAP1_DEFAULT (_USART_RXDOUBLEXP_RXDATAP1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */
mbed_official 50:a417edff4437 651 #define USART_RXDOUBLEXP_PERRP1 (0x1UL << 30) /**< Data Parity Error 1 Peek */
mbed_official 50:a417edff4437 652 #define _USART_RXDOUBLEXP_PERRP1_SHIFT 30 /**< Shift value for USART_PERRP1 */
mbed_official 50:a417edff4437 653 #define _USART_RXDOUBLEXP_PERRP1_MASK 0x40000000UL /**< Bit mask for USART_PERRP1 */
mbed_official 50:a417edff4437 654 #define _USART_RXDOUBLEXP_PERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */
mbed_official 50:a417edff4437 655 #define USART_RXDOUBLEXP_PERRP1_DEFAULT (_USART_RXDOUBLEXP_PERRP1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */
mbed_official 50:a417edff4437 656 #define USART_RXDOUBLEXP_FERRP1 (0x1UL << 31) /**< Data Framing Error 1 Peek */
mbed_official 50:a417edff4437 657 #define _USART_RXDOUBLEXP_FERRP1_SHIFT 31 /**< Shift value for USART_FERRP1 */
mbed_official 50:a417edff4437 658 #define _USART_RXDOUBLEXP_FERRP1_MASK 0x80000000UL /**< Bit mask for USART_FERRP1 */
mbed_official 50:a417edff4437 659 #define _USART_RXDOUBLEXP_FERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */
mbed_official 50:a417edff4437 660 #define USART_RXDOUBLEXP_FERRP1_DEFAULT (_USART_RXDOUBLEXP_FERRP1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */
mbed_official 50:a417edff4437 661
mbed_official 50:a417edff4437 662 /* Bit fields for USART TXDATAX */
mbed_official 50:a417edff4437 663 #define _USART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATAX */
mbed_official 50:a417edff4437 664 #define _USART_TXDATAX_MASK 0x0000F9FFUL /**< Mask for USART_TXDATAX */
mbed_official 50:a417edff4437 665 #define _USART_TXDATAX_TXDATAX_SHIFT 0 /**< Shift value for USART_TXDATAX */
mbed_official 50:a417edff4437 666 #define _USART_TXDATAX_TXDATAX_MASK 0x1FFUL /**< Bit mask for USART_TXDATAX */
mbed_official 50:a417edff4437 667 #define _USART_TXDATAX_TXDATAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */
mbed_official 50:a417edff4437 668 #define USART_TXDATAX_TXDATAX_DEFAULT (_USART_TXDATAX_TXDATAX_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATAX */
mbed_official 50:a417edff4437 669 #define USART_TXDATAX_UBRXAT (0x1UL << 11) /**< Unblock RX After Transmission */
mbed_official 50:a417edff4437 670 #define _USART_TXDATAX_UBRXAT_SHIFT 11 /**< Shift value for USART_UBRXAT */
mbed_official 50:a417edff4437 671 #define _USART_TXDATAX_UBRXAT_MASK 0x800UL /**< Bit mask for USART_UBRXAT */
mbed_official 50:a417edff4437 672 #define _USART_TXDATAX_UBRXAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */
mbed_official 50:a417edff4437 673 #define USART_TXDATAX_UBRXAT_DEFAULT (_USART_TXDATAX_UBRXAT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDATAX */
mbed_official 50:a417edff4437 674 #define USART_TXDATAX_TXTRIAT (0x1UL << 12) /**< Set TXTRI After Transmission */
mbed_official 50:a417edff4437 675 #define _USART_TXDATAX_TXTRIAT_SHIFT 12 /**< Shift value for USART_TXTRIAT */
mbed_official 50:a417edff4437 676 #define _USART_TXDATAX_TXTRIAT_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT */
mbed_official 50:a417edff4437 677 #define _USART_TXDATAX_TXTRIAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */
mbed_official 50:a417edff4437 678 #define USART_TXDATAX_TXTRIAT_DEFAULT (_USART_TXDATAX_TXTRIAT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDATAX */
mbed_official 50:a417edff4437 679 #define USART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data As Break */
mbed_official 50:a417edff4437 680 #define _USART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for USART_TXBREAK */
mbed_official 50:a417edff4437 681 #define _USART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for USART_TXBREAK */
mbed_official 50:a417edff4437 682 #define _USART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */
mbed_official 50:a417edff4437 683 #define USART_TXDATAX_TXBREAK_DEFAULT (_USART_TXDATAX_TXBREAK_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDATAX */
mbed_official 50:a417edff4437 684 #define USART_TXDATAX_TXDISAT (0x1UL << 14) /**< Clear TXEN After Transmission */
mbed_official 50:a417edff4437 685 #define _USART_TXDATAX_TXDISAT_SHIFT 14 /**< Shift value for USART_TXDISAT */
mbed_official 50:a417edff4437 686 #define _USART_TXDATAX_TXDISAT_MASK 0x4000UL /**< Bit mask for USART_TXDISAT */
mbed_official 50:a417edff4437 687 #define _USART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */
mbed_official 50:a417edff4437 688 #define USART_TXDATAX_TXDISAT_DEFAULT (_USART_TXDATAX_TXDISAT_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDATAX */
mbed_official 50:a417edff4437 689 #define USART_TXDATAX_RXENAT (0x1UL << 15) /**< Enable RX After Transmission */
mbed_official 50:a417edff4437 690 #define _USART_TXDATAX_RXENAT_SHIFT 15 /**< Shift value for USART_RXENAT */
mbed_official 50:a417edff4437 691 #define _USART_TXDATAX_RXENAT_MASK 0x8000UL /**< Bit mask for USART_RXENAT */
mbed_official 50:a417edff4437 692 #define _USART_TXDATAX_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */
mbed_official 50:a417edff4437 693 #define USART_TXDATAX_RXENAT_DEFAULT (_USART_TXDATAX_RXENAT_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDATAX */
mbed_official 50:a417edff4437 694
mbed_official 50:a417edff4437 695 /* Bit fields for USART TXDATA */
mbed_official 50:a417edff4437 696 #define _USART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATA */
mbed_official 50:a417edff4437 697 #define _USART_TXDATA_MASK 0x000000FFUL /**< Mask for USART_TXDATA */
mbed_official 50:a417edff4437 698 #define _USART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for USART_TXDATA */
mbed_official 50:a417edff4437 699 #define _USART_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for USART_TXDATA */
mbed_official 50:a417edff4437 700 #define _USART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATA */
mbed_official 50:a417edff4437 701 #define USART_TXDATA_TXDATA_DEFAULT (_USART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATA */
mbed_official 50:a417edff4437 702
mbed_official 50:a417edff4437 703 /* Bit fields for USART TXDOUBLEX */
mbed_official 50:a417edff4437 704 #define _USART_TXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLEX */
mbed_official 50:a417edff4437 705 #define _USART_TXDOUBLEX_MASK 0xF9FFF9FFUL /**< Mask for USART_TXDOUBLEX */
mbed_official 50:a417edff4437 706 #define _USART_TXDOUBLEX_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */
mbed_official 50:a417edff4437 707 #define _USART_TXDOUBLEX_TXDATA0_MASK 0x1FFUL /**< Bit mask for USART_TXDATA0 */
mbed_official 50:a417edff4437 708 #define _USART_TXDOUBLEX_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
mbed_official 50:a417edff4437 709 #define USART_TXDOUBLEX_TXDATA0_DEFAULT (_USART_TXDOUBLEX_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
mbed_official 50:a417edff4437 710 #define USART_TXDOUBLEX_UBRXAT0 (0x1UL << 11) /**< Unblock RX After Transmission */
mbed_official 50:a417edff4437 711 #define _USART_TXDOUBLEX_UBRXAT0_SHIFT 11 /**< Shift value for USART_UBRXAT0 */
mbed_official 50:a417edff4437 712 #define _USART_TXDOUBLEX_UBRXAT0_MASK 0x800UL /**< Bit mask for USART_UBRXAT0 */
mbed_official 50:a417edff4437 713 #define _USART_TXDOUBLEX_UBRXAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
mbed_official 50:a417edff4437 714 #define USART_TXDOUBLEX_UBRXAT0_DEFAULT (_USART_TXDOUBLEX_UBRXAT0_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
mbed_official 50:a417edff4437 715 #define USART_TXDOUBLEX_TXTRIAT0 (0x1UL << 12) /**< Set TXTRI After Transmission */
mbed_official 50:a417edff4437 716 #define _USART_TXDOUBLEX_TXTRIAT0_SHIFT 12 /**< Shift value for USART_TXTRIAT0 */
mbed_official 50:a417edff4437 717 #define _USART_TXDOUBLEX_TXTRIAT0_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT0 */
mbed_official 50:a417edff4437 718 #define _USART_TXDOUBLEX_TXTRIAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
mbed_official 50:a417edff4437 719 #define USART_TXDOUBLEX_TXTRIAT0_DEFAULT (_USART_TXDOUBLEX_TXTRIAT0_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
mbed_official 50:a417edff4437 720 #define USART_TXDOUBLEX_TXBREAK0 (0x1UL << 13) /**< Transmit Data As Break */
mbed_official 50:a417edff4437 721 #define _USART_TXDOUBLEX_TXBREAK0_SHIFT 13 /**< Shift value for USART_TXBREAK0 */
mbed_official 50:a417edff4437 722 #define _USART_TXDOUBLEX_TXBREAK0_MASK 0x2000UL /**< Bit mask for USART_TXBREAK0 */
mbed_official 50:a417edff4437 723 #define _USART_TXDOUBLEX_TXBREAK0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
mbed_official 50:a417edff4437 724 #define USART_TXDOUBLEX_TXBREAK0_DEFAULT (_USART_TXDOUBLEX_TXBREAK0_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
mbed_official 50:a417edff4437 725 #define USART_TXDOUBLEX_TXDISAT0 (0x1UL << 14) /**< Clear TXEN After Transmission */
mbed_official 50:a417edff4437 726 #define _USART_TXDOUBLEX_TXDISAT0_SHIFT 14 /**< Shift value for USART_TXDISAT0 */
mbed_official 50:a417edff4437 727 #define _USART_TXDOUBLEX_TXDISAT0_MASK 0x4000UL /**< Bit mask for USART_TXDISAT0 */
mbed_official 50:a417edff4437 728 #define _USART_TXDOUBLEX_TXDISAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
mbed_official 50:a417edff4437 729 #define USART_TXDOUBLEX_TXDISAT0_DEFAULT (_USART_TXDOUBLEX_TXDISAT0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
mbed_official 50:a417edff4437 730 #define USART_TXDOUBLEX_RXENAT0 (0x1UL << 15) /**< Enable RX After Transmission */
mbed_official 50:a417edff4437 731 #define _USART_TXDOUBLEX_RXENAT0_SHIFT 15 /**< Shift value for USART_RXENAT0 */
mbed_official 50:a417edff4437 732 #define _USART_TXDOUBLEX_RXENAT0_MASK 0x8000UL /**< Bit mask for USART_RXENAT0 */
mbed_official 50:a417edff4437 733 #define _USART_TXDOUBLEX_RXENAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
mbed_official 50:a417edff4437 734 #define USART_TXDOUBLEX_RXENAT0_DEFAULT (_USART_TXDOUBLEX_RXENAT0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
mbed_official 50:a417edff4437 735 #define _USART_TXDOUBLEX_TXDATA1_SHIFT 16 /**< Shift value for USART_TXDATA1 */
mbed_official 50:a417edff4437 736 #define _USART_TXDOUBLEX_TXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_TXDATA1 */
mbed_official 50:a417edff4437 737 #define _USART_TXDOUBLEX_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
mbed_official 50:a417edff4437 738 #define USART_TXDOUBLEX_TXDATA1_DEFAULT (_USART_TXDOUBLEX_TXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
mbed_official 50:a417edff4437 739 #define USART_TXDOUBLEX_UBRXAT1 (0x1UL << 27) /**< Unblock RX After Transmission */
mbed_official 50:a417edff4437 740 #define _USART_TXDOUBLEX_UBRXAT1_SHIFT 27 /**< Shift value for USART_UBRXAT1 */
mbed_official 50:a417edff4437 741 #define _USART_TXDOUBLEX_UBRXAT1_MASK 0x8000000UL /**< Bit mask for USART_UBRXAT1 */
mbed_official 50:a417edff4437 742 #define _USART_TXDOUBLEX_UBRXAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
mbed_official 50:a417edff4437 743 #define USART_TXDOUBLEX_UBRXAT1_DEFAULT (_USART_TXDOUBLEX_UBRXAT1_DEFAULT << 27) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
mbed_official 50:a417edff4437 744 #define USART_TXDOUBLEX_TXTRIAT1 (0x1UL << 28) /**< Set TXTRI After Transmission */
mbed_official 50:a417edff4437 745 #define _USART_TXDOUBLEX_TXTRIAT1_SHIFT 28 /**< Shift value for USART_TXTRIAT1 */
mbed_official 50:a417edff4437 746 #define _USART_TXDOUBLEX_TXTRIAT1_MASK 0x10000000UL /**< Bit mask for USART_TXTRIAT1 */
mbed_official 50:a417edff4437 747 #define _USART_TXDOUBLEX_TXTRIAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
mbed_official 50:a417edff4437 748 #define USART_TXDOUBLEX_TXTRIAT1_DEFAULT (_USART_TXDOUBLEX_TXTRIAT1_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
mbed_official 50:a417edff4437 749 #define USART_TXDOUBLEX_TXBREAK1 (0x1UL << 29) /**< Transmit Data As Break */
mbed_official 50:a417edff4437 750 #define _USART_TXDOUBLEX_TXBREAK1_SHIFT 29 /**< Shift value for USART_TXBREAK1 */
mbed_official 50:a417edff4437 751 #define _USART_TXDOUBLEX_TXBREAK1_MASK 0x20000000UL /**< Bit mask for USART_TXBREAK1 */
mbed_official 50:a417edff4437 752 #define _USART_TXDOUBLEX_TXBREAK1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
mbed_official 50:a417edff4437 753 #define USART_TXDOUBLEX_TXBREAK1_DEFAULT (_USART_TXDOUBLEX_TXBREAK1_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
mbed_official 50:a417edff4437 754 #define USART_TXDOUBLEX_TXDISAT1 (0x1UL << 30) /**< Clear TXEN After Transmission */
mbed_official 50:a417edff4437 755 #define _USART_TXDOUBLEX_TXDISAT1_SHIFT 30 /**< Shift value for USART_TXDISAT1 */
mbed_official 50:a417edff4437 756 #define _USART_TXDOUBLEX_TXDISAT1_MASK 0x40000000UL /**< Bit mask for USART_TXDISAT1 */
mbed_official 50:a417edff4437 757 #define _USART_TXDOUBLEX_TXDISAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
mbed_official 50:a417edff4437 758 #define USART_TXDOUBLEX_TXDISAT1_DEFAULT (_USART_TXDOUBLEX_TXDISAT1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
mbed_official 50:a417edff4437 759 #define USART_TXDOUBLEX_RXENAT1 (0x1UL << 31) /**< Enable RX After Transmission */
mbed_official 50:a417edff4437 760 #define _USART_TXDOUBLEX_RXENAT1_SHIFT 31 /**< Shift value for USART_RXENAT1 */
mbed_official 50:a417edff4437 761 #define _USART_TXDOUBLEX_RXENAT1_MASK 0x80000000UL /**< Bit mask for USART_RXENAT1 */
mbed_official 50:a417edff4437 762 #define _USART_TXDOUBLEX_RXENAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
mbed_official 50:a417edff4437 763 #define USART_TXDOUBLEX_RXENAT1_DEFAULT (_USART_TXDOUBLEX_RXENAT1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
mbed_official 50:a417edff4437 764
mbed_official 50:a417edff4437 765 /* Bit fields for USART TXDOUBLE */
mbed_official 50:a417edff4437 766 #define _USART_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLE */
mbed_official 50:a417edff4437 767 #define _USART_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_TXDOUBLE */
mbed_official 50:a417edff4437 768 #define _USART_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */
mbed_official 50:a417edff4437 769 #define _USART_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for USART_TXDATA0 */
mbed_official 50:a417edff4437 770 #define _USART_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */
mbed_official 50:a417edff4437 771 #define USART_TXDOUBLE_TXDATA0_DEFAULT (_USART_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLE */
mbed_official 50:a417edff4437 772 #define _USART_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for USART_TXDATA1 */
mbed_official 50:a417edff4437 773 #define _USART_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for USART_TXDATA1 */
mbed_official 50:a417edff4437 774 #define _USART_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */
mbed_official 50:a417edff4437 775 #define USART_TXDOUBLE_TXDATA1_DEFAULT (_USART_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TXDOUBLE */
mbed_official 50:a417edff4437 776
mbed_official 50:a417edff4437 777 /* Bit fields for USART IF */
mbed_official 50:a417edff4437 778 #define _USART_IF_RESETVALUE 0x00000002UL /**< Default value for USART_IF */
mbed_official 50:a417edff4437 779 #define _USART_IF_MASK 0x0001FFFFUL /**< Mask for USART_IF */
mbed_official 50:a417edff4437 780 #define USART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */
mbed_official 50:a417edff4437 781 #define _USART_IF_TXC_SHIFT 0 /**< Shift value for USART_TXC */
mbed_official 50:a417edff4437 782 #define _USART_IF_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */
mbed_official 50:a417edff4437 783 #define _USART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
mbed_official 50:a417edff4437 784 #define USART_IF_TXC_DEFAULT (_USART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IF */
mbed_official 50:a417edff4437 785 #define USART_IF_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Flag */
mbed_official 50:a417edff4437 786 #define _USART_IF_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */
mbed_official 50:a417edff4437 787 #define _USART_IF_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */
mbed_official 50:a417edff4437 788 #define _USART_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_IF */
mbed_official 50:a417edff4437 789 #define USART_IF_TXBL_DEFAULT (_USART_IF_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IF */
mbed_official 50:a417edff4437 790 #define USART_IF_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Flag */
mbed_official 50:a417edff4437 791 #define _USART_IF_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */
mbed_official 50:a417edff4437 792 #define _USART_IF_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */
mbed_official 50:a417edff4437 793 #define _USART_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
mbed_official 50:a417edff4437 794 #define USART_IF_RXDATAV_DEFAULT (_USART_IF_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IF */
mbed_official 50:a417edff4437 795 #define USART_IF_RXFULL (0x1UL << 3) /**< RX Buffer Full Interrupt Flag */
mbed_official 50:a417edff4437 796 #define _USART_IF_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */
mbed_official 50:a417edff4437 797 #define _USART_IF_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */
mbed_official 50:a417edff4437 798 #define _USART_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
mbed_official 50:a417edff4437 799 #define USART_IF_RXFULL_DEFAULT (_USART_IF_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IF */
mbed_official 50:a417edff4437 800 #define USART_IF_RXOF (0x1UL << 4) /**< RX Overflow Interrupt Flag */
mbed_official 50:a417edff4437 801 #define _USART_IF_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */
mbed_official 50:a417edff4437 802 #define _USART_IF_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */
mbed_official 50:a417edff4437 803 #define _USART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
mbed_official 50:a417edff4437 804 #define USART_IF_RXOF_DEFAULT (_USART_IF_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IF */
mbed_official 50:a417edff4437 805 #define USART_IF_RXUF (0x1UL << 5) /**< RX Underflow Interrupt Flag */
mbed_official 50:a417edff4437 806 #define _USART_IF_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */
mbed_official 50:a417edff4437 807 #define _USART_IF_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */
mbed_official 50:a417edff4437 808 #define _USART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
mbed_official 50:a417edff4437 809 #define USART_IF_RXUF_DEFAULT (_USART_IF_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IF */
mbed_official 50:a417edff4437 810 #define USART_IF_TXOF (0x1UL << 6) /**< TX Overflow Interrupt Flag */
mbed_official 50:a417edff4437 811 #define _USART_IF_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */
mbed_official 50:a417edff4437 812 #define _USART_IF_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */
mbed_official 50:a417edff4437 813 #define _USART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
mbed_official 50:a417edff4437 814 #define USART_IF_TXOF_DEFAULT (_USART_IF_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IF */
mbed_official 50:a417edff4437 815 #define USART_IF_TXUF (0x1UL << 7) /**< TX Underflow Interrupt Flag */
mbed_official 50:a417edff4437 816 #define _USART_IF_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */
mbed_official 50:a417edff4437 817 #define _USART_IF_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */
mbed_official 50:a417edff4437 818 #define _USART_IF_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
mbed_official 50:a417edff4437 819 #define USART_IF_TXUF_DEFAULT (_USART_IF_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IF */
mbed_official 50:a417edff4437 820 #define USART_IF_PERR (0x1UL << 8) /**< Parity Error Interrupt Flag */
mbed_official 50:a417edff4437 821 #define _USART_IF_PERR_SHIFT 8 /**< Shift value for USART_PERR */
mbed_official 50:a417edff4437 822 #define _USART_IF_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */
mbed_official 50:a417edff4437 823 #define _USART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
mbed_official 50:a417edff4437 824 #define USART_IF_PERR_DEFAULT (_USART_IF_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IF */
mbed_official 50:a417edff4437 825 #define USART_IF_FERR (0x1UL << 9) /**< Framing Error Interrupt Flag */
mbed_official 50:a417edff4437 826 #define _USART_IF_FERR_SHIFT 9 /**< Shift value for USART_FERR */
mbed_official 50:a417edff4437 827 #define _USART_IF_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */
mbed_official 50:a417edff4437 828 #define _USART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
mbed_official 50:a417edff4437 829 #define USART_IF_FERR_DEFAULT (_USART_IF_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IF */
mbed_official 50:a417edff4437 830 #define USART_IF_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt Flag */
mbed_official 50:a417edff4437 831 #define _USART_IF_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */
mbed_official 50:a417edff4437 832 #define _USART_IF_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */
mbed_official 50:a417edff4437 833 #define _USART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
mbed_official 50:a417edff4437 834 #define USART_IF_MPAF_DEFAULT (_USART_IF_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IF */
mbed_official 50:a417edff4437 835 #define USART_IF_SSM (0x1UL << 11) /**< Slave-Select In Master Mode Interrupt Flag */
mbed_official 50:a417edff4437 836 #define _USART_IF_SSM_SHIFT 11 /**< Shift value for USART_SSM */
mbed_official 50:a417edff4437 837 #define _USART_IF_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */
mbed_official 50:a417edff4437 838 #define _USART_IF_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
mbed_official 50:a417edff4437 839 #define USART_IF_SSM_DEFAULT (_USART_IF_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IF */
mbed_official 50:a417edff4437 840 #define USART_IF_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Flag */
mbed_official 50:a417edff4437 841 #define _USART_IF_CCF_SHIFT 12 /**< Shift value for USART_CCF */
mbed_official 50:a417edff4437 842 #define _USART_IF_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */
mbed_official 50:a417edff4437 843 #define _USART_IF_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
mbed_official 50:a417edff4437 844 #define USART_IF_CCF_DEFAULT (_USART_IF_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IF */
mbed_official 50:a417edff4437 845 #define USART_IF_TXIDLE (0x1UL << 13) /**< TX Idle Interrupt Flag */
mbed_official 50:a417edff4437 846 #define _USART_IF_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */
mbed_official 50:a417edff4437 847 #define _USART_IF_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */
mbed_official 50:a417edff4437 848 #define _USART_IF_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
mbed_official 50:a417edff4437 849 #define USART_IF_TXIDLE_DEFAULT (_USART_IF_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IF */
mbed_official 50:a417edff4437 850 #define USART_IF_TCMP0 (0x1UL << 14) /**< Timer comparator 0 Interrupt Flag */
mbed_official 50:a417edff4437 851 #define _USART_IF_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */
mbed_official 50:a417edff4437 852 #define _USART_IF_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */
mbed_official 50:a417edff4437 853 #define _USART_IF_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
mbed_official 50:a417edff4437 854 #define USART_IF_TCMP0_DEFAULT (_USART_IF_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IF */
mbed_official 50:a417edff4437 855 #define USART_IF_TCMP1 (0x1UL << 15) /**< Timer comparator 1 Interrupt Flag */
mbed_official 50:a417edff4437 856 #define _USART_IF_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */
mbed_official 50:a417edff4437 857 #define _USART_IF_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */
mbed_official 50:a417edff4437 858 #define _USART_IF_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
mbed_official 50:a417edff4437 859 #define USART_IF_TCMP1_DEFAULT (_USART_IF_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IF */
mbed_official 50:a417edff4437 860 #define USART_IF_TCMP2 (0x1UL << 16) /**< Timer comparator 2 Interrupt Flag */
mbed_official 50:a417edff4437 861 #define _USART_IF_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */
mbed_official 50:a417edff4437 862 #define _USART_IF_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */
mbed_official 50:a417edff4437 863 #define _USART_IF_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
mbed_official 50:a417edff4437 864 #define USART_IF_TCMP2_DEFAULT (_USART_IF_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IF */
mbed_official 50:a417edff4437 865
mbed_official 50:a417edff4437 866 /* Bit fields for USART IFS */
mbed_official 50:a417edff4437 867 #define _USART_IFS_RESETVALUE 0x00000000UL /**< Default value for USART_IFS */
mbed_official 50:a417edff4437 868 #define _USART_IFS_MASK 0x0001FFF9UL /**< Mask for USART_IFS */
mbed_official 50:a417edff4437 869 #define USART_IFS_TXC (0x1UL << 0) /**< Set TXC Interrupt Flag */
mbed_official 50:a417edff4437 870 #define _USART_IFS_TXC_SHIFT 0 /**< Shift value for USART_TXC */
mbed_official 50:a417edff4437 871 #define _USART_IFS_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */
mbed_official 50:a417edff4437 872 #define _USART_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
mbed_official 50:a417edff4437 873 #define USART_IFS_TXC_DEFAULT (_USART_IFS_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IFS */
mbed_official 50:a417edff4437 874 #define USART_IFS_RXFULL (0x1UL << 3) /**< Set RXFULL Interrupt Flag */
mbed_official 50:a417edff4437 875 #define _USART_IFS_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */
mbed_official 50:a417edff4437 876 #define _USART_IFS_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */
mbed_official 50:a417edff4437 877 #define _USART_IFS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
mbed_official 50:a417edff4437 878 #define USART_IFS_RXFULL_DEFAULT (_USART_IFS_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IFS */
mbed_official 50:a417edff4437 879 #define USART_IFS_RXOF (0x1UL << 4) /**< Set RXOF Interrupt Flag */
mbed_official 50:a417edff4437 880 #define _USART_IFS_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */
mbed_official 50:a417edff4437 881 #define _USART_IFS_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */
mbed_official 50:a417edff4437 882 #define _USART_IFS_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
mbed_official 50:a417edff4437 883 #define USART_IFS_RXOF_DEFAULT (_USART_IFS_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IFS */
mbed_official 50:a417edff4437 884 #define USART_IFS_RXUF (0x1UL << 5) /**< Set RXUF Interrupt Flag */
mbed_official 50:a417edff4437 885 #define _USART_IFS_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */
mbed_official 50:a417edff4437 886 #define _USART_IFS_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */
mbed_official 50:a417edff4437 887 #define _USART_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
mbed_official 50:a417edff4437 888 #define USART_IFS_RXUF_DEFAULT (_USART_IFS_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IFS */
mbed_official 50:a417edff4437 889 #define USART_IFS_TXOF (0x1UL << 6) /**< Set TXOF Interrupt Flag */
mbed_official 50:a417edff4437 890 #define _USART_IFS_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */
mbed_official 50:a417edff4437 891 #define _USART_IFS_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */
mbed_official 50:a417edff4437 892 #define _USART_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
mbed_official 50:a417edff4437 893 #define USART_IFS_TXOF_DEFAULT (_USART_IFS_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IFS */
mbed_official 50:a417edff4437 894 #define USART_IFS_TXUF (0x1UL << 7) /**< Set TXUF Interrupt Flag */
mbed_official 50:a417edff4437 895 #define _USART_IFS_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */
mbed_official 50:a417edff4437 896 #define _USART_IFS_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */
mbed_official 50:a417edff4437 897 #define _USART_IFS_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
mbed_official 50:a417edff4437 898 #define USART_IFS_TXUF_DEFAULT (_USART_IFS_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IFS */
mbed_official 50:a417edff4437 899 #define USART_IFS_PERR (0x1UL << 8) /**< Set PERR Interrupt Flag */
mbed_official 50:a417edff4437 900 #define _USART_IFS_PERR_SHIFT 8 /**< Shift value for USART_PERR */
mbed_official 50:a417edff4437 901 #define _USART_IFS_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */
mbed_official 50:a417edff4437 902 #define _USART_IFS_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
mbed_official 50:a417edff4437 903 #define USART_IFS_PERR_DEFAULT (_USART_IFS_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IFS */
mbed_official 50:a417edff4437 904 #define USART_IFS_FERR (0x1UL << 9) /**< Set FERR Interrupt Flag */
mbed_official 50:a417edff4437 905 #define _USART_IFS_FERR_SHIFT 9 /**< Shift value for USART_FERR */
mbed_official 50:a417edff4437 906 #define _USART_IFS_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */
mbed_official 50:a417edff4437 907 #define _USART_IFS_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
mbed_official 50:a417edff4437 908 #define USART_IFS_FERR_DEFAULT (_USART_IFS_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IFS */
mbed_official 50:a417edff4437 909 #define USART_IFS_MPAF (0x1UL << 10) /**< Set MPAF Interrupt Flag */
mbed_official 50:a417edff4437 910 #define _USART_IFS_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */
mbed_official 50:a417edff4437 911 #define _USART_IFS_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */
mbed_official 50:a417edff4437 912 #define _USART_IFS_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
mbed_official 50:a417edff4437 913 #define USART_IFS_MPAF_DEFAULT (_USART_IFS_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IFS */
mbed_official 50:a417edff4437 914 #define USART_IFS_SSM (0x1UL << 11) /**< Set SSM Interrupt Flag */
mbed_official 50:a417edff4437 915 #define _USART_IFS_SSM_SHIFT 11 /**< Shift value for USART_SSM */
mbed_official 50:a417edff4437 916 #define _USART_IFS_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */
mbed_official 50:a417edff4437 917 #define _USART_IFS_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
mbed_official 50:a417edff4437 918 #define USART_IFS_SSM_DEFAULT (_USART_IFS_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IFS */
mbed_official 50:a417edff4437 919 #define USART_IFS_CCF (0x1UL << 12) /**< Set CCF Interrupt Flag */
mbed_official 50:a417edff4437 920 #define _USART_IFS_CCF_SHIFT 12 /**< Shift value for USART_CCF */
mbed_official 50:a417edff4437 921 #define _USART_IFS_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */
mbed_official 50:a417edff4437 922 #define _USART_IFS_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
mbed_official 50:a417edff4437 923 #define USART_IFS_CCF_DEFAULT (_USART_IFS_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IFS */
mbed_official 50:a417edff4437 924 #define USART_IFS_TXIDLE (0x1UL << 13) /**< Set TXIDLE Interrupt Flag */
mbed_official 50:a417edff4437 925 #define _USART_IFS_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */
mbed_official 50:a417edff4437 926 #define _USART_IFS_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */
mbed_official 50:a417edff4437 927 #define _USART_IFS_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
mbed_official 50:a417edff4437 928 #define USART_IFS_TXIDLE_DEFAULT (_USART_IFS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IFS */
mbed_official 50:a417edff4437 929 #define USART_IFS_TCMP0 (0x1UL << 14) /**< Set TCMP0 Interrupt Flag */
mbed_official 50:a417edff4437 930 #define _USART_IFS_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */
mbed_official 50:a417edff4437 931 #define _USART_IFS_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */
mbed_official 50:a417edff4437 932 #define _USART_IFS_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
mbed_official 50:a417edff4437 933 #define USART_IFS_TCMP0_DEFAULT (_USART_IFS_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IFS */
mbed_official 50:a417edff4437 934 #define USART_IFS_TCMP1 (0x1UL << 15) /**< Set TCMP1 Interrupt Flag */
mbed_official 50:a417edff4437 935 #define _USART_IFS_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */
mbed_official 50:a417edff4437 936 #define _USART_IFS_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */
mbed_official 50:a417edff4437 937 #define _USART_IFS_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
mbed_official 50:a417edff4437 938 #define USART_IFS_TCMP1_DEFAULT (_USART_IFS_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IFS */
mbed_official 50:a417edff4437 939 #define USART_IFS_TCMP2 (0x1UL << 16) /**< Set TCMP2 Interrupt Flag */
mbed_official 50:a417edff4437 940 #define _USART_IFS_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */
mbed_official 50:a417edff4437 941 #define _USART_IFS_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */
mbed_official 50:a417edff4437 942 #define _USART_IFS_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
mbed_official 50:a417edff4437 943 #define USART_IFS_TCMP2_DEFAULT (_USART_IFS_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IFS */
mbed_official 50:a417edff4437 944
mbed_official 50:a417edff4437 945 /* Bit fields for USART IFC */
mbed_official 50:a417edff4437 946 #define _USART_IFC_RESETVALUE 0x00000000UL /**< Default value for USART_IFC */
mbed_official 50:a417edff4437 947 #define _USART_IFC_MASK 0x0001FFF9UL /**< Mask for USART_IFC */
mbed_official 50:a417edff4437 948 #define USART_IFC_TXC (0x1UL << 0) /**< Clear TXC Interrupt Flag */
mbed_official 50:a417edff4437 949 #define _USART_IFC_TXC_SHIFT 0 /**< Shift value for USART_TXC */
mbed_official 50:a417edff4437 950 #define _USART_IFC_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */
mbed_official 50:a417edff4437 951 #define _USART_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
mbed_official 50:a417edff4437 952 #define USART_IFC_TXC_DEFAULT (_USART_IFC_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IFC */
mbed_official 50:a417edff4437 953 #define USART_IFC_RXFULL (0x1UL << 3) /**< Clear RXFULL Interrupt Flag */
mbed_official 50:a417edff4437 954 #define _USART_IFC_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */
mbed_official 50:a417edff4437 955 #define _USART_IFC_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */
mbed_official 50:a417edff4437 956 #define _USART_IFC_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
mbed_official 50:a417edff4437 957 #define USART_IFC_RXFULL_DEFAULT (_USART_IFC_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IFC */
mbed_official 50:a417edff4437 958 #define USART_IFC_RXOF (0x1UL << 4) /**< Clear RXOF Interrupt Flag */
mbed_official 50:a417edff4437 959 #define _USART_IFC_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */
mbed_official 50:a417edff4437 960 #define _USART_IFC_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */
mbed_official 50:a417edff4437 961 #define _USART_IFC_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
mbed_official 50:a417edff4437 962 #define USART_IFC_RXOF_DEFAULT (_USART_IFC_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IFC */
mbed_official 50:a417edff4437 963 #define USART_IFC_RXUF (0x1UL << 5) /**< Clear RXUF Interrupt Flag */
mbed_official 50:a417edff4437 964 #define _USART_IFC_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */
mbed_official 50:a417edff4437 965 #define _USART_IFC_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */
mbed_official 50:a417edff4437 966 #define _USART_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
mbed_official 50:a417edff4437 967 #define USART_IFC_RXUF_DEFAULT (_USART_IFC_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IFC */
mbed_official 50:a417edff4437 968 #define USART_IFC_TXOF (0x1UL << 6) /**< Clear TXOF Interrupt Flag */
mbed_official 50:a417edff4437 969 #define _USART_IFC_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */
mbed_official 50:a417edff4437 970 #define _USART_IFC_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */
mbed_official 50:a417edff4437 971 #define _USART_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
mbed_official 50:a417edff4437 972 #define USART_IFC_TXOF_DEFAULT (_USART_IFC_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IFC */
mbed_official 50:a417edff4437 973 #define USART_IFC_TXUF (0x1UL << 7) /**< Clear TXUF Interrupt Flag */
mbed_official 50:a417edff4437 974 #define _USART_IFC_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */
mbed_official 50:a417edff4437 975 #define _USART_IFC_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */
mbed_official 50:a417edff4437 976 #define _USART_IFC_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
mbed_official 50:a417edff4437 977 #define USART_IFC_TXUF_DEFAULT (_USART_IFC_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IFC */
mbed_official 50:a417edff4437 978 #define USART_IFC_PERR (0x1UL << 8) /**< Clear PERR Interrupt Flag */
mbed_official 50:a417edff4437 979 #define _USART_IFC_PERR_SHIFT 8 /**< Shift value for USART_PERR */
mbed_official 50:a417edff4437 980 #define _USART_IFC_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */
mbed_official 50:a417edff4437 981 #define _USART_IFC_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
mbed_official 50:a417edff4437 982 #define USART_IFC_PERR_DEFAULT (_USART_IFC_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IFC */
mbed_official 50:a417edff4437 983 #define USART_IFC_FERR (0x1UL << 9) /**< Clear FERR Interrupt Flag */
mbed_official 50:a417edff4437 984 #define _USART_IFC_FERR_SHIFT 9 /**< Shift value for USART_FERR */
mbed_official 50:a417edff4437 985 #define _USART_IFC_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */
mbed_official 50:a417edff4437 986 #define _USART_IFC_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
mbed_official 50:a417edff4437 987 #define USART_IFC_FERR_DEFAULT (_USART_IFC_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IFC */
mbed_official 50:a417edff4437 988 #define USART_IFC_MPAF (0x1UL << 10) /**< Clear MPAF Interrupt Flag */
mbed_official 50:a417edff4437 989 #define _USART_IFC_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */
mbed_official 50:a417edff4437 990 #define _USART_IFC_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */
mbed_official 50:a417edff4437 991 #define _USART_IFC_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
mbed_official 50:a417edff4437 992 #define USART_IFC_MPAF_DEFAULT (_USART_IFC_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IFC */
mbed_official 50:a417edff4437 993 #define USART_IFC_SSM (0x1UL << 11) /**< Clear SSM Interrupt Flag */
mbed_official 50:a417edff4437 994 #define _USART_IFC_SSM_SHIFT 11 /**< Shift value for USART_SSM */
mbed_official 50:a417edff4437 995 #define _USART_IFC_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */
mbed_official 50:a417edff4437 996 #define _USART_IFC_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
mbed_official 50:a417edff4437 997 #define USART_IFC_SSM_DEFAULT (_USART_IFC_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IFC */
mbed_official 50:a417edff4437 998 #define USART_IFC_CCF (0x1UL << 12) /**< Clear CCF Interrupt Flag */
mbed_official 50:a417edff4437 999 #define _USART_IFC_CCF_SHIFT 12 /**< Shift value for USART_CCF */
mbed_official 50:a417edff4437 1000 #define _USART_IFC_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */
mbed_official 50:a417edff4437 1001 #define _USART_IFC_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
mbed_official 50:a417edff4437 1002 #define USART_IFC_CCF_DEFAULT (_USART_IFC_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IFC */
mbed_official 50:a417edff4437 1003 #define USART_IFC_TXIDLE (0x1UL << 13) /**< Clear TXIDLE Interrupt Flag */
mbed_official 50:a417edff4437 1004 #define _USART_IFC_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */
mbed_official 50:a417edff4437 1005 #define _USART_IFC_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */
mbed_official 50:a417edff4437 1006 #define _USART_IFC_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
mbed_official 50:a417edff4437 1007 #define USART_IFC_TXIDLE_DEFAULT (_USART_IFC_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IFC */
mbed_official 50:a417edff4437 1008 #define USART_IFC_TCMP0 (0x1UL << 14) /**< Clear TCMP0 Interrupt Flag */
mbed_official 50:a417edff4437 1009 #define _USART_IFC_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */
mbed_official 50:a417edff4437 1010 #define _USART_IFC_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */
mbed_official 50:a417edff4437 1011 #define _USART_IFC_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
mbed_official 50:a417edff4437 1012 #define USART_IFC_TCMP0_DEFAULT (_USART_IFC_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IFC */
mbed_official 50:a417edff4437 1013 #define USART_IFC_TCMP1 (0x1UL << 15) /**< Clear TCMP1 Interrupt Flag */
mbed_official 50:a417edff4437 1014 #define _USART_IFC_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */
mbed_official 50:a417edff4437 1015 #define _USART_IFC_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */
mbed_official 50:a417edff4437 1016 #define _USART_IFC_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
mbed_official 50:a417edff4437 1017 #define USART_IFC_TCMP1_DEFAULT (_USART_IFC_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IFC */
mbed_official 50:a417edff4437 1018 #define USART_IFC_TCMP2 (0x1UL << 16) /**< Clear TCMP2 Interrupt Flag */
mbed_official 50:a417edff4437 1019 #define _USART_IFC_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */
mbed_official 50:a417edff4437 1020 #define _USART_IFC_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */
mbed_official 50:a417edff4437 1021 #define _USART_IFC_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
mbed_official 50:a417edff4437 1022 #define USART_IFC_TCMP2_DEFAULT (_USART_IFC_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IFC */
mbed_official 50:a417edff4437 1023
mbed_official 50:a417edff4437 1024 /* Bit fields for USART IEN */
mbed_official 50:a417edff4437 1025 #define _USART_IEN_RESETVALUE 0x00000000UL /**< Default value for USART_IEN */
mbed_official 50:a417edff4437 1026 #define _USART_IEN_MASK 0x0001FFFFUL /**< Mask for USART_IEN */
mbed_official 50:a417edff4437 1027 #define USART_IEN_TXC (0x1UL << 0) /**< TXC Interrupt Enable */
mbed_official 50:a417edff4437 1028 #define _USART_IEN_TXC_SHIFT 0 /**< Shift value for USART_TXC */
mbed_official 50:a417edff4437 1029 #define _USART_IEN_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */
mbed_official 50:a417edff4437 1030 #define _USART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
mbed_official 50:a417edff4437 1031 #define USART_IEN_TXC_DEFAULT (_USART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IEN */
mbed_official 50:a417edff4437 1032 #define USART_IEN_TXBL (0x1UL << 1) /**< TXBL Interrupt Enable */
mbed_official 50:a417edff4437 1033 #define _USART_IEN_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */
mbed_official 50:a417edff4437 1034 #define _USART_IEN_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */
mbed_official 50:a417edff4437 1035 #define _USART_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
mbed_official 50:a417edff4437 1036 #define USART_IEN_TXBL_DEFAULT (_USART_IEN_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IEN */
mbed_official 50:a417edff4437 1037 #define USART_IEN_RXDATAV (0x1UL << 2) /**< RXDATAV Interrupt Enable */
mbed_official 50:a417edff4437 1038 #define _USART_IEN_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */
mbed_official 50:a417edff4437 1039 #define _USART_IEN_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */
mbed_official 50:a417edff4437 1040 #define _USART_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
mbed_official 50:a417edff4437 1041 #define USART_IEN_RXDATAV_DEFAULT (_USART_IEN_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IEN */
mbed_official 50:a417edff4437 1042 #define USART_IEN_RXFULL (0x1UL << 3) /**< RXFULL Interrupt Enable */
mbed_official 50:a417edff4437 1043 #define _USART_IEN_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */
mbed_official 50:a417edff4437 1044 #define _USART_IEN_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */
mbed_official 50:a417edff4437 1045 #define _USART_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
mbed_official 50:a417edff4437 1046 #define USART_IEN_RXFULL_DEFAULT (_USART_IEN_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IEN */
mbed_official 50:a417edff4437 1047 #define USART_IEN_RXOF (0x1UL << 4) /**< RXOF Interrupt Enable */
mbed_official 50:a417edff4437 1048 #define _USART_IEN_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */
mbed_official 50:a417edff4437 1049 #define _USART_IEN_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */
mbed_official 50:a417edff4437 1050 #define _USART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
mbed_official 50:a417edff4437 1051 #define USART_IEN_RXOF_DEFAULT (_USART_IEN_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IEN */
mbed_official 50:a417edff4437 1052 #define USART_IEN_RXUF (0x1UL << 5) /**< RXUF Interrupt Enable */
mbed_official 50:a417edff4437 1053 #define _USART_IEN_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */
mbed_official 50:a417edff4437 1054 #define _USART_IEN_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */
mbed_official 50:a417edff4437 1055 #define _USART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
mbed_official 50:a417edff4437 1056 #define USART_IEN_RXUF_DEFAULT (_USART_IEN_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IEN */
mbed_official 50:a417edff4437 1057 #define USART_IEN_TXOF (0x1UL << 6) /**< TXOF Interrupt Enable */
mbed_official 50:a417edff4437 1058 #define _USART_IEN_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */
mbed_official 50:a417edff4437 1059 #define _USART_IEN_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */
mbed_official 50:a417edff4437 1060 #define _USART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
mbed_official 50:a417edff4437 1061 #define USART_IEN_TXOF_DEFAULT (_USART_IEN_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IEN */
mbed_official 50:a417edff4437 1062 #define USART_IEN_TXUF (0x1UL << 7) /**< TXUF Interrupt Enable */
mbed_official 50:a417edff4437 1063 #define _USART_IEN_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */
mbed_official 50:a417edff4437 1064 #define _USART_IEN_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */
mbed_official 50:a417edff4437 1065 #define _USART_IEN_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
mbed_official 50:a417edff4437 1066 #define USART_IEN_TXUF_DEFAULT (_USART_IEN_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IEN */
mbed_official 50:a417edff4437 1067 #define USART_IEN_PERR (0x1UL << 8) /**< PERR Interrupt Enable */
mbed_official 50:a417edff4437 1068 #define _USART_IEN_PERR_SHIFT 8 /**< Shift value for USART_PERR */
mbed_official 50:a417edff4437 1069 #define _USART_IEN_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */
mbed_official 50:a417edff4437 1070 #define _USART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
mbed_official 50:a417edff4437 1071 #define USART_IEN_PERR_DEFAULT (_USART_IEN_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IEN */
mbed_official 50:a417edff4437 1072 #define USART_IEN_FERR (0x1UL << 9) /**< FERR Interrupt Enable */
mbed_official 50:a417edff4437 1073 #define _USART_IEN_FERR_SHIFT 9 /**< Shift value for USART_FERR */
mbed_official 50:a417edff4437 1074 #define _USART_IEN_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */
mbed_official 50:a417edff4437 1075 #define _USART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
mbed_official 50:a417edff4437 1076 #define USART_IEN_FERR_DEFAULT (_USART_IEN_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IEN */
mbed_official 50:a417edff4437 1077 #define USART_IEN_MPAF (0x1UL << 10) /**< MPAF Interrupt Enable */
mbed_official 50:a417edff4437 1078 #define _USART_IEN_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */
mbed_official 50:a417edff4437 1079 #define _USART_IEN_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */
mbed_official 50:a417edff4437 1080 #define _USART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
mbed_official 50:a417edff4437 1081 #define USART_IEN_MPAF_DEFAULT (_USART_IEN_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IEN */
mbed_official 50:a417edff4437 1082 #define USART_IEN_SSM (0x1UL << 11) /**< SSM Interrupt Enable */
mbed_official 50:a417edff4437 1083 #define _USART_IEN_SSM_SHIFT 11 /**< Shift value for USART_SSM */
mbed_official 50:a417edff4437 1084 #define _USART_IEN_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */
mbed_official 50:a417edff4437 1085 #define _USART_IEN_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
mbed_official 50:a417edff4437 1086 #define USART_IEN_SSM_DEFAULT (_USART_IEN_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IEN */
mbed_official 50:a417edff4437 1087 #define USART_IEN_CCF (0x1UL << 12) /**< CCF Interrupt Enable */
mbed_official 50:a417edff4437 1088 #define _USART_IEN_CCF_SHIFT 12 /**< Shift value for USART_CCF */
mbed_official 50:a417edff4437 1089 #define _USART_IEN_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */
mbed_official 50:a417edff4437 1090 #define _USART_IEN_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
mbed_official 50:a417edff4437 1091 #define USART_IEN_CCF_DEFAULT (_USART_IEN_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IEN */
mbed_official 50:a417edff4437 1092 #define USART_IEN_TXIDLE (0x1UL << 13) /**< TXIDLE Interrupt Enable */
mbed_official 50:a417edff4437 1093 #define _USART_IEN_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */
mbed_official 50:a417edff4437 1094 #define _USART_IEN_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */
mbed_official 50:a417edff4437 1095 #define _USART_IEN_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
mbed_official 50:a417edff4437 1096 #define USART_IEN_TXIDLE_DEFAULT (_USART_IEN_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IEN */
mbed_official 50:a417edff4437 1097 #define USART_IEN_TCMP0 (0x1UL << 14) /**< TCMP0 Interrupt Enable */
mbed_official 50:a417edff4437 1098 #define _USART_IEN_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */
mbed_official 50:a417edff4437 1099 #define _USART_IEN_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */
mbed_official 50:a417edff4437 1100 #define _USART_IEN_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
mbed_official 50:a417edff4437 1101 #define USART_IEN_TCMP0_DEFAULT (_USART_IEN_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IEN */
mbed_official 50:a417edff4437 1102 #define USART_IEN_TCMP1 (0x1UL << 15) /**< TCMP1 Interrupt Enable */
mbed_official 50:a417edff4437 1103 #define _USART_IEN_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */
mbed_official 50:a417edff4437 1104 #define _USART_IEN_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */
mbed_official 50:a417edff4437 1105 #define _USART_IEN_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
mbed_official 50:a417edff4437 1106 #define USART_IEN_TCMP1_DEFAULT (_USART_IEN_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IEN */
mbed_official 50:a417edff4437 1107 #define USART_IEN_TCMP2 (0x1UL << 16) /**< TCMP2 Interrupt Enable */
mbed_official 50:a417edff4437 1108 #define _USART_IEN_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */
mbed_official 50:a417edff4437 1109 #define _USART_IEN_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */
mbed_official 50:a417edff4437 1110 #define _USART_IEN_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
mbed_official 50:a417edff4437 1111 #define USART_IEN_TCMP2_DEFAULT (_USART_IEN_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IEN */
mbed_official 50:a417edff4437 1112
mbed_official 50:a417edff4437 1113 /* Bit fields for USART IRCTRL */
mbed_official 50:a417edff4437 1114 #define _USART_IRCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_IRCTRL */
mbed_official 50:a417edff4437 1115 #define _USART_IRCTRL_MASK 0x00000F8FUL /**< Mask for USART_IRCTRL */
mbed_official 50:a417edff4437 1116 #define USART_IRCTRL_IREN (0x1UL << 0) /**< Enable IrDA Module */
mbed_official 50:a417edff4437 1117 #define _USART_IRCTRL_IREN_SHIFT 0 /**< Shift value for USART_IREN */
mbed_official 50:a417edff4437 1118 #define _USART_IRCTRL_IREN_MASK 0x1UL /**< Bit mask for USART_IREN */
mbed_official 50:a417edff4437 1119 #define _USART_IRCTRL_IREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */
mbed_official 50:a417edff4437 1120 #define USART_IRCTRL_IREN_DEFAULT (_USART_IRCTRL_IREN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IRCTRL */
mbed_official 50:a417edff4437 1121 #define _USART_IRCTRL_IRPW_SHIFT 1 /**< Shift value for USART_IRPW */
mbed_official 50:a417edff4437 1122 #define _USART_IRCTRL_IRPW_MASK 0x6UL /**< Bit mask for USART_IRPW */
mbed_official 50:a417edff4437 1123 #define _USART_IRCTRL_IRPW_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */
mbed_official 50:a417edff4437 1124 #define _USART_IRCTRL_IRPW_ONE 0x00000000UL /**< Mode ONE for USART_IRCTRL */
mbed_official 50:a417edff4437 1125 #define _USART_IRCTRL_IRPW_TWO 0x00000001UL /**< Mode TWO for USART_IRCTRL */
mbed_official 50:a417edff4437 1126 #define _USART_IRCTRL_IRPW_THREE 0x00000002UL /**< Mode THREE for USART_IRCTRL */
mbed_official 50:a417edff4437 1127 #define _USART_IRCTRL_IRPW_FOUR 0x00000003UL /**< Mode FOUR for USART_IRCTRL */
mbed_official 50:a417edff4437 1128 #define USART_IRCTRL_IRPW_DEFAULT (_USART_IRCTRL_IRPW_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IRCTRL */
mbed_official 50:a417edff4437 1129 #define USART_IRCTRL_IRPW_ONE (_USART_IRCTRL_IRPW_ONE << 1) /**< Shifted mode ONE for USART_IRCTRL */
mbed_official 50:a417edff4437 1130 #define USART_IRCTRL_IRPW_TWO (_USART_IRCTRL_IRPW_TWO << 1) /**< Shifted mode TWO for USART_IRCTRL */
mbed_official 50:a417edff4437 1131 #define USART_IRCTRL_IRPW_THREE (_USART_IRCTRL_IRPW_THREE << 1) /**< Shifted mode THREE for USART_IRCTRL */
mbed_official 50:a417edff4437 1132 #define USART_IRCTRL_IRPW_FOUR (_USART_IRCTRL_IRPW_FOUR << 1) /**< Shifted mode FOUR for USART_IRCTRL */
mbed_official 50:a417edff4437 1133 #define USART_IRCTRL_IRFILT (0x1UL << 3) /**< IrDA RX Filter */
mbed_official 50:a417edff4437 1134 #define _USART_IRCTRL_IRFILT_SHIFT 3 /**< Shift value for USART_IRFILT */
mbed_official 50:a417edff4437 1135 #define _USART_IRCTRL_IRFILT_MASK 0x8UL /**< Bit mask for USART_IRFILT */
mbed_official 50:a417edff4437 1136 #define _USART_IRCTRL_IRFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */
mbed_official 50:a417edff4437 1137 #define USART_IRCTRL_IRFILT_DEFAULT (_USART_IRCTRL_IRFILT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IRCTRL */
mbed_official 50:a417edff4437 1138 #define USART_IRCTRL_IRPRSEN (0x1UL << 7) /**< IrDA PRS Channel Enable */
mbed_official 50:a417edff4437 1139 #define _USART_IRCTRL_IRPRSEN_SHIFT 7 /**< Shift value for USART_IRPRSEN */
mbed_official 50:a417edff4437 1140 #define _USART_IRCTRL_IRPRSEN_MASK 0x80UL /**< Bit mask for USART_IRPRSEN */
mbed_official 50:a417edff4437 1141 #define _USART_IRCTRL_IRPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */
mbed_official 50:a417edff4437 1142 #define USART_IRCTRL_IRPRSEN_DEFAULT (_USART_IRCTRL_IRPRSEN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IRCTRL */
mbed_official 50:a417edff4437 1143 #define _USART_IRCTRL_IRPRSSEL_SHIFT 8 /**< Shift value for USART_IRPRSSEL */
mbed_official 50:a417edff4437 1144 #define _USART_IRCTRL_IRPRSSEL_MASK 0xF00UL /**< Bit mask for USART_IRPRSSEL */
mbed_official 50:a417edff4437 1145 #define _USART_IRCTRL_IRPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */
mbed_official 50:a417edff4437 1146 #define _USART_IRCTRL_IRPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_IRCTRL */
mbed_official 50:a417edff4437 1147 #define _USART_IRCTRL_IRPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_IRCTRL */
mbed_official 50:a417edff4437 1148 #define _USART_IRCTRL_IRPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_IRCTRL */
mbed_official 50:a417edff4437 1149 #define _USART_IRCTRL_IRPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_IRCTRL */
mbed_official 50:a417edff4437 1150 #define _USART_IRCTRL_IRPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_IRCTRL */
mbed_official 50:a417edff4437 1151 #define _USART_IRCTRL_IRPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_IRCTRL */
mbed_official 50:a417edff4437 1152 #define _USART_IRCTRL_IRPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_IRCTRL */
mbed_official 50:a417edff4437 1153 #define _USART_IRCTRL_IRPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_IRCTRL */
mbed_official 50:a417edff4437 1154 #define _USART_IRCTRL_IRPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_IRCTRL */
mbed_official 50:a417edff4437 1155 #define _USART_IRCTRL_IRPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_IRCTRL */
mbed_official 50:a417edff4437 1156 #define _USART_IRCTRL_IRPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_IRCTRL */
mbed_official 50:a417edff4437 1157 #define _USART_IRCTRL_IRPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_IRCTRL */
mbed_official 50:a417edff4437 1158 #define USART_IRCTRL_IRPRSSEL_DEFAULT (_USART_IRCTRL_IRPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IRCTRL */
mbed_official 50:a417edff4437 1159 #define USART_IRCTRL_IRPRSSEL_PRSCH0 (_USART_IRCTRL_IRPRSSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for USART_IRCTRL */
mbed_official 50:a417edff4437 1160 #define USART_IRCTRL_IRPRSSEL_PRSCH1 (_USART_IRCTRL_IRPRSSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for USART_IRCTRL */
mbed_official 50:a417edff4437 1161 #define USART_IRCTRL_IRPRSSEL_PRSCH2 (_USART_IRCTRL_IRPRSSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for USART_IRCTRL */
mbed_official 50:a417edff4437 1162 #define USART_IRCTRL_IRPRSSEL_PRSCH3 (_USART_IRCTRL_IRPRSSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for USART_IRCTRL */
mbed_official 50:a417edff4437 1163 #define USART_IRCTRL_IRPRSSEL_PRSCH4 (_USART_IRCTRL_IRPRSSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for USART_IRCTRL */
mbed_official 50:a417edff4437 1164 #define USART_IRCTRL_IRPRSSEL_PRSCH5 (_USART_IRCTRL_IRPRSSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for USART_IRCTRL */
mbed_official 50:a417edff4437 1165 #define USART_IRCTRL_IRPRSSEL_PRSCH6 (_USART_IRCTRL_IRPRSSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for USART_IRCTRL */
mbed_official 50:a417edff4437 1166 #define USART_IRCTRL_IRPRSSEL_PRSCH7 (_USART_IRCTRL_IRPRSSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for USART_IRCTRL */
mbed_official 50:a417edff4437 1167 #define USART_IRCTRL_IRPRSSEL_PRSCH8 (_USART_IRCTRL_IRPRSSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for USART_IRCTRL */
mbed_official 50:a417edff4437 1168 #define USART_IRCTRL_IRPRSSEL_PRSCH9 (_USART_IRCTRL_IRPRSSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for USART_IRCTRL */
mbed_official 50:a417edff4437 1169 #define USART_IRCTRL_IRPRSSEL_PRSCH10 (_USART_IRCTRL_IRPRSSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for USART_IRCTRL */
mbed_official 50:a417edff4437 1170 #define USART_IRCTRL_IRPRSSEL_PRSCH11 (_USART_IRCTRL_IRPRSSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for USART_IRCTRL */
mbed_official 50:a417edff4437 1171
mbed_official 50:a417edff4437 1172 /* Bit fields for USART INPUT */
mbed_official 50:a417edff4437 1173 #define _USART_INPUT_RESETVALUE 0x00000000UL /**< Default value for USART_INPUT */
mbed_official 50:a417edff4437 1174 #define _USART_INPUT_MASK 0x00008F8FUL /**< Mask for USART_INPUT */
mbed_official 50:a417edff4437 1175 #define _USART_INPUT_RXPRSSEL_SHIFT 0 /**< Shift value for USART_RXPRSSEL */
mbed_official 50:a417edff4437 1176 #define _USART_INPUT_RXPRSSEL_MASK 0xFUL /**< Bit mask for USART_RXPRSSEL */
mbed_official 50:a417edff4437 1177 #define _USART_INPUT_RXPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */
mbed_official 50:a417edff4437 1178 #define _USART_INPUT_RXPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_INPUT */
mbed_official 50:a417edff4437 1179 #define _USART_INPUT_RXPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_INPUT */
mbed_official 50:a417edff4437 1180 #define _USART_INPUT_RXPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_INPUT */
mbed_official 50:a417edff4437 1181 #define _USART_INPUT_RXPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_INPUT */
mbed_official 50:a417edff4437 1182 #define _USART_INPUT_RXPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_INPUT */
mbed_official 50:a417edff4437 1183 #define _USART_INPUT_RXPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_INPUT */
mbed_official 50:a417edff4437 1184 #define _USART_INPUT_RXPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_INPUT */
mbed_official 50:a417edff4437 1185 #define _USART_INPUT_RXPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_INPUT */
mbed_official 50:a417edff4437 1186 #define _USART_INPUT_RXPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_INPUT */
mbed_official 50:a417edff4437 1187 #define _USART_INPUT_RXPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_INPUT */
mbed_official 50:a417edff4437 1188 #define _USART_INPUT_RXPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_INPUT */
mbed_official 50:a417edff4437 1189 #define _USART_INPUT_RXPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_INPUT */
mbed_official 50:a417edff4437 1190 #define USART_INPUT_RXPRSSEL_DEFAULT (_USART_INPUT_RXPRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_INPUT */
mbed_official 50:a417edff4437 1191 #define USART_INPUT_RXPRSSEL_PRSCH0 (_USART_INPUT_RXPRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for USART_INPUT */
mbed_official 50:a417edff4437 1192 #define USART_INPUT_RXPRSSEL_PRSCH1 (_USART_INPUT_RXPRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for USART_INPUT */
mbed_official 50:a417edff4437 1193 #define USART_INPUT_RXPRSSEL_PRSCH2 (_USART_INPUT_RXPRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for USART_INPUT */
mbed_official 50:a417edff4437 1194 #define USART_INPUT_RXPRSSEL_PRSCH3 (_USART_INPUT_RXPRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for USART_INPUT */
mbed_official 50:a417edff4437 1195 #define USART_INPUT_RXPRSSEL_PRSCH4 (_USART_INPUT_RXPRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for USART_INPUT */
mbed_official 50:a417edff4437 1196 #define USART_INPUT_RXPRSSEL_PRSCH5 (_USART_INPUT_RXPRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for USART_INPUT */
mbed_official 50:a417edff4437 1197 #define USART_INPUT_RXPRSSEL_PRSCH6 (_USART_INPUT_RXPRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for USART_INPUT */
mbed_official 50:a417edff4437 1198 #define USART_INPUT_RXPRSSEL_PRSCH7 (_USART_INPUT_RXPRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for USART_INPUT */
mbed_official 50:a417edff4437 1199 #define USART_INPUT_RXPRSSEL_PRSCH8 (_USART_INPUT_RXPRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for USART_INPUT */
mbed_official 50:a417edff4437 1200 #define USART_INPUT_RXPRSSEL_PRSCH9 (_USART_INPUT_RXPRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for USART_INPUT */
mbed_official 50:a417edff4437 1201 #define USART_INPUT_RXPRSSEL_PRSCH10 (_USART_INPUT_RXPRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for USART_INPUT */
mbed_official 50:a417edff4437 1202 #define USART_INPUT_RXPRSSEL_PRSCH11 (_USART_INPUT_RXPRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for USART_INPUT */
mbed_official 50:a417edff4437 1203 #define USART_INPUT_RXPRS (0x1UL << 7) /**< PRS RX Enable */
mbed_official 50:a417edff4437 1204 #define _USART_INPUT_RXPRS_SHIFT 7 /**< Shift value for USART_RXPRS */
mbed_official 50:a417edff4437 1205 #define _USART_INPUT_RXPRS_MASK 0x80UL /**< Bit mask for USART_RXPRS */
mbed_official 50:a417edff4437 1206 #define _USART_INPUT_RXPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */
mbed_official 50:a417edff4437 1207 #define USART_INPUT_RXPRS_DEFAULT (_USART_INPUT_RXPRS_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_INPUT */
mbed_official 50:a417edff4437 1208 #define _USART_INPUT_CLKPRSSEL_SHIFT 8 /**< Shift value for USART_CLKPRSSEL */
mbed_official 50:a417edff4437 1209 #define _USART_INPUT_CLKPRSSEL_MASK 0xF00UL /**< Bit mask for USART_CLKPRSSEL */
mbed_official 50:a417edff4437 1210 #define _USART_INPUT_CLKPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */
mbed_official 50:a417edff4437 1211 #define _USART_INPUT_CLKPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_INPUT */
mbed_official 50:a417edff4437 1212 #define _USART_INPUT_CLKPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_INPUT */
mbed_official 50:a417edff4437 1213 #define _USART_INPUT_CLKPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_INPUT */
mbed_official 50:a417edff4437 1214 #define _USART_INPUT_CLKPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_INPUT */
mbed_official 50:a417edff4437 1215 #define _USART_INPUT_CLKPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_INPUT */
mbed_official 50:a417edff4437 1216 #define _USART_INPUT_CLKPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_INPUT */
mbed_official 50:a417edff4437 1217 #define _USART_INPUT_CLKPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_INPUT */
mbed_official 50:a417edff4437 1218 #define _USART_INPUT_CLKPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_INPUT */
mbed_official 50:a417edff4437 1219 #define _USART_INPUT_CLKPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_INPUT */
mbed_official 50:a417edff4437 1220 #define _USART_INPUT_CLKPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_INPUT */
mbed_official 50:a417edff4437 1221 #define _USART_INPUT_CLKPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_INPUT */
mbed_official 50:a417edff4437 1222 #define _USART_INPUT_CLKPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_INPUT */
mbed_official 50:a417edff4437 1223 #define USART_INPUT_CLKPRSSEL_DEFAULT (_USART_INPUT_CLKPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_INPUT */
mbed_official 50:a417edff4437 1224 #define USART_INPUT_CLKPRSSEL_PRSCH0 (_USART_INPUT_CLKPRSSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for USART_INPUT */
mbed_official 50:a417edff4437 1225 #define USART_INPUT_CLKPRSSEL_PRSCH1 (_USART_INPUT_CLKPRSSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for USART_INPUT */
mbed_official 50:a417edff4437 1226 #define USART_INPUT_CLKPRSSEL_PRSCH2 (_USART_INPUT_CLKPRSSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for USART_INPUT */
mbed_official 50:a417edff4437 1227 #define USART_INPUT_CLKPRSSEL_PRSCH3 (_USART_INPUT_CLKPRSSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for USART_INPUT */
mbed_official 50:a417edff4437 1228 #define USART_INPUT_CLKPRSSEL_PRSCH4 (_USART_INPUT_CLKPRSSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for USART_INPUT */
mbed_official 50:a417edff4437 1229 #define USART_INPUT_CLKPRSSEL_PRSCH5 (_USART_INPUT_CLKPRSSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for USART_INPUT */
mbed_official 50:a417edff4437 1230 #define USART_INPUT_CLKPRSSEL_PRSCH6 (_USART_INPUT_CLKPRSSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for USART_INPUT */
mbed_official 50:a417edff4437 1231 #define USART_INPUT_CLKPRSSEL_PRSCH7 (_USART_INPUT_CLKPRSSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for USART_INPUT */
mbed_official 50:a417edff4437 1232 #define USART_INPUT_CLKPRSSEL_PRSCH8 (_USART_INPUT_CLKPRSSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for USART_INPUT */
mbed_official 50:a417edff4437 1233 #define USART_INPUT_CLKPRSSEL_PRSCH9 (_USART_INPUT_CLKPRSSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for USART_INPUT */
mbed_official 50:a417edff4437 1234 #define USART_INPUT_CLKPRSSEL_PRSCH10 (_USART_INPUT_CLKPRSSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for USART_INPUT */
mbed_official 50:a417edff4437 1235 #define USART_INPUT_CLKPRSSEL_PRSCH11 (_USART_INPUT_CLKPRSSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for USART_INPUT */
mbed_official 50:a417edff4437 1236 #define USART_INPUT_CLKPRS (0x1UL << 15) /**< PRS CLK Enable */
mbed_official 50:a417edff4437 1237 #define _USART_INPUT_CLKPRS_SHIFT 15 /**< Shift value for USART_CLKPRS */
mbed_official 50:a417edff4437 1238 #define _USART_INPUT_CLKPRS_MASK 0x8000UL /**< Bit mask for USART_CLKPRS */
mbed_official 50:a417edff4437 1239 #define _USART_INPUT_CLKPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */
mbed_official 50:a417edff4437 1240 #define USART_INPUT_CLKPRS_DEFAULT (_USART_INPUT_CLKPRS_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_INPUT */
mbed_official 50:a417edff4437 1241
mbed_official 50:a417edff4437 1242 /* Bit fields for USART I2SCTRL */
mbed_official 50:a417edff4437 1243 #define _USART_I2SCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_I2SCTRL */
mbed_official 50:a417edff4437 1244 #define _USART_I2SCTRL_MASK 0x0000071FUL /**< Mask for USART_I2SCTRL */
mbed_official 50:a417edff4437 1245 #define USART_I2SCTRL_EN (0x1UL << 0) /**< Enable I2S Mode */
mbed_official 50:a417edff4437 1246 #define _USART_I2SCTRL_EN_SHIFT 0 /**< Shift value for USART_EN */
mbed_official 50:a417edff4437 1247 #define _USART_I2SCTRL_EN_MASK 0x1UL /**< Bit mask for USART_EN */
mbed_official 50:a417edff4437 1248 #define _USART_I2SCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */
mbed_official 50:a417edff4437 1249 #define USART_I2SCTRL_EN_DEFAULT (_USART_I2SCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_I2SCTRL */
mbed_official 50:a417edff4437 1250 #define USART_I2SCTRL_MONO (0x1UL << 1) /**< Stero or Mono */
mbed_official 50:a417edff4437 1251 #define _USART_I2SCTRL_MONO_SHIFT 1 /**< Shift value for USART_MONO */
mbed_official 50:a417edff4437 1252 #define _USART_I2SCTRL_MONO_MASK 0x2UL /**< Bit mask for USART_MONO */
mbed_official 50:a417edff4437 1253 #define _USART_I2SCTRL_MONO_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */
mbed_official 50:a417edff4437 1254 #define USART_I2SCTRL_MONO_DEFAULT (_USART_I2SCTRL_MONO_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_I2SCTRL */
mbed_official 50:a417edff4437 1255 #define USART_I2SCTRL_JUSTIFY (0x1UL << 2) /**< Justification of I2S Data */
mbed_official 50:a417edff4437 1256 #define _USART_I2SCTRL_JUSTIFY_SHIFT 2 /**< Shift value for USART_JUSTIFY */
mbed_official 50:a417edff4437 1257 #define _USART_I2SCTRL_JUSTIFY_MASK 0x4UL /**< Bit mask for USART_JUSTIFY */
mbed_official 50:a417edff4437 1258 #define _USART_I2SCTRL_JUSTIFY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */
mbed_official 50:a417edff4437 1259 #define _USART_I2SCTRL_JUSTIFY_LEFT 0x00000000UL /**< Mode LEFT for USART_I2SCTRL */
mbed_official 50:a417edff4437 1260 #define _USART_I2SCTRL_JUSTIFY_RIGHT 0x00000001UL /**< Mode RIGHT for USART_I2SCTRL */
mbed_official 50:a417edff4437 1261 #define USART_I2SCTRL_JUSTIFY_DEFAULT (_USART_I2SCTRL_JUSTIFY_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_I2SCTRL */
mbed_official 50:a417edff4437 1262 #define USART_I2SCTRL_JUSTIFY_LEFT (_USART_I2SCTRL_JUSTIFY_LEFT << 2) /**< Shifted mode LEFT for USART_I2SCTRL */
mbed_official 50:a417edff4437 1263 #define USART_I2SCTRL_JUSTIFY_RIGHT (_USART_I2SCTRL_JUSTIFY_RIGHT << 2) /**< Shifted mode RIGHT for USART_I2SCTRL */
mbed_official 50:a417edff4437 1264 #define USART_I2SCTRL_DMASPLIT (0x1UL << 3) /**< Separate DMA Request For Left/Right Data */
mbed_official 50:a417edff4437 1265 #define _USART_I2SCTRL_DMASPLIT_SHIFT 3 /**< Shift value for USART_DMASPLIT */
mbed_official 50:a417edff4437 1266 #define _USART_I2SCTRL_DMASPLIT_MASK 0x8UL /**< Bit mask for USART_DMASPLIT */
mbed_official 50:a417edff4437 1267 #define _USART_I2SCTRL_DMASPLIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */
mbed_official 50:a417edff4437 1268 #define USART_I2SCTRL_DMASPLIT_DEFAULT (_USART_I2SCTRL_DMASPLIT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_I2SCTRL */
mbed_official 50:a417edff4437 1269 #define USART_I2SCTRL_DELAY (0x1UL << 4) /**< Delay on I2S data */
mbed_official 50:a417edff4437 1270 #define _USART_I2SCTRL_DELAY_SHIFT 4 /**< Shift value for USART_DELAY */
mbed_official 50:a417edff4437 1271 #define _USART_I2SCTRL_DELAY_MASK 0x10UL /**< Bit mask for USART_DELAY */
mbed_official 50:a417edff4437 1272 #define _USART_I2SCTRL_DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */
mbed_official 50:a417edff4437 1273 #define USART_I2SCTRL_DELAY_DEFAULT (_USART_I2SCTRL_DELAY_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_I2SCTRL */
mbed_official 50:a417edff4437 1274 #define _USART_I2SCTRL_FORMAT_SHIFT 8 /**< Shift value for USART_FORMAT */
mbed_official 50:a417edff4437 1275 #define _USART_I2SCTRL_FORMAT_MASK 0x700UL /**< Bit mask for USART_FORMAT */
mbed_official 50:a417edff4437 1276 #define _USART_I2SCTRL_FORMAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */
mbed_official 50:a417edff4437 1277 #define _USART_I2SCTRL_FORMAT_W32D32 0x00000000UL /**< Mode W32D32 for USART_I2SCTRL */
mbed_official 50:a417edff4437 1278 #define _USART_I2SCTRL_FORMAT_W32D24M 0x00000001UL /**< Mode W32D24M for USART_I2SCTRL */
mbed_official 50:a417edff4437 1279 #define _USART_I2SCTRL_FORMAT_W32D24 0x00000002UL /**< Mode W32D24 for USART_I2SCTRL */
mbed_official 50:a417edff4437 1280 #define _USART_I2SCTRL_FORMAT_W32D16 0x00000003UL /**< Mode W32D16 for USART_I2SCTRL */
mbed_official 50:a417edff4437 1281 #define _USART_I2SCTRL_FORMAT_W32D8 0x00000004UL /**< Mode W32D8 for USART_I2SCTRL */
mbed_official 50:a417edff4437 1282 #define _USART_I2SCTRL_FORMAT_W16D16 0x00000005UL /**< Mode W16D16 for USART_I2SCTRL */
mbed_official 50:a417edff4437 1283 #define _USART_I2SCTRL_FORMAT_W16D8 0x00000006UL /**< Mode W16D8 for USART_I2SCTRL */
mbed_official 50:a417edff4437 1284 #define _USART_I2SCTRL_FORMAT_W8D8 0x00000007UL /**< Mode W8D8 for USART_I2SCTRL */
mbed_official 50:a417edff4437 1285 #define USART_I2SCTRL_FORMAT_DEFAULT (_USART_I2SCTRL_FORMAT_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_I2SCTRL */
mbed_official 50:a417edff4437 1286 #define USART_I2SCTRL_FORMAT_W32D32 (_USART_I2SCTRL_FORMAT_W32D32 << 8) /**< Shifted mode W32D32 for USART_I2SCTRL */
mbed_official 50:a417edff4437 1287 #define USART_I2SCTRL_FORMAT_W32D24M (_USART_I2SCTRL_FORMAT_W32D24M << 8) /**< Shifted mode W32D24M for USART_I2SCTRL */
mbed_official 50:a417edff4437 1288 #define USART_I2SCTRL_FORMAT_W32D24 (_USART_I2SCTRL_FORMAT_W32D24 << 8) /**< Shifted mode W32D24 for USART_I2SCTRL */
mbed_official 50:a417edff4437 1289 #define USART_I2SCTRL_FORMAT_W32D16 (_USART_I2SCTRL_FORMAT_W32D16 << 8) /**< Shifted mode W32D16 for USART_I2SCTRL */
mbed_official 50:a417edff4437 1290 #define USART_I2SCTRL_FORMAT_W32D8 (_USART_I2SCTRL_FORMAT_W32D8 << 8) /**< Shifted mode W32D8 for USART_I2SCTRL */
mbed_official 50:a417edff4437 1291 #define USART_I2SCTRL_FORMAT_W16D16 (_USART_I2SCTRL_FORMAT_W16D16 << 8) /**< Shifted mode W16D16 for USART_I2SCTRL */
mbed_official 50:a417edff4437 1292 #define USART_I2SCTRL_FORMAT_W16D8 (_USART_I2SCTRL_FORMAT_W16D8 << 8) /**< Shifted mode W16D8 for USART_I2SCTRL */
mbed_official 50:a417edff4437 1293 #define USART_I2SCTRL_FORMAT_W8D8 (_USART_I2SCTRL_FORMAT_W8D8 << 8) /**< Shifted mode W8D8 for USART_I2SCTRL */
mbed_official 50:a417edff4437 1294
mbed_official 50:a417edff4437 1295 /* Bit fields for USART TIMING */
mbed_official 50:a417edff4437 1296 #define _USART_TIMING_RESETVALUE 0x00000000UL /**< Default value for USART_TIMING */
mbed_official 50:a417edff4437 1297 #define _USART_TIMING_MASK 0x77770000UL /**< Mask for USART_TIMING */
mbed_official 50:a417edff4437 1298 #define _USART_TIMING_TXDELAY_SHIFT 16 /**< Shift value for USART_TXDELAY */
mbed_official 50:a417edff4437 1299 #define _USART_TIMING_TXDELAY_MASK 0x70000UL /**< Bit mask for USART_TXDELAY */
mbed_official 50:a417edff4437 1300 #define _USART_TIMING_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */
mbed_official 50:a417edff4437 1301 #define _USART_TIMING_TXDELAY_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMING */
mbed_official 50:a417edff4437 1302 #define _USART_TIMING_TXDELAY_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */
mbed_official 50:a417edff4437 1303 #define _USART_TIMING_TXDELAY_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */
mbed_official 50:a417edff4437 1304 #define _USART_TIMING_TXDELAY_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */
mbed_official 50:a417edff4437 1305 #define _USART_TIMING_TXDELAY_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */
mbed_official 50:a417edff4437 1306 #define _USART_TIMING_TXDELAY_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */
mbed_official 50:a417edff4437 1307 #define _USART_TIMING_TXDELAY_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */
mbed_official 50:a417edff4437 1308 #define _USART_TIMING_TXDELAY_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */
mbed_official 50:a417edff4437 1309 #define USART_TIMING_TXDELAY_DEFAULT (_USART_TIMING_TXDELAY_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMING */
mbed_official 50:a417edff4437 1310 #define USART_TIMING_TXDELAY_DISABLE (_USART_TIMING_TXDELAY_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMING */
mbed_official 50:a417edff4437 1311 #define USART_TIMING_TXDELAY_ONE (_USART_TIMING_TXDELAY_ONE << 16) /**< Shifted mode ONE for USART_TIMING */
mbed_official 50:a417edff4437 1312 #define USART_TIMING_TXDELAY_TWO (_USART_TIMING_TXDELAY_TWO << 16) /**< Shifted mode TWO for USART_TIMING */
mbed_official 50:a417edff4437 1313 #define USART_TIMING_TXDELAY_THREE (_USART_TIMING_TXDELAY_THREE << 16) /**< Shifted mode THREE for USART_TIMING */
mbed_official 50:a417edff4437 1314 #define USART_TIMING_TXDELAY_SEVEN (_USART_TIMING_TXDELAY_SEVEN << 16) /**< Shifted mode SEVEN for USART_TIMING */
mbed_official 50:a417edff4437 1315 #define USART_TIMING_TXDELAY_TCMP0 (_USART_TIMING_TXDELAY_TCMP0 << 16) /**< Shifted mode TCMP0 for USART_TIMING */
mbed_official 50:a417edff4437 1316 #define USART_TIMING_TXDELAY_TCMP1 (_USART_TIMING_TXDELAY_TCMP1 << 16) /**< Shifted mode TCMP1 for USART_TIMING */
mbed_official 50:a417edff4437 1317 #define USART_TIMING_TXDELAY_TCMP2 (_USART_TIMING_TXDELAY_TCMP2 << 16) /**< Shifted mode TCMP2 for USART_TIMING */
mbed_official 50:a417edff4437 1318 #define _USART_TIMING_CSSETUP_SHIFT 20 /**< Shift value for USART_CSSETUP */
mbed_official 50:a417edff4437 1319 #define _USART_TIMING_CSSETUP_MASK 0x700000UL /**< Bit mask for USART_CSSETUP */
mbed_official 50:a417edff4437 1320 #define _USART_TIMING_CSSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */
mbed_official 50:a417edff4437 1321 #define _USART_TIMING_CSSETUP_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */
mbed_official 50:a417edff4437 1322 #define _USART_TIMING_CSSETUP_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */
mbed_official 50:a417edff4437 1323 #define _USART_TIMING_CSSETUP_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */
mbed_official 50:a417edff4437 1324 #define _USART_TIMING_CSSETUP_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */
mbed_official 50:a417edff4437 1325 #define _USART_TIMING_CSSETUP_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */
mbed_official 50:a417edff4437 1326 #define _USART_TIMING_CSSETUP_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */
mbed_official 50:a417edff4437 1327 #define _USART_TIMING_CSSETUP_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */
mbed_official 50:a417edff4437 1328 #define _USART_TIMING_CSSETUP_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */
mbed_official 50:a417edff4437 1329 #define USART_TIMING_CSSETUP_DEFAULT (_USART_TIMING_CSSETUP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMING */
mbed_official 50:a417edff4437 1330 #define USART_TIMING_CSSETUP_ZERO (_USART_TIMING_CSSETUP_ZERO << 20) /**< Shifted mode ZERO for USART_TIMING */
mbed_official 50:a417edff4437 1331 #define USART_TIMING_CSSETUP_ONE (_USART_TIMING_CSSETUP_ONE << 20) /**< Shifted mode ONE for USART_TIMING */
mbed_official 50:a417edff4437 1332 #define USART_TIMING_CSSETUP_TWO (_USART_TIMING_CSSETUP_TWO << 20) /**< Shifted mode TWO for USART_TIMING */
mbed_official 50:a417edff4437 1333 #define USART_TIMING_CSSETUP_THREE (_USART_TIMING_CSSETUP_THREE << 20) /**< Shifted mode THREE for USART_TIMING */
mbed_official 50:a417edff4437 1334 #define USART_TIMING_CSSETUP_SEVEN (_USART_TIMING_CSSETUP_SEVEN << 20) /**< Shifted mode SEVEN for USART_TIMING */
mbed_official 50:a417edff4437 1335 #define USART_TIMING_CSSETUP_TCMP0 (_USART_TIMING_CSSETUP_TCMP0 << 20) /**< Shifted mode TCMP0 for USART_TIMING */
mbed_official 50:a417edff4437 1336 #define USART_TIMING_CSSETUP_TCMP1 (_USART_TIMING_CSSETUP_TCMP1 << 20) /**< Shifted mode TCMP1 for USART_TIMING */
mbed_official 50:a417edff4437 1337 #define USART_TIMING_CSSETUP_TCMP2 (_USART_TIMING_CSSETUP_TCMP2 << 20) /**< Shifted mode TCMP2 for USART_TIMING */
mbed_official 50:a417edff4437 1338 #define _USART_TIMING_ICS_SHIFT 24 /**< Shift value for USART_ICS */
mbed_official 50:a417edff4437 1339 #define _USART_TIMING_ICS_MASK 0x7000000UL /**< Bit mask for USART_ICS */
mbed_official 50:a417edff4437 1340 #define _USART_TIMING_ICS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */
mbed_official 50:a417edff4437 1341 #define _USART_TIMING_ICS_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */
mbed_official 50:a417edff4437 1342 #define _USART_TIMING_ICS_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */
mbed_official 50:a417edff4437 1343 #define _USART_TIMING_ICS_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */
mbed_official 50:a417edff4437 1344 #define _USART_TIMING_ICS_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */
mbed_official 50:a417edff4437 1345 #define _USART_TIMING_ICS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */
mbed_official 50:a417edff4437 1346 #define _USART_TIMING_ICS_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */
mbed_official 50:a417edff4437 1347 #define _USART_TIMING_ICS_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */
mbed_official 50:a417edff4437 1348 #define _USART_TIMING_ICS_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */
mbed_official 50:a417edff4437 1349 #define USART_TIMING_ICS_DEFAULT (_USART_TIMING_ICS_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMING */
mbed_official 50:a417edff4437 1350 #define USART_TIMING_ICS_ZERO (_USART_TIMING_ICS_ZERO << 24) /**< Shifted mode ZERO for USART_TIMING */
mbed_official 50:a417edff4437 1351 #define USART_TIMING_ICS_ONE (_USART_TIMING_ICS_ONE << 24) /**< Shifted mode ONE for USART_TIMING */
mbed_official 50:a417edff4437 1352 #define USART_TIMING_ICS_TWO (_USART_TIMING_ICS_TWO << 24) /**< Shifted mode TWO for USART_TIMING */
mbed_official 50:a417edff4437 1353 #define USART_TIMING_ICS_THREE (_USART_TIMING_ICS_THREE << 24) /**< Shifted mode THREE for USART_TIMING */
mbed_official 50:a417edff4437 1354 #define USART_TIMING_ICS_SEVEN (_USART_TIMING_ICS_SEVEN << 24) /**< Shifted mode SEVEN for USART_TIMING */
mbed_official 50:a417edff4437 1355 #define USART_TIMING_ICS_TCMP0 (_USART_TIMING_ICS_TCMP0 << 24) /**< Shifted mode TCMP0 for USART_TIMING */
mbed_official 50:a417edff4437 1356 #define USART_TIMING_ICS_TCMP1 (_USART_TIMING_ICS_TCMP1 << 24) /**< Shifted mode TCMP1 for USART_TIMING */
mbed_official 50:a417edff4437 1357 #define USART_TIMING_ICS_TCMP2 (_USART_TIMING_ICS_TCMP2 << 24) /**< Shifted mode TCMP2 for USART_TIMING */
mbed_official 50:a417edff4437 1358 #define _USART_TIMING_CSHOLD_SHIFT 28 /**< Shift value for USART_CSHOLD */
mbed_official 50:a417edff4437 1359 #define _USART_TIMING_CSHOLD_MASK 0x70000000UL /**< Bit mask for USART_CSHOLD */
mbed_official 50:a417edff4437 1360 #define _USART_TIMING_CSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */
mbed_official 50:a417edff4437 1361 #define _USART_TIMING_CSHOLD_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */
mbed_official 50:a417edff4437 1362 #define _USART_TIMING_CSHOLD_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */
mbed_official 50:a417edff4437 1363 #define _USART_TIMING_CSHOLD_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */
mbed_official 50:a417edff4437 1364 #define _USART_TIMING_CSHOLD_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */
mbed_official 50:a417edff4437 1365 #define _USART_TIMING_CSHOLD_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */
mbed_official 50:a417edff4437 1366 #define _USART_TIMING_CSHOLD_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */
mbed_official 50:a417edff4437 1367 #define _USART_TIMING_CSHOLD_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */
mbed_official 50:a417edff4437 1368 #define _USART_TIMING_CSHOLD_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */
mbed_official 50:a417edff4437 1369 #define USART_TIMING_CSHOLD_DEFAULT (_USART_TIMING_CSHOLD_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_TIMING */
mbed_official 50:a417edff4437 1370 #define USART_TIMING_CSHOLD_ZERO (_USART_TIMING_CSHOLD_ZERO << 28) /**< Shifted mode ZERO for USART_TIMING */
mbed_official 50:a417edff4437 1371 #define USART_TIMING_CSHOLD_ONE (_USART_TIMING_CSHOLD_ONE << 28) /**< Shifted mode ONE for USART_TIMING */
mbed_official 50:a417edff4437 1372 #define USART_TIMING_CSHOLD_TWO (_USART_TIMING_CSHOLD_TWO << 28) /**< Shifted mode TWO for USART_TIMING */
mbed_official 50:a417edff4437 1373 #define USART_TIMING_CSHOLD_THREE (_USART_TIMING_CSHOLD_THREE << 28) /**< Shifted mode THREE for USART_TIMING */
mbed_official 50:a417edff4437 1374 #define USART_TIMING_CSHOLD_SEVEN (_USART_TIMING_CSHOLD_SEVEN << 28) /**< Shifted mode SEVEN for USART_TIMING */
mbed_official 50:a417edff4437 1375 #define USART_TIMING_CSHOLD_TCMP0 (_USART_TIMING_CSHOLD_TCMP0 << 28) /**< Shifted mode TCMP0 for USART_TIMING */
mbed_official 50:a417edff4437 1376 #define USART_TIMING_CSHOLD_TCMP1 (_USART_TIMING_CSHOLD_TCMP1 << 28) /**< Shifted mode TCMP1 for USART_TIMING */
mbed_official 50:a417edff4437 1377 #define USART_TIMING_CSHOLD_TCMP2 (_USART_TIMING_CSHOLD_TCMP2 << 28) /**< Shifted mode TCMP2 for USART_TIMING */
mbed_official 50:a417edff4437 1378
mbed_official 50:a417edff4437 1379 /* Bit fields for USART CTRLX */
mbed_official 50:a417edff4437 1380 #define _USART_CTRLX_RESETVALUE 0x00000000UL /**< Default value for USART_CTRLX */
mbed_official 50:a417edff4437 1381 #define _USART_CTRLX_MASK 0x0000000FUL /**< Mask for USART_CTRLX */
mbed_official 50:a417edff4437 1382 #define USART_CTRLX_DBGHALT (0x1UL << 0) /**< Debug halt */
mbed_official 50:a417edff4437 1383 #define _USART_CTRLX_DBGHALT_SHIFT 0 /**< Shift value for USART_DBGHALT */
mbed_official 50:a417edff4437 1384 #define _USART_CTRLX_DBGHALT_MASK 0x1UL /**< Bit mask for USART_DBGHALT */
mbed_official 50:a417edff4437 1385 #define _USART_CTRLX_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */
mbed_official 50:a417edff4437 1386 #define USART_CTRLX_DBGHALT_DEFAULT (_USART_CTRLX_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CTRLX */
mbed_official 50:a417edff4437 1387 #define USART_CTRLX_CTSINV (0x1UL << 1) /**< CTS Pin Inversion */
mbed_official 50:a417edff4437 1388 #define _USART_CTRLX_CTSINV_SHIFT 1 /**< Shift value for USART_CTSINV */
mbed_official 50:a417edff4437 1389 #define _USART_CTRLX_CTSINV_MASK 0x2UL /**< Bit mask for USART_CTSINV */
mbed_official 50:a417edff4437 1390 #define _USART_CTRLX_CTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */
mbed_official 50:a417edff4437 1391 #define USART_CTRLX_CTSINV_DEFAULT (_USART_CTRLX_CTSINV_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRLX */
mbed_official 50:a417edff4437 1392 #define USART_CTRLX_CTSEN (0x1UL << 2) /**< CTS Function enabled */
mbed_official 50:a417edff4437 1393 #define _USART_CTRLX_CTSEN_SHIFT 2 /**< Shift value for USART_CTSEN */
mbed_official 50:a417edff4437 1394 #define _USART_CTRLX_CTSEN_MASK 0x4UL /**< Bit mask for USART_CTSEN */
mbed_official 50:a417edff4437 1395 #define _USART_CTRLX_CTSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */
mbed_official 50:a417edff4437 1396 #define USART_CTRLX_CTSEN_DEFAULT (_USART_CTRLX_CTSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CTRLX */
mbed_official 50:a417edff4437 1397 #define USART_CTRLX_RTSINV (0x1UL << 3) /**< RTS Pin Inversion */
mbed_official 50:a417edff4437 1398 #define _USART_CTRLX_RTSINV_SHIFT 3 /**< Shift value for USART_RTSINV */
mbed_official 50:a417edff4437 1399 #define _USART_CTRLX_RTSINV_MASK 0x8UL /**< Bit mask for USART_RTSINV */
mbed_official 50:a417edff4437 1400 #define _USART_CTRLX_RTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */
mbed_official 50:a417edff4437 1401 #define USART_CTRLX_RTSINV_DEFAULT (_USART_CTRLX_RTSINV_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CTRLX */
mbed_official 50:a417edff4437 1402
mbed_official 50:a417edff4437 1403 /* Bit fields for USART TIMECMP0 */
mbed_official 50:a417edff4437 1404 #define _USART_TIMECMP0_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP0 */
mbed_official 50:a417edff4437 1405 #define _USART_TIMECMP0_MASK 0x017700FFUL /**< Mask for USART_TIMECMP0 */
mbed_official 50:a417edff4437 1406 #define _USART_TIMECMP0_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */
mbed_official 50:a417edff4437 1407 #define _USART_TIMECMP0_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */
mbed_official 50:a417edff4437 1408 #define _USART_TIMECMP0_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */
mbed_official 50:a417edff4437 1409 #define USART_TIMECMP0_TCMPVAL_DEFAULT (_USART_TIMECMP0_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP0 */
mbed_official 50:a417edff4437 1410 #define _USART_TIMECMP0_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */
mbed_official 50:a417edff4437 1411 #define _USART_TIMECMP0_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */
mbed_official 50:a417edff4437 1412 #define _USART_TIMECMP0_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */
mbed_official 50:a417edff4437 1413 #define _USART_TIMECMP0_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP0 */
mbed_official 50:a417edff4437 1414 #define _USART_TIMECMP0_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP0 */
mbed_official 50:a417edff4437 1415 #define _USART_TIMECMP0_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP0 */
mbed_official 50:a417edff4437 1416 #define _USART_TIMECMP0_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP0 */
mbed_official 50:a417edff4437 1417 #define _USART_TIMECMP0_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP0 */
mbed_official 50:a417edff4437 1418 #define USART_TIMECMP0_TSTART_DEFAULT (_USART_TIMECMP0_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP0 */
mbed_official 50:a417edff4437 1419 #define USART_TIMECMP0_TSTART_DISABLE (_USART_TIMECMP0_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP0 */
mbed_official 50:a417edff4437 1420 #define USART_TIMECMP0_TSTART_TXEOF (_USART_TIMECMP0_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP0 */
mbed_official 50:a417edff4437 1421 #define USART_TIMECMP0_TSTART_TXC (_USART_TIMECMP0_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP0 */
mbed_official 50:a417edff4437 1422 #define USART_TIMECMP0_TSTART_RXACT (_USART_TIMECMP0_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP0 */
mbed_official 50:a417edff4437 1423 #define USART_TIMECMP0_TSTART_RXEOF (_USART_TIMECMP0_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP0 */
mbed_official 50:a417edff4437 1424 #define _USART_TIMECMP0_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */
mbed_official 50:a417edff4437 1425 #define _USART_TIMECMP0_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */
mbed_official 50:a417edff4437 1426 #define _USART_TIMECMP0_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */
mbed_official 50:a417edff4437 1427 #define _USART_TIMECMP0_TSTOP_TCMP0 0x00000000UL /**< Mode TCMP0 for USART_TIMECMP0 */
mbed_official 50:a417edff4437 1428 #define _USART_TIMECMP0_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP0 */
mbed_official 50:a417edff4437 1429 #define _USART_TIMECMP0_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP0 */
mbed_official 50:a417edff4437 1430 #define _USART_TIMECMP0_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP0 */
mbed_official 50:a417edff4437 1431 #define USART_TIMECMP0_TSTOP_DEFAULT (_USART_TIMECMP0_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP0 */
mbed_official 50:a417edff4437 1432 #define USART_TIMECMP0_TSTOP_TCMP0 (_USART_TIMECMP0_TSTOP_TCMP0 << 20) /**< Shifted mode TCMP0 for USART_TIMECMP0 */
mbed_official 50:a417edff4437 1433 #define USART_TIMECMP0_TSTOP_TXST (_USART_TIMECMP0_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP0 */
mbed_official 50:a417edff4437 1434 #define USART_TIMECMP0_TSTOP_RXACT (_USART_TIMECMP0_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP0 */
mbed_official 50:a417edff4437 1435 #define USART_TIMECMP0_TSTOP_RXACTN (_USART_TIMECMP0_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP0 */
mbed_official 50:a417edff4437 1436 #define USART_TIMECMP0_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP0 */
mbed_official 50:a417edff4437 1437 #define _USART_TIMECMP0_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */
mbed_official 50:a417edff4437 1438 #define _USART_TIMECMP0_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */
mbed_official 50:a417edff4437 1439 #define _USART_TIMECMP0_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */
mbed_official 50:a417edff4437 1440 #define USART_TIMECMP0_RESTARTEN_DEFAULT (_USART_TIMECMP0_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP0 */
mbed_official 50:a417edff4437 1441
mbed_official 50:a417edff4437 1442 /* Bit fields for USART TIMECMP1 */
mbed_official 50:a417edff4437 1443 #define _USART_TIMECMP1_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP1 */
mbed_official 50:a417edff4437 1444 #define _USART_TIMECMP1_MASK 0x017700FFUL /**< Mask for USART_TIMECMP1 */
mbed_official 50:a417edff4437 1445 #define _USART_TIMECMP1_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */
mbed_official 50:a417edff4437 1446 #define _USART_TIMECMP1_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */
mbed_official 50:a417edff4437 1447 #define _USART_TIMECMP1_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */
mbed_official 50:a417edff4437 1448 #define USART_TIMECMP1_TCMPVAL_DEFAULT (_USART_TIMECMP1_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP1 */
mbed_official 50:a417edff4437 1449 #define _USART_TIMECMP1_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */
mbed_official 50:a417edff4437 1450 #define _USART_TIMECMP1_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */
mbed_official 50:a417edff4437 1451 #define _USART_TIMECMP1_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */
mbed_official 50:a417edff4437 1452 #define _USART_TIMECMP1_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP1 */
mbed_official 50:a417edff4437 1453 #define _USART_TIMECMP1_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP1 */
mbed_official 50:a417edff4437 1454 #define _USART_TIMECMP1_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP1 */
mbed_official 50:a417edff4437 1455 #define _USART_TIMECMP1_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP1 */
mbed_official 50:a417edff4437 1456 #define _USART_TIMECMP1_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP1 */
mbed_official 50:a417edff4437 1457 #define USART_TIMECMP1_TSTART_DEFAULT (_USART_TIMECMP1_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP1 */
mbed_official 50:a417edff4437 1458 #define USART_TIMECMP1_TSTART_DISABLE (_USART_TIMECMP1_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP1 */
mbed_official 50:a417edff4437 1459 #define USART_TIMECMP1_TSTART_TXEOF (_USART_TIMECMP1_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP1 */
mbed_official 50:a417edff4437 1460 #define USART_TIMECMP1_TSTART_TXC (_USART_TIMECMP1_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP1 */
mbed_official 50:a417edff4437 1461 #define USART_TIMECMP1_TSTART_RXACT (_USART_TIMECMP1_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP1 */
mbed_official 50:a417edff4437 1462 #define USART_TIMECMP1_TSTART_RXEOF (_USART_TIMECMP1_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP1 */
mbed_official 50:a417edff4437 1463 #define _USART_TIMECMP1_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */
mbed_official 50:a417edff4437 1464 #define _USART_TIMECMP1_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */
mbed_official 50:a417edff4437 1465 #define _USART_TIMECMP1_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */
mbed_official 50:a417edff4437 1466 #define _USART_TIMECMP1_TSTOP_TCMP1 0x00000000UL /**< Mode TCMP1 for USART_TIMECMP1 */
mbed_official 50:a417edff4437 1467 #define _USART_TIMECMP1_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP1 */
mbed_official 50:a417edff4437 1468 #define _USART_TIMECMP1_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP1 */
mbed_official 50:a417edff4437 1469 #define _USART_TIMECMP1_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP1 */
mbed_official 50:a417edff4437 1470 #define USART_TIMECMP1_TSTOP_DEFAULT (_USART_TIMECMP1_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP1 */
mbed_official 50:a417edff4437 1471 #define USART_TIMECMP1_TSTOP_TCMP1 (_USART_TIMECMP1_TSTOP_TCMP1 << 20) /**< Shifted mode TCMP1 for USART_TIMECMP1 */
mbed_official 50:a417edff4437 1472 #define USART_TIMECMP1_TSTOP_TXST (_USART_TIMECMP1_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP1 */
mbed_official 50:a417edff4437 1473 #define USART_TIMECMP1_TSTOP_RXACT (_USART_TIMECMP1_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP1 */
mbed_official 50:a417edff4437 1474 #define USART_TIMECMP1_TSTOP_RXACTN (_USART_TIMECMP1_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP1 */
mbed_official 50:a417edff4437 1475 #define USART_TIMECMP1_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP1 */
mbed_official 50:a417edff4437 1476 #define _USART_TIMECMP1_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */
mbed_official 50:a417edff4437 1477 #define _USART_TIMECMP1_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */
mbed_official 50:a417edff4437 1478 #define _USART_TIMECMP1_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */
mbed_official 50:a417edff4437 1479 #define USART_TIMECMP1_RESTARTEN_DEFAULT (_USART_TIMECMP1_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP1 */
mbed_official 50:a417edff4437 1480
mbed_official 50:a417edff4437 1481 /* Bit fields for USART TIMECMP2 */
mbed_official 50:a417edff4437 1482 #define _USART_TIMECMP2_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP2 */
mbed_official 50:a417edff4437 1483 #define _USART_TIMECMP2_MASK 0x017700FFUL /**< Mask for USART_TIMECMP2 */
mbed_official 50:a417edff4437 1484 #define _USART_TIMECMP2_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */
mbed_official 50:a417edff4437 1485 #define _USART_TIMECMP2_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */
mbed_official 50:a417edff4437 1486 #define _USART_TIMECMP2_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */
mbed_official 50:a417edff4437 1487 #define USART_TIMECMP2_TCMPVAL_DEFAULT (_USART_TIMECMP2_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP2 */
mbed_official 50:a417edff4437 1488 #define _USART_TIMECMP2_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */
mbed_official 50:a417edff4437 1489 #define _USART_TIMECMP2_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */
mbed_official 50:a417edff4437 1490 #define _USART_TIMECMP2_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */
mbed_official 50:a417edff4437 1491 #define _USART_TIMECMP2_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP2 */
mbed_official 50:a417edff4437 1492 #define _USART_TIMECMP2_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP2 */
mbed_official 50:a417edff4437 1493 #define _USART_TIMECMP2_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP2 */
mbed_official 50:a417edff4437 1494 #define _USART_TIMECMP2_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP2 */
mbed_official 50:a417edff4437 1495 #define _USART_TIMECMP2_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP2 */
mbed_official 50:a417edff4437 1496 #define USART_TIMECMP2_TSTART_DEFAULT (_USART_TIMECMP2_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP2 */
mbed_official 50:a417edff4437 1497 #define USART_TIMECMP2_TSTART_DISABLE (_USART_TIMECMP2_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP2 */
mbed_official 50:a417edff4437 1498 #define USART_TIMECMP2_TSTART_TXEOF (_USART_TIMECMP2_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP2 */
mbed_official 50:a417edff4437 1499 #define USART_TIMECMP2_TSTART_TXC (_USART_TIMECMP2_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP2 */
mbed_official 50:a417edff4437 1500 #define USART_TIMECMP2_TSTART_RXACT (_USART_TIMECMP2_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP2 */
mbed_official 50:a417edff4437 1501 #define USART_TIMECMP2_TSTART_RXEOF (_USART_TIMECMP2_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP2 */
mbed_official 50:a417edff4437 1502 #define _USART_TIMECMP2_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */
mbed_official 50:a417edff4437 1503 #define _USART_TIMECMP2_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */
mbed_official 50:a417edff4437 1504 #define _USART_TIMECMP2_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */
mbed_official 50:a417edff4437 1505 #define _USART_TIMECMP2_TSTOP_TCMP2 0x00000000UL /**< Mode TCMP2 for USART_TIMECMP2 */
mbed_official 50:a417edff4437 1506 #define _USART_TIMECMP2_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP2 */
mbed_official 50:a417edff4437 1507 #define _USART_TIMECMP2_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP2 */
mbed_official 50:a417edff4437 1508 #define _USART_TIMECMP2_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP2 */
mbed_official 50:a417edff4437 1509 #define USART_TIMECMP2_TSTOP_DEFAULT (_USART_TIMECMP2_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP2 */
mbed_official 50:a417edff4437 1510 #define USART_TIMECMP2_TSTOP_TCMP2 (_USART_TIMECMP2_TSTOP_TCMP2 << 20) /**< Shifted mode TCMP2 for USART_TIMECMP2 */
mbed_official 50:a417edff4437 1511 #define USART_TIMECMP2_TSTOP_TXST (_USART_TIMECMP2_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP2 */
mbed_official 50:a417edff4437 1512 #define USART_TIMECMP2_TSTOP_RXACT (_USART_TIMECMP2_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP2 */
mbed_official 50:a417edff4437 1513 #define USART_TIMECMP2_TSTOP_RXACTN (_USART_TIMECMP2_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP2 */
mbed_official 50:a417edff4437 1514 #define USART_TIMECMP2_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP2 */
mbed_official 50:a417edff4437 1515 #define _USART_TIMECMP2_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */
mbed_official 50:a417edff4437 1516 #define _USART_TIMECMP2_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */
mbed_official 50:a417edff4437 1517 #define _USART_TIMECMP2_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */
mbed_official 50:a417edff4437 1518 #define USART_TIMECMP2_RESTARTEN_DEFAULT (_USART_TIMECMP2_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP2 */
mbed_official 50:a417edff4437 1519
mbed_official 50:a417edff4437 1520 /* Bit fields for USART ROUTEPEN */
mbed_official 50:a417edff4437 1521 #define _USART_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for USART_ROUTEPEN */
mbed_official 50:a417edff4437 1522 #define _USART_ROUTEPEN_MASK 0x0000003FUL /**< Mask for USART_ROUTEPEN */
mbed_official 50:a417edff4437 1523 #define USART_ROUTEPEN_RXPEN (0x1UL << 0) /**< RX Pin Enable */
mbed_official 50:a417edff4437 1524 #define _USART_ROUTEPEN_RXPEN_SHIFT 0 /**< Shift value for USART_RXPEN */
mbed_official 50:a417edff4437 1525 #define _USART_ROUTEPEN_RXPEN_MASK 0x1UL /**< Bit mask for USART_RXPEN */
mbed_official 50:a417edff4437 1526 #define _USART_ROUTEPEN_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */
mbed_official 50:a417edff4437 1527 #define USART_ROUTEPEN_RXPEN_DEFAULT (_USART_ROUTEPEN_RXPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_ROUTEPEN */
mbed_official 50:a417edff4437 1528 #define USART_ROUTEPEN_TXPEN (0x1UL << 1) /**< TX Pin Enable */
mbed_official 50:a417edff4437 1529 #define _USART_ROUTEPEN_TXPEN_SHIFT 1 /**< Shift value for USART_TXPEN */
mbed_official 50:a417edff4437 1530 #define _USART_ROUTEPEN_TXPEN_MASK 0x2UL /**< Bit mask for USART_TXPEN */
mbed_official 50:a417edff4437 1531 #define _USART_ROUTEPEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */
mbed_official 50:a417edff4437 1532 #define USART_ROUTEPEN_TXPEN_DEFAULT (_USART_ROUTEPEN_TXPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_ROUTEPEN */
mbed_official 50:a417edff4437 1533 #define USART_ROUTEPEN_CSPEN (0x1UL << 2) /**< CS Pin Enable */
mbed_official 50:a417edff4437 1534 #define _USART_ROUTEPEN_CSPEN_SHIFT 2 /**< Shift value for USART_CSPEN */
mbed_official 50:a417edff4437 1535 #define _USART_ROUTEPEN_CSPEN_MASK 0x4UL /**< Bit mask for USART_CSPEN */
mbed_official 50:a417edff4437 1536 #define _USART_ROUTEPEN_CSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */
mbed_official 50:a417edff4437 1537 #define USART_ROUTEPEN_CSPEN_DEFAULT (_USART_ROUTEPEN_CSPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_ROUTEPEN */
mbed_official 50:a417edff4437 1538 #define USART_ROUTEPEN_CLKPEN (0x1UL << 3) /**< CLK Pin Enable */
mbed_official 50:a417edff4437 1539 #define _USART_ROUTEPEN_CLKPEN_SHIFT 3 /**< Shift value for USART_CLKPEN */
mbed_official 50:a417edff4437 1540 #define _USART_ROUTEPEN_CLKPEN_MASK 0x8UL /**< Bit mask for USART_CLKPEN */
mbed_official 50:a417edff4437 1541 #define _USART_ROUTEPEN_CLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */
mbed_official 50:a417edff4437 1542 #define USART_ROUTEPEN_CLKPEN_DEFAULT (_USART_ROUTEPEN_CLKPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_ROUTEPEN */
mbed_official 50:a417edff4437 1543 #define USART_ROUTEPEN_CTSPEN (0x1UL << 4) /**< CTS Pin Enable */
mbed_official 50:a417edff4437 1544 #define _USART_ROUTEPEN_CTSPEN_SHIFT 4 /**< Shift value for USART_CTSPEN */
mbed_official 50:a417edff4437 1545 #define _USART_ROUTEPEN_CTSPEN_MASK 0x10UL /**< Bit mask for USART_CTSPEN */
mbed_official 50:a417edff4437 1546 #define _USART_ROUTEPEN_CTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */
mbed_official 50:a417edff4437 1547 #define USART_ROUTEPEN_CTSPEN_DEFAULT (_USART_ROUTEPEN_CTSPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_ROUTEPEN */
mbed_official 50:a417edff4437 1548 #define USART_ROUTEPEN_RTSPEN (0x1UL << 5) /**< RTS Pin Enable */
mbed_official 50:a417edff4437 1549 #define _USART_ROUTEPEN_RTSPEN_SHIFT 5 /**< Shift value for USART_RTSPEN */
mbed_official 50:a417edff4437 1550 #define _USART_ROUTEPEN_RTSPEN_MASK 0x20UL /**< Bit mask for USART_RTSPEN */
mbed_official 50:a417edff4437 1551 #define _USART_ROUTEPEN_RTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */
mbed_official 50:a417edff4437 1552 #define USART_ROUTEPEN_RTSPEN_DEFAULT (_USART_ROUTEPEN_RTSPEN_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_ROUTEPEN */
mbed_official 50:a417edff4437 1553
mbed_official 50:a417edff4437 1554 /* Bit fields for USART ROUTELOC0 */
mbed_official 50:a417edff4437 1555 #define _USART_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1556 #define _USART_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1557 #define _USART_ROUTELOC0_RXLOC_SHIFT 0 /**< Shift value for USART_RXLOC */
mbed_official 50:a417edff4437 1558 #define _USART_ROUTELOC0_RXLOC_MASK 0x1FUL /**< Bit mask for USART_RXLOC */
mbed_official 50:a417edff4437 1559 #define _USART_ROUTELOC0_RXLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1560 #define _USART_ROUTELOC0_RXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1561 #define _USART_ROUTELOC0_RXLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1562 #define _USART_ROUTELOC0_RXLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1563 #define _USART_ROUTELOC0_RXLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1564 #define _USART_ROUTELOC0_RXLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1565 #define _USART_ROUTELOC0_RXLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1566 #define _USART_ROUTELOC0_RXLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1567 #define _USART_ROUTELOC0_RXLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1568 #define _USART_ROUTELOC0_RXLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1569 #define _USART_ROUTELOC0_RXLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1570 #define _USART_ROUTELOC0_RXLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1571 #define _USART_ROUTELOC0_RXLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1572 #define _USART_ROUTELOC0_RXLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1573 #define _USART_ROUTELOC0_RXLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1574 #define _USART_ROUTELOC0_RXLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1575 #define _USART_ROUTELOC0_RXLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1576 #define _USART_ROUTELOC0_RXLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1577 #define _USART_ROUTELOC0_RXLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1578 #define _USART_ROUTELOC0_RXLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1579 #define _USART_ROUTELOC0_RXLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1580 #define _USART_ROUTELOC0_RXLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1581 #define _USART_ROUTELOC0_RXLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1582 #define _USART_ROUTELOC0_RXLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1583 #define _USART_ROUTELOC0_RXLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1584 #define _USART_ROUTELOC0_RXLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1585 #define _USART_ROUTELOC0_RXLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1586 #define _USART_ROUTELOC0_RXLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1587 #define _USART_ROUTELOC0_RXLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1588 #define _USART_ROUTELOC0_RXLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1589 #define _USART_ROUTELOC0_RXLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1590 #define _USART_ROUTELOC0_RXLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1591 #define _USART_ROUTELOC0_RXLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1592 #define USART_ROUTELOC0_RXLOC_LOC0 (_USART_ROUTELOC0_RXLOC_LOC0 << 0) /**< Shifted mode LOC0 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1593 #define USART_ROUTELOC0_RXLOC_DEFAULT (_USART_ROUTELOC0_RXLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1594 #define USART_ROUTELOC0_RXLOC_LOC1 (_USART_ROUTELOC0_RXLOC_LOC1 << 0) /**< Shifted mode LOC1 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1595 #define USART_ROUTELOC0_RXLOC_LOC2 (_USART_ROUTELOC0_RXLOC_LOC2 << 0) /**< Shifted mode LOC2 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1596 #define USART_ROUTELOC0_RXLOC_LOC3 (_USART_ROUTELOC0_RXLOC_LOC3 << 0) /**< Shifted mode LOC3 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1597 #define USART_ROUTELOC0_RXLOC_LOC4 (_USART_ROUTELOC0_RXLOC_LOC4 << 0) /**< Shifted mode LOC4 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1598 #define USART_ROUTELOC0_RXLOC_LOC5 (_USART_ROUTELOC0_RXLOC_LOC5 << 0) /**< Shifted mode LOC5 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1599 #define USART_ROUTELOC0_RXLOC_LOC6 (_USART_ROUTELOC0_RXLOC_LOC6 << 0) /**< Shifted mode LOC6 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1600 #define USART_ROUTELOC0_RXLOC_LOC7 (_USART_ROUTELOC0_RXLOC_LOC7 << 0) /**< Shifted mode LOC7 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1601 #define USART_ROUTELOC0_RXLOC_LOC8 (_USART_ROUTELOC0_RXLOC_LOC8 << 0) /**< Shifted mode LOC8 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1602 #define USART_ROUTELOC0_RXLOC_LOC9 (_USART_ROUTELOC0_RXLOC_LOC9 << 0) /**< Shifted mode LOC9 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1603 #define USART_ROUTELOC0_RXLOC_LOC10 (_USART_ROUTELOC0_RXLOC_LOC10 << 0) /**< Shifted mode LOC10 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1604 #define USART_ROUTELOC0_RXLOC_LOC11 (_USART_ROUTELOC0_RXLOC_LOC11 << 0) /**< Shifted mode LOC11 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1605 #define USART_ROUTELOC0_RXLOC_LOC12 (_USART_ROUTELOC0_RXLOC_LOC12 << 0) /**< Shifted mode LOC12 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1606 #define USART_ROUTELOC0_RXLOC_LOC13 (_USART_ROUTELOC0_RXLOC_LOC13 << 0) /**< Shifted mode LOC13 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1607 #define USART_ROUTELOC0_RXLOC_LOC14 (_USART_ROUTELOC0_RXLOC_LOC14 << 0) /**< Shifted mode LOC14 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1608 #define USART_ROUTELOC0_RXLOC_LOC15 (_USART_ROUTELOC0_RXLOC_LOC15 << 0) /**< Shifted mode LOC15 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1609 #define USART_ROUTELOC0_RXLOC_LOC16 (_USART_ROUTELOC0_RXLOC_LOC16 << 0) /**< Shifted mode LOC16 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1610 #define USART_ROUTELOC0_RXLOC_LOC17 (_USART_ROUTELOC0_RXLOC_LOC17 << 0) /**< Shifted mode LOC17 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1611 #define USART_ROUTELOC0_RXLOC_LOC18 (_USART_ROUTELOC0_RXLOC_LOC18 << 0) /**< Shifted mode LOC18 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1612 #define USART_ROUTELOC0_RXLOC_LOC19 (_USART_ROUTELOC0_RXLOC_LOC19 << 0) /**< Shifted mode LOC19 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1613 #define USART_ROUTELOC0_RXLOC_LOC20 (_USART_ROUTELOC0_RXLOC_LOC20 << 0) /**< Shifted mode LOC20 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1614 #define USART_ROUTELOC0_RXLOC_LOC21 (_USART_ROUTELOC0_RXLOC_LOC21 << 0) /**< Shifted mode LOC21 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1615 #define USART_ROUTELOC0_RXLOC_LOC22 (_USART_ROUTELOC0_RXLOC_LOC22 << 0) /**< Shifted mode LOC22 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1616 #define USART_ROUTELOC0_RXLOC_LOC23 (_USART_ROUTELOC0_RXLOC_LOC23 << 0) /**< Shifted mode LOC23 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1617 #define USART_ROUTELOC0_RXLOC_LOC24 (_USART_ROUTELOC0_RXLOC_LOC24 << 0) /**< Shifted mode LOC24 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1618 #define USART_ROUTELOC0_RXLOC_LOC25 (_USART_ROUTELOC0_RXLOC_LOC25 << 0) /**< Shifted mode LOC25 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1619 #define USART_ROUTELOC0_RXLOC_LOC26 (_USART_ROUTELOC0_RXLOC_LOC26 << 0) /**< Shifted mode LOC26 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1620 #define USART_ROUTELOC0_RXLOC_LOC27 (_USART_ROUTELOC0_RXLOC_LOC27 << 0) /**< Shifted mode LOC27 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1621 #define USART_ROUTELOC0_RXLOC_LOC28 (_USART_ROUTELOC0_RXLOC_LOC28 << 0) /**< Shifted mode LOC28 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1622 #define USART_ROUTELOC0_RXLOC_LOC29 (_USART_ROUTELOC0_RXLOC_LOC29 << 0) /**< Shifted mode LOC29 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1623 #define USART_ROUTELOC0_RXLOC_LOC30 (_USART_ROUTELOC0_RXLOC_LOC30 << 0) /**< Shifted mode LOC30 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1624 #define USART_ROUTELOC0_RXLOC_LOC31 (_USART_ROUTELOC0_RXLOC_LOC31 << 0) /**< Shifted mode LOC31 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1625 #define _USART_ROUTELOC0_TXLOC_SHIFT 8 /**< Shift value for USART_TXLOC */
mbed_official 50:a417edff4437 1626 #define _USART_ROUTELOC0_TXLOC_MASK 0x1F00UL /**< Bit mask for USART_TXLOC */
mbed_official 50:a417edff4437 1627 #define _USART_ROUTELOC0_TXLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1628 #define _USART_ROUTELOC0_TXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1629 #define _USART_ROUTELOC0_TXLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1630 #define _USART_ROUTELOC0_TXLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1631 #define _USART_ROUTELOC0_TXLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1632 #define _USART_ROUTELOC0_TXLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1633 #define _USART_ROUTELOC0_TXLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1634 #define _USART_ROUTELOC0_TXLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1635 #define _USART_ROUTELOC0_TXLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1636 #define _USART_ROUTELOC0_TXLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1637 #define _USART_ROUTELOC0_TXLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1638 #define _USART_ROUTELOC0_TXLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1639 #define _USART_ROUTELOC0_TXLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1640 #define _USART_ROUTELOC0_TXLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1641 #define _USART_ROUTELOC0_TXLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1642 #define _USART_ROUTELOC0_TXLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1643 #define _USART_ROUTELOC0_TXLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1644 #define _USART_ROUTELOC0_TXLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1645 #define _USART_ROUTELOC0_TXLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1646 #define _USART_ROUTELOC0_TXLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1647 #define _USART_ROUTELOC0_TXLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1648 #define _USART_ROUTELOC0_TXLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1649 #define _USART_ROUTELOC0_TXLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1650 #define _USART_ROUTELOC0_TXLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1651 #define _USART_ROUTELOC0_TXLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1652 #define _USART_ROUTELOC0_TXLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1653 #define _USART_ROUTELOC0_TXLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1654 #define _USART_ROUTELOC0_TXLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1655 #define _USART_ROUTELOC0_TXLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1656 #define _USART_ROUTELOC0_TXLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1657 #define _USART_ROUTELOC0_TXLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1658 #define _USART_ROUTELOC0_TXLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1659 #define _USART_ROUTELOC0_TXLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1660 #define USART_ROUTELOC0_TXLOC_LOC0 (_USART_ROUTELOC0_TXLOC_LOC0 << 8) /**< Shifted mode LOC0 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1661 #define USART_ROUTELOC0_TXLOC_DEFAULT (_USART_ROUTELOC0_TXLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1662 #define USART_ROUTELOC0_TXLOC_LOC1 (_USART_ROUTELOC0_TXLOC_LOC1 << 8) /**< Shifted mode LOC1 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1663 #define USART_ROUTELOC0_TXLOC_LOC2 (_USART_ROUTELOC0_TXLOC_LOC2 << 8) /**< Shifted mode LOC2 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1664 #define USART_ROUTELOC0_TXLOC_LOC3 (_USART_ROUTELOC0_TXLOC_LOC3 << 8) /**< Shifted mode LOC3 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1665 #define USART_ROUTELOC0_TXLOC_LOC4 (_USART_ROUTELOC0_TXLOC_LOC4 << 8) /**< Shifted mode LOC4 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1666 #define USART_ROUTELOC0_TXLOC_LOC5 (_USART_ROUTELOC0_TXLOC_LOC5 << 8) /**< Shifted mode LOC5 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1667 #define USART_ROUTELOC0_TXLOC_LOC6 (_USART_ROUTELOC0_TXLOC_LOC6 << 8) /**< Shifted mode LOC6 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1668 #define USART_ROUTELOC0_TXLOC_LOC7 (_USART_ROUTELOC0_TXLOC_LOC7 << 8) /**< Shifted mode LOC7 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1669 #define USART_ROUTELOC0_TXLOC_LOC8 (_USART_ROUTELOC0_TXLOC_LOC8 << 8) /**< Shifted mode LOC8 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1670 #define USART_ROUTELOC0_TXLOC_LOC9 (_USART_ROUTELOC0_TXLOC_LOC9 << 8) /**< Shifted mode LOC9 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1671 #define USART_ROUTELOC0_TXLOC_LOC10 (_USART_ROUTELOC0_TXLOC_LOC10 << 8) /**< Shifted mode LOC10 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1672 #define USART_ROUTELOC0_TXLOC_LOC11 (_USART_ROUTELOC0_TXLOC_LOC11 << 8) /**< Shifted mode LOC11 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1673 #define USART_ROUTELOC0_TXLOC_LOC12 (_USART_ROUTELOC0_TXLOC_LOC12 << 8) /**< Shifted mode LOC12 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1674 #define USART_ROUTELOC0_TXLOC_LOC13 (_USART_ROUTELOC0_TXLOC_LOC13 << 8) /**< Shifted mode LOC13 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1675 #define USART_ROUTELOC0_TXLOC_LOC14 (_USART_ROUTELOC0_TXLOC_LOC14 << 8) /**< Shifted mode LOC14 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1676 #define USART_ROUTELOC0_TXLOC_LOC15 (_USART_ROUTELOC0_TXLOC_LOC15 << 8) /**< Shifted mode LOC15 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1677 #define USART_ROUTELOC0_TXLOC_LOC16 (_USART_ROUTELOC0_TXLOC_LOC16 << 8) /**< Shifted mode LOC16 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1678 #define USART_ROUTELOC0_TXLOC_LOC17 (_USART_ROUTELOC0_TXLOC_LOC17 << 8) /**< Shifted mode LOC17 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1679 #define USART_ROUTELOC0_TXLOC_LOC18 (_USART_ROUTELOC0_TXLOC_LOC18 << 8) /**< Shifted mode LOC18 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1680 #define USART_ROUTELOC0_TXLOC_LOC19 (_USART_ROUTELOC0_TXLOC_LOC19 << 8) /**< Shifted mode LOC19 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1681 #define USART_ROUTELOC0_TXLOC_LOC20 (_USART_ROUTELOC0_TXLOC_LOC20 << 8) /**< Shifted mode LOC20 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1682 #define USART_ROUTELOC0_TXLOC_LOC21 (_USART_ROUTELOC0_TXLOC_LOC21 << 8) /**< Shifted mode LOC21 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1683 #define USART_ROUTELOC0_TXLOC_LOC22 (_USART_ROUTELOC0_TXLOC_LOC22 << 8) /**< Shifted mode LOC22 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1684 #define USART_ROUTELOC0_TXLOC_LOC23 (_USART_ROUTELOC0_TXLOC_LOC23 << 8) /**< Shifted mode LOC23 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1685 #define USART_ROUTELOC0_TXLOC_LOC24 (_USART_ROUTELOC0_TXLOC_LOC24 << 8) /**< Shifted mode LOC24 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1686 #define USART_ROUTELOC0_TXLOC_LOC25 (_USART_ROUTELOC0_TXLOC_LOC25 << 8) /**< Shifted mode LOC25 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1687 #define USART_ROUTELOC0_TXLOC_LOC26 (_USART_ROUTELOC0_TXLOC_LOC26 << 8) /**< Shifted mode LOC26 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1688 #define USART_ROUTELOC0_TXLOC_LOC27 (_USART_ROUTELOC0_TXLOC_LOC27 << 8) /**< Shifted mode LOC27 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1689 #define USART_ROUTELOC0_TXLOC_LOC28 (_USART_ROUTELOC0_TXLOC_LOC28 << 8) /**< Shifted mode LOC28 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1690 #define USART_ROUTELOC0_TXLOC_LOC29 (_USART_ROUTELOC0_TXLOC_LOC29 << 8) /**< Shifted mode LOC29 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1691 #define USART_ROUTELOC0_TXLOC_LOC30 (_USART_ROUTELOC0_TXLOC_LOC30 << 8) /**< Shifted mode LOC30 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1692 #define USART_ROUTELOC0_TXLOC_LOC31 (_USART_ROUTELOC0_TXLOC_LOC31 << 8) /**< Shifted mode LOC31 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1693 #define _USART_ROUTELOC0_CSLOC_SHIFT 16 /**< Shift value for USART_CSLOC */
mbed_official 50:a417edff4437 1694 #define _USART_ROUTELOC0_CSLOC_MASK 0x1F0000UL /**< Bit mask for USART_CSLOC */
mbed_official 50:a417edff4437 1695 #define _USART_ROUTELOC0_CSLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1696 #define _USART_ROUTELOC0_CSLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1697 #define _USART_ROUTELOC0_CSLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1698 #define _USART_ROUTELOC0_CSLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1699 #define _USART_ROUTELOC0_CSLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1700 #define _USART_ROUTELOC0_CSLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1701 #define _USART_ROUTELOC0_CSLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1702 #define _USART_ROUTELOC0_CSLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1703 #define _USART_ROUTELOC0_CSLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1704 #define _USART_ROUTELOC0_CSLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1705 #define _USART_ROUTELOC0_CSLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1706 #define _USART_ROUTELOC0_CSLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1707 #define _USART_ROUTELOC0_CSLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1708 #define _USART_ROUTELOC0_CSLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1709 #define _USART_ROUTELOC0_CSLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1710 #define _USART_ROUTELOC0_CSLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1711 #define _USART_ROUTELOC0_CSLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1712 #define _USART_ROUTELOC0_CSLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1713 #define _USART_ROUTELOC0_CSLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1714 #define _USART_ROUTELOC0_CSLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1715 #define _USART_ROUTELOC0_CSLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1716 #define _USART_ROUTELOC0_CSLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1717 #define _USART_ROUTELOC0_CSLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1718 #define _USART_ROUTELOC0_CSLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1719 #define _USART_ROUTELOC0_CSLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1720 #define _USART_ROUTELOC0_CSLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1721 #define _USART_ROUTELOC0_CSLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1722 #define _USART_ROUTELOC0_CSLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1723 #define _USART_ROUTELOC0_CSLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1724 #define _USART_ROUTELOC0_CSLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1725 #define _USART_ROUTELOC0_CSLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1726 #define _USART_ROUTELOC0_CSLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1727 #define _USART_ROUTELOC0_CSLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1728 #define USART_ROUTELOC0_CSLOC_LOC0 (_USART_ROUTELOC0_CSLOC_LOC0 << 16) /**< Shifted mode LOC0 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1729 #define USART_ROUTELOC0_CSLOC_DEFAULT (_USART_ROUTELOC0_CSLOC_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1730 #define USART_ROUTELOC0_CSLOC_LOC1 (_USART_ROUTELOC0_CSLOC_LOC1 << 16) /**< Shifted mode LOC1 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1731 #define USART_ROUTELOC0_CSLOC_LOC2 (_USART_ROUTELOC0_CSLOC_LOC2 << 16) /**< Shifted mode LOC2 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1732 #define USART_ROUTELOC0_CSLOC_LOC3 (_USART_ROUTELOC0_CSLOC_LOC3 << 16) /**< Shifted mode LOC3 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1733 #define USART_ROUTELOC0_CSLOC_LOC4 (_USART_ROUTELOC0_CSLOC_LOC4 << 16) /**< Shifted mode LOC4 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1734 #define USART_ROUTELOC0_CSLOC_LOC5 (_USART_ROUTELOC0_CSLOC_LOC5 << 16) /**< Shifted mode LOC5 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1735 #define USART_ROUTELOC0_CSLOC_LOC6 (_USART_ROUTELOC0_CSLOC_LOC6 << 16) /**< Shifted mode LOC6 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1736 #define USART_ROUTELOC0_CSLOC_LOC7 (_USART_ROUTELOC0_CSLOC_LOC7 << 16) /**< Shifted mode LOC7 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1737 #define USART_ROUTELOC0_CSLOC_LOC8 (_USART_ROUTELOC0_CSLOC_LOC8 << 16) /**< Shifted mode LOC8 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1738 #define USART_ROUTELOC0_CSLOC_LOC9 (_USART_ROUTELOC0_CSLOC_LOC9 << 16) /**< Shifted mode LOC9 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1739 #define USART_ROUTELOC0_CSLOC_LOC10 (_USART_ROUTELOC0_CSLOC_LOC10 << 16) /**< Shifted mode LOC10 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1740 #define USART_ROUTELOC0_CSLOC_LOC11 (_USART_ROUTELOC0_CSLOC_LOC11 << 16) /**< Shifted mode LOC11 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1741 #define USART_ROUTELOC0_CSLOC_LOC12 (_USART_ROUTELOC0_CSLOC_LOC12 << 16) /**< Shifted mode LOC12 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1742 #define USART_ROUTELOC0_CSLOC_LOC13 (_USART_ROUTELOC0_CSLOC_LOC13 << 16) /**< Shifted mode LOC13 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1743 #define USART_ROUTELOC0_CSLOC_LOC14 (_USART_ROUTELOC0_CSLOC_LOC14 << 16) /**< Shifted mode LOC14 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1744 #define USART_ROUTELOC0_CSLOC_LOC15 (_USART_ROUTELOC0_CSLOC_LOC15 << 16) /**< Shifted mode LOC15 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1745 #define USART_ROUTELOC0_CSLOC_LOC16 (_USART_ROUTELOC0_CSLOC_LOC16 << 16) /**< Shifted mode LOC16 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1746 #define USART_ROUTELOC0_CSLOC_LOC17 (_USART_ROUTELOC0_CSLOC_LOC17 << 16) /**< Shifted mode LOC17 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1747 #define USART_ROUTELOC0_CSLOC_LOC18 (_USART_ROUTELOC0_CSLOC_LOC18 << 16) /**< Shifted mode LOC18 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1748 #define USART_ROUTELOC0_CSLOC_LOC19 (_USART_ROUTELOC0_CSLOC_LOC19 << 16) /**< Shifted mode LOC19 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1749 #define USART_ROUTELOC0_CSLOC_LOC20 (_USART_ROUTELOC0_CSLOC_LOC20 << 16) /**< Shifted mode LOC20 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1750 #define USART_ROUTELOC0_CSLOC_LOC21 (_USART_ROUTELOC0_CSLOC_LOC21 << 16) /**< Shifted mode LOC21 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1751 #define USART_ROUTELOC0_CSLOC_LOC22 (_USART_ROUTELOC0_CSLOC_LOC22 << 16) /**< Shifted mode LOC22 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1752 #define USART_ROUTELOC0_CSLOC_LOC23 (_USART_ROUTELOC0_CSLOC_LOC23 << 16) /**< Shifted mode LOC23 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1753 #define USART_ROUTELOC0_CSLOC_LOC24 (_USART_ROUTELOC0_CSLOC_LOC24 << 16) /**< Shifted mode LOC24 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1754 #define USART_ROUTELOC0_CSLOC_LOC25 (_USART_ROUTELOC0_CSLOC_LOC25 << 16) /**< Shifted mode LOC25 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1755 #define USART_ROUTELOC0_CSLOC_LOC26 (_USART_ROUTELOC0_CSLOC_LOC26 << 16) /**< Shifted mode LOC26 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1756 #define USART_ROUTELOC0_CSLOC_LOC27 (_USART_ROUTELOC0_CSLOC_LOC27 << 16) /**< Shifted mode LOC27 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1757 #define USART_ROUTELOC0_CSLOC_LOC28 (_USART_ROUTELOC0_CSLOC_LOC28 << 16) /**< Shifted mode LOC28 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1758 #define USART_ROUTELOC0_CSLOC_LOC29 (_USART_ROUTELOC0_CSLOC_LOC29 << 16) /**< Shifted mode LOC29 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1759 #define USART_ROUTELOC0_CSLOC_LOC30 (_USART_ROUTELOC0_CSLOC_LOC30 << 16) /**< Shifted mode LOC30 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1760 #define USART_ROUTELOC0_CSLOC_LOC31 (_USART_ROUTELOC0_CSLOC_LOC31 << 16) /**< Shifted mode LOC31 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1761 #define _USART_ROUTELOC0_CLKLOC_SHIFT 24 /**< Shift value for USART_CLKLOC */
mbed_official 50:a417edff4437 1762 #define _USART_ROUTELOC0_CLKLOC_MASK 0x1F000000UL /**< Bit mask for USART_CLKLOC */
mbed_official 50:a417edff4437 1763 #define _USART_ROUTELOC0_CLKLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1764 #define _USART_ROUTELOC0_CLKLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1765 #define _USART_ROUTELOC0_CLKLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1766 #define _USART_ROUTELOC0_CLKLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1767 #define _USART_ROUTELOC0_CLKLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1768 #define _USART_ROUTELOC0_CLKLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1769 #define _USART_ROUTELOC0_CLKLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1770 #define _USART_ROUTELOC0_CLKLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1771 #define _USART_ROUTELOC0_CLKLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1772 #define _USART_ROUTELOC0_CLKLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1773 #define _USART_ROUTELOC0_CLKLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1774 #define _USART_ROUTELOC0_CLKLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1775 #define _USART_ROUTELOC0_CLKLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1776 #define _USART_ROUTELOC0_CLKLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1777 #define _USART_ROUTELOC0_CLKLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1778 #define _USART_ROUTELOC0_CLKLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1779 #define _USART_ROUTELOC0_CLKLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1780 #define _USART_ROUTELOC0_CLKLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1781 #define _USART_ROUTELOC0_CLKLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1782 #define _USART_ROUTELOC0_CLKLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1783 #define _USART_ROUTELOC0_CLKLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1784 #define _USART_ROUTELOC0_CLKLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1785 #define _USART_ROUTELOC0_CLKLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1786 #define _USART_ROUTELOC0_CLKLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1787 #define _USART_ROUTELOC0_CLKLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1788 #define _USART_ROUTELOC0_CLKLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1789 #define _USART_ROUTELOC0_CLKLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1790 #define _USART_ROUTELOC0_CLKLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1791 #define _USART_ROUTELOC0_CLKLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1792 #define _USART_ROUTELOC0_CLKLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1793 #define _USART_ROUTELOC0_CLKLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1794 #define _USART_ROUTELOC0_CLKLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1795 #define _USART_ROUTELOC0_CLKLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1796 #define USART_ROUTELOC0_CLKLOC_LOC0 (_USART_ROUTELOC0_CLKLOC_LOC0 << 24) /**< Shifted mode LOC0 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1797 #define USART_ROUTELOC0_CLKLOC_DEFAULT (_USART_ROUTELOC0_CLKLOC_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1798 #define USART_ROUTELOC0_CLKLOC_LOC1 (_USART_ROUTELOC0_CLKLOC_LOC1 << 24) /**< Shifted mode LOC1 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1799 #define USART_ROUTELOC0_CLKLOC_LOC2 (_USART_ROUTELOC0_CLKLOC_LOC2 << 24) /**< Shifted mode LOC2 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1800 #define USART_ROUTELOC0_CLKLOC_LOC3 (_USART_ROUTELOC0_CLKLOC_LOC3 << 24) /**< Shifted mode LOC3 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1801 #define USART_ROUTELOC0_CLKLOC_LOC4 (_USART_ROUTELOC0_CLKLOC_LOC4 << 24) /**< Shifted mode LOC4 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1802 #define USART_ROUTELOC0_CLKLOC_LOC5 (_USART_ROUTELOC0_CLKLOC_LOC5 << 24) /**< Shifted mode LOC5 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1803 #define USART_ROUTELOC0_CLKLOC_LOC6 (_USART_ROUTELOC0_CLKLOC_LOC6 << 24) /**< Shifted mode LOC6 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1804 #define USART_ROUTELOC0_CLKLOC_LOC7 (_USART_ROUTELOC0_CLKLOC_LOC7 << 24) /**< Shifted mode LOC7 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1805 #define USART_ROUTELOC0_CLKLOC_LOC8 (_USART_ROUTELOC0_CLKLOC_LOC8 << 24) /**< Shifted mode LOC8 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1806 #define USART_ROUTELOC0_CLKLOC_LOC9 (_USART_ROUTELOC0_CLKLOC_LOC9 << 24) /**< Shifted mode LOC9 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1807 #define USART_ROUTELOC0_CLKLOC_LOC10 (_USART_ROUTELOC0_CLKLOC_LOC10 << 24) /**< Shifted mode LOC10 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1808 #define USART_ROUTELOC0_CLKLOC_LOC11 (_USART_ROUTELOC0_CLKLOC_LOC11 << 24) /**< Shifted mode LOC11 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1809 #define USART_ROUTELOC0_CLKLOC_LOC12 (_USART_ROUTELOC0_CLKLOC_LOC12 << 24) /**< Shifted mode LOC12 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1810 #define USART_ROUTELOC0_CLKLOC_LOC13 (_USART_ROUTELOC0_CLKLOC_LOC13 << 24) /**< Shifted mode LOC13 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1811 #define USART_ROUTELOC0_CLKLOC_LOC14 (_USART_ROUTELOC0_CLKLOC_LOC14 << 24) /**< Shifted mode LOC14 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1812 #define USART_ROUTELOC0_CLKLOC_LOC15 (_USART_ROUTELOC0_CLKLOC_LOC15 << 24) /**< Shifted mode LOC15 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1813 #define USART_ROUTELOC0_CLKLOC_LOC16 (_USART_ROUTELOC0_CLKLOC_LOC16 << 24) /**< Shifted mode LOC16 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1814 #define USART_ROUTELOC0_CLKLOC_LOC17 (_USART_ROUTELOC0_CLKLOC_LOC17 << 24) /**< Shifted mode LOC17 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1815 #define USART_ROUTELOC0_CLKLOC_LOC18 (_USART_ROUTELOC0_CLKLOC_LOC18 << 24) /**< Shifted mode LOC18 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1816 #define USART_ROUTELOC0_CLKLOC_LOC19 (_USART_ROUTELOC0_CLKLOC_LOC19 << 24) /**< Shifted mode LOC19 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1817 #define USART_ROUTELOC0_CLKLOC_LOC20 (_USART_ROUTELOC0_CLKLOC_LOC20 << 24) /**< Shifted mode LOC20 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1818 #define USART_ROUTELOC0_CLKLOC_LOC21 (_USART_ROUTELOC0_CLKLOC_LOC21 << 24) /**< Shifted mode LOC21 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1819 #define USART_ROUTELOC0_CLKLOC_LOC22 (_USART_ROUTELOC0_CLKLOC_LOC22 << 24) /**< Shifted mode LOC22 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1820 #define USART_ROUTELOC0_CLKLOC_LOC23 (_USART_ROUTELOC0_CLKLOC_LOC23 << 24) /**< Shifted mode LOC23 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1821 #define USART_ROUTELOC0_CLKLOC_LOC24 (_USART_ROUTELOC0_CLKLOC_LOC24 << 24) /**< Shifted mode LOC24 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1822 #define USART_ROUTELOC0_CLKLOC_LOC25 (_USART_ROUTELOC0_CLKLOC_LOC25 << 24) /**< Shifted mode LOC25 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1823 #define USART_ROUTELOC0_CLKLOC_LOC26 (_USART_ROUTELOC0_CLKLOC_LOC26 << 24) /**< Shifted mode LOC26 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1824 #define USART_ROUTELOC0_CLKLOC_LOC27 (_USART_ROUTELOC0_CLKLOC_LOC27 << 24) /**< Shifted mode LOC27 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1825 #define USART_ROUTELOC0_CLKLOC_LOC28 (_USART_ROUTELOC0_CLKLOC_LOC28 << 24) /**< Shifted mode LOC28 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1826 #define USART_ROUTELOC0_CLKLOC_LOC29 (_USART_ROUTELOC0_CLKLOC_LOC29 << 24) /**< Shifted mode LOC29 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1827 #define USART_ROUTELOC0_CLKLOC_LOC30 (_USART_ROUTELOC0_CLKLOC_LOC30 << 24) /**< Shifted mode LOC30 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1828 #define USART_ROUTELOC0_CLKLOC_LOC31 (_USART_ROUTELOC0_CLKLOC_LOC31 << 24) /**< Shifted mode LOC31 for USART_ROUTELOC0 */
mbed_official 50:a417edff4437 1829
mbed_official 50:a417edff4437 1830 /* Bit fields for USART ROUTELOC1 */
mbed_official 50:a417edff4437 1831 #define _USART_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1832 #define _USART_ROUTELOC1_MASK 0x00001F1FUL /**< Mask for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1833 #define _USART_ROUTELOC1_CTSLOC_SHIFT 0 /**< Shift value for USART_CTSLOC */
mbed_official 50:a417edff4437 1834 #define _USART_ROUTELOC1_CTSLOC_MASK 0x1FUL /**< Bit mask for USART_CTSLOC */
mbed_official 50:a417edff4437 1835 #define _USART_ROUTELOC1_CTSLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1836 #define _USART_ROUTELOC1_CTSLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1837 #define _USART_ROUTELOC1_CTSLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1838 #define _USART_ROUTELOC1_CTSLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1839 #define _USART_ROUTELOC1_CTSLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1840 #define _USART_ROUTELOC1_CTSLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1841 #define _USART_ROUTELOC1_CTSLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1842 #define _USART_ROUTELOC1_CTSLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1843 #define _USART_ROUTELOC1_CTSLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1844 #define _USART_ROUTELOC1_CTSLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1845 #define _USART_ROUTELOC1_CTSLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1846 #define _USART_ROUTELOC1_CTSLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1847 #define _USART_ROUTELOC1_CTSLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1848 #define _USART_ROUTELOC1_CTSLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1849 #define _USART_ROUTELOC1_CTSLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1850 #define _USART_ROUTELOC1_CTSLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1851 #define _USART_ROUTELOC1_CTSLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1852 #define _USART_ROUTELOC1_CTSLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1853 #define _USART_ROUTELOC1_CTSLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1854 #define _USART_ROUTELOC1_CTSLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1855 #define _USART_ROUTELOC1_CTSLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1856 #define _USART_ROUTELOC1_CTSLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1857 #define _USART_ROUTELOC1_CTSLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1858 #define _USART_ROUTELOC1_CTSLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1859 #define _USART_ROUTELOC1_CTSLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1860 #define _USART_ROUTELOC1_CTSLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1861 #define _USART_ROUTELOC1_CTSLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1862 #define _USART_ROUTELOC1_CTSLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1863 #define _USART_ROUTELOC1_CTSLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1864 #define _USART_ROUTELOC1_CTSLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1865 #define _USART_ROUTELOC1_CTSLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1866 #define _USART_ROUTELOC1_CTSLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1867 #define _USART_ROUTELOC1_CTSLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1868 #define USART_ROUTELOC1_CTSLOC_LOC0 (_USART_ROUTELOC1_CTSLOC_LOC0 << 0) /**< Shifted mode LOC0 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1869 #define USART_ROUTELOC1_CTSLOC_DEFAULT (_USART_ROUTELOC1_CTSLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1870 #define USART_ROUTELOC1_CTSLOC_LOC1 (_USART_ROUTELOC1_CTSLOC_LOC1 << 0) /**< Shifted mode LOC1 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1871 #define USART_ROUTELOC1_CTSLOC_LOC2 (_USART_ROUTELOC1_CTSLOC_LOC2 << 0) /**< Shifted mode LOC2 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1872 #define USART_ROUTELOC1_CTSLOC_LOC3 (_USART_ROUTELOC1_CTSLOC_LOC3 << 0) /**< Shifted mode LOC3 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1873 #define USART_ROUTELOC1_CTSLOC_LOC4 (_USART_ROUTELOC1_CTSLOC_LOC4 << 0) /**< Shifted mode LOC4 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1874 #define USART_ROUTELOC1_CTSLOC_LOC5 (_USART_ROUTELOC1_CTSLOC_LOC5 << 0) /**< Shifted mode LOC5 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1875 #define USART_ROUTELOC1_CTSLOC_LOC6 (_USART_ROUTELOC1_CTSLOC_LOC6 << 0) /**< Shifted mode LOC6 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1876 #define USART_ROUTELOC1_CTSLOC_LOC7 (_USART_ROUTELOC1_CTSLOC_LOC7 << 0) /**< Shifted mode LOC7 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1877 #define USART_ROUTELOC1_CTSLOC_LOC8 (_USART_ROUTELOC1_CTSLOC_LOC8 << 0) /**< Shifted mode LOC8 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1878 #define USART_ROUTELOC1_CTSLOC_LOC9 (_USART_ROUTELOC1_CTSLOC_LOC9 << 0) /**< Shifted mode LOC9 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1879 #define USART_ROUTELOC1_CTSLOC_LOC10 (_USART_ROUTELOC1_CTSLOC_LOC10 << 0) /**< Shifted mode LOC10 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1880 #define USART_ROUTELOC1_CTSLOC_LOC11 (_USART_ROUTELOC1_CTSLOC_LOC11 << 0) /**< Shifted mode LOC11 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1881 #define USART_ROUTELOC1_CTSLOC_LOC12 (_USART_ROUTELOC1_CTSLOC_LOC12 << 0) /**< Shifted mode LOC12 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1882 #define USART_ROUTELOC1_CTSLOC_LOC13 (_USART_ROUTELOC1_CTSLOC_LOC13 << 0) /**< Shifted mode LOC13 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1883 #define USART_ROUTELOC1_CTSLOC_LOC14 (_USART_ROUTELOC1_CTSLOC_LOC14 << 0) /**< Shifted mode LOC14 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1884 #define USART_ROUTELOC1_CTSLOC_LOC15 (_USART_ROUTELOC1_CTSLOC_LOC15 << 0) /**< Shifted mode LOC15 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1885 #define USART_ROUTELOC1_CTSLOC_LOC16 (_USART_ROUTELOC1_CTSLOC_LOC16 << 0) /**< Shifted mode LOC16 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1886 #define USART_ROUTELOC1_CTSLOC_LOC17 (_USART_ROUTELOC1_CTSLOC_LOC17 << 0) /**< Shifted mode LOC17 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1887 #define USART_ROUTELOC1_CTSLOC_LOC18 (_USART_ROUTELOC1_CTSLOC_LOC18 << 0) /**< Shifted mode LOC18 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1888 #define USART_ROUTELOC1_CTSLOC_LOC19 (_USART_ROUTELOC1_CTSLOC_LOC19 << 0) /**< Shifted mode LOC19 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1889 #define USART_ROUTELOC1_CTSLOC_LOC20 (_USART_ROUTELOC1_CTSLOC_LOC20 << 0) /**< Shifted mode LOC20 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1890 #define USART_ROUTELOC1_CTSLOC_LOC21 (_USART_ROUTELOC1_CTSLOC_LOC21 << 0) /**< Shifted mode LOC21 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1891 #define USART_ROUTELOC1_CTSLOC_LOC22 (_USART_ROUTELOC1_CTSLOC_LOC22 << 0) /**< Shifted mode LOC22 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1892 #define USART_ROUTELOC1_CTSLOC_LOC23 (_USART_ROUTELOC1_CTSLOC_LOC23 << 0) /**< Shifted mode LOC23 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1893 #define USART_ROUTELOC1_CTSLOC_LOC24 (_USART_ROUTELOC1_CTSLOC_LOC24 << 0) /**< Shifted mode LOC24 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1894 #define USART_ROUTELOC1_CTSLOC_LOC25 (_USART_ROUTELOC1_CTSLOC_LOC25 << 0) /**< Shifted mode LOC25 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1895 #define USART_ROUTELOC1_CTSLOC_LOC26 (_USART_ROUTELOC1_CTSLOC_LOC26 << 0) /**< Shifted mode LOC26 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1896 #define USART_ROUTELOC1_CTSLOC_LOC27 (_USART_ROUTELOC1_CTSLOC_LOC27 << 0) /**< Shifted mode LOC27 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1897 #define USART_ROUTELOC1_CTSLOC_LOC28 (_USART_ROUTELOC1_CTSLOC_LOC28 << 0) /**< Shifted mode LOC28 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1898 #define USART_ROUTELOC1_CTSLOC_LOC29 (_USART_ROUTELOC1_CTSLOC_LOC29 << 0) /**< Shifted mode LOC29 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1899 #define USART_ROUTELOC1_CTSLOC_LOC30 (_USART_ROUTELOC1_CTSLOC_LOC30 << 0) /**< Shifted mode LOC30 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1900 #define USART_ROUTELOC1_CTSLOC_LOC31 (_USART_ROUTELOC1_CTSLOC_LOC31 << 0) /**< Shifted mode LOC31 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1901 #define _USART_ROUTELOC1_RTSLOC_SHIFT 8 /**< Shift value for USART_RTSLOC */
mbed_official 50:a417edff4437 1902 #define _USART_ROUTELOC1_RTSLOC_MASK 0x1F00UL /**< Bit mask for USART_RTSLOC */
mbed_official 50:a417edff4437 1903 #define _USART_ROUTELOC1_RTSLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1904 #define _USART_ROUTELOC1_RTSLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1905 #define _USART_ROUTELOC1_RTSLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1906 #define _USART_ROUTELOC1_RTSLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1907 #define _USART_ROUTELOC1_RTSLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1908 #define _USART_ROUTELOC1_RTSLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1909 #define _USART_ROUTELOC1_RTSLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1910 #define _USART_ROUTELOC1_RTSLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1911 #define _USART_ROUTELOC1_RTSLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1912 #define _USART_ROUTELOC1_RTSLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1913 #define _USART_ROUTELOC1_RTSLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1914 #define _USART_ROUTELOC1_RTSLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1915 #define _USART_ROUTELOC1_RTSLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1916 #define _USART_ROUTELOC1_RTSLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1917 #define _USART_ROUTELOC1_RTSLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1918 #define _USART_ROUTELOC1_RTSLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1919 #define _USART_ROUTELOC1_RTSLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1920 #define _USART_ROUTELOC1_RTSLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1921 #define _USART_ROUTELOC1_RTSLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1922 #define _USART_ROUTELOC1_RTSLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1923 #define _USART_ROUTELOC1_RTSLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1924 #define _USART_ROUTELOC1_RTSLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1925 #define _USART_ROUTELOC1_RTSLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1926 #define _USART_ROUTELOC1_RTSLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1927 #define _USART_ROUTELOC1_RTSLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1928 #define _USART_ROUTELOC1_RTSLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1929 #define _USART_ROUTELOC1_RTSLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1930 #define _USART_ROUTELOC1_RTSLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1931 #define _USART_ROUTELOC1_RTSLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1932 #define _USART_ROUTELOC1_RTSLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1933 #define _USART_ROUTELOC1_RTSLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1934 #define _USART_ROUTELOC1_RTSLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1935 #define _USART_ROUTELOC1_RTSLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1936 #define USART_ROUTELOC1_RTSLOC_LOC0 (_USART_ROUTELOC1_RTSLOC_LOC0 << 8) /**< Shifted mode LOC0 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1937 #define USART_ROUTELOC1_RTSLOC_DEFAULT (_USART_ROUTELOC1_RTSLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1938 #define USART_ROUTELOC1_RTSLOC_LOC1 (_USART_ROUTELOC1_RTSLOC_LOC1 << 8) /**< Shifted mode LOC1 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1939 #define USART_ROUTELOC1_RTSLOC_LOC2 (_USART_ROUTELOC1_RTSLOC_LOC2 << 8) /**< Shifted mode LOC2 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1940 #define USART_ROUTELOC1_RTSLOC_LOC3 (_USART_ROUTELOC1_RTSLOC_LOC3 << 8) /**< Shifted mode LOC3 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1941 #define USART_ROUTELOC1_RTSLOC_LOC4 (_USART_ROUTELOC1_RTSLOC_LOC4 << 8) /**< Shifted mode LOC4 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1942 #define USART_ROUTELOC1_RTSLOC_LOC5 (_USART_ROUTELOC1_RTSLOC_LOC5 << 8) /**< Shifted mode LOC5 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1943 #define USART_ROUTELOC1_RTSLOC_LOC6 (_USART_ROUTELOC1_RTSLOC_LOC6 << 8) /**< Shifted mode LOC6 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1944 #define USART_ROUTELOC1_RTSLOC_LOC7 (_USART_ROUTELOC1_RTSLOC_LOC7 << 8) /**< Shifted mode LOC7 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1945 #define USART_ROUTELOC1_RTSLOC_LOC8 (_USART_ROUTELOC1_RTSLOC_LOC8 << 8) /**< Shifted mode LOC8 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1946 #define USART_ROUTELOC1_RTSLOC_LOC9 (_USART_ROUTELOC1_RTSLOC_LOC9 << 8) /**< Shifted mode LOC9 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1947 #define USART_ROUTELOC1_RTSLOC_LOC10 (_USART_ROUTELOC1_RTSLOC_LOC10 << 8) /**< Shifted mode LOC10 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1948 #define USART_ROUTELOC1_RTSLOC_LOC11 (_USART_ROUTELOC1_RTSLOC_LOC11 << 8) /**< Shifted mode LOC11 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1949 #define USART_ROUTELOC1_RTSLOC_LOC12 (_USART_ROUTELOC1_RTSLOC_LOC12 << 8) /**< Shifted mode LOC12 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1950 #define USART_ROUTELOC1_RTSLOC_LOC13 (_USART_ROUTELOC1_RTSLOC_LOC13 << 8) /**< Shifted mode LOC13 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1951 #define USART_ROUTELOC1_RTSLOC_LOC14 (_USART_ROUTELOC1_RTSLOC_LOC14 << 8) /**< Shifted mode LOC14 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1952 #define USART_ROUTELOC1_RTSLOC_LOC15 (_USART_ROUTELOC1_RTSLOC_LOC15 << 8) /**< Shifted mode LOC15 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1953 #define USART_ROUTELOC1_RTSLOC_LOC16 (_USART_ROUTELOC1_RTSLOC_LOC16 << 8) /**< Shifted mode LOC16 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1954 #define USART_ROUTELOC1_RTSLOC_LOC17 (_USART_ROUTELOC1_RTSLOC_LOC17 << 8) /**< Shifted mode LOC17 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1955 #define USART_ROUTELOC1_RTSLOC_LOC18 (_USART_ROUTELOC1_RTSLOC_LOC18 << 8) /**< Shifted mode LOC18 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1956 #define USART_ROUTELOC1_RTSLOC_LOC19 (_USART_ROUTELOC1_RTSLOC_LOC19 << 8) /**< Shifted mode LOC19 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1957 #define USART_ROUTELOC1_RTSLOC_LOC20 (_USART_ROUTELOC1_RTSLOC_LOC20 << 8) /**< Shifted mode LOC20 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1958 #define USART_ROUTELOC1_RTSLOC_LOC21 (_USART_ROUTELOC1_RTSLOC_LOC21 << 8) /**< Shifted mode LOC21 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1959 #define USART_ROUTELOC1_RTSLOC_LOC22 (_USART_ROUTELOC1_RTSLOC_LOC22 << 8) /**< Shifted mode LOC22 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1960 #define USART_ROUTELOC1_RTSLOC_LOC23 (_USART_ROUTELOC1_RTSLOC_LOC23 << 8) /**< Shifted mode LOC23 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1961 #define USART_ROUTELOC1_RTSLOC_LOC24 (_USART_ROUTELOC1_RTSLOC_LOC24 << 8) /**< Shifted mode LOC24 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1962 #define USART_ROUTELOC1_RTSLOC_LOC25 (_USART_ROUTELOC1_RTSLOC_LOC25 << 8) /**< Shifted mode LOC25 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1963 #define USART_ROUTELOC1_RTSLOC_LOC26 (_USART_ROUTELOC1_RTSLOC_LOC26 << 8) /**< Shifted mode LOC26 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1964 #define USART_ROUTELOC1_RTSLOC_LOC27 (_USART_ROUTELOC1_RTSLOC_LOC27 << 8) /**< Shifted mode LOC27 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1965 #define USART_ROUTELOC1_RTSLOC_LOC28 (_USART_ROUTELOC1_RTSLOC_LOC28 << 8) /**< Shifted mode LOC28 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1966 #define USART_ROUTELOC1_RTSLOC_LOC29 (_USART_ROUTELOC1_RTSLOC_LOC29 << 8) /**< Shifted mode LOC29 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1967 #define USART_ROUTELOC1_RTSLOC_LOC30 (_USART_ROUTELOC1_RTSLOC_LOC30 << 8) /**< Shifted mode LOC30 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1968 #define USART_ROUTELOC1_RTSLOC_LOC31 (_USART_ROUTELOC1_RTSLOC_LOC31 << 8) /**< Shifted mode LOC31 for USART_ROUTELOC1 */
mbed_official 50:a417edff4437 1969
mbed_official 50:a417edff4437 1970 /** @} End of group EFM32PG1B_USART */
mbed_official 50:a417edff4437 1971 /** @} End of group Parts */
mbed_official 50:a417edff4437 1972