Fawwaz Nadzmy / mbed-STM

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targets/TARGET_ARM_SSG/TARGET_IOTSS/SDK/fpga.c@153:9398a535854b, 2016-12-22 (annotated)

Committer:
fwndz
Date:
Thu Dec 22 05:12:40 2016 +0000
Revision:
153:9398a535854b
Parent:
149:156823d33999 
device target maximize

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2006-2015 ARM Limited
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 * ----------------------------------------------------------------
<> 144:ef7eb2e8f9f7 16 * File: fpga.c
<> 144:ef7eb2e8f9f7 17 * Release: Version 1.0
<> 144:ef7eb2e8f9f7 18 * ----------------------------------------------------------------
<> 144:ef7eb2e8f9f7 19 */
<> 144:ef7eb2e8f9f7 20
<> 144:ef7eb2e8f9f7 21 /*
<> 144:ef7eb2e8f9f7 22 * Code implementation file for the fpga functions.
<> 144:ef7eb2e8f9f7 23 */
<> 144:ef7eb2e8f9f7 24
<> 144:ef7eb2e8f9f7 25 #include "SMM_MPS2.h" // MPS2 common header
<> 144:ef7eb2e8f9f7 26
<> 144:ef7eb2e8f9f7 27 // Function to delay n*ticks (25MHz = 40nS per tick)
<> 144:ef7eb2e8f9f7 28 // Used for I2C drivers
<> 144:ef7eb2e8f9f7 29 void i2c_delay(unsigned int tick)
<> 144:ef7eb2e8f9f7 30 {
<> 144:ef7eb2e8f9f7 31 unsigned int end;
<> 144:ef7eb2e8f9f7 32 unsigned int start;
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 start = MPS2_FPGAIO->COUNTER;
<> 144:ef7eb2e8f9f7 35 end = start + (tick);
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 if(end >= start)
<> 144:ef7eb2e8f9f7 38 {
<> 144:ef7eb2e8f9f7 39 while (MPS2_FPGAIO->COUNTER >= start && MPS2_FPGAIO->COUNTER < end);
<> 144:ef7eb2e8f9f7 40 }
<> 144:ef7eb2e8f9f7 41 else
<> 144:ef7eb2e8f9f7 42 {
<> 144:ef7eb2e8f9f7 43 while (MPS2_FPGAIO->COUNTER >= start);
<> 144:ef7eb2e8f9f7 44 while (MPS2_FPGAIO->COUNTER < end);
<> 144:ef7eb2e8f9f7 45 }
<> 144:ef7eb2e8f9f7 46 }
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 /* Sleep function to delay n*mS
<> 144:ef7eb2e8f9f7 49 * Uses FPGA counter.
<> 144:ef7eb2e8f9f7 50 */
<> 144:ef7eb2e8f9f7 51 void Sleepms(unsigned int msec)
<> 144:ef7eb2e8f9f7 52 {
<> 144:ef7eb2e8f9f7 53 unsigned int end;
<> 144:ef7eb2e8f9f7 54 unsigned int start;
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 start = MPS2_FPGAIO->COUNTER;
<> 144:ef7eb2e8f9f7 57 end = start + (25 * msec * 1000);
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 if(end >= start)
<> 144:ef7eb2e8f9f7 60 {
<> 144:ef7eb2e8f9f7 61 while (MPS2_FPGAIO->COUNTER >= start && MPS2_FPGAIO->COUNTER < end);
<> 144:ef7eb2e8f9f7 62 }
<> 144:ef7eb2e8f9f7 63 else
<> 144:ef7eb2e8f9f7 64 {
<> 144:ef7eb2e8f9f7 65 while (MPS2_FPGAIO->COUNTER >= start);
<> 144:ef7eb2e8f9f7 66 while (MPS2_FPGAIO->COUNTER < end);
<> 144:ef7eb2e8f9f7 67 }
<> 144:ef7eb2e8f9f7 68 }
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 /* Sleep function to delay n*uS
<> 144:ef7eb2e8f9f7 71 */
<> 144:ef7eb2e8f9f7 72 void Sleepus(unsigned int usec)
<> 144:ef7eb2e8f9f7 73 {
<> 144:ef7eb2e8f9f7 74 unsigned int end;
<> 144:ef7eb2e8f9f7 75 unsigned int start;
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 start = MPS2_FPGAIO->COUNTER;
<> 144:ef7eb2e8f9f7 78 end = start + (25 * usec);
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 if(end >= start)
<> 144:ef7eb2e8f9f7 81 {
<> 144:ef7eb2e8f9f7 82 while (MPS2_FPGAIO->COUNTER >= start && MPS2_FPGAIO->COUNTER < end);
<> 144:ef7eb2e8f9f7 83 }
<> 144:ef7eb2e8f9f7 84 else
<> 144:ef7eb2e8f9f7 85 {
<> 144:ef7eb2e8f9f7 86 while (MPS2_FPGAIO->COUNTER >= start);
<> 144:ef7eb2e8f9f7 87 while (MPS2_FPGAIO->COUNTER < end);
<> 144:ef7eb2e8f9f7 88 }
<> 144:ef7eb2e8f9f7 89 }
<> 144:ef7eb2e8f9f7 90