Fawwaz Nadzmy / mbed-STM

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targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/system_stm32l0xx.c@151:5eaa88a5bcc7, 2016-11-24 (annotated)

Committer:
<>
Date:
Thu Nov 24 17:03:03 2016 +0000
Revision:
151:5eaa88a5bcc7
Parent:
149:156823d33999 
This updates the lib to the mbed lib v130

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 114:fe4fe5cfc3a3 1 /**
mbed_official 114:fe4fe5cfc3a3 2 ******************************************************************************
mbed_official 114:fe4fe5cfc3a3 3 * @file system_stm32l0xx.c
mbed_official 114:fe4fe5cfc3a3 4 * @author MCD Application Team
<> 151:5eaa88a5bcc7 5 * @version V1.7.0
<> 151:5eaa88a5bcc7 6 * @date 31-May-2016
mbed_official 114:fe4fe5cfc3a3 7 * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File.
mbed_official 114:fe4fe5cfc3a3 8 *
mbed_official 114:fe4fe5cfc3a3 9 * This file provides two functions and one global variable to be called from
mbed_official 114:fe4fe5cfc3a3 10 * user application:
mbed_official 114:fe4fe5cfc3a3 11 * - SystemInit(): This function is called at startup just after reset and
mbed_official 114:fe4fe5cfc3a3 12 * before branch to main program. This call is made inside
mbed_official 114:fe4fe5cfc3a3 13 * the "startup_stm32l0xx.s" file.
mbed_official 114:fe4fe5cfc3a3 14 *
mbed_official 114:fe4fe5cfc3a3 15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
mbed_official 114:fe4fe5cfc3a3 16 * by the user application to setup the SysTick
mbed_official 114:fe4fe5cfc3a3 17 * timer or configure other parameters.
mbed_official 114:fe4fe5cfc3a3 18 *
mbed_official 114:fe4fe5cfc3a3 19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
mbed_official 114:fe4fe5cfc3a3 20 * be called whenever the core clock is changed
mbed_official 114:fe4fe5cfc3a3 21 * during program execution.
mbed_official 114:fe4fe5cfc3a3 22 *
mbed_official 114:fe4fe5cfc3a3 23 * This file configures the system clock as follows:
mbed_official 114:fe4fe5cfc3a3 24 *-----------------------------------------------------------------------------
mbed_official 114:fe4fe5cfc3a3 25 * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
mbed_official 114:fe4fe5cfc3a3 26 * | (external 8 MHz clock) | (internal 16 MHz)
mbed_official 114:fe4fe5cfc3a3 27 * | 2- PLL_HSE_XTAL |
mbed_official 114:fe4fe5cfc3a3 28 * | (external 8 MHz xtal) |
mbed_official 114:fe4fe5cfc3a3 29 *-----------------------------------------------------------------------------
mbed_official 114:fe4fe5cfc3a3 30 * SYSCLK(MHz) | 32 | 32
mbed_official 114:fe4fe5cfc3a3 31 *-----------------------------------------------------------------------------
mbed_official 114:fe4fe5cfc3a3 32 * AHBCLK (MHz) | 32 | 32
mbed_official 114:fe4fe5cfc3a3 33 *-----------------------------------------------------------------------------
mbed_official 114:fe4fe5cfc3a3 34 * APB1CLK (MHz) | 32 | 32
mbed_official 114:fe4fe5cfc3a3 35 *-----------------------------------------------------------------------------
mbed_official 114:fe4fe5cfc3a3 36 * APB2CLK (MHz) | 32 | 32
mbed_official 114:fe4fe5cfc3a3 37 *-----------------------------------------------------------------------------
mbed_official 114:fe4fe5cfc3a3 38 * USB capable (48 MHz precise clock) | YES | YES
mbed_official 114:fe4fe5cfc3a3 39 *-----------------------------------------------------------------------------
mbed_official 114:fe4fe5cfc3a3 40 ******************************************************************************
mbed_official 114:fe4fe5cfc3a3 41 * @attention
mbed_official 114:fe4fe5cfc3a3 42 *
<> 151:5eaa88a5bcc7 43 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
mbed_official 114:fe4fe5cfc3a3 44 *
mbed_official 114:fe4fe5cfc3a3 45 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 114:fe4fe5cfc3a3 46 * are permitted provided that the following conditions are met:
mbed_official 114:fe4fe5cfc3a3 47 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 114:fe4fe5cfc3a3 48 * this list of conditions and the following disclaimer.
mbed_official 114:fe4fe5cfc3a3 49 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 114:fe4fe5cfc3a3 50 * this list of conditions and the following disclaimer in the documentation
mbed_official 114:fe4fe5cfc3a3 51 * and/or other materials provided with the distribution.
mbed_official 114:fe4fe5cfc3a3 52 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 114:fe4fe5cfc3a3 53 * may be used to endorse or promote products derived from this software
mbed_official 114:fe4fe5cfc3a3 54 * without specific prior written permission.
mbed_official 114:fe4fe5cfc3a3 55 *
mbed_official 114:fe4fe5cfc3a3 56 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 114:fe4fe5cfc3a3 57 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 114:fe4fe5cfc3a3 58 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 114:fe4fe5cfc3a3 59 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 114:fe4fe5cfc3a3 60 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 114:fe4fe5cfc3a3 61 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 114:fe4fe5cfc3a3 62 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 114:fe4fe5cfc3a3 63 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 114:fe4fe5cfc3a3 64 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 114:fe4fe5cfc3a3 65 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 114:fe4fe5cfc3a3 66 *
mbed_official 114:fe4fe5cfc3a3 67 ******************************************************************************
mbed_official 114:fe4fe5cfc3a3 68 */
mbed_official 114:fe4fe5cfc3a3 69
mbed_official 114:fe4fe5cfc3a3 70 /** @addtogroup CMSIS
mbed_official 114:fe4fe5cfc3a3 71 * @{
mbed_official 114:fe4fe5cfc3a3 72 */
mbed_official 114:fe4fe5cfc3a3 73
mbed_official 114:fe4fe5cfc3a3 74 /** @addtogroup stm32l0xx_system
mbed_official 114:fe4fe5cfc3a3 75 * @{
mbed_official 114:fe4fe5cfc3a3 76 */
mbed_official 114:fe4fe5cfc3a3 77
mbed_official 114:fe4fe5cfc3a3 78 /** @addtogroup STM32L0xx_System_Private_Includes
mbed_official 114:fe4fe5cfc3a3 79 * @{
mbed_official 114:fe4fe5cfc3a3 80 */
mbed_official 114:fe4fe5cfc3a3 81
mbed_official 114:fe4fe5cfc3a3 82 #include "stm32l0xx.h"
mbed_official 114:fe4fe5cfc3a3 83 #include "hal_tick.h"
mbed_official 114:fe4fe5cfc3a3 84
mbed_official 114:fe4fe5cfc3a3 85 #if !defined (HSE_VALUE)
<> 151:5eaa88a5bcc7 86 #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
mbed_official 114:fe4fe5cfc3a3 87 #endif /* HSE_VALUE */
mbed_official 114:fe4fe5cfc3a3 88
mbed_official 114:fe4fe5cfc3a3 89 #if !defined (MSI_VALUE)
<> 151:5eaa88a5bcc7 90 #define MSI_VALUE ((uint32_t)2000000U) /*!< Value of the Internal oscillator in Hz*/
mbed_official 114:fe4fe5cfc3a3 91 #endif /* MSI_VALUE */
mbed_official 114:fe4fe5cfc3a3 92
mbed_official 114:fe4fe5cfc3a3 93 #if !defined (HSI_VALUE)
<> 151:5eaa88a5bcc7 94 #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
mbed_official 114:fe4fe5cfc3a3 95 #endif /* HSI_VALUE */
mbed_official 114:fe4fe5cfc3a3 96
mbed_official 114:fe4fe5cfc3a3 97
mbed_official 114:fe4fe5cfc3a3 98 /**
mbed_official 114:fe4fe5cfc3a3 99 * @}
mbed_official 114:fe4fe5cfc3a3 100 */
mbed_official 114:fe4fe5cfc3a3 101
mbed_official 114:fe4fe5cfc3a3 102 /** @addtogroup STM32L0xx_System_Private_TypesDefinitions
mbed_official 114:fe4fe5cfc3a3 103 * @{
mbed_official 114:fe4fe5cfc3a3 104 */
mbed_official 114:fe4fe5cfc3a3 105
mbed_official 114:fe4fe5cfc3a3 106 /**
mbed_official 114:fe4fe5cfc3a3 107 * @}
mbed_official 114:fe4fe5cfc3a3 108 */
mbed_official 114:fe4fe5cfc3a3 109
mbed_official 114:fe4fe5cfc3a3 110 /** @addtogroup STM32L0xx_System_Private_Defines
mbed_official 114:fe4fe5cfc3a3 111 * @{
mbed_official 114:fe4fe5cfc3a3 112 */
mbed_official 114:fe4fe5cfc3a3 113 /************************* Miscellaneous Configuration ************************/
mbed_official 114:fe4fe5cfc3a3 114
mbed_official 114:fe4fe5cfc3a3 115 /*!< Uncomment the following line if you need to relocate your vector Table in
mbed_official 114:fe4fe5cfc3a3 116 Internal SRAM. */
mbed_official 114:fe4fe5cfc3a3 117 /* #define VECT_TAB_SRAM */
<> 151:5eaa88a5bcc7 118 #define VECT_TAB_OFFSET 0x00U /*!< Vector Table base offset field.
<> 151:5eaa88a5bcc7 119 This value must be a multiple of 0x100. */
mbed_official 114:fe4fe5cfc3a3 120 /******************************************************************************/
mbed_official 114:fe4fe5cfc3a3 121 /**
mbed_official 114:fe4fe5cfc3a3 122 * @}
mbed_official 114:fe4fe5cfc3a3 123 */
mbed_official 114:fe4fe5cfc3a3 124
mbed_official 114:fe4fe5cfc3a3 125 /** @addtogroup STM32L0xx_System_Private_Macros
mbed_official 114:fe4fe5cfc3a3 126 * @{
mbed_official 114:fe4fe5cfc3a3 127 */
mbed_official 114:fe4fe5cfc3a3 128
mbed_official 114:fe4fe5cfc3a3 129 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
mbed_official 114:fe4fe5cfc3a3 130 #define USE_PLL_HSE_EXTC (0) /* Use external clock */
mbed_official 114:fe4fe5cfc3a3 131 #define USE_PLL_HSE_XTAL (0) /* Use external xtal */
mbed_official 114:fe4fe5cfc3a3 132 #define USE_MSI_OSC (0) /* Use multi-speed internal RC oscillator */
mbed_official 114:fe4fe5cfc3a3 133
mbed_official 114:fe4fe5cfc3a3 134 /**
mbed_official 114:fe4fe5cfc3a3 135 * @}
mbed_official 114:fe4fe5cfc3a3 136 */
mbed_official 114:fe4fe5cfc3a3 137
mbed_official 114:fe4fe5cfc3a3 138 /** @addtogroup STM32L0xx_System_Private_Variables
mbed_official 114:fe4fe5cfc3a3 139 * @{
mbed_official 114:fe4fe5cfc3a3 140 */
mbed_official 114:fe4fe5cfc3a3 141 /* This variable is updated in three ways:
mbed_official 114:fe4fe5cfc3a3 142 1) by calling CMSIS function SystemCoreClockUpdate()
mbed_official 114:fe4fe5cfc3a3 143 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
mbed_official 114:fe4fe5cfc3a3 144 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
mbed_official 114:fe4fe5cfc3a3 145 Note: If you use this function to configure the system clock; then there
mbed_official 114:fe4fe5cfc3a3 146 is no need to call the 2 first functions listed above, since SystemCoreClock
mbed_official 114:fe4fe5cfc3a3 147 variable is updated automatically.
mbed_official 114:fe4fe5cfc3a3 148 */
mbed_official 114:fe4fe5cfc3a3 149 uint32_t SystemCoreClock = 32000000;
<> 151:5eaa88a5bcc7 150 const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
<> 151:5eaa88a5bcc7 151 const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
<> 151:5eaa88a5bcc7 152 const uint8_t PLLMulTable[9] = {3U, 4U, 6U, 8U, 12U, 16U, 24U, 32U, 48U};
mbed_official 114:fe4fe5cfc3a3 153
mbed_official 114:fe4fe5cfc3a3 154 /**
mbed_official 114:fe4fe5cfc3a3 155 * @}
mbed_official 114:fe4fe5cfc3a3 156 */
mbed_official 114:fe4fe5cfc3a3 157
mbed_official 114:fe4fe5cfc3a3 158 /** @addtogroup STM32L0xx_System_Private_FunctionPrototypes
mbed_official 114:fe4fe5cfc3a3 159 * @{
mbed_official 114:fe4fe5cfc3a3 160 */
mbed_official 114:fe4fe5cfc3a3 161
mbed_official 114:fe4fe5cfc3a3 162 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
mbed_official 114:fe4fe5cfc3a3 163 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
mbed_official 114:fe4fe5cfc3a3 164 #endif
mbed_official 114:fe4fe5cfc3a3 165
mbed_official 114:fe4fe5cfc3a3 166 uint8_t SetSysClock_PLL_HSI(void);
mbed_official 114:fe4fe5cfc3a3 167 uint8_t SetSysClock_MSI(void);
mbed_official 114:fe4fe5cfc3a3 168
mbed_official 114:fe4fe5cfc3a3 169 /**
mbed_official 114:fe4fe5cfc3a3 170 * @}
mbed_official 114:fe4fe5cfc3a3 171 */
mbed_official 114:fe4fe5cfc3a3 172
mbed_official 114:fe4fe5cfc3a3 173 /** @addtogroup STM32L0xx_System_Private_Functions
mbed_official 114:fe4fe5cfc3a3 174 * @{
mbed_official 114:fe4fe5cfc3a3 175 */
mbed_official 114:fe4fe5cfc3a3 176
mbed_official 114:fe4fe5cfc3a3 177 /**
mbed_official 114:fe4fe5cfc3a3 178 * @brief Setup the microcontroller system.
mbed_official 114:fe4fe5cfc3a3 179 * @param None
mbed_official 114:fe4fe5cfc3a3 180 * @retval None
mbed_official 114:fe4fe5cfc3a3 181 */
mbed_official 114:fe4fe5cfc3a3 182 void SystemInit (void)
mbed_official 114:fe4fe5cfc3a3 183 {
mbed_official 114:fe4fe5cfc3a3 184 /*!< Set MSION bit */
<> 151:5eaa88a5bcc7 185 RCC->CR |= (uint32_t)0x00000100U;
mbed_official 114:fe4fe5cfc3a3 186
mbed_official 114:fe4fe5cfc3a3 187 /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
<> 151:5eaa88a5bcc7 188 RCC->CFGR &= (uint32_t) 0x88FF400CU;
mbed_official 114:fe4fe5cfc3a3 189
mbed_official 114:fe4fe5cfc3a3 190 /*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */
<> 151:5eaa88a5bcc7 191 RCC->CR &= (uint32_t)0xFEF6FFF6U;
mbed_official 114:fe4fe5cfc3a3 192
mbed_official 114:fe4fe5cfc3a3 193 /*!< Reset HSI48ON bit */
<> 151:5eaa88a5bcc7 194 RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
mbed_official 114:fe4fe5cfc3a3 195
mbed_official 114:fe4fe5cfc3a3 196 /*!< Reset HSEBYP bit */
<> 151:5eaa88a5bcc7 197 RCC->CR &= (uint32_t)0xFFFBFFFFU;
mbed_official 114:fe4fe5cfc3a3 198
mbed_official 114:fe4fe5cfc3a3 199 /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
<> 151:5eaa88a5bcc7 200 RCC->CFGR &= (uint32_t)0xFF02FFFFU;
mbed_official 114:fe4fe5cfc3a3 201
mbed_official 114:fe4fe5cfc3a3 202 /*!< Disable all interrupts */
<> 151:5eaa88a5bcc7 203 RCC->CIER = 0x00000000U;
mbed_official 114:fe4fe5cfc3a3 204
mbed_official 114:fe4fe5cfc3a3 205 /* Configure the Vector Table location add offset address ------------------*/
mbed_official 114:fe4fe5cfc3a3 206 #ifdef VECT_TAB_SRAM
mbed_official 114:fe4fe5cfc3a3 207 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
mbed_official 114:fe4fe5cfc3a3 208 #else
mbed_official 114:fe4fe5cfc3a3 209 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
mbed_official 114:fe4fe5cfc3a3 210 #endif
mbed_official 114:fe4fe5cfc3a3 211
mbed_official 114:fe4fe5cfc3a3 212 /* Configure the Cube driver */
mbed_official 114:fe4fe5cfc3a3 213 SystemCoreClock = 8000000; // At this stage the HSI is used as system clock
mbed_official 114:fe4fe5cfc3a3 214 HAL_Init();
mbed_official 114:fe4fe5cfc3a3 215
mbed_official 114:fe4fe5cfc3a3 216 /* Configure the System clock source, PLL Multiplier and Divider factors,
mbed_official 114:fe4fe5cfc3a3 217 AHB/APBx prescalers and Flash settings */
mbed_official 114:fe4fe5cfc3a3 218 SetSysClock();
mbed_official 114:fe4fe5cfc3a3 219
mbed_official 114:fe4fe5cfc3a3 220 /* Reset the timer to avoid issues after the RAM initialization */
mbed_official 114:fe4fe5cfc3a3 221 TIM_MST_RESET_ON;
mbed_official 114:fe4fe5cfc3a3 222 TIM_MST_RESET_OFF;
mbed_official 114:fe4fe5cfc3a3 223 }
mbed_official 114:fe4fe5cfc3a3 224
mbed_official 114:fe4fe5cfc3a3 225 /**
mbed_official 114:fe4fe5cfc3a3 226 * @brief Update SystemCoreClock according to Clock Register Values
mbed_official 114:fe4fe5cfc3a3 227 * The SystemCoreClock variable contains the core clock (HCLK), it can
mbed_official 114:fe4fe5cfc3a3 228 * be used by the user application to setup the SysTick timer or configure
mbed_official 114:fe4fe5cfc3a3 229 * other parameters.
mbed_official 114:fe4fe5cfc3a3 230 *
mbed_official 114:fe4fe5cfc3a3 231 * @note Each time the core clock (HCLK) changes, this function must be called
mbed_official 114:fe4fe5cfc3a3 232 * to update SystemCoreClock variable value. Otherwise, any configuration
mbed_official 114:fe4fe5cfc3a3 233 * based on this variable will be incorrect.
mbed_official 114:fe4fe5cfc3a3 234 *
mbed_official 114:fe4fe5cfc3a3 235 * @note - The system frequency computed by this function is not the real
mbed_official 114:fe4fe5cfc3a3 236 * frequency in the chip. It is calculated based on the predefined
mbed_official 114:fe4fe5cfc3a3 237 * constant and the selected clock source:
mbed_official 114:fe4fe5cfc3a3 238 *
mbed_official 114:fe4fe5cfc3a3 239 * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI
mbed_official 114:fe4fe5cfc3a3 240 * value as defined by the MSI range.
mbed_official 114:fe4fe5cfc3a3 241 *
mbed_official 114:fe4fe5cfc3a3 242 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
mbed_official 114:fe4fe5cfc3a3 243 *
mbed_official 114:fe4fe5cfc3a3 244 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 114:fe4fe5cfc3a3 245 *
mbed_official 114:fe4fe5cfc3a3 246 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 114:fe4fe5cfc3a3 247 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
mbed_official 114:fe4fe5cfc3a3 248 *
mbed_official 114:fe4fe5cfc3a3 249 * (*) HSI_VALUE is a constant defined in stm32l0xx_hal.h file (default value
mbed_official 114:fe4fe5cfc3a3 250 * 16 MHz) but the real value may vary depending on the variations
mbed_official 114:fe4fe5cfc3a3 251 * in voltage and temperature.
mbed_official 114:fe4fe5cfc3a3 252 *
mbed_official 114:fe4fe5cfc3a3 253 * (**) HSE_VALUE is a constant defined in stm32l0xx_hal.h file (default value
mbed_official 114:fe4fe5cfc3a3 254 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
mbed_official 114:fe4fe5cfc3a3 255 * frequency of the crystal used. Otherwise, this function may
mbed_official 114:fe4fe5cfc3a3 256 * have wrong result.
mbed_official 114:fe4fe5cfc3a3 257 *
mbed_official 114:fe4fe5cfc3a3 258 * - The result of this function could be not correct when using fractional
mbed_official 114:fe4fe5cfc3a3 259 * value for HSE crystal.
mbed_official 114:fe4fe5cfc3a3 260 * @param None
mbed_official 114:fe4fe5cfc3a3 261 * @retval None
mbed_official 114:fe4fe5cfc3a3 262 */
mbed_official 114:fe4fe5cfc3a3 263 void SystemCoreClockUpdate (void)
mbed_official 114:fe4fe5cfc3a3 264 {
<> 151:5eaa88a5bcc7 265 uint32_t tmp = 0U, pllmul = 0U, plldiv = 0U, pllsource = 0U, msirange = 0U;
mbed_official 114:fe4fe5cfc3a3 266
mbed_official 114:fe4fe5cfc3a3 267 /* Get SYSCLK source -------------------------------------------------------*/
mbed_official 114:fe4fe5cfc3a3 268 tmp = RCC->CFGR & RCC_CFGR_SWS;
mbed_official 114:fe4fe5cfc3a3 269
mbed_official 114:fe4fe5cfc3a3 270 switch (tmp)
mbed_official 114:fe4fe5cfc3a3 271 {
<> 151:5eaa88a5bcc7 272 case 0x00U: /* MSI used as system clock */
<> 151:5eaa88a5bcc7 273 msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U;
<> 151:5eaa88a5bcc7 274 SystemCoreClock = (32768U * (1U << (msirange + 1U)));
mbed_official 114:fe4fe5cfc3a3 275 break;
<> 151:5eaa88a5bcc7 276 case 0x04U: /* HSI used as system clock */
mbed_official 114:fe4fe5cfc3a3 277 SystemCoreClock = HSI_VALUE;
mbed_official 114:fe4fe5cfc3a3 278 break;
<> 151:5eaa88a5bcc7 279 case 0x08U: /* HSE used as system clock */
mbed_official 114:fe4fe5cfc3a3 280 SystemCoreClock = HSE_VALUE;
mbed_official 114:fe4fe5cfc3a3 281 break;
<> 151:5eaa88a5bcc7 282 case 0x0CU: /* PLL used as system clock */
mbed_official 114:fe4fe5cfc3a3 283 /* Get PLL clock source and multiplication factor ----------------------*/
mbed_official 114:fe4fe5cfc3a3 284 pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
mbed_official 114:fe4fe5cfc3a3 285 plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
<> 151:5eaa88a5bcc7 286 pllmul = PLLMulTable[(pllmul >> 18U)];
<> 151:5eaa88a5bcc7 287 plldiv = (plldiv >> 22U) + 1U;
mbed_official 114:fe4fe5cfc3a3 288
mbed_official 114:fe4fe5cfc3a3 289 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
mbed_official 114:fe4fe5cfc3a3 290
<> 151:5eaa88a5bcc7 291 if (pllsource == 0x00U)
mbed_official 114:fe4fe5cfc3a3 292 {
mbed_official 114:fe4fe5cfc3a3 293 /* HSI oscillator clock selected as PLL clock entry */
mbed_official 114:fe4fe5cfc3a3 294 SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
mbed_official 114:fe4fe5cfc3a3 295 }
mbed_official 114:fe4fe5cfc3a3 296 else
mbed_official 114:fe4fe5cfc3a3 297 {
mbed_official 114:fe4fe5cfc3a3 298 /* HSE selected as PLL clock entry */
mbed_official 114:fe4fe5cfc3a3 299 SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
mbed_official 114:fe4fe5cfc3a3 300 }
mbed_official 114:fe4fe5cfc3a3 301 break;
mbed_official 114:fe4fe5cfc3a3 302 default: /* MSI used as system clock */
<> 151:5eaa88a5bcc7 303 msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U;
<> 151:5eaa88a5bcc7 304 SystemCoreClock = (32768U * (1U << (msirange + 1U)));
mbed_official 114:fe4fe5cfc3a3 305 break;
mbed_official 114:fe4fe5cfc3a3 306 }
mbed_official 114:fe4fe5cfc3a3 307 /* Compute HCLK clock frequency --------------------------------------------*/
mbed_official 114:fe4fe5cfc3a3 308 /* Get HCLK prescaler */
<> 151:5eaa88a5bcc7 309 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
mbed_official 114:fe4fe5cfc3a3 310 /* HCLK clock frequency */
mbed_official 114:fe4fe5cfc3a3 311 SystemCoreClock >>= tmp;
mbed_official 114:fe4fe5cfc3a3 312 }
mbed_official 114:fe4fe5cfc3a3 313
mbed_official 114:fe4fe5cfc3a3 314 /**
mbed_official 114:fe4fe5cfc3a3 315 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
mbed_official 114:fe4fe5cfc3a3 316 * AHB/APBx prescalers and Flash settings
mbed_official 114:fe4fe5cfc3a3 317 * @note This function should be called only once the RCC clock configuration
mbed_official 114:fe4fe5cfc3a3 318 * is reset to the default reset state (done in SystemInit() function).
mbed_official 114:fe4fe5cfc3a3 319 * @param None
mbed_official 114:fe4fe5cfc3a3 320 * @retval None
mbed_official 114:fe4fe5cfc3a3 321 */
mbed_official 114:fe4fe5cfc3a3 322 void SetSysClock(void)
mbed_official 114:fe4fe5cfc3a3 323 {
mbed_official 114:fe4fe5cfc3a3 324 /* 1- Try to start with HSE and external clock */
mbed_official 114:fe4fe5cfc3a3 325 #if USE_PLL_HSE_EXTC != 0
mbed_official 114:fe4fe5cfc3a3 326 if (SetSysClock_PLL_HSE(1) == 0)
mbed_official 114:fe4fe5cfc3a3 327 #endif
mbed_official 114:fe4fe5cfc3a3 328 {
mbed_official 114:fe4fe5cfc3a3 329 /* 2- If fail try to start with HSE and external xtal */
mbed_official 114:fe4fe5cfc3a3 330 #if USE_PLL_HSE_XTAL != 0
mbed_official 114:fe4fe5cfc3a3 331 if (SetSysClock_PLL_HSE(0) == 0)
mbed_official 114:fe4fe5cfc3a3 332 #endif
mbed_official 114:fe4fe5cfc3a3 333 {
mbed_official 114:fe4fe5cfc3a3 334 /* 3- If fail try to start with MSI */
mbed_official 114:fe4fe5cfc3a3 335 #if USE_MSI_OSC != 0
mbed_official 114:fe4fe5cfc3a3 336 if (SetSysClock_MSI() == 0)
mbed_official 114:fe4fe5cfc3a3 337 #endif
mbed_official 114:fe4fe5cfc3a3 338 {
mbed_official 114:fe4fe5cfc3a3 339 /* 4- If fail start with HSI clock */
mbed_official 114:fe4fe5cfc3a3 340 if (SetSysClock_PLL_HSI() == 0)
mbed_official 114:fe4fe5cfc3a3 341 {
mbed_official 114:fe4fe5cfc3a3 342 while(1)
mbed_official 114:fe4fe5cfc3a3 343 {
mbed_official 114:fe4fe5cfc3a3 344 // [TODO] Put something here to tell the user that a problem occured...
mbed_official 114:fe4fe5cfc3a3 345 }
mbed_official 114:fe4fe5cfc3a3 346 }
mbed_official 114:fe4fe5cfc3a3 347 }
mbed_official 114:fe4fe5cfc3a3 348 }
mbed_official 114:fe4fe5cfc3a3 349 }
mbed_official 114:fe4fe5cfc3a3 350
mbed_official 114:fe4fe5cfc3a3 351 /* Output clock on MCO1 pin(PA8) for debugging purpose */
mbed_official 114:fe4fe5cfc3a3 352 //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
mbed_official 114:fe4fe5cfc3a3 353 //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI48, RCC_MCODIV_1);
mbed_official 114:fe4fe5cfc3a3 354 }
mbed_official 114:fe4fe5cfc3a3 355
mbed_official 114:fe4fe5cfc3a3 356 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
mbed_official 114:fe4fe5cfc3a3 357 /******************************************************************************/
mbed_official 114:fe4fe5cfc3a3 358 /* PLL (clocked by HSE) used as System clock source */
mbed_official 114:fe4fe5cfc3a3 359 /******************************************************************************/
mbed_official 114:fe4fe5cfc3a3 360 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
mbed_official 114:fe4fe5cfc3a3 361 {
mbed_official 114:fe4fe5cfc3a3 362 RCC_ClkInitTypeDef RCC_ClkInitStruct;
mbed_official 114:fe4fe5cfc3a3 363 RCC_OscInitTypeDef RCC_OscInitStruct;
mbed_official 114:fe4fe5cfc3a3 364
mbed_official 114:fe4fe5cfc3a3 365 /* Used to gain time after DeepSleep in case HSI is used */
mbed_official 114:fe4fe5cfc3a3 366 if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
mbed_official 114:fe4fe5cfc3a3 367 {
mbed_official 114:fe4fe5cfc3a3 368 return 0;
mbed_official 114:fe4fe5cfc3a3 369 }
mbed_official 114:fe4fe5cfc3a3 370
mbed_official 114:fe4fe5cfc3a3 371 /* The voltage scaling allows optimizing the power consumption when the device is
mbed_official 114:fe4fe5cfc3a3 372 clocked below the maximum system frequency, to update the voltage scaling value
mbed_official 114:fe4fe5cfc3a3 373 regarding system frequency refer to product datasheet. */
mbed_official 114:fe4fe5cfc3a3 374 __PWR_CLK_ENABLE();
mbed_official 114:fe4fe5cfc3a3 375 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
mbed_official 114:fe4fe5cfc3a3 376
mbed_official 114:fe4fe5cfc3a3 377 /* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */
mbed_official 114:fe4fe5cfc3a3 378 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
mbed_official 114:fe4fe5cfc3a3 379 if (bypass == 0)
mbed_official 114:fe4fe5cfc3a3 380 {
mbed_official 114:fe4fe5cfc3a3 381 RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
mbed_official 114:fe4fe5cfc3a3 382 }
mbed_official 114:fe4fe5cfc3a3 383 else
mbed_official 114:fe4fe5cfc3a3 384 {
mbed_official 114:fe4fe5cfc3a3 385 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
mbed_official 114:fe4fe5cfc3a3 386 }
mbed_official 114:fe4fe5cfc3a3 387 RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
mbed_official 114:fe4fe5cfc3a3 388 #if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) && \
mbed_official 114:fe4fe5cfc3a3 389 !defined (STM32L011xx) && !defined (STM32L021xx)
mbed_official 114:fe4fe5cfc3a3 390 RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; /* For USB and RNG clock */
mbed_official 114:fe4fe5cfc3a3 391 #endif
mbed_official 114:fe4fe5cfc3a3 392 // PLLCLK = (8 MHz * 8)/2 = 32 MHz
mbed_official 114:fe4fe5cfc3a3 393 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official 114:fe4fe5cfc3a3 394 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
mbed_official 114:fe4fe5cfc3a3 395 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_8;
mbed_official 114:fe4fe5cfc3a3 396 RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2;
mbed_official 114:fe4fe5cfc3a3 397 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
mbed_official 114:fe4fe5cfc3a3 398 {
mbed_official 114:fe4fe5cfc3a3 399 return 0; // FAIL
mbed_official 114:fe4fe5cfc3a3 400 }
mbed_official 114:fe4fe5cfc3a3 401
mbed_official 114:fe4fe5cfc3a3 402 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
mbed_official 114:fe4fe5cfc3a3 403 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
mbed_official 114:fe4fe5cfc3a3 404 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
mbed_official 114:fe4fe5cfc3a3 405 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 32 MHz
mbed_official 114:fe4fe5cfc3a3 406 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 32 MHz
mbed_official 114:fe4fe5cfc3a3 407 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 32 MHz
mbed_official 114:fe4fe5cfc3a3 408 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
mbed_official 114:fe4fe5cfc3a3 409 {
mbed_official 114:fe4fe5cfc3a3 410 return 0; // FAIL
mbed_official 114:fe4fe5cfc3a3 411 }
mbed_official 114:fe4fe5cfc3a3 412
mbed_official 114:fe4fe5cfc3a3 413 /* Output clock on MCO1 pin(PA8) for debugging purpose */
mbed_official 114:fe4fe5cfc3a3 414 //if (bypass == 0)
mbed_official 114:fe4fe5cfc3a3 415 // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
mbed_official 114:fe4fe5cfc3a3 416 //else
mbed_official 114:fe4fe5cfc3a3 417 // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
mbed_official 114:fe4fe5cfc3a3 418
mbed_official 114:fe4fe5cfc3a3 419 return 1; // OK
mbed_official 114:fe4fe5cfc3a3 420 }
mbed_official 114:fe4fe5cfc3a3 421 #endif
mbed_official 114:fe4fe5cfc3a3 422
mbed_official 114:fe4fe5cfc3a3 423 /******************************************************************************/
mbed_official 114:fe4fe5cfc3a3 424 /* PLL (clocked by HSI) used as System clock source */
mbed_official 114:fe4fe5cfc3a3 425 /******************************************************************************/
mbed_official 114:fe4fe5cfc3a3 426 uint8_t SetSysClock_PLL_HSI(void)
mbed_official 114:fe4fe5cfc3a3 427 {
mbed_official 114:fe4fe5cfc3a3 428 RCC_ClkInitTypeDef RCC_ClkInitStruct;
mbed_official 114:fe4fe5cfc3a3 429 RCC_OscInitTypeDef RCC_OscInitStruct;
mbed_official 114:fe4fe5cfc3a3 430
mbed_official 114:fe4fe5cfc3a3 431 /* The voltage scaling allows optimizing the power consumption when the device is
mbed_official 114:fe4fe5cfc3a3 432 clocked below the maximum system frequency, to update the voltage scaling value
mbed_official 114:fe4fe5cfc3a3 433 regarding system frequency refer to product datasheet. */
mbed_official 114:fe4fe5cfc3a3 434 __PWR_CLK_ENABLE();
mbed_official 114:fe4fe5cfc3a3 435 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
mbed_official 114:fe4fe5cfc3a3 436
mbed_official 114:fe4fe5cfc3a3 437 /* Enable HSI and HSI48 oscillators and activate PLL with HSI as source */
mbed_official 114:fe4fe5cfc3a3 438 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48;
mbed_official 114:fe4fe5cfc3a3 439 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
mbed_official 114:fe4fe5cfc3a3 440 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
mbed_official 114:fe4fe5cfc3a3 441 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
mbed_official 114:fe4fe5cfc3a3 442 #if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) && \
mbed_official 114:fe4fe5cfc3a3 443 !defined (STM32L011xx) && !defined (STM32L021xx)
mbed_official 114:fe4fe5cfc3a3 444 RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; /* For USB and RNG clock */
mbed_official 114:fe4fe5cfc3a3 445 #endif
mbed_official 114:fe4fe5cfc3a3 446 // PLLCLK = (16 MHz * 4)/2 = 32 MHz
mbed_official 114:fe4fe5cfc3a3 447 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official 114:fe4fe5cfc3a3 448 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
mbed_official 114:fe4fe5cfc3a3 449 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_4;
mbed_official 114:fe4fe5cfc3a3 450 RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2;
mbed_official 114:fe4fe5cfc3a3 451 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
mbed_official 114:fe4fe5cfc3a3 452 {
mbed_official 114:fe4fe5cfc3a3 453 return 0; // FAIL
mbed_official 114:fe4fe5cfc3a3 454 }
mbed_official 114:fe4fe5cfc3a3 455
mbed_official 114:fe4fe5cfc3a3 456 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
mbed_official 114:fe4fe5cfc3a3 457 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
mbed_official 114:fe4fe5cfc3a3 458 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
mbed_official 114:fe4fe5cfc3a3 459 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 32 MHz
mbed_official 114:fe4fe5cfc3a3 460 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 32 MHz
mbed_official 114:fe4fe5cfc3a3 461 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 32 MHz
mbed_official 114:fe4fe5cfc3a3 462 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
mbed_official 114:fe4fe5cfc3a3 463 {
mbed_official 114:fe4fe5cfc3a3 464 return 0; // FAIL
mbed_official 114:fe4fe5cfc3a3 465 }
mbed_official 114:fe4fe5cfc3a3 466
mbed_official 114:fe4fe5cfc3a3 467 /* Output clock on MCO1 pin(PA8) for debugging purpose */
mbed_official 114:fe4fe5cfc3a3 468 //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
mbed_official 114:fe4fe5cfc3a3 469
mbed_official 114:fe4fe5cfc3a3 470 return 1; // OK
mbed_official 114:fe4fe5cfc3a3 471 }
mbed_official 114:fe4fe5cfc3a3 472
mbed_official 114:fe4fe5cfc3a3 473 /******************************************************************************/
mbed_official 114:fe4fe5cfc3a3 474 /* MSI (4Mhz) used as System clock source */
mbed_official 114:fe4fe5cfc3a3 475 /******************************************************************************/
mbed_official 114:fe4fe5cfc3a3 476 uint8_t SetSysClock_MSI(void)
mbed_official 114:fe4fe5cfc3a3 477 {
mbed_official 114:fe4fe5cfc3a3 478 RCC_ClkInitTypeDef RCC_ClkInitStruct;
mbed_official 114:fe4fe5cfc3a3 479 RCC_OscInitTypeDef RCC_OscInitStruct;
mbed_official 114:fe4fe5cfc3a3 480
mbed_official 114:fe4fe5cfc3a3 481 /* Enable MSI Oscillator */
mbed_official 114:fe4fe5cfc3a3 482 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
mbed_official 114:fe4fe5cfc3a3 483 RCC_OscInitStruct.MSIState = RCC_MSI_ON;
mbed_official 114:fe4fe5cfc3a3 484 RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
mbed_official 114:fe4fe5cfc3a3 485 RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
mbed_official 114:fe4fe5cfc3a3 486 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
mbed_official 114:fe4fe5cfc3a3 487 if (HAL_RCC_OscConfig(&RCC_OscInitStruct)!= HAL_OK)
mbed_official 114:fe4fe5cfc3a3 488 {
mbed_official 114:fe4fe5cfc3a3 489 /* Initialization Error */
mbed_official 114:fe4fe5cfc3a3 490 return 0;
mbed_official 114:fe4fe5cfc3a3 491 }
mbed_official 114:fe4fe5cfc3a3 492
mbed_official 114:fe4fe5cfc3a3 493 /* Select MSI as system clock source and configure the HCLK, PCLK1 and PCLK2
mbed_official 114:fe4fe5cfc3a3 494 clocks dividers */
mbed_official 114:fe4fe5cfc3a3 495 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
mbed_official 114:fe4fe5cfc3a3 496 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI; // 4 MHz
mbed_official 114:fe4fe5cfc3a3 497 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 4 MHz
mbed_official 114:fe4fe5cfc3a3 498 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 4 MHz
mbed_official 114:fe4fe5cfc3a3 499 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 4 MHz
mbed_official 114:fe4fe5cfc3a3 500 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0)!= HAL_OK)
mbed_official 114:fe4fe5cfc3a3 501 {
mbed_official 114:fe4fe5cfc3a3 502 /* Initialization Error */
mbed_official 114:fe4fe5cfc3a3 503 return 0;
mbed_official 114:fe4fe5cfc3a3 504 }
mbed_official 114:fe4fe5cfc3a3 505
mbed_official 114:fe4fe5cfc3a3 506 /* Enable Power Control clock */
mbed_official 114:fe4fe5cfc3a3 507 __HAL_RCC_PWR_CLK_ENABLE();
mbed_official 114:fe4fe5cfc3a3 508
mbed_official 114:fe4fe5cfc3a3 509 /* The voltage scaling allows optimizing the power consumption when the device is
mbed_official 114:fe4fe5cfc3a3 510 clocked below the maximum system frequency, to update the voltage scaling value
mbed_official 114:fe4fe5cfc3a3 511 regarding system frequency refer to product datasheet. */
mbed_official 114:fe4fe5cfc3a3 512 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
mbed_official 114:fe4fe5cfc3a3 513
mbed_official 114:fe4fe5cfc3a3 514 /* Disable Power Control clock */
mbed_official 114:fe4fe5cfc3a3 515 __HAL_RCC_PWR_CLK_DISABLE();
mbed_official 114:fe4fe5cfc3a3 516
mbed_official 114:fe4fe5cfc3a3 517 /* Output clock on MCO1 pin(PA8) for debugging purpose */
mbed_official 114:fe4fe5cfc3a3 518 //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
mbed_official 114:fe4fe5cfc3a3 519
mbed_official 114:fe4fe5cfc3a3 520 return 1; // OK
mbed_official 114:fe4fe5cfc3a3 521 }
mbed_official 114:fe4fe5cfc3a3 522
mbed_official 114:fe4fe5cfc3a3 523 /**
mbed_official 114:fe4fe5cfc3a3 524 * @}
mbed_official 114:fe4fe5cfc3a3 525 */
mbed_official 114:fe4fe5cfc3a3 526
mbed_official 114:fe4fe5cfc3a3 527 /**
mbed_official 114:fe4fe5cfc3a3 528 * @}
mbed_official 114:fe4fe5cfc3a3 529 */
mbed_official 114:fe4fe5cfc3a3 530
mbed_official 114:fe4fe5cfc3a3 531 /**
mbed_official 114:fe4fe5cfc3a3 532 * @}
mbed_official 114:fe4fe5cfc3a3 533 */
mbed_official 114:fe4fe5cfc3a3 534
mbed_official 114:fe4fe5cfc3a3 535 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/