Fawwaz Nadzmy / mbed-STM

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targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/device/efm32lg_lcd.h@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_lcd.h@144:ef7eb2e8f9f7 
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 2 * @file efm32lg_lcd.h
<> 144:ef7eb2e8f9f7 3 * @brief EFM32LG_LCD register and bit field definitions
<> 144:ef7eb2e8f9f7 4 * @version 4.2.0
<> 144:ef7eb2e8f9f7 5 ******************************************************************************
<> 144:ef7eb2e8f9f7 6 * @section License
<> 144:ef7eb2e8f9f7 7 * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Permission is granted to anyone to use this software for any purpose,
<> 144:ef7eb2e8f9f7 11 * including commercial applications, and to alter it and redistribute it
<> 144:ef7eb2e8f9f7 12 * freely, subject to the following restrictions:
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * 1. The origin of this software must not be misrepresented; you must not
<> 144:ef7eb2e8f9f7 15 * claim that you wrote the original software.@n
<> 144:ef7eb2e8f9f7 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 144:ef7eb2e8f9f7 17 * misrepresented as being the original software.@n
<> 144:ef7eb2e8f9f7 18 * 3. This notice may not be removed or altered from any source distribution.
<> 144:ef7eb2e8f9f7 19 *
<> 144:ef7eb2e8f9f7 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 144:ef7eb2e8f9f7 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 144:ef7eb2e8f9f7 22 * providing the Software "AS IS", with no express or implied warranties of any
<> 144:ef7eb2e8f9f7 23 * kind, including, but not limited to, any implied warranties of
<> 144:ef7eb2e8f9f7 24 * merchantability or fitness for any particular purpose or warranties against
<> 144:ef7eb2e8f9f7 25 * infringement of any proprietary rights of a third party.
<> 144:ef7eb2e8f9f7 26 *
<> 144:ef7eb2e8f9f7 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 144:ef7eb2e8f9f7 28 * incidental, or special damages, or any other relief, or for any claim by
<> 144:ef7eb2e8f9f7 29 * any third party, arising from your use of this Software.
<> 144:ef7eb2e8f9f7 30 *
<> 144:ef7eb2e8f9f7 31 *****************************************************************************/
<> 144:ef7eb2e8f9f7 32 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 33 * @addtogroup Parts
<> 144:ef7eb2e8f9f7 34 * @{
<> 144:ef7eb2e8f9f7 35 ******************************************************************************/
<> 144:ef7eb2e8f9f7 36 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 37 * @defgroup EFM32LG_LCD
<> 144:ef7eb2e8f9f7 38 * @{
<> 144:ef7eb2e8f9f7 39 * @brief EFM32LG_LCD Register Declaration
<> 144:ef7eb2e8f9f7 40 *****************************************************************************/
<> 144:ef7eb2e8f9f7 41 typedef struct
<> 144:ef7eb2e8f9f7 42 {
<> 144:ef7eb2e8f9f7 43 __IO uint32_t CTRL; /**< Control Register */
<> 144:ef7eb2e8f9f7 44 __IO uint32_t DISPCTRL; /**< Display Control Register */
<> 144:ef7eb2e8f9f7 45 __IO uint32_t SEGEN; /**< Segment Enable Register */
<> 144:ef7eb2e8f9f7 46 __IO uint32_t BACTRL; /**< Blink and Animation Control Register */
<> 144:ef7eb2e8f9f7 47 __I uint32_t STATUS; /**< Status Register */
<> 144:ef7eb2e8f9f7 48 __IO uint32_t AREGA; /**< Animation Register A */
<> 144:ef7eb2e8f9f7 49 __IO uint32_t AREGB; /**< Animation Register B */
<> 144:ef7eb2e8f9f7 50 __I uint32_t IF; /**< Interrupt Flag Register */
<> 144:ef7eb2e8f9f7 51 __IO uint32_t IFS; /**< Interrupt Flag Set Register */
<> 144:ef7eb2e8f9f7 52 __IO uint32_t IFC; /**< Interrupt Flag Clear Register */
<> 144:ef7eb2e8f9f7 53 __IO uint32_t IEN; /**< Interrupt Enable Register */
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 uint32_t RESERVED0[5]; /**< Reserved for future use **/
<> 144:ef7eb2e8f9f7 56 __IO uint32_t SEGD0L; /**< Segment Data Low Register 0 */
<> 144:ef7eb2e8f9f7 57 __IO uint32_t SEGD1L; /**< Segment Data Low Register 1 */
<> 144:ef7eb2e8f9f7 58 __IO uint32_t SEGD2L; /**< Segment Data Low Register 2 */
<> 144:ef7eb2e8f9f7 59 __IO uint32_t SEGD3L; /**< Segment Data Low Register 3 */
<> 144:ef7eb2e8f9f7 60 __IO uint32_t SEGD0H; /**< Segment Data High Register 0 */
<> 144:ef7eb2e8f9f7 61 __IO uint32_t SEGD1H; /**< Segment Data High Register 1 */
<> 144:ef7eb2e8f9f7 62 __IO uint32_t SEGD2H; /**< Segment Data High Register 2 */
<> 144:ef7eb2e8f9f7 63 __IO uint32_t SEGD3H; /**< Segment Data High Register 3 */
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65 __IO uint32_t FREEZE; /**< Freeze Register */
<> 144:ef7eb2e8f9f7 66 __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 uint32_t RESERVED1[19]; /**< Reserved for future use **/
<> 144:ef7eb2e8f9f7 69 __IO uint32_t SEGD4H; /**< Segment Data High Register 4 */
<> 144:ef7eb2e8f9f7 70 __IO uint32_t SEGD5H; /**< Segment Data High Register 5 */
<> 144:ef7eb2e8f9f7 71 __IO uint32_t SEGD6H; /**< Segment Data High Register 6 */
<> 144:ef7eb2e8f9f7 72 __IO uint32_t SEGD7H; /**< Segment Data High Register 7 */
<> 144:ef7eb2e8f9f7 73 uint32_t RESERVED2[2]; /**< Reserved for future use **/
<> 144:ef7eb2e8f9f7 74 __IO uint32_t SEGD4L; /**< Segment Data Low Register 4 */
<> 144:ef7eb2e8f9f7 75 __IO uint32_t SEGD5L; /**< Segment Data Low Register 5 */
<> 144:ef7eb2e8f9f7 76 __IO uint32_t SEGD6L; /**< Segment Data Low Register 6 */
<> 144:ef7eb2e8f9f7 77 __IO uint32_t SEGD7L; /**< Segment Data Low Register 7 */
<> 144:ef7eb2e8f9f7 78 } LCD_TypeDef; /** @} */
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 81 * @defgroup EFM32LG_LCD_BitFields
<> 144:ef7eb2e8f9f7 82 * @{
<> 144:ef7eb2e8f9f7 83 *****************************************************************************/
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 /* Bit fields for LCD CTRL */
<> 144:ef7eb2e8f9f7 86 #define _LCD_CTRL_RESETVALUE 0x00000000UL /**< Default value for LCD_CTRL */
<> 144:ef7eb2e8f9f7 87 #define _LCD_CTRL_MASK 0x00800007UL /**< Mask for LCD_CTRL */
<> 144:ef7eb2e8f9f7 88 #define LCD_CTRL_EN (0x1UL << 0) /**< LCD Enable */
<> 144:ef7eb2e8f9f7 89 #define _LCD_CTRL_EN_SHIFT 0 /**< Shift value for LCD_EN */
<> 144:ef7eb2e8f9f7 90 #define _LCD_CTRL_EN_MASK 0x1UL /**< Bit mask for LCD_EN */
<> 144:ef7eb2e8f9f7 91 #define _LCD_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CTRL */
<> 144:ef7eb2e8f9f7 92 #define LCD_CTRL_EN_DEFAULT (_LCD_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_CTRL */
<> 144:ef7eb2e8f9f7 93 #define _LCD_CTRL_UDCTRL_SHIFT 1 /**< Shift value for LCD_UDCTRL */
<> 144:ef7eb2e8f9f7 94 #define _LCD_CTRL_UDCTRL_MASK 0x6UL /**< Bit mask for LCD_UDCTRL */
<> 144:ef7eb2e8f9f7 95 #define _LCD_CTRL_UDCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CTRL */
<> 144:ef7eb2e8f9f7 96 #define _LCD_CTRL_UDCTRL_REGULAR 0x00000000UL /**< Mode REGULAR for LCD_CTRL */
<> 144:ef7eb2e8f9f7 97 #define _LCD_CTRL_UDCTRL_FCEVENT 0x00000001UL /**< Mode FCEVENT for LCD_CTRL */
<> 144:ef7eb2e8f9f7 98 #define _LCD_CTRL_UDCTRL_FRAMESTART 0x00000002UL /**< Mode FRAMESTART for LCD_CTRL */
<> 144:ef7eb2e8f9f7 99 #define LCD_CTRL_UDCTRL_DEFAULT (_LCD_CTRL_UDCTRL_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_CTRL */
<> 144:ef7eb2e8f9f7 100 #define LCD_CTRL_UDCTRL_REGULAR (_LCD_CTRL_UDCTRL_REGULAR << 1) /**< Shifted mode REGULAR for LCD_CTRL */
<> 144:ef7eb2e8f9f7 101 #define LCD_CTRL_UDCTRL_FCEVENT (_LCD_CTRL_UDCTRL_FCEVENT << 1) /**< Shifted mode FCEVENT for LCD_CTRL */
<> 144:ef7eb2e8f9f7 102 #define LCD_CTRL_UDCTRL_FRAMESTART (_LCD_CTRL_UDCTRL_FRAMESTART << 1) /**< Shifted mode FRAMESTART for LCD_CTRL */
<> 144:ef7eb2e8f9f7 103 #define LCD_CTRL_DSC (0x1UL << 23) /**< Direct Segment Control */
<> 144:ef7eb2e8f9f7 104 #define _LCD_CTRL_DSC_SHIFT 23 /**< Shift value for LCD_DSC */
<> 144:ef7eb2e8f9f7 105 #define _LCD_CTRL_DSC_MASK 0x800000UL /**< Bit mask for LCD_DSC */
<> 144:ef7eb2e8f9f7 106 #define _LCD_CTRL_DSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CTRL */
<> 144:ef7eb2e8f9f7 107 #define LCD_CTRL_DSC_DEFAULT (_LCD_CTRL_DSC_DEFAULT << 23) /**< Shifted mode DEFAULT for LCD_CTRL */
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 /* Bit fields for LCD DISPCTRL */
<> 144:ef7eb2e8f9f7 110 #define _LCD_DISPCTRL_RESETVALUE 0x000C1F00UL /**< Default value for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 111 #define _LCD_DISPCTRL_MASK 0x005D9F1FUL /**< Mask for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 112 #define _LCD_DISPCTRL_MUX_SHIFT 0 /**< Shift value for LCD_MUX */
<> 144:ef7eb2e8f9f7 113 #define _LCD_DISPCTRL_MUX_MASK 0x3UL /**< Bit mask for LCD_MUX */
<> 144:ef7eb2e8f9f7 114 #define _LCD_DISPCTRL_MUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 115 #define _LCD_DISPCTRL_MUX_STATIC 0x00000000UL /**< Mode STATIC for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 116 #define _LCD_DISPCTRL_MUX_DUPLEX 0x00000001UL /**< Mode DUPLEX for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 117 #define _LCD_DISPCTRL_MUX_TRIPLEX 0x00000002UL /**< Mode TRIPLEX for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 118 #define _LCD_DISPCTRL_MUX_QUADRUPLEX 0x00000003UL /**< Mode QUADRUPLEX for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 119 #define LCD_DISPCTRL_MUX_DEFAULT (_LCD_DISPCTRL_MUX_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 120 #define LCD_DISPCTRL_MUX_STATIC (_LCD_DISPCTRL_MUX_STATIC << 0) /**< Shifted mode STATIC for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 121 #define LCD_DISPCTRL_MUX_DUPLEX (_LCD_DISPCTRL_MUX_DUPLEX << 0) /**< Shifted mode DUPLEX for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 122 #define LCD_DISPCTRL_MUX_TRIPLEX (_LCD_DISPCTRL_MUX_TRIPLEX << 0) /**< Shifted mode TRIPLEX for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 123 #define LCD_DISPCTRL_MUX_QUADRUPLEX (_LCD_DISPCTRL_MUX_QUADRUPLEX << 0) /**< Shifted mode QUADRUPLEX for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 124 #define _LCD_DISPCTRL_BIAS_SHIFT 2 /**< Shift value for LCD_BIAS */
<> 144:ef7eb2e8f9f7 125 #define _LCD_DISPCTRL_BIAS_MASK 0xCUL /**< Bit mask for LCD_BIAS */
<> 144:ef7eb2e8f9f7 126 #define _LCD_DISPCTRL_BIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 127 #define _LCD_DISPCTRL_BIAS_STATIC 0x00000000UL /**< Mode STATIC for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 128 #define _LCD_DISPCTRL_BIAS_ONEHALF 0x00000001UL /**< Mode ONEHALF for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 129 #define _LCD_DISPCTRL_BIAS_ONETHIRD 0x00000002UL /**< Mode ONETHIRD for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 130 #define _LCD_DISPCTRL_BIAS_ONEFOURTH 0x00000003UL /**< Mode ONEFOURTH for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 131 #define LCD_DISPCTRL_BIAS_DEFAULT (_LCD_DISPCTRL_BIAS_DEFAULT << 2) /**< Shifted mode DEFAULT for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 132 #define LCD_DISPCTRL_BIAS_STATIC (_LCD_DISPCTRL_BIAS_STATIC << 2) /**< Shifted mode STATIC for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 133 #define LCD_DISPCTRL_BIAS_ONEHALF (_LCD_DISPCTRL_BIAS_ONEHALF << 2) /**< Shifted mode ONEHALF for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 134 #define LCD_DISPCTRL_BIAS_ONETHIRD (_LCD_DISPCTRL_BIAS_ONETHIRD << 2) /**< Shifted mode ONETHIRD for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 135 #define LCD_DISPCTRL_BIAS_ONEFOURTH (_LCD_DISPCTRL_BIAS_ONEFOURTH << 2) /**< Shifted mode ONEFOURTH for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 136 #define LCD_DISPCTRL_WAVE (0x1UL << 4) /**< Waveform Selection */
<> 144:ef7eb2e8f9f7 137 #define _LCD_DISPCTRL_WAVE_SHIFT 4 /**< Shift value for LCD_WAVE */
<> 144:ef7eb2e8f9f7 138 #define _LCD_DISPCTRL_WAVE_MASK 0x10UL /**< Bit mask for LCD_WAVE */
<> 144:ef7eb2e8f9f7 139 #define _LCD_DISPCTRL_WAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 140 #define _LCD_DISPCTRL_WAVE_LOWPOWER 0x00000000UL /**< Mode LOWPOWER for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 141 #define _LCD_DISPCTRL_WAVE_NORMAL 0x00000001UL /**< Mode NORMAL for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 142 #define LCD_DISPCTRL_WAVE_DEFAULT (_LCD_DISPCTRL_WAVE_DEFAULT << 4) /**< Shifted mode DEFAULT for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 143 #define LCD_DISPCTRL_WAVE_LOWPOWER (_LCD_DISPCTRL_WAVE_LOWPOWER << 4) /**< Shifted mode LOWPOWER for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 144 #define LCD_DISPCTRL_WAVE_NORMAL (_LCD_DISPCTRL_WAVE_NORMAL << 4) /**< Shifted mode NORMAL for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 145 #define _LCD_DISPCTRL_CONLEV_SHIFT 8 /**< Shift value for LCD_CONLEV */
<> 144:ef7eb2e8f9f7 146 #define _LCD_DISPCTRL_CONLEV_MASK 0x1F00UL /**< Bit mask for LCD_CONLEV */
<> 144:ef7eb2e8f9f7 147 #define _LCD_DISPCTRL_CONLEV_MIN 0x00000000UL /**< Mode MIN for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 148 #define _LCD_DISPCTRL_CONLEV_DEFAULT 0x0000001FUL /**< Mode DEFAULT for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 149 #define _LCD_DISPCTRL_CONLEV_MAX 0x0000001FUL /**< Mode MAX for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 150 #define LCD_DISPCTRL_CONLEV_MIN (_LCD_DISPCTRL_CONLEV_MIN << 8) /**< Shifted mode MIN for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 151 #define LCD_DISPCTRL_CONLEV_DEFAULT (_LCD_DISPCTRL_CONLEV_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 152 #define LCD_DISPCTRL_CONLEV_MAX (_LCD_DISPCTRL_CONLEV_MAX << 8) /**< Shifted mode MAX for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 153 #define LCD_DISPCTRL_CONCONF (0x1UL << 15) /**< Contrast Configuration */
<> 144:ef7eb2e8f9f7 154 #define _LCD_DISPCTRL_CONCONF_SHIFT 15 /**< Shift value for LCD_CONCONF */
<> 144:ef7eb2e8f9f7 155 #define _LCD_DISPCTRL_CONCONF_MASK 0x8000UL /**< Bit mask for LCD_CONCONF */
<> 144:ef7eb2e8f9f7 156 #define _LCD_DISPCTRL_CONCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 157 #define _LCD_DISPCTRL_CONCONF_VLCD 0x00000000UL /**< Mode VLCD for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 158 #define _LCD_DISPCTRL_CONCONF_GND 0x00000001UL /**< Mode GND for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 159 #define LCD_DISPCTRL_CONCONF_DEFAULT (_LCD_DISPCTRL_CONCONF_DEFAULT << 15) /**< Shifted mode DEFAULT for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 160 #define LCD_DISPCTRL_CONCONF_VLCD (_LCD_DISPCTRL_CONCONF_VLCD << 15) /**< Shifted mode VLCD for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 161 #define LCD_DISPCTRL_CONCONF_GND (_LCD_DISPCTRL_CONCONF_GND << 15) /**< Shifted mode GND for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 162 #define LCD_DISPCTRL_VLCDSEL (0x1UL << 16) /**< VLCD Selection */
<> 144:ef7eb2e8f9f7 163 #define _LCD_DISPCTRL_VLCDSEL_SHIFT 16 /**< Shift value for LCD_VLCDSEL */
<> 144:ef7eb2e8f9f7 164 #define _LCD_DISPCTRL_VLCDSEL_MASK 0x10000UL /**< Bit mask for LCD_VLCDSEL */
<> 144:ef7eb2e8f9f7 165 #define _LCD_DISPCTRL_VLCDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 166 #define _LCD_DISPCTRL_VLCDSEL_VDD 0x00000000UL /**< Mode VDD for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 167 #define _LCD_DISPCTRL_VLCDSEL_VEXTBOOST 0x00000001UL /**< Mode VEXTBOOST for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 168 #define LCD_DISPCTRL_VLCDSEL_DEFAULT (_LCD_DISPCTRL_VLCDSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 169 #define LCD_DISPCTRL_VLCDSEL_VDD (_LCD_DISPCTRL_VLCDSEL_VDD << 16) /**< Shifted mode VDD for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 170 #define LCD_DISPCTRL_VLCDSEL_VEXTBOOST (_LCD_DISPCTRL_VLCDSEL_VEXTBOOST << 16) /**< Shifted mode VEXTBOOST for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 171 #define _LCD_DISPCTRL_VBLEV_SHIFT 18 /**< Shift value for LCD_VBLEV */
<> 144:ef7eb2e8f9f7 172 #define _LCD_DISPCTRL_VBLEV_MASK 0x1C0000UL /**< Bit mask for LCD_VBLEV */
<> 144:ef7eb2e8f9f7 173 #define _LCD_DISPCTRL_VBLEV_LEVEL0 0x00000000UL /**< Mode LEVEL0 for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 174 #define _LCD_DISPCTRL_VBLEV_LEVEL1 0x00000001UL /**< Mode LEVEL1 for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 175 #define _LCD_DISPCTRL_VBLEV_LEVEL2 0x00000002UL /**< Mode LEVEL2 for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 176 #define _LCD_DISPCTRL_VBLEV_DEFAULT 0x00000003UL /**< Mode DEFAULT for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 177 #define _LCD_DISPCTRL_VBLEV_LEVEL3 0x00000003UL /**< Mode LEVEL3 for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 178 #define _LCD_DISPCTRL_VBLEV_LEVEL4 0x00000004UL /**< Mode LEVEL4 for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 179 #define _LCD_DISPCTRL_VBLEV_LEVEL5 0x00000005UL /**< Mode LEVEL5 for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 180 #define _LCD_DISPCTRL_VBLEV_LEVEL6 0x00000006UL /**< Mode LEVEL6 for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 181 #define _LCD_DISPCTRL_VBLEV_LEVEL7 0x00000007UL /**< Mode LEVEL7 for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 182 #define LCD_DISPCTRL_VBLEV_LEVEL0 (_LCD_DISPCTRL_VBLEV_LEVEL0 << 18) /**< Shifted mode LEVEL0 for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 183 #define LCD_DISPCTRL_VBLEV_LEVEL1 (_LCD_DISPCTRL_VBLEV_LEVEL1 << 18) /**< Shifted mode LEVEL1 for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 184 #define LCD_DISPCTRL_VBLEV_LEVEL2 (_LCD_DISPCTRL_VBLEV_LEVEL2 << 18) /**< Shifted mode LEVEL2 for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 185 #define LCD_DISPCTRL_VBLEV_DEFAULT (_LCD_DISPCTRL_VBLEV_DEFAULT << 18) /**< Shifted mode DEFAULT for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 186 #define LCD_DISPCTRL_VBLEV_LEVEL3 (_LCD_DISPCTRL_VBLEV_LEVEL3 << 18) /**< Shifted mode LEVEL3 for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 187 #define LCD_DISPCTRL_VBLEV_LEVEL4 (_LCD_DISPCTRL_VBLEV_LEVEL4 << 18) /**< Shifted mode LEVEL4 for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 188 #define LCD_DISPCTRL_VBLEV_LEVEL5 (_LCD_DISPCTRL_VBLEV_LEVEL5 << 18) /**< Shifted mode LEVEL5 for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 189 #define LCD_DISPCTRL_VBLEV_LEVEL6 (_LCD_DISPCTRL_VBLEV_LEVEL6 << 18) /**< Shifted mode LEVEL6 for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 190 #define LCD_DISPCTRL_VBLEV_LEVEL7 (_LCD_DISPCTRL_VBLEV_LEVEL7 << 18) /**< Shifted mode LEVEL7 for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 191 #define LCD_DISPCTRL_MUXE (0x1UL << 22) /**< Extended Mux Configuration */
<> 144:ef7eb2e8f9f7 192 #define _LCD_DISPCTRL_MUXE_SHIFT 22 /**< Shift value for LCD_MUXE */
<> 144:ef7eb2e8f9f7 193 #define _LCD_DISPCTRL_MUXE_MASK 0x400000UL /**< Bit mask for LCD_MUXE */
<> 144:ef7eb2e8f9f7 194 #define _LCD_DISPCTRL_MUXE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 195 #define _LCD_DISPCTRL_MUXE_MUX 0x00000000UL /**< Mode MUX for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 196 #define _LCD_DISPCTRL_MUXE_MUXE 0x00000001UL /**< Mode MUXE for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 197 #define LCD_DISPCTRL_MUXE_DEFAULT (_LCD_DISPCTRL_MUXE_DEFAULT << 22) /**< Shifted mode DEFAULT for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 198 #define LCD_DISPCTRL_MUXE_MUX (_LCD_DISPCTRL_MUXE_MUX << 22) /**< Shifted mode MUX for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 199 #define LCD_DISPCTRL_MUXE_MUXE (_LCD_DISPCTRL_MUXE_MUXE << 22) /**< Shifted mode MUXE for LCD_DISPCTRL */
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 /* Bit fields for LCD SEGEN */
<> 144:ef7eb2e8f9f7 202 #define _LCD_SEGEN_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGEN */
<> 144:ef7eb2e8f9f7 203 #define _LCD_SEGEN_MASK 0x000003FFUL /**< Mask for LCD_SEGEN */
<> 144:ef7eb2e8f9f7 204 #define _LCD_SEGEN_SEGEN_SHIFT 0 /**< Shift value for LCD_SEGEN */
<> 144:ef7eb2e8f9f7 205 #define _LCD_SEGEN_SEGEN_MASK 0x3FFUL /**< Bit mask for LCD_SEGEN */
<> 144:ef7eb2e8f9f7 206 #define _LCD_SEGEN_SEGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGEN */
<> 144:ef7eb2e8f9f7 207 #define LCD_SEGEN_SEGEN_DEFAULT (_LCD_SEGEN_SEGEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGEN */
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 /* Bit fields for LCD BACTRL */
<> 144:ef7eb2e8f9f7 210 #define _LCD_BACTRL_RESETVALUE 0x00000000UL /**< Default value for LCD_BACTRL */
<> 144:ef7eb2e8f9f7 211 #define _LCD_BACTRL_MASK 0x10FF01FFUL /**< Mask for LCD_BACTRL */
<> 144:ef7eb2e8f9f7 212 #define LCD_BACTRL_BLINKEN (0x1UL << 0) /**< Blink Enable */
<> 144:ef7eb2e8f9f7 213 #define _LCD_BACTRL_BLINKEN_SHIFT 0 /**< Shift value for LCD_BLINKEN */
<> 144:ef7eb2e8f9f7 214 #define _LCD_BACTRL_BLINKEN_MASK 0x1UL /**< Bit mask for LCD_BLINKEN */
<> 144:ef7eb2e8f9f7 215 #define _LCD_BACTRL_BLINKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
<> 144:ef7eb2e8f9f7 216 #define LCD_BACTRL_BLINKEN_DEFAULT (_LCD_BACTRL_BLINKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_BACTRL */
<> 144:ef7eb2e8f9f7 217 #define LCD_BACTRL_BLANK (0x1UL << 1) /**< Blank Display */
<> 144:ef7eb2e8f9f7 218 #define _LCD_BACTRL_BLANK_SHIFT 1 /**< Shift value for LCD_BLANK */
<> 144:ef7eb2e8f9f7 219 #define _LCD_BACTRL_BLANK_MASK 0x2UL /**< Bit mask for LCD_BLANK */
<> 144:ef7eb2e8f9f7 220 #define _LCD_BACTRL_BLANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
<> 144:ef7eb2e8f9f7 221 #define LCD_BACTRL_BLANK_DEFAULT (_LCD_BACTRL_BLANK_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_BACTRL */
<> 144:ef7eb2e8f9f7 222 #define LCD_BACTRL_AEN (0x1UL << 2) /**< Animation Enable */
<> 144:ef7eb2e8f9f7 223 #define _LCD_BACTRL_AEN_SHIFT 2 /**< Shift value for LCD_AEN */
<> 144:ef7eb2e8f9f7 224 #define _LCD_BACTRL_AEN_MASK 0x4UL /**< Bit mask for LCD_AEN */
<> 144:ef7eb2e8f9f7 225 #define _LCD_BACTRL_AEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
<> 144:ef7eb2e8f9f7 226 #define LCD_BACTRL_AEN_DEFAULT (_LCD_BACTRL_AEN_DEFAULT << 2) /**< Shifted mode DEFAULT for LCD_BACTRL */
<> 144:ef7eb2e8f9f7 227 #define _LCD_BACTRL_AREGASC_SHIFT 3 /**< Shift value for LCD_AREGASC */
<> 144:ef7eb2e8f9f7 228 #define _LCD_BACTRL_AREGASC_MASK 0x18UL /**< Bit mask for LCD_AREGASC */
<> 144:ef7eb2e8f9f7 229 #define _LCD_BACTRL_AREGASC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
<> 144:ef7eb2e8f9f7 230 #define _LCD_BACTRL_AREGASC_NOSHIFT 0x00000000UL /**< Mode NOSHIFT for LCD_BACTRL */
<> 144:ef7eb2e8f9f7 231 #define _LCD_BACTRL_AREGASC_SHIFTLEFT 0x00000001UL /**< Mode SHIFTLEFT for LCD_BACTRL */
<> 144:ef7eb2e8f9f7 232 #define _LCD_BACTRL_AREGASC_SHIFTRIGHT 0x00000002UL /**< Mode SHIFTRIGHT for LCD_BACTRL */
<> 144:ef7eb2e8f9f7 233 #define LCD_BACTRL_AREGASC_DEFAULT (_LCD_BACTRL_AREGASC_DEFAULT << 3) /**< Shifted mode DEFAULT for LCD_BACTRL */
<> 144:ef7eb2e8f9f7 234 #define LCD_BACTRL_AREGASC_NOSHIFT (_LCD_BACTRL_AREGASC_NOSHIFT << 3) /**< Shifted mode NOSHIFT for LCD_BACTRL */
<> 144:ef7eb2e8f9f7 235 #define LCD_BACTRL_AREGASC_SHIFTLEFT (_LCD_BACTRL_AREGASC_SHIFTLEFT << 3) /**< Shifted mode SHIFTLEFT for LCD_BACTRL */
<> 144:ef7eb2e8f9f7 236 #define LCD_BACTRL_AREGASC_SHIFTRIGHT (_LCD_BACTRL_AREGASC_SHIFTRIGHT << 3) /**< Shifted mode SHIFTRIGHT for LCD_BACTRL */
<> 144:ef7eb2e8f9f7 237 #define _LCD_BACTRL_AREGBSC_SHIFT 5 /**< Shift value for LCD_AREGBSC */
<> 144:ef7eb2e8f9f7 238 #define _LCD_BACTRL_AREGBSC_MASK 0x60UL /**< Bit mask for LCD_AREGBSC */
<> 144:ef7eb2e8f9f7 239 #define _LCD_BACTRL_AREGBSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
<> 144:ef7eb2e8f9f7 240 #define _LCD_BACTRL_AREGBSC_NOSHIFT 0x00000000UL /**< Mode NOSHIFT for LCD_BACTRL */
<> 144:ef7eb2e8f9f7 241 #define _LCD_BACTRL_AREGBSC_SHIFTLEFT 0x00000001UL /**< Mode SHIFTLEFT for LCD_BACTRL */
<> 144:ef7eb2e8f9f7 242 #define _LCD_BACTRL_AREGBSC_SHIFTRIGHT 0x00000002UL /**< Mode SHIFTRIGHT for LCD_BACTRL */
<> 144:ef7eb2e8f9f7 243 #define LCD_BACTRL_AREGBSC_DEFAULT (_LCD_BACTRL_AREGBSC_DEFAULT << 5) /**< Shifted mode DEFAULT for LCD_BACTRL */
<> 144:ef7eb2e8f9f7 244 #define LCD_BACTRL_AREGBSC_NOSHIFT (_LCD_BACTRL_AREGBSC_NOSHIFT << 5) /**< Shifted mode NOSHIFT for LCD_BACTRL */
<> 144:ef7eb2e8f9f7 245 #define LCD_BACTRL_AREGBSC_SHIFTLEFT (_LCD_BACTRL_AREGBSC_SHIFTLEFT << 5) /**< Shifted mode SHIFTLEFT for LCD_BACTRL */
<> 144:ef7eb2e8f9f7 246 #define LCD_BACTRL_AREGBSC_SHIFTRIGHT (_LCD_BACTRL_AREGBSC_SHIFTRIGHT << 5) /**< Shifted mode SHIFTRIGHT for LCD_BACTRL */
<> 144:ef7eb2e8f9f7 247 #define LCD_BACTRL_ALOGSEL (0x1UL << 7) /**< Animate Logic Function Select */
<> 144:ef7eb2e8f9f7 248 #define _LCD_BACTRL_ALOGSEL_SHIFT 7 /**< Shift value for LCD_ALOGSEL */
<> 144:ef7eb2e8f9f7 249 #define _LCD_BACTRL_ALOGSEL_MASK 0x80UL /**< Bit mask for LCD_ALOGSEL */
<> 144:ef7eb2e8f9f7 250 #define _LCD_BACTRL_ALOGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
<> 144:ef7eb2e8f9f7 251 #define _LCD_BACTRL_ALOGSEL_AND 0x00000000UL /**< Mode AND for LCD_BACTRL */
<> 144:ef7eb2e8f9f7 252 #define _LCD_BACTRL_ALOGSEL_OR 0x00000001UL /**< Mode OR for LCD_BACTRL */
<> 144:ef7eb2e8f9f7 253 #define LCD_BACTRL_ALOGSEL_DEFAULT (_LCD_BACTRL_ALOGSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for LCD_BACTRL */
<> 144:ef7eb2e8f9f7 254 #define LCD_BACTRL_ALOGSEL_AND (_LCD_BACTRL_ALOGSEL_AND << 7) /**< Shifted mode AND for LCD_BACTRL */
<> 144:ef7eb2e8f9f7 255 #define LCD_BACTRL_ALOGSEL_OR (_LCD_BACTRL_ALOGSEL_OR << 7) /**< Shifted mode OR for LCD_BACTRL */
<> 144:ef7eb2e8f9f7 256 #define LCD_BACTRL_FCEN (0x1UL << 8) /**< Frame Counter Enable */
<> 144:ef7eb2e8f9f7 257 #define _LCD_BACTRL_FCEN_SHIFT 8 /**< Shift value for LCD_FCEN */
<> 144:ef7eb2e8f9f7 258 #define _LCD_BACTRL_FCEN_MASK 0x100UL /**< Bit mask for LCD_FCEN */
<> 144:ef7eb2e8f9f7 259 #define _LCD_BACTRL_FCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
<> 144:ef7eb2e8f9f7 260 #define LCD_BACTRL_FCEN_DEFAULT (_LCD_BACTRL_FCEN_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_BACTRL */
<> 144:ef7eb2e8f9f7 261 #define _LCD_BACTRL_FCPRESC_SHIFT 16 /**< Shift value for LCD_FCPRESC */
<> 144:ef7eb2e8f9f7 262 #define _LCD_BACTRL_FCPRESC_MASK 0x30000UL /**< Bit mask for LCD_FCPRESC */
<> 144:ef7eb2e8f9f7 263 #define _LCD_BACTRL_FCPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
<> 144:ef7eb2e8f9f7 264 #define _LCD_BACTRL_FCPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LCD_BACTRL */
<> 144:ef7eb2e8f9f7 265 #define _LCD_BACTRL_FCPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LCD_BACTRL */
<> 144:ef7eb2e8f9f7 266 #define _LCD_BACTRL_FCPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LCD_BACTRL */
<> 144:ef7eb2e8f9f7 267 #define _LCD_BACTRL_FCPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LCD_BACTRL */
<> 144:ef7eb2e8f9f7 268 #define LCD_BACTRL_FCPRESC_DEFAULT (_LCD_BACTRL_FCPRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for LCD_BACTRL */
<> 144:ef7eb2e8f9f7 269 #define LCD_BACTRL_FCPRESC_DIV1 (_LCD_BACTRL_FCPRESC_DIV1 << 16) /**< Shifted mode DIV1 for LCD_BACTRL */
<> 144:ef7eb2e8f9f7 270 #define LCD_BACTRL_FCPRESC_DIV2 (_LCD_BACTRL_FCPRESC_DIV2 << 16) /**< Shifted mode DIV2 for LCD_BACTRL */
<> 144:ef7eb2e8f9f7 271 #define LCD_BACTRL_FCPRESC_DIV4 (_LCD_BACTRL_FCPRESC_DIV4 << 16) /**< Shifted mode DIV4 for LCD_BACTRL */
<> 144:ef7eb2e8f9f7 272 #define LCD_BACTRL_FCPRESC_DIV8 (_LCD_BACTRL_FCPRESC_DIV8 << 16) /**< Shifted mode DIV8 for LCD_BACTRL */
<> 144:ef7eb2e8f9f7 273 #define _LCD_BACTRL_FCTOP_SHIFT 18 /**< Shift value for LCD_FCTOP */
<> 144:ef7eb2e8f9f7 274 #define _LCD_BACTRL_FCTOP_MASK 0xFC0000UL /**< Bit mask for LCD_FCTOP */
<> 144:ef7eb2e8f9f7 275 #define _LCD_BACTRL_FCTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
<> 144:ef7eb2e8f9f7 276 #define LCD_BACTRL_FCTOP_DEFAULT (_LCD_BACTRL_FCTOP_DEFAULT << 18) /**< Shifted mode DEFAULT for LCD_BACTRL */
<> 144:ef7eb2e8f9f7 277 #define LCD_BACTRL_ALOC (0x1UL << 28) /**< Animation Location */
<> 144:ef7eb2e8f9f7 278 #define _LCD_BACTRL_ALOC_SHIFT 28 /**< Shift value for LCD_ALOC */
<> 144:ef7eb2e8f9f7 279 #define _LCD_BACTRL_ALOC_MASK 0x10000000UL /**< Bit mask for LCD_ALOC */
<> 144:ef7eb2e8f9f7 280 #define _LCD_BACTRL_ALOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
<> 144:ef7eb2e8f9f7 281 #define _LCD_BACTRL_ALOC_SEG0TO7 0x00000000UL /**< Mode SEG0TO7 for LCD_BACTRL */
<> 144:ef7eb2e8f9f7 282 #define _LCD_BACTRL_ALOC_SEG8TO15 0x00000001UL /**< Mode SEG8TO15 for LCD_BACTRL */
<> 144:ef7eb2e8f9f7 283 #define LCD_BACTRL_ALOC_DEFAULT (_LCD_BACTRL_ALOC_DEFAULT << 28) /**< Shifted mode DEFAULT for LCD_BACTRL */
<> 144:ef7eb2e8f9f7 284 #define LCD_BACTRL_ALOC_SEG0TO7 (_LCD_BACTRL_ALOC_SEG0TO7 << 28) /**< Shifted mode SEG0TO7 for LCD_BACTRL */
<> 144:ef7eb2e8f9f7 285 #define LCD_BACTRL_ALOC_SEG8TO15 (_LCD_BACTRL_ALOC_SEG8TO15 << 28) /**< Shifted mode SEG8TO15 for LCD_BACTRL */
<> 144:ef7eb2e8f9f7 286
<> 144:ef7eb2e8f9f7 287 /* Bit fields for LCD STATUS */
<> 144:ef7eb2e8f9f7 288 #define _LCD_STATUS_RESETVALUE 0x00000000UL /**< Default value for LCD_STATUS */
<> 144:ef7eb2e8f9f7 289 #define _LCD_STATUS_MASK 0x0000010FUL /**< Mask for LCD_STATUS */
<> 144:ef7eb2e8f9f7 290 #define _LCD_STATUS_ASTATE_SHIFT 0 /**< Shift value for LCD_ASTATE */
<> 144:ef7eb2e8f9f7 291 #define _LCD_STATUS_ASTATE_MASK 0xFUL /**< Bit mask for LCD_ASTATE */
<> 144:ef7eb2e8f9f7 292 #define _LCD_STATUS_ASTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_STATUS */
<> 144:ef7eb2e8f9f7 293 #define LCD_STATUS_ASTATE_DEFAULT (_LCD_STATUS_ASTATE_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_STATUS */
<> 144:ef7eb2e8f9f7 294 #define LCD_STATUS_BLINK (0x1UL << 8) /**< Blink State */
<> 144:ef7eb2e8f9f7 295 #define _LCD_STATUS_BLINK_SHIFT 8 /**< Shift value for LCD_BLINK */
<> 144:ef7eb2e8f9f7 296 #define _LCD_STATUS_BLINK_MASK 0x100UL /**< Bit mask for LCD_BLINK */
<> 144:ef7eb2e8f9f7 297 #define _LCD_STATUS_BLINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_STATUS */
<> 144:ef7eb2e8f9f7 298 #define LCD_STATUS_BLINK_DEFAULT (_LCD_STATUS_BLINK_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_STATUS */
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300 /* Bit fields for LCD AREGA */
<> 144:ef7eb2e8f9f7 301 #define _LCD_AREGA_RESETVALUE 0x00000000UL /**< Default value for LCD_AREGA */
<> 144:ef7eb2e8f9f7 302 #define _LCD_AREGA_MASK 0x000000FFUL /**< Mask for LCD_AREGA */
<> 144:ef7eb2e8f9f7 303 #define _LCD_AREGA_AREGA_SHIFT 0 /**< Shift value for LCD_AREGA */
<> 144:ef7eb2e8f9f7 304 #define _LCD_AREGA_AREGA_MASK 0xFFUL /**< Bit mask for LCD_AREGA */
<> 144:ef7eb2e8f9f7 305 #define _LCD_AREGA_AREGA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_AREGA */
<> 144:ef7eb2e8f9f7 306 #define LCD_AREGA_AREGA_DEFAULT (_LCD_AREGA_AREGA_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_AREGA */
<> 144:ef7eb2e8f9f7 307
<> 144:ef7eb2e8f9f7 308 /* Bit fields for LCD AREGB */
<> 144:ef7eb2e8f9f7 309 #define _LCD_AREGB_RESETVALUE 0x00000000UL /**< Default value for LCD_AREGB */
<> 144:ef7eb2e8f9f7 310 #define _LCD_AREGB_MASK 0x000000FFUL /**< Mask for LCD_AREGB */
<> 144:ef7eb2e8f9f7 311 #define _LCD_AREGB_AREGB_SHIFT 0 /**< Shift value for LCD_AREGB */
<> 144:ef7eb2e8f9f7 312 #define _LCD_AREGB_AREGB_MASK 0xFFUL /**< Bit mask for LCD_AREGB */
<> 144:ef7eb2e8f9f7 313 #define _LCD_AREGB_AREGB_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_AREGB */
<> 144:ef7eb2e8f9f7 314 #define LCD_AREGB_AREGB_DEFAULT (_LCD_AREGB_AREGB_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_AREGB */
<> 144:ef7eb2e8f9f7 315
<> 144:ef7eb2e8f9f7 316 /* Bit fields for LCD IF */
<> 144:ef7eb2e8f9f7 317 #define _LCD_IF_RESETVALUE 0x00000000UL /**< Default value for LCD_IF */
<> 144:ef7eb2e8f9f7 318 #define _LCD_IF_MASK 0x00000001UL /**< Mask for LCD_IF */
<> 144:ef7eb2e8f9f7 319 #define LCD_IF_FC (0x1UL << 0) /**< Frame Counter Interrupt Flag */
<> 144:ef7eb2e8f9f7 320 #define _LCD_IF_FC_SHIFT 0 /**< Shift value for LCD_FC */
<> 144:ef7eb2e8f9f7 321 #define _LCD_IF_FC_MASK 0x1UL /**< Bit mask for LCD_FC */
<> 144:ef7eb2e8f9f7 322 #define _LCD_IF_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IF */
<> 144:ef7eb2e8f9f7 323 #define LCD_IF_FC_DEFAULT (_LCD_IF_FC_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IF */
<> 144:ef7eb2e8f9f7 324
<> 144:ef7eb2e8f9f7 325 /* Bit fields for LCD IFS */
<> 144:ef7eb2e8f9f7 326 #define _LCD_IFS_RESETVALUE 0x00000000UL /**< Default value for LCD_IFS */
<> 144:ef7eb2e8f9f7 327 #define _LCD_IFS_MASK 0x00000001UL /**< Mask for LCD_IFS */
<> 144:ef7eb2e8f9f7 328 #define LCD_IFS_FC (0x1UL << 0) /**< Frame Counter Interrupt Flag Set */
<> 144:ef7eb2e8f9f7 329 #define _LCD_IFS_FC_SHIFT 0 /**< Shift value for LCD_FC */
<> 144:ef7eb2e8f9f7 330 #define _LCD_IFS_FC_MASK 0x1UL /**< Bit mask for LCD_FC */
<> 144:ef7eb2e8f9f7 331 #define _LCD_IFS_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IFS */
<> 144:ef7eb2e8f9f7 332 #define LCD_IFS_FC_DEFAULT (_LCD_IFS_FC_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IFS */
<> 144:ef7eb2e8f9f7 333
<> 144:ef7eb2e8f9f7 334 /* Bit fields for LCD IFC */
<> 144:ef7eb2e8f9f7 335 #define _LCD_IFC_RESETVALUE 0x00000000UL /**< Default value for LCD_IFC */
<> 144:ef7eb2e8f9f7 336 #define _LCD_IFC_MASK 0x00000001UL /**< Mask for LCD_IFC */
<> 144:ef7eb2e8f9f7 337 #define LCD_IFC_FC (0x1UL << 0) /**< Frame Counter Interrupt Flag Clear */
<> 144:ef7eb2e8f9f7 338 #define _LCD_IFC_FC_SHIFT 0 /**< Shift value for LCD_FC */
<> 144:ef7eb2e8f9f7 339 #define _LCD_IFC_FC_MASK 0x1UL /**< Bit mask for LCD_FC */
<> 144:ef7eb2e8f9f7 340 #define _LCD_IFC_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IFC */
<> 144:ef7eb2e8f9f7 341 #define LCD_IFC_FC_DEFAULT (_LCD_IFC_FC_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IFC */
<> 144:ef7eb2e8f9f7 342
<> 144:ef7eb2e8f9f7 343 /* Bit fields for LCD IEN */
<> 144:ef7eb2e8f9f7 344 #define _LCD_IEN_RESETVALUE 0x00000000UL /**< Default value for LCD_IEN */
<> 144:ef7eb2e8f9f7 345 #define _LCD_IEN_MASK 0x00000001UL /**< Mask for LCD_IEN */
<> 144:ef7eb2e8f9f7 346 #define LCD_IEN_FC (0x1UL << 0) /**< Frame Counter Interrupt Enable */
<> 144:ef7eb2e8f9f7 347 #define _LCD_IEN_FC_SHIFT 0 /**< Shift value for LCD_FC */
<> 144:ef7eb2e8f9f7 348 #define _LCD_IEN_FC_MASK 0x1UL /**< Bit mask for LCD_FC */
<> 144:ef7eb2e8f9f7 349 #define _LCD_IEN_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IEN */
<> 144:ef7eb2e8f9f7 350 #define LCD_IEN_FC_DEFAULT (_LCD_IEN_FC_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IEN */
<> 144:ef7eb2e8f9f7 351
<> 144:ef7eb2e8f9f7 352 /* Bit fields for LCD SEGD0L */
<> 144:ef7eb2e8f9f7 353 #define _LCD_SEGD0L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD0L */
<> 144:ef7eb2e8f9f7 354 #define _LCD_SEGD0L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD0L */
<> 144:ef7eb2e8f9f7 355 #define _LCD_SEGD0L_SEGD0L_SHIFT 0 /**< Shift value for LCD_SEGD0L */
<> 144:ef7eb2e8f9f7 356 #define _LCD_SEGD0L_SEGD0L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD0L */
<> 144:ef7eb2e8f9f7 357 #define _LCD_SEGD0L_SEGD0L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD0L */
<> 144:ef7eb2e8f9f7 358 #define LCD_SEGD0L_SEGD0L_DEFAULT (_LCD_SEGD0L_SEGD0L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD0L */
<> 144:ef7eb2e8f9f7 359
<> 144:ef7eb2e8f9f7 360 /* Bit fields for LCD SEGD1L */
<> 144:ef7eb2e8f9f7 361 #define _LCD_SEGD1L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD1L */
<> 144:ef7eb2e8f9f7 362 #define _LCD_SEGD1L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD1L */
<> 144:ef7eb2e8f9f7 363 #define _LCD_SEGD1L_SEGD1L_SHIFT 0 /**< Shift value for LCD_SEGD1L */
<> 144:ef7eb2e8f9f7 364 #define _LCD_SEGD1L_SEGD1L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD1L */
<> 144:ef7eb2e8f9f7 365 #define _LCD_SEGD1L_SEGD1L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD1L */
<> 144:ef7eb2e8f9f7 366 #define LCD_SEGD1L_SEGD1L_DEFAULT (_LCD_SEGD1L_SEGD1L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD1L */
<> 144:ef7eb2e8f9f7 367
<> 144:ef7eb2e8f9f7 368 /* Bit fields for LCD SEGD2L */
<> 144:ef7eb2e8f9f7 369 #define _LCD_SEGD2L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD2L */
<> 144:ef7eb2e8f9f7 370 #define _LCD_SEGD2L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD2L */
<> 144:ef7eb2e8f9f7 371 #define _LCD_SEGD2L_SEGD2L_SHIFT 0 /**< Shift value for LCD_SEGD2L */
<> 144:ef7eb2e8f9f7 372 #define _LCD_SEGD2L_SEGD2L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD2L */
<> 144:ef7eb2e8f9f7 373 #define _LCD_SEGD2L_SEGD2L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD2L */
<> 144:ef7eb2e8f9f7 374 #define LCD_SEGD2L_SEGD2L_DEFAULT (_LCD_SEGD2L_SEGD2L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD2L */
<> 144:ef7eb2e8f9f7 375
<> 144:ef7eb2e8f9f7 376 /* Bit fields for LCD SEGD3L */
<> 144:ef7eb2e8f9f7 377 #define _LCD_SEGD3L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD3L */
<> 144:ef7eb2e8f9f7 378 #define _LCD_SEGD3L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD3L */
<> 144:ef7eb2e8f9f7 379 #define _LCD_SEGD3L_SEGD3L_SHIFT 0 /**< Shift value for LCD_SEGD3L */
<> 144:ef7eb2e8f9f7 380 #define _LCD_SEGD3L_SEGD3L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD3L */
<> 144:ef7eb2e8f9f7 381 #define _LCD_SEGD3L_SEGD3L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD3L */
<> 144:ef7eb2e8f9f7 382 #define LCD_SEGD3L_SEGD3L_DEFAULT (_LCD_SEGD3L_SEGD3L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD3L */
<> 144:ef7eb2e8f9f7 383
<> 144:ef7eb2e8f9f7 384 /* Bit fields for LCD SEGD0H */
<> 144:ef7eb2e8f9f7 385 #define _LCD_SEGD0H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD0H */
<> 144:ef7eb2e8f9f7 386 #define _LCD_SEGD0H_MASK 0x000000FFUL /**< Mask for LCD_SEGD0H */
<> 144:ef7eb2e8f9f7 387 #define _LCD_SEGD0H_SEGD0H_SHIFT 0 /**< Shift value for LCD_SEGD0H */
<> 144:ef7eb2e8f9f7 388 #define _LCD_SEGD0H_SEGD0H_MASK 0xFFUL /**< Bit mask for LCD_SEGD0H */
<> 144:ef7eb2e8f9f7 389 #define _LCD_SEGD0H_SEGD0H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD0H */
<> 144:ef7eb2e8f9f7 390 #define LCD_SEGD0H_SEGD0H_DEFAULT (_LCD_SEGD0H_SEGD0H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD0H */
<> 144:ef7eb2e8f9f7 391
<> 144:ef7eb2e8f9f7 392 /* Bit fields for LCD SEGD1H */
<> 144:ef7eb2e8f9f7 393 #define _LCD_SEGD1H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD1H */
<> 144:ef7eb2e8f9f7 394 #define _LCD_SEGD1H_MASK 0x000000FFUL /**< Mask for LCD_SEGD1H */
<> 144:ef7eb2e8f9f7 395 #define _LCD_SEGD1H_SEGD1H_SHIFT 0 /**< Shift value for LCD_SEGD1H */
<> 144:ef7eb2e8f9f7 396 #define _LCD_SEGD1H_SEGD1H_MASK 0xFFUL /**< Bit mask for LCD_SEGD1H */
<> 144:ef7eb2e8f9f7 397 #define _LCD_SEGD1H_SEGD1H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD1H */
<> 144:ef7eb2e8f9f7 398 #define LCD_SEGD1H_SEGD1H_DEFAULT (_LCD_SEGD1H_SEGD1H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD1H */
<> 144:ef7eb2e8f9f7 399
<> 144:ef7eb2e8f9f7 400 /* Bit fields for LCD SEGD2H */
<> 144:ef7eb2e8f9f7 401 #define _LCD_SEGD2H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD2H */
<> 144:ef7eb2e8f9f7 402 #define _LCD_SEGD2H_MASK 0x000000FFUL /**< Mask for LCD_SEGD2H */
<> 144:ef7eb2e8f9f7 403 #define _LCD_SEGD2H_SEGD2H_SHIFT 0 /**< Shift value for LCD_SEGD2H */
<> 144:ef7eb2e8f9f7 404 #define _LCD_SEGD2H_SEGD2H_MASK 0xFFUL /**< Bit mask for LCD_SEGD2H */
<> 144:ef7eb2e8f9f7 405 #define _LCD_SEGD2H_SEGD2H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD2H */
<> 144:ef7eb2e8f9f7 406 #define LCD_SEGD2H_SEGD2H_DEFAULT (_LCD_SEGD2H_SEGD2H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD2H */
<> 144:ef7eb2e8f9f7 407
<> 144:ef7eb2e8f9f7 408 /* Bit fields for LCD SEGD3H */
<> 144:ef7eb2e8f9f7 409 #define _LCD_SEGD3H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD3H */
<> 144:ef7eb2e8f9f7 410 #define _LCD_SEGD3H_MASK 0x000000FFUL /**< Mask for LCD_SEGD3H */
<> 144:ef7eb2e8f9f7 411 #define _LCD_SEGD3H_SEGD3H_SHIFT 0 /**< Shift value for LCD_SEGD3H */
<> 144:ef7eb2e8f9f7 412 #define _LCD_SEGD3H_SEGD3H_MASK 0xFFUL /**< Bit mask for LCD_SEGD3H */
<> 144:ef7eb2e8f9f7 413 #define _LCD_SEGD3H_SEGD3H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD3H */
<> 144:ef7eb2e8f9f7 414 #define LCD_SEGD3H_SEGD3H_DEFAULT (_LCD_SEGD3H_SEGD3H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD3H */
<> 144:ef7eb2e8f9f7 415
<> 144:ef7eb2e8f9f7 416 /* Bit fields for LCD FREEZE */
<> 144:ef7eb2e8f9f7 417 #define _LCD_FREEZE_RESETVALUE 0x00000000UL /**< Default value for LCD_FREEZE */
<> 144:ef7eb2e8f9f7 418 #define _LCD_FREEZE_MASK 0x00000001UL /**< Mask for LCD_FREEZE */
<> 144:ef7eb2e8f9f7 419 #define LCD_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */
<> 144:ef7eb2e8f9f7 420 #define _LCD_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for LCD_REGFREEZE */
<> 144:ef7eb2e8f9f7 421 #define _LCD_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for LCD_REGFREEZE */
<> 144:ef7eb2e8f9f7 422 #define _LCD_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_FREEZE */
<> 144:ef7eb2e8f9f7 423 #define _LCD_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for LCD_FREEZE */
<> 144:ef7eb2e8f9f7 424 #define _LCD_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for LCD_FREEZE */
<> 144:ef7eb2e8f9f7 425 #define LCD_FREEZE_REGFREEZE_DEFAULT (_LCD_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_FREEZE */
<> 144:ef7eb2e8f9f7 426 #define LCD_FREEZE_REGFREEZE_UPDATE (_LCD_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for LCD_FREEZE */
<> 144:ef7eb2e8f9f7 427 #define LCD_FREEZE_REGFREEZE_FREEZE (_LCD_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for LCD_FREEZE */
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429 /* Bit fields for LCD SYNCBUSY */
<> 144:ef7eb2e8f9f7 430 #define _LCD_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LCD_SYNCBUSY */
<> 144:ef7eb2e8f9f7 431 #define _LCD_SYNCBUSY_MASK 0x000FFFFFUL /**< Mask for LCD_SYNCBUSY */
<> 144:ef7eb2e8f9f7 432 #define LCD_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */
<> 144:ef7eb2e8f9f7 433 #define _LCD_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for LCD_CTRL */
<> 144:ef7eb2e8f9f7 434 #define _LCD_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for LCD_CTRL */
<> 144:ef7eb2e8f9f7 435 #define _LCD_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
<> 144:ef7eb2e8f9f7 436 #define LCD_SYNCBUSY_CTRL_DEFAULT (_LCD_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
<> 144:ef7eb2e8f9f7 437 #define LCD_SYNCBUSY_BACTRL (0x1UL << 1) /**< BACTRL Register Busy */
<> 144:ef7eb2e8f9f7 438 #define _LCD_SYNCBUSY_BACTRL_SHIFT 1 /**< Shift value for LCD_BACTRL */
<> 144:ef7eb2e8f9f7 439 #define _LCD_SYNCBUSY_BACTRL_MASK 0x2UL /**< Bit mask for LCD_BACTRL */
<> 144:ef7eb2e8f9f7 440 #define _LCD_SYNCBUSY_BACTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
<> 144:ef7eb2e8f9f7 441 #define LCD_SYNCBUSY_BACTRL_DEFAULT (_LCD_SYNCBUSY_BACTRL_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
<> 144:ef7eb2e8f9f7 442 #define LCD_SYNCBUSY_AREGA (0x1UL << 2) /**< AREGA Register Busy */
<> 144:ef7eb2e8f9f7 443 #define _LCD_SYNCBUSY_AREGA_SHIFT 2 /**< Shift value for LCD_AREGA */
<> 144:ef7eb2e8f9f7 444 #define _LCD_SYNCBUSY_AREGA_MASK 0x4UL /**< Bit mask for LCD_AREGA */
<> 144:ef7eb2e8f9f7 445 #define _LCD_SYNCBUSY_AREGA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
<> 144:ef7eb2e8f9f7 446 #define LCD_SYNCBUSY_AREGA_DEFAULT (_LCD_SYNCBUSY_AREGA_DEFAULT << 2) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
<> 144:ef7eb2e8f9f7 447 #define LCD_SYNCBUSY_AREGB (0x1UL << 3) /**< AREGB Register Busy */
<> 144:ef7eb2e8f9f7 448 #define _LCD_SYNCBUSY_AREGB_SHIFT 3 /**< Shift value for LCD_AREGB */
<> 144:ef7eb2e8f9f7 449 #define _LCD_SYNCBUSY_AREGB_MASK 0x8UL /**< Bit mask for LCD_AREGB */
<> 144:ef7eb2e8f9f7 450 #define _LCD_SYNCBUSY_AREGB_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
<> 144:ef7eb2e8f9f7 451 #define LCD_SYNCBUSY_AREGB_DEFAULT (_LCD_SYNCBUSY_AREGB_DEFAULT << 3) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
<> 144:ef7eb2e8f9f7 452 #define LCD_SYNCBUSY_SEGD0L (0x1UL << 4) /**< SEGD0L Register Busy */
<> 144:ef7eb2e8f9f7 453 #define _LCD_SYNCBUSY_SEGD0L_SHIFT 4 /**< Shift value for LCD_SEGD0L */
<> 144:ef7eb2e8f9f7 454 #define _LCD_SYNCBUSY_SEGD0L_MASK 0x10UL /**< Bit mask for LCD_SEGD0L */
<> 144:ef7eb2e8f9f7 455 #define _LCD_SYNCBUSY_SEGD0L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
<> 144:ef7eb2e8f9f7 456 #define LCD_SYNCBUSY_SEGD0L_DEFAULT (_LCD_SYNCBUSY_SEGD0L_DEFAULT << 4) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
<> 144:ef7eb2e8f9f7 457 #define LCD_SYNCBUSY_SEGD1L (0x1UL << 5) /**< SEGD1L Register Busy */
<> 144:ef7eb2e8f9f7 458 #define _LCD_SYNCBUSY_SEGD1L_SHIFT 5 /**< Shift value for LCD_SEGD1L */
<> 144:ef7eb2e8f9f7 459 #define _LCD_SYNCBUSY_SEGD1L_MASK 0x20UL /**< Bit mask for LCD_SEGD1L */
<> 144:ef7eb2e8f9f7 460 #define _LCD_SYNCBUSY_SEGD1L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
<> 144:ef7eb2e8f9f7 461 #define LCD_SYNCBUSY_SEGD1L_DEFAULT (_LCD_SYNCBUSY_SEGD1L_DEFAULT << 5) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
<> 144:ef7eb2e8f9f7 462 #define LCD_SYNCBUSY_SEGD2L (0x1UL << 6) /**< SEGD2L Register Busy */
<> 144:ef7eb2e8f9f7 463 #define _LCD_SYNCBUSY_SEGD2L_SHIFT 6 /**< Shift value for LCD_SEGD2L */
<> 144:ef7eb2e8f9f7 464 #define _LCD_SYNCBUSY_SEGD2L_MASK 0x40UL /**< Bit mask for LCD_SEGD2L */
<> 144:ef7eb2e8f9f7 465 #define _LCD_SYNCBUSY_SEGD2L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
<> 144:ef7eb2e8f9f7 466 #define LCD_SYNCBUSY_SEGD2L_DEFAULT (_LCD_SYNCBUSY_SEGD2L_DEFAULT << 6) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
<> 144:ef7eb2e8f9f7 467 #define LCD_SYNCBUSY_SEGD3L (0x1UL << 7) /**< SEGD3L Register Busy */
<> 144:ef7eb2e8f9f7 468 #define _LCD_SYNCBUSY_SEGD3L_SHIFT 7 /**< Shift value for LCD_SEGD3L */
<> 144:ef7eb2e8f9f7 469 #define _LCD_SYNCBUSY_SEGD3L_MASK 0x80UL /**< Bit mask for LCD_SEGD3L */
<> 144:ef7eb2e8f9f7 470 #define _LCD_SYNCBUSY_SEGD3L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
<> 144:ef7eb2e8f9f7 471 #define LCD_SYNCBUSY_SEGD3L_DEFAULT (_LCD_SYNCBUSY_SEGD3L_DEFAULT << 7) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
<> 144:ef7eb2e8f9f7 472 #define LCD_SYNCBUSY_SEGD0H (0x1UL << 8) /**< SEGD0H Register Busy */
<> 144:ef7eb2e8f9f7 473 #define _LCD_SYNCBUSY_SEGD0H_SHIFT 8 /**< Shift value for LCD_SEGD0H */
<> 144:ef7eb2e8f9f7 474 #define _LCD_SYNCBUSY_SEGD0H_MASK 0x100UL /**< Bit mask for LCD_SEGD0H */
<> 144:ef7eb2e8f9f7 475 #define _LCD_SYNCBUSY_SEGD0H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
<> 144:ef7eb2e8f9f7 476 #define LCD_SYNCBUSY_SEGD0H_DEFAULT (_LCD_SYNCBUSY_SEGD0H_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
<> 144:ef7eb2e8f9f7 477 #define LCD_SYNCBUSY_SEGD1H (0x1UL << 9) /**< SEGD1H Register Busy */
<> 144:ef7eb2e8f9f7 478 #define _LCD_SYNCBUSY_SEGD1H_SHIFT 9 /**< Shift value for LCD_SEGD1H */
<> 144:ef7eb2e8f9f7 479 #define _LCD_SYNCBUSY_SEGD1H_MASK 0x200UL /**< Bit mask for LCD_SEGD1H */
<> 144:ef7eb2e8f9f7 480 #define _LCD_SYNCBUSY_SEGD1H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
<> 144:ef7eb2e8f9f7 481 #define LCD_SYNCBUSY_SEGD1H_DEFAULT (_LCD_SYNCBUSY_SEGD1H_DEFAULT << 9) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
<> 144:ef7eb2e8f9f7 482 #define LCD_SYNCBUSY_SEGD2H (0x1UL << 10) /**< SEGD2H Register Busy */
<> 144:ef7eb2e8f9f7 483 #define _LCD_SYNCBUSY_SEGD2H_SHIFT 10 /**< Shift value for LCD_SEGD2H */
<> 144:ef7eb2e8f9f7 484 #define _LCD_SYNCBUSY_SEGD2H_MASK 0x400UL /**< Bit mask for LCD_SEGD2H */
<> 144:ef7eb2e8f9f7 485 #define _LCD_SYNCBUSY_SEGD2H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
<> 144:ef7eb2e8f9f7 486 #define LCD_SYNCBUSY_SEGD2H_DEFAULT (_LCD_SYNCBUSY_SEGD2H_DEFAULT << 10) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
<> 144:ef7eb2e8f9f7 487 #define LCD_SYNCBUSY_SEGD3H (0x1UL << 11) /**< SEGD3H Register Busy */
<> 144:ef7eb2e8f9f7 488 #define _LCD_SYNCBUSY_SEGD3H_SHIFT 11 /**< Shift value for LCD_SEGD3H */
<> 144:ef7eb2e8f9f7 489 #define _LCD_SYNCBUSY_SEGD3H_MASK 0x800UL /**< Bit mask for LCD_SEGD3H */
<> 144:ef7eb2e8f9f7 490 #define _LCD_SYNCBUSY_SEGD3H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
<> 144:ef7eb2e8f9f7 491 #define LCD_SYNCBUSY_SEGD3H_DEFAULT (_LCD_SYNCBUSY_SEGD3H_DEFAULT << 11) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
<> 144:ef7eb2e8f9f7 492 #define LCD_SYNCBUSY_SEGD4H (0x1UL << 12) /**< SEGD4H Register Busy */
<> 144:ef7eb2e8f9f7 493 #define _LCD_SYNCBUSY_SEGD4H_SHIFT 12 /**< Shift value for LCD_SEGD4H */
<> 144:ef7eb2e8f9f7 494 #define _LCD_SYNCBUSY_SEGD4H_MASK 0x1000UL /**< Bit mask for LCD_SEGD4H */
<> 144:ef7eb2e8f9f7 495 #define _LCD_SYNCBUSY_SEGD4H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
<> 144:ef7eb2e8f9f7 496 #define LCD_SYNCBUSY_SEGD4H_DEFAULT (_LCD_SYNCBUSY_SEGD4H_DEFAULT << 12) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
<> 144:ef7eb2e8f9f7 497 #define LCD_SYNCBUSY_SEGD5H (0x1UL << 13) /**< SEGD5H Register Busy */
<> 144:ef7eb2e8f9f7 498 #define _LCD_SYNCBUSY_SEGD5H_SHIFT 13 /**< Shift value for LCD_SEGD5H */
<> 144:ef7eb2e8f9f7 499 #define _LCD_SYNCBUSY_SEGD5H_MASK 0x2000UL /**< Bit mask for LCD_SEGD5H */
<> 144:ef7eb2e8f9f7 500 #define _LCD_SYNCBUSY_SEGD5H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
<> 144:ef7eb2e8f9f7 501 #define LCD_SYNCBUSY_SEGD5H_DEFAULT (_LCD_SYNCBUSY_SEGD5H_DEFAULT << 13) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
<> 144:ef7eb2e8f9f7 502 #define LCD_SYNCBUSY_SEGD6H (0x1UL << 14) /**< SEGD6H Register Busy */
<> 144:ef7eb2e8f9f7 503 #define _LCD_SYNCBUSY_SEGD6H_SHIFT 14 /**< Shift value for LCD_SEGD6H */
<> 144:ef7eb2e8f9f7 504 #define _LCD_SYNCBUSY_SEGD6H_MASK 0x4000UL /**< Bit mask for LCD_SEGD6H */
<> 144:ef7eb2e8f9f7 505 #define _LCD_SYNCBUSY_SEGD6H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
<> 144:ef7eb2e8f9f7 506 #define LCD_SYNCBUSY_SEGD6H_DEFAULT (_LCD_SYNCBUSY_SEGD6H_DEFAULT << 14) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
<> 144:ef7eb2e8f9f7 507 #define LCD_SYNCBUSY_SEGD7H (0x1UL << 15) /**< SEGD7H Register Busy */
<> 144:ef7eb2e8f9f7 508 #define _LCD_SYNCBUSY_SEGD7H_SHIFT 15 /**< Shift value for LCD_SEGD7H */
<> 144:ef7eb2e8f9f7 509 #define _LCD_SYNCBUSY_SEGD7H_MASK 0x8000UL /**< Bit mask for LCD_SEGD7H */
<> 144:ef7eb2e8f9f7 510 #define _LCD_SYNCBUSY_SEGD7H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
<> 144:ef7eb2e8f9f7 511 #define LCD_SYNCBUSY_SEGD7H_DEFAULT (_LCD_SYNCBUSY_SEGD7H_DEFAULT << 15) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
<> 144:ef7eb2e8f9f7 512 #define LCD_SYNCBUSY_SEGD4L (0x1UL << 16) /**< SEGD4L Register Busy */
<> 144:ef7eb2e8f9f7 513 #define _LCD_SYNCBUSY_SEGD4L_SHIFT 16 /**< Shift value for LCD_SEGD4L */
<> 144:ef7eb2e8f9f7 514 #define _LCD_SYNCBUSY_SEGD4L_MASK 0x10000UL /**< Bit mask for LCD_SEGD4L */
<> 144:ef7eb2e8f9f7 515 #define _LCD_SYNCBUSY_SEGD4L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
<> 144:ef7eb2e8f9f7 516 #define LCD_SYNCBUSY_SEGD4L_DEFAULT (_LCD_SYNCBUSY_SEGD4L_DEFAULT << 16) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
<> 144:ef7eb2e8f9f7 517 #define LCD_SYNCBUSY_SEGD5L (0x1UL << 17) /**< SEGD5L Register Busy */
<> 144:ef7eb2e8f9f7 518 #define _LCD_SYNCBUSY_SEGD5L_SHIFT 17 /**< Shift value for LCD_SEGD5L */
<> 144:ef7eb2e8f9f7 519 #define _LCD_SYNCBUSY_SEGD5L_MASK 0x20000UL /**< Bit mask for LCD_SEGD5L */
<> 144:ef7eb2e8f9f7 520 #define _LCD_SYNCBUSY_SEGD5L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
<> 144:ef7eb2e8f9f7 521 #define LCD_SYNCBUSY_SEGD5L_DEFAULT (_LCD_SYNCBUSY_SEGD5L_DEFAULT << 17) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
<> 144:ef7eb2e8f9f7 522 #define LCD_SYNCBUSY_SEGD6L (0x1UL << 18) /**< SEGD6L Register Busy */
<> 144:ef7eb2e8f9f7 523 #define _LCD_SYNCBUSY_SEGD6L_SHIFT 18 /**< Shift value for LCD_SEGD6L */
<> 144:ef7eb2e8f9f7 524 #define _LCD_SYNCBUSY_SEGD6L_MASK 0x40000UL /**< Bit mask for LCD_SEGD6L */
<> 144:ef7eb2e8f9f7 525 #define _LCD_SYNCBUSY_SEGD6L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
<> 144:ef7eb2e8f9f7 526 #define LCD_SYNCBUSY_SEGD6L_DEFAULT (_LCD_SYNCBUSY_SEGD6L_DEFAULT << 18) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
<> 144:ef7eb2e8f9f7 527 #define LCD_SYNCBUSY_SEGD7L (0x1UL << 19) /**< SEGD7L Register Busy */
<> 144:ef7eb2e8f9f7 528 #define _LCD_SYNCBUSY_SEGD7L_SHIFT 19 /**< Shift value for LCD_SEGD7L */
<> 144:ef7eb2e8f9f7 529 #define _LCD_SYNCBUSY_SEGD7L_MASK 0x80000UL /**< Bit mask for LCD_SEGD7L */
<> 144:ef7eb2e8f9f7 530 #define _LCD_SYNCBUSY_SEGD7L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
<> 144:ef7eb2e8f9f7 531 #define LCD_SYNCBUSY_SEGD7L_DEFAULT (_LCD_SYNCBUSY_SEGD7L_DEFAULT << 19) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
<> 144:ef7eb2e8f9f7 532
<> 144:ef7eb2e8f9f7 533 /* Bit fields for LCD SEGD4H */
<> 144:ef7eb2e8f9f7 534 #define _LCD_SEGD4H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD4H */
<> 144:ef7eb2e8f9f7 535 #define _LCD_SEGD4H_MASK 0x000000FFUL /**< Mask for LCD_SEGD4H */
<> 144:ef7eb2e8f9f7 536 #define _LCD_SEGD4H_SEGD4H_SHIFT 0 /**< Shift value for LCD_SEGD4H */
<> 144:ef7eb2e8f9f7 537 #define _LCD_SEGD4H_SEGD4H_MASK 0xFFUL /**< Bit mask for LCD_SEGD4H */
<> 144:ef7eb2e8f9f7 538 #define _LCD_SEGD4H_SEGD4H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD4H */
<> 144:ef7eb2e8f9f7 539 #define LCD_SEGD4H_SEGD4H_DEFAULT (_LCD_SEGD4H_SEGD4H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD4H */
<> 144:ef7eb2e8f9f7 540
<> 144:ef7eb2e8f9f7 541 /* Bit fields for LCD SEGD5H */
<> 144:ef7eb2e8f9f7 542 #define _LCD_SEGD5H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD5H */
<> 144:ef7eb2e8f9f7 543 #define _LCD_SEGD5H_MASK 0x000000FFUL /**< Mask for LCD_SEGD5H */
<> 144:ef7eb2e8f9f7 544 #define _LCD_SEGD5H_SEGD5H_SHIFT 0 /**< Shift value for LCD_SEGD5H */
<> 144:ef7eb2e8f9f7 545 #define _LCD_SEGD5H_SEGD5H_MASK 0xFFUL /**< Bit mask for LCD_SEGD5H */
<> 144:ef7eb2e8f9f7 546 #define _LCD_SEGD5H_SEGD5H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD5H */
<> 144:ef7eb2e8f9f7 547 #define LCD_SEGD5H_SEGD5H_DEFAULT (_LCD_SEGD5H_SEGD5H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD5H */
<> 144:ef7eb2e8f9f7 548
<> 144:ef7eb2e8f9f7 549 /* Bit fields for LCD SEGD6H */
<> 144:ef7eb2e8f9f7 550 #define _LCD_SEGD6H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD6H */
<> 144:ef7eb2e8f9f7 551 #define _LCD_SEGD6H_MASK 0x000000FFUL /**< Mask for LCD_SEGD6H */
<> 144:ef7eb2e8f9f7 552 #define _LCD_SEGD6H_SEGD6H_SHIFT 0 /**< Shift value for LCD_SEGD6H */
<> 144:ef7eb2e8f9f7 553 #define _LCD_SEGD6H_SEGD6H_MASK 0xFFUL /**< Bit mask for LCD_SEGD6H */
<> 144:ef7eb2e8f9f7 554 #define _LCD_SEGD6H_SEGD6H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD6H */
<> 144:ef7eb2e8f9f7 555 #define LCD_SEGD6H_SEGD6H_DEFAULT (_LCD_SEGD6H_SEGD6H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD6H */
<> 144:ef7eb2e8f9f7 556
<> 144:ef7eb2e8f9f7 557 /* Bit fields for LCD SEGD7H */
<> 144:ef7eb2e8f9f7 558 #define _LCD_SEGD7H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD7H */
<> 144:ef7eb2e8f9f7 559 #define _LCD_SEGD7H_MASK 0x000000FFUL /**< Mask for LCD_SEGD7H */
<> 144:ef7eb2e8f9f7 560 #define _LCD_SEGD7H_SEGD7H_SHIFT 0 /**< Shift value for LCD_SEGD7H */
<> 144:ef7eb2e8f9f7 561 #define _LCD_SEGD7H_SEGD7H_MASK 0xFFUL /**< Bit mask for LCD_SEGD7H */
<> 144:ef7eb2e8f9f7 562 #define _LCD_SEGD7H_SEGD7H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD7H */
<> 144:ef7eb2e8f9f7 563 #define LCD_SEGD7H_SEGD7H_DEFAULT (_LCD_SEGD7H_SEGD7H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD7H */
<> 144:ef7eb2e8f9f7 564
<> 144:ef7eb2e8f9f7 565 /* Bit fields for LCD SEGD4L */
<> 144:ef7eb2e8f9f7 566 #define _LCD_SEGD4L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD4L */
<> 144:ef7eb2e8f9f7 567 #define _LCD_SEGD4L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD4L */
<> 144:ef7eb2e8f9f7 568 #define _LCD_SEGD4L_SEGD4L_SHIFT 0 /**< Shift value for LCD_SEGD4L */
<> 144:ef7eb2e8f9f7 569 #define _LCD_SEGD4L_SEGD4L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD4L */
<> 144:ef7eb2e8f9f7 570 #define _LCD_SEGD4L_SEGD4L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD4L */
<> 144:ef7eb2e8f9f7 571 #define LCD_SEGD4L_SEGD4L_DEFAULT (_LCD_SEGD4L_SEGD4L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD4L */
<> 144:ef7eb2e8f9f7 572
<> 144:ef7eb2e8f9f7 573 /* Bit fields for LCD SEGD5L */
<> 144:ef7eb2e8f9f7 574 #define _LCD_SEGD5L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD5L */
<> 144:ef7eb2e8f9f7 575 #define _LCD_SEGD5L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD5L */
<> 144:ef7eb2e8f9f7 576 #define _LCD_SEGD5L_SEGD5L_SHIFT 0 /**< Shift value for LCD_SEGD5L */
<> 144:ef7eb2e8f9f7 577 #define _LCD_SEGD5L_SEGD5L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD5L */
<> 144:ef7eb2e8f9f7 578 #define _LCD_SEGD5L_SEGD5L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD5L */
<> 144:ef7eb2e8f9f7 579 #define LCD_SEGD5L_SEGD5L_DEFAULT (_LCD_SEGD5L_SEGD5L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD5L */
<> 144:ef7eb2e8f9f7 580
<> 144:ef7eb2e8f9f7 581 /* Bit fields for LCD SEGD6L */
<> 144:ef7eb2e8f9f7 582 #define _LCD_SEGD6L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD6L */
<> 144:ef7eb2e8f9f7 583 #define _LCD_SEGD6L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD6L */
<> 144:ef7eb2e8f9f7 584 #define _LCD_SEGD6L_SEGD6L_SHIFT 0 /**< Shift value for LCD_SEGD6L */
<> 144:ef7eb2e8f9f7 585 #define _LCD_SEGD6L_SEGD6L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD6L */
<> 144:ef7eb2e8f9f7 586 #define _LCD_SEGD6L_SEGD6L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD6L */
<> 144:ef7eb2e8f9f7 587 #define LCD_SEGD6L_SEGD6L_DEFAULT (_LCD_SEGD6L_SEGD6L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD6L */
<> 144:ef7eb2e8f9f7 588
<> 144:ef7eb2e8f9f7 589 /* Bit fields for LCD SEGD7L */
<> 144:ef7eb2e8f9f7 590 #define _LCD_SEGD7L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD7L */
<> 144:ef7eb2e8f9f7 591 #define _LCD_SEGD7L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD7L */
<> 144:ef7eb2e8f9f7 592 #define _LCD_SEGD7L_SEGD7L_SHIFT 0 /**< Shift value for LCD_SEGD7L */
<> 144:ef7eb2e8f9f7 593 #define _LCD_SEGD7L_SEGD7L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD7L */
<> 144:ef7eb2e8f9f7 594 #define _LCD_SEGD7L_SEGD7L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD7L */
<> 144:ef7eb2e8f9f7 595 #define LCD_SEGD7L_SEGD7L_DEFAULT (_LCD_SEGD7L_SEGD7L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD7L */
<> 144:ef7eb2e8f9f7 596
<> 144:ef7eb2e8f9f7 597 /** @} End of group EFM32LG_LCD */
<> 144:ef7eb2e8f9f7 598 /** @} End of group Parts */
<> 144:ef7eb2e8f9f7 599