Fawwaz Nadzmy / mbed-STM

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targets/TARGET_RENESAS/TARGET_RZ_A1H/device/MBRZA1H.h@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/MBRZA1H.h@144:ef7eb2e8f9f7 
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*******************************************************************************
<> 144:ef7eb2e8f9f7 2 * DISCLAIMER
<> 144:ef7eb2e8f9f7 3 * This software is supplied by Renesas Electronics Corporation and is only
<> 144:ef7eb2e8f9f7 4 * intended for use with Renesas products. No other uses are authorized. This
<> 144:ef7eb2e8f9f7 5 * software is owned by Renesas Electronics Corporation and is protected under
<> 144:ef7eb2e8f9f7 6 * all applicable laws, including copyright laws.
<> 144:ef7eb2e8f9f7 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
<> 144:ef7eb2e8f9f7 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
<> 144:ef7eb2e8f9f7 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
<> 144:ef7eb2e8f9f7 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
<> 144:ef7eb2e8f9f7 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
<> 144:ef7eb2e8f9f7 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
<> 144:ef7eb2e8f9f7 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
<> 144:ef7eb2e8f9f7 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
<> 144:ef7eb2e8f9f7 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
<> 144:ef7eb2e8f9f7 16 * Renesas reserves the right, without notice, to make changes to this software
<> 144:ef7eb2e8f9f7 17 * and to discontinue the availability of this software. By using this software,
<> 144:ef7eb2e8f9f7 18 * you agree to the additional terms and conditions found by accessing the
<> 144:ef7eb2e8f9f7 19 * following link:
<> 144:ef7eb2e8f9f7 20 * http://www.renesas.com/disclaimer
<> 144:ef7eb2e8f9f7 21 * Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
<> 144:ef7eb2e8f9f7 22 *******************************************************************************/
<> 144:ef7eb2e8f9f7 23 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 24 * @file MBRZA1H.h
<> 144:ef7eb2e8f9f7 25 * @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File for
<> 144:ef7eb2e8f9f7 26 * Renesas MBRZA1H Device Series
<> 144:ef7eb2e8f9f7 27 * @version
<> 144:ef7eb2e8f9f7 28 * @date 19 Sept 2013
<> 144:ef7eb2e8f9f7 29 *
<> 144:ef7eb2e8f9f7 30 * @note
<> 144:ef7eb2e8f9f7 31 *
<> 144:ef7eb2e8f9f7 32 ******************************************************************************/
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 #ifndef __MBRZA1H_H__
<> 144:ef7eb2e8f9f7 35 #define __MBRZA1H_H__
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 38 extern "C" {
<> 144:ef7eb2e8f9f7 39 #endif
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 /* ------------------------- Interrupt Number Definition ------------------------ */
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 typedef enum IRQn
<> 144:ef7eb2e8f9f7 45 {
<> 144:ef7eb2e8f9f7 46 /****** SGI Interrupts Numbers ****************************************/
<> 144:ef7eb2e8f9f7 47 SGI0_IRQn = 0,
<> 144:ef7eb2e8f9f7 48 SGI1_IRQn = 1,
<> 144:ef7eb2e8f9f7 49 SGI2_IRQn = 2,
<> 144:ef7eb2e8f9f7 50 SGI3_IRQn = 3,
<> 144:ef7eb2e8f9f7 51 SGI4_IRQn = 4,
<> 144:ef7eb2e8f9f7 52 SGI5_IRQn = 5,
<> 144:ef7eb2e8f9f7 53 SGI6_IRQn = 6,
<> 144:ef7eb2e8f9f7 54 SGI7_IRQn = 7,
<> 144:ef7eb2e8f9f7 55 SGI8_IRQn = 8,
<> 144:ef7eb2e8f9f7 56 SGI9_IRQn = 9,
<> 144:ef7eb2e8f9f7 57 SGI10_IRQn = 10,
<> 144:ef7eb2e8f9f7 58 SGI11_IRQn = 11,
<> 144:ef7eb2e8f9f7 59 SGI12_IRQn = 12,
<> 144:ef7eb2e8f9f7 60 SGI13_IRQn = 13,
<> 144:ef7eb2e8f9f7 61 SGI14_IRQn = 14,
<> 144:ef7eb2e8f9f7 62 SGI15_IRQn = 15,
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 /****** Cortex-A9 Processor Exceptions Numbers ****************************************/
<> 144:ef7eb2e8f9f7 65 /* 16 - 578 */
<> 144:ef7eb2e8f9f7 66 PMUIRQ0_IRQn = 16,
<> 144:ef7eb2e8f9f7 67 COMMRX0_IRQn = 17,
<> 144:ef7eb2e8f9f7 68 COMMTX0_IRQn = 18,
<> 144:ef7eb2e8f9f7 69 CTIIRQ0_IRQn = 19,
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 IRQ0_IRQn = 32,
<> 144:ef7eb2e8f9f7 72 IRQ1_IRQn = 33,
<> 144:ef7eb2e8f9f7 73 IRQ2_IRQn = 34,
<> 144:ef7eb2e8f9f7 74 IRQ3_IRQn = 35,
<> 144:ef7eb2e8f9f7 75 IRQ4_IRQn = 36,
<> 144:ef7eb2e8f9f7 76 IRQ5_IRQn = 37,
<> 144:ef7eb2e8f9f7 77 IRQ6_IRQn = 38,
<> 144:ef7eb2e8f9f7 78 IRQ7_IRQn = 39,
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 PL310ERR_IRQn = 40,
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 DMAINT0_IRQn = 41, /*!< DMAC Interrupt */
<> 144:ef7eb2e8f9f7 83 DMAINT1_IRQn = 42, /*!< DMAC Interrupt */
<> 144:ef7eb2e8f9f7 84 DMAINT2_IRQn = 43, /*!< DMAC Interrupt */
<> 144:ef7eb2e8f9f7 85 DMAINT3_IRQn = 44, /*!< DMAC Interrupt */
<> 144:ef7eb2e8f9f7 86 DMAINT4_IRQn = 45, /*!< DMAC Interrupt */
<> 144:ef7eb2e8f9f7 87 DMAINT5_IRQn = 46, /*!< DMAC Interrupt */
<> 144:ef7eb2e8f9f7 88 DMAINT6_IRQn = 47, /*!< DMAC Interrupt */
<> 144:ef7eb2e8f9f7 89 DMAINT7_IRQn = 48, /*!< DMAC Interrupt */
<> 144:ef7eb2e8f9f7 90 DMAINT8_IRQn = 49, /*!< DMAC Interrupt */
<> 144:ef7eb2e8f9f7 91 DMAINT9_IRQn = 50, /*!< DMAC Interrupt */
<> 144:ef7eb2e8f9f7 92 DMAINT10_IRQn = 51, /*!< DMAC Interrupt */
<> 144:ef7eb2e8f9f7 93 DMAINT11_IRQn = 52, /*!< DMAC Interrupt */
<> 144:ef7eb2e8f9f7 94 DMAINT12_IRQn = 53, /*!< DMAC Interrupt */
<> 144:ef7eb2e8f9f7 95 DMAINT13_IRQn = 54, /*!< DMAC Interrupt */
<> 144:ef7eb2e8f9f7 96 DMAINT14_IRQn = 55, /*!< DMAC Interrupt */
<> 144:ef7eb2e8f9f7 97 DMAINT15_IRQn = 56, /*!< DMAC Interrupt */
<> 144:ef7eb2e8f9f7 98 DMAERR_IRQn = 57, /*!< DMAC Interrupt */
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 /* 58-72 Reserved */
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 USBI0_IRQn = 73,
<> 144:ef7eb2e8f9f7 103 USBI1_IRQn = 74,
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 S0_VI_VSYNC0_IRQn = 75,
<> 144:ef7eb2e8f9f7 106 S0_LO_VSYNC0_IRQn = 76,
<> 144:ef7eb2e8f9f7 107 S0_VSYNCERR0_IRQn = 77,
<> 144:ef7eb2e8f9f7 108 GR3_VLINE0_IRQn = 78,
<> 144:ef7eb2e8f9f7 109 S0_VFIELD0_IRQn = 79,
<> 144:ef7eb2e8f9f7 110 IV1_VBUFERR0_IRQn = 80,
<> 144:ef7eb2e8f9f7 111 IV3_VBUFERR0_IRQn = 81,
<> 144:ef7eb2e8f9f7 112 IV5_VBUFERR0_IRQn = 82,
<> 144:ef7eb2e8f9f7 113 IV6_VBUFERR0_IRQn = 83,
<> 144:ef7eb2e8f9f7 114 S0_WLINE0_IRQn = 84,
<> 144:ef7eb2e8f9f7 115 S1_VI_VSYNC0_IRQn = 85,
<> 144:ef7eb2e8f9f7 116 S1_LO_VSYNC0_IRQn = 86,
<> 144:ef7eb2e8f9f7 117 S1_VSYNCERR0_IRQn = 87,
<> 144:ef7eb2e8f9f7 118 S1_VFIELD0_IRQn = 88,
<> 144:ef7eb2e8f9f7 119 IV2_VBUFERR0_IRQn = 89,
<> 144:ef7eb2e8f9f7 120 IV4_VBUFERR0_IRQn = 90,
<> 144:ef7eb2e8f9f7 121 S1_WLINE0_IRQn = 91,
<> 144:ef7eb2e8f9f7 122 OIR_VI_VSYNC0_IRQn = 92,
<> 144:ef7eb2e8f9f7 123 OIR_LO_VSYNC0_IRQn = 93,
<> 144:ef7eb2e8f9f7 124 OIR_VSYNCERR0_IRQn = 94,
<> 144:ef7eb2e8f9f7 125 OIR_VFIELD0_IRQn = 95,
<> 144:ef7eb2e8f9f7 126 IV7_VBUFERR0_IRQn = 96,
<> 144:ef7eb2e8f9f7 127 IV8_VBUFERR0_IRQn = 97,
<> 144:ef7eb2e8f9f7 128 /* 98 Reserved */
<> 144:ef7eb2e8f9f7 129 S0_VI_VSYNC1_IRQn = 99,
<> 144:ef7eb2e8f9f7 130 S0_LO_VSYNC1_IRQn = 100,
<> 144:ef7eb2e8f9f7 131 S0_VSYNCERR1_IRQn = 101,
<> 144:ef7eb2e8f9f7 132 GR3_VLINE1_IRQn = 102,
<> 144:ef7eb2e8f9f7 133 S0_VFIELD1_IRQn = 103,
<> 144:ef7eb2e8f9f7 134 IV1_VBUFERR1_IRQn = 104,
<> 144:ef7eb2e8f9f7 135 IV3_VBUFERR1_IRQn = 105,
<> 144:ef7eb2e8f9f7 136 IV5_VBUFERR1_IRQn = 106,
<> 144:ef7eb2e8f9f7 137 IV6_VBUFERR1_IRQn = 107,
<> 144:ef7eb2e8f9f7 138 S0_WLINE1_IRQn = 108,
<> 144:ef7eb2e8f9f7 139 S1_VI_VSYNC1_IRQn = 109,
<> 144:ef7eb2e8f9f7 140 S1_LO_VSYNC1_IRQn = 110,
<> 144:ef7eb2e8f9f7 141 S1_VSYNCERR1_IRQn = 111,
<> 144:ef7eb2e8f9f7 142 S1_VFIELD1_IRQn = 112,
<> 144:ef7eb2e8f9f7 143 IV2_VBUFERR1_IRQn = 113,
<> 144:ef7eb2e8f9f7 144 IV4_VBUFERR1_IRQn = 114,
<> 144:ef7eb2e8f9f7 145 S1_WLINE1_IRQn = 115,
<> 144:ef7eb2e8f9f7 146 OIR_VI_VSYNC1_IRQn = 116,
<> 144:ef7eb2e8f9f7 147 OIR_LO_VSYNC1_IRQn = 117,
<> 144:ef7eb2e8f9f7 148 OIR_VSYNCERR1_IRQn = 118,
<> 144:ef7eb2e8f9f7 149 OIR_VFIELD1_IRQn = 119,
<> 144:ef7eb2e8f9f7 150 IV7_VBUFERR1_IRQn = 120,
<> 144:ef7eb2e8f9f7 151 IV8_VBUFERR1_IRQn = 121,
<> 144:ef7eb2e8f9f7 152 /* Reserved = 122 */
<> 144:ef7eb2e8f9f7 153
<> 144:ef7eb2e8f9f7 154 IMRDI_IRQn = 123,
<> 144:ef7eb2e8f9f7 155 IMR2I0_IRQn = 124,
<> 144:ef7eb2e8f9f7 156 IMR2I1_IRQn = 125,
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 JEDI_IRQn = 126,
<> 144:ef7eb2e8f9f7 159 JDTI_IRQn = 127,
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 CMP0_IRQn = 128,
<> 144:ef7eb2e8f9f7 162 CMP1_IRQn = 129,
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 INT0_IRQn = 130,
<> 144:ef7eb2e8f9f7 165 INT1_IRQn = 131,
<> 144:ef7eb2e8f9f7 166 INT2_IRQn = 132,
<> 144:ef7eb2e8f9f7 167 INT3_IRQn = 133,
<> 144:ef7eb2e8f9f7 168
<> 144:ef7eb2e8f9f7 169 OSTMI0TINT_IRQn = 134, /*!< OSTM Interrupt */
<> 144:ef7eb2e8f9f7 170 OSTMI1TINT_IRQn = 135, /*!< OSTM Interrupt */
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 CMI_IRQn = 136,
<> 144:ef7eb2e8f9f7 173 WTOUT_IRQn = 137,
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 ITI_IRQn = 138,
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 TGI0A_IRQn = 139,
<> 144:ef7eb2e8f9f7 178 TGI0B_IRQn = 140,
<> 144:ef7eb2e8f9f7 179 TGI0C_IRQn = 141,
<> 144:ef7eb2e8f9f7 180 TGI0D_IRQn = 142,
<> 144:ef7eb2e8f9f7 181 TGI0V_IRQn = 143,
<> 144:ef7eb2e8f9f7 182 TGI0E_IRQn = 144,
<> 144:ef7eb2e8f9f7 183 TGI0F_IRQn = 145,
<> 144:ef7eb2e8f9f7 184 TGI1A_IRQn = 146,
<> 144:ef7eb2e8f9f7 185 TGI1B_IRQn = 147,
<> 144:ef7eb2e8f9f7 186 TGI1V_IRQn = 148,
<> 144:ef7eb2e8f9f7 187 TGI1U_IRQn = 149,
<> 144:ef7eb2e8f9f7 188 TGI2A_IRQn = 150,
<> 144:ef7eb2e8f9f7 189 TGI2B_IRQn = 151,
<> 144:ef7eb2e8f9f7 190 TGI2V_IRQn = 152,
<> 144:ef7eb2e8f9f7 191 TGI2U_IRQn = 153,
<> 144:ef7eb2e8f9f7 192 TGI3A_IRQn = 154,
<> 144:ef7eb2e8f9f7 193 TGI3B_IRQn = 155,
<> 144:ef7eb2e8f9f7 194 TGI3C_IRQn = 156,
<> 144:ef7eb2e8f9f7 195 TGI3D_IRQn = 157,
<> 144:ef7eb2e8f9f7 196 TGI3V_IRQn = 158,
<> 144:ef7eb2e8f9f7 197 TGI4A_IRQn = 159,
<> 144:ef7eb2e8f9f7 198 TGI4B_IRQn = 160,
<> 144:ef7eb2e8f9f7 199 TGI4C_IRQn = 161,
<> 144:ef7eb2e8f9f7 200 TGI4D_IRQn = 162,
<> 144:ef7eb2e8f9f7 201 TGI4V_IRQn = 163,
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 CMI1_IRQn = 164,
<> 144:ef7eb2e8f9f7 204 CMI2_IRQn = 165,
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 SGDEI0_IRQn = 166,
<> 144:ef7eb2e8f9f7 207 SGDEI1_IRQn = 167,
<> 144:ef7eb2e8f9f7 208 SGDEI2_IRQn = 168,
<> 144:ef7eb2e8f9f7 209 SGDEI3_IRQn = 169,
<> 144:ef7eb2e8f9f7 210
<> 144:ef7eb2e8f9f7 211 ADI_IRQn = 170,
<> 144:ef7eb2e8f9f7 212 LMTI_IRQn = 171,
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 SSII0_IRQn = 172, /*!< SSIF Interrupt */
<> 144:ef7eb2e8f9f7 215 SSIRXI0_IRQn = 173, /*!< SSIF Interrupt */
<> 144:ef7eb2e8f9f7 216 SSITXI0_IRQn = 174, /*!< SSIF Interrupt */
<> 144:ef7eb2e8f9f7 217 SSII1_IRQn = 175, /*!< SSIF Interrupt */
<> 144:ef7eb2e8f9f7 218 SSIRXI1_IRQn = 176, /*!< SSIF Interrupt */
<> 144:ef7eb2e8f9f7 219 SSITXI1_IRQn = 177, /*!< SSIF Interrupt */
<> 144:ef7eb2e8f9f7 220 SSII2_IRQn = 178, /*!< SSIF Interrupt */
<> 144:ef7eb2e8f9f7 221 SSIRTI2_IRQn = 179, /*!< SSIF Interrupt */
<> 144:ef7eb2e8f9f7 222 SSII3_IRQn = 180, /*!< SSIF Interrupt */
<> 144:ef7eb2e8f9f7 223 SSIRXI3_IRQn = 181, /*!< SSIF Interrupt */
<> 144:ef7eb2e8f9f7 224 SSITXI3_IRQn = 182, /*!< SSIF Interrupt */
<> 144:ef7eb2e8f9f7 225 SSII4_IRQn = 183, /*!< SSIF Interrupt */
<> 144:ef7eb2e8f9f7 226 SSIRTI4_IRQn = 184, /*!< SSIF Interrupt */
<> 144:ef7eb2e8f9f7 227 SSII5_IRQn = 185, /*!< SSIF Interrupt */
<> 144:ef7eb2e8f9f7 228 SSIRXI5_IRQn = 186, /*!< SSIF Interrupt */
<> 144:ef7eb2e8f9f7 229 SSITXI5_IRQn = 187, /*!< SSIF Interrupt */
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 SPDIFI_IRQn = 188,
<> 144:ef7eb2e8f9f7 232
<> 144:ef7eb2e8f9f7 233 INTIICTEI0_IRQn = 189, /*!< RIIC Interrupt */
<> 144:ef7eb2e8f9f7 234 INTIICRI0_IRQn = 190, /*!< RIIC Interrupt */
<> 144:ef7eb2e8f9f7 235 INTIICTI0_IRQn = 191, /*!< RIIC Interrupt */
<> 144:ef7eb2e8f9f7 236 INTIICSPI0_IRQn = 192, /*!< RIIC Interrupt */
<> 144:ef7eb2e8f9f7 237 INTIICSTI0_IRQn = 193, /*!< RIIC Interrupt */
<> 144:ef7eb2e8f9f7 238 INTIICNAKI0_IRQn = 194, /*!< RIIC Interrupt */
<> 144:ef7eb2e8f9f7 239 INTIICALI0_IRQn = 195, /*!< RIIC Interrupt */
<> 144:ef7eb2e8f9f7 240 INTIICTMOI0_IRQn = 196, /*!< RIIC Interrupt */
<> 144:ef7eb2e8f9f7 241 INTIICTEI1_IRQn = 197, /*!< RIIC Interrupt */
<> 144:ef7eb2e8f9f7 242 INTIICRI1_IRQn = 198, /*!< RIIC Interrupt */
<> 144:ef7eb2e8f9f7 243 INTIICTI1_IRQn = 199, /*!< RIIC Interrupt */
<> 144:ef7eb2e8f9f7 244 INTIICSPI1_IRQn = 200, /*!< RIIC Interrupt */
<> 144:ef7eb2e8f9f7 245 INTIICSTI1_IRQn = 201, /*!< RIIC Interrupt */
<> 144:ef7eb2e8f9f7 246 INTIICNAKI1_IRQn = 202, /*!< RIIC Interrupt */
<> 144:ef7eb2e8f9f7 247 INTIICALI1_IRQn = 203, /*!< RIIC Interrupt */
<> 144:ef7eb2e8f9f7 248 INTIICTMOI1_IRQn = 204, /*!< RIIC Interrupt */
<> 144:ef7eb2e8f9f7 249 INTIICTEI2_IRQn = 205, /*!< RIIC Interrupt */
<> 144:ef7eb2e8f9f7 250 INTIICRI2_IRQn = 206, /*!< RIIC Interrupt */
<> 144:ef7eb2e8f9f7 251 INTIICTI2_IRQn = 207, /*!< RIIC Interrupt */
<> 144:ef7eb2e8f9f7 252 INTIICSPI2_IRQn = 208, /*!< RIIC Interrupt */
<> 144:ef7eb2e8f9f7 253 INTIICSTI2_IRQn = 209, /*!< RIIC Interrupt */
<> 144:ef7eb2e8f9f7 254 INTIICNAKI2_IRQn = 210, /*!< RIIC Interrupt */
<> 144:ef7eb2e8f9f7 255 INTIICALI2_IRQn = 211, /*!< RIIC Interrupt */
<> 144:ef7eb2e8f9f7 256 INTIICTMOI2_IRQn = 212, /*!< RIIC Interrupt */
<> 144:ef7eb2e8f9f7 257 INTIICTEI3_IRQn = 213, /*!< RIIC Interrupt */
<> 144:ef7eb2e8f9f7 258 INTIICRI3_IRQn = 214, /*!< RIIC Interrupt */
<> 144:ef7eb2e8f9f7 259 INTIICTI3_IRQn = 215, /*!< RIIC Interrupt */
<> 144:ef7eb2e8f9f7 260 INTIICSPI3_IRQn = 216, /*!< RIIC Interrupt */
<> 144:ef7eb2e8f9f7 261 INTIICSTI3_IRQn = 217, /*!< RIIC Interrupt */
<> 144:ef7eb2e8f9f7 262 INTIICNAKI3_IRQn = 218, /*!< RIIC Interrupt */
<> 144:ef7eb2e8f9f7 263 INTIICALI3_IRQn = 219, /*!< RIIC Interrupt */
<> 144:ef7eb2e8f9f7 264 INTIICTMOI3_IRQn = 220, /*!< RIIC Interrupt */
<> 144:ef7eb2e8f9f7 265
<> 144:ef7eb2e8f9f7 266 SCIFBRI0_IRQn = 221, /*!< SCIF Interrupt */
<> 144:ef7eb2e8f9f7 267 SCIFERI0_IRQn = 222, /*!< SCIF Interrupt */
<> 144:ef7eb2e8f9f7 268 SCIFRXI0_IRQn = 223, /*!< SCIF Interrupt */
<> 144:ef7eb2e8f9f7 269 SCIFTXI0_IRQn = 224, /*!< SCIF Interrupt */
<> 144:ef7eb2e8f9f7 270 SCIFBRI1_IRQn = 225, /*!< SCIF Interrupt */
<> 144:ef7eb2e8f9f7 271 SCIFERI1_IRQn = 226, /*!< SCIF Interrupt */
<> 144:ef7eb2e8f9f7 272 SCIFRXI1_IRQn = 227, /*!< SCIF Interrupt */
<> 144:ef7eb2e8f9f7 273 SCIFTXI1_IRQn = 228, /*!< SCIF Interrupt */
<> 144:ef7eb2e8f9f7 274 SCIFBRI2_IRQn = 229, /*!< SCIF Interrupt */
<> 144:ef7eb2e8f9f7 275 SCIFERI2_IRQn = 230, /*!< SCIF Interrupt */
<> 144:ef7eb2e8f9f7 276 SCIFRXI2_IRQn = 231, /*!< SCIF Interrupt */
<> 144:ef7eb2e8f9f7 277 SCIFTXI2_IRQn = 232, /*!< SCIF Interrupt */
<> 144:ef7eb2e8f9f7 278 SCIFBRI3_IRQn = 233, /*!< SCIF Interrupt */
<> 144:ef7eb2e8f9f7 279 SCIFERI3_IRQn = 234, /*!< SCIF Interrupt */
<> 144:ef7eb2e8f9f7 280 SCIFRXI3_IRQn = 235, /*!< SCIF Interrupt */
<> 144:ef7eb2e8f9f7 281 SCIFTXI3_IRQn = 236, /*!< SCIF Interrupt */
<> 144:ef7eb2e8f9f7 282 SCIFBRI4_IRQn = 237, /*!< SCIF Interrupt */
<> 144:ef7eb2e8f9f7 283 SCIFERI4_IRQn = 238, /*!< SCIF Interrupt */
<> 144:ef7eb2e8f9f7 284 SCIFRXI4_IRQn = 239, /*!< SCIF Interrupt */
<> 144:ef7eb2e8f9f7 285 SCIFTXI4_IRQn = 240, /*!< SCIF Interrupt */
<> 144:ef7eb2e8f9f7 286 SCIFBRI5_IRQn = 241, /*!< SCIF Interrupt */
<> 144:ef7eb2e8f9f7 287 SCIFERI5_IRQn = 242, /*!< SCIF Interrupt */
<> 144:ef7eb2e8f9f7 288 SCIFRXI5_IRQn = 243, /*!< SCIF Interrupt */
<> 144:ef7eb2e8f9f7 289 SCIFTXI5_IRQn = 244, /*!< SCIF Interrupt */
<> 144:ef7eb2e8f9f7 290 SCIFBRI6_IRQn = 245, /*!< SCIF Interrupt */
<> 144:ef7eb2e8f9f7 291 SCIFERI6_IRQn = 246, /*!< SCIF Interrupt */
<> 144:ef7eb2e8f9f7 292 SCIFRXI6_IRQn = 247, /*!< SCIF Interrupt */
<> 144:ef7eb2e8f9f7 293 SCIFTXI6_IRQn = 248, /*!< SCIF Interrupt */
<> 144:ef7eb2e8f9f7 294 SCIFBRI7_IRQn = 249, /*!< SCIF Interrupt */
<> 144:ef7eb2e8f9f7 295 SCIFERI7_IRQn = 250, /*!< SCIF Interrupt */
<> 144:ef7eb2e8f9f7 296 SCIFRXI7_IRQn = 251, /*!< SCIF Interrupt */
<> 144:ef7eb2e8f9f7 297 SCIFTXI7_IRQn = 252, /*!< SCIF Interrupt */
<> 144:ef7eb2e8f9f7 298
<> 144:ef7eb2e8f9f7 299 INTRCANGERR_IRQn = 253,
<> 144:ef7eb2e8f9f7 300 INTRCANGRECC_IRQn = 254,
<> 144:ef7eb2e8f9f7 301 INTRCAN0REC_IRQn = 255,
<> 144:ef7eb2e8f9f7 302 INTRCAN0ERR_IRQn = 256,
<> 144:ef7eb2e8f9f7 303 INTRCAN0TRX_IRQn = 257,
<> 144:ef7eb2e8f9f7 304 INTRCAN1REC_IRQn = 258,
<> 144:ef7eb2e8f9f7 305 INTRCAN1ERR_IRQn = 259,
<> 144:ef7eb2e8f9f7 306 INTRCAN1TRX_IRQn = 260,
<> 144:ef7eb2e8f9f7 307 INTRCAN2REC_IRQn = 261,
<> 144:ef7eb2e8f9f7 308 INTRCAN2ERR_IRQn = 262,
<> 144:ef7eb2e8f9f7 309 INTRCAN2TRX_IRQn = 263,
<> 144:ef7eb2e8f9f7 310 INTRCAN3REC_IRQn = 264,
<> 144:ef7eb2e8f9f7 311 INTRCAN3ERR_IRQn = 265,
<> 144:ef7eb2e8f9f7 312 INTRCAN3TRX_IRQn = 266,
<> 144:ef7eb2e8f9f7 313 INTRCAN4REC_IRQn = 267,
<> 144:ef7eb2e8f9f7 314 INTRCAN4ERR_IRQn = 268,
<> 144:ef7eb2e8f9f7 315 INTRCAN4TRX_IRQn = 269,
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 RSPISPEI0_IRQn = 270, /*!< RSPI Interrupt */
<> 144:ef7eb2e8f9f7 318 RSPISPRI0_IRQn = 271, /*!< RSPI Interrupt */
<> 144:ef7eb2e8f9f7 319 RSPISPTI0_IRQn = 272, /*!< RSPI Interrupt */
<> 144:ef7eb2e8f9f7 320 RSPISPEI1_IRQn = 273, /*!< RSPI Interrupt */
<> 144:ef7eb2e8f9f7 321 RSPISPRI1_IRQn = 274, /*!< RSPI Interrupt */
<> 144:ef7eb2e8f9f7 322 RSPISPTI1_IRQn = 275, /*!< RSPI Interrupt */
<> 144:ef7eb2e8f9f7 323 RSPISPEI2_IRQn = 276, /*!< RSPI Interrupt */
<> 144:ef7eb2e8f9f7 324 RSPISPRI2_IRQn = 277, /*!< RSPI Interrupt */
<> 144:ef7eb2e8f9f7 325 RSPISPTI2_IRQn = 278, /*!< RSPI Interrupt */
<> 144:ef7eb2e8f9f7 326 RSPISPEI3_IRQn = 279, /*!< RSPI Interrupt */
<> 144:ef7eb2e8f9f7 327 RSPISPRI3_IRQn = 280, /*!< RSPI Interrupt */
<> 144:ef7eb2e8f9f7 328 RSPISPTI3_IRQn = 281, /*!< RSPI Interrupt */
<> 144:ef7eb2e8f9f7 329 RSPISPEI4_IRQn = 282, /*!< RSPI Interrupt */
<> 144:ef7eb2e8f9f7 330 RSPISPRI4_IRQn = 283, /*!< RSPI Interrupt */
<> 144:ef7eb2e8f9f7 331 RSPISPTI4_IRQn = 284, /*!< RSPI Interrupt */
<> 144:ef7eb2e8f9f7 332
<> 144:ef7eb2e8f9f7 333 IEBBTD_IRQn = 285,
<> 144:ef7eb2e8f9f7 334 IEBBTERR_IRQn = 286,
<> 144:ef7eb2e8f9f7 335 IEBBTSTA_IRQn = 287,
<> 144:ef7eb2e8f9f7 336 IEBBTV_IRQn = 288,
<> 144:ef7eb2e8f9f7 337
<> 144:ef7eb2e8f9f7 338 ISY_IRQn = 289,
<> 144:ef7eb2e8f9f7 339 IERR_IRQn = 290,
<> 144:ef7eb2e8f9f7 340 ITARG_IRQn = 291,
<> 144:ef7eb2e8f9f7 341 ISEC_IRQn = 292,
<> 144:ef7eb2e8f9f7 342 IBUF_IRQn = 293,
<> 144:ef7eb2e8f9f7 343 IREADY_IRQn = 294,
<> 144:ef7eb2e8f9f7 344
<> 144:ef7eb2e8f9f7 345 STERB_IRQn = 295,
<> 144:ef7eb2e8f9f7 346 FLTENDI_IRQn = 296,
<> 144:ef7eb2e8f9f7 347 FLTREQ0I_IRQn = 297,
<> 144:ef7eb2e8f9f7 348 FLTREQ1I_IRQn = 298,
<> 144:ef7eb2e8f9f7 349
<> 144:ef7eb2e8f9f7 350 MMC0_IRQn = 299,
<> 144:ef7eb2e8f9f7 351 MMC1_IRQn = 300,
<> 144:ef7eb2e8f9f7 352 MMC2_IRQn = 301,
<> 144:ef7eb2e8f9f7 353
<> 144:ef7eb2e8f9f7 354 SCHI0_3_IRQn = 302,
<> 144:ef7eb2e8f9f7 355 SDHI0_0_IRQn = 303,
<> 144:ef7eb2e8f9f7 356 SDHI0_1_IRQn = 304,
<> 144:ef7eb2e8f9f7 357 SCHI1_3_IRQn = 305,
<> 144:ef7eb2e8f9f7 358 SDHI1_0_IRQn = 306,
<> 144:ef7eb2e8f9f7 359 SDHI1_1_IRQn = 307,
<> 144:ef7eb2e8f9f7 360
<> 144:ef7eb2e8f9f7 361 ARM_IRQn = 308,
<> 144:ef7eb2e8f9f7 362 PRD_IRQn = 309,
<> 144:ef7eb2e8f9f7 363 CUP_IRQn = 310,
<> 144:ef7eb2e8f9f7 364
<> 144:ef7eb2e8f9f7 365 SCUAI0_IRQn = 311,
<> 144:ef7eb2e8f9f7 366 SCUAI1_IRQn = 312,
<> 144:ef7eb2e8f9f7 367 SCUFDI0_IRQn = 313,
<> 144:ef7eb2e8f9f7 368 SCUFDI1_IRQn = 314,
<> 144:ef7eb2e8f9f7 369 SCUFDI2_IRQn = 315,
<> 144:ef7eb2e8f9f7 370 SCUFDI3_IRQn = 316,
<> 144:ef7eb2e8f9f7 371 SCUFUI0_IRQn = 317,
<> 144:ef7eb2e8f9f7 372 SCUFUI1_IRQn = 318,
<> 144:ef7eb2e8f9f7 373 SCUFUI2_IRQn = 319,
<> 144:ef7eb2e8f9f7 374 SCUFUI3_IRQn = 320,
<> 144:ef7eb2e8f9f7 375 SCUDVI0_IRQn = 321,
<> 144:ef7eb2e8f9f7 376 SCUDVI1_IRQn = 322,
<> 144:ef7eb2e8f9f7 377 SCUDVI2_IRQn = 323,
<> 144:ef7eb2e8f9f7 378 SCUDVI3_IRQn = 324,
<> 144:ef7eb2e8f9f7 379
<> 144:ef7eb2e8f9f7 380 MLB_CINT_IRQn = 325,
<> 144:ef7eb2e8f9f7 381 MLB_SINT_IRQn = 326,
<> 144:ef7eb2e8f9f7 382
<> 144:ef7eb2e8f9f7 383 DRC10_IRQn = 327,
<> 144:ef7eb2e8f9f7 384 DRC11_IRQn = 328,
<> 144:ef7eb2e8f9f7 385
<> 144:ef7eb2e8f9f7 386 /* 329-330 Reserved */
<> 144:ef7eb2e8f9f7 387
<> 144:ef7eb2e8f9f7 388 LINI0_INT_T_IRQn = 331,
<> 144:ef7eb2e8f9f7 389 LINI0_INT_R_IRQn = 332,
<> 144:ef7eb2e8f9f7 390 LINI0_INT_S_IRQn = 333,
<> 144:ef7eb2e8f9f7 391 LINI0_INT_M_IRQn = 334,
<> 144:ef7eb2e8f9f7 392 LINI1_INT_T_IRQn = 335,
<> 144:ef7eb2e8f9f7 393 LINI1_INT_R_IRQn = 336,
<> 144:ef7eb2e8f9f7 394 LINI1_INT_S_IRQn = 337,
<> 144:ef7eb2e8f9f7 395 LINI1_INT_M_IRQn = 338,
<> 144:ef7eb2e8f9f7 396
<> 144:ef7eb2e8f9f7 397 /* 339-346 Reserved */
<> 144:ef7eb2e8f9f7 398
<> 144:ef7eb2e8f9f7 399 SCIERI0_IRQn = 347,
<> 144:ef7eb2e8f9f7 400 SCIRXI0_IRQn = 348,
<> 144:ef7eb2e8f9f7 401 SCITXI0_IRQn = 349,
<> 144:ef7eb2e8f9f7 402 SCITEI0_IRQn = 350,
<> 144:ef7eb2e8f9f7 403 SCIERI1_IRQn = 351,
<> 144:ef7eb2e8f9f7 404 SCIRXI1_IRQn = 352,
<> 144:ef7eb2e8f9f7 405 SCITXI1_IRQn = 353,
<> 144:ef7eb2e8f9f7 406 SCITEI1_IRQn = 354,
<> 144:ef7eb2e8f9f7 407
<> 144:ef7eb2e8f9f7 408 AVBI_DATA = 355,
<> 144:ef7eb2e8f9f7 409 AVBI_ERROR = 356,
<> 144:ef7eb2e8f9f7 410 AVBI_MANAGE = 357,
<> 144:ef7eb2e8f9f7 411 AVBI_MAC = 358,
<> 144:ef7eb2e8f9f7 412
<> 144:ef7eb2e8f9f7 413 ETHERI_IRQn = 359,
<> 144:ef7eb2e8f9f7 414
<> 144:ef7eb2e8f9f7 415 /* 360-363 Reserved */
<> 144:ef7eb2e8f9f7 416
<> 144:ef7eb2e8f9f7 417 CEUI_IRQn = 364,
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419 /* 365-380 Reserved */
<> 144:ef7eb2e8f9f7 420
<> 144:ef7eb2e8f9f7 421
<> 144:ef7eb2e8f9f7 422 H2XMLB_ERRINT_IRQn = 381,
<> 144:ef7eb2e8f9f7 423 H2XIC1_ERRINT_IRQn = 382,
<> 144:ef7eb2e8f9f7 424 X2HPERI1_ERRINT_IRQn = 383,
<> 144:ef7eb2e8f9f7 425 X2HPERR2_ERRINT_IRQn = 384,
<> 144:ef7eb2e8f9f7 426 X2HPERR34_ERRINT_IRQn= 385,
<> 144:ef7eb2e8f9f7 427 X2HPERR5_ERRINT_IRQn = 386,
<> 144:ef7eb2e8f9f7 428 X2HPERR67_ERRINT_IRQn= 387,
<> 144:ef7eb2e8f9f7 429 X2HDBGR_ERRINT_IRQn = 388,
<> 144:ef7eb2e8f9f7 430 X2HBSC_ERRINT_IRQn = 389,
<> 144:ef7eb2e8f9f7 431 X2HSPI1_ERRINT_IRQn = 390,
<> 144:ef7eb2e8f9f7 432 X2HSPI2_ERRINT_IRQn = 391,
<> 144:ef7eb2e8f9f7 433 PRRI_IRQn = 392,
<> 144:ef7eb2e8f9f7 434
<> 144:ef7eb2e8f9f7 435 IFEI0_IRQn = 393,
<> 144:ef7eb2e8f9f7 436 OFFI0_IRQn = 394,
<> 144:ef7eb2e8f9f7 437 PFVEI0_IRQn = 395,
<> 144:ef7eb2e8f9f7 438 IFEI1_IRQn = 396,
<> 144:ef7eb2e8f9f7 439 OFFI1_IRQn = 397,
<> 144:ef7eb2e8f9f7 440 PFVEI1_IRQn = 398,
<> 144:ef7eb2e8f9f7 441
<> 144:ef7eb2e8f9f7 442 /* 399-415 Reserved */
<> 144:ef7eb2e8f9f7 443 TINT0_IRQn = 416,
<> 144:ef7eb2e8f9f7 444 TINT1_IRQn = 417,
<> 144:ef7eb2e8f9f7 445 TINT2_IRQn = 418,
<> 144:ef7eb2e8f9f7 446 TINT3_IRQn = 419,
<> 144:ef7eb2e8f9f7 447 TINT4_IRQn = 420,
<> 144:ef7eb2e8f9f7 448 TINT5_IRQn = 421,
<> 144:ef7eb2e8f9f7 449 TINT6_IRQn = 422,
<> 144:ef7eb2e8f9f7 450 TINT7_IRQn = 423,
<> 144:ef7eb2e8f9f7 451 TINT8_IRQn = 424,
<> 144:ef7eb2e8f9f7 452 TINT9_IRQn = 425,
<> 144:ef7eb2e8f9f7 453 TINT10_IRQn = 426,
<> 144:ef7eb2e8f9f7 454 TINT11_IRQn = 427,
<> 144:ef7eb2e8f9f7 455 TINT12_IRQn = 428,
<> 144:ef7eb2e8f9f7 456 TINT13_IRQn = 429,
<> 144:ef7eb2e8f9f7 457 TINT14_IRQn = 430,
<> 144:ef7eb2e8f9f7 458 TINT15_IRQn = 431,
<> 144:ef7eb2e8f9f7 459 TINT16_IRQn = 432,
<> 144:ef7eb2e8f9f7 460 TINT17_IRQn = 433,
<> 144:ef7eb2e8f9f7 461 TINT18_IRQn = 434,
<> 144:ef7eb2e8f9f7 462 TINT19_IRQn = 435,
<> 144:ef7eb2e8f9f7 463 TINT20_IRQn = 436,
<> 144:ef7eb2e8f9f7 464 TINT21_IRQn = 437,
<> 144:ef7eb2e8f9f7 465 TINT22_IRQn = 438,
<> 144:ef7eb2e8f9f7 466 TINT23_IRQn = 439,
<> 144:ef7eb2e8f9f7 467 TINT24_IRQn = 440,
<> 144:ef7eb2e8f9f7 468 TINT25_IRQn = 441,
<> 144:ef7eb2e8f9f7 469 TINT26_IRQn = 442,
<> 144:ef7eb2e8f9f7 470 TINT27_IRQn = 443,
<> 144:ef7eb2e8f9f7 471 TINT28_IRQn = 444,
<> 144:ef7eb2e8f9f7 472 TINT29_IRQn = 445,
<> 144:ef7eb2e8f9f7 473 TINT30_IRQn = 446,
<> 144:ef7eb2e8f9f7 474 TINT31_IRQn = 447,
<> 144:ef7eb2e8f9f7 475 TINT32_IRQn = 448,
<> 144:ef7eb2e8f9f7 476 TINT33_IRQn = 449,
<> 144:ef7eb2e8f9f7 477 TINT34_IRQn = 450,
<> 144:ef7eb2e8f9f7 478 TINT35_IRQn = 451,
<> 144:ef7eb2e8f9f7 479 TINT36_IRQn = 452,
<> 144:ef7eb2e8f9f7 480 TINT37_IRQn = 453,
<> 144:ef7eb2e8f9f7 481 TINT38_IRQn = 454,
<> 144:ef7eb2e8f9f7 482 TINT39_IRQn = 455,
<> 144:ef7eb2e8f9f7 483 TINT40_IRQn = 456,
<> 144:ef7eb2e8f9f7 484 TINT41_IRQn = 457,
<> 144:ef7eb2e8f9f7 485 TINT42_IRQn = 458,
<> 144:ef7eb2e8f9f7 486 TINT43_IRQn = 459,
<> 144:ef7eb2e8f9f7 487 TINT44_IRQn = 460,
<> 144:ef7eb2e8f9f7 488 TINT45_IRQn = 461,
<> 144:ef7eb2e8f9f7 489 TINT46_IRQn = 462,
<> 144:ef7eb2e8f9f7 490 TINT47_IRQn = 463,
<> 144:ef7eb2e8f9f7 491 TINT48_IRQn = 464,
<> 144:ef7eb2e8f9f7 492 TINT49_IRQn = 465,
<> 144:ef7eb2e8f9f7 493 TINT50_IRQn = 466,
<> 144:ef7eb2e8f9f7 494 TINT51_IRQn = 467,
<> 144:ef7eb2e8f9f7 495 TINT52_IRQn = 468,
<> 144:ef7eb2e8f9f7 496 TINT53_IRQn = 469,
<> 144:ef7eb2e8f9f7 497 TINT54_IRQn = 470,
<> 144:ef7eb2e8f9f7 498 TINT55_IRQn = 471,
<> 144:ef7eb2e8f9f7 499 TINT56_IRQn = 472,
<> 144:ef7eb2e8f9f7 500 TINT57_IRQn = 473,
<> 144:ef7eb2e8f9f7 501 TINT58_IRQn = 474,
<> 144:ef7eb2e8f9f7 502 TINT59_IRQn = 475,
<> 144:ef7eb2e8f9f7 503 TINT60_IRQn = 476,
<> 144:ef7eb2e8f9f7 504 TINT61_IRQn = 477,
<> 144:ef7eb2e8f9f7 505 TINT62_IRQn = 478,
<> 144:ef7eb2e8f9f7 506 TINT63_IRQn = 479,
<> 144:ef7eb2e8f9f7 507 TINT64_IRQn = 480,
<> 144:ef7eb2e8f9f7 508 TINT65_IRQn = 481,
<> 144:ef7eb2e8f9f7 509 TINT66_IRQn = 482,
<> 144:ef7eb2e8f9f7 510 TINT67_IRQn = 483,
<> 144:ef7eb2e8f9f7 511 TINT68_IRQn = 484,
<> 144:ef7eb2e8f9f7 512 TINT69_IRQn = 485,
<> 144:ef7eb2e8f9f7 513 TINT70_IRQn = 486,
<> 144:ef7eb2e8f9f7 514 TINT71_IRQn = 487,
<> 144:ef7eb2e8f9f7 515 TINT72_IRQn = 488,
<> 144:ef7eb2e8f9f7 516 TINT73_IRQn = 489,
<> 144:ef7eb2e8f9f7 517 TINT74_IRQn = 490,
<> 144:ef7eb2e8f9f7 518 TINT75_IRQn = 491,
<> 144:ef7eb2e8f9f7 519 TINT76_IRQn = 492,
<> 144:ef7eb2e8f9f7 520 TINT77_IRQn = 493,
<> 144:ef7eb2e8f9f7 521 TINT78_IRQn = 494,
<> 144:ef7eb2e8f9f7 522 TINT79_IRQn = 495,
<> 144:ef7eb2e8f9f7 523 TINT80_IRQn = 496,
<> 144:ef7eb2e8f9f7 524 TINT81_IRQn = 497,
<> 144:ef7eb2e8f9f7 525 TINT82_IRQn = 498,
<> 144:ef7eb2e8f9f7 526 TINT83_IRQn = 499,
<> 144:ef7eb2e8f9f7 527 TINT84_IRQn = 500,
<> 144:ef7eb2e8f9f7 528 TINT85_IRQn = 501,
<> 144:ef7eb2e8f9f7 529 TINT86_IRQn = 502,
<> 144:ef7eb2e8f9f7 530 TINT87_IRQn = 503,
<> 144:ef7eb2e8f9f7 531 TINT88_IRQn = 504,
<> 144:ef7eb2e8f9f7 532 TINT89_IRQn = 505,
<> 144:ef7eb2e8f9f7 533 TINT90_IRQn = 506,
<> 144:ef7eb2e8f9f7 534 TINT91_IRQn = 507,
<> 144:ef7eb2e8f9f7 535 TINT92_IRQn = 508,
<> 144:ef7eb2e8f9f7 536 TINT93_IRQn = 509,
<> 144:ef7eb2e8f9f7 537 TINT94_IRQn = 510,
<> 144:ef7eb2e8f9f7 538 TINT95_IRQn = 511,
<> 144:ef7eb2e8f9f7 539 TINT96_IRQn = 512,
<> 144:ef7eb2e8f9f7 540 TINT97_IRQn = 513,
<> 144:ef7eb2e8f9f7 541 TINT98_IRQn = 514,
<> 144:ef7eb2e8f9f7 542 TINT99_IRQn = 515,
<> 144:ef7eb2e8f9f7 543 TINT100_IRQn = 516,
<> 144:ef7eb2e8f9f7 544 TINT101_IRQn = 517,
<> 144:ef7eb2e8f9f7 545 TINT102_IRQn = 518,
<> 144:ef7eb2e8f9f7 546 TINT103_IRQn = 519,
<> 144:ef7eb2e8f9f7 547 TINT104_IRQn = 520,
<> 144:ef7eb2e8f9f7 548 TINT105_IRQn = 521,
<> 144:ef7eb2e8f9f7 549 TINT106_IRQn = 522,
<> 144:ef7eb2e8f9f7 550 TINT107_IRQn = 523,
<> 144:ef7eb2e8f9f7 551 TINT108_IRQn = 524,
<> 144:ef7eb2e8f9f7 552 TINT109_IRQn = 525,
<> 144:ef7eb2e8f9f7 553 TINT110_IRQn = 526,
<> 144:ef7eb2e8f9f7 554 TINT111_IRQn = 527,
<> 144:ef7eb2e8f9f7 555 TINT112_IRQn = 528,
<> 144:ef7eb2e8f9f7 556 TINT113_IRQn = 529,
<> 144:ef7eb2e8f9f7 557 TINT114_IRQn = 530,
<> 144:ef7eb2e8f9f7 558 TINT115_IRQn = 531,
<> 144:ef7eb2e8f9f7 559 TINT116_IRQn = 532,
<> 144:ef7eb2e8f9f7 560 TINT117_IRQn = 533,
<> 144:ef7eb2e8f9f7 561 TINT118_IRQn = 534,
<> 144:ef7eb2e8f9f7 562 TINT119_IRQn = 535,
<> 144:ef7eb2e8f9f7 563 TINT120_IRQn = 536,
<> 144:ef7eb2e8f9f7 564 TINT121_IRQn = 537,
<> 144:ef7eb2e8f9f7 565 TINT122_IRQn = 538,
<> 144:ef7eb2e8f9f7 566 TINT123_IRQn = 539,
<> 144:ef7eb2e8f9f7 567 TINT124_IRQn = 540,
<> 144:ef7eb2e8f9f7 568 TINT125_IRQn = 541,
<> 144:ef7eb2e8f9f7 569 TINT126_IRQn = 542,
<> 144:ef7eb2e8f9f7 570 TINT127_IRQn = 543,
<> 144:ef7eb2e8f9f7 571 TINT128_IRQn = 544,
<> 144:ef7eb2e8f9f7 572 TINT129_IRQn = 545,
<> 144:ef7eb2e8f9f7 573 TINT130_IRQn = 546,
<> 144:ef7eb2e8f9f7 574 TINT131_IRQn = 547,
<> 144:ef7eb2e8f9f7 575 TINT132_IRQn = 548,
<> 144:ef7eb2e8f9f7 576 TINT133_IRQn = 549,
<> 144:ef7eb2e8f9f7 577 TINT134_IRQn = 550,
<> 144:ef7eb2e8f9f7 578 TINT135_IRQn = 551,
<> 144:ef7eb2e8f9f7 579 TINT136_IRQn = 552,
<> 144:ef7eb2e8f9f7 580 TINT137_IRQn = 553,
<> 144:ef7eb2e8f9f7 581 TINT138_IRQn = 554,
<> 144:ef7eb2e8f9f7 582 TINT139_IRQn = 555,
<> 144:ef7eb2e8f9f7 583 TINT140_IRQn = 556,
<> 144:ef7eb2e8f9f7 584 TINT141_IRQn = 557,
<> 144:ef7eb2e8f9f7 585 TINT142_IRQn = 558,
<> 144:ef7eb2e8f9f7 586 TINT143_IRQn = 559,
<> 144:ef7eb2e8f9f7 587 TINT144_IRQn = 560,
<> 144:ef7eb2e8f9f7 588 TINT145_IRQn = 561,
<> 144:ef7eb2e8f9f7 589 TINT146_IRQn = 562,
<> 144:ef7eb2e8f9f7 590 TINT147_IRQn = 563,
<> 144:ef7eb2e8f9f7 591 TINT148_IRQn = 564,
<> 144:ef7eb2e8f9f7 592 TINT149_IRQn = 565,
<> 144:ef7eb2e8f9f7 593 TINT150_IRQn = 566,
<> 144:ef7eb2e8f9f7 594 TINT151_IRQn = 567,
<> 144:ef7eb2e8f9f7 595 TINT152_IRQn = 568,
<> 144:ef7eb2e8f9f7 596 TINT153_IRQn = 569,
<> 144:ef7eb2e8f9f7 597 TINT154_IRQn = 570,
<> 144:ef7eb2e8f9f7 598 TINT155_IRQn = 571,
<> 144:ef7eb2e8f9f7 599 TINT156_IRQn = 572,
<> 144:ef7eb2e8f9f7 600 TINT157_IRQn = 573,
<> 144:ef7eb2e8f9f7 601 TINT158_IRQn = 574,
<> 144:ef7eb2e8f9f7 602 TINT159_IRQn = 575,
<> 144:ef7eb2e8f9f7 603 TINT160_IRQn = 576,
<> 144:ef7eb2e8f9f7 604 TINT161_IRQn = 577,
<> 144:ef7eb2e8f9f7 605 TINT162_IRQn = 578,
<> 144:ef7eb2e8f9f7 606 TINT163_IRQn = 579,
<> 144:ef7eb2e8f9f7 607 TINT164_IRQn = 580,
<> 144:ef7eb2e8f9f7 608 TINT165_IRQn = 581,
<> 144:ef7eb2e8f9f7 609 TINT166_IRQn = 582,
<> 144:ef7eb2e8f9f7 610 TINT167_IRQn = 583,
<> 144:ef7eb2e8f9f7 611 TINT168_IRQn = 584,
<> 144:ef7eb2e8f9f7 612 TINT169_IRQn = 585,
<> 144:ef7eb2e8f9f7 613 TINT170_IRQn = 586
<> 144:ef7eb2e8f9f7 614
<> 144:ef7eb2e8f9f7 615 } IRQn_Type;
<> 144:ef7eb2e8f9f7 616
<> 144:ef7eb2e8f9f7 617 #define Renesas_RZ_A1_IRQ_MAX TINT170_IRQn
<> 144:ef7eb2e8f9f7 618
<> 144:ef7eb2e8f9f7 619 /* -------- Configuration of the Cortex-A9 Processor and Core Peripherals ------- */
<> 144:ef7eb2e8f9f7 620 #define __CA9_REV 0x0000 /*!< Core revision r0 */
<> 144:ef7eb2e8f9f7 621
<> 144:ef7eb2e8f9f7 622 #define __MPU_PRESENT 1 /*!< MPU present or not */
<> 144:ef7eb2e8f9f7 623
<> 144:ef7eb2e8f9f7 624 #define __FPU_PRESENT 1 /*!< FPU present or not */
<> 144:ef7eb2e8f9f7 625
<> 144:ef7eb2e8f9f7 626 #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
<> 144:ef7eb2e8f9f7 627 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
<> 144:ef7eb2e8f9f7 628
<> 144:ef7eb2e8f9f7 629 #include <core_ca9.h>
<> 144:ef7eb2e8f9f7 630 #include "system_MBRZA1H.h"
<> 144:ef7eb2e8f9f7 631
<> 144:ef7eb2e8f9f7 632
<> 144:ef7eb2e8f9f7 633 /******************************************************************************/
<> 144:ef7eb2e8f9f7 634 /* Device Specific Peripheral Section */
<> 144:ef7eb2e8f9f7 635 /******************************************************************************/
<> 144:ef7eb2e8f9f7 636 /** @addtogroup Renesas_RZ_A1_Peripherals Renesas_RZ_A1 Peripherals
<> 144:ef7eb2e8f9f7 637 Renesas_RZ_A1 Device Specific Peripheral registers structures
<> 144:ef7eb2e8f9f7 638 @{
<> 144:ef7eb2e8f9f7 639 */
<> 144:ef7eb2e8f9f7 640
<> 144:ef7eb2e8f9f7 641 #if defined ( __CC_ARM )
<> 144:ef7eb2e8f9f7 642 #pragma anon_unions
<> 144:ef7eb2e8f9f7 643 #endif
<> 144:ef7eb2e8f9f7 644
<> 144:ef7eb2e8f9f7 645 #include "pl310.h"
<> 144:ef7eb2e8f9f7 646 #include "gic.h"
<> 144:ef7eb2e8f9f7 647 #include "nvic_wrapper.h"
<> 144:ef7eb2e8f9f7 648 #include "cmsis_nvic.h"
<> 144:ef7eb2e8f9f7 649
<> 144:ef7eb2e8f9f7 650 #include "ostm_iodefine.h"
<> 144:ef7eb2e8f9f7 651 #include "gpio_iodefine.h"
<> 144:ef7eb2e8f9f7 652 #include "cpg_iodefine.h"
<> 144:ef7eb2e8f9f7 653 #include "l2c_iodefine.h"
<> 144:ef7eb2e8f9f7 654
<> 144:ef7eb2e8f9f7 655 #if defined ( __CC_ARM )
<> 144:ef7eb2e8f9f7 656 #pragma no_anon_unions
<> 144:ef7eb2e8f9f7 657 #endif
<> 144:ef7eb2e8f9f7 658
<> 144:ef7eb2e8f9f7 659 /*@}*/ /* end of group Renesas_RZ_A1_Peripherals */
<> 144:ef7eb2e8f9f7 660
<> 144:ef7eb2e8f9f7 661
<> 144:ef7eb2e8f9f7 662 /******************************************************************************/
<> 144:ef7eb2e8f9f7 663 /* Peripheral memory map */
<> 144:ef7eb2e8f9f7 664 /******************************************************************************/
<> 144:ef7eb2e8f9f7 665 /** @addtogroup Renesas_RZ_A1_MemoryMap Renesas_RZ_A1 Memory Mapping
<> 144:ef7eb2e8f9f7 666 @{
<> 144:ef7eb2e8f9f7 667 */
<> 144:ef7eb2e8f9f7 668
<> 144:ef7eb2e8f9f7 669 /* R7S72100 CPU board */
<> 144:ef7eb2e8f9f7 670 #define Renesas_RZ_A1_NORFLASH_BASE0 (0x00000000UL) /*!< (FLASH0 ) Base Address */
<> 144:ef7eb2e8f9f7 671 #define Renesas_RZ_A1_NORFLASH_BASE1 (0x04000000UL) /*!< (FLASH1 ) Base Address */
<> 144:ef7eb2e8f9f7 672 #define Renesas_RZ_A1_SDRAM_BASE0 (0x08000000UL) /*!< (SDRAM0 ) Base Address */
<> 144:ef7eb2e8f9f7 673 #define Renesas_RZ_A1_SDRAM_BASE1 (0x0C000000UL) /*!< (SDRAM1 ) Base Address */
<> 144:ef7eb2e8f9f7 674 #define Renesas_RZ_A1_USER_AREA0 (0x10000000UL) /*!< (USER0 ) Base Address */
<> 144:ef7eb2e8f9f7 675 #define Renesas_RZ_A1_USER_AREA1 (0x14000000UL) /*!< (USER1 ) Base Address */
<> 144:ef7eb2e8f9f7 676 #define Renesas_RZ_A1_SPI_IO0 (0x18000000UL) /*!< (SPI_IO0 ) Base Address */
<> 144:ef7eb2e8f9f7 677 #define Renesas_RZ_A1_SPI_IO1 (0x1C000000UL) /*!< (SPI_IO1 ) Base Address */
<> 144:ef7eb2e8f9f7 678 #define Renesas_RZ_A1_ONCHIP_SRAM_BASE (0x20000000UL) /*!< (SRAM_OC ) Base Address */
<> 144:ef7eb2e8f9f7 679 #define Renesas_RZ_A1_SPI_MIO_BASE (0x3fe00000UL) /*!< (SPI_MIO ) Base Address */
<> 144:ef7eb2e8f9f7 680 #define Renesas_RZ_A1_BSC_BASE (0x3ff00000UL) /*!< (BSC ) Base Address */
<> 144:ef7eb2e8f9f7 681 #define Renesas_RZ_A1_PERIPH_BASE0 (0xe8000000UL) /*!< (PERIPH0 ) Base Address */
<> 144:ef7eb2e8f9f7 682 #define Renesas_RZ_A1_PERIPH_BASE1 (0xfcf00000UL) /*!< (PERIPH1 ) Base Address */
<> 144:ef7eb2e8f9f7 683 #define Renesas_RZ_A1_GIC_DISTRIBUTOR_BASE (0xe8201000UL) /*!< (GIC DIST ) Base Address */
<> 144:ef7eb2e8f9f7 684 #define Renesas_RZ_A1_GIC_INTERFACE_BASE (0xe8202000UL) /*!< (GIC CPU IF) Base Address */
<> 144:ef7eb2e8f9f7 685 #define Renesas_RZ_A1_PL310_BASE (0x3ffff000UL) /*!< (PL310 ) Base Address */
<> 144:ef7eb2e8f9f7 686 #define Renesas_RZ_A1_ONCHIP_SRAM_NC_BASE (0x60000000UL) /*!< (SRAM_OC ) Base Address */
<> 144:ef7eb2e8f9f7 687
<> 144:ef7eb2e8f9f7 688 //Following macros define the descriptors and attributes used to define the Renesas_RZ_A1 MMU flat-map
<> 144:ef7eb2e8f9f7 689 //Sect_Normal. Outer & inner wb/wa, non-shareable, executable, rw, domain 0.
<> 144:ef7eb2e8f9f7 690 #define section_normal(descriptor_l1, region) region.rg_t = SECTION; \
<> 144:ef7eb2e8f9f7 691 region.domain = 0x0; \
<> 144:ef7eb2e8f9f7 692 region.e_t = ECC_DISABLED; \
<> 144:ef7eb2e8f9f7 693 region.g_t = GLOBAL; \
<> 144:ef7eb2e8f9f7 694 region.inner_norm_t = WB_WA; \
<> 144:ef7eb2e8f9f7 695 region.outer_norm_t = WB_WA; \
<> 144:ef7eb2e8f9f7 696 region.mem_t = NORMAL; \
<> 144:ef7eb2e8f9f7 697 region.sec_t = NON_SECURE; \
<> 144:ef7eb2e8f9f7 698 region.xn_t = EXECUTE; \
<> 144:ef7eb2e8f9f7 699 region.priv_t = RW; \
<> 144:ef7eb2e8f9f7 700 region.user_t = RW; \
<> 144:ef7eb2e8f9f7 701 region.sh_t = NON_SHARED; \
<> 144:ef7eb2e8f9f7 702 __get_section_descriptor(&descriptor_l1, region);
<> 144:ef7eb2e8f9f7 703
<> 144:ef7eb2e8f9f7 704 #define section_normal_nc(descriptor_l1, region) region.rg_t = SECTION; \
<> 144:ef7eb2e8f9f7 705 region.domain = 0x0; \
<> 144:ef7eb2e8f9f7 706 region.e_t = ECC_DISABLED; \
<> 144:ef7eb2e8f9f7 707 region.g_t = GLOBAL; \
<> 144:ef7eb2e8f9f7 708 region.inner_norm_t = NON_CACHEABLE; \
<> 144:ef7eb2e8f9f7 709 region.outer_norm_t = NON_CACHEABLE; \
<> 144:ef7eb2e8f9f7 710 region.mem_t = NORMAL; \
<> 144:ef7eb2e8f9f7 711 region.sec_t = SECURE; \
<> 144:ef7eb2e8f9f7 712 region.xn_t = EXECUTE; \
<> 144:ef7eb2e8f9f7 713 region.priv_t = RW; \
<> 144:ef7eb2e8f9f7 714 region.user_t = RW; \
<> 144:ef7eb2e8f9f7 715 region.sh_t = NON_SHARED; \
<> 144:ef7eb2e8f9f7 716 __get_section_descriptor(&descriptor_l1, region);
<> 144:ef7eb2e8f9f7 717
<> 144:ef7eb2e8f9f7 718 //Sect_Normal_Cod. Outer & inner wb/wa, non-shareable, executable, ro, domain 0.
<> 144:ef7eb2e8f9f7 719 #define section_normal_cod(descriptor_l1, region) region.rg_t = SECTION; \
<> 144:ef7eb2e8f9f7 720 region.domain = 0x0; \
<> 144:ef7eb2e8f9f7 721 region.e_t = ECC_DISABLED; \
<> 144:ef7eb2e8f9f7 722 region.g_t = GLOBAL; \
<> 144:ef7eb2e8f9f7 723 region.inner_norm_t = WB_WA; \
<> 144:ef7eb2e8f9f7 724 region.outer_norm_t = WB_WA; \
<> 144:ef7eb2e8f9f7 725 region.mem_t = NORMAL; \
<> 144:ef7eb2e8f9f7 726 region.sec_t = NON_SECURE; \
<> 144:ef7eb2e8f9f7 727 region.xn_t = EXECUTE; \
<> 144:ef7eb2e8f9f7 728 region.priv_t = READ; \
<> 144:ef7eb2e8f9f7 729 region.user_t = READ; \
<> 144:ef7eb2e8f9f7 730 region.sh_t = NON_SHARED; \
<> 144:ef7eb2e8f9f7 731 __get_section_descriptor(&descriptor_l1, region);
<> 144:ef7eb2e8f9f7 732
<> 144:ef7eb2e8f9f7 733 //Sect_Normal_RO. Sect_Normal_Cod, but not executable
<> 144:ef7eb2e8f9f7 734 #define section_normal_ro(descriptor_l1, region) region.rg_t = SECTION; \
<> 144:ef7eb2e8f9f7 735 region.domain = 0x0; \
<> 144:ef7eb2e8f9f7 736 region.e_t = ECC_DISABLED; \
<> 144:ef7eb2e8f9f7 737 region.g_t = GLOBAL; \
<> 144:ef7eb2e8f9f7 738 region.inner_norm_t = WB_WA; \
<> 144:ef7eb2e8f9f7 739 region.outer_norm_t = WB_WA; \
<> 144:ef7eb2e8f9f7 740 region.mem_t = NORMAL; \
<> 144:ef7eb2e8f9f7 741 region.sec_t = NON_SECURE; \
<> 144:ef7eb2e8f9f7 742 region.xn_t = NON_EXECUTE; \
<> 144:ef7eb2e8f9f7 743 region.priv_t = READ; \
<> 144:ef7eb2e8f9f7 744 region.user_t = READ; \
<> 144:ef7eb2e8f9f7 745 region.sh_t = NON_SHARED; \
<> 144:ef7eb2e8f9f7 746 __get_section_descriptor(&descriptor_l1, region);
<> 144:ef7eb2e8f9f7 747
<> 144:ef7eb2e8f9f7 748 //Sect_Normal_RW. Sect_Normal_Cod, but writeable and not executable
<> 144:ef7eb2e8f9f7 749 #define section_normal_rw(descriptor_l1, region) region.rg_t = SECTION; \
<> 144:ef7eb2e8f9f7 750 region.domain = 0x0; \
<> 144:ef7eb2e8f9f7 751 region.e_t = ECC_DISABLED; \
<> 144:ef7eb2e8f9f7 752 region.g_t = GLOBAL; \
<> 144:ef7eb2e8f9f7 753 region.inner_norm_t = WB_WA; \
<> 144:ef7eb2e8f9f7 754 region.outer_norm_t = WB_WA; \
<> 144:ef7eb2e8f9f7 755 region.mem_t = NORMAL; \
<> 144:ef7eb2e8f9f7 756 region.sec_t = NON_SECURE; \
<> 144:ef7eb2e8f9f7 757 region.xn_t = EXECUTE; \
<> 144:ef7eb2e8f9f7 758 region.priv_t = RW; \
<> 144:ef7eb2e8f9f7 759 region.user_t = RW; \
<> 144:ef7eb2e8f9f7 760 region.sh_t = NON_SHARED; \
<> 144:ef7eb2e8f9f7 761 __get_section_descriptor(&descriptor_l1, region);
<> 144:ef7eb2e8f9f7 762
<> 144:ef7eb2e8f9f7 763 //Sect_SO. Strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0
<> 144:ef7eb2e8f9f7 764 #define section_so(descriptor_l1, region) region.rg_t = SECTION; \
<> 144:ef7eb2e8f9f7 765 region.domain = 0x0; \
<> 144:ef7eb2e8f9f7 766 region.e_t = ECC_DISABLED; \
<> 144:ef7eb2e8f9f7 767 region.g_t = GLOBAL; \
<> 144:ef7eb2e8f9f7 768 region.inner_norm_t = NON_CACHEABLE; \
<> 144:ef7eb2e8f9f7 769 region.outer_norm_t = NON_CACHEABLE; \
<> 144:ef7eb2e8f9f7 770 region.mem_t = STRONGLY_ORDERED; \
<> 144:ef7eb2e8f9f7 771 region.sec_t = SECURE; \
<> 144:ef7eb2e8f9f7 772 region.xn_t = NON_EXECUTE; \
<> 144:ef7eb2e8f9f7 773 region.priv_t = RW; \
<> 144:ef7eb2e8f9f7 774 region.user_t = RW; \
<> 144:ef7eb2e8f9f7 775 region.sh_t = NON_SHARED; \
<> 144:ef7eb2e8f9f7 776 __get_section_descriptor(&descriptor_l1, region);
<> 144:ef7eb2e8f9f7 777
<> 144:ef7eb2e8f9f7 778 //Sect_Device_RO. Device, non-shareable, non-executable, ro, domain 0, base addr 0
<> 144:ef7eb2e8f9f7 779 #define section_device_ro(descriptor_l1, region) region.rg_t = SECTION; \
<> 144:ef7eb2e8f9f7 780 region.domain = 0x0; \
<> 144:ef7eb2e8f9f7 781 region.e_t = ECC_DISABLED; \
<> 144:ef7eb2e8f9f7 782 region.g_t = GLOBAL; \
<> 144:ef7eb2e8f9f7 783 region.inner_norm_t = NON_CACHEABLE; \
<> 144:ef7eb2e8f9f7 784 region.outer_norm_t = NON_CACHEABLE; \
<> 144:ef7eb2e8f9f7 785 region.mem_t = STRONGLY_ORDERED; \
<> 144:ef7eb2e8f9f7 786 region.sec_t = SECURE; \
<> 144:ef7eb2e8f9f7 787 region.xn_t = NON_EXECUTE; \
<> 144:ef7eb2e8f9f7 788 region.priv_t = READ; \
<> 144:ef7eb2e8f9f7 789 region.user_t = READ; \
<> 144:ef7eb2e8f9f7 790 region.sh_t = NON_SHARED; \
<> 144:ef7eb2e8f9f7 791 __get_section_descriptor(&descriptor_l1, region);
<> 144:ef7eb2e8f9f7 792
<> 144:ef7eb2e8f9f7 793 //Sect_Device_RW. Sect_Device_RO, but writeable
<> 144:ef7eb2e8f9f7 794 #define section_device_rw(descriptor_l1, region) region.rg_t = SECTION; \
<> 144:ef7eb2e8f9f7 795 region.domain = 0x0; \
<> 144:ef7eb2e8f9f7 796 region.e_t = ECC_DISABLED; \
<> 144:ef7eb2e8f9f7 797 region.g_t = GLOBAL; \
<> 144:ef7eb2e8f9f7 798 region.inner_norm_t = NON_CACHEABLE; \
<> 144:ef7eb2e8f9f7 799 region.outer_norm_t = NON_CACHEABLE; \
<> 144:ef7eb2e8f9f7 800 region.mem_t = STRONGLY_ORDERED; \
<> 144:ef7eb2e8f9f7 801 region.sec_t = SECURE; \
<> 144:ef7eb2e8f9f7 802 region.xn_t = NON_EXECUTE; \
<> 144:ef7eb2e8f9f7 803 region.priv_t = RW; \
<> 144:ef7eb2e8f9f7 804 region.user_t = RW; \
<> 144:ef7eb2e8f9f7 805 region.sh_t = NON_SHARED; \
<> 144:ef7eb2e8f9f7 806 __get_section_descriptor(&descriptor_l1, region);
<> 144:ef7eb2e8f9f7 807 //Page_4k_Device_RW. Shared device, not executable, rw, domain 0
<> 144:ef7eb2e8f9f7 808 #define page4k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_4k; \
<> 144:ef7eb2e8f9f7 809 region.domain = 0x0; \
<> 144:ef7eb2e8f9f7 810 region.e_t = ECC_DISABLED; \
<> 144:ef7eb2e8f9f7 811 region.g_t = GLOBAL; \
<> 144:ef7eb2e8f9f7 812 region.inner_norm_t = NON_CACHEABLE; \
<> 144:ef7eb2e8f9f7 813 region.outer_norm_t = NON_CACHEABLE; \
<> 144:ef7eb2e8f9f7 814 region.mem_t = SHARED_DEVICE; \
<> 144:ef7eb2e8f9f7 815 region.sec_t = SECURE; \
<> 144:ef7eb2e8f9f7 816 region.xn_t = NON_EXECUTE; \
<> 144:ef7eb2e8f9f7 817 region.priv_t = RW; \
<> 144:ef7eb2e8f9f7 818 region.user_t = RW; \
<> 144:ef7eb2e8f9f7 819 region.sh_t = NON_SHARED; \
<> 144:ef7eb2e8f9f7 820 __get_page_descriptor(&descriptor_l1, &descriptor_l2, region);
<> 144:ef7eb2e8f9f7 821
<> 144:ef7eb2e8f9f7 822 //Page_64k_Device_RW. Shared device, not executable, rw, domain 0
<> 144:ef7eb2e8f9f7 823 #define page64k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_64k; \
<> 144:ef7eb2e8f9f7 824 region.domain = 0x0; \
<> 144:ef7eb2e8f9f7 825 region.e_t = ECC_DISABLED; \
<> 144:ef7eb2e8f9f7 826 region.g_t = GLOBAL; \
<> 144:ef7eb2e8f9f7 827 region.inner_norm_t = NON_CACHEABLE; \
<> 144:ef7eb2e8f9f7 828 region.outer_norm_t = NON_CACHEABLE; \
<> 144:ef7eb2e8f9f7 829 region.mem_t = SHARED_DEVICE; \
<> 144:ef7eb2e8f9f7 830 region.sec_t = SECURE; \
<> 144:ef7eb2e8f9f7 831 region.xn_t = NON_EXECUTE; \
<> 144:ef7eb2e8f9f7 832 region.priv_t = RW; \
<> 144:ef7eb2e8f9f7 833 region.user_t = RW; \
<> 144:ef7eb2e8f9f7 834 region.sh_t = NON_SHARED; \
<> 144:ef7eb2e8f9f7 835 __get_page_descriptor(&descriptor_l1, &descriptor_l2, region);
<> 144:ef7eb2e8f9f7 836
<> 144:ef7eb2e8f9f7 837
<> 144:ef7eb2e8f9f7 838 /*@}*/ /* end of group Renesas_RZ_A1_MemoryMap */
<> 144:ef7eb2e8f9f7 839
<> 144:ef7eb2e8f9f7 840 /******************************************************************************/
<> 144:ef7eb2e8f9f7 841 /* Clock Settings */
<> 144:ef7eb2e8f9f7 842 /******************************************************************************/
<> 144:ef7eb2e8f9f7 843 /** @addtogroup Renesas_RZ_A1_H_Clocks Renesas_RZ_A1 Clock definitions
<> 144:ef7eb2e8f9f7 844 @{
<> 144:ef7eb2e8f9f7 845 */
<> 144:ef7eb2e8f9f7 846
<> 144:ef7eb2e8f9f7 847 /*
<> 144:ef7eb2e8f9f7 848 * Clock Mode 0 settings
<> 144:ef7eb2e8f9f7 849 * SW1-4(MD_CLK):ON
<> 144:ef7eb2e8f9f7 850 * SW1-5(MD_CLKS):ON
<> 144:ef7eb2e8f9f7 851 * FRQCR=0x1035
<> 144:ef7eb2e8f9f7 852 * CLKEN2 = 0b - unstable
<> 144:ef7eb2e8f9f7 853 * CLKEN[1:0]=01b - Output, Low, Low
<> 144:ef7eb2e8f9f7 854 * IFC[1:0] =00b - CPU clock is 1/1 PLL clock
<> 144:ef7eb2e8f9f7 855 * FRQCR2=0x0001
<> 144:ef7eb2e8f9f7 856 * GFC[1:0] =01b - Graphic clock is 2/3 bus clock
<> 144:ef7eb2e8f9f7 857 */
<> 144:ef7eb2e8f9f7 858 #define CM0_RENESAS_RZ_A1_CLKIN ( 13333333u)
<> 144:ef7eb2e8f9f7 859 #define CM0_RENESAS_RZ_A1_CLKO ( 66666666u)
<> 144:ef7eb2e8f9f7 860 #define CM0_RENESAS_RZ_A1_I_CLK (400000000u)
<> 144:ef7eb2e8f9f7 861 #define CM0_RENESAS_RZ_A1_G_CLK (266666666u)
<> 144:ef7eb2e8f9f7 862 #define CM0_RENESAS_RZ_A1_B_CLK (133333333u)
<> 144:ef7eb2e8f9f7 863 #define CM0_RENESAS_RZ_A1_P1_CLK ( 66666666u)
<> 144:ef7eb2e8f9f7 864 #define CM0_RENESAS_RZ_A1_P0_CLK ( 33333333u)
<> 144:ef7eb2e8f9f7 865
<> 144:ef7eb2e8f9f7 866 /*
<> 144:ef7eb2e8f9f7 867 * Clock Mode 1 settings
<> 144:ef7eb2e8f9f7 868 * SW1-4(MD_CLK):OFF
<> 144:ef7eb2e8f9f7 869 * SW1-5(MD_CLKS):ON
<> 144:ef7eb2e8f9f7 870 * FRQCR=0x1335
<> 144:ef7eb2e8f9f7 871 * CLKEN2 = 0b - unstable
<> 144:ef7eb2e8f9f7 872 * CLKEN[1:0]=01b - Output, Low, Low
<> 144:ef7eb2e8f9f7 873 * IFC[1:0] =11b - CPU clock is 1/3 PLL clock
<> 144:ef7eb2e8f9f7 874 * FRQCR2=0x0003
<> 144:ef7eb2e8f9f7 875 * GFC[1:0] =11b - graphic clock is 1/3 bus clock
<> 144:ef7eb2e8f9f7 876 */
<> 144:ef7eb2e8f9f7 877 #define CM1_RENESAS_RZ_A1_CLKIN ( 48000000u)
<> 144:ef7eb2e8f9f7 878 #define CM1_RENESAS_RZ_A1_CLKO ( 64000000u)
<> 144:ef7eb2e8f9f7 879 #define CM1_RENESAS_RZ_A1_I_CLK (128000000u)
<> 144:ef7eb2e8f9f7 880 #define CM1_RENESAS_RZ_A1_G_CLK (128000000u)
<> 144:ef7eb2e8f9f7 881 #define CM1_RENESAS_RZ_A1_B_CLK (128000000u)
<> 144:ef7eb2e8f9f7 882 #define CM1_RENESAS_RZ_A1_P1_CLK ( 64000000u)
<> 144:ef7eb2e8f9f7 883 #define CM1_RENESAS_RZ_A1_P0_CLK ( 32000000u)
<> 144:ef7eb2e8f9f7 884
<> 144:ef7eb2e8f9f7 885 /*@}*/ /* end of group Renesas_RZ_A1_Clocks */
<> 144:ef7eb2e8f9f7 886
<> 144:ef7eb2e8f9f7 887 /******************************************************************************/
<> 144:ef7eb2e8f9f7 888 /* CPG Settings */
<> 144:ef7eb2e8f9f7 889 /******************************************************************************/
<> 144:ef7eb2e8f9f7 890 /** @addtogroup Renesas_RZ_A1_H_CPG Renesas_RZ_A1 CPG Bit definitions
<> 144:ef7eb2e8f9f7 891 @{
<> 144:ef7eb2e8f9f7 892 */
<> 144:ef7eb2e8f9f7 893
<> 144:ef7eb2e8f9f7 894 #define CPG_FRQCR_SHIFT_CKOEN2 (14)
<> 144:ef7eb2e8f9f7 895 #define CPG_FRQCR_BIT_CKOEN2 (0x1 << CPG_FRQCR_SHIFT_CKOEN2)
<> 144:ef7eb2e8f9f7 896 #define CPG_FRQCR_SHIFT_CKOEN0 (12)
<> 144:ef7eb2e8f9f7 897 #define CPG_FRQCR_BITS_CKOEN0 (0x3 << CPG_FRQCR_SHIFT_CKOEN0)
<> 144:ef7eb2e8f9f7 898 #define CPG_FRQCR_SHIFT_IFC (8)
<> 144:ef7eb2e8f9f7 899 #define CPG_FRQCR_BITS_IFC (0x3 << CPG_FRQCR_SHIFT_IFC)
<> 144:ef7eb2e8f9f7 900
<> 144:ef7eb2e8f9f7 901 #define CPG_FRQCR2_SHIFT_GFC (0)
<> 144:ef7eb2e8f9f7 902 #define CPG_FRQCR2_BITS_GFC (0x3 << CPG_FRQCR2_SHIFT_GFC)
<> 144:ef7eb2e8f9f7 903
<> 144:ef7eb2e8f9f7 904
<> 144:ef7eb2e8f9f7 905 #define CPG_STBCR1_BIT_STBY (0x80u)
<> 144:ef7eb2e8f9f7 906 #define CPG_STBCR1_BIT_DEEP (0x40u)
<> 144:ef7eb2e8f9f7 907 #define CPG_STBCR2_BIT_HIZ (0x80u)
<> 144:ef7eb2e8f9f7 908 #define CPG_STBCR2_BIT_MSTP20 (0x01u) /* CoreSight */
<> 144:ef7eb2e8f9f7 909 #define CPG_STBCR3_BIT_MSTP37 (0x80u) /* IEBus */
<> 144:ef7eb2e8f9f7 910 #define CPG_STBCR3_BIT_MSTP36 (0x40u) /* IrDA */
<> 144:ef7eb2e8f9f7 911 #define CPG_STBCR3_BIT_MSTP35 (0x20u) /* LIN0 */
<> 144:ef7eb2e8f9f7 912 #define CPG_STBCR3_BIT_MSTP34 (0x10u) /* LIN1 */
<> 144:ef7eb2e8f9f7 913 #define CPG_STBCR3_BIT_MSTP33 (0x08u) /* Multi-Function Timer */
<> 144:ef7eb2e8f9f7 914 #define CPG_STBCR3_BIT_MSTP32 (0x04u) /* CAN */
<> 144:ef7eb2e8f9f7 915 #define CPG_STBCR3_BIT_MSTP30 (0x01u) /* Motor Control PWM Timer */
<> 144:ef7eb2e8f9f7 916 #define CPG_STBCR4_BIT_MSTP47 (0x80u) /* SCIF0 */
<> 144:ef7eb2e8f9f7 917 #define CPG_STBCR4_BIT_MSTP46 (0x40u) /* SCIF1 */
<> 144:ef7eb2e8f9f7 918 #define CPG_STBCR4_BIT_MSTP45 (0x20u) /* SCIF2 */
<> 144:ef7eb2e8f9f7 919 #define CPG_STBCR4_BIT_MSTP44 (0x10u) /* SCIF3 */
<> 144:ef7eb2e8f9f7 920 #define CPG_STBCR4_BIT_MSTP43 (0x08u) /* SCIF4 */
<> 144:ef7eb2e8f9f7 921 #define CPG_STBCR4_BIT_MSTP42 (0x04u) /* SCIF5 */
<> 144:ef7eb2e8f9f7 922 #define CPG_STBCR4_BIT_MSTP41 (0x02u) /* SCIF6 */
<> 144:ef7eb2e8f9f7 923 #define CPG_STBCR4_BIT_MSTP40 (0x01u) /* SCIF7 */
<> 144:ef7eb2e8f9f7 924 #define CPG_STBCR5_BIT_MSTP57 (0x80u) /* SCI0 */
<> 144:ef7eb2e8f9f7 925 #define CPG_STBCR5_BIT_MSTP56 (0x40u) /* SCI1 */
<> 144:ef7eb2e8f9f7 926 #define CPG_STBCR5_BIT_MSTP55 (0x20u) /* Sound Generator0 */
<> 144:ef7eb2e8f9f7 927 #define CPG_STBCR5_BIT_MSTP54 (0x10u) /* Sound Generator1 */
<> 144:ef7eb2e8f9f7 928 #define CPG_STBCR5_BIT_MSTP53 (0x08u) /* Sound Generator2 */
<> 144:ef7eb2e8f9f7 929 #define CPG_STBCR5_BIT_MSTP52 (0x04u) /* Sound Generator3 */
<> 144:ef7eb2e8f9f7 930 #define CPG_STBCR5_BIT_MSTP51 (0x02u) /* OSTM0 */
<> 144:ef7eb2e8f9f7 931 #define CPG_STBCR5_BIT_MSTP50 (0x01u) /* OSTM1 */
<> 144:ef7eb2e8f9f7 932 #define CPG_STBCR6_BIT_MSTP67 (0x80u) /* General A/D Comvertor */
<> 144:ef7eb2e8f9f7 933 #define CPG_STBCR6_BIT_MSTP66 (0x40u) /* Capture Engine */
<> 144:ef7eb2e8f9f7 934 #define CPG_STBCR6_BIT_MSTP65 (0x20u) /* Display out comparison0 */
<> 144:ef7eb2e8f9f7 935 #define CPG_STBCR6_BIT_MSTP64 (0x10u) /* Display out comparison1 */
<> 144:ef7eb2e8f9f7 936 #define CPG_STBCR6_BIT_MSTP63 (0x08u) /* Dynamic Range Compalator0 */
<> 144:ef7eb2e8f9f7 937 #define CPG_STBCR6_BIT_MSTP62 (0x04u) /* Dynamic Range Compalator1 */
<> 144:ef7eb2e8f9f7 938 #define CPG_STBCR6_BIT_MSTP61 (0x02u) /* JPEG Decoder */
<> 144:ef7eb2e8f9f7 939 #define CPG_STBCR6_BIT_MSTP60 (0x01u) /* Realtime Clock */
<> 144:ef7eb2e8f9f7 940 #define CPG_STBCR7_BIT_MSTP77 (0x80u) /* Video Decoder0 */
<> 144:ef7eb2e8f9f7 941 #define CPG_STBCR7_BIT_MSTP76 (0x40u) /* Video Decoder1 */
<> 144:ef7eb2e8f9f7 942 #define CPG_STBCR7_BIT_MSTP74 (0x10u) /* Ether */
<> 144:ef7eb2e8f9f7 943 #define CPG_STBCR7_BIT_MSTP73 (0x04u) /* NAND Flash Memory Controller */
<> 144:ef7eb2e8f9f7 944 #define CPG_STBCR7_BIT_MSTP71 (0x02u) /* USB0 */
<> 144:ef7eb2e8f9f7 945 #define CPG_STBCR7_BIT_MSTP70 (0x01u) /* USB1 */
<> 144:ef7eb2e8f9f7 946 #define CPG_STBCR8_BIT_MSTP87 (0x80u) /* IMR-LS2_0 */
<> 144:ef7eb2e8f9f7 947 #define CPG_STBCR8_BIT_MSTP86 (0x40u) /* IMR-LS2_1 */
<> 144:ef7eb2e8f9f7 948 #define CPG_STBCR8_BIT_MSTP85 (0x20u) /* IMR-LSD */
<> 144:ef7eb2e8f9f7 949 #define CPG_STBCR8_BIT_MSTP84 (0x10u) /* MMC Host Interface */
<> 144:ef7eb2e8f9f7 950 #define CPG_STBCR8_BIT_MSTP83 (0x08u) /* MediaLB */
<> 144:ef7eb2e8f9f7 951 #define CPG_STBCR8_BIT_MSTP81 (0x02u) /* SCUX */
<> 144:ef7eb2e8f9f7 952 #define CPG_STBCR9_BIT_MSTP97 (0x80u) /* RIIC0 */
<> 144:ef7eb2e8f9f7 953 #define CPG_STBCR9_BIT_MSTP96 (0x40u) /* RIIC1 */
<> 144:ef7eb2e8f9f7 954 #define CPG_STBCR9_BIT_MSTP95 (0x20u) /* RIIC2 */
<> 144:ef7eb2e8f9f7 955 #define CPG_STBCR9_BIT_MSTP94 (0x10u) /* RIIC3 */
<> 144:ef7eb2e8f9f7 956 #define CPG_STBCR9_BIT_MSTP93 (0x08u) /* SPI Multi I/O Bus Controller0 */
<> 144:ef7eb2e8f9f7 957 #define CPG_STBCR9_BIT_MSTP92 (0x04u) /* SPI Multi I/O Bus Controller1 */
<> 144:ef7eb2e8f9f7 958 #define CPG_STBCR9_BIT_MSTP91 (0x02u) /* VDC5_0 */
<> 144:ef7eb2e8f9f7 959 #define CPG_STBCR9_BIT_MSTP90 (0x01u) /* VDC5_1 */
<> 144:ef7eb2e8f9f7 960 #define CPG_STBCR10_BIT_MSTP107 (0x80u) /* RSPI0 */
<> 144:ef7eb2e8f9f7 961 #define CPG_STBCR10_BIT_MSTP106 (0x40u) /* RSPI1 */
<> 144:ef7eb2e8f9f7 962 #define CPG_STBCR10_BIT_MSTP105 (0x20u) /* RSPI2 */
<> 144:ef7eb2e8f9f7 963 #define CPG_STBCR10_BIT_MSTP104 (0x10u) /* RSPI3 */
<> 144:ef7eb2e8f9f7 964 #define CPG_STBCR10_BIT_MSTP103 (0x08u) /* RSPI4 */
<> 144:ef7eb2e8f9f7 965 #define CPG_STBCR10_BIT_MSTP102 (0x04u) /* ROMDEC */
<> 144:ef7eb2e8f9f7 966 #define CPG_STBCR10_BIT_MSTP101 (0x02u) /* SPIDF */
<> 144:ef7eb2e8f9f7 967 #define CPG_STBCR10_BIT_MSTP100 (0x01u) /* OpenVG */
<> 144:ef7eb2e8f9f7 968 #define CPG_STBCR11_BIT_MSTP115 (0x20u) /* SSIF0 */
<> 144:ef7eb2e8f9f7 969 #define CPG_STBCR11_BIT_MSTP114 (0x10u) /* SSIF1 */
<> 144:ef7eb2e8f9f7 970 #define CPG_STBCR11_BIT_MSTP113 (0x08u) /* SSIF2 */
<> 144:ef7eb2e8f9f7 971 #define CPG_STBCR11_BIT_MSTP112 (0x04u) /* SSIF3 */
<> 144:ef7eb2e8f9f7 972 #define CPG_STBCR11_BIT_MSTP111 (0x02u) /* SSIF4 */
<> 144:ef7eb2e8f9f7 973 #define CPG_STBCR11_BIT_MSTP110 (0x01u) /* SSIF5 */
<> 144:ef7eb2e8f9f7 974 #define CPG_STBCR12_BIT_MSTP123 (0x08u) /* SD Host Interface00 */
<> 144:ef7eb2e8f9f7 975 #define CPG_STBCR12_BIT_MSTP122 (0x04u) /* SD Host Interface01 */
<> 144:ef7eb2e8f9f7 976 #define CPG_STBCR12_BIT_MSTP121 (0x02u) /* SD Host Interface10 */
<> 144:ef7eb2e8f9f7 977 #define CPG_STBCR12_BIT_MSTP120 (0x01u) /* SD Host Interface11 */
<> 144:ef7eb2e8f9f7 978 #define CPG_CSTBCR1_BIT_CMSTP11 (0x02u) /* PFV */
<> 144:ef7eb2e8f9f7 979 #define CPG_SWRSTCR1_BIT_AXTALE (0x80u) /* AUDIO_X1 */
<> 144:ef7eb2e8f9f7 980 #define CPG_SWRSTCR1_BIT_SRST16 (0x40u) /* SSIF0 */
<> 144:ef7eb2e8f9f7 981 #define CPG_SWRSTCR1_BIT_SRST15 (0x20u) /* SSIF1 */
<> 144:ef7eb2e8f9f7 982 #define CPG_SWRSTCR1_BIT_SRST14 (0x10u) /* SSIF2 */
<> 144:ef7eb2e8f9f7 983 #define CPG_SWRSTCR1_BIT_SRST13 (0x08u) /* SSIF3 */
<> 144:ef7eb2e8f9f7 984 #define CPG_SWRSTCR1_BIT_SRST12 (0x04u) /* SSIF4 */
<> 144:ef7eb2e8f9f7 985 #define CPG_SWRSTCR1_BIT_SRST11 (0x02u) /* SSIF5 */
<> 144:ef7eb2e8f9f7 986 #define CPG_SWRSTCR2_BIT_SRST27 (0x80u) /* Display out comparison0 */
<> 144:ef7eb2e8f9f7 987 #define CPG_SWRSTCR2_BIT_SRST26 (0x40u) /* Display out comparison1 */
<> 144:ef7eb2e8f9f7 988 #define CPG_SWRSTCR2_BIT_SRST25 (0x20u) /* Dynamic Range Compalator0 */
<> 144:ef7eb2e8f9f7 989 #define CPG_SWRSTCR2_BIT_SRST24 (0x10u) /* Dynamic Range Compalator1 */
<> 144:ef7eb2e8f9f7 990 #define CPG_SWRSTCR2_BIT_SRST23 (0x08u) /* VDC5_0 */
<> 144:ef7eb2e8f9f7 991 #define CPG_SWRSTCR2_BIT_SRST22 (0x04u) /* VDC5_1 */
<> 144:ef7eb2e8f9f7 992 #define CPG_SWRSTCR2_BIT_SRST21 (0x02u) /* JPEG Decoder */
<> 144:ef7eb2e8f9f7 993 #define CPG_SWRSTCR3_BIT_SRST36 (0x40u) /* DMA */
<> 144:ef7eb2e8f9f7 994 #define CPG_SWRSTCR3_BIT_SRST35 (0x20u) /* IMR-LS2_0 */
<> 144:ef7eb2e8f9f7 995 #define CPG_SWRSTCR3_BIT_SRST34 (0x10u) /* IMR-LS2_1 */
<> 144:ef7eb2e8f9f7 996 #define CPG_SWRSTCR3_BIT_SRST33 (0x08u) /* IMR-LSD? */
<> 144:ef7eb2e8f9f7 997 #define CPG_SWRSTCR3_BIT_SRST32 (0x04u) /* OpenVG */
<> 144:ef7eb2e8f9f7 998 #define CPG_SWRSTCR3_BIT_SRST31 (0x02u) /* Capture Engine */
<> 144:ef7eb2e8f9f7 999 #define CPG_SWRSTCR4_BIT_SRST41 (0x02u) /* Video Decoder0 */
<> 144:ef7eb2e8f9f7 1000 #define CPG_SWRSTCR4_BIT_SRST40 (0x01u) /* Video Decoder1 */
<> 144:ef7eb2e8f9f7 1001 #define CPG_SYSCR1_BIT_VRAME4 (0x10u) /* VRAM E Page4 */
<> 144:ef7eb2e8f9f7 1002 #define CPG_SYSCR1_BIT_VRAME3 (0x08u) /* VRAM E Page3 */
<> 144:ef7eb2e8f9f7 1003 #define CPG_SYSCR1_BIT_VRAME2 (0x04u) /* VRAM E Page2 */
<> 144:ef7eb2e8f9f7 1004 #define CPG_SYSCR1_BIT_VRAME1 (0x02u) /* VRAM E Page1 */
<> 144:ef7eb2e8f9f7 1005 #define CPG_SYSCR1_BIT_VRAME0 (0x01u) /* VRAM E Page0 */
<> 144:ef7eb2e8f9f7 1006 #define CPG_SYSCR2_BIT_VRAMWE4 (0x10u) /* VRAM WE Page4 */
<> 144:ef7eb2e8f9f7 1007 #define CPG_SYSCR2_BIT_VRAMWE3 (0x08u) /* VRAM WE Page3 */
<> 144:ef7eb2e8f9f7 1008 #define CPG_SYSCR2_BIT_VRAMWE2 (0x04u) /* VRAM WE Page2 */
<> 144:ef7eb2e8f9f7 1009 #define CPG_SYSCR2_BIT_VRAMWE1 (0x02u) /* VRAM WE Page1 */
<> 144:ef7eb2e8f9f7 1010 #define CPG_SYSCR2_BIT_VRAMWE0 (0x01u) /* VRAM WE Page0 */
<> 144:ef7eb2e8f9f7 1011 #define CPG_SYSCR3_BIT_RRAMWE3 (0x08u) /* RRAM WE Page3 */
<> 144:ef7eb2e8f9f7 1012 #define CPG_SYSCR3_BIT_RRAMWE2 (0x04u) /* RRAM WE Page2 */
<> 144:ef7eb2e8f9f7 1013 #define CPG_SYSCR3_BIT_RRAMWE1 (0x02u) /* RRAM WE Page1 */
<> 144:ef7eb2e8f9f7 1014 #define CPG_SYSCR3_BIT_RRAMWE0 (0x01u) /* RRAM WE Page0 */
<> 144:ef7eb2e8f9f7 1015
<> 144:ef7eb2e8f9f7 1016 /*@}*/ /* end of group Renesas_RZ_A1_CPG */
<> 144:ef7eb2e8f9f7 1017
<> 144:ef7eb2e8f9f7 1018 /******************************************************************************/
<> 144:ef7eb2e8f9f7 1019 /* GPIO Settings */
<> 144:ef7eb2e8f9f7 1020 /******************************************************************************/
<> 144:ef7eb2e8f9f7 1021 /** @addtogroup Renesas_RZ_A1_H_GPIO Renesas_RZ_A1 GPIO Bit definitions
<> 144:ef7eb2e8f9f7 1022 @{
<> 144:ef7eb2e8f9f7 1023 */
<> 144:ef7eb2e8f9f7 1024
<> 144:ef7eb2e8f9f7 1025 #define GPIO_BIT_N0 (1u << 0)
<> 144:ef7eb2e8f9f7 1026 #define GPIO_BIT_N1 (1u << 1)
<> 144:ef7eb2e8f9f7 1027 #define GPIO_BIT_N2 (1u << 2)
<> 144:ef7eb2e8f9f7 1028 #define GPIO_BIT_N3 (1u << 3)
<> 144:ef7eb2e8f9f7 1029 #define GPIO_BIT_N4 (1u << 4)
<> 144:ef7eb2e8f9f7 1030 #define GPIO_BIT_N5 (1u << 5)
<> 144:ef7eb2e8f9f7 1031 #define GPIO_BIT_N6 (1u << 6)
<> 144:ef7eb2e8f9f7 1032 #define GPIO_BIT_N7 (1u << 7)
<> 144:ef7eb2e8f9f7 1033 #define GPIO_BIT_N8 (1u << 8)
<> 144:ef7eb2e8f9f7 1034 #define GPIO_BIT_N9 (1u << 9)
<> 144:ef7eb2e8f9f7 1035 #define GPIO_BIT_N10 (1u << 10)
<> 144:ef7eb2e8f9f7 1036 #define GPIO_BIT_N11 (1u << 11)
<> 144:ef7eb2e8f9f7 1037 #define GPIO_BIT_N12 (1u << 12)
<> 144:ef7eb2e8f9f7 1038 #define GPIO_BIT_N13 (1u << 13)
<> 144:ef7eb2e8f9f7 1039 #define GPIO_BIT_N14 (1u << 14)
<> 144:ef7eb2e8f9f7 1040 #define GPIO_BIT_N15 (1u << 15)
<> 144:ef7eb2e8f9f7 1041
<> 144:ef7eb2e8f9f7 1042
<> 144:ef7eb2e8f9f7 1043 #define MD_BOOT10_MASK (0x3)
<> 144:ef7eb2e8f9f7 1044
<> 144:ef7eb2e8f9f7 1045 #define MD_BOOT10_BM0 (0x0)
<> 144:ef7eb2e8f9f7 1046 #define MD_BOOT10_BM1 (0x2)
<> 144:ef7eb2e8f9f7 1047 #define MD_BOOT10_BM3 (0x1)
<> 144:ef7eb2e8f9f7 1048 #define MD_BOOT10_BM4_5 (0x3)
<> 144:ef7eb2e8f9f7 1049
<> 144:ef7eb2e8f9f7 1050 #define MD_CLK (1u << 2)
<> 144:ef7eb2e8f9f7 1051 #define MD_CLKS (1u << 3)
<> 144:ef7eb2e8f9f7 1052
<> 144:ef7eb2e8f9f7 1053 /*@}*/ /* end of group Renesas_RZ_A1_GPIO */
<> 144:ef7eb2e8f9f7 1054
<> 144:ef7eb2e8f9f7 1055 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 1056 }
<> 144:ef7eb2e8f9f7 1057 #endif
<> 144:ef7eb2e8f9f7 1058
<> 144:ef7eb2e8f9f7 1059 #endif // __MBRZA1H_H__