Fawwaz Nadzmy / mbed-STM

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targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_cmu.c@150:02e0a0aed4ec, 2016-11-08 (annotated)

Committer:
<>
Date:
Tue Nov 08 17:45:16 2016 +0000
Revision:
150:02e0a0aed4ec
Parent:
149:156823d33999 
This updates the lib to the mbed lib v129

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 2 * @file em_cmu.c
<> 144:ef7eb2e8f9f7 3 * @brief Clock management unit (CMU) Peripheral API
<> 150:02e0a0aed4ec 4 * @version 5.0.0
<> 144:ef7eb2e8f9f7 5 *******************************************************************************
<> 144:ef7eb2e8f9f7 6 * @section License
<> 150:02e0a0aed4ec 7 * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 144:ef7eb2e8f9f7 8 *******************************************************************************
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Permission is granted to anyone to use this software for any purpose,
<> 144:ef7eb2e8f9f7 11 * including commercial applications, and to alter it and redistribute it
<> 144:ef7eb2e8f9f7 12 * freely, subject to the following restrictions:
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * 1. The origin of this software must not be misrepresented; you must not
<> 144:ef7eb2e8f9f7 15 * claim that you wrote the original software.
<> 144:ef7eb2e8f9f7 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 144:ef7eb2e8f9f7 17 * misrepresented as being the original software.
<> 144:ef7eb2e8f9f7 18 * 3. This notice may not be removed or altered from any source distribution.
<> 144:ef7eb2e8f9f7 19 *
<> 144:ef7eb2e8f9f7 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
<> 144:ef7eb2e8f9f7 21 * obligation to support this Software. Silicon Labs is providing the
<> 144:ef7eb2e8f9f7 22 * Software "AS IS", with no express or implied warranties of any kind,
<> 144:ef7eb2e8f9f7 23 * including, but not limited to, any implied warranties of merchantability
<> 144:ef7eb2e8f9f7 24 * or fitness for any particular purpose or warranties against infringement
<> 144:ef7eb2e8f9f7 25 * of any proprietary rights of a third party.
<> 144:ef7eb2e8f9f7 26 *
<> 144:ef7eb2e8f9f7 27 * Silicon Labs will not be liable for any consequential, incidental, or
<> 144:ef7eb2e8f9f7 28 * special damages, or any other relief, or for any claim by any third party,
<> 144:ef7eb2e8f9f7 29 * arising from your use of this Software.
<> 144:ef7eb2e8f9f7 30 *
<> 144:ef7eb2e8f9f7 31 ******************************************************************************/
<> 144:ef7eb2e8f9f7 32 #include "em_cmu.h"
<> 144:ef7eb2e8f9f7 33 #if defined( CMU_PRESENT )
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 #include <stddef.h>
<> 144:ef7eb2e8f9f7 36 #include <limits.h>
<> 144:ef7eb2e8f9f7 37 #include "em_assert.h"
<> 144:ef7eb2e8f9f7 38 #include "em_bus.h"
<> 144:ef7eb2e8f9f7 39 #include "em_emu.h"
<> 144:ef7eb2e8f9f7 40 #include "em_system.h"
<> 150:02e0a0aed4ec 41 #include "em_common.h"
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 /***************************************************************************//**
<> 150:02e0a0aed4ec 44 * @addtogroup emlib
<> 144:ef7eb2e8f9f7 45 * @{
<> 144:ef7eb2e8f9f7 46 ******************************************************************************/
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 49 * @addtogroup CMU
<> 144:ef7eb2e8f9f7 50 * @brief Clock management unit (CMU) Peripheral API
<> 150:02e0a0aed4ec 51 * @details
<> 150:02e0a0aed4ec 52 * This module contains functions to control the CMU peripheral of Silicon
<> 150:02e0a0aed4ec 53 * Labs 32-bit MCUs and SoCs. The CMU controls oscillators and clocks.
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 ******************************************************************************/
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /*******************************************************************************
<> 144:ef7eb2e8f9f7 58 ****************************** DEFINES ************************************
<> 144:ef7eb2e8f9f7 59 ******************************************************************************/
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
<> 144:ef7eb2e8f9f7 64 /** Maximum allowed core frequency when using 0 wait-states on flash access. */
<> 144:ef7eb2e8f9f7 65 #define CMU_MAX_FREQ_0WS 26000000
<> 144:ef7eb2e8f9f7 66 /** Maximum allowed core frequency when using 1 wait-states on flash access */
<> 144:ef7eb2e8f9f7 67 #define CMU_MAX_FREQ_1WS 40000000
<> 144:ef7eb2e8f9f7 68 #elif defined( _SILICON_LABS_32B_PLATFORM_1 )
<> 144:ef7eb2e8f9f7 69 /** Maximum allowed core frequency when using 0 wait-states on flash access. */
<> 144:ef7eb2e8f9f7 70 #define CMU_MAX_FREQ_0WS 16000000
<> 144:ef7eb2e8f9f7 71 /** Maximum allowed core frequency when using 1 wait-states on flash access */
<> 144:ef7eb2e8f9f7 72 #define CMU_MAX_FREQ_1WS 32000000
<> 144:ef7eb2e8f9f7 73 #else
<> 150:02e0a0aed4ec 74 #error "Max Flash wait-state frequencies are not defined for this platform."
<> 144:ef7eb2e8f9f7 75 #endif
<> 144:ef7eb2e8f9f7 76
<> 150:02e0a0aed4ec 77 /** Maximum frequency for HFLE interface */
<> 144:ef7eb2e8f9f7 78 #if defined( CMU_CTRL_HFLE )
<> 150:02e0a0aed4ec 79 /** Maximum HFLE frequency for EFM32 and EZR32 Wonder Gecko. */
<> 150:02e0a0aed4ec 80 #if defined( _EFM32_WONDER_FAMILY ) \
<> 144:ef7eb2e8f9f7 81 || defined( _EZR32_WONDER_FAMILY )
<> 150:02e0a0aed4ec 82 #define CMU_MAX_FREQ_HFLE 24000000
<> 150:02e0a0aed4ec 83 /** Maximum HFLE frequency for other platform 1 parts with maximum core clock
<> 150:02e0a0aed4ec 84 higher than 32MHz. */
<> 150:02e0a0aed4ec 85 #elif defined( _EFM32_GIANT_FAMILY ) \
<> 150:02e0a0aed4ec 86 || defined( _EFM32_LEOPARD_FAMILY ) \
<> 150:02e0a0aed4ec 87 || defined( _EZR32_LEOPARD_FAMILY )
<> 150:02e0a0aed4ec 88 #define CMU_MAX_FREQ_HFLE maxFreqHfle()
<> 144:ef7eb2e8f9f7 89 #endif
<> 150:02e0a0aed4ec 90 #elif defined( CMU_CTRL_WSHFLE )
<> 150:02e0a0aed4ec 91 /** Maximum HFLE frequency for platform 2 parts */
<> 150:02e0a0aed4ec 92 #define CMU_MAX_FREQ_HFLE 32000000
<> 144:ef7eb2e8f9f7 93 #endif
<> 144:ef7eb2e8f9f7 94
<> 150:02e0a0aed4ec 95
<> 144:ef7eb2e8f9f7 96 /*******************************************************************************
<> 144:ef7eb2e8f9f7 97 ************************** LOCAL VARIABLES ********************************
<> 144:ef7eb2e8f9f7 98 ******************************************************************************/
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 #if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
<> 144:ef7eb2e8f9f7 101 static CMU_AUXHFRCOFreq_TypeDef auxHfrcoFreq = cmuAUXHFRCOFreq_19M0Hz;
<> 144:ef7eb2e8f9f7 102 #endif
<> 150:02e0a0aed4ec 103 #if defined( _CMU_STATUS_HFXOSHUNTOPTRDY_MASK )
<> 150:02e0a0aed4ec 104 #define HFXO_INVALID_TRIM (~_CMU_HFXOTRIMSTATUS_MASK)
<> 150:02e0a0aed4ec 105 #endif
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 /** @endcond */
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 /*******************************************************************************
<> 144:ef7eb2e8f9f7 110 ************************** LOCAL FUNCTIONS ********************************
<> 144:ef7eb2e8f9f7 111 ******************************************************************************/
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
<> 144:ef7eb2e8f9f7 114
<> 150:02e0a0aed4ec 115 #if defined( _EFM32_GIANT_FAMILY ) \
<> 150:02e0a0aed4ec 116 || defined( _EFM32_LEOPARD_FAMILY ) \
<> 150:02e0a0aed4ec 117 || defined( _EZR32_LEOPARD_FAMILY )
<> 150:02e0a0aed4ec 118 /***************************************************************************//**
<> 150:02e0a0aed4ec 119 * @brief
<> 150:02e0a0aed4ec 120 * Return max allowed frequency for low energy peripherals.
<> 150:02e0a0aed4ec 121 ******************************************************************************/
<> 150:02e0a0aed4ec 122 static uint32_t maxFreqHfle(void)
<> 150:02e0a0aed4ec 123 {
<> 150:02e0a0aed4ec 124 uint16_t majorMinorRev;
<> 150:02e0a0aed4ec 125
<> 150:02e0a0aed4ec 126 switch (SYSTEM_GetFamily())
<> 150:02e0a0aed4ec 127 {
<> 150:02e0a0aed4ec 128 case systemPartFamilyEfm32Leopard:
<> 150:02e0a0aed4ec 129 case systemPartFamilyEzr32Leopard:
<> 150:02e0a0aed4ec 130 /* CHIP MAJOR bit [5:0] */
<> 150:02e0a0aed4ec 131 majorMinorRev = (((ROMTABLE->PID0 & _ROMTABLE_PID0_REVMAJOR_MASK)
<> 150:02e0a0aed4ec 132 >> _ROMTABLE_PID0_REVMAJOR_SHIFT) << 8);
<> 150:02e0a0aed4ec 133 /* CHIP MINOR bit [7:4] */
<> 150:02e0a0aed4ec 134 majorMinorRev |= (((ROMTABLE->PID2 & _ROMTABLE_PID2_REVMINORMSB_MASK)
<> 150:02e0a0aed4ec 135 >> _ROMTABLE_PID2_REVMINORMSB_SHIFT) << 4);
<> 150:02e0a0aed4ec 136 /* CHIP MINOR bit [3:0] */
<> 150:02e0a0aed4ec 137 majorMinorRev |= ((ROMTABLE->PID3 & _ROMTABLE_PID3_REVMINORLSB_MASK)
<> 150:02e0a0aed4ec 138 >> _ROMTABLE_PID3_REVMINORLSB_SHIFT);
<> 150:02e0a0aed4ec 139
<> 150:02e0a0aed4ec 140 if (majorMinorRev >= 0x0204)
<> 150:02e0a0aed4ec 141 {
<> 150:02e0a0aed4ec 142 return 24000000;
<> 150:02e0a0aed4ec 143 }
<> 150:02e0a0aed4ec 144 else
<> 150:02e0a0aed4ec 145 {
<> 150:02e0a0aed4ec 146 return 32000000;
<> 150:02e0a0aed4ec 147 }
<> 150:02e0a0aed4ec 148
<> 150:02e0a0aed4ec 149 case systemPartFamilyEfm32Giant:
<> 150:02e0a0aed4ec 150 return 32000000;
<> 150:02e0a0aed4ec 151
<> 150:02e0a0aed4ec 152 default:
<> 150:02e0a0aed4ec 153 /* Invalid device family. */
<> 150:02e0a0aed4ec 154 EFM_ASSERT(false);
<> 150:02e0a0aed4ec 155 return 0;
<> 150:02e0a0aed4ec 156 }
<> 150:02e0a0aed4ec 157 }
<> 150:02e0a0aed4ec 158 #endif
<> 150:02e0a0aed4ec 159
<> 150:02e0a0aed4ec 160 #if defined( CMU_MAX_FREQ_HFLE )
<> 150:02e0a0aed4ec 161
<> 150:02e0a0aed4ec 162 /* Unified definitions for HFLE wait-state and prescaler fields. */
<> 150:02e0a0aed4ec 163 #if defined( CMU_CTRL_HFLE )
<> 150:02e0a0aed4ec 164 #define CMU_HFLE_WS_MASK _CMU_CTRL_HFLE_MASK
<> 150:02e0a0aed4ec 165 #define CMU_HFLE_WS_SHIFT _CMU_CTRL_HFLE_SHIFT
<> 150:02e0a0aed4ec 166 #define CMU_HFLE_PRESC_REG CMU->HFCORECLKDIV
<> 150:02e0a0aed4ec 167 #define CMU_HFLE_PRESC_MASK _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK
<> 150:02e0a0aed4ec 168 #define CMU_HFLE_PRESC_SHIFT _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT
<> 150:02e0a0aed4ec 169 #elif defined( CMU_CTRL_WSHFLE )
<> 150:02e0a0aed4ec 170 #define CMU_HFLE_WS_MASK _CMU_CTRL_WSHFLE_MASK
<> 150:02e0a0aed4ec 171 #define CMU_HFLE_WS_SHIFT _CMU_CTRL_WSHFLE_SHIFT
<> 150:02e0a0aed4ec 172 #define CMU_HFLE_PRESC_REG CMU->HFPRESC
<> 150:02e0a0aed4ec 173 #define CMU_HFLE_PRESC_MASK _CMU_HFPRESC_HFCLKLEPRESC_MASK
<> 150:02e0a0aed4ec 174 #define CMU_HFLE_PRESC_SHIFT _CMU_HFPRESC_HFCLKLEPRESC_SHIFT
<> 150:02e0a0aed4ec 175 #endif
<> 150:02e0a0aed4ec 176
<> 150:02e0a0aed4ec 177 /***************************************************************************//**
<> 150:02e0a0aed4ec 178 * @brief
<> 150:02e0a0aed4ec 179 * Set HFLE wait-states and HFCLKLE prescaler.
<> 150:02e0a0aed4ec 180 *
<> 150:02e0a0aed4ec 181 * @param[in] maxLeFreq
<> 150:02e0a0aed4ec 182 * Max LE frequency
<> 150:02e0a0aed4ec 183 *
<> 150:02e0a0aed4ec 184 * @param[in] maxFreq
<> 150:02e0a0aed4ec 185 * Max LE frequency
<> 150:02e0a0aed4ec 186 ******************************************************************************/
<> 150:02e0a0aed4ec 187 static void setHfLeConfig(uint32_t hfFreq, uint32_t maxLeFreq)
<> 150:02e0a0aed4ec 188 {
<> 150:02e0a0aed4ec 189 /* Check for 1 bit fields. BUS_RegBitWrite() below are going to fail if the
<> 150:02e0a0aed4ec 190 fields are changed to more than 1 bit. */
<> 150:02e0a0aed4ec 191 EFM_ASSERT((CMU_HFLE_WS_MASK >> CMU_HFLE_WS_SHIFT) == 0x1);
<> 150:02e0a0aed4ec 192 EFM_ASSERT((CMU_HFLE_PRESC_MASK >> CMU_HFLE_PRESC_SHIFT) == 0x1);
<> 150:02e0a0aed4ec 193
<> 150:02e0a0aed4ec 194 /* 0: set 0 wait-states and DIV2
<> 150:02e0a0aed4ec 195 1: set 1 wait-states and DIV4 */
<> 150:02e0a0aed4ec 196 unsigned int val = (hfFreq <= maxLeFreq) ? 0 : 1;
<> 150:02e0a0aed4ec 197 BUS_RegBitWrite(&CMU->CTRL, CMU_HFLE_WS_SHIFT, val);
<> 150:02e0a0aed4ec 198 BUS_RegBitWrite(&CMU_HFLE_PRESC_REG, CMU_HFLE_PRESC_SHIFT, val);
<> 150:02e0a0aed4ec 199 }
<> 150:02e0a0aed4ec 200
<> 150:02e0a0aed4ec 201
<> 150:02e0a0aed4ec 202 /***************************************************************************//**
<> 150:02e0a0aed4ec 203 * @brief
<> 150:02e0a0aed4ec 204 * Get HFLE wait-state configuration.
<> 150:02e0a0aed4ec 205 *
<> 150:02e0a0aed4ec 206 * @return
<> 150:02e0a0aed4ec 207 * Current wait-state configuration.
<> 150:02e0a0aed4ec 208 ******************************************************************************/
<> 150:02e0a0aed4ec 209 static uint32_t getHfLeConfig(void)
<> 150:02e0a0aed4ec 210 {
<> 150:02e0a0aed4ec 211 uint32_t ws = BUS_RegBitRead(&CMU->CTRL, CMU_HFLE_WS_SHIFT);
<> 150:02e0a0aed4ec 212 uint32_t presc = BUS_RegBitRead(&CMU_HFLE_PRESC_REG, CMU_HFLE_PRESC_SHIFT);
<> 150:02e0a0aed4ec 213
<> 150:02e0a0aed4ec 214 /* HFLE wait-state and DIV2(0) / DIV4(1) should
<> 150:02e0a0aed4ec 215 always be set to the same value. */
<> 150:02e0a0aed4ec 216 EFM_ASSERT(ws == presc);
<> 150:02e0a0aed4ec 217 return ws;
<> 150:02e0a0aed4ec 218 }
<> 150:02e0a0aed4ec 219 #endif
<> 150:02e0a0aed4ec 220
<> 150:02e0a0aed4ec 221
<> 144:ef7eb2e8f9f7 222 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 223 * @brief
<> 144:ef7eb2e8f9f7 224 * Get the AUX clock frequency. Used by MSC flash programming and LESENSE,
<> 144:ef7eb2e8f9f7 225 * by default also as debug clock.
<> 144:ef7eb2e8f9f7 226 *
<> 144:ef7eb2e8f9f7 227 * @return
<> 144:ef7eb2e8f9f7 228 * AUX Frequency in Hz
<> 144:ef7eb2e8f9f7 229 ******************************************************************************/
<> 144:ef7eb2e8f9f7 230 static uint32_t auxClkGet(void)
<> 144:ef7eb2e8f9f7 231 {
<> 144:ef7eb2e8f9f7 232 uint32_t ret;
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234 #if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
<> 144:ef7eb2e8f9f7 235 ret = auxHfrcoFreq;
<> 144:ef7eb2e8f9f7 236
<> 144:ef7eb2e8f9f7 237 #elif defined( _CMU_AUXHFRCOCTRL_BAND_MASK )
<> 150:02e0a0aed4ec 238 /* All platform 1 families except EFM32G */
<> 144:ef7eb2e8f9f7 239 switch(CMU->AUXHFRCOCTRL & _CMU_AUXHFRCOCTRL_BAND_MASK)
<> 144:ef7eb2e8f9f7 240 {
<> 144:ef7eb2e8f9f7 241 case CMU_AUXHFRCOCTRL_BAND_1MHZ:
<> 150:02e0a0aed4ec 242 if ( SYSTEM_GetProdRev() >= 19 )
<> 150:02e0a0aed4ec 243 {
<> 150:02e0a0aed4ec 244 ret = 1200000;
<> 150:02e0a0aed4ec 245 }
<> 150:02e0a0aed4ec 246 else
<> 150:02e0a0aed4ec 247 {
<> 150:02e0a0aed4ec 248 ret = 1000000;
<> 150:02e0a0aed4ec 249 }
<> 144:ef7eb2e8f9f7 250 break;
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 case CMU_AUXHFRCOCTRL_BAND_7MHZ:
<> 150:02e0a0aed4ec 253 if ( SYSTEM_GetProdRev() >= 19 )
<> 150:02e0a0aed4ec 254 {
<> 150:02e0a0aed4ec 255 ret = 6600000;
<> 150:02e0a0aed4ec 256 }
<> 150:02e0a0aed4ec 257 else
<> 150:02e0a0aed4ec 258 {
<> 150:02e0a0aed4ec 259 ret = 7000000;
<> 150:02e0a0aed4ec 260 }
<> 144:ef7eb2e8f9f7 261 break;
<> 144:ef7eb2e8f9f7 262
<> 144:ef7eb2e8f9f7 263 case CMU_AUXHFRCOCTRL_BAND_11MHZ:
<> 144:ef7eb2e8f9f7 264 ret = 11000000;
<> 144:ef7eb2e8f9f7 265 break;
<> 144:ef7eb2e8f9f7 266
<> 144:ef7eb2e8f9f7 267 case CMU_AUXHFRCOCTRL_BAND_14MHZ:
<> 144:ef7eb2e8f9f7 268 ret = 14000000;
<> 144:ef7eb2e8f9f7 269 break;
<> 144:ef7eb2e8f9f7 270
<> 144:ef7eb2e8f9f7 271 case CMU_AUXHFRCOCTRL_BAND_21MHZ:
<> 144:ef7eb2e8f9f7 272 ret = 21000000;
<> 144:ef7eb2e8f9f7 273 break;
<> 144:ef7eb2e8f9f7 274
<> 144:ef7eb2e8f9f7 275 #if defined( _CMU_AUXHFRCOCTRL_BAND_28MHZ )
<> 144:ef7eb2e8f9f7 276 case CMU_AUXHFRCOCTRL_BAND_28MHZ:
<> 144:ef7eb2e8f9f7 277 ret = 28000000;
<> 144:ef7eb2e8f9f7 278 break;
<> 144:ef7eb2e8f9f7 279 #endif
<> 144:ef7eb2e8f9f7 280
<> 144:ef7eb2e8f9f7 281 default:
<> 144:ef7eb2e8f9f7 282 EFM_ASSERT(0);
<> 144:ef7eb2e8f9f7 283 ret = 0;
<> 144:ef7eb2e8f9f7 284 break;
<> 144:ef7eb2e8f9f7 285 }
<> 144:ef7eb2e8f9f7 286
<> 144:ef7eb2e8f9f7 287 #else
<> 144:ef7eb2e8f9f7 288 /* Gecko has a fixed 14Mhz AUXHFRCO clock */
<> 144:ef7eb2e8f9f7 289 ret = 14000000;
<> 144:ef7eb2e8f9f7 290
<> 144:ef7eb2e8f9f7 291 #endif
<> 144:ef7eb2e8f9f7 292
<> 144:ef7eb2e8f9f7 293 return ret;
<> 144:ef7eb2e8f9f7 294 }
<> 144:ef7eb2e8f9f7 295
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 298 * @brief
<> 144:ef7eb2e8f9f7 299 * Get the Debug Trace clock frequency
<> 144:ef7eb2e8f9f7 300 *
<> 144:ef7eb2e8f9f7 301 * @return
<> 144:ef7eb2e8f9f7 302 * Debug Trace frequency in Hz
<> 144:ef7eb2e8f9f7 303 ******************************************************************************/
<> 144:ef7eb2e8f9f7 304 static uint32_t dbgClkGet(void)
<> 144:ef7eb2e8f9f7 305 {
<> 144:ef7eb2e8f9f7 306 uint32_t ret;
<> 144:ef7eb2e8f9f7 307 CMU_Select_TypeDef clk;
<> 144:ef7eb2e8f9f7 308
<> 144:ef7eb2e8f9f7 309 /* Get selected clock source */
<> 144:ef7eb2e8f9f7 310 clk = CMU_ClockSelectGet(cmuClock_DBG);
<> 144:ef7eb2e8f9f7 311
<> 144:ef7eb2e8f9f7 312 switch(clk)
<> 144:ef7eb2e8f9f7 313 {
<> 144:ef7eb2e8f9f7 314 case cmuSelect_HFCLK:
<> 144:ef7eb2e8f9f7 315 ret = SystemHFClockGet();
<> 144:ef7eb2e8f9f7 316 break;
<> 144:ef7eb2e8f9f7 317
<> 144:ef7eb2e8f9f7 318 case cmuSelect_AUXHFRCO:
<> 144:ef7eb2e8f9f7 319 ret = auxClkGet();
<> 144:ef7eb2e8f9f7 320 break;
<> 144:ef7eb2e8f9f7 321
<> 144:ef7eb2e8f9f7 322 default:
<> 144:ef7eb2e8f9f7 323 EFM_ASSERT(0);
<> 144:ef7eb2e8f9f7 324 ret = 0;
<> 144:ef7eb2e8f9f7 325 break;
<> 144:ef7eb2e8f9f7 326 }
<> 144:ef7eb2e8f9f7 327 return ret;
<> 144:ef7eb2e8f9f7 328 }
<> 144:ef7eb2e8f9f7 329
<> 144:ef7eb2e8f9f7 330
<> 144:ef7eb2e8f9f7 331 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 332 * @brief
<> 144:ef7eb2e8f9f7 333 * Configure flash access wait states in order to support given core clock
<> 144:ef7eb2e8f9f7 334 * frequency.
<> 144:ef7eb2e8f9f7 335 *
<> 144:ef7eb2e8f9f7 336 * @param[in] coreFreq
<> 144:ef7eb2e8f9f7 337 * Core clock frequency to configure flash wait-states for
<> 144:ef7eb2e8f9f7 338 ******************************************************************************/
<> 144:ef7eb2e8f9f7 339 static void flashWaitStateControl(uint32_t coreFreq)
<> 144:ef7eb2e8f9f7 340 {
<> 144:ef7eb2e8f9f7 341 uint32_t mode;
<> 144:ef7eb2e8f9f7 342 bool mscLocked;
<> 144:ef7eb2e8f9f7 343 #if defined( MSC_READCTRL_MODE_WS0SCBTP )
<> 144:ef7eb2e8f9f7 344 bool scbtpEn; /* Suppressed Conditional Branch Target Prefetch setting. */
<> 144:ef7eb2e8f9f7 345 #endif
<> 144:ef7eb2e8f9f7 346
<> 144:ef7eb2e8f9f7 347 /* Make sure the MSC is unlocked */
<> 144:ef7eb2e8f9f7 348 mscLocked = MSC->LOCK;
<> 144:ef7eb2e8f9f7 349 MSC->LOCK = MSC_UNLOCK_CODE;
<> 144:ef7eb2e8f9f7 350
<> 144:ef7eb2e8f9f7 351 /* Get mode and SCBTP enable */
<> 144:ef7eb2e8f9f7 352 mode = MSC->READCTRL & _MSC_READCTRL_MODE_MASK;
<> 144:ef7eb2e8f9f7 353 #if defined( MSC_READCTRL_MODE_WS0SCBTP )
<> 144:ef7eb2e8f9f7 354 switch(mode)
<> 144:ef7eb2e8f9f7 355 {
<> 144:ef7eb2e8f9f7 356 case MSC_READCTRL_MODE_WS0:
<> 144:ef7eb2e8f9f7 357 case MSC_READCTRL_MODE_WS1:
<> 144:ef7eb2e8f9f7 358 #if defined( MSC_READCTRL_MODE_WS2 )
<> 144:ef7eb2e8f9f7 359 case MSC_READCTRL_MODE_WS2:
<> 144:ef7eb2e8f9f7 360 #endif
<> 144:ef7eb2e8f9f7 361 scbtpEn = false;
<> 144:ef7eb2e8f9f7 362 break;
<> 144:ef7eb2e8f9f7 363
<> 144:ef7eb2e8f9f7 364 default: /* WSxSCBTP */
<> 144:ef7eb2e8f9f7 365 scbtpEn = true;
<> 144:ef7eb2e8f9f7 366 break;
<> 144:ef7eb2e8f9f7 367 }
<> 144:ef7eb2e8f9f7 368 #endif
<> 144:ef7eb2e8f9f7 369
<> 144:ef7eb2e8f9f7 370
<> 144:ef7eb2e8f9f7 371 /* Set mode based on the core clock frequency and SCBTP enable */
<> 144:ef7eb2e8f9f7 372 #if defined( MSC_READCTRL_MODE_WS0SCBTP )
<> 144:ef7eb2e8f9f7 373 if (false)
<> 144:ef7eb2e8f9f7 374 {
<> 144:ef7eb2e8f9f7 375 }
<> 144:ef7eb2e8f9f7 376 #if defined( MSC_READCTRL_MODE_WS2 )
<> 144:ef7eb2e8f9f7 377 else if (coreFreq > CMU_MAX_FREQ_1WS)
<> 144:ef7eb2e8f9f7 378 {
<> 144:ef7eb2e8f9f7 379 mode = (scbtpEn ? MSC_READCTRL_MODE_WS2SCBTP : MSC_READCTRL_MODE_WS2);
<> 144:ef7eb2e8f9f7 380 }
<> 144:ef7eb2e8f9f7 381 #endif
<> 144:ef7eb2e8f9f7 382 else if ((coreFreq <= CMU_MAX_FREQ_1WS) && (coreFreq > CMU_MAX_FREQ_0WS))
<> 144:ef7eb2e8f9f7 383 {
<> 144:ef7eb2e8f9f7 384 mode = (scbtpEn ? MSC_READCTRL_MODE_WS1SCBTP : MSC_READCTRL_MODE_WS1);
<> 144:ef7eb2e8f9f7 385 }
<> 144:ef7eb2e8f9f7 386 else
<> 144:ef7eb2e8f9f7 387 {
<> 144:ef7eb2e8f9f7 388 mode = (scbtpEn ? MSC_READCTRL_MODE_WS0SCBTP : MSC_READCTRL_MODE_WS0);
<> 144:ef7eb2e8f9f7 389 }
<> 144:ef7eb2e8f9f7 390
<> 144:ef7eb2e8f9f7 391 #else /* If MODE and SCBTP is in separate register fields */
<> 144:ef7eb2e8f9f7 392
<> 144:ef7eb2e8f9f7 393 if (false)
<> 144:ef7eb2e8f9f7 394 {
<> 144:ef7eb2e8f9f7 395 }
<> 144:ef7eb2e8f9f7 396 #if defined( MSC_READCTRL_MODE_WS2 )
<> 144:ef7eb2e8f9f7 397 else if (coreFreq > CMU_MAX_FREQ_1WS)
<> 144:ef7eb2e8f9f7 398 {
<> 144:ef7eb2e8f9f7 399 mode = MSC_READCTRL_MODE_WS2;
<> 144:ef7eb2e8f9f7 400 }
<> 144:ef7eb2e8f9f7 401 #endif
<> 144:ef7eb2e8f9f7 402 else if ((coreFreq <= CMU_MAX_FREQ_1WS) && (coreFreq > CMU_MAX_FREQ_0WS))
<> 144:ef7eb2e8f9f7 403 {
<> 144:ef7eb2e8f9f7 404 mode = MSC_READCTRL_MODE_WS1;
<> 144:ef7eb2e8f9f7 405 }
<> 144:ef7eb2e8f9f7 406 else
<> 144:ef7eb2e8f9f7 407 {
<> 144:ef7eb2e8f9f7 408 mode = MSC_READCTRL_MODE_WS0;
<> 144:ef7eb2e8f9f7 409 }
<> 144:ef7eb2e8f9f7 410 #endif
<> 144:ef7eb2e8f9f7 411
<> 144:ef7eb2e8f9f7 412 /* BUS_RegMaskedWrite cannot be used here as it would temporarely set the
<> 144:ef7eb2e8f9f7 413 mode field to WS0 */
<> 144:ef7eb2e8f9f7 414 MSC->READCTRL = (MSC->READCTRL &~_MSC_READCTRL_MODE_MASK) | mode;
<> 144:ef7eb2e8f9f7 415
<> 144:ef7eb2e8f9f7 416 if (mscLocked)
<> 144:ef7eb2e8f9f7 417 {
<> 144:ef7eb2e8f9f7 418 MSC->LOCK = 0;
<> 144:ef7eb2e8f9f7 419 }
<> 144:ef7eb2e8f9f7 420 }
<> 144:ef7eb2e8f9f7 421
<> 144:ef7eb2e8f9f7 422
<> 144:ef7eb2e8f9f7 423 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 424 * @brief
<> 144:ef7eb2e8f9f7 425 * Configure flash access wait states to most conservative setting for
<> 144:ef7eb2e8f9f7 426 * this target. Retain SCBTP (Suppressed Conditional Branch Target Prefetch)
<> 144:ef7eb2e8f9f7 427 * setting.
<> 144:ef7eb2e8f9f7 428 ******************************************************************************/
<> 144:ef7eb2e8f9f7 429 static void flashWaitStateMax(void)
<> 144:ef7eb2e8f9f7 430 {
<> 144:ef7eb2e8f9f7 431 flashWaitStateControl(SystemMaxCoreClockGet());
<> 144:ef7eb2e8f9f7 432 }
<> 144:ef7eb2e8f9f7 433
<> 144:ef7eb2e8f9f7 434
<> 150:02e0a0aed4ec 435 #if defined(_CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK)
<> 150:02e0a0aed4ec 436 /***************************************************************************//**
<> 150:02e0a0aed4ec 437 * @brief
<> 150:02e0a0aed4ec 438 * Return upper value for CMU_HFXOSTEADYSTATECTRL_REGISH
<> 150:02e0a0aed4ec 439 ******************************************************************************/
<> 150:02e0a0aed4ec 440 static uint32_t getRegIshUpperVal(uint32_t steadyStateRegIsh)
<> 150:02e0a0aed4ec 441 {
<> 150:02e0a0aed4ec 442 uint32_t regIshUpper;
<> 150:02e0a0aed4ec 443 const uint32_t upperMax = _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK
<> 150:02e0a0aed4ec 444 >> _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_SHIFT;
<> 150:02e0a0aed4ec 445 /* Add 3 as specified in register description for CMU_HFXOSTEADYSTATECTRL_REGISHUPPER. */
<> 150:02e0a0aed4ec 446 regIshUpper = SL_MIN(steadyStateRegIsh + 3, upperMax);
<> 150:02e0a0aed4ec 447 regIshUpper <<= _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_SHIFT;
<> 150:02e0a0aed4ec 448 return regIshUpper;
<> 150:02e0a0aed4ec 449 }
<> 150:02e0a0aed4ec 450 #endif
<> 150:02e0a0aed4ec 451
<> 150:02e0a0aed4ec 452
<> 144:ef7eb2e8f9f7 453 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 454 * @brief
<> 144:ef7eb2e8f9f7 455 * Get the LFnCLK frequency based on current configuration.
<> 144:ef7eb2e8f9f7 456 *
<> 144:ef7eb2e8f9f7 457 * @param[in] lfClkBranch
<> 144:ef7eb2e8f9f7 458 * Selected LF branch
<> 144:ef7eb2e8f9f7 459 *
<> 144:ef7eb2e8f9f7 460 * @return
<> 144:ef7eb2e8f9f7 461 * The LFnCLK frequency in Hz. If no LFnCLK is selected (disabled), 0 is
<> 144:ef7eb2e8f9f7 462 * returned.
<> 144:ef7eb2e8f9f7 463 ******************************************************************************/
<> 144:ef7eb2e8f9f7 464 static uint32_t lfClkGet(CMU_Clock_TypeDef lfClkBranch)
<> 144:ef7eb2e8f9f7 465 {
<> 144:ef7eb2e8f9f7 466 uint32_t sel;
<> 144:ef7eb2e8f9f7 467 uint32_t ret = 0;
<> 144:ef7eb2e8f9f7 468
<> 144:ef7eb2e8f9f7 469 switch (lfClkBranch)
<> 144:ef7eb2e8f9f7 470 {
<> 144:ef7eb2e8f9f7 471 case cmuClock_LFA:
<> 144:ef7eb2e8f9f7 472 case cmuClock_LFB:
<> 144:ef7eb2e8f9f7 473 #if defined( _CMU_LFCCLKEN0_MASK )
<> 144:ef7eb2e8f9f7 474 case cmuClock_LFC:
<> 144:ef7eb2e8f9f7 475 #endif
<> 144:ef7eb2e8f9f7 476 #if defined( _CMU_LFECLKSEL_MASK )
<> 144:ef7eb2e8f9f7 477 case cmuClock_LFE:
<> 144:ef7eb2e8f9f7 478 #endif
<> 144:ef7eb2e8f9f7 479 break;
<> 144:ef7eb2e8f9f7 480
<> 144:ef7eb2e8f9f7 481 default:
<> 144:ef7eb2e8f9f7 482 EFM_ASSERT(0);
<> 144:ef7eb2e8f9f7 483 break;
<> 144:ef7eb2e8f9f7 484 }
<> 144:ef7eb2e8f9f7 485
<> 144:ef7eb2e8f9f7 486 sel = CMU_ClockSelectGet(lfClkBranch);
<> 144:ef7eb2e8f9f7 487
<> 144:ef7eb2e8f9f7 488 /* Get clock select field */
<> 144:ef7eb2e8f9f7 489 switch (lfClkBranch)
<> 144:ef7eb2e8f9f7 490 {
<> 144:ef7eb2e8f9f7 491 case cmuClock_LFA:
<> 144:ef7eb2e8f9f7 492 #if defined( _CMU_LFCLKSEL_MASK )
<> 144:ef7eb2e8f9f7 493 sel = (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFA_MASK) >> _CMU_LFCLKSEL_LFA_SHIFT;
<> 144:ef7eb2e8f9f7 494 #elif defined( _CMU_LFACLKSEL_MASK )
<> 144:ef7eb2e8f9f7 495 sel = (CMU->LFACLKSEL & _CMU_LFACLKSEL_LFA_MASK) >> _CMU_LFACLKSEL_LFA_SHIFT;
<> 144:ef7eb2e8f9f7 496 #else
<> 144:ef7eb2e8f9f7 497 EFM_ASSERT(0);
<> 144:ef7eb2e8f9f7 498 #endif
<> 144:ef7eb2e8f9f7 499 break;
<> 144:ef7eb2e8f9f7 500
<> 144:ef7eb2e8f9f7 501 case cmuClock_LFB:
<> 144:ef7eb2e8f9f7 502 #if defined( _CMU_LFCLKSEL_MASK )
<> 144:ef7eb2e8f9f7 503 sel = (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFB_MASK) >> _CMU_LFCLKSEL_LFB_SHIFT;
<> 144:ef7eb2e8f9f7 504 #elif defined( _CMU_LFBCLKSEL_MASK )
<> 144:ef7eb2e8f9f7 505 sel = (CMU->LFBCLKSEL & _CMU_LFBCLKSEL_LFB_MASK) >> _CMU_LFBCLKSEL_LFB_SHIFT;
<> 144:ef7eb2e8f9f7 506 #else
<> 144:ef7eb2e8f9f7 507 EFM_ASSERT(0);
<> 144:ef7eb2e8f9f7 508 #endif
<> 144:ef7eb2e8f9f7 509 break;
<> 144:ef7eb2e8f9f7 510
<> 144:ef7eb2e8f9f7 511 #if defined( _CMU_LFCCLKEN0_MASK )
<> 144:ef7eb2e8f9f7 512 case cmuClock_LFC:
<> 144:ef7eb2e8f9f7 513 sel = (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFC_MASK) >> _CMU_LFCLKSEL_LFC_SHIFT;
<> 144:ef7eb2e8f9f7 514 break;
<> 144:ef7eb2e8f9f7 515 #endif
<> 144:ef7eb2e8f9f7 516
<> 144:ef7eb2e8f9f7 517 #if defined( _CMU_LFECLKSEL_MASK )
<> 144:ef7eb2e8f9f7 518 case cmuClock_LFE:
<> 144:ef7eb2e8f9f7 519 sel = (CMU->LFECLKSEL & _CMU_LFECLKSEL_LFE_MASK) >> _CMU_LFECLKSEL_LFE_SHIFT;
<> 144:ef7eb2e8f9f7 520 break;
<> 144:ef7eb2e8f9f7 521 #endif
<> 144:ef7eb2e8f9f7 522
<> 144:ef7eb2e8f9f7 523 default:
<> 144:ef7eb2e8f9f7 524 EFM_ASSERT(0);
<> 144:ef7eb2e8f9f7 525 break;
<> 144:ef7eb2e8f9f7 526 }
<> 144:ef7eb2e8f9f7 527
<> 144:ef7eb2e8f9f7 528 /* Get clock frequency */
<> 144:ef7eb2e8f9f7 529 #if defined( _CMU_LFCLKSEL_MASK )
<> 144:ef7eb2e8f9f7 530 switch (sel)
<> 144:ef7eb2e8f9f7 531 {
<> 144:ef7eb2e8f9f7 532 case _CMU_LFCLKSEL_LFA_LFRCO:
<> 144:ef7eb2e8f9f7 533 ret = SystemLFRCOClockGet();
<> 144:ef7eb2e8f9f7 534 break;
<> 144:ef7eb2e8f9f7 535
<> 144:ef7eb2e8f9f7 536 case _CMU_LFCLKSEL_LFA_LFXO:
<> 144:ef7eb2e8f9f7 537 ret = SystemLFXOClockGet();
<> 144:ef7eb2e8f9f7 538 break;
<> 144:ef7eb2e8f9f7 539
<> 144:ef7eb2e8f9f7 540 #if defined( _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 )
<> 144:ef7eb2e8f9f7 541 case _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2:
<> 150:02e0a0aed4ec 542 #if defined( CMU_MAX_FREQ_HFLE )
<> 150:02e0a0aed4ec 543 ret = SystemCoreClockGet() / (1U << (getHfLeConfig() + 1));
<> 144:ef7eb2e8f9f7 544 #else
<> 144:ef7eb2e8f9f7 545 ret = SystemCoreClockGet() / 2U;
<> 144:ef7eb2e8f9f7 546 #endif
<> 144:ef7eb2e8f9f7 547 break;
<> 144:ef7eb2e8f9f7 548 #endif
<> 144:ef7eb2e8f9f7 549
<> 144:ef7eb2e8f9f7 550 case _CMU_LFCLKSEL_LFA_DISABLED:
<> 144:ef7eb2e8f9f7 551 ret = 0;
<> 144:ef7eb2e8f9f7 552 #if defined( CMU_LFCLKSEL_LFAE )
<> 144:ef7eb2e8f9f7 553 /* Check LF Extended bit setting for LFA or LFB ULFRCO clock */
<> 144:ef7eb2e8f9f7 554 if ((lfClkBranch == cmuClock_LFA) || (lfClkBranch == cmuClock_LFB))
<> 144:ef7eb2e8f9f7 555 {
<> 144:ef7eb2e8f9f7 556 if (CMU->LFCLKSEL >> (lfClkBranch == cmuClock_LFA
<> 144:ef7eb2e8f9f7 557 ? _CMU_LFCLKSEL_LFAE_SHIFT
<> 144:ef7eb2e8f9f7 558 : _CMU_LFCLKSEL_LFBE_SHIFT))
<> 144:ef7eb2e8f9f7 559 {
<> 144:ef7eb2e8f9f7 560 ret = SystemULFRCOClockGet();
<> 144:ef7eb2e8f9f7 561 }
<> 144:ef7eb2e8f9f7 562 }
<> 144:ef7eb2e8f9f7 563 #endif
<> 144:ef7eb2e8f9f7 564 break;
<> 144:ef7eb2e8f9f7 565
<> 144:ef7eb2e8f9f7 566 default:
<> 144:ef7eb2e8f9f7 567 EFM_ASSERT(0);
<> 144:ef7eb2e8f9f7 568 ret = 0U;
<> 144:ef7eb2e8f9f7 569 break;
<> 144:ef7eb2e8f9f7 570 }
<> 144:ef7eb2e8f9f7 571 #endif /* _CMU_LFCLKSEL_MASK */
<> 144:ef7eb2e8f9f7 572
<> 144:ef7eb2e8f9f7 573 #if defined( _CMU_LFACLKSEL_MASK )
<> 144:ef7eb2e8f9f7 574 switch (sel)
<> 144:ef7eb2e8f9f7 575 {
<> 144:ef7eb2e8f9f7 576 case _CMU_LFACLKSEL_LFA_LFRCO:
<> 144:ef7eb2e8f9f7 577 ret = SystemLFRCOClockGet();
<> 144:ef7eb2e8f9f7 578 break;
<> 144:ef7eb2e8f9f7 579
<> 144:ef7eb2e8f9f7 580 case _CMU_LFACLKSEL_LFA_LFXO:
<> 144:ef7eb2e8f9f7 581 ret = SystemLFXOClockGet();
<> 144:ef7eb2e8f9f7 582 break;
<> 144:ef7eb2e8f9f7 583
<> 144:ef7eb2e8f9f7 584 case _CMU_LFACLKSEL_LFA_ULFRCO:
<> 144:ef7eb2e8f9f7 585 ret = SystemULFRCOClockGet();
<> 144:ef7eb2e8f9f7 586 break;
<> 144:ef7eb2e8f9f7 587
<> 144:ef7eb2e8f9f7 588 #if defined( _CMU_LFACLKSEL_LFA_HFCLKLE )
<> 144:ef7eb2e8f9f7 589 case _CMU_LFACLKSEL_LFA_HFCLKLE:
<> 144:ef7eb2e8f9f7 590 ret = ((CMU->HFPRESC & _CMU_HFPRESC_HFCLKLEPRESC_MASK)
<> 144:ef7eb2e8f9f7 591 == CMU_HFPRESC_HFCLKLEPRESC_DIV4)
<> 144:ef7eb2e8f9f7 592 ? SystemCoreClockGet() / 4U
<> 144:ef7eb2e8f9f7 593 : SystemCoreClockGet() / 2U;
<> 144:ef7eb2e8f9f7 594 break;
<> 144:ef7eb2e8f9f7 595 #elif defined( _CMU_LFBCLKSEL_LFB_HFCLKLE )
<> 144:ef7eb2e8f9f7 596 case _CMU_LFBCLKSEL_LFB_HFCLKLE:
<> 144:ef7eb2e8f9f7 597 ret = ((CMU->HFPRESC & _CMU_HFPRESC_HFCLKLEPRESC_MASK)
<> 144:ef7eb2e8f9f7 598 == CMU_HFPRESC_HFCLKLEPRESC_DIV4)
<> 144:ef7eb2e8f9f7 599 ? SystemCoreClockGet() / 4U
<> 144:ef7eb2e8f9f7 600 : SystemCoreClockGet() / 2U;
<> 144:ef7eb2e8f9f7 601 break;
<> 144:ef7eb2e8f9f7 602 #endif
<> 144:ef7eb2e8f9f7 603
<> 144:ef7eb2e8f9f7 604 case _CMU_LFACLKSEL_LFA_DISABLED:
<> 144:ef7eb2e8f9f7 605 ret = 0;
<> 144:ef7eb2e8f9f7 606 break;
<> 144:ef7eb2e8f9f7 607 }
<> 144:ef7eb2e8f9f7 608 #endif
<> 144:ef7eb2e8f9f7 609
<> 144:ef7eb2e8f9f7 610 return ret;
<> 144:ef7eb2e8f9f7 611 }
<> 144:ef7eb2e8f9f7 612
<> 144:ef7eb2e8f9f7 613
<> 144:ef7eb2e8f9f7 614 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 615 * @brief
<> 144:ef7eb2e8f9f7 616 * Wait for ongoing sync of register(s) to low frequency domain to complete.
<> 144:ef7eb2e8f9f7 617 *
<> 144:ef7eb2e8f9f7 618 * @param[in] mask
<> 144:ef7eb2e8f9f7 619 * Bitmask corresponding to SYNCBUSY register defined bits, indicating
<> 144:ef7eb2e8f9f7 620 * registers that must complete any ongoing synchronization.
<> 144:ef7eb2e8f9f7 621 ******************************************************************************/
<> 144:ef7eb2e8f9f7 622 __STATIC_INLINE void syncReg(uint32_t mask)
<> 144:ef7eb2e8f9f7 623 {
<> 144:ef7eb2e8f9f7 624 /* Avoid deadlock if modifying the same register twice when freeze mode is */
<> 144:ef7eb2e8f9f7 625 /* activated. */
<> 144:ef7eb2e8f9f7 626 if (CMU->FREEZE & CMU_FREEZE_REGFREEZE)
<> 144:ef7eb2e8f9f7 627 return;
<> 144:ef7eb2e8f9f7 628
<> 144:ef7eb2e8f9f7 629 /* Wait for any pending previous write operation to have been completed */
<> 144:ef7eb2e8f9f7 630 /* in low frequency domain */
<> 144:ef7eb2e8f9f7 631 while (CMU->SYNCBUSY & mask)
<> 144:ef7eb2e8f9f7 632 {
<> 144:ef7eb2e8f9f7 633 }
<> 144:ef7eb2e8f9f7 634 }
<> 144:ef7eb2e8f9f7 635
<> 144:ef7eb2e8f9f7 636
<> 144:ef7eb2e8f9f7 637 #if defined(USB_PRESENT)
<> 144:ef7eb2e8f9f7 638 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 639 * @brief
<> 144:ef7eb2e8f9f7 640 * Get the USBC frequency
<> 144:ef7eb2e8f9f7 641 *
<> 144:ef7eb2e8f9f7 642 * @return
<> 144:ef7eb2e8f9f7 643 * USBC frequency in Hz
<> 144:ef7eb2e8f9f7 644 ******************************************************************************/
<> 144:ef7eb2e8f9f7 645 static uint32_t usbCClkGet(void)
<> 144:ef7eb2e8f9f7 646 {
<> 144:ef7eb2e8f9f7 647 uint32_t ret;
<> 144:ef7eb2e8f9f7 648 CMU_Select_TypeDef clk;
<> 144:ef7eb2e8f9f7 649
<> 144:ef7eb2e8f9f7 650 /* Get selected clock source */
<> 144:ef7eb2e8f9f7 651 clk = CMU_ClockSelectGet(cmuClock_USBC);
<> 144:ef7eb2e8f9f7 652
<> 144:ef7eb2e8f9f7 653 switch(clk)
<> 144:ef7eb2e8f9f7 654 {
<> 144:ef7eb2e8f9f7 655 case cmuSelect_LFXO:
<> 144:ef7eb2e8f9f7 656 ret = SystemLFXOClockGet();
<> 144:ef7eb2e8f9f7 657 break;
<> 144:ef7eb2e8f9f7 658 case cmuSelect_LFRCO:
<> 144:ef7eb2e8f9f7 659 ret = SystemLFRCOClockGet();
<> 144:ef7eb2e8f9f7 660 break;
<> 144:ef7eb2e8f9f7 661 case cmuSelect_HFCLK:
<> 144:ef7eb2e8f9f7 662 ret = SystemHFClockGet();
<> 144:ef7eb2e8f9f7 663 break;
<> 144:ef7eb2e8f9f7 664 default:
<> 144:ef7eb2e8f9f7 665 /* Clock is not enabled */
<> 144:ef7eb2e8f9f7 666 ret = 0;
<> 144:ef7eb2e8f9f7 667 break;
<> 144:ef7eb2e8f9f7 668 }
<> 144:ef7eb2e8f9f7 669 return ret;
<> 144:ef7eb2e8f9f7 670 }
<> 144:ef7eb2e8f9f7 671 #endif
<> 144:ef7eb2e8f9f7 672
<> 144:ef7eb2e8f9f7 673
<> 144:ef7eb2e8f9f7 674 /** @endcond */
<> 144:ef7eb2e8f9f7 675
<> 144:ef7eb2e8f9f7 676 /*******************************************************************************
<> 144:ef7eb2e8f9f7 677 ************************** GLOBAL FUNCTIONS *******************************
<> 144:ef7eb2e8f9f7 678 ******************************************************************************/
<> 144:ef7eb2e8f9f7 679
<> 144:ef7eb2e8f9f7 680 #if defined( _CMU_AUXHFRCOCTRL_BAND_MASK )
<> 144:ef7eb2e8f9f7 681 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 682 * @brief
<> 144:ef7eb2e8f9f7 683 * Get AUXHFRCO band in use.
<> 144:ef7eb2e8f9f7 684 *
<> 144:ef7eb2e8f9f7 685 * @return
<> 144:ef7eb2e8f9f7 686 * AUXHFRCO band in use.
<> 144:ef7eb2e8f9f7 687 ******************************************************************************/
<> 144:ef7eb2e8f9f7 688 CMU_AUXHFRCOBand_TypeDef CMU_AUXHFRCOBandGet(void)
<> 144:ef7eb2e8f9f7 689 {
<> 144:ef7eb2e8f9f7 690 return (CMU_AUXHFRCOBand_TypeDef)((CMU->AUXHFRCOCTRL
<> 144:ef7eb2e8f9f7 691 & _CMU_AUXHFRCOCTRL_BAND_MASK)
<> 144:ef7eb2e8f9f7 692 >> _CMU_AUXHFRCOCTRL_BAND_SHIFT);
<> 144:ef7eb2e8f9f7 693 }
<> 144:ef7eb2e8f9f7 694 #endif /* _CMU_AUXHFRCOCTRL_BAND_MASK */
<> 144:ef7eb2e8f9f7 695
<> 144:ef7eb2e8f9f7 696
<> 144:ef7eb2e8f9f7 697 #if defined( _CMU_AUXHFRCOCTRL_BAND_MASK )
<> 144:ef7eb2e8f9f7 698 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 699 * @brief
<> 144:ef7eb2e8f9f7 700 * Set AUXHFRCO band and the tuning value based on the value in the
<> 144:ef7eb2e8f9f7 701 * calibration table made during production.
<> 144:ef7eb2e8f9f7 702 *
<> 144:ef7eb2e8f9f7 703 * @param[in] band
<> 144:ef7eb2e8f9f7 704 * AUXHFRCO band to activate.
<> 144:ef7eb2e8f9f7 705 ******************************************************************************/
<> 144:ef7eb2e8f9f7 706 void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOBand_TypeDef band)
<> 144:ef7eb2e8f9f7 707 {
<> 144:ef7eb2e8f9f7 708 uint32_t tuning;
<> 144:ef7eb2e8f9f7 709
<> 144:ef7eb2e8f9f7 710 /* Read tuning value from calibration table */
<> 144:ef7eb2e8f9f7 711 switch (band)
<> 144:ef7eb2e8f9f7 712 {
<> 144:ef7eb2e8f9f7 713 case cmuAUXHFRCOBand_1MHz:
<> 144:ef7eb2e8f9f7 714 tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND1_MASK)
<> 144:ef7eb2e8f9f7 715 >> _DEVINFO_AUXHFRCOCAL0_BAND1_SHIFT;
<> 144:ef7eb2e8f9f7 716 break;
<> 144:ef7eb2e8f9f7 717
<> 144:ef7eb2e8f9f7 718 case cmuAUXHFRCOBand_7MHz:
<> 144:ef7eb2e8f9f7 719 tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND7_MASK)
<> 144:ef7eb2e8f9f7 720 >> _DEVINFO_AUXHFRCOCAL0_BAND7_SHIFT;
<> 144:ef7eb2e8f9f7 721 break;
<> 144:ef7eb2e8f9f7 722
<> 144:ef7eb2e8f9f7 723 case cmuAUXHFRCOBand_11MHz:
<> 144:ef7eb2e8f9f7 724 tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND11_MASK)
<> 144:ef7eb2e8f9f7 725 >> _DEVINFO_AUXHFRCOCAL0_BAND11_SHIFT;
<> 144:ef7eb2e8f9f7 726 break;
<> 144:ef7eb2e8f9f7 727
<> 144:ef7eb2e8f9f7 728 case cmuAUXHFRCOBand_14MHz:
<> 144:ef7eb2e8f9f7 729 tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND14_MASK)
<> 144:ef7eb2e8f9f7 730 >> _DEVINFO_AUXHFRCOCAL0_BAND14_SHIFT;
<> 144:ef7eb2e8f9f7 731 break;
<> 144:ef7eb2e8f9f7 732
<> 144:ef7eb2e8f9f7 733 case cmuAUXHFRCOBand_21MHz:
<> 144:ef7eb2e8f9f7 734 tuning = (DEVINFO->AUXHFRCOCAL1 & _DEVINFO_AUXHFRCOCAL1_BAND21_MASK)
<> 144:ef7eb2e8f9f7 735 >> _DEVINFO_AUXHFRCOCAL1_BAND21_SHIFT;
<> 144:ef7eb2e8f9f7 736 break;
<> 144:ef7eb2e8f9f7 737
<> 144:ef7eb2e8f9f7 738 #if defined( _CMU_AUXHFRCOCTRL_BAND_28MHZ )
<> 144:ef7eb2e8f9f7 739 case cmuAUXHFRCOBand_28MHz:
<> 144:ef7eb2e8f9f7 740 tuning = (DEVINFO->AUXHFRCOCAL1 & _DEVINFO_AUXHFRCOCAL1_BAND28_MASK)
<> 144:ef7eb2e8f9f7 741 >> _DEVINFO_AUXHFRCOCAL1_BAND28_SHIFT;
<> 144:ef7eb2e8f9f7 742 break;
<> 144:ef7eb2e8f9f7 743 #endif
<> 144:ef7eb2e8f9f7 744
<> 144:ef7eb2e8f9f7 745 default:
<> 144:ef7eb2e8f9f7 746 EFM_ASSERT(0);
<> 144:ef7eb2e8f9f7 747 return;
<> 144:ef7eb2e8f9f7 748 }
<> 144:ef7eb2e8f9f7 749
<> 144:ef7eb2e8f9f7 750 /* Set band/tuning */
<> 144:ef7eb2e8f9f7 751 CMU->AUXHFRCOCTRL = (CMU->AUXHFRCOCTRL &
<> 144:ef7eb2e8f9f7 752 ~(_CMU_AUXHFRCOCTRL_BAND_MASK
<> 144:ef7eb2e8f9f7 753 | _CMU_AUXHFRCOCTRL_TUNING_MASK))
<> 144:ef7eb2e8f9f7 754 | (band << _CMU_AUXHFRCOCTRL_BAND_SHIFT)
<> 144:ef7eb2e8f9f7 755 | (tuning << _CMU_AUXHFRCOCTRL_TUNING_SHIFT);
<> 144:ef7eb2e8f9f7 756
<> 144:ef7eb2e8f9f7 757 }
<> 144:ef7eb2e8f9f7 758 #endif /* _CMU_AUXHFRCOCTRL_BAND_MASK */
<> 144:ef7eb2e8f9f7 759
<> 144:ef7eb2e8f9f7 760
<> 144:ef7eb2e8f9f7 761 #if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
<> 144:ef7eb2e8f9f7 762 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 763 * @brief
<> 144:ef7eb2e8f9f7 764 * Get a pointer to the AUXHFRCO frequency calibration word in DEVINFO
<> 144:ef7eb2e8f9f7 765 *
<> 144:ef7eb2e8f9f7 766 * @param[in] freq
<> 144:ef7eb2e8f9f7 767 * Frequency in Hz
<> 144:ef7eb2e8f9f7 768 *
<> 144:ef7eb2e8f9f7 769 * @return
<> 144:ef7eb2e8f9f7 770 * AUXHFRCO calibration word for a given frequency
<> 144:ef7eb2e8f9f7 771 *****************************************************************************/
<> 144:ef7eb2e8f9f7 772 static uint32_t CMU_AUXHFRCODevinfoGet(CMU_AUXHFRCOFreq_TypeDef freq)
<> 144:ef7eb2e8f9f7 773 {
<> 144:ef7eb2e8f9f7 774 switch (freq)
<> 144:ef7eb2e8f9f7 775 {
<> 144:ef7eb2e8f9f7 776 /* 1, 2 and 4MHz share the same calibration word */
<> 144:ef7eb2e8f9f7 777 case cmuAUXHFRCOFreq_1M0Hz:
<> 144:ef7eb2e8f9f7 778 case cmuAUXHFRCOFreq_2M0Hz:
<> 144:ef7eb2e8f9f7 779 case cmuAUXHFRCOFreq_4M0Hz:
<> 144:ef7eb2e8f9f7 780 return DEVINFO->AUXHFRCOCAL0;
<> 144:ef7eb2e8f9f7 781
<> 144:ef7eb2e8f9f7 782 case cmuAUXHFRCOFreq_7M0Hz:
<> 144:ef7eb2e8f9f7 783 return DEVINFO->AUXHFRCOCAL3;
<> 144:ef7eb2e8f9f7 784
<> 144:ef7eb2e8f9f7 785 case cmuAUXHFRCOFreq_13M0Hz:
<> 144:ef7eb2e8f9f7 786 return DEVINFO->AUXHFRCOCAL6;
<> 144:ef7eb2e8f9f7 787
<> 144:ef7eb2e8f9f7 788 case cmuAUXHFRCOFreq_16M0Hz:
<> 144:ef7eb2e8f9f7 789 return DEVINFO->AUXHFRCOCAL7;
<> 144:ef7eb2e8f9f7 790
<> 144:ef7eb2e8f9f7 791 case cmuAUXHFRCOFreq_19M0Hz:
<> 144:ef7eb2e8f9f7 792 return DEVINFO->AUXHFRCOCAL8;
<> 144:ef7eb2e8f9f7 793
<> 144:ef7eb2e8f9f7 794 case cmuAUXHFRCOFreq_26M0Hz:
<> 144:ef7eb2e8f9f7 795 return DEVINFO->AUXHFRCOCAL10;
<> 144:ef7eb2e8f9f7 796
<> 144:ef7eb2e8f9f7 797 case cmuAUXHFRCOFreq_32M0Hz:
<> 144:ef7eb2e8f9f7 798 return DEVINFO->AUXHFRCOCAL11;
<> 144:ef7eb2e8f9f7 799
<> 144:ef7eb2e8f9f7 800 case cmuAUXHFRCOFreq_38M0Hz:
<> 144:ef7eb2e8f9f7 801 return DEVINFO->AUXHFRCOCAL12;
<> 144:ef7eb2e8f9f7 802
<> 144:ef7eb2e8f9f7 803 default: /* cmuAUXHFRCOFreq_UserDefined */
<> 144:ef7eb2e8f9f7 804 return 0;
<> 144:ef7eb2e8f9f7 805 }
<> 144:ef7eb2e8f9f7 806 }
<> 144:ef7eb2e8f9f7 807 #endif /* _CMU_AUXHFRCOCTRL_FREQRANGE_MASK */
<> 144:ef7eb2e8f9f7 808
<> 144:ef7eb2e8f9f7 809
<> 144:ef7eb2e8f9f7 810 #if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
<> 144:ef7eb2e8f9f7 811 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 812 * @brief
<> 150:02e0a0aed4ec 813 * Get current AUXHFRCO frequency.
<> 144:ef7eb2e8f9f7 814 *
<> 144:ef7eb2e8f9f7 815 * @return
<> 150:02e0a0aed4ec 816 * AUXHFRCO frequency
<> 144:ef7eb2e8f9f7 817 ******************************************************************************/
<> 150:02e0a0aed4ec 818 CMU_AUXHFRCOFreq_TypeDef CMU_AUXHFRCOBandGet(void)
<> 144:ef7eb2e8f9f7 819 {
<> 144:ef7eb2e8f9f7 820 return auxHfrcoFreq;
<> 144:ef7eb2e8f9f7 821 }
<> 144:ef7eb2e8f9f7 822 #endif /* _CMU_AUXHFRCOCTRL_FREQRANGE_MASK */
<> 144:ef7eb2e8f9f7 823
<> 144:ef7eb2e8f9f7 824
<> 144:ef7eb2e8f9f7 825 #if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
<> 144:ef7eb2e8f9f7 826 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 827 * @brief
<> 150:02e0a0aed4ec 828 * Set AUXHFRCO calibration for the selected target frequency.
<> 144:ef7eb2e8f9f7 829 *
<> 150:02e0a0aed4ec 830 * @param[in] setFreq
<> 144:ef7eb2e8f9f7 831 * AUXHFRCO frequency to set
<> 144:ef7eb2e8f9f7 832 ******************************************************************************/
<> 150:02e0a0aed4ec 833 void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOFreq_TypeDef setFreq)
<> 144:ef7eb2e8f9f7 834 {
<> 144:ef7eb2e8f9f7 835 uint32_t freqCal;
<> 144:ef7eb2e8f9f7 836
<> 144:ef7eb2e8f9f7 837 /* Get DEVINFO index, set global auxHfrcoFreq */
<> 150:02e0a0aed4ec 838 freqCal = CMU_AUXHFRCODevinfoGet(setFreq);
<> 144:ef7eb2e8f9f7 839 EFM_ASSERT((freqCal != 0) && (freqCal != UINT_MAX));
<> 150:02e0a0aed4ec 840 auxHfrcoFreq = setFreq;
<> 144:ef7eb2e8f9f7 841
<> 144:ef7eb2e8f9f7 842 /* Wait for any previous sync to complete, and then set calibration data
<> 144:ef7eb2e8f9f7 843 for the selected frequency. */
<> 144:ef7eb2e8f9f7 844 while(BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT));
<> 144:ef7eb2e8f9f7 845
<> 144:ef7eb2e8f9f7 846 /* Set divider in AUXHFRCOCTRL for 1, 2 and 4MHz */
<> 150:02e0a0aed4ec 847 switch(setFreq)
<> 144:ef7eb2e8f9f7 848 {
<> 144:ef7eb2e8f9f7 849 case cmuAUXHFRCOFreq_1M0Hz:
<> 144:ef7eb2e8f9f7 850 freqCal = (freqCal & ~_CMU_AUXHFRCOCTRL_CLKDIV_MASK)
<> 144:ef7eb2e8f9f7 851 | CMU_AUXHFRCOCTRL_CLKDIV_DIV4;
<> 144:ef7eb2e8f9f7 852 break;
<> 144:ef7eb2e8f9f7 853
<> 144:ef7eb2e8f9f7 854 case cmuAUXHFRCOFreq_2M0Hz:
<> 144:ef7eb2e8f9f7 855 freqCal = (freqCal & ~_CMU_AUXHFRCOCTRL_CLKDIV_MASK)
<> 144:ef7eb2e8f9f7 856 | CMU_AUXHFRCOCTRL_CLKDIV_DIV2;
<> 144:ef7eb2e8f9f7 857 break;
<> 144:ef7eb2e8f9f7 858
<> 144:ef7eb2e8f9f7 859 case cmuAUXHFRCOFreq_4M0Hz:
<> 144:ef7eb2e8f9f7 860 freqCal = (freqCal & ~_CMU_AUXHFRCOCTRL_CLKDIV_MASK)
<> 144:ef7eb2e8f9f7 861 | CMU_AUXHFRCOCTRL_CLKDIV_DIV1;
<> 144:ef7eb2e8f9f7 862 break;
<> 144:ef7eb2e8f9f7 863
<> 144:ef7eb2e8f9f7 864 default:
<> 144:ef7eb2e8f9f7 865 break;
<> 144:ef7eb2e8f9f7 866 }
<> 144:ef7eb2e8f9f7 867 CMU->AUXHFRCOCTRL = freqCal;
<> 144:ef7eb2e8f9f7 868 }
<> 144:ef7eb2e8f9f7 869 #endif /* _CMU_AUXHFRCOCTRL_FREQRANGE_MASK */
<> 144:ef7eb2e8f9f7 870
<> 144:ef7eb2e8f9f7 871
<> 144:ef7eb2e8f9f7 872 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 873 * @brief
<> 144:ef7eb2e8f9f7 874 * Calibrate clock.
<> 144:ef7eb2e8f9f7 875 *
<> 144:ef7eb2e8f9f7 876 * @details
<> 144:ef7eb2e8f9f7 877 * Run a calibration for HFCLK against a selectable reference clock. Please
<> 144:ef7eb2e8f9f7 878 * refer to the reference manual, CMU chapter, for further details.
<> 144:ef7eb2e8f9f7 879 *
<> 144:ef7eb2e8f9f7 880 * @note
<> 144:ef7eb2e8f9f7 881 * This function will not return until calibration measurement is completed.
<> 144:ef7eb2e8f9f7 882 *
<> 144:ef7eb2e8f9f7 883 * @param[in] HFCycles
<> 144:ef7eb2e8f9f7 884 * The number of HFCLK cycles to run calibration. Increasing this number
<> 144:ef7eb2e8f9f7 885 * increases precision, but the calibration will take more time.
<> 144:ef7eb2e8f9f7 886 *
<> 144:ef7eb2e8f9f7 887 * @param[in] ref
<> 144:ef7eb2e8f9f7 888 * The reference clock used to compare HFCLK with.
<> 144:ef7eb2e8f9f7 889 *
<> 144:ef7eb2e8f9f7 890 * @return
<> 144:ef7eb2e8f9f7 891 * The number of ticks the reference clock after HFCycles ticks on the HF
<> 144:ef7eb2e8f9f7 892 * clock.
<> 144:ef7eb2e8f9f7 893 ******************************************************************************/
<> 144:ef7eb2e8f9f7 894 uint32_t CMU_Calibrate(uint32_t HFCycles, CMU_Osc_TypeDef ref)
<> 144:ef7eb2e8f9f7 895 {
<> 144:ef7eb2e8f9f7 896 EFM_ASSERT(HFCycles <= (_CMU_CALCNT_CALCNT_MASK >> _CMU_CALCNT_CALCNT_SHIFT));
<> 144:ef7eb2e8f9f7 897
<> 144:ef7eb2e8f9f7 898 /* Set reference clock source */
<> 144:ef7eb2e8f9f7 899 switch (ref)
<> 144:ef7eb2e8f9f7 900 {
<> 144:ef7eb2e8f9f7 901 case cmuOsc_LFXO:
<> 144:ef7eb2e8f9f7 902 CMU->CALCTRL = CMU_CALCTRL_UPSEL_LFXO;
<> 144:ef7eb2e8f9f7 903 break;
<> 144:ef7eb2e8f9f7 904
<> 144:ef7eb2e8f9f7 905 case cmuOsc_LFRCO:
<> 144:ef7eb2e8f9f7 906 CMU->CALCTRL = CMU_CALCTRL_UPSEL_LFRCO;
<> 144:ef7eb2e8f9f7 907 break;
<> 144:ef7eb2e8f9f7 908
<> 144:ef7eb2e8f9f7 909 case cmuOsc_HFXO:
<> 144:ef7eb2e8f9f7 910 CMU->CALCTRL = CMU_CALCTRL_UPSEL_HFXO;
<> 144:ef7eb2e8f9f7 911 break;
<> 144:ef7eb2e8f9f7 912
<> 144:ef7eb2e8f9f7 913 case cmuOsc_HFRCO:
<> 144:ef7eb2e8f9f7 914 CMU->CALCTRL = CMU_CALCTRL_UPSEL_HFRCO;
<> 144:ef7eb2e8f9f7 915 break;
<> 144:ef7eb2e8f9f7 916
<> 144:ef7eb2e8f9f7 917 case cmuOsc_AUXHFRCO:
<> 144:ef7eb2e8f9f7 918 CMU->CALCTRL = CMU_CALCTRL_UPSEL_AUXHFRCO;
<> 144:ef7eb2e8f9f7 919 break;
<> 144:ef7eb2e8f9f7 920
<> 144:ef7eb2e8f9f7 921 default:
<> 144:ef7eb2e8f9f7 922 EFM_ASSERT(0);
<> 144:ef7eb2e8f9f7 923 return 0;
<> 144:ef7eb2e8f9f7 924 }
<> 144:ef7eb2e8f9f7 925
<> 144:ef7eb2e8f9f7 926 /* Set top value */
<> 144:ef7eb2e8f9f7 927 CMU->CALCNT = HFCycles;
<> 144:ef7eb2e8f9f7 928
<> 144:ef7eb2e8f9f7 929 /* Start calibration */
<> 144:ef7eb2e8f9f7 930 CMU->CMD = CMU_CMD_CALSTART;
<> 144:ef7eb2e8f9f7 931
<> 144:ef7eb2e8f9f7 932 #if defined( CMU_STATUS_CALRDY )
<> 144:ef7eb2e8f9f7 933 /* Wait until calibration completes */
<> 144:ef7eb2e8f9f7 934 while (!BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALRDY_SHIFT))
<> 144:ef7eb2e8f9f7 935 {
<> 144:ef7eb2e8f9f7 936 }
<> 144:ef7eb2e8f9f7 937 #else
<> 144:ef7eb2e8f9f7 938 /* Wait until calibration completes */
<> 144:ef7eb2e8f9f7 939 while (BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALBSY_SHIFT))
<> 144:ef7eb2e8f9f7 940 {
<> 144:ef7eb2e8f9f7 941 }
<> 144:ef7eb2e8f9f7 942 #endif
<> 144:ef7eb2e8f9f7 943
<> 144:ef7eb2e8f9f7 944 return CMU->CALCNT;
<> 144:ef7eb2e8f9f7 945 }
<> 144:ef7eb2e8f9f7 946
<> 144:ef7eb2e8f9f7 947
<> 144:ef7eb2e8f9f7 948 #if defined( _CMU_CALCTRL_UPSEL_MASK ) && defined( _CMU_CALCTRL_DOWNSEL_MASK )
<> 144:ef7eb2e8f9f7 949 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 950 * @brief
<> 144:ef7eb2e8f9f7 951 * Configure clock calibration
<> 144:ef7eb2e8f9f7 952 *
<> 144:ef7eb2e8f9f7 953 * @details
<> 144:ef7eb2e8f9f7 954 * Configure a calibration for a selectable clock source against another
<> 144:ef7eb2e8f9f7 955 * selectable reference clock.
<> 144:ef7eb2e8f9f7 956 * Refer to the reference manual, CMU chapter, for further details.
<> 144:ef7eb2e8f9f7 957 *
<> 144:ef7eb2e8f9f7 958 * @note
<> 144:ef7eb2e8f9f7 959 * After configuration, a call to CMU_CalibrateStart() is required, and
<> 144:ef7eb2e8f9f7 960 * the resulting calibration value can be read out with the
<> 144:ef7eb2e8f9f7 961 * CMU_CalibrateCountGet() function call.
<> 144:ef7eb2e8f9f7 962 *
<> 144:ef7eb2e8f9f7 963 * @param[in] downCycles
<> 144:ef7eb2e8f9f7 964 * The number of downSel clock cycles to run calibration. Increasing this
<> 144:ef7eb2e8f9f7 965 * number increases precision, but the calibration will take more time.
<> 144:ef7eb2e8f9f7 966 *
<> 144:ef7eb2e8f9f7 967 * @param[in] downSel
<> 144:ef7eb2e8f9f7 968 * The clock which will be counted down downCycles
<> 144:ef7eb2e8f9f7 969 *
<> 144:ef7eb2e8f9f7 970 * @param[in] upSel
<> 144:ef7eb2e8f9f7 971 * The reference clock, the number of cycles generated by this clock will
<> 144:ef7eb2e8f9f7 972 * be counted and added up, the result can be given with the
<> 144:ef7eb2e8f9f7 973 * CMU_CalibrateCountGet() function call.
<> 144:ef7eb2e8f9f7 974 ******************************************************************************/
<> 144:ef7eb2e8f9f7 975 void CMU_CalibrateConfig(uint32_t downCycles, CMU_Osc_TypeDef downSel,
<> 144:ef7eb2e8f9f7 976 CMU_Osc_TypeDef upSel)
<> 144:ef7eb2e8f9f7 977 {
<> 144:ef7eb2e8f9f7 978 /* Keep untouched configuration settings */
<> 144:ef7eb2e8f9f7 979 uint32_t calCtrl = CMU->CALCTRL
<> 144:ef7eb2e8f9f7 980 & ~(_CMU_CALCTRL_UPSEL_MASK | _CMU_CALCTRL_DOWNSEL_MASK);
<> 144:ef7eb2e8f9f7 981
<> 144:ef7eb2e8f9f7 982 /* 20 bits of precision to calibration count register */
<> 144:ef7eb2e8f9f7 983 EFM_ASSERT(downCycles <= (_CMU_CALCNT_CALCNT_MASK >> _CMU_CALCNT_CALCNT_SHIFT));
<> 144:ef7eb2e8f9f7 984
<> 144:ef7eb2e8f9f7 985 /* Set down counting clock source - down counter */
<> 144:ef7eb2e8f9f7 986 switch (downSel)
<> 144:ef7eb2e8f9f7 987 {
<> 144:ef7eb2e8f9f7 988 case cmuOsc_LFXO:
<> 144:ef7eb2e8f9f7 989 calCtrl |= CMU_CALCTRL_DOWNSEL_LFXO;
<> 144:ef7eb2e8f9f7 990 break;
<> 144:ef7eb2e8f9f7 991
<> 144:ef7eb2e8f9f7 992 case cmuOsc_LFRCO:
<> 144:ef7eb2e8f9f7 993 calCtrl |= CMU_CALCTRL_DOWNSEL_LFRCO;
<> 144:ef7eb2e8f9f7 994 break;
<> 144:ef7eb2e8f9f7 995
<> 144:ef7eb2e8f9f7 996 case cmuOsc_HFXO:
<> 144:ef7eb2e8f9f7 997 calCtrl |= CMU_CALCTRL_DOWNSEL_HFXO;
<> 144:ef7eb2e8f9f7 998 break;
<> 144:ef7eb2e8f9f7 999
<> 144:ef7eb2e8f9f7 1000 case cmuOsc_HFRCO:
<> 144:ef7eb2e8f9f7 1001 calCtrl |= CMU_CALCTRL_DOWNSEL_HFRCO;
<> 144:ef7eb2e8f9f7 1002 break;
<> 144:ef7eb2e8f9f7 1003
<> 144:ef7eb2e8f9f7 1004 case cmuOsc_AUXHFRCO:
<> 144:ef7eb2e8f9f7 1005 calCtrl |= CMU_CALCTRL_DOWNSEL_AUXHFRCO;
<> 144:ef7eb2e8f9f7 1006 break;
<> 144:ef7eb2e8f9f7 1007
<> 144:ef7eb2e8f9f7 1008 default:
<> 144:ef7eb2e8f9f7 1009 EFM_ASSERT(0);
<> 144:ef7eb2e8f9f7 1010 break;
<> 144:ef7eb2e8f9f7 1011 }
<> 144:ef7eb2e8f9f7 1012
<> 144:ef7eb2e8f9f7 1013 /* Set top value to be counted down by the downSel clock */
<> 144:ef7eb2e8f9f7 1014 CMU->CALCNT = downCycles;
<> 144:ef7eb2e8f9f7 1015
<> 144:ef7eb2e8f9f7 1016 /* Set reference clock source - up counter */
<> 144:ef7eb2e8f9f7 1017 switch (upSel)
<> 144:ef7eb2e8f9f7 1018 {
<> 144:ef7eb2e8f9f7 1019 case cmuOsc_LFXO:
<> 144:ef7eb2e8f9f7 1020 calCtrl |= CMU_CALCTRL_UPSEL_LFXO;
<> 144:ef7eb2e8f9f7 1021 break;
<> 144:ef7eb2e8f9f7 1022
<> 144:ef7eb2e8f9f7 1023 case cmuOsc_LFRCO:
<> 144:ef7eb2e8f9f7 1024 calCtrl |= CMU_CALCTRL_UPSEL_LFRCO;
<> 144:ef7eb2e8f9f7 1025 break;
<> 144:ef7eb2e8f9f7 1026
<> 144:ef7eb2e8f9f7 1027 case cmuOsc_HFXO:
<> 144:ef7eb2e8f9f7 1028 calCtrl |= CMU_CALCTRL_UPSEL_HFXO;
<> 144:ef7eb2e8f9f7 1029 break;
<> 144:ef7eb2e8f9f7 1030
<> 144:ef7eb2e8f9f7 1031 case cmuOsc_HFRCO:
<> 144:ef7eb2e8f9f7 1032 calCtrl |= CMU_CALCTRL_UPSEL_HFRCO;
<> 144:ef7eb2e8f9f7 1033 break;
<> 144:ef7eb2e8f9f7 1034
<> 144:ef7eb2e8f9f7 1035 case cmuOsc_AUXHFRCO:
<> 144:ef7eb2e8f9f7 1036 calCtrl |= CMU_CALCTRL_UPSEL_AUXHFRCO;
<> 144:ef7eb2e8f9f7 1037 break;
<> 144:ef7eb2e8f9f7 1038
<> 144:ef7eb2e8f9f7 1039 default:
<> 144:ef7eb2e8f9f7 1040 EFM_ASSERT(0);
<> 144:ef7eb2e8f9f7 1041 break;
<> 144:ef7eb2e8f9f7 1042 }
<> 144:ef7eb2e8f9f7 1043
<> 144:ef7eb2e8f9f7 1044 CMU->CALCTRL = calCtrl;
<> 144:ef7eb2e8f9f7 1045 }
<> 144:ef7eb2e8f9f7 1046 #endif
<> 144:ef7eb2e8f9f7 1047
<> 144:ef7eb2e8f9f7 1048
<> 144:ef7eb2e8f9f7 1049 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 1050 * @brief
<> 144:ef7eb2e8f9f7 1051 * Get calibration count register
<> 144:ef7eb2e8f9f7 1052 * @note
<> 144:ef7eb2e8f9f7 1053 * If continuous calibrartion mode is active, calibration busy will almost
<> 144:ef7eb2e8f9f7 1054 * always be off, and we just need to read the value, where the normal case
<> 144:ef7eb2e8f9f7 1055 * would be that this function call has been triggered by the CALRDY
<> 144:ef7eb2e8f9f7 1056 * interrupt flag.
<> 144:ef7eb2e8f9f7 1057 * @return
<> 144:ef7eb2e8f9f7 1058 * Calibration count, the number of UPSEL clocks (see CMU_CalibrateConfig)
<> 144:ef7eb2e8f9f7 1059 * in the period of DOWNSEL oscillator clock cycles configured by a previous
<> 144:ef7eb2e8f9f7 1060 * write operation to CMU->CALCNT
<> 144:ef7eb2e8f9f7 1061 ******************************************************************************/
<> 144:ef7eb2e8f9f7 1062 uint32_t CMU_CalibrateCountGet(void)
<> 144:ef7eb2e8f9f7 1063 {
<> 144:ef7eb2e8f9f7 1064 /* Wait until calibration completes, UNLESS continuous calibration mode is */
<> 144:ef7eb2e8f9f7 1065 /* active */
<> 144:ef7eb2e8f9f7 1066 #if defined( CMU_CALCTRL_CONT )
<> 144:ef7eb2e8f9f7 1067 if (!BUS_RegBitRead(&CMU->CALCTRL, _CMU_CALCTRL_CONT_SHIFT))
<> 144:ef7eb2e8f9f7 1068 {
<> 144:ef7eb2e8f9f7 1069 #if defined( CMU_STATUS_CALRDY )
<> 144:ef7eb2e8f9f7 1070 /* Wait until calibration completes */
<> 144:ef7eb2e8f9f7 1071 while (!BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALRDY_SHIFT))
<> 144:ef7eb2e8f9f7 1072 {
<> 144:ef7eb2e8f9f7 1073 }
<> 144:ef7eb2e8f9f7 1074 #else
<> 144:ef7eb2e8f9f7 1075 /* Wait until calibration completes */
<> 144:ef7eb2e8f9f7 1076 while (BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALBSY_SHIFT))
<> 144:ef7eb2e8f9f7 1077 {
<> 144:ef7eb2e8f9f7 1078 }
<> 144:ef7eb2e8f9f7 1079 #endif
<> 144:ef7eb2e8f9f7 1080 }
<> 144:ef7eb2e8f9f7 1081 #else
<> 144:ef7eb2e8f9f7 1082 while (BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALBSY_SHIFT))
<> 144:ef7eb2e8f9f7 1083 {
<> 144:ef7eb2e8f9f7 1084 }
<> 144:ef7eb2e8f9f7 1085 #endif
<> 144:ef7eb2e8f9f7 1086 return CMU->CALCNT;
<> 144:ef7eb2e8f9f7 1087 }
<> 144:ef7eb2e8f9f7 1088
<> 144:ef7eb2e8f9f7 1089
<> 144:ef7eb2e8f9f7 1090 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 1091 * @brief
<> 144:ef7eb2e8f9f7 1092 * Get clock divisor/prescaler.
<> 144:ef7eb2e8f9f7 1093 *
<> 144:ef7eb2e8f9f7 1094 * @param[in] clock
<> 144:ef7eb2e8f9f7 1095 * Clock point to get divisor/prescaler for. Notice that not all clock points
<> 144:ef7eb2e8f9f7 1096 * have a divisor/prescaler. Please refer to CMU overview in reference manual.
<> 144:ef7eb2e8f9f7 1097 *
<> 144:ef7eb2e8f9f7 1098 * @return
<> 144:ef7eb2e8f9f7 1099 * The current clock point divisor/prescaler. 1 is returned
<> 144:ef7eb2e8f9f7 1100 * if @p clock specifies a clock point without a divisor/prescaler.
<> 144:ef7eb2e8f9f7 1101 ******************************************************************************/
<> 144:ef7eb2e8f9f7 1102 CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock)
<> 144:ef7eb2e8f9f7 1103 {
<> 144:ef7eb2e8f9f7 1104 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
<> 144:ef7eb2e8f9f7 1105 return 1 + (uint32_t)CMU_ClockPrescGet(clock);
<> 144:ef7eb2e8f9f7 1106
<> 144:ef7eb2e8f9f7 1107 #elif defined( _SILICON_LABS_32B_PLATFORM_1 )
<> 144:ef7eb2e8f9f7 1108 uint32_t divReg;
<> 144:ef7eb2e8f9f7 1109 CMU_ClkDiv_TypeDef ret;
<> 144:ef7eb2e8f9f7 1110
<> 144:ef7eb2e8f9f7 1111 /* Get divisor reg id */
<> 144:ef7eb2e8f9f7 1112 divReg = (clock >> CMU_DIV_REG_POS) & CMU_DIV_REG_MASK;
<> 144:ef7eb2e8f9f7 1113
<> 144:ef7eb2e8f9f7 1114 switch (divReg)
<> 144:ef7eb2e8f9f7 1115 {
<> 144:ef7eb2e8f9f7 1116 #if defined( _CMU_CTRL_HFCLKDIV_MASK )
<> 144:ef7eb2e8f9f7 1117 case CMU_HFCLKDIV_REG:
<> 144:ef7eb2e8f9f7 1118 ret = 1 + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK)
<> 144:ef7eb2e8f9f7 1119 >> _CMU_CTRL_HFCLKDIV_SHIFT);
<> 144:ef7eb2e8f9f7 1120 break;
<> 144:ef7eb2e8f9f7 1121 #endif
<> 144:ef7eb2e8f9f7 1122
<> 144:ef7eb2e8f9f7 1123 case CMU_HFPERCLKDIV_REG:
<> 144:ef7eb2e8f9f7 1124 ret = (CMU_ClkDiv_TypeDef)((CMU->HFPERCLKDIV
<> 144:ef7eb2e8f9f7 1125 & _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK)
<> 144:ef7eb2e8f9f7 1126 >> _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT);
<> 144:ef7eb2e8f9f7 1127 ret = CMU_Log2ToDiv(ret);
<> 144:ef7eb2e8f9f7 1128 break;
<> 144:ef7eb2e8f9f7 1129
<> 144:ef7eb2e8f9f7 1130 case CMU_HFCORECLKDIV_REG:
<> 144:ef7eb2e8f9f7 1131 ret = (CMU_ClkDiv_TypeDef)((CMU->HFCORECLKDIV
<> 144:ef7eb2e8f9f7 1132 & _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK)
<> 144:ef7eb2e8f9f7 1133 >> _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT);
<> 144:ef7eb2e8f9f7 1134 ret = CMU_Log2ToDiv(ret);
<> 144:ef7eb2e8f9f7 1135 break;
<> 144:ef7eb2e8f9f7 1136
<> 144:ef7eb2e8f9f7 1137 case CMU_LFAPRESC0_REG:
<> 144:ef7eb2e8f9f7 1138 switch (clock)
<> 144:ef7eb2e8f9f7 1139 {
<> 144:ef7eb2e8f9f7 1140 case cmuClock_RTC:
<> 144:ef7eb2e8f9f7 1141 ret = (CMU_ClkDiv_TypeDef)((CMU->LFAPRESC0 & _CMU_LFAPRESC0_RTC_MASK)
<> 144:ef7eb2e8f9f7 1142 >> _CMU_LFAPRESC0_RTC_SHIFT);
<> 144:ef7eb2e8f9f7 1143 ret = CMU_Log2ToDiv(ret);
<> 144:ef7eb2e8f9f7 1144 break;
<> 144:ef7eb2e8f9f7 1145
<> 144:ef7eb2e8f9f7 1146 #if defined(_CMU_LFAPRESC0_LETIMER0_MASK)
<> 144:ef7eb2e8f9f7 1147 case cmuClock_LETIMER0:
<> 144:ef7eb2e8f9f7 1148 ret = (CMU_ClkDiv_TypeDef)((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK)
<> 144:ef7eb2e8f9f7 1149 >> _CMU_LFAPRESC0_LETIMER0_SHIFT);
<> 144:ef7eb2e8f9f7 1150 ret = CMU_Log2ToDiv(ret);
<> 144:ef7eb2e8f9f7 1151 break;
<> 144:ef7eb2e8f9f7 1152 #endif
<> 144:ef7eb2e8f9f7 1153
<> 144:ef7eb2e8f9f7 1154 #if defined(_CMU_LFAPRESC0_LCD_MASK)
<> 144:ef7eb2e8f9f7 1155 case cmuClock_LCDpre:
<> 144:ef7eb2e8f9f7 1156 ret = (CMU_ClkDiv_TypeDef)(((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK)
<> 144:ef7eb2e8f9f7 1157 >> _CMU_LFAPRESC0_LCD_SHIFT)
<> 144:ef7eb2e8f9f7 1158 + CMU_DivToLog2(cmuClkDiv_16));
<> 144:ef7eb2e8f9f7 1159 ret = CMU_Log2ToDiv(ret);
<> 144:ef7eb2e8f9f7 1160 break;
<> 144:ef7eb2e8f9f7 1161 #endif
<> 144:ef7eb2e8f9f7 1162
<> 144:ef7eb2e8f9f7 1163 #if defined(_CMU_LFAPRESC0_LESENSE_MASK)
<> 144:ef7eb2e8f9f7 1164 case cmuClock_LESENSE:
<> 144:ef7eb2e8f9f7 1165 ret = (CMU_ClkDiv_TypeDef)((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LESENSE_MASK)
<> 144:ef7eb2e8f9f7 1166 >> _CMU_LFAPRESC0_LESENSE_SHIFT);
<> 144:ef7eb2e8f9f7 1167 ret = CMU_Log2ToDiv(ret);
<> 144:ef7eb2e8f9f7 1168 break;
<> 144:ef7eb2e8f9f7 1169 #endif
<> 144:ef7eb2e8f9f7 1170
<> 144:ef7eb2e8f9f7 1171 default:
<> 144:ef7eb2e8f9f7 1172 EFM_ASSERT(0);
<> 144:ef7eb2e8f9f7 1173 ret = cmuClkDiv_1;
<> 144:ef7eb2e8f9f7 1174 break;
<> 144:ef7eb2e8f9f7 1175 }
<> 144:ef7eb2e8f9f7 1176 break;
<> 144:ef7eb2e8f9f7 1177
<> 144:ef7eb2e8f9f7 1178 case CMU_LFBPRESC0_REG:
<> 144:ef7eb2e8f9f7 1179 switch (clock)
<> 144:ef7eb2e8f9f7 1180 {
<> 144:ef7eb2e8f9f7 1181 #if defined(_CMU_LFBPRESC0_LEUART0_MASK)
<> 144:ef7eb2e8f9f7 1182 case cmuClock_LEUART0:
<> 144:ef7eb2e8f9f7 1183 ret = (CMU_ClkDiv_TypeDef)((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK)
<> 144:ef7eb2e8f9f7 1184 >> _CMU_LFBPRESC0_LEUART0_SHIFT);
<> 144:ef7eb2e8f9f7 1185 ret = CMU_Log2ToDiv(ret);
<> 144:ef7eb2e8f9f7 1186 break;
<> 144:ef7eb2e8f9f7 1187 #endif
<> 144:ef7eb2e8f9f7 1188
<> 144:ef7eb2e8f9f7 1189 #if defined(_CMU_LFBPRESC0_LEUART1_MASK)
<> 144:ef7eb2e8f9f7 1190 case cmuClock_LEUART1:
<> 144:ef7eb2e8f9f7 1191 ret = (CMU_ClkDiv_TypeDef)((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK)
<> 144:ef7eb2e8f9f7 1192 >> _CMU_LFBPRESC0_LEUART1_SHIFT);
<> 144:ef7eb2e8f9f7 1193 ret = CMU_Log2ToDiv(ret);
<> 144:ef7eb2e8f9f7 1194 break;
<> 144:ef7eb2e8f9f7 1195 #endif
<> 144:ef7eb2e8f9f7 1196
<> 144:ef7eb2e8f9f7 1197 default:
<> 144:ef7eb2e8f9f7 1198 EFM_ASSERT(0);
<> 144:ef7eb2e8f9f7 1199 ret = cmuClkDiv_1;
<> 144:ef7eb2e8f9f7 1200 break;
<> 144:ef7eb2e8f9f7 1201 }
<> 144:ef7eb2e8f9f7 1202 break;
<> 144:ef7eb2e8f9f7 1203
<> 144:ef7eb2e8f9f7 1204 default:
<> 144:ef7eb2e8f9f7 1205 EFM_ASSERT(0);
<> 144:ef7eb2e8f9f7 1206 ret = cmuClkDiv_1;
<> 144:ef7eb2e8f9f7 1207 break;
<> 144:ef7eb2e8f9f7 1208 }
<> 144:ef7eb2e8f9f7 1209
<> 144:ef7eb2e8f9f7 1210 return ret;
<> 144:ef7eb2e8f9f7 1211 #endif
<> 144:ef7eb2e8f9f7 1212 }
<> 144:ef7eb2e8f9f7 1213
<> 144:ef7eb2e8f9f7 1214
<> 144:ef7eb2e8f9f7 1215 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 1216 * @brief
<> 144:ef7eb2e8f9f7 1217 * Set clock divisor/prescaler.
<> 144:ef7eb2e8f9f7 1218 *
<> 144:ef7eb2e8f9f7 1219 * @note
<> 144:ef7eb2e8f9f7 1220 * If setting a LF clock prescaler, synchronization into the low frequency
<> 144:ef7eb2e8f9f7 1221 * domain is required. If the same register is modified before a previous
<> 144:ef7eb2e8f9f7 1222 * update has completed, this function will stall until the previous
<> 144:ef7eb2e8f9f7 1223 * synchronization has completed. Please refer to CMU_FreezeEnable() for
<> 144:ef7eb2e8f9f7 1224 * a suggestion on how to reduce stalling time in some use cases.
<> 144:ef7eb2e8f9f7 1225 *
<> 144:ef7eb2e8f9f7 1226 * @param[in] clock
<> 144:ef7eb2e8f9f7 1227 * Clock point to set divisor/prescaler for. Notice that not all clock points
<> 144:ef7eb2e8f9f7 1228 * have a divisor/prescaler, please refer to CMU overview in the reference
<> 144:ef7eb2e8f9f7 1229 * manual.
<> 144:ef7eb2e8f9f7 1230 *
<> 144:ef7eb2e8f9f7 1231 * @param[in] div
<> 144:ef7eb2e8f9f7 1232 * The clock divisor to use (<= cmuClkDiv_512).
<> 144:ef7eb2e8f9f7 1233 ******************************************************************************/
<> 144:ef7eb2e8f9f7 1234 void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div)
<> 144:ef7eb2e8f9f7 1235 {
<> 144:ef7eb2e8f9f7 1236 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
<> 144:ef7eb2e8f9f7 1237 CMU_ClockPrescSet(clock, (CMU_ClkPresc_TypeDef)(div - 1));
<> 144:ef7eb2e8f9f7 1238
<> 144:ef7eb2e8f9f7 1239 #elif defined( _SILICON_LABS_32B_PLATFORM_1 )
<> 144:ef7eb2e8f9f7 1240 uint32_t freq;
<> 144:ef7eb2e8f9f7 1241 uint32_t divReg;
<> 144:ef7eb2e8f9f7 1242
<> 144:ef7eb2e8f9f7 1243 /* Get divisor reg id */
<> 144:ef7eb2e8f9f7 1244 divReg = (clock >> CMU_DIV_REG_POS) & CMU_DIV_REG_MASK;
<> 144:ef7eb2e8f9f7 1245
<> 144:ef7eb2e8f9f7 1246 switch (divReg)
<> 144:ef7eb2e8f9f7 1247 {
<> 144:ef7eb2e8f9f7 1248 #if defined( _CMU_CTRL_HFCLKDIV_MASK )
<> 144:ef7eb2e8f9f7 1249 case CMU_HFCLKDIV_REG:
<> 144:ef7eb2e8f9f7 1250 EFM_ASSERT((div>=cmuClkDiv_1) && (div<=cmuClkDiv_8));
<> 144:ef7eb2e8f9f7 1251
<> 144:ef7eb2e8f9f7 1252 /* Configure worst case wait states for flash access before setting divisor */
<> 144:ef7eb2e8f9f7 1253 flashWaitStateMax();
<> 144:ef7eb2e8f9f7 1254
<> 144:ef7eb2e8f9f7 1255 /* Set divider */
<> 144:ef7eb2e8f9f7 1256 CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFCLKDIV_MASK)
<> 144:ef7eb2e8f9f7 1257 | ((div-1) << _CMU_CTRL_HFCLKDIV_SHIFT);
<> 144:ef7eb2e8f9f7 1258
<> 144:ef7eb2e8f9f7 1259 /* Update CMSIS core clock variable */
<> 144:ef7eb2e8f9f7 1260 /* (The function will update the global variable) */
<> 144:ef7eb2e8f9f7 1261 freq = SystemCoreClockGet();
<> 144:ef7eb2e8f9f7 1262
<> 144:ef7eb2e8f9f7 1263 /* Optimize flash access wait state setting for current core clk */
<> 144:ef7eb2e8f9f7 1264 flashWaitStateControl(freq);
<> 144:ef7eb2e8f9f7 1265 break;
<> 144:ef7eb2e8f9f7 1266 #endif
<> 144:ef7eb2e8f9f7 1267
<> 144:ef7eb2e8f9f7 1268 case CMU_HFPERCLKDIV_REG:
<> 144:ef7eb2e8f9f7 1269 EFM_ASSERT((div >= cmuClkDiv_1) && (div <= cmuClkDiv_512));
<> 144:ef7eb2e8f9f7 1270 /* Convert to correct scale */
<> 144:ef7eb2e8f9f7 1271 div = CMU_DivToLog2(div);
<> 144:ef7eb2e8f9f7 1272 CMU->HFPERCLKDIV = (CMU->HFPERCLKDIV & ~_CMU_HFPERCLKDIV_HFPERCLKDIV_MASK)
<> 144:ef7eb2e8f9f7 1273 | (div << _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT);
<> 144:ef7eb2e8f9f7 1274 break;
<> 144:ef7eb2e8f9f7 1275
<> 144:ef7eb2e8f9f7 1276 case CMU_HFCORECLKDIV_REG:
<> 150:02e0a0aed4ec 1277 EFM_ASSERT((div >= cmuClkDiv_1) && (div <= cmuClkDiv_512));
<> 144:ef7eb2e8f9f7 1278
<> 144:ef7eb2e8f9f7 1279 /* Configure worst case wait states for flash access before setting divisor */
<> 144:ef7eb2e8f9f7 1280 flashWaitStateMax();
<> 144:ef7eb2e8f9f7 1281
<> 150:02e0a0aed4ec 1282 #if defined( CMU_MAX_FREQ_HFLE )
<> 150:02e0a0aed4ec 1283 setHfLeConfig(SystemHFClockGet() / div, CMU_MAX_FREQ_HFLE);
<> 144:ef7eb2e8f9f7 1284 #endif
<> 144:ef7eb2e8f9f7 1285
<> 144:ef7eb2e8f9f7 1286 /* Convert to correct scale */
<> 144:ef7eb2e8f9f7 1287 div = CMU_DivToLog2(div);
<> 144:ef7eb2e8f9f7 1288
<> 144:ef7eb2e8f9f7 1289 CMU->HFCORECLKDIV = (CMU->HFCORECLKDIV
<> 144:ef7eb2e8f9f7 1290 & ~_CMU_HFCORECLKDIV_HFCORECLKDIV_MASK)
<> 144:ef7eb2e8f9f7 1291 | (div << _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT);
<> 144:ef7eb2e8f9f7 1292
<> 144:ef7eb2e8f9f7 1293 /* Update CMSIS core clock variable */
<> 144:ef7eb2e8f9f7 1294 /* (The function will update the global variable) */
<> 144:ef7eb2e8f9f7 1295 freq = SystemCoreClockGet();
<> 144:ef7eb2e8f9f7 1296
<> 144:ef7eb2e8f9f7 1297 /* Optimize flash access wait state setting for current core clk */
<> 144:ef7eb2e8f9f7 1298 flashWaitStateControl(freq);
<> 144:ef7eb2e8f9f7 1299 break;
<> 144:ef7eb2e8f9f7 1300
<> 144:ef7eb2e8f9f7 1301 case CMU_LFAPRESC0_REG:
<> 144:ef7eb2e8f9f7 1302 switch (clock)
<> 144:ef7eb2e8f9f7 1303 {
<> 144:ef7eb2e8f9f7 1304 case cmuClock_RTC:
<> 144:ef7eb2e8f9f7 1305 EFM_ASSERT(div <= cmuClkDiv_32768);
<> 144:ef7eb2e8f9f7 1306
<> 144:ef7eb2e8f9f7 1307 /* LF register about to be modified require sync. busy check */
<> 144:ef7eb2e8f9f7 1308 syncReg(CMU_SYNCBUSY_LFAPRESC0);
<> 144:ef7eb2e8f9f7 1309
<> 144:ef7eb2e8f9f7 1310 /* Convert to correct scale */
<> 144:ef7eb2e8f9f7 1311 div = CMU_DivToLog2(div);
<> 144:ef7eb2e8f9f7 1312
<> 144:ef7eb2e8f9f7 1313 CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_RTC_MASK)
<> 144:ef7eb2e8f9f7 1314 | (div << _CMU_LFAPRESC0_RTC_SHIFT);
<> 144:ef7eb2e8f9f7 1315 break;
<> 144:ef7eb2e8f9f7 1316
<> 144:ef7eb2e8f9f7 1317 #if defined(_CMU_LFAPRESC0_LETIMER0_MASK)
<> 144:ef7eb2e8f9f7 1318 case cmuClock_LETIMER0:
<> 144:ef7eb2e8f9f7 1319 EFM_ASSERT(div <= cmuClkDiv_32768);
<> 144:ef7eb2e8f9f7 1320
<> 144:ef7eb2e8f9f7 1321 /* LF register about to be modified require sync. busy check */
<> 144:ef7eb2e8f9f7 1322 syncReg(CMU_SYNCBUSY_LFAPRESC0);
<> 144:ef7eb2e8f9f7 1323
<> 144:ef7eb2e8f9f7 1324 /* Convert to correct scale */
<> 144:ef7eb2e8f9f7 1325 div = CMU_DivToLog2(div);
<> 144:ef7eb2e8f9f7 1326
<> 144:ef7eb2e8f9f7 1327 CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LETIMER0_MASK)
<> 144:ef7eb2e8f9f7 1328 | (div << _CMU_LFAPRESC0_LETIMER0_SHIFT);
<> 144:ef7eb2e8f9f7 1329 break;
<> 144:ef7eb2e8f9f7 1330 #endif
<> 144:ef7eb2e8f9f7 1331
<> 144:ef7eb2e8f9f7 1332 #if defined(LCD_PRESENT)
<> 144:ef7eb2e8f9f7 1333 case cmuClock_LCDpre:
<> 144:ef7eb2e8f9f7 1334 EFM_ASSERT((div >= cmuClkDiv_16) && (div <= cmuClkDiv_128));
<> 144:ef7eb2e8f9f7 1335
<> 144:ef7eb2e8f9f7 1336 /* LF register about to be modified require sync. busy check */
<> 144:ef7eb2e8f9f7 1337 syncReg(CMU_SYNCBUSY_LFAPRESC0);
<> 144:ef7eb2e8f9f7 1338
<> 144:ef7eb2e8f9f7 1339 /* Convert to correct scale */
<> 144:ef7eb2e8f9f7 1340 div = CMU_DivToLog2(div);
<> 144:ef7eb2e8f9f7 1341
<> 144:ef7eb2e8f9f7 1342 CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LCD_MASK)
<> 144:ef7eb2e8f9f7 1343 | ((div - CMU_DivToLog2(cmuClkDiv_16))
<> 144:ef7eb2e8f9f7 1344 << _CMU_LFAPRESC0_LCD_SHIFT);
<> 144:ef7eb2e8f9f7 1345 break;
<> 144:ef7eb2e8f9f7 1346 #endif /* defined(LCD_PRESENT) */
<> 144:ef7eb2e8f9f7 1347
<> 144:ef7eb2e8f9f7 1348 #if defined(LESENSE_PRESENT)
<> 144:ef7eb2e8f9f7 1349 case cmuClock_LESENSE:
<> 144:ef7eb2e8f9f7 1350 EFM_ASSERT(div <= cmuClkDiv_8);
<> 144:ef7eb2e8f9f7 1351
<> 144:ef7eb2e8f9f7 1352 /* LF register about to be modified require sync. busy check */
<> 144:ef7eb2e8f9f7 1353 syncReg(CMU_SYNCBUSY_LFAPRESC0);
<> 144:ef7eb2e8f9f7 1354
<> 144:ef7eb2e8f9f7 1355 /* Convert to correct scale */
<> 144:ef7eb2e8f9f7 1356 div = CMU_DivToLog2(div);
<> 144:ef7eb2e8f9f7 1357
<> 144:ef7eb2e8f9f7 1358 CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LESENSE_MASK)
<> 144:ef7eb2e8f9f7 1359 | (div << _CMU_LFAPRESC0_LESENSE_SHIFT);
<> 144:ef7eb2e8f9f7 1360 break;
<> 144:ef7eb2e8f9f7 1361 #endif /* defined(LESENSE_PRESENT) */
<> 144:ef7eb2e8f9f7 1362
<> 144:ef7eb2e8f9f7 1363 default:
<> 144:ef7eb2e8f9f7 1364 EFM_ASSERT(0);
<> 144:ef7eb2e8f9f7 1365 break;
<> 144:ef7eb2e8f9f7 1366 }
<> 144:ef7eb2e8f9f7 1367 break;
<> 144:ef7eb2e8f9f7 1368
<> 144:ef7eb2e8f9f7 1369 case CMU_LFBPRESC0_REG:
<> 144:ef7eb2e8f9f7 1370 switch (clock)
<> 144:ef7eb2e8f9f7 1371 {
<> 144:ef7eb2e8f9f7 1372 #if defined(_CMU_LFBPRESC0_LEUART0_MASK)
<> 144:ef7eb2e8f9f7 1373 case cmuClock_LEUART0:
<> 144:ef7eb2e8f9f7 1374 EFM_ASSERT(div <= cmuClkDiv_8);
<> 144:ef7eb2e8f9f7 1375
<> 144:ef7eb2e8f9f7 1376 /* LF register about to be modified require sync. busy check */
<> 144:ef7eb2e8f9f7 1377 syncReg(CMU_SYNCBUSY_LFBPRESC0);
<> 144:ef7eb2e8f9f7 1378
<> 144:ef7eb2e8f9f7 1379 /* Convert to correct scale */
<> 144:ef7eb2e8f9f7 1380 div = CMU_DivToLog2(div);
<> 144:ef7eb2e8f9f7 1381
<> 144:ef7eb2e8f9f7 1382 CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART0_MASK)
<> 144:ef7eb2e8f9f7 1383 | (((uint32_t)div) << _CMU_LFBPRESC0_LEUART0_SHIFT);
<> 144:ef7eb2e8f9f7 1384 break;
<> 144:ef7eb2e8f9f7 1385 #endif
<> 144:ef7eb2e8f9f7 1386
<> 144:ef7eb2e8f9f7 1387 #if defined(_CMU_LFBPRESC0_LEUART1_MASK)
<> 144:ef7eb2e8f9f7 1388 case cmuClock_LEUART1:
<> 144:ef7eb2e8f9f7 1389 EFM_ASSERT(div <= cmuClkDiv_8);
<> 144:ef7eb2e8f9f7 1390
<> 144:ef7eb2e8f9f7 1391 /* LF register about to be modified require sync. busy check */
<> 144:ef7eb2e8f9f7 1392 syncReg(CMU_SYNCBUSY_LFBPRESC0);
<> 144:ef7eb2e8f9f7 1393
<> 144:ef7eb2e8f9f7 1394 /* Convert to correct scale */
<> 144:ef7eb2e8f9f7 1395 div = CMU_DivToLog2(div);
<> 144:ef7eb2e8f9f7 1396
<> 144:ef7eb2e8f9f7 1397 CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART1_MASK)
<> 144:ef7eb2e8f9f7 1398 | (((uint32_t)div) << _CMU_LFBPRESC0_LEUART1_SHIFT);
<> 144:ef7eb2e8f9f7 1399 break;
<> 144:ef7eb2e8f9f7 1400 #endif
<> 144:ef7eb2e8f9f7 1401
<> 144:ef7eb2e8f9f7 1402 default:
<> 144:ef7eb2e8f9f7 1403 EFM_ASSERT(0);
<> 144:ef7eb2e8f9f7 1404 break;
<> 144:ef7eb2e8f9f7 1405 }
<> 144:ef7eb2e8f9f7 1406 break;
<> 144:ef7eb2e8f9f7 1407
<> 144:ef7eb2e8f9f7 1408 default:
<> 144:ef7eb2e8f9f7 1409 EFM_ASSERT(0);
<> 144:ef7eb2e8f9f7 1410 break;
<> 144:ef7eb2e8f9f7 1411 }
<> 144:ef7eb2e8f9f7 1412 #endif
<> 144:ef7eb2e8f9f7 1413 }
<> 144:ef7eb2e8f9f7 1414
<> 144:ef7eb2e8f9f7 1415
<> 144:ef7eb2e8f9f7 1416 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 1417 * @brief
<> 144:ef7eb2e8f9f7 1418 * Enable/disable a clock.
<> 144:ef7eb2e8f9f7 1419 *
<> 144:ef7eb2e8f9f7 1420 * @details
<> 144:ef7eb2e8f9f7 1421 * In general, module clocking is disabled after a reset. If a module
<> 144:ef7eb2e8f9f7 1422 * clock is disabled, the registers of that module are not accessible and
<> 144:ef7eb2e8f9f7 1423 * reading from such registers may return undefined values. Writing to
<> 144:ef7eb2e8f9f7 1424 * registers of clock disabled modules have no effect. One should normally
<> 144:ef7eb2e8f9f7 1425 * avoid accessing module registers of a module with a disabled clock.
<> 144:ef7eb2e8f9f7 1426 *
<> 144:ef7eb2e8f9f7 1427 * @note
<> 144:ef7eb2e8f9f7 1428 * If enabling/disabling a LF clock, synchronization into the low frequency
<> 144:ef7eb2e8f9f7 1429 * domain is required. If the same register is modified before a previous
<> 144:ef7eb2e8f9f7 1430 * update has completed, this function will stall until the previous
<> 144:ef7eb2e8f9f7 1431 * synchronization has completed. Please refer to CMU_FreezeEnable() for
<> 144:ef7eb2e8f9f7 1432 * a suggestion on how to reduce stalling time in some use cases.
<> 144:ef7eb2e8f9f7 1433 *
<> 144:ef7eb2e8f9f7 1434 * @param[in] clock
<> 144:ef7eb2e8f9f7 1435 * The clock to enable/disable. Notice that not all defined clock
<> 144:ef7eb2e8f9f7 1436 * points have separate enable/disable control, please refer to CMU overview
<> 144:ef7eb2e8f9f7 1437 * in reference manual.
<> 144:ef7eb2e8f9f7 1438 *
<> 144:ef7eb2e8f9f7 1439 * @param[in] enable
<> 144:ef7eb2e8f9f7 1440 * @li true - enable specified clock.
<> 144:ef7eb2e8f9f7 1441 * @li false - disable specified clock.
<> 144:ef7eb2e8f9f7 1442 ******************************************************************************/
<> 144:ef7eb2e8f9f7 1443 void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable)
<> 144:ef7eb2e8f9f7 1444 {
<> 144:ef7eb2e8f9f7 1445 volatile uint32_t *reg;
<> 144:ef7eb2e8f9f7 1446 uint32_t bit;
<> 144:ef7eb2e8f9f7 1447 uint32_t sync = 0;
<> 144:ef7eb2e8f9f7 1448
<> 144:ef7eb2e8f9f7 1449 /* Identify enable register */
<> 144:ef7eb2e8f9f7 1450 switch ((clock >> CMU_EN_REG_POS) & CMU_EN_REG_MASK)
<> 144:ef7eb2e8f9f7 1451 {
<> 150:02e0a0aed4ec 1452 #if defined( _CMU_CTRL_HFPERCLKEN_MASK )
<> 144:ef7eb2e8f9f7 1453 case CMU_CTRL_EN_REG:
<> 144:ef7eb2e8f9f7 1454 reg = &CMU->CTRL;
<> 144:ef7eb2e8f9f7 1455 break;
<> 144:ef7eb2e8f9f7 1456 #endif
<> 144:ef7eb2e8f9f7 1457
<> 150:02e0a0aed4ec 1458 #if defined( _CMU_HFCORECLKEN0_MASK )
<> 144:ef7eb2e8f9f7 1459 case CMU_HFCORECLKEN0_EN_REG:
<> 144:ef7eb2e8f9f7 1460 reg = &CMU->HFCORECLKEN0;
<> 150:02e0a0aed4ec 1461 #if defined( CMU_MAX_FREQ_HFLE )
<> 150:02e0a0aed4ec 1462 setHfLeConfig(CMU_ClockFreqGet(cmuClock_HFLE), CMU_MAX_FREQ_HFLE);
<> 144:ef7eb2e8f9f7 1463 #endif
<> 144:ef7eb2e8f9f7 1464 break;
<> 144:ef7eb2e8f9f7 1465 #endif
<> 144:ef7eb2e8f9f7 1466
<> 144:ef7eb2e8f9f7 1467 #if defined( _CMU_HFBUSCLKEN0_MASK )
<> 144:ef7eb2e8f9f7 1468 case CMU_HFBUSCLKEN0_EN_REG:
<> 144:ef7eb2e8f9f7 1469 reg = &CMU->HFBUSCLKEN0;
<> 144:ef7eb2e8f9f7 1470 break;
<> 144:ef7eb2e8f9f7 1471 #endif
<> 144:ef7eb2e8f9f7 1472
<> 144:ef7eb2e8f9f7 1473 #if defined( _CMU_HFPERCLKDIV_MASK )
<> 144:ef7eb2e8f9f7 1474 case CMU_HFPERCLKDIV_EN_REG:
<> 144:ef7eb2e8f9f7 1475 reg = &CMU->HFPERCLKDIV;
<> 144:ef7eb2e8f9f7 1476 break;
<> 144:ef7eb2e8f9f7 1477 #endif
<> 144:ef7eb2e8f9f7 1478
<> 144:ef7eb2e8f9f7 1479 case CMU_HFPERCLKEN0_EN_REG:
<> 144:ef7eb2e8f9f7 1480 reg = &CMU->HFPERCLKEN0;
<> 144:ef7eb2e8f9f7 1481 break;
<> 144:ef7eb2e8f9f7 1482
<> 144:ef7eb2e8f9f7 1483 case CMU_LFACLKEN0_EN_REG:
<> 144:ef7eb2e8f9f7 1484 reg = &CMU->LFACLKEN0;
<> 144:ef7eb2e8f9f7 1485 sync = CMU_SYNCBUSY_LFACLKEN0;
<> 144:ef7eb2e8f9f7 1486 break;
<> 144:ef7eb2e8f9f7 1487
<> 144:ef7eb2e8f9f7 1488 case CMU_LFBCLKEN0_EN_REG:
<> 144:ef7eb2e8f9f7 1489 reg = &CMU->LFBCLKEN0;
<> 144:ef7eb2e8f9f7 1490 sync = CMU_SYNCBUSY_LFBCLKEN0;
<> 144:ef7eb2e8f9f7 1491 break;
<> 144:ef7eb2e8f9f7 1492
<> 144:ef7eb2e8f9f7 1493 #if defined( _CMU_LFCCLKEN0_MASK )
<> 144:ef7eb2e8f9f7 1494 case CMU_LFCCLKEN0_EN_REG:
<> 144:ef7eb2e8f9f7 1495 reg = &CMU->LFCCLKEN0;
<> 144:ef7eb2e8f9f7 1496 sync = CMU_SYNCBUSY_LFCCLKEN0;
<> 144:ef7eb2e8f9f7 1497 break;
<> 144:ef7eb2e8f9f7 1498 #endif
<> 144:ef7eb2e8f9f7 1499
<> 144:ef7eb2e8f9f7 1500 #if defined( _CMU_LFECLKEN0_MASK )
<> 144:ef7eb2e8f9f7 1501 case CMU_LFECLKEN0_EN_REG:
<> 144:ef7eb2e8f9f7 1502 reg = &CMU->LFECLKEN0;
<> 144:ef7eb2e8f9f7 1503 sync = CMU_SYNCBUSY_LFECLKEN0;
<> 144:ef7eb2e8f9f7 1504 break;
<> 144:ef7eb2e8f9f7 1505 #endif
<> 144:ef7eb2e8f9f7 1506
<> 144:ef7eb2e8f9f7 1507 case CMU_PCNT_EN_REG:
<> 144:ef7eb2e8f9f7 1508 reg = &CMU->PCNTCTRL;
<> 144:ef7eb2e8f9f7 1509 break;
<> 144:ef7eb2e8f9f7 1510
<> 144:ef7eb2e8f9f7 1511 default: /* Cannot enable/disable clock point */
<> 144:ef7eb2e8f9f7 1512 EFM_ASSERT(0);
<> 144:ef7eb2e8f9f7 1513 return;
<> 144:ef7eb2e8f9f7 1514 }
<> 144:ef7eb2e8f9f7 1515
<> 144:ef7eb2e8f9f7 1516 /* Get bit position used to enable/disable */
<> 144:ef7eb2e8f9f7 1517 bit = (clock >> CMU_EN_BIT_POS) & CMU_EN_BIT_MASK;
<> 144:ef7eb2e8f9f7 1518
<> 144:ef7eb2e8f9f7 1519 /* LF synchronization required? */
<> 144:ef7eb2e8f9f7 1520 if (sync)
<> 144:ef7eb2e8f9f7 1521 {
<> 144:ef7eb2e8f9f7 1522 syncReg(sync);
<> 144:ef7eb2e8f9f7 1523 }
<> 144:ef7eb2e8f9f7 1524
<> 144:ef7eb2e8f9f7 1525 /* Set/clear bit as requested */
<> 144:ef7eb2e8f9f7 1526 BUS_RegBitWrite(reg, bit, enable);
<> 144:ef7eb2e8f9f7 1527 }
<> 144:ef7eb2e8f9f7 1528
<> 144:ef7eb2e8f9f7 1529
<> 144:ef7eb2e8f9f7 1530 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 1531 * @brief
<> 144:ef7eb2e8f9f7 1532 * Get clock frequency for a clock point.
<> 144:ef7eb2e8f9f7 1533 *
<> 144:ef7eb2e8f9f7 1534 * @param[in] clock
<> 144:ef7eb2e8f9f7 1535 * Clock point to fetch frequency for.
<> 144:ef7eb2e8f9f7 1536 *
<> 144:ef7eb2e8f9f7 1537 * @return
<> 144:ef7eb2e8f9f7 1538 * The current frequency in Hz.
<> 144:ef7eb2e8f9f7 1539 ******************************************************************************/
<> 144:ef7eb2e8f9f7 1540 uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock)
<> 144:ef7eb2e8f9f7 1541 {
<> 144:ef7eb2e8f9f7 1542 uint32_t ret;
<> 144:ef7eb2e8f9f7 1543
<> 144:ef7eb2e8f9f7 1544 switch(clock & (CMU_CLK_BRANCH_MASK << CMU_CLK_BRANCH_POS))
<> 144:ef7eb2e8f9f7 1545 {
<> 144:ef7eb2e8f9f7 1546 case (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS):
<> 144:ef7eb2e8f9f7 1547 ret = SystemHFClockGet();
<> 144:ef7eb2e8f9f7 1548 break;
<> 144:ef7eb2e8f9f7 1549
<> 144:ef7eb2e8f9f7 1550 case (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS):
<> 144:ef7eb2e8f9f7 1551 ret = SystemHFClockGet();
<> 150:02e0a0aed4ec 1552 /* Calculate frequency after HFPER divider. */
<> 150:02e0a0aed4ec 1553 #if defined( _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK )
<> 144:ef7eb2e8f9f7 1554 ret >>= (CMU->HFPERCLKDIV & _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK)
<> 144:ef7eb2e8f9f7 1555 >> _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT;
<> 150:02e0a0aed4ec 1556 #endif
<> 150:02e0a0aed4ec 1557 #if defined( _CMU_HFPERPRESC_PRESC_MASK )
<> 144:ef7eb2e8f9f7 1558 ret /= 1U + ((CMU->HFPERPRESC & _CMU_HFPERPRESC_PRESC_MASK)
<> 144:ef7eb2e8f9f7 1559 >> _CMU_HFPERPRESC_PRESC_SHIFT);
<> 144:ef7eb2e8f9f7 1560 #endif
<> 144:ef7eb2e8f9f7 1561 break;
<> 144:ef7eb2e8f9f7 1562
<> 144:ef7eb2e8f9f7 1563 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
<> 144:ef7eb2e8f9f7 1564 #if defined( CRYPTO_PRESENT ) \
<> 144:ef7eb2e8f9f7 1565 || defined( LDMA_PRESENT ) \
<> 144:ef7eb2e8f9f7 1566 || defined( GPCRC_PRESENT ) \
<> 144:ef7eb2e8f9f7 1567 || defined( PRS_PRESENT ) \
<> 144:ef7eb2e8f9f7 1568 || defined( GPIO_PRESENT )
<> 144:ef7eb2e8f9f7 1569 case (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS):
<> 144:ef7eb2e8f9f7 1570 ret = SystemHFClockGet();
<> 144:ef7eb2e8f9f7 1571 break;
<> 144:ef7eb2e8f9f7 1572 #endif
<> 144:ef7eb2e8f9f7 1573
<> 144:ef7eb2e8f9f7 1574 case (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS):
<> 144:ef7eb2e8f9f7 1575 ret = SystemHFClockGet();
<> 144:ef7eb2e8f9f7 1576 ret /= 1U + ((CMU->HFCOREPRESC & _CMU_HFCOREPRESC_PRESC_MASK)
<> 144:ef7eb2e8f9f7 1577 >> _CMU_HFCOREPRESC_PRESC_SHIFT);
<> 144:ef7eb2e8f9f7 1578 break;
<> 144:ef7eb2e8f9f7 1579
<> 144:ef7eb2e8f9f7 1580 case (CMU_HFEXP_CLK_BRANCH << CMU_CLK_BRANCH_POS):
<> 144:ef7eb2e8f9f7 1581 ret = SystemHFClockGet();
<> 144:ef7eb2e8f9f7 1582 ret /= 1U + ((CMU->HFEXPPRESC & _CMU_HFEXPPRESC_PRESC_MASK)
<> 144:ef7eb2e8f9f7 1583 >> _CMU_HFEXPPRESC_PRESC_SHIFT);
<> 144:ef7eb2e8f9f7 1584 break;
<> 144:ef7eb2e8f9f7 1585 #endif
<> 144:ef7eb2e8f9f7 1586
<> 144:ef7eb2e8f9f7 1587 #if defined( _SILICON_LABS_32B_PLATFORM_1 )
<> 150:02e0a0aed4ec 1588 #if defined( AES_PRESENT ) \
<> 150:02e0a0aed4ec 1589 || defined( DMA_PRESENT ) \
<> 150:02e0a0aed4ec 1590 || defined( EBI_PRESENT ) \
<> 150:02e0a0aed4ec 1591 || defined( USB_PRESENT )
<> 144:ef7eb2e8f9f7 1592 case (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS):
<> 144:ef7eb2e8f9f7 1593 {
<> 144:ef7eb2e8f9f7 1594 ret = SystemCoreClockGet();
<> 144:ef7eb2e8f9f7 1595 } break;
<> 144:ef7eb2e8f9f7 1596 #endif
<> 144:ef7eb2e8f9f7 1597 #endif
<> 144:ef7eb2e8f9f7 1598
<> 144:ef7eb2e8f9f7 1599 case (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS):
<> 144:ef7eb2e8f9f7 1600 ret = lfClkGet(cmuClock_LFA);
<> 144:ef7eb2e8f9f7 1601 break;
<> 144:ef7eb2e8f9f7 1602
<> 144:ef7eb2e8f9f7 1603 #if defined( _CMU_LFACLKEN0_RTC_MASK )
<> 144:ef7eb2e8f9f7 1604 case (CMU_RTC_CLK_BRANCH << CMU_CLK_BRANCH_POS):
<> 144:ef7eb2e8f9f7 1605 ret = lfClkGet(cmuClock_LFA);
<> 144:ef7eb2e8f9f7 1606 ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_RTC_MASK)
<> 144:ef7eb2e8f9f7 1607 >> _CMU_LFAPRESC0_RTC_SHIFT;
<> 144:ef7eb2e8f9f7 1608 break;
<> 144:ef7eb2e8f9f7 1609 #endif
<> 144:ef7eb2e8f9f7 1610
<> 144:ef7eb2e8f9f7 1611 #if defined( _CMU_LFECLKEN0_RTCC_MASK )
<> 144:ef7eb2e8f9f7 1612 case (CMU_RTCC_CLK_BRANCH << CMU_CLK_BRANCH_POS):
<> 144:ef7eb2e8f9f7 1613 ret = lfClkGet(cmuClock_LFE);
<> 144:ef7eb2e8f9f7 1614 break;
<> 144:ef7eb2e8f9f7 1615 #endif
<> 144:ef7eb2e8f9f7 1616
<> 144:ef7eb2e8f9f7 1617 #if defined( _CMU_LFACLKEN0_LETIMER0_MASK )
<> 144:ef7eb2e8f9f7 1618 case (CMU_LETIMER0_CLK_BRANCH << CMU_CLK_BRANCH_POS):
<> 144:ef7eb2e8f9f7 1619 ret = lfClkGet(cmuClock_LFA);
<> 144:ef7eb2e8f9f7 1620 #if defined( _SILICON_LABS_32B_PLATFORM_1 )
<> 144:ef7eb2e8f9f7 1621 ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK)
<> 144:ef7eb2e8f9f7 1622 >> _CMU_LFAPRESC0_LETIMER0_SHIFT;
<> 144:ef7eb2e8f9f7 1623 #elif defined( _SILICON_LABS_32B_PLATFORM_2 )
<> 144:ef7eb2e8f9f7 1624 ret /= CMU_Log2ToDiv((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK)
<> 144:ef7eb2e8f9f7 1625 >> _CMU_LFAPRESC0_LETIMER0_SHIFT);
<> 144:ef7eb2e8f9f7 1626 #endif
<> 144:ef7eb2e8f9f7 1627 break;
<> 144:ef7eb2e8f9f7 1628 #endif
<> 144:ef7eb2e8f9f7 1629
<> 150:02e0a0aed4ec 1630 #if defined( _CMU_LFACLKEN0_LCD_MASK )
<> 144:ef7eb2e8f9f7 1631 case (CMU_LCDPRE_CLK_BRANCH << CMU_CLK_BRANCH_POS):
<> 144:ef7eb2e8f9f7 1632 ret = lfClkGet(cmuClock_LFA);
<> 144:ef7eb2e8f9f7 1633 ret >>= ((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK)
<> 144:ef7eb2e8f9f7 1634 >> _CMU_LFAPRESC0_LCD_SHIFT)
<> 144:ef7eb2e8f9f7 1635 + CMU_DivToLog2(cmuClkDiv_16);
<> 144:ef7eb2e8f9f7 1636 break;
<> 144:ef7eb2e8f9f7 1637
<> 144:ef7eb2e8f9f7 1638 case (CMU_LCD_CLK_BRANCH << CMU_CLK_BRANCH_POS):
<> 144:ef7eb2e8f9f7 1639 ret = lfClkGet(cmuClock_LFA);
<> 144:ef7eb2e8f9f7 1640 ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK)
<> 144:ef7eb2e8f9f7 1641 >> _CMU_LFAPRESC0_LCD_SHIFT;
<> 144:ef7eb2e8f9f7 1642 ret /= 1U + ((CMU->LCDCTRL & _CMU_LCDCTRL_FDIV_MASK)
<> 144:ef7eb2e8f9f7 1643 >> _CMU_LCDCTRL_FDIV_SHIFT);
<> 144:ef7eb2e8f9f7 1644 break;
<> 144:ef7eb2e8f9f7 1645 #endif
<> 144:ef7eb2e8f9f7 1646
<> 150:02e0a0aed4ec 1647 #if defined( _CMU_LFACLKEN0_LESENSE_MASK )
<> 144:ef7eb2e8f9f7 1648 case (CMU_LESENSE_CLK_BRANCH << CMU_CLK_BRANCH_POS):
<> 144:ef7eb2e8f9f7 1649 ret = lfClkGet(cmuClock_LFA);
<> 144:ef7eb2e8f9f7 1650 ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LESENSE_MASK)
<> 144:ef7eb2e8f9f7 1651 >> _CMU_LFAPRESC0_LESENSE_SHIFT;
<> 144:ef7eb2e8f9f7 1652 break;
<> 144:ef7eb2e8f9f7 1653 #endif
<> 144:ef7eb2e8f9f7 1654
<> 144:ef7eb2e8f9f7 1655 case (CMU_LFB_CLK_BRANCH << CMU_CLK_BRANCH_POS):
<> 144:ef7eb2e8f9f7 1656 ret = lfClkGet(cmuClock_LFB);
<> 144:ef7eb2e8f9f7 1657 break;
<> 144:ef7eb2e8f9f7 1658
<> 144:ef7eb2e8f9f7 1659 #if defined( _CMU_LFBCLKEN0_LEUART0_MASK )
<> 144:ef7eb2e8f9f7 1660 case (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS):
<> 144:ef7eb2e8f9f7 1661 ret = lfClkGet(cmuClock_LFB);
<> 144:ef7eb2e8f9f7 1662 #if defined( _SILICON_LABS_32B_PLATFORM_1 )
<> 144:ef7eb2e8f9f7 1663 ret >>= (CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK)
<> 144:ef7eb2e8f9f7 1664 >> _CMU_LFBPRESC0_LEUART0_SHIFT;
<> 144:ef7eb2e8f9f7 1665 #elif defined( _SILICON_LABS_32B_PLATFORM_2 )
<> 144:ef7eb2e8f9f7 1666 ret /= CMU_Log2ToDiv((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK)
<> 144:ef7eb2e8f9f7 1667 >> _CMU_LFBPRESC0_LEUART0_SHIFT);
<> 144:ef7eb2e8f9f7 1668 #endif
<> 144:ef7eb2e8f9f7 1669 break;
<> 144:ef7eb2e8f9f7 1670 #endif
<> 144:ef7eb2e8f9f7 1671
<> 144:ef7eb2e8f9f7 1672 #if defined( _CMU_LFBCLKEN0_LEUART1_MASK )
<> 144:ef7eb2e8f9f7 1673 case (CMU_LEUART1_CLK_BRANCH << CMU_CLK_BRANCH_POS):
<> 144:ef7eb2e8f9f7 1674 ret = lfClkGet(cmuClock_LFB);
<> 144:ef7eb2e8f9f7 1675 #if defined( _SILICON_LABS_32B_PLATFORM_1 )
<> 144:ef7eb2e8f9f7 1676 ret >>= (CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK)
<> 144:ef7eb2e8f9f7 1677 >> _CMU_LFBPRESC0_LEUART1_SHIFT;
<> 144:ef7eb2e8f9f7 1678 #elif defined( _SILICON_LABS_32B_PLATFORM_2 )
<> 144:ef7eb2e8f9f7 1679 ret /= CMU_Log2ToDiv((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK)
<> 144:ef7eb2e8f9f7 1680 >> _CMU_LFBPRESC0_LEUART1_SHIFT);
<> 144:ef7eb2e8f9f7 1681 #endif
<> 144:ef7eb2e8f9f7 1682 break;
<> 144:ef7eb2e8f9f7 1683 #endif
<> 144:ef7eb2e8f9f7 1684
<> 144:ef7eb2e8f9f7 1685 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
<> 144:ef7eb2e8f9f7 1686 case (CMU_LFE_CLK_BRANCH << CMU_CLK_BRANCH_POS):
<> 144:ef7eb2e8f9f7 1687 ret = lfClkGet(cmuClock_LFE);
<> 144:ef7eb2e8f9f7 1688 break;
<> 144:ef7eb2e8f9f7 1689 #endif
<> 144:ef7eb2e8f9f7 1690
<> 144:ef7eb2e8f9f7 1691 case (CMU_DBG_CLK_BRANCH << CMU_CLK_BRANCH_POS):
<> 144:ef7eb2e8f9f7 1692 ret = dbgClkGet();
<> 144:ef7eb2e8f9f7 1693 break;
<> 144:ef7eb2e8f9f7 1694
<> 144:ef7eb2e8f9f7 1695 case (CMU_AUX_CLK_BRANCH << CMU_CLK_BRANCH_POS):
<> 144:ef7eb2e8f9f7 1696 ret = auxClkGet();
<> 144:ef7eb2e8f9f7 1697 break;
<> 144:ef7eb2e8f9f7 1698
<> 144:ef7eb2e8f9f7 1699 #if defined(USB_PRESENT)
<> 144:ef7eb2e8f9f7 1700 case (CMU_USBC_CLK_BRANCH << CMU_CLK_BRANCH_POS):
<> 144:ef7eb2e8f9f7 1701 ret = usbCClkGet();
<> 144:ef7eb2e8f9f7 1702 break;
<> 144:ef7eb2e8f9f7 1703 #endif
<> 144:ef7eb2e8f9f7 1704
<> 144:ef7eb2e8f9f7 1705 default:
<> 144:ef7eb2e8f9f7 1706 EFM_ASSERT(0);
<> 144:ef7eb2e8f9f7 1707 ret = 0;
<> 144:ef7eb2e8f9f7 1708 break;
<> 144:ef7eb2e8f9f7 1709 }
<> 144:ef7eb2e8f9f7 1710
<> 144:ef7eb2e8f9f7 1711 return ret;
<> 144:ef7eb2e8f9f7 1712 }
<> 144:ef7eb2e8f9f7 1713
<> 144:ef7eb2e8f9f7 1714
<> 144:ef7eb2e8f9f7 1715 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
<> 144:ef7eb2e8f9f7 1716 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 1717 * @brief
<> 144:ef7eb2e8f9f7 1718 * Get clock prescaler.
<> 144:ef7eb2e8f9f7 1719 *
<> 144:ef7eb2e8f9f7 1720 * @param[in] clock
<> 144:ef7eb2e8f9f7 1721 * Clock point to get the prescaler for. Notice that not all clock points
<> 144:ef7eb2e8f9f7 1722 * have a prescaler. Please refer to CMU overview in reference manual.
<> 144:ef7eb2e8f9f7 1723 *
<> 144:ef7eb2e8f9f7 1724 * @return
<> 144:ef7eb2e8f9f7 1725 * The prescaler value of the current clock point. 0 is returned
<> 144:ef7eb2e8f9f7 1726 * if @p clock specifies a clock point without a prescaler.
<> 144:ef7eb2e8f9f7 1727 ******************************************************************************/
<> 144:ef7eb2e8f9f7 1728 uint32_t CMU_ClockPrescGet(CMU_Clock_TypeDef clock)
<> 144:ef7eb2e8f9f7 1729 {
<> 144:ef7eb2e8f9f7 1730 uint32_t prescReg;
<> 144:ef7eb2e8f9f7 1731 uint32_t ret;
<> 144:ef7eb2e8f9f7 1732
<> 144:ef7eb2e8f9f7 1733 /* Get prescaler register id. */
<> 144:ef7eb2e8f9f7 1734 prescReg = (clock >> CMU_PRESC_REG_POS) & CMU_PRESC_REG_MASK;
<> 144:ef7eb2e8f9f7 1735
<> 144:ef7eb2e8f9f7 1736 switch (prescReg)
<> 144:ef7eb2e8f9f7 1737 {
<> 144:ef7eb2e8f9f7 1738 case CMU_HFPRESC_REG:
<> 144:ef7eb2e8f9f7 1739 ret = ((CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK)
<> 144:ef7eb2e8f9f7 1740 >> _CMU_HFPRESC_PRESC_SHIFT);
<> 144:ef7eb2e8f9f7 1741 break;
<> 144:ef7eb2e8f9f7 1742
<> 144:ef7eb2e8f9f7 1743 case CMU_HFEXPPRESC_REG:
<> 144:ef7eb2e8f9f7 1744 ret = ((CMU->HFEXPPRESC & _CMU_HFEXPPRESC_PRESC_MASK)
<> 144:ef7eb2e8f9f7 1745 >> _CMU_HFEXPPRESC_PRESC_SHIFT);
<> 144:ef7eb2e8f9f7 1746 break;
<> 144:ef7eb2e8f9f7 1747
<> 144:ef7eb2e8f9f7 1748 case CMU_HFCLKLEPRESC_REG:
<> 144:ef7eb2e8f9f7 1749 ret = ((CMU->HFPRESC & _CMU_HFPRESC_HFCLKLEPRESC_MASK)
<> 144:ef7eb2e8f9f7 1750 >> _CMU_HFPRESC_HFCLKLEPRESC_SHIFT);
<> 144:ef7eb2e8f9f7 1751 break;
<> 144:ef7eb2e8f9f7 1752
<> 144:ef7eb2e8f9f7 1753 case CMU_HFPERPRESC_REG:
<> 144:ef7eb2e8f9f7 1754 ret = ((CMU->HFPERPRESC & _CMU_HFPERPRESC_PRESC_MASK)
<> 144:ef7eb2e8f9f7 1755 >> _CMU_HFPERPRESC_PRESC_SHIFT);
<> 144:ef7eb2e8f9f7 1756 break;
<> 144:ef7eb2e8f9f7 1757
<> 144:ef7eb2e8f9f7 1758 case CMU_HFCOREPRESC_REG:
<> 144:ef7eb2e8f9f7 1759 ret = ((CMU->HFCOREPRESC & _CMU_HFCOREPRESC_PRESC_MASK)
<> 144:ef7eb2e8f9f7 1760 >> _CMU_HFCOREPRESC_PRESC_SHIFT);
<> 144:ef7eb2e8f9f7 1761 break;
<> 144:ef7eb2e8f9f7 1762
<> 144:ef7eb2e8f9f7 1763 case CMU_LFAPRESC0_REG:
<> 144:ef7eb2e8f9f7 1764 switch (clock)
<> 144:ef7eb2e8f9f7 1765 {
<> 144:ef7eb2e8f9f7 1766 #if defined( _CMU_LFAPRESC0_LETIMER0_MASK )
<> 144:ef7eb2e8f9f7 1767 case cmuClock_LETIMER0:
<> 144:ef7eb2e8f9f7 1768 ret = (((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK)
<> 144:ef7eb2e8f9f7 1769 >> _CMU_LFAPRESC0_LETIMER0_SHIFT));
<> 144:ef7eb2e8f9f7 1770 /* Convert the exponent to prescaler value. */
<> 144:ef7eb2e8f9f7 1771 ret = CMU_Log2ToDiv(ret) - 1U;
<> 144:ef7eb2e8f9f7 1772 break;
<> 144:ef7eb2e8f9f7 1773 #endif
<> 144:ef7eb2e8f9f7 1774
<> 150:02e0a0aed4ec 1775 #if defined( _CMU_LFAPRESC0_LESENSE_MASK )
<> 150:02e0a0aed4ec 1776 case cmuClock_LESENSE:
<> 150:02e0a0aed4ec 1777 ret = (((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LESENSE_MASK)
<> 150:02e0a0aed4ec 1778 >> _CMU_LFAPRESC0_LESENSE_SHIFT));
<> 150:02e0a0aed4ec 1779 /* Convert the exponent to prescaler value. */
<> 150:02e0a0aed4ec 1780 ret = CMU_Log2ToDiv(ret) - 1U;
<> 150:02e0a0aed4ec 1781 break;
<> 150:02e0a0aed4ec 1782 #endif
<> 150:02e0a0aed4ec 1783
<> 144:ef7eb2e8f9f7 1784 default:
<> 144:ef7eb2e8f9f7 1785 EFM_ASSERT(0);
<> 144:ef7eb2e8f9f7 1786 ret = 0U;
<> 144:ef7eb2e8f9f7 1787 break;
<> 144:ef7eb2e8f9f7 1788 }
<> 144:ef7eb2e8f9f7 1789 break;
<> 144:ef7eb2e8f9f7 1790
<> 144:ef7eb2e8f9f7 1791 case CMU_LFBPRESC0_REG:
<> 144:ef7eb2e8f9f7 1792 switch (clock)
<> 144:ef7eb2e8f9f7 1793 {
<> 144:ef7eb2e8f9f7 1794 #if defined( _CMU_LFBPRESC0_LEUART0_MASK )
<> 144:ef7eb2e8f9f7 1795 case cmuClock_LEUART0:
<> 144:ef7eb2e8f9f7 1796 ret = (((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK)
<> 144:ef7eb2e8f9f7 1797 >> _CMU_LFBPRESC0_LEUART0_SHIFT));
<> 144:ef7eb2e8f9f7 1798 /* Convert the exponent to prescaler value. */
<> 144:ef7eb2e8f9f7 1799 ret = CMU_Log2ToDiv(ret) - 1U;
<> 144:ef7eb2e8f9f7 1800 break;
<> 144:ef7eb2e8f9f7 1801 #endif
<> 144:ef7eb2e8f9f7 1802
<> 144:ef7eb2e8f9f7 1803 #if defined( _CMU_LFBPRESC0_LEUART1_MASK )
<> 144:ef7eb2e8f9f7 1804 case cmuClock_LEUART1:
<> 144:ef7eb2e8f9f7 1805 ret = (((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK)
<> 144:ef7eb2e8f9f7 1806 >> _CMU_LFBPRESC0_LEUART1_SHIFT));
<> 144:ef7eb2e8f9f7 1807 /* Convert the exponent to prescaler value. */
<> 144:ef7eb2e8f9f7 1808 ret = CMU_Log2ToDiv(ret) - 1U;
<> 144:ef7eb2e8f9f7 1809 break;
<> 144:ef7eb2e8f9f7 1810 #endif
<> 144:ef7eb2e8f9f7 1811
<> 144:ef7eb2e8f9f7 1812 default:
<> 144:ef7eb2e8f9f7 1813 EFM_ASSERT(0);
<> 144:ef7eb2e8f9f7 1814 ret = 0U;
<> 144:ef7eb2e8f9f7 1815 break;
<> 144:ef7eb2e8f9f7 1816 }
<> 144:ef7eb2e8f9f7 1817 break;
<> 144:ef7eb2e8f9f7 1818
<> 144:ef7eb2e8f9f7 1819 case CMU_LFEPRESC0_REG:
<> 144:ef7eb2e8f9f7 1820 switch (clock)
<> 144:ef7eb2e8f9f7 1821 {
<> 144:ef7eb2e8f9f7 1822 #if defined( RTCC_PRESENT )
<> 144:ef7eb2e8f9f7 1823 case cmuClock_RTCC:
<> 144:ef7eb2e8f9f7 1824 /* No need to compute with LFEPRESC0_RTCC - DIV1 is the only */
<> 144:ef7eb2e8f9f7 1825 /* allowed value. Convert the exponent to prescaler value. */
<> 144:ef7eb2e8f9f7 1826 ret = _CMU_LFEPRESC0_RTCC_DIV1;
<> 144:ef7eb2e8f9f7 1827 break;
<> 144:ef7eb2e8f9f7 1828
<> 144:ef7eb2e8f9f7 1829 default:
<> 144:ef7eb2e8f9f7 1830 EFM_ASSERT(0);
<> 144:ef7eb2e8f9f7 1831 ret = 0U;
<> 144:ef7eb2e8f9f7 1832 break;
<> 144:ef7eb2e8f9f7 1833 #endif
<> 144:ef7eb2e8f9f7 1834 }
<> 144:ef7eb2e8f9f7 1835 break;
<> 144:ef7eb2e8f9f7 1836
<> 144:ef7eb2e8f9f7 1837 default:
<> 144:ef7eb2e8f9f7 1838 EFM_ASSERT(0);
<> 144:ef7eb2e8f9f7 1839 ret = 0U;
<> 144:ef7eb2e8f9f7 1840 break;
<> 144:ef7eb2e8f9f7 1841 }
<> 144:ef7eb2e8f9f7 1842
<> 144:ef7eb2e8f9f7 1843 return ret;
<> 144:ef7eb2e8f9f7 1844 }
<> 144:ef7eb2e8f9f7 1845 #endif
<> 144:ef7eb2e8f9f7 1846
<> 144:ef7eb2e8f9f7 1847
<> 144:ef7eb2e8f9f7 1848 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
<> 144:ef7eb2e8f9f7 1849 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 1850 * @brief
<> 144:ef7eb2e8f9f7 1851 * Set clock prescaler.
<> 144:ef7eb2e8f9f7 1852 *
<> 144:ef7eb2e8f9f7 1853 * @note
<> 144:ef7eb2e8f9f7 1854 * If setting a LF clock prescaler, synchronization into the low frequency
<> 144:ef7eb2e8f9f7 1855 * domain is required. If the same register is modified before a previous
<> 144:ef7eb2e8f9f7 1856 * update has completed, this function will stall until the previous
<> 144:ef7eb2e8f9f7 1857 * synchronization has completed. Please refer to CMU_FreezeEnable() for
<> 144:ef7eb2e8f9f7 1858 * a suggestion on how to reduce stalling time in some use cases.
<> 144:ef7eb2e8f9f7 1859 *
<> 144:ef7eb2e8f9f7 1860 * @param[in] clock
<> 144:ef7eb2e8f9f7 1861 * Clock point to set prescaler for. Notice that not all clock points
<> 144:ef7eb2e8f9f7 1862 * have a prescaler, please refer to CMU overview in the reference manual.
<> 144:ef7eb2e8f9f7 1863 *
<> 144:ef7eb2e8f9f7 1864 * @param[in] presc
<> 144:ef7eb2e8f9f7 1865 * The clock prescaler to use.
<> 144:ef7eb2e8f9f7 1866 ******************************************************************************/
<> 144:ef7eb2e8f9f7 1867 void CMU_ClockPrescSet(CMU_Clock_TypeDef clock, CMU_ClkPresc_TypeDef presc)
<> 144:ef7eb2e8f9f7 1868 {
<> 144:ef7eb2e8f9f7 1869 uint32_t freq;
<> 144:ef7eb2e8f9f7 1870 uint32_t prescReg;
<> 144:ef7eb2e8f9f7 1871
<> 144:ef7eb2e8f9f7 1872 /* Get divisor reg id */
<> 144:ef7eb2e8f9f7 1873 prescReg = (clock >> CMU_PRESC_REG_POS) & CMU_PRESC_REG_MASK;
<> 144:ef7eb2e8f9f7 1874
<> 144:ef7eb2e8f9f7 1875 switch (prescReg)
<> 144:ef7eb2e8f9f7 1876 {
<> 144:ef7eb2e8f9f7 1877 case CMU_HFPRESC_REG:
<> 144:ef7eb2e8f9f7 1878 EFM_ASSERT(presc < 32U);
<> 144:ef7eb2e8f9f7 1879
<> 150:02e0a0aed4ec 1880 /* Configure worst case wait-states for flash and HFLE. */
<> 150:02e0a0aed4ec 1881 flashWaitStateMax();
<> 150:02e0a0aed4ec 1882 setHfLeConfig(CMU_MAX_FREQ_HFLE + 1, CMU_MAX_FREQ_HFLE);
<> 150:02e0a0aed4ec 1883
<> 144:ef7eb2e8f9f7 1884 CMU->HFPRESC = (CMU->HFPRESC & ~_CMU_HFPRESC_PRESC_MASK)
<> 144:ef7eb2e8f9f7 1885 | (presc << _CMU_HFPRESC_PRESC_SHIFT);
<> 150:02e0a0aed4ec 1886
<> 150:02e0a0aed4ec 1887 /* Update CMSIS core clock variable (this function updates the global variable).
<> 150:02e0a0aed4ec 1888 Optimize flash and HFLE wait states. */
<> 150:02e0a0aed4ec 1889 freq = SystemCoreClockGet();
<> 150:02e0a0aed4ec 1890 flashWaitStateControl(freq);
<> 150:02e0a0aed4ec 1891 setHfLeConfig(CMU_ClockFreqGet(cmuClock_HFLE) ,CMU_MAX_FREQ_HFLE);
<> 144:ef7eb2e8f9f7 1892 break;
<> 144:ef7eb2e8f9f7 1893
<> 144:ef7eb2e8f9f7 1894 case CMU_HFEXPPRESC_REG:
<> 144:ef7eb2e8f9f7 1895 EFM_ASSERT(presc < 32U);
<> 144:ef7eb2e8f9f7 1896
<> 144:ef7eb2e8f9f7 1897 CMU->HFEXPPRESC = (CMU->HFEXPPRESC & ~_CMU_HFEXPPRESC_PRESC_MASK)
<> 144:ef7eb2e8f9f7 1898 | (presc << _CMU_HFEXPPRESC_PRESC_SHIFT);
<> 144:ef7eb2e8f9f7 1899 break;
<> 144:ef7eb2e8f9f7 1900
<> 144:ef7eb2e8f9f7 1901 case CMU_HFCLKLEPRESC_REG:
<> 144:ef7eb2e8f9f7 1902 EFM_ASSERT(presc < 2U);
<> 144:ef7eb2e8f9f7 1903
<> 144:ef7eb2e8f9f7 1904 /* Specifies the clock divider for HFCLKLE. When running at frequencies
<> 144:ef7eb2e8f9f7 1905 * higher than 32 MHz, this must be set to DIV4. */
<> 144:ef7eb2e8f9f7 1906 CMU->HFPRESC = (CMU->HFPRESC & ~_CMU_HFPRESC_HFCLKLEPRESC_MASK)
<> 144:ef7eb2e8f9f7 1907 | (presc << _CMU_HFPRESC_HFCLKLEPRESC_SHIFT);
<> 144:ef7eb2e8f9f7 1908 break;
<> 144:ef7eb2e8f9f7 1909
<> 144:ef7eb2e8f9f7 1910 case CMU_HFPERPRESC_REG:
<> 144:ef7eb2e8f9f7 1911 EFM_ASSERT(presc < 512U);
<> 144:ef7eb2e8f9f7 1912
<> 144:ef7eb2e8f9f7 1913 CMU->HFPERPRESC = (CMU->HFPERPRESC & ~_CMU_HFPERPRESC_PRESC_MASK)
<> 144:ef7eb2e8f9f7 1914 | (presc << _CMU_HFPERPRESC_PRESC_SHIFT);
<> 144:ef7eb2e8f9f7 1915 break;
<> 144:ef7eb2e8f9f7 1916
<> 144:ef7eb2e8f9f7 1917 case CMU_HFCOREPRESC_REG:
<> 144:ef7eb2e8f9f7 1918 EFM_ASSERT(presc < 512U);
<> 144:ef7eb2e8f9f7 1919
<> 150:02e0a0aed4ec 1920 /* Configure worst case wait-states for flash and HFLE. */
<> 150:02e0a0aed4ec 1921 flashWaitStateMax();
<> 150:02e0a0aed4ec 1922 setHfLeConfig(CMU_MAX_FREQ_HFLE + 1, CMU_MAX_FREQ_HFLE);
<> 144:ef7eb2e8f9f7 1923
<> 144:ef7eb2e8f9f7 1924 CMU->HFCOREPRESC = (CMU->HFCOREPRESC & ~_CMU_HFCOREPRESC_PRESC_MASK)
<> 144:ef7eb2e8f9f7 1925 | (presc << _CMU_HFCOREPRESC_PRESC_SHIFT);
<> 144:ef7eb2e8f9f7 1926
<> 150:02e0a0aed4ec 1927 /* Update CMSIS core clock variable (this function updates the global variable).
<> 150:02e0a0aed4ec 1928 Optimize flash and HFLE wait states. */
<> 144:ef7eb2e8f9f7 1929 freq = SystemCoreClockGet();
<> 144:ef7eb2e8f9f7 1930 flashWaitStateControl(freq);
<> 150:02e0a0aed4ec 1931 setHfLeConfig(CMU_ClockFreqGet(cmuClock_HFLE) ,CMU_MAX_FREQ_HFLE);
<> 144:ef7eb2e8f9f7 1932 break;
<> 144:ef7eb2e8f9f7 1933
<> 144:ef7eb2e8f9f7 1934 case CMU_LFAPRESC0_REG:
<> 144:ef7eb2e8f9f7 1935 switch (clock)
<> 144:ef7eb2e8f9f7 1936 {
<> 144:ef7eb2e8f9f7 1937 #if defined( RTC_PRESENT )
<> 144:ef7eb2e8f9f7 1938 case cmuClock_RTC:
<> 144:ef7eb2e8f9f7 1939 EFM_ASSERT(presc <= 32768U);
<> 144:ef7eb2e8f9f7 1940
<> 144:ef7eb2e8f9f7 1941 /* Convert prescaler value to DIV exponent scale. */
<> 144:ef7eb2e8f9f7 1942 presc = CMU_PrescToLog2(presc);
<> 144:ef7eb2e8f9f7 1943
<> 144:ef7eb2e8f9f7 1944 /* LF register about to be modified require sync. Busy check. */
<> 144:ef7eb2e8f9f7 1945 syncReg(CMU_SYNCBUSY_LFAPRESC0);
<> 144:ef7eb2e8f9f7 1946
<> 144:ef7eb2e8f9f7 1947 CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_RTC_MASK)
<> 144:ef7eb2e8f9f7 1948 | (presc << _CMU_LFAPRESC0_RTC_SHIFT);
<> 144:ef7eb2e8f9f7 1949 break;
<> 144:ef7eb2e8f9f7 1950 #endif
<> 144:ef7eb2e8f9f7 1951
<> 144:ef7eb2e8f9f7 1952 #if defined( RTCC_PRESENT )
<> 144:ef7eb2e8f9f7 1953 case cmuClock_RTCC:
<> 144:ef7eb2e8f9f7 1954 #if defined( _CMU_LFEPRESC0_RTCC_MASK )
<> 144:ef7eb2e8f9f7 1955 /* DIV1 is the only accepted value. */
<> 144:ef7eb2e8f9f7 1956 EFM_ASSERT(presc <= 0U);
<> 144:ef7eb2e8f9f7 1957
<> 144:ef7eb2e8f9f7 1958 /* LF register about to be modified require sync. Busy check.. */
<> 144:ef7eb2e8f9f7 1959 syncReg(CMU_SYNCBUSY_LFEPRESC0);
<> 144:ef7eb2e8f9f7 1960
<> 144:ef7eb2e8f9f7 1961 CMU->LFEPRESC0 = (CMU->LFEPRESC0 & ~_CMU_LFEPRESC0_RTCC_MASK)
<> 144:ef7eb2e8f9f7 1962 | (presc << _CMU_LFEPRESC0_RTCC_SHIFT);
<> 144:ef7eb2e8f9f7 1963 #else
<> 144:ef7eb2e8f9f7 1964 EFM_ASSERT(presc <= 32768U);
<> 144:ef7eb2e8f9f7 1965
<> 144:ef7eb2e8f9f7 1966 /* Convert prescaler value to DIV exponent scale. */
<> 144:ef7eb2e8f9f7 1967 presc = CMU_PrescToLog2(presc);
<> 144:ef7eb2e8f9f7 1968
<> 144:ef7eb2e8f9f7 1969 /* LF register about to be modified require sync. Busy check. */
<> 144:ef7eb2e8f9f7 1970 syncReg(CMU_SYNCBUSY_LFAPRESC0);
<> 144:ef7eb2e8f9f7 1971
<> 144:ef7eb2e8f9f7 1972 CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_RTCC_MASK)
<> 144:ef7eb2e8f9f7 1973 | (presc << _CMU_LFAPRESC0_RTCC_SHIFT);
<> 144:ef7eb2e8f9f7 1974 #endif
<> 144:ef7eb2e8f9f7 1975 break;
<> 144:ef7eb2e8f9f7 1976 #endif
<> 144:ef7eb2e8f9f7 1977
<> 144:ef7eb2e8f9f7 1978 #if defined( _CMU_LFAPRESC0_LETIMER0_MASK )
<> 144:ef7eb2e8f9f7 1979 case cmuClock_LETIMER0:
<> 144:ef7eb2e8f9f7 1980 EFM_ASSERT(presc <= 32768U);
<> 144:ef7eb2e8f9f7 1981
<> 144:ef7eb2e8f9f7 1982 /* Convert prescaler value to DIV exponent scale. */
<> 144:ef7eb2e8f9f7 1983 presc = CMU_PrescToLog2(presc);
<> 144:ef7eb2e8f9f7 1984
<> 144:ef7eb2e8f9f7 1985 /* LF register about to be modified require sync. Busy check. */
<> 144:ef7eb2e8f9f7 1986 syncReg(CMU_SYNCBUSY_LFAPRESC0);
<> 144:ef7eb2e8f9f7 1987
<> 144:ef7eb2e8f9f7 1988 CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LETIMER0_MASK)
<> 144:ef7eb2e8f9f7 1989 | (presc << _CMU_LFAPRESC0_LETIMER0_SHIFT);
<> 144:ef7eb2e8f9f7 1990 break;
<> 144:ef7eb2e8f9f7 1991 #endif
<> 144:ef7eb2e8f9f7 1992
<> 150:02e0a0aed4ec 1993 #if defined( _CMU_LFAPRESC0_LESENSE_MASK )
<> 150:02e0a0aed4ec 1994 case cmuClock_LESENSE:
<> 150:02e0a0aed4ec 1995 EFM_ASSERT(presc <= 8);
<> 150:02e0a0aed4ec 1996
<> 150:02e0a0aed4ec 1997 /* Convert prescaler value to DIV exponent scale. */
<> 150:02e0a0aed4ec 1998 presc = CMU_PrescToLog2(presc);
<> 150:02e0a0aed4ec 1999
<> 150:02e0a0aed4ec 2000 /* LF register about to be modified require sync. Busy check. */
<> 150:02e0a0aed4ec 2001 syncReg(CMU_SYNCBUSY_LFAPRESC0);
<> 150:02e0a0aed4ec 2002
<> 150:02e0a0aed4ec 2003 CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LESENSE_MASK)
<> 150:02e0a0aed4ec 2004 | (presc << _CMU_LFAPRESC0_LESENSE_SHIFT);
<> 150:02e0a0aed4ec 2005 break;
<> 150:02e0a0aed4ec 2006 #endif
<> 150:02e0a0aed4ec 2007
<> 144:ef7eb2e8f9f7 2008 default:
<> 144:ef7eb2e8f9f7 2009 EFM_ASSERT(0);
<> 144:ef7eb2e8f9f7 2010 break;
<> 144:ef7eb2e8f9f7 2011 }
<> 144:ef7eb2e8f9f7 2012 break;
<> 144:ef7eb2e8f9f7 2013
<> 144:ef7eb2e8f9f7 2014 case CMU_LFBPRESC0_REG:
<> 144:ef7eb2e8f9f7 2015 switch (clock)
<> 144:ef7eb2e8f9f7 2016 {
<> 144:ef7eb2e8f9f7 2017 #if defined( _CMU_LFBPRESC0_LEUART0_MASK )
<> 144:ef7eb2e8f9f7 2018 case cmuClock_LEUART0:
<> 144:ef7eb2e8f9f7 2019 EFM_ASSERT(presc <= 8U);
<> 144:ef7eb2e8f9f7 2020
<> 144:ef7eb2e8f9f7 2021 /* Convert prescaler value to DIV exponent scale. */
<> 144:ef7eb2e8f9f7 2022 presc = CMU_PrescToLog2(presc);
<> 144:ef7eb2e8f9f7 2023
<> 144:ef7eb2e8f9f7 2024 /* LF register about to be modified require sync. Busy check. */
<> 144:ef7eb2e8f9f7 2025 syncReg(CMU_SYNCBUSY_LFBPRESC0);
<> 144:ef7eb2e8f9f7 2026
<> 144:ef7eb2e8f9f7 2027 CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART0_MASK)
<> 144:ef7eb2e8f9f7 2028 | (presc << _CMU_LFBPRESC0_LEUART0_SHIFT);
<> 144:ef7eb2e8f9f7 2029 break;
<> 144:ef7eb2e8f9f7 2030 #endif
<> 144:ef7eb2e8f9f7 2031
<> 144:ef7eb2e8f9f7 2032 #if defined( _CMU_LFBPRESC0_LEUART1_MASK )
<> 144:ef7eb2e8f9f7 2033 case cmuClock_LEUART1:
<> 144:ef7eb2e8f9f7 2034 EFM_ASSERT(presc <= 8U);
<> 144:ef7eb2e8f9f7 2035
<> 144:ef7eb2e8f9f7 2036 /* Convert prescaler value to DIV exponent scale. */
<> 144:ef7eb2e8f9f7 2037 presc = CMU_PrescToLog2(presc);
<> 144:ef7eb2e8f9f7 2038
<> 144:ef7eb2e8f9f7 2039 /* LF register about to be modified require sync. Busy check. */
<> 144:ef7eb2e8f9f7 2040 syncReg(CMU_SYNCBUSY_LFBPRESC0);
<> 144:ef7eb2e8f9f7 2041
<> 144:ef7eb2e8f9f7 2042 CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART1_MASK)
<> 144:ef7eb2e8f9f7 2043 | (presc << _CMU_LFBPRESC0_LEUART1_SHIFT);
<> 144:ef7eb2e8f9f7 2044 break;
<> 144:ef7eb2e8f9f7 2045 #endif
<> 144:ef7eb2e8f9f7 2046
<> 144:ef7eb2e8f9f7 2047 default:
<> 144:ef7eb2e8f9f7 2048 EFM_ASSERT(0);
<> 144:ef7eb2e8f9f7 2049 break;
<> 144:ef7eb2e8f9f7 2050 }
<> 144:ef7eb2e8f9f7 2051 break;
<> 144:ef7eb2e8f9f7 2052
<> 144:ef7eb2e8f9f7 2053 case CMU_LFEPRESC0_REG:
<> 144:ef7eb2e8f9f7 2054 switch (clock)
<> 144:ef7eb2e8f9f7 2055 {
<> 144:ef7eb2e8f9f7 2056 #if defined( _CMU_LFEPRESC0_RTCC_MASK )
<> 144:ef7eb2e8f9f7 2057 case cmuClock_RTCC:
<> 144:ef7eb2e8f9f7 2058 EFM_ASSERT(presc <= 0U);
<> 144:ef7eb2e8f9f7 2059
<> 144:ef7eb2e8f9f7 2060 /* LF register about to be modified require sync. Busy check. */
<> 144:ef7eb2e8f9f7 2061 syncReg(CMU_SYNCBUSY_LFEPRESC0);
<> 144:ef7eb2e8f9f7 2062
<> 144:ef7eb2e8f9f7 2063 CMU->LFEPRESC0 = (CMU->LFEPRESC0 & ~_CMU_LFEPRESC0_RTCC_MASK)
<> 144:ef7eb2e8f9f7 2064 | (presc << _CMU_LFEPRESC0_RTCC_SHIFT);
<> 144:ef7eb2e8f9f7 2065 break;
<> 144:ef7eb2e8f9f7 2066 #endif
<> 144:ef7eb2e8f9f7 2067
<> 144:ef7eb2e8f9f7 2068 default:
<> 144:ef7eb2e8f9f7 2069 EFM_ASSERT(0);
<> 144:ef7eb2e8f9f7 2070 break;
<> 144:ef7eb2e8f9f7 2071 }
<> 144:ef7eb2e8f9f7 2072 break;
<> 144:ef7eb2e8f9f7 2073
<> 144:ef7eb2e8f9f7 2074 default:
<> 144:ef7eb2e8f9f7 2075 EFM_ASSERT(0);
<> 144:ef7eb2e8f9f7 2076 break;
<> 144:ef7eb2e8f9f7 2077 }
<> 144:ef7eb2e8f9f7 2078 }
<> 144:ef7eb2e8f9f7 2079 #endif
<> 144:ef7eb2e8f9f7 2080
<> 144:ef7eb2e8f9f7 2081
<> 144:ef7eb2e8f9f7 2082 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 2083 * @brief
<> 144:ef7eb2e8f9f7 2084 * Get currently selected reference clock used for a clock branch.
<> 144:ef7eb2e8f9f7 2085 *
<> 144:ef7eb2e8f9f7 2086 * @param[in] clock
<> 144:ef7eb2e8f9f7 2087 * Clock branch to fetch selected ref. clock for. One of:
<> 144:ef7eb2e8f9f7 2088 * @li #cmuClock_HF
<> 144:ef7eb2e8f9f7 2089 * @li #cmuClock_LFA
<> 144:ef7eb2e8f9f7 2090 * @li #cmuClock_LFB @if _CMU_LFCLKSEL_LFAE_ULFRCO
<> 144:ef7eb2e8f9f7 2091 * @li #cmuClock_LFC
<> 144:ef7eb2e8f9f7 2092 * @endif @if _SILICON_LABS_32B_PLATFORM_2
<> 144:ef7eb2e8f9f7 2093 * @li #cmuClock_LFE
<> 144:ef7eb2e8f9f7 2094 * @endif
<> 144:ef7eb2e8f9f7 2095 * @li #cmuClock_DBG @if DOXYDOC_USB_PRESENT
<> 144:ef7eb2e8f9f7 2096 * @li #cmuClock_USBC
<> 144:ef7eb2e8f9f7 2097 * @endif
<> 144:ef7eb2e8f9f7 2098 *
<> 144:ef7eb2e8f9f7 2099 * @return
<> 144:ef7eb2e8f9f7 2100 * Reference clock used for clocking selected branch, #cmuSelect_Error if
<> 144:ef7eb2e8f9f7 2101 * invalid @p clock provided.
<> 144:ef7eb2e8f9f7 2102 ******************************************************************************/
<> 144:ef7eb2e8f9f7 2103 CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock)
<> 144:ef7eb2e8f9f7 2104 {
<> 144:ef7eb2e8f9f7 2105 CMU_Select_TypeDef ret = cmuSelect_Disabled;
<> 144:ef7eb2e8f9f7 2106 uint32_t selReg;
<> 144:ef7eb2e8f9f7 2107
<> 144:ef7eb2e8f9f7 2108 selReg = (clock >> CMU_SEL_REG_POS) & CMU_SEL_REG_MASK;
<> 144:ef7eb2e8f9f7 2109
<> 144:ef7eb2e8f9f7 2110 switch (selReg)
<> 144:ef7eb2e8f9f7 2111 {
<> 144:ef7eb2e8f9f7 2112 case CMU_HFCLKSEL_REG:
<> 150:02e0a0aed4ec 2113 #if defined( _CMU_HFCLKSTATUS_MASK )
<> 150:02e0a0aed4ec 2114 switch (CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK)
<> 144:ef7eb2e8f9f7 2115 {
<> 150:02e0a0aed4ec 2116 case CMU_HFCLKSTATUS_SELECTED_LFXO:
<> 144:ef7eb2e8f9f7 2117 ret = cmuSelect_LFXO;
<> 144:ef7eb2e8f9f7 2118 break;
<> 144:ef7eb2e8f9f7 2119
<> 150:02e0a0aed4ec 2120 case CMU_HFCLKSTATUS_SELECTED_LFRCO:
<> 144:ef7eb2e8f9f7 2121 ret = cmuSelect_LFRCO;
<> 144:ef7eb2e8f9f7 2122 break;
<> 144:ef7eb2e8f9f7 2123
<> 150:02e0a0aed4ec 2124 case CMU_HFCLKSTATUS_SELECTED_HFXO:
<> 144:ef7eb2e8f9f7 2125 ret = cmuSelect_HFXO;
<> 144:ef7eb2e8f9f7 2126 break;
<> 144:ef7eb2e8f9f7 2127
<> 144:ef7eb2e8f9f7 2128 default:
<> 144:ef7eb2e8f9f7 2129 ret = cmuSelect_HFRCO;
<> 144:ef7eb2e8f9f7 2130 break;
<> 144:ef7eb2e8f9f7 2131 }
<> 144:ef7eb2e8f9f7 2132 #else
<> 144:ef7eb2e8f9f7 2133 switch (CMU->STATUS
<> 144:ef7eb2e8f9f7 2134 & (CMU_STATUS_HFRCOSEL
<> 144:ef7eb2e8f9f7 2135 | CMU_STATUS_HFXOSEL
<> 144:ef7eb2e8f9f7 2136 | CMU_STATUS_LFRCOSEL
<> 144:ef7eb2e8f9f7 2137 #if defined( CMU_STATUS_USHFRCODIV2SEL )
<> 144:ef7eb2e8f9f7 2138 | CMU_STATUS_USHFRCODIV2SEL
<> 144:ef7eb2e8f9f7 2139 #endif
<> 144:ef7eb2e8f9f7 2140 | CMU_STATUS_LFXOSEL))
<> 144:ef7eb2e8f9f7 2141 {
<> 144:ef7eb2e8f9f7 2142 case CMU_STATUS_LFXOSEL:
<> 144:ef7eb2e8f9f7 2143 ret = cmuSelect_LFXO;
<> 144:ef7eb2e8f9f7 2144 break;
<> 144:ef7eb2e8f9f7 2145
<> 144:ef7eb2e8f9f7 2146 case CMU_STATUS_LFRCOSEL:
<> 144:ef7eb2e8f9f7 2147 ret = cmuSelect_LFRCO;
<> 144:ef7eb2e8f9f7 2148 break;
<> 144:ef7eb2e8f9f7 2149
<> 144:ef7eb2e8f9f7 2150 case CMU_STATUS_HFXOSEL:
<> 144:ef7eb2e8f9f7 2151 ret = cmuSelect_HFXO;
<> 144:ef7eb2e8f9f7 2152 break;
<> 144:ef7eb2e8f9f7 2153
<> 144:ef7eb2e8f9f7 2154 #if defined( CMU_STATUS_USHFRCODIV2SEL )
<> 144:ef7eb2e8f9f7 2155 case CMU_STATUS_USHFRCODIV2SEL:
<> 144:ef7eb2e8f9f7 2156 ret = cmuSelect_USHFRCODIV2;
<> 144:ef7eb2e8f9f7 2157 break;
<> 144:ef7eb2e8f9f7 2158 #endif
<> 144:ef7eb2e8f9f7 2159
<> 144:ef7eb2e8f9f7 2160 default:
<> 144:ef7eb2e8f9f7 2161 ret = cmuSelect_HFRCO;
<> 144:ef7eb2e8f9f7 2162 break;
<> 144:ef7eb2e8f9f7 2163 }
<> 144:ef7eb2e8f9f7 2164 #endif
<> 144:ef7eb2e8f9f7 2165 break;
<> 144:ef7eb2e8f9f7 2166
<> 150:02e0a0aed4ec 2167 #if defined( _CMU_LFCLKSEL_MASK ) || defined( _CMU_LFACLKSEL_MASK )
<> 144:ef7eb2e8f9f7 2168 case CMU_LFACLKSEL_REG:
<> 144:ef7eb2e8f9f7 2169 #if defined( _CMU_LFCLKSEL_MASK )
<> 144:ef7eb2e8f9f7 2170 switch (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFA_MASK)
<> 144:ef7eb2e8f9f7 2171 {
<> 144:ef7eb2e8f9f7 2172 case CMU_LFCLKSEL_LFA_LFRCO:
<> 144:ef7eb2e8f9f7 2173 ret = cmuSelect_LFRCO;
<> 144:ef7eb2e8f9f7 2174 break;
<> 144:ef7eb2e8f9f7 2175
<> 144:ef7eb2e8f9f7 2176 case CMU_LFCLKSEL_LFA_LFXO:
<> 144:ef7eb2e8f9f7 2177 ret = cmuSelect_LFXO;
<> 144:ef7eb2e8f9f7 2178 break;
<> 144:ef7eb2e8f9f7 2179
<> 144:ef7eb2e8f9f7 2180 #if defined( CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 )
<> 144:ef7eb2e8f9f7 2181 case CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2:
<> 150:02e0a0aed4ec 2182 ret = cmuSelect_HFCLKLE;
<> 144:ef7eb2e8f9f7 2183 break;
<> 144:ef7eb2e8f9f7 2184 #endif
<> 144:ef7eb2e8f9f7 2185
<> 144:ef7eb2e8f9f7 2186 default:
<> 144:ef7eb2e8f9f7 2187 #if defined( CMU_LFCLKSEL_LFAE )
<> 144:ef7eb2e8f9f7 2188 if (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFAE_MASK)
<> 144:ef7eb2e8f9f7 2189 {
<> 144:ef7eb2e8f9f7 2190 ret = cmuSelect_ULFRCO;
<> 144:ef7eb2e8f9f7 2191 break;
<> 144:ef7eb2e8f9f7 2192 }
<> 144:ef7eb2e8f9f7 2193 #else
<> 144:ef7eb2e8f9f7 2194 ret = cmuSelect_Disabled;
<> 144:ef7eb2e8f9f7 2195 #endif
<> 144:ef7eb2e8f9f7 2196 break;
<> 144:ef7eb2e8f9f7 2197 }
<> 150:02e0a0aed4ec 2198
<> 150:02e0a0aed4ec 2199 #elif defined( _CMU_LFACLKSEL_MASK )
<> 144:ef7eb2e8f9f7 2200 switch (CMU->LFACLKSEL & _CMU_LFACLKSEL_LFA_MASK)
<> 144:ef7eb2e8f9f7 2201 {
<> 144:ef7eb2e8f9f7 2202 case CMU_LFACLKSEL_LFA_LFRCO:
<> 144:ef7eb2e8f9f7 2203 ret = cmuSelect_LFRCO;
<> 144:ef7eb2e8f9f7 2204 break;
<> 144:ef7eb2e8f9f7 2205
<> 144:ef7eb2e8f9f7 2206 case CMU_LFACLKSEL_LFA_LFXO:
<> 144:ef7eb2e8f9f7 2207 ret = cmuSelect_LFXO;
<> 144:ef7eb2e8f9f7 2208 break;
<> 144:ef7eb2e8f9f7 2209
<> 144:ef7eb2e8f9f7 2210 case CMU_LFACLKSEL_LFA_ULFRCO:
<> 144:ef7eb2e8f9f7 2211 ret = cmuSelect_ULFRCO;
<> 144:ef7eb2e8f9f7 2212 break;
<> 144:ef7eb2e8f9f7 2213
<> 144:ef7eb2e8f9f7 2214 #if defined( _CMU_LFACLKSEL_LFA_HFCLKLE )
<> 144:ef7eb2e8f9f7 2215 case CMU_LFACLKSEL_LFA_HFCLKLE:
<> 144:ef7eb2e8f9f7 2216 ret = cmuSelect_HFCLKLE;
<> 144:ef7eb2e8f9f7 2217 break;
<> 144:ef7eb2e8f9f7 2218 #endif
<> 144:ef7eb2e8f9f7 2219
<> 144:ef7eb2e8f9f7 2220 default:
<> 144:ef7eb2e8f9f7 2221 ret = cmuSelect_Disabled;
<> 144:ef7eb2e8f9f7 2222 break;
<> 144:ef7eb2e8f9f7 2223 }
<> 144:ef7eb2e8f9f7 2224 #endif
<> 144:ef7eb2e8f9f7 2225 break;
<> 150:02e0a0aed4ec 2226 #endif /* _CMU_LFCLKSEL_MASK || _CMU_LFACLKSEL_MASK */
<> 150:02e0a0aed4ec 2227
<> 150:02e0a0aed4ec 2228 #if defined( _CMU_LFCLKSEL_MASK ) || defined( _CMU_LFBCLKSEL_MASK )
<> 144:ef7eb2e8f9f7 2229 case CMU_LFBCLKSEL_REG:
<> 144:ef7eb2e8f9f7 2230 #if defined( _CMU_LFCLKSEL_MASK )
<> 144:ef7eb2e8f9f7 2231 switch (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFB_MASK)
<> 144:ef7eb2e8f9f7 2232 {
<> 144:ef7eb2e8f9f7 2233 case CMU_LFCLKSEL_LFB_LFRCO:
<> 144:ef7eb2e8f9f7 2234 ret = cmuSelect_LFRCO;
<> 144:ef7eb2e8f9f7 2235 break;
<> 144:ef7eb2e8f9f7 2236
<> 144:ef7eb2e8f9f7 2237 case CMU_LFCLKSEL_LFB_LFXO:
<> 144:ef7eb2e8f9f7 2238 ret = cmuSelect_LFXO;
<> 144:ef7eb2e8f9f7 2239 break;
<> 144:ef7eb2e8f9f7 2240
<> 144:ef7eb2e8f9f7 2241 #if defined( CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 )
<> 144:ef7eb2e8f9f7 2242 case CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2:
<> 150:02e0a0aed4ec 2243 ret = cmuSelect_HFCLKLE;
<> 144:ef7eb2e8f9f7 2244 break;
<> 144:ef7eb2e8f9f7 2245 #endif
<> 144:ef7eb2e8f9f7 2246
<> 144:ef7eb2e8f9f7 2247 #if defined( CMU_LFCLKSEL_LFB_HFCLKLE )
<> 144:ef7eb2e8f9f7 2248 case CMU_LFCLKSEL_LFB_HFCLKLE:
<> 144:ef7eb2e8f9f7 2249 ret = cmuSelect_HFCLKLE;
<> 144:ef7eb2e8f9f7 2250 break;
<> 144:ef7eb2e8f9f7 2251 #endif
<> 144:ef7eb2e8f9f7 2252
<> 144:ef7eb2e8f9f7 2253 default:
<> 144:ef7eb2e8f9f7 2254 #if defined( CMU_LFCLKSEL_LFBE )
<> 144:ef7eb2e8f9f7 2255 if (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFBE_MASK)
<> 144:ef7eb2e8f9f7 2256 {
<> 144:ef7eb2e8f9f7 2257 ret = cmuSelect_ULFRCO;
<> 144:ef7eb2e8f9f7 2258 break;
<> 144:ef7eb2e8f9f7 2259 }
<> 144:ef7eb2e8f9f7 2260 #else
<> 144:ef7eb2e8f9f7 2261 ret = cmuSelect_Disabled;
<> 144:ef7eb2e8f9f7 2262 #endif
<> 144:ef7eb2e8f9f7 2263 break;
<> 144:ef7eb2e8f9f7 2264 }
<> 150:02e0a0aed4ec 2265
<> 150:02e0a0aed4ec 2266 #elif defined( _CMU_LFBCLKSEL_MASK )
<> 144:ef7eb2e8f9f7 2267 switch (CMU->LFBCLKSEL & _CMU_LFBCLKSEL_LFB_MASK)
<> 144:ef7eb2e8f9f7 2268 {
<> 144:ef7eb2e8f9f7 2269 case CMU_LFBCLKSEL_LFB_LFRCO:
<> 144:ef7eb2e8f9f7 2270 ret = cmuSelect_LFRCO;
<> 144:ef7eb2e8f9f7 2271 break;
<> 144:ef7eb2e8f9f7 2272
<> 144:ef7eb2e8f9f7 2273 case CMU_LFBCLKSEL_LFB_LFXO:
<> 144:ef7eb2e8f9f7 2274 ret = cmuSelect_LFXO;
<> 144:ef7eb2e8f9f7 2275 break;
<> 144:ef7eb2e8f9f7 2276
<> 144:ef7eb2e8f9f7 2277 case CMU_LFBCLKSEL_LFB_ULFRCO:
<> 144:ef7eb2e8f9f7 2278 ret = cmuSelect_ULFRCO;
<> 144:ef7eb2e8f9f7 2279 break;
<> 144:ef7eb2e8f9f7 2280
<> 144:ef7eb2e8f9f7 2281 case CMU_LFBCLKSEL_LFB_HFCLKLE:
<> 144:ef7eb2e8f9f7 2282 ret = cmuSelect_HFCLKLE;
<> 144:ef7eb2e8f9f7 2283 break;
<> 144:ef7eb2e8f9f7 2284
<> 144:ef7eb2e8f9f7 2285 default:
<> 144:ef7eb2e8f9f7 2286 ret = cmuSelect_Disabled;
<> 144:ef7eb2e8f9f7 2287 break;
<> 144:ef7eb2e8f9f7 2288 }
<> 144:ef7eb2e8f9f7 2289 #endif
<> 144:ef7eb2e8f9f7 2290 break;
<> 150:02e0a0aed4ec 2291 #endif /* _CMU_LFCLKSEL_MASK || _CMU_LFBCLKSEL_MASK */
<> 144:ef7eb2e8f9f7 2292
<> 144:ef7eb2e8f9f7 2293 #if defined( _CMU_LFCLKSEL_LFC_MASK )
<> 144:ef7eb2e8f9f7 2294 case CMU_LFCCLKSEL_REG:
<> 144:ef7eb2e8f9f7 2295 switch (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFC_MASK)
<> 144:ef7eb2e8f9f7 2296 {
<> 144:ef7eb2e8f9f7 2297 case CMU_LFCLKSEL_LFC_LFRCO:
<> 144:ef7eb2e8f9f7 2298 ret = cmuSelect_LFRCO;
<> 144:ef7eb2e8f9f7 2299 break;
<> 144:ef7eb2e8f9f7 2300
<> 144:ef7eb2e8f9f7 2301 case CMU_LFCLKSEL_LFC_LFXO:
<> 144:ef7eb2e8f9f7 2302 ret = cmuSelect_LFXO;
<> 144:ef7eb2e8f9f7 2303 break;
<> 144:ef7eb2e8f9f7 2304
<> 144:ef7eb2e8f9f7 2305 default:
<> 144:ef7eb2e8f9f7 2306 ret = cmuSelect_Disabled;
<> 144:ef7eb2e8f9f7 2307 break;
<> 144:ef7eb2e8f9f7 2308 }
<> 144:ef7eb2e8f9f7 2309 break;
<> 144:ef7eb2e8f9f7 2310 #endif
<> 144:ef7eb2e8f9f7 2311
<> 144:ef7eb2e8f9f7 2312 #if defined( _CMU_LFECLKSEL_LFE_MASK )
<> 144:ef7eb2e8f9f7 2313 case CMU_LFECLKSEL_REG:
<> 144:ef7eb2e8f9f7 2314 switch (CMU->LFECLKSEL & _CMU_LFECLKSEL_LFE_MASK)
<> 144:ef7eb2e8f9f7 2315 {
<> 144:ef7eb2e8f9f7 2316 case CMU_LFECLKSEL_LFE_LFRCO:
<> 144:ef7eb2e8f9f7 2317 ret = cmuSelect_LFRCO;
<> 144:ef7eb2e8f9f7 2318 break;
<> 144:ef7eb2e8f9f7 2319
<> 144:ef7eb2e8f9f7 2320 case CMU_LFECLKSEL_LFE_LFXO:
<> 144:ef7eb2e8f9f7 2321 ret = cmuSelect_LFXO;
<> 144:ef7eb2e8f9f7 2322 break;
<> 144:ef7eb2e8f9f7 2323
<> 144:ef7eb2e8f9f7 2324 case CMU_LFECLKSEL_LFE_ULFRCO:
<> 144:ef7eb2e8f9f7 2325 ret = cmuSelect_ULFRCO;
<> 144:ef7eb2e8f9f7 2326 break;
<> 144:ef7eb2e8f9f7 2327
<> 144:ef7eb2e8f9f7 2328 #if defined ( _CMU_LFECLKSEL_LFE_HFCLKLE )
<> 144:ef7eb2e8f9f7 2329 case CMU_LFECLKSEL_LFE_HFCLKLE:
<> 144:ef7eb2e8f9f7 2330 ret = cmuSelect_HFCLKLE;
<> 144:ef7eb2e8f9f7 2331 break;
<> 144:ef7eb2e8f9f7 2332 #endif
<> 144:ef7eb2e8f9f7 2333
<> 144:ef7eb2e8f9f7 2334 default:
<> 144:ef7eb2e8f9f7 2335 ret = cmuSelect_Disabled;
<> 144:ef7eb2e8f9f7 2336 break;
<> 144:ef7eb2e8f9f7 2337 }
<> 144:ef7eb2e8f9f7 2338 break;
<> 144:ef7eb2e8f9f7 2339 #endif /* CMU_LFECLKSEL_REG */
<> 144:ef7eb2e8f9f7 2340
<> 144:ef7eb2e8f9f7 2341 case CMU_DBGCLKSEL_REG:
<> 144:ef7eb2e8f9f7 2342 #if defined( _CMU_DBGCLKSEL_DBG_MASK )
<> 144:ef7eb2e8f9f7 2343 switch (CMU->DBGCLKSEL & _CMU_DBGCLKSEL_DBG_MASK)
<> 144:ef7eb2e8f9f7 2344 {
<> 144:ef7eb2e8f9f7 2345 case CMU_DBGCLKSEL_DBG_HFCLK:
<> 144:ef7eb2e8f9f7 2346 ret = cmuSelect_HFCLK;
<> 144:ef7eb2e8f9f7 2347 break;
<> 144:ef7eb2e8f9f7 2348
<> 144:ef7eb2e8f9f7 2349 case CMU_DBGCLKSEL_DBG_AUXHFRCO:
<> 144:ef7eb2e8f9f7 2350 ret = cmuSelect_AUXHFRCO;
<> 144:ef7eb2e8f9f7 2351 break;
<> 144:ef7eb2e8f9f7 2352 }
<> 150:02e0a0aed4ec 2353
<> 150:02e0a0aed4ec 2354 #elif defined( _CMU_CTRL_DBGCLK_MASK )
<> 144:ef7eb2e8f9f7 2355 switch(CMU->CTRL & _CMU_CTRL_DBGCLK_MASK)
<> 144:ef7eb2e8f9f7 2356 {
<> 144:ef7eb2e8f9f7 2357 case CMU_CTRL_DBGCLK_AUXHFRCO:
<> 144:ef7eb2e8f9f7 2358 ret = cmuSelect_AUXHFRCO;
<> 144:ef7eb2e8f9f7 2359 break;
<> 144:ef7eb2e8f9f7 2360
<> 144:ef7eb2e8f9f7 2361 case CMU_CTRL_DBGCLK_HFCLK:
<> 144:ef7eb2e8f9f7 2362 ret = cmuSelect_HFCLK;
<> 144:ef7eb2e8f9f7 2363 break;
<> 144:ef7eb2e8f9f7 2364 }
<> 144:ef7eb2e8f9f7 2365 #else
<> 144:ef7eb2e8f9f7 2366 ret = cmuSelect_AUXHFRCO;
<> 144:ef7eb2e8f9f7 2367 #endif
<> 144:ef7eb2e8f9f7 2368 break;
<> 144:ef7eb2e8f9f7 2369
<> 144:ef7eb2e8f9f7 2370 #if defined( USB_PRESENT )
<> 144:ef7eb2e8f9f7 2371 case CMU_USBCCLKSEL_REG:
<> 144:ef7eb2e8f9f7 2372 switch (CMU->STATUS
<> 144:ef7eb2e8f9f7 2373 & (CMU_STATUS_USBCLFXOSEL
<> 144:ef7eb2e8f9f7 2374 #if defined(_CMU_STATUS_USBCHFCLKSEL_MASK)
<> 144:ef7eb2e8f9f7 2375 | CMU_STATUS_USBCHFCLKSEL
<> 144:ef7eb2e8f9f7 2376 #endif
<> 144:ef7eb2e8f9f7 2377 #if defined(_CMU_STATUS_USBCUSHFRCOSEL_MASK)
<> 144:ef7eb2e8f9f7 2378 | CMU_STATUS_USBCUSHFRCOSEL
<> 144:ef7eb2e8f9f7 2379 #endif
<> 144:ef7eb2e8f9f7 2380 | CMU_STATUS_USBCLFRCOSEL))
<> 144:ef7eb2e8f9f7 2381 {
<> 144:ef7eb2e8f9f7 2382 #if defined(_CMU_STATUS_USBCHFCLKSEL_MASK)
<> 144:ef7eb2e8f9f7 2383 case CMU_STATUS_USBCHFCLKSEL:
<> 144:ef7eb2e8f9f7 2384 ret = cmuSelect_HFCLK;
<> 144:ef7eb2e8f9f7 2385 break;
<> 144:ef7eb2e8f9f7 2386 #endif
<> 144:ef7eb2e8f9f7 2387
<> 144:ef7eb2e8f9f7 2388 #if defined(_CMU_STATUS_USBCUSHFRCOSEL_MASK)
<> 144:ef7eb2e8f9f7 2389 case CMU_STATUS_USBCUSHFRCOSEL:
<> 144:ef7eb2e8f9f7 2390 ret = cmuSelect_USHFRCO;
<> 144:ef7eb2e8f9f7 2391 break;
<> 144:ef7eb2e8f9f7 2392 #endif
<> 144:ef7eb2e8f9f7 2393
<> 144:ef7eb2e8f9f7 2394 case CMU_STATUS_USBCLFXOSEL:
<> 144:ef7eb2e8f9f7 2395 ret = cmuSelect_LFXO;
<> 144:ef7eb2e8f9f7 2396 break;
<> 144:ef7eb2e8f9f7 2397
<> 144:ef7eb2e8f9f7 2398 case CMU_STATUS_USBCLFRCOSEL:
<> 144:ef7eb2e8f9f7 2399 ret = cmuSelect_LFRCO;
<> 144:ef7eb2e8f9f7 2400 break;
<> 144:ef7eb2e8f9f7 2401
<> 144:ef7eb2e8f9f7 2402 default:
<> 144:ef7eb2e8f9f7 2403 ret = cmuSelect_Disabled;
<> 144:ef7eb2e8f9f7 2404 break;
<> 144:ef7eb2e8f9f7 2405 }
<> 144:ef7eb2e8f9f7 2406 break;
<> 144:ef7eb2e8f9f7 2407 #endif
<> 144:ef7eb2e8f9f7 2408
<> 144:ef7eb2e8f9f7 2409 default:
<> 144:ef7eb2e8f9f7 2410 EFM_ASSERT(0);
<> 144:ef7eb2e8f9f7 2411 ret = cmuSelect_Error;
<> 144:ef7eb2e8f9f7 2412 break;
<> 144:ef7eb2e8f9f7 2413 }
<> 144:ef7eb2e8f9f7 2414
<> 144:ef7eb2e8f9f7 2415 return ret;
<> 144:ef7eb2e8f9f7 2416 }
<> 144:ef7eb2e8f9f7 2417
<> 144:ef7eb2e8f9f7 2418
<> 144:ef7eb2e8f9f7 2419 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 2420 * @brief
<> 144:ef7eb2e8f9f7 2421 * Select reference clock/oscillator used for a clock branch.
<> 144:ef7eb2e8f9f7 2422 *
<> 144:ef7eb2e8f9f7 2423 * @details
<> 144:ef7eb2e8f9f7 2424 * Notice that if a selected reference is not enabled prior to selecting its
<> 144:ef7eb2e8f9f7 2425 * use, it will be enabled, and this function will wait for the selected
<> 144:ef7eb2e8f9f7 2426 * oscillator to be stable. It will however NOT be disabled if another
<> 144:ef7eb2e8f9f7 2427 * reference clock is selected later.
<> 144:ef7eb2e8f9f7 2428 *
<> 144:ef7eb2e8f9f7 2429 * This feature is particularly important if selecting a new reference
<> 144:ef7eb2e8f9f7 2430 * clock for the clock branch clocking the core, otherwise the system
<> 144:ef7eb2e8f9f7 2431 * may halt.
<> 144:ef7eb2e8f9f7 2432 *
<> 144:ef7eb2e8f9f7 2433 * @param[in] clock
<> 144:ef7eb2e8f9f7 2434 * Clock branch to select reference clock for. One of:
<> 144:ef7eb2e8f9f7 2435 * @li #cmuClock_HF
<> 144:ef7eb2e8f9f7 2436 * @li #cmuClock_LFA
<> 144:ef7eb2e8f9f7 2437 * @li #cmuClock_LFB @if _CMU_LFCLKSEL_LFAE_ULFRCO
<> 144:ef7eb2e8f9f7 2438 * @li #cmuClock_LFC
<> 144:ef7eb2e8f9f7 2439 * @endif @if _SILICON_LABS_32B_PLATFORM_2
<> 144:ef7eb2e8f9f7 2440 * @li #cmuClock_LFE
<> 144:ef7eb2e8f9f7 2441 * @endif
<> 144:ef7eb2e8f9f7 2442 * @li #cmuClock_DBG @if DOXYDOC_USB_PRESENT
<> 144:ef7eb2e8f9f7 2443 * @li #cmuClock_USBC
<> 144:ef7eb2e8f9f7 2444 * @endif
<> 144:ef7eb2e8f9f7 2445 *
<> 144:ef7eb2e8f9f7 2446 * @param[in] ref
<> 144:ef7eb2e8f9f7 2447 * Reference selected for clocking, please refer to reference manual for
<> 144:ef7eb2e8f9f7 2448 * for details on which reference is available for a specific clock branch.
<> 144:ef7eb2e8f9f7 2449 * @li #cmuSelect_HFRCO
<> 144:ef7eb2e8f9f7 2450 * @li #cmuSelect_LFRCO
<> 144:ef7eb2e8f9f7 2451 * @li #cmuSelect_HFXO
<> 144:ef7eb2e8f9f7 2452 * @li #cmuSelect_LFXO
<> 150:02e0a0aed4ec 2453 * @li #cmuSelect_HFCLKLE
<> 144:ef7eb2e8f9f7 2454 * @li #cmuSelect_AUXHFRCO
<> 144:ef7eb2e8f9f7 2455 * @li #cmuSelect_HFCLK @ifnot DOXYDOC_EFM32_GECKO_FAMILY
<> 144:ef7eb2e8f9f7 2456 * @li #cmuSelect_ULFRCO
<> 144:ef7eb2e8f9f7 2457 * @endif
<> 144:ef7eb2e8f9f7 2458 ******************************************************************************/
<> 144:ef7eb2e8f9f7 2459 void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref)
<> 144:ef7eb2e8f9f7 2460 {
<> 144:ef7eb2e8f9f7 2461 uint32_t select = cmuOsc_HFRCO;
<> 144:ef7eb2e8f9f7 2462 CMU_Osc_TypeDef osc = cmuOsc_HFRCO;
<> 144:ef7eb2e8f9f7 2463 uint32_t freq;
<> 144:ef7eb2e8f9f7 2464 uint32_t tmp;
<> 144:ef7eb2e8f9f7 2465 uint32_t selRegId;
<> 144:ef7eb2e8f9f7 2466 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
<> 144:ef7eb2e8f9f7 2467 volatile uint32_t *selReg = NULL;
<> 144:ef7eb2e8f9f7 2468 #endif
<> 144:ef7eb2e8f9f7 2469 #if defined( CMU_LFCLKSEL_LFAE_ULFRCO )
<> 144:ef7eb2e8f9f7 2470 uint32_t lfExtended = 0;
<> 144:ef7eb2e8f9f7 2471 #endif
<> 144:ef7eb2e8f9f7 2472
<> 144:ef7eb2e8f9f7 2473 selRegId = (clock >> CMU_SEL_REG_POS) & CMU_SEL_REG_MASK;
<> 144:ef7eb2e8f9f7 2474
<> 144:ef7eb2e8f9f7 2475 switch (selRegId)
<> 144:ef7eb2e8f9f7 2476 {
<> 144:ef7eb2e8f9f7 2477 case CMU_HFCLKSEL_REG:
<> 144:ef7eb2e8f9f7 2478 switch (ref)
<> 144:ef7eb2e8f9f7 2479 {
<> 144:ef7eb2e8f9f7 2480 case cmuSelect_LFXO:
<> 144:ef7eb2e8f9f7 2481 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
<> 144:ef7eb2e8f9f7 2482 select = CMU_HFCLKSEL_HF_LFXO;
<> 144:ef7eb2e8f9f7 2483 #elif defined( _SILICON_LABS_32B_PLATFORM_1 )
<> 144:ef7eb2e8f9f7 2484 select = CMU_CMD_HFCLKSEL_LFXO;
<> 144:ef7eb2e8f9f7 2485 #endif
<> 144:ef7eb2e8f9f7 2486 osc = cmuOsc_LFXO;
<> 144:ef7eb2e8f9f7 2487 break;
<> 144:ef7eb2e8f9f7 2488
<> 144:ef7eb2e8f9f7 2489 case cmuSelect_LFRCO:
<> 144:ef7eb2e8f9f7 2490 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
<> 144:ef7eb2e8f9f7 2491 select = CMU_HFCLKSEL_HF_LFRCO;
<> 144:ef7eb2e8f9f7 2492 #elif defined( _SILICON_LABS_32B_PLATFORM_1 )
<> 144:ef7eb2e8f9f7 2493 select = CMU_CMD_HFCLKSEL_LFRCO;
<> 144:ef7eb2e8f9f7 2494 #endif
<> 144:ef7eb2e8f9f7 2495 osc = cmuOsc_LFRCO;
<> 144:ef7eb2e8f9f7 2496 break;
<> 144:ef7eb2e8f9f7 2497
<> 144:ef7eb2e8f9f7 2498 case cmuSelect_HFXO:
<> 150:02e0a0aed4ec 2499 #if defined( CMU_HFCLKSEL_HF_HFXO )
<> 144:ef7eb2e8f9f7 2500 select = CMU_HFCLKSEL_HF_HFXO;
<> 150:02e0a0aed4ec 2501 #elif defined( CMU_CMD_HFCLKSEL_HFXO )
<> 150:02e0a0aed4ec 2502 select = CMU_CMD_HFCLKSEL_HFXO;
<> 150:02e0a0aed4ec 2503 #endif
<> 150:02e0a0aed4ec 2504 osc = cmuOsc_HFXO;
<> 150:02e0a0aed4ec 2505 #if defined( CMU_MAX_FREQ_HFLE )
<> 150:02e0a0aed4ec 2506 /* Set 1 HFLE wait-state until the new HFCLKLE frequency is known.
<> 150:02e0a0aed4ec 2507 This is known after 'select' is written below. */
<> 150:02e0a0aed4ec 2508 setHfLeConfig(CMU_MAX_FREQ_HFLE + 1, CMU_MAX_FREQ_HFLE);
<> 150:02e0a0aed4ec 2509 #endif
<> 150:02e0a0aed4ec 2510 #if defined( CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ )
<> 150:02e0a0aed4ec 2511 /* Adjust HFXO buffer current for frequencies above 32MHz */
<> 144:ef7eb2e8f9f7 2512 if (SystemHFXOClockGet() > 32000000)
<> 144:ef7eb2e8f9f7 2513 {
<> 144:ef7eb2e8f9f7 2514 CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK)
<> 150:02e0a0aed4ec 2515 | CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ;
<> 144:ef7eb2e8f9f7 2516 }
<> 144:ef7eb2e8f9f7 2517 else
<> 144:ef7eb2e8f9f7 2518 {
<> 144:ef7eb2e8f9f7 2519 CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK)
<> 144:ef7eb2e8f9f7 2520 | CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ;
<> 144:ef7eb2e8f9f7 2521 }
<> 144:ef7eb2e8f9f7 2522 #endif
<> 144:ef7eb2e8f9f7 2523 break;
<> 144:ef7eb2e8f9f7 2524
<> 144:ef7eb2e8f9f7 2525 case cmuSelect_HFRCO:
<> 144:ef7eb2e8f9f7 2526 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
<> 144:ef7eb2e8f9f7 2527 select = CMU_HFCLKSEL_HF_HFRCO;
<> 144:ef7eb2e8f9f7 2528 #elif defined( _SILICON_LABS_32B_PLATFORM_1 )
<> 144:ef7eb2e8f9f7 2529 select = CMU_CMD_HFCLKSEL_HFRCO;
<> 144:ef7eb2e8f9f7 2530 #endif
<> 144:ef7eb2e8f9f7 2531 osc = cmuOsc_HFRCO;
<> 150:02e0a0aed4ec 2532 #if defined( CMU_MAX_FREQ_HFLE )
<> 150:02e0a0aed4ec 2533 /* Set 1 HFLE wait-state until the new HFCLKLE frequency is known.
<> 150:02e0a0aed4ec 2534 This is known after 'select' is written below. */
<> 150:02e0a0aed4ec 2535 setHfLeConfig(CMU_MAX_FREQ_HFLE + 1, CMU_MAX_FREQ_HFLE);
<> 150:02e0a0aed4ec 2536 #endif
<> 144:ef7eb2e8f9f7 2537 break;
<> 144:ef7eb2e8f9f7 2538
<> 144:ef7eb2e8f9f7 2539 #if defined( CMU_CMD_HFCLKSEL_USHFRCODIV2 )
<> 144:ef7eb2e8f9f7 2540 case cmuSelect_USHFRCODIV2:
<> 144:ef7eb2e8f9f7 2541 select = CMU_CMD_HFCLKSEL_USHFRCODIV2;
<> 144:ef7eb2e8f9f7 2542 osc = cmuOsc_USHFRCO;
<> 144:ef7eb2e8f9f7 2543 break;
<> 144:ef7eb2e8f9f7 2544 #endif
<> 144:ef7eb2e8f9f7 2545
<> 144:ef7eb2e8f9f7 2546 #if defined( CMU_LFCLKSEL_LFAE_ULFRCO ) || defined( CMU_LFACLKSEL_LFA_ULFRCO )
<> 144:ef7eb2e8f9f7 2547 case cmuSelect_ULFRCO:
<> 144:ef7eb2e8f9f7 2548 /* ULFRCO cannot be used as HFCLK */
<> 144:ef7eb2e8f9f7 2549 EFM_ASSERT(0);
<> 144:ef7eb2e8f9f7 2550 return;
<> 144:ef7eb2e8f9f7 2551 #endif
<> 144:ef7eb2e8f9f7 2552
<> 144:ef7eb2e8f9f7 2553 default:
<> 144:ef7eb2e8f9f7 2554 EFM_ASSERT(0);
<> 144:ef7eb2e8f9f7 2555 return;
<> 144:ef7eb2e8f9f7 2556 }
<> 144:ef7eb2e8f9f7 2557
<> 144:ef7eb2e8f9f7 2558 /* Ensure selected oscillator is enabled, waiting for it to stabilize */
<> 144:ef7eb2e8f9f7 2559 CMU_OscillatorEnable(osc, true, true);
<> 144:ef7eb2e8f9f7 2560
<> 144:ef7eb2e8f9f7 2561 /* Configure worst case wait states for flash access before selecting */
<> 144:ef7eb2e8f9f7 2562 flashWaitStateMax();
<> 144:ef7eb2e8f9f7 2563
<> 144:ef7eb2e8f9f7 2564 /* Switch to selected oscillator */
<> 150:02e0a0aed4ec 2565 #if defined( _CMU_HFCLKSEL_MASK )
<> 144:ef7eb2e8f9f7 2566 CMU->HFCLKSEL = select;
<> 150:02e0a0aed4ec 2567 #else
<> 144:ef7eb2e8f9f7 2568 CMU->CMD = select;
<> 144:ef7eb2e8f9f7 2569 #endif
<> 150:02e0a0aed4ec 2570 #if defined( CMU_MAX_FREQ_HFLE )
<> 150:02e0a0aed4ec 2571 /* Update HFLE configuration after 'select' is set.
<> 150:02e0a0aed4ec 2572 Note that the HFCLKLE clock is connected differently on planform 1 and 2 */
<> 150:02e0a0aed4ec 2573 setHfLeConfig(CMU_ClockFreqGet(cmuClock_HFLE), CMU_MAX_FREQ_HFLE);
<> 150:02e0a0aed4ec 2574 #endif
<> 144:ef7eb2e8f9f7 2575
<> 144:ef7eb2e8f9f7 2576 /* Keep EMU module informed */
<> 144:ef7eb2e8f9f7 2577 EMU_UpdateOscConfig();
<> 144:ef7eb2e8f9f7 2578
<> 144:ef7eb2e8f9f7 2579 /* Update CMSIS core clock variable */
<> 144:ef7eb2e8f9f7 2580 /* (The function will update the global variable) */
<> 144:ef7eb2e8f9f7 2581 freq = SystemCoreClockGet();
<> 144:ef7eb2e8f9f7 2582
<> 144:ef7eb2e8f9f7 2583 /* Optimize flash access wait state setting for currently selected core clk */
<> 144:ef7eb2e8f9f7 2584 flashWaitStateControl(freq);
<> 144:ef7eb2e8f9f7 2585 break;
<> 144:ef7eb2e8f9f7 2586
<> 144:ef7eb2e8f9f7 2587 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
<> 144:ef7eb2e8f9f7 2588 case CMU_LFACLKSEL_REG:
<> 144:ef7eb2e8f9f7 2589 selReg = (selReg == NULL) ? &CMU->LFACLKSEL : selReg;
<> 144:ef7eb2e8f9f7 2590 #if !defined( _CMU_LFACLKSEL_LFA_HFCLKLE )
<> 144:ef7eb2e8f9f7 2591 /* HFCLKCLE can not be used as LFACLK */
<> 144:ef7eb2e8f9f7 2592 EFM_ASSERT(ref != cmuSelect_HFCLKLE);
<> 144:ef7eb2e8f9f7 2593 #endif
<> 150:02e0a0aed4ec 2594 /* Fall through and select clock source */
<> 150:02e0a0aed4ec 2595
<> 144:ef7eb2e8f9f7 2596 case CMU_LFECLKSEL_REG:
<> 144:ef7eb2e8f9f7 2597 selReg = (selReg == NULL) ? &CMU->LFECLKSEL : selReg;
<> 144:ef7eb2e8f9f7 2598 #if !defined( _CMU_LFECLKSEL_LFE_HFCLKLE )
<> 144:ef7eb2e8f9f7 2599 /* HFCLKCLE can not be used as LFECLK */
<> 144:ef7eb2e8f9f7 2600 EFM_ASSERT(ref != cmuSelect_HFCLKLE);
<> 144:ef7eb2e8f9f7 2601 #endif
<> 150:02e0a0aed4ec 2602 /* Fall through and select clock source */
<> 150:02e0a0aed4ec 2603
<> 144:ef7eb2e8f9f7 2604 case CMU_LFBCLKSEL_REG:
<> 144:ef7eb2e8f9f7 2605 selReg = (selReg == NULL) ? &CMU->LFBCLKSEL : selReg;
<> 144:ef7eb2e8f9f7 2606 switch (ref)
<> 144:ef7eb2e8f9f7 2607 {
<> 144:ef7eb2e8f9f7 2608 case cmuSelect_Disabled:
<> 144:ef7eb2e8f9f7 2609 tmp = _CMU_LFACLKSEL_LFA_DISABLED;
<> 144:ef7eb2e8f9f7 2610 break;
<> 144:ef7eb2e8f9f7 2611
<> 144:ef7eb2e8f9f7 2612 case cmuSelect_LFXO:
<> 144:ef7eb2e8f9f7 2613 /* Ensure selected oscillator is enabled, waiting for it to stabilize */
<> 144:ef7eb2e8f9f7 2614 CMU_OscillatorEnable(cmuOsc_LFXO, true, true);
<> 144:ef7eb2e8f9f7 2615 tmp = _CMU_LFACLKSEL_LFA_LFXO;
<> 144:ef7eb2e8f9f7 2616 break;
<> 144:ef7eb2e8f9f7 2617
<> 144:ef7eb2e8f9f7 2618 case cmuSelect_LFRCO:
<> 144:ef7eb2e8f9f7 2619 /* Ensure selected oscillator is enabled, waiting for it to stabilize */
<> 144:ef7eb2e8f9f7 2620 CMU_OscillatorEnable(cmuOsc_LFRCO, true, true);
<> 144:ef7eb2e8f9f7 2621 tmp = _CMU_LFACLKSEL_LFA_LFRCO;
<> 144:ef7eb2e8f9f7 2622 break;
<> 144:ef7eb2e8f9f7 2623
<> 144:ef7eb2e8f9f7 2624 case cmuSelect_HFCLKLE:
<> 150:02e0a0aed4ec 2625 /* Ensure correct HFLE wait-states and enable HFCLK to LE */
<> 150:02e0a0aed4ec 2626 setHfLeConfig(SystemCoreClockGet(), CMU_MAX_FREQ_HFLE);
<> 144:ef7eb2e8f9f7 2627 BUS_RegBitWrite(&CMU->HFBUSCLKEN0, _CMU_HFBUSCLKEN0_LE_SHIFT, 1);
<> 144:ef7eb2e8f9f7 2628 tmp = _CMU_LFBCLKSEL_LFB_HFCLKLE;
<> 144:ef7eb2e8f9f7 2629 break;
<> 144:ef7eb2e8f9f7 2630
<> 144:ef7eb2e8f9f7 2631 case cmuSelect_ULFRCO:
<> 144:ef7eb2e8f9f7 2632 /* ULFRCO is always on, there is no need to enable it. */
<> 144:ef7eb2e8f9f7 2633 tmp = _CMU_LFACLKSEL_LFA_ULFRCO;
<> 144:ef7eb2e8f9f7 2634 break;
<> 144:ef7eb2e8f9f7 2635
<> 144:ef7eb2e8f9f7 2636 default:
<> 144:ef7eb2e8f9f7 2637 EFM_ASSERT(0);
<> 144:ef7eb2e8f9f7 2638 return;
<> 144:ef7eb2e8f9f7 2639 }
<> 144:ef7eb2e8f9f7 2640 *selReg = tmp;
<> 144:ef7eb2e8f9f7 2641 break;
<> 144:ef7eb2e8f9f7 2642
<> 144:ef7eb2e8f9f7 2643 #elif defined( _SILICON_LABS_32B_PLATFORM_1 )
<> 144:ef7eb2e8f9f7 2644 case CMU_LFACLKSEL_REG:
<> 144:ef7eb2e8f9f7 2645 case CMU_LFBCLKSEL_REG:
<> 144:ef7eb2e8f9f7 2646 switch (ref)
<> 144:ef7eb2e8f9f7 2647 {
<> 144:ef7eb2e8f9f7 2648 case cmuSelect_Disabled:
<> 144:ef7eb2e8f9f7 2649 tmp = _CMU_LFCLKSEL_LFA_DISABLED;
<> 144:ef7eb2e8f9f7 2650 break;
<> 144:ef7eb2e8f9f7 2651
<> 144:ef7eb2e8f9f7 2652 case cmuSelect_LFXO:
<> 144:ef7eb2e8f9f7 2653 /* Ensure selected oscillator is enabled, waiting for it to stabilize */
<> 144:ef7eb2e8f9f7 2654 CMU_OscillatorEnable(cmuOsc_LFXO, true, true);
<> 144:ef7eb2e8f9f7 2655 tmp = _CMU_LFCLKSEL_LFA_LFXO;
<> 144:ef7eb2e8f9f7 2656 break;
<> 144:ef7eb2e8f9f7 2657
<> 144:ef7eb2e8f9f7 2658 case cmuSelect_LFRCO:
<> 144:ef7eb2e8f9f7 2659 /* Ensure selected oscillator is enabled, waiting for it to stabilize */
<> 144:ef7eb2e8f9f7 2660 CMU_OscillatorEnable(cmuOsc_LFRCO, true, true);
<> 144:ef7eb2e8f9f7 2661 tmp = _CMU_LFCLKSEL_LFA_LFRCO;
<> 144:ef7eb2e8f9f7 2662 break;
<> 144:ef7eb2e8f9f7 2663
<> 150:02e0a0aed4ec 2664 case cmuSelect_HFCLKLE:
<> 150:02e0a0aed4ec 2665 #if defined( CMU_MAX_FREQ_HFLE )
<> 150:02e0a0aed4ec 2666 /* Set HFLE wait-state and divider */
<> 144:ef7eb2e8f9f7 2667 freq = SystemCoreClockGet();
<> 150:02e0a0aed4ec 2668 setHfLeConfig(freq, CMU_MAX_FREQ_HFLE);
<> 144:ef7eb2e8f9f7 2669 #endif
<> 150:02e0a0aed4ec 2670 /* Ensure HFCORE to LE clocking is enabled */
<> 150:02e0a0aed4ec 2671 BUS_RegBitWrite(&CMU->HFCORECLKEN0, _CMU_HFCORECLKEN0_LE_SHIFT, 1);
<> 150:02e0a0aed4ec 2672 tmp = _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2;
<> 144:ef7eb2e8f9f7 2673 break;
<> 144:ef7eb2e8f9f7 2674
<> 144:ef7eb2e8f9f7 2675 #if defined( CMU_LFCLKSEL_LFAE_ULFRCO )
<> 144:ef7eb2e8f9f7 2676 case cmuSelect_ULFRCO:
<> 144:ef7eb2e8f9f7 2677 /* ULFRCO is always enabled */
<> 144:ef7eb2e8f9f7 2678 tmp = _CMU_LFCLKSEL_LFA_DISABLED;
<> 144:ef7eb2e8f9f7 2679 lfExtended = 1;
<> 144:ef7eb2e8f9f7 2680 break;
<> 144:ef7eb2e8f9f7 2681 #endif
<> 144:ef7eb2e8f9f7 2682
<> 144:ef7eb2e8f9f7 2683 default:
<> 144:ef7eb2e8f9f7 2684 /* Illegal clock source for LFA/LFB selected */
<> 144:ef7eb2e8f9f7 2685 EFM_ASSERT(0);
<> 144:ef7eb2e8f9f7 2686 return;
<> 144:ef7eb2e8f9f7 2687 }
<> 144:ef7eb2e8f9f7 2688
<> 144:ef7eb2e8f9f7 2689 /* Apply select */
<> 144:ef7eb2e8f9f7 2690 if (selRegId == CMU_LFACLKSEL_REG)
<> 144:ef7eb2e8f9f7 2691 {
<> 144:ef7eb2e8f9f7 2692 #if defined( _CMU_LFCLKSEL_LFAE_MASK )
<> 144:ef7eb2e8f9f7 2693 CMU->LFCLKSEL = (CMU->LFCLKSEL
<> 144:ef7eb2e8f9f7 2694 & ~(_CMU_LFCLKSEL_LFA_MASK | _CMU_LFCLKSEL_LFAE_MASK))
<> 144:ef7eb2e8f9f7 2695 | (tmp << _CMU_LFCLKSEL_LFA_SHIFT)
<> 144:ef7eb2e8f9f7 2696 | (lfExtended << _CMU_LFCLKSEL_LFAE_SHIFT);
<> 144:ef7eb2e8f9f7 2697 #else
<> 144:ef7eb2e8f9f7 2698 CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFA_MASK)
<> 144:ef7eb2e8f9f7 2699 | (tmp << _CMU_LFCLKSEL_LFA_SHIFT);
<> 144:ef7eb2e8f9f7 2700 #endif
<> 144:ef7eb2e8f9f7 2701 }
<> 144:ef7eb2e8f9f7 2702 else
<> 144:ef7eb2e8f9f7 2703 {
<> 144:ef7eb2e8f9f7 2704 #if defined( _CMU_LFCLKSEL_LFBE_MASK )
<> 144:ef7eb2e8f9f7 2705 CMU->LFCLKSEL = (CMU->LFCLKSEL
<> 144:ef7eb2e8f9f7 2706 & ~(_CMU_LFCLKSEL_LFB_MASK | _CMU_LFCLKSEL_LFBE_MASK))
<> 144:ef7eb2e8f9f7 2707 | (tmp << _CMU_LFCLKSEL_LFB_SHIFT)
<> 144:ef7eb2e8f9f7 2708 | (lfExtended << _CMU_LFCLKSEL_LFBE_SHIFT);
<> 144:ef7eb2e8f9f7 2709 #else
<> 144:ef7eb2e8f9f7 2710 CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFB_MASK)
<> 144:ef7eb2e8f9f7 2711 | (tmp << _CMU_LFCLKSEL_LFB_SHIFT);
<> 144:ef7eb2e8f9f7 2712 #endif
<> 144:ef7eb2e8f9f7 2713 }
<> 144:ef7eb2e8f9f7 2714 break;
<> 144:ef7eb2e8f9f7 2715
<> 144:ef7eb2e8f9f7 2716 #if defined( _CMU_LFCLKSEL_LFC_MASK )
<> 144:ef7eb2e8f9f7 2717 case CMU_LFCCLKSEL_REG:
<> 144:ef7eb2e8f9f7 2718 switch(ref)
<> 144:ef7eb2e8f9f7 2719 {
<> 144:ef7eb2e8f9f7 2720 case cmuSelect_Disabled:
<> 144:ef7eb2e8f9f7 2721 tmp = _CMU_LFCLKSEL_LFA_DISABLED;
<> 144:ef7eb2e8f9f7 2722 break;
<> 144:ef7eb2e8f9f7 2723
<> 144:ef7eb2e8f9f7 2724 case cmuSelect_LFXO:
<> 144:ef7eb2e8f9f7 2725 /* Ensure selected oscillator is enabled, waiting for it to stabilize */
<> 144:ef7eb2e8f9f7 2726 CMU_OscillatorEnable(cmuOsc_LFXO, true, true);
<> 144:ef7eb2e8f9f7 2727 tmp = _CMU_LFCLKSEL_LFC_LFXO;
<> 144:ef7eb2e8f9f7 2728 break;
<> 144:ef7eb2e8f9f7 2729
<> 144:ef7eb2e8f9f7 2730 case cmuSelect_LFRCO:
<> 144:ef7eb2e8f9f7 2731 /* Ensure selected oscillator is enabled, waiting for it to stabilize */
<> 144:ef7eb2e8f9f7 2732 CMU_OscillatorEnable(cmuOsc_LFRCO, true, true);
<> 144:ef7eb2e8f9f7 2733 tmp = _CMU_LFCLKSEL_LFC_LFRCO;
<> 144:ef7eb2e8f9f7 2734 break;
<> 144:ef7eb2e8f9f7 2735
<> 144:ef7eb2e8f9f7 2736 default:
<> 144:ef7eb2e8f9f7 2737 /* Illegal clock source for LFC selected */
<> 144:ef7eb2e8f9f7 2738 EFM_ASSERT(0);
<> 144:ef7eb2e8f9f7 2739 return;
<> 144:ef7eb2e8f9f7 2740 }
<> 144:ef7eb2e8f9f7 2741
<> 144:ef7eb2e8f9f7 2742 /* Apply select */
<> 144:ef7eb2e8f9f7 2743 CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFC_MASK)
<> 144:ef7eb2e8f9f7 2744 | (tmp << _CMU_LFCLKSEL_LFC_SHIFT);
<> 144:ef7eb2e8f9f7 2745 break;
<> 144:ef7eb2e8f9f7 2746 #endif
<> 144:ef7eb2e8f9f7 2747 #endif
<> 144:ef7eb2e8f9f7 2748
<> 144:ef7eb2e8f9f7 2749 #if defined( CMU_DBGCLKSEL_DBG ) || defined( CMU_CTRL_DBGCLK )
<> 144:ef7eb2e8f9f7 2750 case CMU_DBGCLKSEL_REG:
<> 144:ef7eb2e8f9f7 2751 switch(ref)
<> 144:ef7eb2e8f9f7 2752 {
<> 144:ef7eb2e8f9f7 2753 #if defined( CMU_DBGCLKSEL_DBG )
<> 144:ef7eb2e8f9f7 2754 case cmuSelect_AUXHFRCO:
<> 144:ef7eb2e8f9f7 2755 /* Select AUXHFRCO as debug clock */
<> 144:ef7eb2e8f9f7 2756 CMU->DBGCLKSEL = CMU_DBGCLKSEL_DBG_AUXHFRCO;
<> 144:ef7eb2e8f9f7 2757 break;
<> 144:ef7eb2e8f9f7 2758
<> 144:ef7eb2e8f9f7 2759 case cmuSelect_HFCLK:
<> 144:ef7eb2e8f9f7 2760 /* Select divided HFCLK as debug clock */
<> 144:ef7eb2e8f9f7 2761 CMU->DBGCLKSEL = CMU_DBGCLKSEL_DBG_HFCLK;
<> 144:ef7eb2e8f9f7 2762 break;
<> 144:ef7eb2e8f9f7 2763 #endif
<> 144:ef7eb2e8f9f7 2764
<> 144:ef7eb2e8f9f7 2765 #if defined( CMU_CTRL_DBGCLK )
<> 144:ef7eb2e8f9f7 2766 case cmuSelect_AUXHFRCO:
<> 144:ef7eb2e8f9f7 2767 /* Select AUXHFRCO as debug clock */
<> 144:ef7eb2e8f9f7 2768 CMU->CTRL = (CMU->CTRL & ~(_CMU_CTRL_DBGCLK_MASK))
<> 144:ef7eb2e8f9f7 2769 | CMU_CTRL_DBGCLK_AUXHFRCO;
<> 144:ef7eb2e8f9f7 2770 break;
<> 144:ef7eb2e8f9f7 2771
<> 144:ef7eb2e8f9f7 2772 case cmuSelect_HFCLK:
<> 144:ef7eb2e8f9f7 2773 /* Select divided HFCLK as debug clock */
<> 144:ef7eb2e8f9f7 2774 CMU->CTRL = (CMU->CTRL & ~(_CMU_CTRL_DBGCLK_MASK))
<> 144:ef7eb2e8f9f7 2775 | CMU_CTRL_DBGCLK_HFCLK;
<> 144:ef7eb2e8f9f7 2776 break;
<> 144:ef7eb2e8f9f7 2777 #endif
<> 144:ef7eb2e8f9f7 2778
<> 144:ef7eb2e8f9f7 2779 default:
<> 144:ef7eb2e8f9f7 2780 /* Illegal clock source for debug selected */
<> 144:ef7eb2e8f9f7 2781 EFM_ASSERT(0);
<> 144:ef7eb2e8f9f7 2782 return;
<> 144:ef7eb2e8f9f7 2783 }
<> 144:ef7eb2e8f9f7 2784 break;
<> 144:ef7eb2e8f9f7 2785 #endif
<> 144:ef7eb2e8f9f7 2786
<> 150:02e0a0aed4ec 2787 #if defined( USB_PRESENT )
<> 144:ef7eb2e8f9f7 2788 case CMU_USBCCLKSEL_REG:
<> 144:ef7eb2e8f9f7 2789 switch(ref)
<> 144:ef7eb2e8f9f7 2790 {
<> 144:ef7eb2e8f9f7 2791 case cmuSelect_LFXO:
<> 144:ef7eb2e8f9f7 2792 /* Select LFXO as clock source for USB, can only be used in sleep mode */
<> 144:ef7eb2e8f9f7 2793 /* Ensure selected oscillator is enabled, waiting for it to stabilize */
<> 144:ef7eb2e8f9f7 2794 CMU_OscillatorEnable(cmuOsc_LFXO, true, true);
<> 144:ef7eb2e8f9f7 2795
<> 144:ef7eb2e8f9f7 2796 /* Switch oscillator */
<> 144:ef7eb2e8f9f7 2797 CMU->CMD = CMU_CMD_USBCCLKSEL_LFXO;
<> 144:ef7eb2e8f9f7 2798
<> 144:ef7eb2e8f9f7 2799 /* Wait until clock is activated */
<> 144:ef7eb2e8f9f7 2800 while((CMU->STATUS & CMU_STATUS_USBCLFXOSEL)==0)
<> 144:ef7eb2e8f9f7 2801 {
<> 144:ef7eb2e8f9f7 2802 }
<> 144:ef7eb2e8f9f7 2803 break;
<> 144:ef7eb2e8f9f7 2804
<> 144:ef7eb2e8f9f7 2805 case cmuSelect_LFRCO:
<> 144:ef7eb2e8f9f7 2806 /* Select LFRCO as clock source for USB, can only be used in sleep mode */
<> 144:ef7eb2e8f9f7 2807 /* Ensure selected oscillator is enabled, waiting for it to stabilize */
<> 144:ef7eb2e8f9f7 2808 CMU_OscillatorEnable(cmuOsc_LFRCO, true, true);
<> 144:ef7eb2e8f9f7 2809
<> 144:ef7eb2e8f9f7 2810 /* Switch oscillator */
<> 144:ef7eb2e8f9f7 2811 CMU->CMD = CMU_CMD_USBCCLKSEL_LFRCO;
<> 144:ef7eb2e8f9f7 2812
<> 144:ef7eb2e8f9f7 2813 /* Wait until clock is activated */
<> 144:ef7eb2e8f9f7 2814 while((CMU->STATUS & CMU_STATUS_USBCLFRCOSEL)==0)
<> 144:ef7eb2e8f9f7 2815 {
<> 144:ef7eb2e8f9f7 2816 }
<> 144:ef7eb2e8f9f7 2817 break;
<> 144:ef7eb2e8f9f7 2818
<> 144:ef7eb2e8f9f7 2819 #if defined( CMU_STATUS_USBCHFCLKSEL )
<> 144:ef7eb2e8f9f7 2820 case cmuSelect_HFCLK:
<> 144:ef7eb2e8f9f7 2821 /* Select undivided HFCLK as clock source for USB */
<> 144:ef7eb2e8f9f7 2822 /* Oscillator must already be enabled to avoid a core lockup */
<> 144:ef7eb2e8f9f7 2823 CMU->CMD = CMU_CMD_USBCCLKSEL_HFCLKNODIV;
<> 144:ef7eb2e8f9f7 2824 /* Wait until clock is activated */
<> 144:ef7eb2e8f9f7 2825 while((CMU->STATUS & CMU_STATUS_USBCHFCLKSEL)==0)
<> 144:ef7eb2e8f9f7 2826 {
<> 144:ef7eb2e8f9f7 2827 }
<> 144:ef7eb2e8f9f7 2828 break;
<> 144:ef7eb2e8f9f7 2829 #endif
<> 144:ef7eb2e8f9f7 2830
<> 144:ef7eb2e8f9f7 2831 #if defined( CMU_CMD_USBCCLKSEL_USHFRCO )
<> 144:ef7eb2e8f9f7 2832 case cmuSelect_USHFRCO:
<> 144:ef7eb2e8f9f7 2833 /* Select USHFRCO as clock source for USB */
<> 144:ef7eb2e8f9f7 2834 /* Ensure selected oscillator is enabled, waiting for it to stabilize */
<> 144:ef7eb2e8f9f7 2835 CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true);
<> 144:ef7eb2e8f9f7 2836
<> 144:ef7eb2e8f9f7 2837 /* Switch oscillator */
<> 144:ef7eb2e8f9f7 2838 CMU->CMD = CMU_CMD_USBCCLKSEL_USHFRCO;
<> 144:ef7eb2e8f9f7 2839
<> 144:ef7eb2e8f9f7 2840 /* Wait until clock is activated */
<> 144:ef7eb2e8f9f7 2841 while((CMU->STATUS & CMU_STATUS_USBCUSHFRCOSEL)==0)
<> 144:ef7eb2e8f9f7 2842 {
<> 144:ef7eb2e8f9f7 2843 }
<> 144:ef7eb2e8f9f7 2844 break;
<> 144:ef7eb2e8f9f7 2845 #endif
<> 144:ef7eb2e8f9f7 2846
<> 144:ef7eb2e8f9f7 2847 default:
<> 144:ef7eb2e8f9f7 2848 /* Illegal clock source for USB */
<> 144:ef7eb2e8f9f7 2849 EFM_ASSERT(0);
<> 144:ef7eb2e8f9f7 2850 return;
<> 144:ef7eb2e8f9f7 2851 }
<> 144:ef7eb2e8f9f7 2852 break;
<> 144:ef7eb2e8f9f7 2853 #endif
<> 144:ef7eb2e8f9f7 2854
<> 144:ef7eb2e8f9f7 2855 default:
<> 144:ef7eb2e8f9f7 2856 EFM_ASSERT(0);
<> 144:ef7eb2e8f9f7 2857 break;
<> 144:ef7eb2e8f9f7 2858 }
<> 150:02e0a0aed4ec 2859 #if defined( CMU_MAX_FREQ_HFLE )
<> 150:02e0a0aed4ec 2860 /* Get to assert wait-state config. */
<> 150:02e0a0aed4ec 2861 getHfLeConfig();
<> 150:02e0a0aed4ec 2862 #endif
<> 144:ef7eb2e8f9f7 2863 }
<> 144:ef7eb2e8f9f7 2864
<> 144:ef7eb2e8f9f7 2865 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 2866 * @brief
<> 144:ef7eb2e8f9f7 2867 * CMU low frequency register synchronization freeze control.
<> 144:ef7eb2e8f9f7 2868 *
<> 144:ef7eb2e8f9f7 2869 * @details
<> 144:ef7eb2e8f9f7 2870 * Some CMU registers requires synchronization into the low frequency (LF)
<> 144:ef7eb2e8f9f7 2871 * domain. The freeze feature allows for several such registers to be
<> 144:ef7eb2e8f9f7 2872 * modified before passing them to the LF domain simultaneously (which
<> 144:ef7eb2e8f9f7 2873 * takes place when the freeze mode is disabled).
<> 144:ef7eb2e8f9f7 2874 *
<> 144:ef7eb2e8f9f7 2875 * Another usage scenario of this feature, is when using an API (such
<> 144:ef7eb2e8f9f7 2876 * as the CMU API) for modifying several bit fields consecutively in the
<> 144:ef7eb2e8f9f7 2877 * same register. If freeze mode is enabled during this sequence, stalling
<> 144:ef7eb2e8f9f7 2878 * can be avoided.
<> 144:ef7eb2e8f9f7 2879 *
<> 144:ef7eb2e8f9f7 2880 * @note
<> 144:ef7eb2e8f9f7 2881 * When enabling freeze mode, this function will wait for all current
<> 144:ef7eb2e8f9f7 2882 * ongoing CMU synchronization to LF domain to complete (Normally
<> 144:ef7eb2e8f9f7 2883 * synchronization will not be in progress.) However for this reason, when
<> 144:ef7eb2e8f9f7 2884 * using freeze mode, modifications of registers requiring LF synchronization
<> 144:ef7eb2e8f9f7 2885 * should be done within one freeze enable/disable block to avoid unecessary
<> 144:ef7eb2e8f9f7 2886 * stalling.
<> 144:ef7eb2e8f9f7 2887 *
<> 144:ef7eb2e8f9f7 2888 * @param[in] enable
<> 144:ef7eb2e8f9f7 2889 * @li true - enable freeze, modified registers are not propagated to the
<> 144:ef7eb2e8f9f7 2890 * LF domain
<> 144:ef7eb2e8f9f7 2891 * @li false - disable freeze, modified registers are propagated to LF
<> 144:ef7eb2e8f9f7 2892 * domain
<> 144:ef7eb2e8f9f7 2893 *****************************************************************************/
<> 144:ef7eb2e8f9f7 2894 void CMU_FreezeEnable(bool enable)
<> 144:ef7eb2e8f9f7 2895 {
<> 144:ef7eb2e8f9f7 2896 if (enable)
<> 144:ef7eb2e8f9f7 2897 {
<> 144:ef7eb2e8f9f7 2898 /* Wait for any ongoing LF synchronization to complete. This is just to */
<> 144:ef7eb2e8f9f7 2899 /* protect against the rare case when a user */
<> 144:ef7eb2e8f9f7 2900 /* - modifies a register requiring LF sync */
<> 144:ef7eb2e8f9f7 2901 /* - then enables freeze before LF sync completed */
<> 144:ef7eb2e8f9f7 2902 /* - then modifies the same register again */
<> 144:ef7eb2e8f9f7 2903 /* since modifying a register while it is in sync progress should be */
<> 144:ef7eb2e8f9f7 2904 /* avoided. */
<> 144:ef7eb2e8f9f7 2905 while (CMU->SYNCBUSY)
<> 144:ef7eb2e8f9f7 2906 {
<> 144:ef7eb2e8f9f7 2907 }
<> 144:ef7eb2e8f9f7 2908
<> 144:ef7eb2e8f9f7 2909 CMU->FREEZE = CMU_FREEZE_REGFREEZE;
<> 144:ef7eb2e8f9f7 2910 }
<> 144:ef7eb2e8f9f7 2911 else
<> 144:ef7eb2e8f9f7 2912 {
<> 144:ef7eb2e8f9f7 2913 CMU->FREEZE = 0;
<> 144:ef7eb2e8f9f7 2914 }
<> 144:ef7eb2e8f9f7 2915 }
<> 144:ef7eb2e8f9f7 2916
<> 144:ef7eb2e8f9f7 2917
<> 144:ef7eb2e8f9f7 2918 #if defined( _CMU_HFRCOCTRL_BAND_MASK )
<> 144:ef7eb2e8f9f7 2919 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 2920 * @brief
<> 144:ef7eb2e8f9f7 2921 * Get HFRCO band in use.
<> 144:ef7eb2e8f9f7 2922 *
<> 144:ef7eb2e8f9f7 2923 * @return
<> 144:ef7eb2e8f9f7 2924 * HFRCO band in use.
<> 144:ef7eb2e8f9f7 2925 ******************************************************************************/
<> 144:ef7eb2e8f9f7 2926 CMU_HFRCOBand_TypeDef CMU_HFRCOBandGet(void)
<> 144:ef7eb2e8f9f7 2927 {
<> 144:ef7eb2e8f9f7 2928 return (CMU_HFRCOBand_TypeDef)((CMU->HFRCOCTRL & _CMU_HFRCOCTRL_BAND_MASK)
<> 144:ef7eb2e8f9f7 2929 >> _CMU_HFRCOCTRL_BAND_SHIFT);
<> 144:ef7eb2e8f9f7 2930 }
<> 144:ef7eb2e8f9f7 2931 #endif /* _CMU_HFRCOCTRL_BAND_MASK */
<> 144:ef7eb2e8f9f7 2932
<> 144:ef7eb2e8f9f7 2933
<> 144:ef7eb2e8f9f7 2934 #if defined( _CMU_HFRCOCTRL_BAND_MASK )
<> 144:ef7eb2e8f9f7 2935 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 2936 * @brief
<> 144:ef7eb2e8f9f7 2937 * Set HFRCO band and the tuning value based on the value in the calibration
<> 144:ef7eb2e8f9f7 2938 * table made during production.
<> 144:ef7eb2e8f9f7 2939 *
<> 144:ef7eb2e8f9f7 2940 * @param[in] band
<> 144:ef7eb2e8f9f7 2941 * HFRCO band to activate.
<> 144:ef7eb2e8f9f7 2942 ******************************************************************************/
<> 144:ef7eb2e8f9f7 2943 void CMU_HFRCOBandSet(CMU_HFRCOBand_TypeDef band)
<> 144:ef7eb2e8f9f7 2944 {
<> 144:ef7eb2e8f9f7 2945 uint32_t tuning;
<> 144:ef7eb2e8f9f7 2946 uint32_t freq;
<> 144:ef7eb2e8f9f7 2947 CMU_Select_TypeDef osc;
<> 144:ef7eb2e8f9f7 2948
<> 144:ef7eb2e8f9f7 2949 /* Read tuning value from calibration table */
<> 144:ef7eb2e8f9f7 2950 switch (band)
<> 144:ef7eb2e8f9f7 2951 {
<> 144:ef7eb2e8f9f7 2952 case cmuHFRCOBand_1MHz:
<> 144:ef7eb2e8f9f7 2953 tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND1_MASK)
<> 144:ef7eb2e8f9f7 2954 >> _DEVINFO_HFRCOCAL0_BAND1_SHIFT;
<> 144:ef7eb2e8f9f7 2955 break;
<> 144:ef7eb2e8f9f7 2956
<> 144:ef7eb2e8f9f7 2957 case cmuHFRCOBand_7MHz:
<> 144:ef7eb2e8f9f7 2958 tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND7_MASK)
<> 144:ef7eb2e8f9f7 2959 >> _DEVINFO_HFRCOCAL0_BAND7_SHIFT;
<> 144:ef7eb2e8f9f7 2960 break;
<> 144:ef7eb2e8f9f7 2961
<> 144:ef7eb2e8f9f7 2962 case cmuHFRCOBand_11MHz:
<> 144:ef7eb2e8f9f7 2963 tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND11_MASK)
<> 144:ef7eb2e8f9f7 2964 >> _DEVINFO_HFRCOCAL0_BAND11_SHIFT;
<> 144:ef7eb2e8f9f7 2965 break;
<> 144:ef7eb2e8f9f7 2966
<> 144:ef7eb2e8f9f7 2967 case cmuHFRCOBand_14MHz:
<> 144:ef7eb2e8f9f7 2968 tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND14_MASK)
<> 144:ef7eb2e8f9f7 2969 >> _DEVINFO_HFRCOCAL0_BAND14_SHIFT;
<> 144:ef7eb2e8f9f7 2970 break;
<> 144:ef7eb2e8f9f7 2971
<> 144:ef7eb2e8f9f7 2972 case cmuHFRCOBand_21MHz:
<> 144:ef7eb2e8f9f7 2973 tuning = (DEVINFO->HFRCOCAL1 & _DEVINFO_HFRCOCAL1_BAND21_MASK)
<> 144:ef7eb2e8f9f7 2974 >> _DEVINFO_HFRCOCAL1_BAND21_SHIFT;
<> 144:ef7eb2e8f9f7 2975 break;
<> 144:ef7eb2e8f9f7 2976
<> 144:ef7eb2e8f9f7 2977 #if defined( _CMU_HFRCOCTRL_BAND_28MHZ )
<> 144:ef7eb2e8f9f7 2978 case cmuHFRCOBand_28MHz:
<> 144:ef7eb2e8f9f7 2979 tuning = (DEVINFO->HFRCOCAL1 & _DEVINFO_HFRCOCAL1_BAND28_MASK)
<> 144:ef7eb2e8f9f7 2980 >> _DEVINFO_HFRCOCAL1_BAND28_SHIFT;
<> 144:ef7eb2e8f9f7 2981 break;
<> 144:ef7eb2e8f9f7 2982 #endif
<> 144:ef7eb2e8f9f7 2983
<> 144:ef7eb2e8f9f7 2984 default:
<> 144:ef7eb2e8f9f7 2985 EFM_ASSERT(0);
<> 144:ef7eb2e8f9f7 2986 return;
<> 144:ef7eb2e8f9f7 2987 }
<> 144:ef7eb2e8f9f7 2988
<> 144:ef7eb2e8f9f7 2989 /* If HFRCO is used for core clock, we have to consider flash access WS. */
<> 144:ef7eb2e8f9f7 2990 osc = CMU_ClockSelectGet(cmuClock_HF);
<> 144:ef7eb2e8f9f7 2991 if (osc == cmuSelect_HFRCO)
<> 144:ef7eb2e8f9f7 2992 {
<> 144:ef7eb2e8f9f7 2993 /* Configure worst case wait states for flash access before setting divider */
<> 144:ef7eb2e8f9f7 2994 flashWaitStateMax();
<> 144:ef7eb2e8f9f7 2995 }
<> 144:ef7eb2e8f9f7 2996
<> 144:ef7eb2e8f9f7 2997 /* Set band/tuning */
<> 144:ef7eb2e8f9f7 2998 CMU->HFRCOCTRL = (CMU->HFRCOCTRL &
<> 144:ef7eb2e8f9f7 2999 ~(_CMU_HFRCOCTRL_BAND_MASK | _CMU_HFRCOCTRL_TUNING_MASK))
<> 144:ef7eb2e8f9f7 3000 | (band << _CMU_HFRCOCTRL_BAND_SHIFT)
<> 144:ef7eb2e8f9f7 3001 | (tuning << _CMU_HFRCOCTRL_TUNING_SHIFT);
<> 144:ef7eb2e8f9f7 3002
<> 144:ef7eb2e8f9f7 3003 /* If HFRCO is used for core clock, optimize flash WS */
<> 144:ef7eb2e8f9f7 3004 if (osc == cmuSelect_HFRCO)
<> 144:ef7eb2e8f9f7 3005 {
<> 150:02e0a0aed4ec 3006 /* Call SystemCoreClockGet() to update CMSIS core clock variable. */
<> 144:ef7eb2e8f9f7 3007 freq = SystemCoreClockGet();
<> 144:ef7eb2e8f9f7 3008 flashWaitStateControl(freq);
<> 144:ef7eb2e8f9f7 3009 }
<> 150:02e0a0aed4ec 3010
<> 150:02e0a0aed4ec 3011 #if defined(CMU_MAX_FREQ_HFLE)
<> 150:02e0a0aed4ec 3012 /* Reduce HFLE frequency if possible. */
<> 150:02e0a0aed4ec 3013 setHfLeConfig(CMU_ClockFreqGet(cmuClock_HFLE), CMU_MAX_FREQ_HFLE);
<> 150:02e0a0aed4ec 3014 #endif
<> 150:02e0a0aed4ec 3015
<> 144:ef7eb2e8f9f7 3016 }
<> 144:ef7eb2e8f9f7 3017 #endif /* _CMU_HFRCOCTRL_BAND_MASK */
<> 144:ef7eb2e8f9f7 3018
<> 144:ef7eb2e8f9f7 3019
<> 144:ef7eb2e8f9f7 3020 #if defined( _CMU_HFRCOCTRL_FREQRANGE_MASK )
<> 144:ef7eb2e8f9f7 3021 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 3022 * @brief
<> 144:ef7eb2e8f9f7 3023 * Get a pointer to the HFRCO frequency calibration word in DEVINFO
<> 144:ef7eb2e8f9f7 3024 *
<> 144:ef7eb2e8f9f7 3025 * @param[in] freq
<> 144:ef7eb2e8f9f7 3026 * Frequency in Hz
<> 144:ef7eb2e8f9f7 3027 *
<> 144:ef7eb2e8f9f7 3028 * @return
<> 144:ef7eb2e8f9f7 3029 * HFRCO calibration word for a given frequency
<> 144:ef7eb2e8f9f7 3030 *****************************************************************************/
<> 144:ef7eb2e8f9f7 3031 static uint32_t CMU_HFRCODevinfoGet(CMU_HFRCOFreq_TypeDef freq)
<> 144:ef7eb2e8f9f7 3032 {
<> 144:ef7eb2e8f9f7 3033 switch (freq)
<> 144:ef7eb2e8f9f7 3034 {
<> 144:ef7eb2e8f9f7 3035 /* 1, 2 and 4MHz share the same calibration word */
<> 144:ef7eb2e8f9f7 3036 case cmuHFRCOFreq_1M0Hz:
<> 144:ef7eb2e8f9f7 3037 case cmuHFRCOFreq_2M0Hz:
<> 144:ef7eb2e8f9f7 3038 case cmuHFRCOFreq_4M0Hz:
<> 144:ef7eb2e8f9f7 3039 return DEVINFO->HFRCOCAL0;
<> 144:ef7eb2e8f9f7 3040
<> 144:ef7eb2e8f9f7 3041 case cmuHFRCOFreq_7M0Hz:
<> 144:ef7eb2e8f9f7 3042 return DEVINFO->HFRCOCAL3;
<> 144:ef7eb2e8f9f7 3043
<> 144:ef7eb2e8f9f7 3044 case cmuHFRCOFreq_13M0Hz:
<> 144:ef7eb2e8f9f7 3045 return DEVINFO->HFRCOCAL6;
<> 144:ef7eb2e8f9f7 3046
<> 144:ef7eb2e8f9f7 3047 case cmuHFRCOFreq_16M0Hz:
<> 144:ef7eb2e8f9f7 3048 return DEVINFO->HFRCOCAL7;
<> 144:ef7eb2e8f9f7 3049
<> 144:ef7eb2e8f9f7 3050 case cmuHFRCOFreq_19M0Hz:
<> 144:ef7eb2e8f9f7 3051 return DEVINFO->HFRCOCAL8;
<> 144:ef7eb2e8f9f7 3052
<> 144:ef7eb2e8f9f7 3053 case cmuHFRCOFreq_26M0Hz:
<> 144:ef7eb2e8f9f7 3054 return DEVINFO->HFRCOCAL10;
<> 144:ef7eb2e8f9f7 3055
<> 144:ef7eb2e8f9f7 3056 case cmuHFRCOFreq_32M0Hz:
<> 144:ef7eb2e8f9f7 3057 return DEVINFO->HFRCOCAL11;
<> 144:ef7eb2e8f9f7 3058
<> 144:ef7eb2e8f9f7 3059 case cmuHFRCOFreq_38M0Hz:
<> 144:ef7eb2e8f9f7 3060 return DEVINFO->HFRCOCAL12;
<> 144:ef7eb2e8f9f7 3061
<> 144:ef7eb2e8f9f7 3062 default: /* cmuHFRCOFreq_UserDefined */
<> 144:ef7eb2e8f9f7 3063 return 0;
<> 144:ef7eb2e8f9f7 3064 }
<> 144:ef7eb2e8f9f7 3065 }
<> 144:ef7eb2e8f9f7 3066
<> 144:ef7eb2e8f9f7 3067
<> 144:ef7eb2e8f9f7 3068 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 3069 * @brief
<> 150:02e0a0aed4ec 3070 * Get current HFRCO frequency.
<> 144:ef7eb2e8f9f7 3071 *
<> 144:ef7eb2e8f9f7 3072 * @return
<> 150:02e0a0aed4ec 3073 * HFRCO frequency
<> 144:ef7eb2e8f9f7 3074 ******************************************************************************/
<> 150:02e0a0aed4ec 3075 CMU_HFRCOFreq_TypeDef CMU_HFRCOBandGet(void)
<> 144:ef7eb2e8f9f7 3076 {
<> 144:ef7eb2e8f9f7 3077 return (CMU_HFRCOFreq_TypeDef)SystemHfrcoFreq;
<> 144:ef7eb2e8f9f7 3078 }
<> 144:ef7eb2e8f9f7 3079
<> 144:ef7eb2e8f9f7 3080
<> 144:ef7eb2e8f9f7 3081 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 3082 * @brief
<> 150:02e0a0aed4ec 3083 * Set HFRCO calibration for the selected target frequency.
<> 144:ef7eb2e8f9f7 3084 *
<> 150:02e0a0aed4ec 3085 * @param[in] setFreq
<> 150:02e0a0aed4ec 3086 * HFRCO frequency to set
<> 144:ef7eb2e8f9f7 3087 ******************************************************************************/
<> 150:02e0a0aed4ec 3088 void CMU_HFRCOBandSet(CMU_HFRCOFreq_TypeDef setFreq)
<> 144:ef7eb2e8f9f7 3089 {
<> 144:ef7eb2e8f9f7 3090 uint32_t freqCal;
<> 150:02e0a0aed4ec 3091 uint32_t sysFreq;
<> 144:ef7eb2e8f9f7 3092
<> 144:ef7eb2e8f9f7 3093 /* Get DEVINFO index, set CMSIS frequency SystemHfrcoFreq */
<> 150:02e0a0aed4ec 3094 freqCal = CMU_HFRCODevinfoGet(setFreq);
<> 144:ef7eb2e8f9f7 3095 EFM_ASSERT((freqCal != 0) && (freqCal != UINT_MAX));
<> 150:02e0a0aed4ec 3096 SystemHfrcoFreq = (uint32_t)setFreq;
<> 144:ef7eb2e8f9f7 3097
<> 144:ef7eb2e8f9f7 3098 /* Set max wait-states while changing core clock */
<> 144:ef7eb2e8f9f7 3099 if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO)
<> 144:ef7eb2e8f9f7 3100 {
<> 144:ef7eb2e8f9f7 3101 flashWaitStateMax();
<> 144:ef7eb2e8f9f7 3102 }
<> 144:ef7eb2e8f9f7 3103
<> 144:ef7eb2e8f9f7 3104 /* Wait for any previous sync to complete, and then set calibration data
<> 144:ef7eb2e8f9f7 3105 for the selected frequency. */
<> 144:ef7eb2e8f9f7 3106 while(BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_HFRCOBSY_SHIFT));
<> 144:ef7eb2e8f9f7 3107
<> 144:ef7eb2e8f9f7 3108 /* Check for valid calibration data */
<> 144:ef7eb2e8f9f7 3109 EFM_ASSERT(freqCal != UINT_MAX);
<> 144:ef7eb2e8f9f7 3110
<> 144:ef7eb2e8f9f7 3111 /* Set divider in HFRCOCTRL for 1, 2 and 4MHz */
<> 150:02e0a0aed4ec 3112 switch(setFreq)
<> 144:ef7eb2e8f9f7 3113 {
<> 144:ef7eb2e8f9f7 3114 case cmuHFRCOFreq_1M0Hz:
<> 144:ef7eb2e8f9f7 3115 freqCal = (freqCal & ~_CMU_HFRCOCTRL_CLKDIV_MASK)
<> 144:ef7eb2e8f9f7 3116 | CMU_HFRCOCTRL_CLKDIV_DIV4;
<> 144:ef7eb2e8f9f7 3117 break;
<> 144:ef7eb2e8f9f7 3118
<> 144:ef7eb2e8f9f7 3119 case cmuHFRCOFreq_2M0Hz:
<> 144:ef7eb2e8f9f7 3120 freqCal = (freqCal & ~_CMU_HFRCOCTRL_CLKDIV_MASK)
<> 144:ef7eb2e8f9f7 3121 | CMU_HFRCOCTRL_CLKDIV_DIV2;
<> 144:ef7eb2e8f9f7 3122 break;
<> 144:ef7eb2e8f9f7 3123
<> 144:ef7eb2e8f9f7 3124 case cmuHFRCOFreq_4M0Hz:
<> 144:ef7eb2e8f9f7 3125 freqCal = (freqCal & ~_CMU_HFRCOCTRL_CLKDIV_MASK)
<> 144:ef7eb2e8f9f7 3126 | CMU_HFRCOCTRL_CLKDIV_DIV1;
<> 144:ef7eb2e8f9f7 3127 break;
<> 144:ef7eb2e8f9f7 3128
<> 144:ef7eb2e8f9f7 3129 default:
<> 144:ef7eb2e8f9f7 3130 break;
<> 144:ef7eb2e8f9f7 3131 }
<> 150:02e0a0aed4ec 3132
<> 150:02e0a0aed4ec 3133 /* Update HFLE configuration before updating HFRCO.
<> 150:02e0a0aed4ec 3134 Use the new set frequency. */
<> 144:ef7eb2e8f9f7 3135 if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO)
<> 144:ef7eb2e8f9f7 3136 {
<> 150:02e0a0aed4ec 3137 /* setFreq is worst-case as dividers may reduce the HFLE frequency. */
<> 150:02e0a0aed4ec 3138 setHfLeConfig(setFreq, CMU_MAX_FREQ_HFLE);
<> 144:ef7eb2e8f9f7 3139 }
<> 150:02e0a0aed4ec 3140
<> 150:02e0a0aed4ec 3141 CMU->HFRCOCTRL = freqCal;
<> 150:02e0a0aed4ec 3142
<> 150:02e0a0aed4ec 3143 /* If HFRCO is selected as HF clock, optimize flash access wait-state configuration
<> 150:02e0a0aed4ec 3144 for this frequency and update CMSIS core clock variable. */
<> 150:02e0a0aed4ec 3145 if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO)
<> 150:02e0a0aed4ec 3146 {
<> 150:02e0a0aed4ec 3147 /* Call SystemCoreClockGet() to update CMSIS core clock variable. */
<> 150:02e0a0aed4ec 3148 sysFreq = SystemCoreClockGet();
<> 150:02e0a0aed4ec 3149 EFM_ASSERT(sysFreq <= (uint32_t)setFreq);
<> 150:02e0a0aed4ec 3150 EFM_ASSERT(sysFreq <= SystemHfrcoFreq);
<> 150:02e0a0aed4ec 3151 EFM_ASSERT(setFreq == SystemHfrcoFreq);
<> 150:02e0a0aed4ec 3152 flashWaitStateControl(sysFreq);
<> 150:02e0a0aed4ec 3153 }
<> 150:02e0a0aed4ec 3154
<> 150:02e0a0aed4ec 3155 /* Reduce HFLE frequency if possible. */
<> 150:02e0a0aed4ec 3156 setHfLeConfig(CMU_ClockFreqGet(cmuClock_HFLE), CMU_MAX_FREQ_HFLE);
<> 144:ef7eb2e8f9f7 3157 }
<> 144:ef7eb2e8f9f7 3158 #endif /* _CMU_HFRCOCTRL_FREQRANGE_MASK */
<> 144:ef7eb2e8f9f7 3159
<> 144:ef7eb2e8f9f7 3160 #if defined( _CMU_HFRCOCTRL_SUDELAY_MASK )
<> 144:ef7eb2e8f9f7 3161 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 3162 * @brief
<> 144:ef7eb2e8f9f7 3163 * Get the HFRCO startup delay.
<> 144:ef7eb2e8f9f7 3164 *
<> 144:ef7eb2e8f9f7 3165 * @details
<> 144:ef7eb2e8f9f7 3166 * Please refer to the reference manual for further details.
<> 144:ef7eb2e8f9f7 3167 *
<> 144:ef7eb2e8f9f7 3168 * @return
<> 144:ef7eb2e8f9f7 3169 * The startup delay in use.
<> 144:ef7eb2e8f9f7 3170 ******************************************************************************/
<> 144:ef7eb2e8f9f7 3171 uint32_t CMU_HFRCOStartupDelayGet(void)
<> 144:ef7eb2e8f9f7 3172 {
<> 144:ef7eb2e8f9f7 3173 return (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_SUDELAY_MASK)
<> 144:ef7eb2e8f9f7 3174 >> _CMU_HFRCOCTRL_SUDELAY_SHIFT;
<> 144:ef7eb2e8f9f7 3175 }
<> 144:ef7eb2e8f9f7 3176
<> 144:ef7eb2e8f9f7 3177
<> 144:ef7eb2e8f9f7 3178 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 3179 * @brief
<> 144:ef7eb2e8f9f7 3180 * Set the HFRCO startup delay.
<> 144:ef7eb2e8f9f7 3181 *
<> 144:ef7eb2e8f9f7 3182 * @details
<> 144:ef7eb2e8f9f7 3183 * Please refer to the reference manual for further details.
<> 144:ef7eb2e8f9f7 3184 *
<> 144:ef7eb2e8f9f7 3185 * @param[in] delay
<> 144:ef7eb2e8f9f7 3186 * The startup delay to set (<= 31).
<> 144:ef7eb2e8f9f7 3187 ******************************************************************************/
<> 144:ef7eb2e8f9f7 3188 void CMU_HFRCOStartupDelaySet(uint32_t delay)
<> 144:ef7eb2e8f9f7 3189 {
<> 144:ef7eb2e8f9f7 3190 EFM_ASSERT(delay <= 31);
<> 144:ef7eb2e8f9f7 3191
<> 144:ef7eb2e8f9f7 3192 delay &= _CMU_HFRCOCTRL_SUDELAY_MASK >> _CMU_HFRCOCTRL_SUDELAY_SHIFT;
<> 144:ef7eb2e8f9f7 3193 CMU->HFRCOCTRL = (CMU->HFRCOCTRL & ~(_CMU_HFRCOCTRL_SUDELAY_MASK))
<> 144:ef7eb2e8f9f7 3194 | (delay << _CMU_HFRCOCTRL_SUDELAY_SHIFT);
<> 144:ef7eb2e8f9f7 3195 }
<> 144:ef7eb2e8f9f7 3196 #endif
<> 144:ef7eb2e8f9f7 3197
<> 144:ef7eb2e8f9f7 3198
<> 150:02e0a0aed4ec 3199 #if defined( _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK )
<> 144:ef7eb2e8f9f7 3200 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 3201 * @brief
<> 144:ef7eb2e8f9f7 3202 * Enable or disable HFXO autostart
<> 144:ef7eb2e8f9f7 3203 *
<> 150:02e0a0aed4ec 3204 * @param[in] userSel
<> 150:02e0a0aed4ec 3205 * Additional user specified enable bit.
<> 144:ef7eb2e8f9f7 3206 *
<> 144:ef7eb2e8f9f7 3207 * @param[in] enEM0EM1Start
<> 144:ef7eb2e8f9f7 3208 * If true, HFXO is automatically started upon entering EM0/EM1 entry from
<> 144:ef7eb2e8f9f7 3209 * EM2/EM3. HFXO selection has to be handled by the user.
<> 144:ef7eb2e8f9f7 3210 * If false, HFXO is not started automatically when entering EM0/EM1.
<> 144:ef7eb2e8f9f7 3211 *
<> 144:ef7eb2e8f9f7 3212 * @param[in] enEM0EM1StartSel
<> 144:ef7eb2e8f9f7 3213 * If true, HFXO is automatically started and immediately selected upon
<> 144:ef7eb2e8f9f7 3214 * entering EM0/EM1 entry from EM2/EM3. Note that this option stalls the use of
<> 144:ef7eb2e8f9f7 3215 * HFSRCCLK until HFXO becomes ready.
<> 144:ef7eb2e8f9f7 3216 * If false, HFXO is not started or selected automatically when entering
<> 144:ef7eb2e8f9f7 3217 * EM0/EM1.
<> 144:ef7eb2e8f9f7 3218 ******************************************************************************/
<> 150:02e0a0aed4ec 3219 void CMU_HFXOAutostartEnable(uint32_t userSel,
<> 144:ef7eb2e8f9f7 3220 bool enEM0EM1Start,
<> 144:ef7eb2e8f9f7 3221 bool enEM0EM1StartSel)
<> 144:ef7eb2e8f9f7 3222 {
<> 150:02e0a0aed4ec 3223 uint32_t hfxoFreq;
<> 144:ef7eb2e8f9f7 3224 uint32_t hfxoCtrl;
<> 150:02e0a0aed4ec 3225
<> 150:02e0a0aed4ec 3226 /* Mask supported enable bits. */
<> 150:02e0a0aed4ec 3227 #if defined( _CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK )
<> 150:02e0a0aed4ec 3228 userSel &= _CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK;
<> 150:02e0a0aed4ec 3229 #else
<> 150:02e0a0aed4ec 3230 userSel = 0;
<> 150:02e0a0aed4ec 3231 #endif
<> 150:02e0a0aed4ec 3232
<> 150:02e0a0aed4ec 3233 hfxoCtrl = CMU->HFXOCTRL & ~( userSel
<> 144:ef7eb2e8f9f7 3234 | _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK
<> 144:ef7eb2e8f9f7 3235 | _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK);
<> 144:ef7eb2e8f9f7 3236
<> 150:02e0a0aed4ec 3237 hfxoCtrl |= userSel
<> 144:ef7eb2e8f9f7 3238 | (enEM0EM1Start ? CMU_HFXOCTRL_AUTOSTARTEM0EM1 : 0)
<> 144:ef7eb2e8f9f7 3239 | (enEM0EM1StartSel ? CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 : 0);
<> 144:ef7eb2e8f9f7 3240
<> 144:ef7eb2e8f9f7 3241 CMU->HFXOCTRL = hfxoCtrl;
<> 150:02e0a0aed4ec 3242
<> 150:02e0a0aed4ec 3243 /* Set wait-states for HFXO if automatic start and select is configured. */
<> 150:02e0a0aed4ec 3244 if (userSel || enEM0EM1StartSel)
<> 150:02e0a0aed4ec 3245 {
<> 150:02e0a0aed4ec 3246 hfxoFreq = SystemHFXOClockGet();
<> 150:02e0a0aed4ec 3247 flashWaitStateControl(hfxoFreq);
<> 150:02e0a0aed4ec 3248 setHfLeConfig(hfxoFreq, CMU_MAX_FREQ_HFLE);
<> 150:02e0a0aed4ec 3249 }
<> 144:ef7eb2e8f9f7 3250 }
<> 150:02e0a0aed4ec 3251 #endif
<> 150:02e0a0aed4ec 3252
<> 150:02e0a0aed4ec 3253
<> 144:ef7eb2e8f9f7 3254 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 3255 * @brief
<> 144:ef7eb2e8f9f7 3256 * Set HFXO control registers
<> 144:ef7eb2e8f9f7 3257 *
<> 144:ef7eb2e8f9f7 3258 * @note
<> 144:ef7eb2e8f9f7 3259 * HFXO configuration should be obtained from a configuration tool,
<> 144:ef7eb2e8f9f7 3260 * app note or xtal datasheet. This function disables the HFXO to ensure
<> 144:ef7eb2e8f9f7 3261 * a valid state before update.
<> 144:ef7eb2e8f9f7 3262 *
<> 144:ef7eb2e8f9f7 3263 * @param[in] hfxoInit
<> 144:ef7eb2e8f9f7 3264 * HFXO setup parameters
<> 144:ef7eb2e8f9f7 3265 *****************************************************************************/
<> 150:02e0a0aed4ec 3266 void CMU_HFXOInit(const CMU_HFXOInit_TypeDef *hfxoInit)
<> 144:ef7eb2e8f9f7 3267 {
<> 144:ef7eb2e8f9f7 3268 /* Do not disable HFXO if it is currently selected as HF/Core clock */
<> 144:ef7eb2e8f9f7 3269 EFM_ASSERT(CMU_ClockSelectGet(cmuClock_HF) != cmuSelect_HFXO);
<> 144:ef7eb2e8f9f7 3270
<> 144:ef7eb2e8f9f7 3271 /* HFXO must be disabled before reconfiguration */
<> 150:02e0a0aed4ec 3272 CMU_OscillatorEnable(cmuOsc_HFXO, false, true);
<> 150:02e0a0aed4ec 3273
<> 150:02e0a0aed4ec 3274 #if defined( _CMU_HFXOCTRL_MASK )
<> 150:02e0a0aed4ec 3275 /* Verify that the deprecated autostart fields are not used,
<> 150:02e0a0aed4ec 3276 * @ref CMU_HFXOAutostartEnable must be used instead. */
<> 150:02e0a0aed4ec 3277 EFM_ASSERT(!(hfxoInit->autoStartEm01
<> 150:02e0a0aed4ec 3278 || hfxoInit->autoSelEm01
<> 150:02e0a0aed4ec 3279 || hfxoInit->autoStartSelOnRacWakeup));
<> 150:02e0a0aed4ec 3280
<> 150:02e0a0aed4ec 3281 uint32_t mode = CMU_HFXOCTRL_MODE_XTAL;
<> 150:02e0a0aed4ec 3282
<> 150:02e0a0aed4ec 3283 /* AC coupled external clock not supported */
<> 150:02e0a0aed4ec 3284 EFM_ASSERT(hfxoInit->mode != cmuOscMode_AcCoupled);
<> 150:02e0a0aed4ec 3285 if (hfxoInit->mode == cmuOscMode_External)
<> 150:02e0a0aed4ec 3286 {
<> 150:02e0a0aed4ec 3287 mode = CMU_HFXOCTRL_MODE_EXTCLK;
<> 150:02e0a0aed4ec 3288 }
<> 144:ef7eb2e8f9f7 3289
<> 144:ef7eb2e8f9f7 3290 /* Apply control settings */
<> 144:ef7eb2e8f9f7 3291 BUS_RegMaskedWrite(&CMU->HFXOCTRL,
<> 150:02e0a0aed4ec 3292 _CMU_HFXOCTRL_LOWPOWER_MASK | _CMU_HFXOCTRL_MODE_MASK,
<> 150:02e0a0aed4ec 3293 (hfxoInit->lowPowerMode ? CMU_HFXOCTRL_LOWPOWER : 0) | mode);
<> 144:ef7eb2e8f9f7 3294
<> 144:ef7eb2e8f9f7 3295 /* Set XTAL tuning parameters */
<> 144:ef7eb2e8f9f7 3296
<> 150:02e0a0aed4ec 3297 #if defined(_CMU_HFXOCTRL1_PEAKDETTHR_MASK)
<> 150:02e0a0aed4ec 3298 /* Set peak detection threshold */
<> 150:02e0a0aed4ec 3299 BUS_RegMaskedWrite(&CMU->HFXOCTRL1,
<> 150:02e0a0aed4ec 3300 _CMU_HFXOCTRL1_PEAKDETTHR_MASK,
<> 150:02e0a0aed4ec 3301 hfxoInit->thresholdPeakDetect);
<> 150:02e0a0aed4ec 3302 #endif
<> 144:ef7eb2e8f9f7 3303
<> 144:ef7eb2e8f9f7 3304 /* Set tuning for startup and steady state */
<> 144:ef7eb2e8f9f7 3305 BUS_RegMaskedWrite(&CMU->HFXOSTARTUPCTRL,
<> 144:ef7eb2e8f9f7 3306 _CMU_HFXOSTARTUPCTRL_CTUNE_MASK
<> 150:02e0a0aed4ec 3307 | _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK,
<> 144:ef7eb2e8f9f7 3308 (hfxoInit->ctuneStartup
<> 144:ef7eb2e8f9f7 3309 << _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT)
<> 144:ef7eb2e8f9f7 3310 | (hfxoInit->xoCoreBiasTrimStartup
<> 150:02e0a0aed4ec 3311 << _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT));
<> 144:ef7eb2e8f9f7 3312
<> 144:ef7eb2e8f9f7 3313 BUS_RegMaskedWrite(&CMU->HFXOSTEADYSTATECTRL,
<> 144:ef7eb2e8f9f7 3314 _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK
<> 144:ef7eb2e8f9f7 3315 | _CMU_HFXOSTEADYSTATECTRL_REGISH_MASK
<> 144:ef7eb2e8f9f7 3316 | _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK
<> 144:ef7eb2e8f9f7 3317 | _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK,
<> 144:ef7eb2e8f9f7 3318 (hfxoInit->ctuneSteadyState
<> 144:ef7eb2e8f9f7 3319 << _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT)
<> 144:ef7eb2e8f9f7 3320 | (hfxoInit->regIshSteadyState
<> 144:ef7eb2e8f9f7 3321 << _CMU_HFXOSTEADYSTATECTRL_REGISH_SHIFT)
<> 144:ef7eb2e8f9f7 3322 | (hfxoInit->xoCoreBiasTrimSteadyState
<> 144:ef7eb2e8f9f7 3323 << _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT)
<> 150:02e0a0aed4ec 3324 | getRegIshUpperVal(hfxoInit->regIshSteadyState));
<> 144:ef7eb2e8f9f7 3325
<> 144:ef7eb2e8f9f7 3326 /* Set timeouts */
<> 144:ef7eb2e8f9f7 3327 BUS_RegMaskedWrite(&CMU->HFXOTIMEOUTCTRL,
<> 144:ef7eb2e8f9f7 3328 _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_MASK
<> 144:ef7eb2e8f9f7 3329 | _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK
<> 144:ef7eb2e8f9f7 3330 | _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK
<> 144:ef7eb2e8f9f7 3331 | _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK,
<> 144:ef7eb2e8f9f7 3332 (hfxoInit->timeoutShuntOptimization
<> 144:ef7eb2e8f9f7 3333 << _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_SHIFT)
<> 144:ef7eb2e8f9f7 3334 | (hfxoInit->timeoutPeakDetect
<> 144:ef7eb2e8f9f7 3335 << _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT)
<> 144:ef7eb2e8f9f7 3336 | (hfxoInit->timeoutSteady
<> 144:ef7eb2e8f9f7 3337 << _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT)
<> 144:ef7eb2e8f9f7 3338 | (hfxoInit->timeoutStartup
<> 144:ef7eb2e8f9f7 3339 << _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT));
<> 150:02e0a0aed4ec 3340 #else
<> 150:02e0a0aed4ec 3341 BUS_RegMaskedWrite(&CMU->CTRL,
<> 150:02e0a0aed4ec 3342 _CMU_CTRL_HFXOTIMEOUT_MASK
<> 150:02e0a0aed4ec 3343 | _CMU_CTRL_HFXOBOOST_MASK
<> 150:02e0a0aed4ec 3344 | _CMU_CTRL_HFXOMODE_MASK
<> 150:02e0a0aed4ec 3345 | _CMU_CTRL_HFXOGLITCHDETEN_MASK,
<> 150:02e0a0aed4ec 3346 (hfxoInit->timeout << _CMU_CTRL_HFXOTIMEOUT_SHIFT)
<> 150:02e0a0aed4ec 3347 | (hfxoInit->boost << _CMU_CTRL_HFXOBOOST_SHIFT)
<> 150:02e0a0aed4ec 3348 | (hfxoInit->mode << _CMU_CTRL_HFXOMODE_SHIFT)
<> 150:02e0a0aed4ec 3349 | (hfxoInit->glitchDetector ? CMU_CTRL_HFXOGLITCHDETEN : 0));
<> 150:02e0a0aed4ec 3350 #endif
<> 144:ef7eb2e8f9f7 3351 }
<> 144:ef7eb2e8f9f7 3352
<> 144:ef7eb2e8f9f7 3353
<> 144:ef7eb2e8f9f7 3354 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 3355 * @brief
<> 144:ef7eb2e8f9f7 3356 * Get the LCD framerate divisor (FDIV) setting.
<> 144:ef7eb2e8f9f7 3357 *
<> 144:ef7eb2e8f9f7 3358 * @return
<> 144:ef7eb2e8f9f7 3359 * The LCD framerate divisor.
<> 144:ef7eb2e8f9f7 3360 ******************************************************************************/
<> 144:ef7eb2e8f9f7 3361 uint32_t CMU_LCDClkFDIVGet(void)
<> 144:ef7eb2e8f9f7 3362 {
<> 144:ef7eb2e8f9f7 3363 #if defined( LCD_PRESENT )
<> 144:ef7eb2e8f9f7 3364 return (CMU->LCDCTRL & _CMU_LCDCTRL_FDIV_MASK) >> _CMU_LCDCTRL_FDIV_SHIFT;
<> 144:ef7eb2e8f9f7 3365 #else
<> 144:ef7eb2e8f9f7 3366 return 0;
<> 144:ef7eb2e8f9f7 3367 #endif /* defined(LCD_PRESENT) */
<> 144:ef7eb2e8f9f7 3368 }
<> 144:ef7eb2e8f9f7 3369
<> 144:ef7eb2e8f9f7 3370
<> 144:ef7eb2e8f9f7 3371 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 3372 * @brief
<> 144:ef7eb2e8f9f7 3373 * Set the LCD framerate divisor (FDIV) setting.
<> 144:ef7eb2e8f9f7 3374 *
<> 144:ef7eb2e8f9f7 3375 * @note
<> 144:ef7eb2e8f9f7 3376 * The FDIV field (CMU LCDCTRL register) should only be modified while the
<> 144:ef7eb2e8f9f7 3377 * LCD module is clock disabled (CMU LFACLKEN0.LCD bit is 0). This function
<> 144:ef7eb2e8f9f7 3378 * will NOT modify FDIV if the LCD module clock is enabled. Please refer to
<> 144:ef7eb2e8f9f7 3379 * CMU_ClockEnable() for disabling/enabling LCD clock.
<> 144:ef7eb2e8f9f7 3380 *
<> 144:ef7eb2e8f9f7 3381 * @param[in] div
<> 144:ef7eb2e8f9f7 3382 * The FDIV setting to use.
<> 144:ef7eb2e8f9f7 3383 ******************************************************************************/
<> 144:ef7eb2e8f9f7 3384 void CMU_LCDClkFDIVSet(uint32_t div)
<> 144:ef7eb2e8f9f7 3385 {
<> 144:ef7eb2e8f9f7 3386 #if defined( LCD_PRESENT )
<> 144:ef7eb2e8f9f7 3387 EFM_ASSERT(div <= cmuClkDiv_128);
<> 144:ef7eb2e8f9f7 3388
<> 144:ef7eb2e8f9f7 3389 /* Do not allow modification if LCD clock enabled */
<> 144:ef7eb2e8f9f7 3390 if (CMU->LFACLKEN0 & CMU_LFACLKEN0_LCD)
<> 144:ef7eb2e8f9f7 3391 {
<> 144:ef7eb2e8f9f7 3392 return;
<> 144:ef7eb2e8f9f7 3393 }
<> 144:ef7eb2e8f9f7 3394
<> 144:ef7eb2e8f9f7 3395 div <<= _CMU_LCDCTRL_FDIV_SHIFT;
<> 144:ef7eb2e8f9f7 3396 div &= _CMU_LCDCTRL_FDIV_MASK;
<> 144:ef7eb2e8f9f7 3397 CMU->LCDCTRL = (CMU->LCDCTRL & ~_CMU_LCDCTRL_FDIV_MASK) | div;
<> 144:ef7eb2e8f9f7 3398 #else
<> 144:ef7eb2e8f9f7 3399 (void)div; /* Unused parameter */
<> 144:ef7eb2e8f9f7 3400 #endif /* defined(LCD_PRESENT) */
<> 144:ef7eb2e8f9f7 3401 }
<> 144:ef7eb2e8f9f7 3402
<> 144:ef7eb2e8f9f7 3403
<> 144:ef7eb2e8f9f7 3404 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 3405 * @brief
<> 144:ef7eb2e8f9f7 3406 * Set LFXO control registers
<> 144:ef7eb2e8f9f7 3407 *
<> 144:ef7eb2e8f9f7 3408 * @note
<> 144:ef7eb2e8f9f7 3409 * LFXO configuration should be obtained from a configuration tool,
<> 144:ef7eb2e8f9f7 3410 * app note or xtal datasheet. This function disables the LFXO to ensure
<> 144:ef7eb2e8f9f7 3411 * a valid state before update.
<> 144:ef7eb2e8f9f7 3412 *
<> 144:ef7eb2e8f9f7 3413 * @param[in] lfxoInit
<> 144:ef7eb2e8f9f7 3414 * LFXO setup parameters
<> 144:ef7eb2e8f9f7 3415 *****************************************************************************/
<> 150:02e0a0aed4ec 3416 void CMU_LFXOInit(const CMU_LFXOInit_TypeDef *lfxoInit)
<> 144:ef7eb2e8f9f7 3417 {
<> 144:ef7eb2e8f9f7 3418 /* Do not disable LFXO if it is currently selected as HF/Core clock */
<> 144:ef7eb2e8f9f7 3419 EFM_ASSERT(CMU_ClockSelectGet(cmuClock_HF) != cmuSelect_LFXO);
<> 144:ef7eb2e8f9f7 3420
<> 144:ef7eb2e8f9f7 3421 /* LFXO must be disabled before reconfiguration */
<> 144:ef7eb2e8f9f7 3422 CMU_OscillatorEnable(cmuOsc_LFXO, false, false);
<> 144:ef7eb2e8f9f7 3423
<> 150:02e0a0aed4ec 3424 #if defined( _CMU_LFXOCTRL_MASK )
<> 144:ef7eb2e8f9f7 3425 BUS_RegMaskedWrite(&CMU->LFXOCTRL,
<> 144:ef7eb2e8f9f7 3426 _CMU_LFXOCTRL_TUNING_MASK
<> 144:ef7eb2e8f9f7 3427 | _CMU_LFXOCTRL_GAIN_MASK
<> 150:02e0a0aed4ec 3428 | _CMU_LFXOCTRL_TIMEOUT_MASK
<> 150:02e0a0aed4ec 3429 | _CMU_LFXOCTRL_MODE_MASK,
<> 144:ef7eb2e8f9f7 3430 (lfxoInit->ctune << _CMU_LFXOCTRL_TUNING_SHIFT)
<> 144:ef7eb2e8f9f7 3431 | (lfxoInit->gain << _CMU_LFXOCTRL_GAIN_SHIFT)
<> 150:02e0a0aed4ec 3432 | (lfxoInit->timeout << _CMU_LFXOCTRL_TIMEOUT_SHIFT)
<> 150:02e0a0aed4ec 3433 | (lfxoInit->mode << _CMU_LFXOCTRL_MODE_SHIFT));
<> 150:02e0a0aed4ec 3434 #else
<> 150:02e0a0aed4ec 3435 bool cmuBoost = (lfxoInit->boost & 0x2);
<> 150:02e0a0aed4ec 3436 BUS_RegMaskedWrite(&CMU->CTRL,
<> 150:02e0a0aed4ec 3437 _CMU_CTRL_LFXOTIMEOUT_MASK
<> 150:02e0a0aed4ec 3438 | _CMU_CTRL_LFXOBOOST_MASK
<> 150:02e0a0aed4ec 3439 | _CMU_CTRL_LFXOMODE_MASK,
<> 150:02e0a0aed4ec 3440 (lfxoInit->timeout << _CMU_CTRL_LFXOTIMEOUT_SHIFT)
<> 150:02e0a0aed4ec 3441 | ((cmuBoost ? 1 : 0) << _CMU_CTRL_LFXOBOOST_SHIFT)
<> 150:02e0a0aed4ec 3442 | (lfxoInit->mode << _CMU_CTRL_LFXOMODE_SHIFT));
<> 150:02e0a0aed4ec 3443 #endif
<> 150:02e0a0aed4ec 3444
<> 150:02e0a0aed4ec 3445 #if defined( _EMU_AUXCTRL_REDLFXOBOOST_MASK )
<> 150:02e0a0aed4ec 3446 bool emuReduce = (lfxoInit->boost & 0x1);
<> 150:02e0a0aed4ec 3447 BUS_RegBitWrite(&EMU->AUXCTRL, _EMU_AUXCTRL_REDLFXOBOOST_SHIFT, emuReduce ? 1 : 0);
<> 150:02e0a0aed4ec 3448 #endif
<> 144:ef7eb2e8f9f7 3449 }
<> 144:ef7eb2e8f9f7 3450
<> 144:ef7eb2e8f9f7 3451
<> 144:ef7eb2e8f9f7 3452 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 3453 * @brief
<> 144:ef7eb2e8f9f7 3454 * Enable/disable oscillator.
<> 144:ef7eb2e8f9f7 3455 *
<> 144:ef7eb2e8f9f7 3456 * @note
<> 144:ef7eb2e8f9f7 3457 * WARNING: When this function is called to disable either cmuOsc_LFXO or
<> 144:ef7eb2e8f9f7 3458 * cmuOsc_HFXO the LFXOMODE or HFXOMODE fields of the CMU_CTRL register
<> 144:ef7eb2e8f9f7 3459 * are reset to the reset value. I.e. if external clock sources are selected
<> 144:ef7eb2e8f9f7 3460 * in either LFXOMODE or HFXOMODE fields, the configuration will be cleared
<> 144:ef7eb2e8f9f7 3461 * and needs to be reconfigured if needed later.
<> 144:ef7eb2e8f9f7 3462 *
<> 144:ef7eb2e8f9f7 3463 * @param[in] osc
<> 144:ef7eb2e8f9f7 3464 * The oscillator to enable/disable.
<> 144:ef7eb2e8f9f7 3465 *
<> 144:ef7eb2e8f9f7 3466 * @param[in] enable
<> 144:ef7eb2e8f9f7 3467 * @li true - enable specified oscillator.
<> 144:ef7eb2e8f9f7 3468 * @li false - disable specified oscillator.
<> 144:ef7eb2e8f9f7 3469 *
<> 144:ef7eb2e8f9f7 3470 * @param[in] wait
<> 144:ef7eb2e8f9f7 3471 * Only used if @p enable is true.
<> 144:ef7eb2e8f9f7 3472 * @li true - wait for oscillator start-up time to timeout before returning.
<> 144:ef7eb2e8f9f7 3473 * @li false - do not wait for oscillator start-up time to timeout before
<> 144:ef7eb2e8f9f7 3474 * returning.
<> 144:ef7eb2e8f9f7 3475 ******************************************************************************/
<> 144:ef7eb2e8f9f7 3476 void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait)
<> 144:ef7eb2e8f9f7 3477 {
<> 144:ef7eb2e8f9f7 3478 uint32_t rdyBitPos;
<> 144:ef7eb2e8f9f7 3479 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
<> 144:ef7eb2e8f9f7 3480 uint32_t ensBitPos;
<> 144:ef7eb2e8f9f7 3481 #endif
<> 150:02e0a0aed4ec 3482 #if defined( _CMU_STATUS_HFXOSHUNTOPTRDY_MASK )
<> 150:02e0a0aed4ec 3483 uint32_t hfxoTrimStatus;
<> 150:02e0a0aed4ec 3484 #endif
<> 150:02e0a0aed4ec 3485
<> 144:ef7eb2e8f9f7 3486 uint32_t enBit;
<> 144:ef7eb2e8f9f7 3487 uint32_t disBit;
<> 144:ef7eb2e8f9f7 3488
<> 144:ef7eb2e8f9f7 3489 switch (osc)
<> 144:ef7eb2e8f9f7 3490 {
<> 144:ef7eb2e8f9f7 3491 case cmuOsc_HFRCO:
<> 144:ef7eb2e8f9f7 3492 enBit = CMU_OSCENCMD_HFRCOEN;
<> 144:ef7eb2e8f9f7 3493 disBit = CMU_OSCENCMD_HFRCODIS;
<> 144:ef7eb2e8f9f7 3494 rdyBitPos = _CMU_STATUS_HFRCORDY_SHIFT;
<> 144:ef7eb2e8f9f7 3495 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
<> 144:ef7eb2e8f9f7 3496 ensBitPos = _CMU_STATUS_HFRCOENS_SHIFT;
<> 144:ef7eb2e8f9f7 3497 #endif
<> 144:ef7eb2e8f9f7 3498 break;
<> 144:ef7eb2e8f9f7 3499
<> 144:ef7eb2e8f9f7 3500 case cmuOsc_HFXO:
<> 144:ef7eb2e8f9f7 3501 enBit = CMU_OSCENCMD_HFXOEN;
<> 144:ef7eb2e8f9f7 3502 disBit = CMU_OSCENCMD_HFXODIS;
<> 144:ef7eb2e8f9f7 3503 rdyBitPos = _CMU_STATUS_HFXORDY_SHIFT;
<> 144:ef7eb2e8f9f7 3504 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
<> 144:ef7eb2e8f9f7 3505 ensBitPos = _CMU_STATUS_HFXOENS_SHIFT;
<> 144:ef7eb2e8f9f7 3506 #endif
<> 144:ef7eb2e8f9f7 3507 break;
<> 144:ef7eb2e8f9f7 3508
<> 144:ef7eb2e8f9f7 3509 case cmuOsc_AUXHFRCO:
<> 144:ef7eb2e8f9f7 3510 enBit = CMU_OSCENCMD_AUXHFRCOEN;
<> 144:ef7eb2e8f9f7 3511 disBit = CMU_OSCENCMD_AUXHFRCODIS;
<> 144:ef7eb2e8f9f7 3512 rdyBitPos = _CMU_STATUS_AUXHFRCORDY_SHIFT;
<> 144:ef7eb2e8f9f7 3513 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
<> 144:ef7eb2e8f9f7 3514 ensBitPos = _CMU_STATUS_AUXHFRCOENS_SHIFT;
<> 144:ef7eb2e8f9f7 3515 #endif
<> 144:ef7eb2e8f9f7 3516 break;
<> 144:ef7eb2e8f9f7 3517
<> 144:ef7eb2e8f9f7 3518 case cmuOsc_LFRCO:
<> 144:ef7eb2e8f9f7 3519 enBit = CMU_OSCENCMD_LFRCOEN;
<> 144:ef7eb2e8f9f7 3520 disBit = CMU_OSCENCMD_LFRCODIS;
<> 144:ef7eb2e8f9f7 3521 rdyBitPos = _CMU_STATUS_LFRCORDY_SHIFT;
<> 144:ef7eb2e8f9f7 3522 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
<> 144:ef7eb2e8f9f7 3523 ensBitPos = _CMU_STATUS_LFRCOENS_SHIFT;
<> 144:ef7eb2e8f9f7 3524 #endif
<> 144:ef7eb2e8f9f7 3525 break;
<> 144:ef7eb2e8f9f7 3526
<> 144:ef7eb2e8f9f7 3527 case cmuOsc_LFXO:
<> 144:ef7eb2e8f9f7 3528 enBit = CMU_OSCENCMD_LFXOEN;
<> 144:ef7eb2e8f9f7 3529 disBit = CMU_OSCENCMD_LFXODIS;
<> 144:ef7eb2e8f9f7 3530 rdyBitPos = _CMU_STATUS_LFXORDY_SHIFT;
<> 144:ef7eb2e8f9f7 3531 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
<> 144:ef7eb2e8f9f7 3532 ensBitPos = _CMU_STATUS_LFXOENS_SHIFT;
<> 144:ef7eb2e8f9f7 3533 #endif
<> 144:ef7eb2e8f9f7 3534 break;
<> 144:ef7eb2e8f9f7 3535
<> 144:ef7eb2e8f9f7 3536 #if defined( _CMU_STATUS_USHFRCOENS_MASK )
<> 144:ef7eb2e8f9f7 3537 case cmuOsc_USHFRCO:
<> 144:ef7eb2e8f9f7 3538 enBit = CMU_OSCENCMD_USHFRCOEN;
<> 144:ef7eb2e8f9f7 3539 disBit = CMU_OSCENCMD_USHFRCODIS;
<> 144:ef7eb2e8f9f7 3540 rdyBitPos = _CMU_STATUS_USHFRCORDY_SHIFT;
<> 144:ef7eb2e8f9f7 3541 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
<> 144:ef7eb2e8f9f7 3542 ensBitPos = _CMU_STATUS_USHFRCOENS_SHIFT;
<> 144:ef7eb2e8f9f7 3543 #endif
<> 144:ef7eb2e8f9f7 3544 break;
<> 144:ef7eb2e8f9f7 3545 #endif
<> 144:ef7eb2e8f9f7 3546
<> 144:ef7eb2e8f9f7 3547 default:
<> 150:02e0a0aed4ec 3548 /* Undefined clock source or cmuOsc_ULFRCO. ULFRCO is always enabled,
<> 150:02e0a0aed4ec 3549 and cannot be disabled. Ie. the definition of cmuOsc_ULFRCO is primarely
<> 150:02e0a0aed4ec 3550 intended for information: the ULFRCO is always on. */
<> 144:ef7eb2e8f9f7 3551 EFM_ASSERT(0);
<> 144:ef7eb2e8f9f7 3552 return;
<> 144:ef7eb2e8f9f7 3553 }
<> 144:ef7eb2e8f9f7 3554
<> 144:ef7eb2e8f9f7 3555 if (enable)
<> 144:ef7eb2e8f9f7 3556 {
<> 150:02e0a0aed4ec 3557 #if defined( _CMU_HFXOCTRL_MASK )
<> 150:02e0a0aed4ec 3558 bool firstHfxoEnable = false;
<> 150:02e0a0aed4ec 3559
<> 150:02e0a0aed4ec 3560 /* Enabling the HFXO for the first time requires special handling. We use the
<> 150:02e0a0aed4ec 3561 * PEAKDETSHUTOPTMODE field of the HFXOCTRL register to see if this is the
<> 150:02e0a0aed4ec 3562 * first time the HFXO is enabled. */
<> 150:02e0a0aed4ec 3563 if ((osc == cmuOsc_HFXO) &&
<> 150:02e0a0aed4ec 3564 ((CMU->HFXOCTRL & (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK))
<> 150:02e0a0aed4ec 3565 == CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD))
<> 150:02e0a0aed4ec 3566 {
<> 150:02e0a0aed4ec 3567 firstHfxoEnable = true;
<> 150:02e0a0aed4ec 3568 /* First time we enable an external clock we should switch to CMD mode to make sure that
<> 150:02e0a0aed4ec 3569 * we only do SCO and not PDA tuning. */
<> 150:02e0a0aed4ec 3570 if ((CMU->HFXOCTRL & (_CMU_HFXOCTRL_MODE_MASK)) == CMU_HFXOCTRL_MODE_EXTCLK)
<> 150:02e0a0aed4ec 3571 {
<> 150:02e0a0aed4ec 3572 CMU->HFXOCTRL = (CMU->HFXOCTRL & ~_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK)
<> 150:02e0a0aed4ec 3573 | CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD;
<> 150:02e0a0aed4ec 3574 }
<> 150:02e0a0aed4ec 3575 }
<> 150:02e0a0aed4ec 3576 #endif
<> 144:ef7eb2e8f9f7 3577 CMU->OSCENCMD = enBit;
<> 144:ef7eb2e8f9f7 3578
<> 144:ef7eb2e8f9f7 3579 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
<> 144:ef7eb2e8f9f7 3580 /* Always wait for ENS to go high */
<> 144:ef7eb2e8f9f7 3581 while (!BUS_RegBitRead(&CMU->STATUS, ensBitPos))
<> 144:ef7eb2e8f9f7 3582 {
<> 144:ef7eb2e8f9f7 3583 }
<> 144:ef7eb2e8f9f7 3584 #endif
<> 144:ef7eb2e8f9f7 3585
<> 144:ef7eb2e8f9f7 3586 /* Wait for clock to become ready after enable */
<> 144:ef7eb2e8f9f7 3587 if (wait)
<> 144:ef7eb2e8f9f7 3588 {
<> 144:ef7eb2e8f9f7 3589 while (!BUS_RegBitRead(&CMU->STATUS, rdyBitPos));
<> 144:ef7eb2e8f9f7 3590 #if defined( _CMU_STATUS_HFXOSHUNTOPTRDY_MASK )
<> 150:02e0a0aed4ec 3591 if ((osc == cmuOsc_HFXO) && firstHfxoEnable)
<> 144:ef7eb2e8f9f7 3592 {
<> 150:02e0a0aed4ec 3593 if ((CMU->HFXOCTRL & _CMU_HFXOCTRL_MODE_MASK) == CMU_HFXOCTRL_MODE_EXTCLK)
<> 144:ef7eb2e8f9f7 3594 {
<> 150:02e0a0aed4ec 3595 /* External clock mode should only do shunt current optimization. */
<> 150:02e0a0aed4ec 3596 CMU_OscillatorTuningOptimize(cmuOsc_HFXO, cmuHFXOTuningMode_ShuntCommand, true);
<> 150:02e0a0aed4ec 3597 }
<> 150:02e0a0aed4ec 3598 else
<> 150:02e0a0aed4ec 3599 {
<> 150:02e0a0aed4ec 3600 /* Wait for peak detection and shunt current optimization to complete. */
<> 150:02e0a0aed4ec 3601 CMU_OscillatorTuningWait(cmuOsc_HFXO, cmuHFXOTuningMode_Auto);
<> 144:ef7eb2e8f9f7 3602 }
<> 150:02e0a0aed4ec 3603
<> 150:02e0a0aed4ec 3604 /* Disable the HFXO again to apply the trims. Apply trim from HFXOTRIMSTATUS
<> 150:02e0a0aed4ec 3605 when disabled. */
<> 150:02e0a0aed4ec 3606 hfxoTrimStatus = CMU_OscillatorTuningGet(cmuOsc_HFXO);
<> 150:02e0a0aed4ec 3607 CMU_OscillatorEnable(cmuOsc_HFXO, false, true);
<> 150:02e0a0aed4ec 3608 CMU_OscillatorTuningSet(cmuOsc_HFXO, hfxoTrimStatus);
<> 150:02e0a0aed4ec 3609
<> 150:02e0a0aed4ec 3610 /* Restart in CMD mode. */
<> 150:02e0a0aed4ec 3611 CMU->OSCENCMD = enBit;
<> 150:02e0a0aed4ec 3612 while (!BUS_RegBitRead(&CMU->STATUS, rdyBitPos));
<> 144:ef7eb2e8f9f7 3613 }
<> 144:ef7eb2e8f9f7 3614 #endif
<> 144:ef7eb2e8f9f7 3615 }
<> 144:ef7eb2e8f9f7 3616 }
<> 144:ef7eb2e8f9f7 3617 else
<> 144:ef7eb2e8f9f7 3618 {
<> 144:ef7eb2e8f9f7 3619 CMU->OSCENCMD = disBit;
<> 144:ef7eb2e8f9f7 3620
<> 144:ef7eb2e8f9f7 3621 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
<> 144:ef7eb2e8f9f7 3622 /* Always wait for ENS to go low */
<> 144:ef7eb2e8f9f7 3623 while (BUS_RegBitRead(&CMU->STATUS, ensBitPos))
<> 144:ef7eb2e8f9f7 3624 {
<> 144:ef7eb2e8f9f7 3625 }
<> 144:ef7eb2e8f9f7 3626 #endif
<> 144:ef7eb2e8f9f7 3627 }
<> 144:ef7eb2e8f9f7 3628
<> 144:ef7eb2e8f9f7 3629 /* Keep EMU module informed */
<> 144:ef7eb2e8f9f7 3630 EMU_UpdateOscConfig();
<> 144:ef7eb2e8f9f7 3631 }
<> 144:ef7eb2e8f9f7 3632
<> 144:ef7eb2e8f9f7 3633
<> 144:ef7eb2e8f9f7 3634 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 3635 * @brief
<> 144:ef7eb2e8f9f7 3636 * Get oscillator frequency tuning setting.
<> 144:ef7eb2e8f9f7 3637 *
<> 144:ef7eb2e8f9f7 3638 * @param[in] osc
<> 144:ef7eb2e8f9f7 3639 * Oscillator to get tuning value for, one of:
<> 144:ef7eb2e8f9f7 3640 * @li #cmuOsc_LFRCO
<> 144:ef7eb2e8f9f7 3641 * @li #cmuOsc_HFRCO
<> 144:ef7eb2e8f9f7 3642 * @li #cmuOsc_AUXHFRCO
<> 150:02e0a0aed4ec 3643 * @li #cmuOsc_HFXO if CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE is defined
<> 144:ef7eb2e8f9f7 3644 *
<> 144:ef7eb2e8f9f7 3645 * @return
<> 144:ef7eb2e8f9f7 3646 * The oscillator frequency tuning setting in use.
<> 144:ef7eb2e8f9f7 3647 ******************************************************************************/
<> 144:ef7eb2e8f9f7 3648 uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc)
<> 144:ef7eb2e8f9f7 3649 {
<> 144:ef7eb2e8f9f7 3650 uint32_t ret;
<> 144:ef7eb2e8f9f7 3651
<> 144:ef7eb2e8f9f7 3652 switch (osc)
<> 144:ef7eb2e8f9f7 3653 {
<> 144:ef7eb2e8f9f7 3654 case cmuOsc_LFRCO:
<> 144:ef7eb2e8f9f7 3655 ret = (CMU->LFRCOCTRL & _CMU_LFRCOCTRL_TUNING_MASK)
<> 144:ef7eb2e8f9f7 3656 >> _CMU_LFRCOCTRL_TUNING_SHIFT;
<> 144:ef7eb2e8f9f7 3657 break;
<> 144:ef7eb2e8f9f7 3658
<> 144:ef7eb2e8f9f7 3659 case cmuOsc_HFRCO:
<> 144:ef7eb2e8f9f7 3660 ret = (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_TUNING_MASK)
<> 144:ef7eb2e8f9f7 3661 >> _CMU_HFRCOCTRL_TUNING_SHIFT;
<> 144:ef7eb2e8f9f7 3662 break;
<> 144:ef7eb2e8f9f7 3663
<> 144:ef7eb2e8f9f7 3664 case cmuOsc_AUXHFRCO:
<> 144:ef7eb2e8f9f7 3665 ret = (CMU->AUXHFRCOCTRL & _CMU_AUXHFRCOCTRL_TUNING_MASK)
<> 144:ef7eb2e8f9f7 3666 >> _CMU_AUXHFRCOCTRL_TUNING_SHIFT;
<> 144:ef7eb2e8f9f7 3667 break;
<> 144:ef7eb2e8f9f7 3668
<> 150:02e0a0aed4ec 3669 #if defined( _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK )
<> 150:02e0a0aed4ec 3670 case cmuOsc_HFXO:
<> 150:02e0a0aed4ec 3671 ret = CMU->HFXOTRIMSTATUS & ( _CMU_HFXOTRIMSTATUS_REGISH_MASK
<> 150:02e0a0aed4ec 3672 | _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK);
<> 150:02e0a0aed4ec 3673 break;
<> 150:02e0a0aed4ec 3674 #endif
<> 150:02e0a0aed4ec 3675
<> 144:ef7eb2e8f9f7 3676 default:
<> 144:ef7eb2e8f9f7 3677 EFM_ASSERT(0);
<> 144:ef7eb2e8f9f7 3678 ret = 0;
<> 144:ef7eb2e8f9f7 3679 break;
<> 144:ef7eb2e8f9f7 3680 }
<> 144:ef7eb2e8f9f7 3681
<> 144:ef7eb2e8f9f7 3682 return ret;
<> 144:ef7eb2e8f9f7 3683 }
<> 144:ef7eb2e8f9f7 3684
<> 144:ef7eb2e8f9f7 3685
<> 144:ef7eb2e8f9f7 3686 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 3687 * @brief
<> 144:ef7eb2e8f9f7 3688 * Set the oscillator frequency tuning control.
<> 144:ef7eb2e8f9f7 3689 *
<> 144:ef7eb2e8f9f7 3690 * @note
<> 144:ef7eb2e8f9f7 3691 * Oscillator tuning is done during production, and the tuning value is
<> 144:ef7eb2e8f9f7 3692 * automatically loaded after a reset. Changing the tuning value from the
<> 150:02e0a0aed4ec 3693 * calibrated value is for more advanced use. Certain oscillators also have
<> 150:02e0a0aed4ec 3694 * build-in tuning optimization.
<> 144:ef7eb2e8f9f7 3695 *
<> 144:ef7eb2e8f9f7 3696 * @param[in] osc
<> 144:ef7eb2e8f9f7 3697 * Oscillator to set tuning value for, one of:
<> 144:ef7eb2e8f9f7 3698 * @li #cmuOsc_LFRCO
<> 144:ef7eb2e8f9f7 3699 * @li #cmuOsc_HFRCO
<> 144:ef7eb2e8f9f7 3700 * @li #cmuOsc_AUXHFRCO
<> 150:02e0a0aed4ec 3701 * @li #cmuOsc_HFXO if PEAKDETSHUNTOPTMODE is available. Note that CMD mode is set.
<> 144:ef7eb2e8f9f7 3702 *
<> 144:ef7eb2e8f9f7 3703 * @param[in] val
<> 144:ef7eb2e8f9f7 3704 * The oscillator frequency tuning setting to use.
<> 144:ef7eb2e8f9f7 3705 ******************************************************************************/
<> 144:ef7eb2e8f9f7 3706 void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val)
<> 144:ef7eb2e8f9f7 3707 {
<> 150:02e0a0aed4ec 3708 #if defined( _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK )
<> 150:02e0a0aed4ec 3709 uint32_t regIshUpper;
<> 150:02e0a0aed4ec 3710 #endif
<> 150:02e0a0aed4ec 3711
<> 144:ef7eb2e8f9f7 3712 switch (osc)
<> 144:ef7eb2e8f9f7 3713 {
<> 144:ef7eb2e8f9f7 3714 case cmuOsc_LFRCO:
<> 144:ef7eb2e8f9f7 3715 EFM_ASSERT(val <= (_CMU_LFRCOCTRL_TUNING_MASK
<> 144:ef7eb2e8f9f7 3716 >> _CMU_LFRCOCTRL_TUNING_SHIFT));
<> 144:ef7eb2e8f9f7 3717 val &= (_CMU_LFRCOCTRL_TUNING_MASK >> _CMU_LFRCOCTRL_TUNING_SHIFT);
<> 144:ef7eb2e8f9f7 3718 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
<> 144:ef7eb2e8f9f7 3719 while(BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_LFRCOBSY_SHIFT));
<> 144:ef7eb2e8f9f7 3720 #endif
<> 144:ef7eb2e8f9f7 3721 CMU->LFRCOCTRL = (CMU->LFRCOCTRL & ~(_CMU_LFRCOCTRL_TUNING_MASK))
<> 144:ef7eb2e8f9f7 3722 | (val << _CMU_LFRCOCTRL_TUNING_SHIFT);
<> 144:ef7eb2e8f9f7 3723 break;
<> 144:ef7eb2e8f9f7 3724
<> 144:ef7eb2e8f9f7 3725 case cmuOsc_HFRCO:
<> 144:ef7eb2e8f9f7 3726 EFM_ASSERT(val <= (_CMU_HFRCOCTRL_TUNING_MASK
<> 144:ef7eb2e8f9f7 3727 >> _CMU_HFRCOCTRL_TUNING_SHIFT));
<> 144:ef7eb2e8f9f7 3728 val &= (_CMU_HFRCOCTRL_TUNING_MASK >> _CMU_HFRCOCTRL_TUNING_SHIFT);
<> 144:ef7eb2e8f9f7 3729 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
<> 144:ef7eb2e8f9f7 3730 while(BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_HFRCOBSY_SHIFT))
<> 144:ef7eb2e8f9f7 3731 {
<> 144:ef7eb2e8f9f7 3732 }
<> 144:ef7eb2e8f9f7 3733 #endif
<> 144:ef7eb2e8f9f7 3734 CMU->HFRCOCTRL = (CMU->HFRCOCTRL & ~(_CMU_HFRCOCTRL_TUNING_MASK))
<> 144:ef7eb2e8f9f7 3735 | (val << _CMU_HFRCOCTRL_TUNING_SHIFT);
<> 144:ef7eb2e8f9f7 3736 break;
<> 144:ef7eb2e8f9f7 3737
<> 144:ef7eb2e8f9f7 3738 case cmuOsc_AUXHFRCO:
<> 144:ef7eb2e8f9f7 3739 EFM_ASSERT(val <= (_CMU_AUXHFRCOCTRL_TUNING_MASK
<> 144:ef7eb2e8f9f7 3740 >> _CMU_AUXHFRCOCTRL_TUNING_SHIFT));
<> 144:ef7eb2e8f9f7 3741 val &= (_CMU_AUXHFRCOCTRL_TUNING_MASK >> _CMU_AUXHFRCOCTRL_TUNING_SHIFT);
<> 144:ef7eb2e8f9f7 3742 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
<> 144:ef7eb2e8f9f7 3743 while(BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT))
<> 144:ef7eb2e8f9f7 3744 {
<> 144:ef7eb2e8f9f7 3745 }
<> 144:ef7eb2e8f9f7 3746 #endif
<> 144:ef7eb2e8f9f7 3747 CMU->AUXHFRCOCTRL = (CMU->AUXHFRCOCTRL & ~(_CMU_AUXHFRCOCTRL_TUNING_MASK))
<> 144:ef7eb2e8f9f7 3748 | (val << _CMU_AUXHFRCOCTRL_TUNING_SHIFT);
<> 144:ef7eb2e8f9f7 3749 break;
<> 144:ef7eb2e8f9f7 3750
<> 150:02e0a0aed4ec 3751 #if defined( _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK )
<> 150:02e0a0aed4ec 3752 case cmuOsc_HFXO:
<> 150:02e0a0aed4ec 3753
<> 150:02e0a0aed4ec 3754 /* Do set PEAKDETSHUNTOPTMODE or HFXOSTEADYSTATECTRL if HFXO is enabled */
<> 150:02e0a0aed4ec 3755 EFM_ASSERT(!(CMU->STATUS & CMU_STATUS_HFXOENS));
<> 150:02e0a0aed4ec 3756
<> 150:02e0a0aed4ec 3757 /* Switch to command mode. Automatic SCO and PDA calibration is not done
<> 150:02e0a0aed4ec 3758 at the next enable. Set user REGISH, REGISHUPPER and IBTRIMXOCORE. */
<> 150:02e0a0aed4ec 3759 CMU->HFXOCTRL = (CMU->HFXOCTRL & ~_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK)
<> 150:02e0a0aed4ec 3760 | CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD;
<> 150:02e0a0aed4ec 3761
<> 150:02e0a0aed4ec 3762 regIshUpper = getRegIshUpperVal((val & _CMU_HFXOSTEADYSTATECTRL_REGISH_MASK)
<> 150:02e0a0aed4ec 3763 >> _CMU_HFXOSTEADYSTATECTRL_REGISH_SHIFT);
<> 150:02e0a0aed4ec 3764
<> 150:02e0a0aed4ec 3765 BUS_RegMaskedWrite(&CMU->HFXOSTEADYSTATECTRL,
<> 150:02e0a0aed4ec 3766 _CMU_HFXOSTEADYSTATECTRL_REGISH_MASK
<> 150:02e0a0aed4ec 3767 | _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK
<> 150:02e0a0aed4ec 3768 | _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK,
<> 150:02e0a0aed4ec 3769 val | regIshUpper);
<> 150:02e0a0aed4ec 3770 break;
<> 150:02e0a0aed4ec 3771 #endif
<> 150:02e0a0aed4ec 3772
<> 144:ef7eb2e8f9f7 3773 default:
<> 144:ef7eb2e8f9f7 3774 EFM_ASSERT(0);
<> 144:ef7eb2e8f9f7 3775 break;
<> 144:ef7eb2e8f9f7 3776 }
<> 144:ef7eb2e8f9f7 3777 }
<> 144:ef7eb2e8f9f7 3778
<> 150:02e0a0aed4ec 3779 #if defined( _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK )
<> 150:02e0a0aed4ec 3780 /***************************************************************************//**
<> 150:02e0a0aed4ec 3781 * @brief
<> 150:02e0a0aed4ec 3782 * Wait for oscillator tuning optimization.
<> 150:02e0a0aed4ec 3783 *
<> 150:02e0a0aed4ec 3784 * @param[in] osc
<> 150:02e0a0aed4ec 3785 * Oscillator to set tuning value for, one of:
<> 150:02e0a0aed4ec 3786 * @li #cmuOsc_HFXO
<> 150:02e0a0aed4ec 3787 *
<> 150:02e0a0aed4ec 3788 * @param[in] mode
<> 150:02e0a0aed4ec 3789 * Tuning optimization mode.
<> 150:02e0a0aed4ec 3790 *
<> 150:02e0a0aed4ec 3791 * @return
<> 150:02e0a0aed4ec 3792 * Returns false on invalid parameters or oscillator error status.
<> 150:02e0a0aed4ec 3793 ******************************************************************************/
<> 150:02e0a0aed4ec 3794 bool CMU_OscillatorTuningWait(CMU_Osc_TypeDef osc,
<> 150:02e0a0aed4ec 3795 CMU_HFXOTuningMode_TypeDef mode)
<> 150:02e0a0aed4ec 3796 {
<> 150:02e0a0aed4ec 3797 EFM_ASSERT(osc == cmuOsc_HFXO);
<> 150:02e0a0aed4ec 3798 uint32_t waitFlags;
<> 150:02e0a0aed4ec 3799
<> 150:02e0a0aed4ec 3800 /* Currently implemented for HFXO with PEAKDETSHUNTOPTMODE only */
<> 150:02e0a0aed4ec 3801 (void)osc;
<> 150:02e0a0aed4ec 3802
<> 150:02e0a0aed4ec 3803 if (BUS_RegMaskedRead(&CMU->HFXOCTRL, _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK)
<> 150:02e0a0aed4ec 3804 == CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD)
<> 150:02e0a0aed4ec 3805 {
<> 150:02e0a0aed4ec 3806 waitFlags = CMU_STATUS_HFXOSHUNTOPTRDY | CMU_STATUS_HFXOPEAKDETRDY;
<> 150:02e0a0aed4ec 3807 }
<> 150:02e0a0aed4ec 3808 else
<> 150:02e0a0aed4ec 3809 {
<> 150:02e0a0aed4ec 3810 /* Set wait flags for each command and wait */
<> 150:02e0a0aed4ec 3811 switch (mode)
<> 150:02e0a0aed4ec 3812 {
<> 150:02e0a0aed4ec 3813 case cmuHFXOTuningMode_ShuntCommand:
<> 150:02e0a0aed4ec 3814 waitFlags = CMU_STATUS_HFXOSHUNTOPTRDY;
<> 150:02e0a0aed4ec 3815 break;
<> 150:02e0a0aed4ec 3816
<> 150:02e0a0aed4ec 3817 case cmuHFXOTuningMode_Auto:
<> 150:02e0a0aed4ec 3818 /* Fall through */
<> 150:02e0a0aed4ec 3819 case cmuHFXOTuningMode_PeakShuntCommand:
<> 150:02e0a0aed4ec 3820 waitFlags = CMU_STATUS_HFXOSHUNTOPTRDY | CMU_STATUS_HFXOPEAKDETRDY;
<> 150:02e0a0aed4ec 3821 break;
<> 150:02e0a0aed4ec 3822
<> 150:02e0a0aed4ec 3823 default:
<> 150:02e0a0aed4ec 3824 waitFlags = _CMU_STATUS_MASK;
<> 150:02e0a0aed4ec 3825 EFM_ASSERT(false);
<> 150:02e0a0aed4ec 3826 }
<> 150:02e0a0aed4ec 3827 }
<> 150:02e0a0aed4ec 3828 while ((CMU->STATUS & waitFlags) != waitFlags);
<> 150:02e0a0aed4ec 3829
<> 150:02e0a0aed4ec 3830 /* Check error flags */
<> 150:02e0a0aed4ec 3831 if (waitFlags & CMU_STATUS_HFXOPEAKDETRDY)
<> 150:02e0a0aed4ec 3832 {
<> 150:02e0a0aed4ec 3833 return (CMU->IF & CMU_IF_HFXOPEAKDETERR ? true : false);
<> 150:02e0a0aed4ec 3834 }
<> 150:02e0a0aed4ec 3835 return true;
<> 150:02e0a0aed4ec 3836 }
<> 150:02e0a0aed4ec 3837
<> 150:02e0a0aed4ec 3838
<> 150:02e0a0aed4ec 3839 /***************************************************************************//**
<> 150:02e0a0aed4ec 3840 * @brief
<> 150:02e0a0aed4ec 3841 * Start and optionally wait for oscillator tuning optimization.
<> 150:02e0a0aed4ec 3842 *
<> 150:02e0a0aed4ec 3843 * @param[in] osc
<> 150:02e0a0aed4ec 3844 * Oscillator to set tuning value for, one of:
<> 150:02e0a0aed4ec 3845 * @li #cmuOsc_HFXO
<> 150:02e0a0aed4ec 3846 *
<> 150:02e0a0aed4ec 3847 * @param[in] mode
<> 150:02e0a0aed4ec 3848 * Tuning optimization mode.
<> 150:02e0a0aed4ec 3849 *
<> 150:02e0a0aed4ec 3850 * @param[in] wait
<> 150:02e0a0aed4ec 3851 * Wait for tuning optimization to complete.
<> 150:02e0a0aed4ec 3852 * true - wait for tuning optimization to complete.
<> 150:02e0a0aed4ec 3853 * false - return without waiting.
<> 150:02e0a0aed4ec 3854 *
<> 150:02e0a0aed4ec 3855 * @return
<> 150:02e0a0aed4ec 3856 * Returns false on invalid parameters or oscillator error status.
<> 150:02e0a0aed4ec 3857 ******************************************************************************/
<> 150:02e0a0aed4ec 3858 bool CMU_OscillatorTuningOptimize(CMU_Osc_TypeDef osc,
<> 150:02e0a0aed4ec 3859 CMU_HFXOTuningMode_TypeDef mode,
<> 150:02e0a0aed4ec 3860 bool wait)
<> 150:02e0a0aed4ec 3861 {
<> 150:02e0a0aed4ec 3862 switch (osc)
<> 150:02e0a0aed4ec 3863 {
<> 150:02e0a0aed4ec 3864 case cmuOsc_HFXO:
<> 150:02e0a0aed4ec 3865 if (mode)
<> 150:02e0a0aed4ec 3866 {
<> 150:02e0a0aed4ec 3867 /* Clear error flag before command write */
<> 150:02e0a0aed4ec 3868 CMU->IFC = CMU_IFC_HFXOPEAKDETERR;
<> 150:02e0a0aed4ec 3869 CMU->CMD = mode;
<> 150:02e0a0aed4ec 3870 }
<> 150:02e0a0aed4ec 3871 if (wait)
<> 150:02e0a0aed4ec 3872 {
<> 150:02e0a0aed4ec 3873 return CMU_OscillatorTuningWait(osc, mode);
<> 150:02e0a0aed4ec 3874 }
<> 150:02e0a0aed4ec 3875
<> 150:02e0a0aed4ec 3876 default:
<> 150:02e0a0aed4ec 3877 EFM_ASSERT(false);
<> 150:02e0a0aed4ec 3878 }
<> 150:02e0a0aed4ec 3879 return true;
<> 150:02e0a0aed4ec 3880 }
<> 150:02e0a0aed4ec 3881 #endif
<> 150:02e0a0aed4ec 3882
<> 144:ef7eb2e8f9f7 3883
<> 144:ef7eb2e8f9f7 3884 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 3885 * @brief
<> 144:ef7eb2e8f9f7 3886 * Determine if currently selected PCNTn clock used is external or LFBCLK.
<> 144:ef7eb2e8f9f7 3887 *
<> 144:ef7eb2e8f9f7 3888 * @param[in] instance
<> 144:ef7eb2e8f9f7 3889 * PCNT instance number to get currently selected clock source for.
<> 144:ef7eb2e8f9f7 3890 *
<> 144:ef7eb2e8f9f7 3891 * @return
<> 144:ef7eb2e8f9f7 3892 * @li true - selected clock is external clock.
<> 144:ef7eb2e8f9f7 3893 * @li false - selected clock is LFBCLK.
<> 144:ef7eb2e8f9f7 3894 *****************************************************************************/
<> 144:ef7eb2e8f9f7 3895 bool CMU_PCNTClockExternalGet(unsigned int instance)
<> 144:ef7eb2e8f9f7 3896 {
<> 144:ef7eb2e8f9f7 3897 uint32_t setting;
<> 144:ef7eb2e8f9f7 3898
<> 144:ef7eb2e8f9f7 3899 switch (instance)
<> 144:ef7eb2e8f9f7 3900 {
<> 144:ef7eb2e8f9f7 3901 #if defined( _CMU_PCNTCTRL_PCNT0CLKEN_MASK )
<> 144:ef7eb2e8f9f7 3902 case 0:
<> 144:ef7eb2e8f9f7 3903 setting = CMU->PCNTCTRL & CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0;
<> 144:ef7eb2e8f9f7 3904 break;
<> 144:ef7eb2e8f9f7 3905
<> 144:ef7eb2e8f9f7 3906 #if defined( _CMU_PCNTCTRL_PCNT1CLKEN_MASK )
<> 144:ef7eb2e8f9f7 3907 case 1:
<> 144:ef7eb2e8f9f7 3908 setting = CMU->PCNTCTRL & CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0;
<> 144:ef7eb2e8f9f7 3909 break;
<> 144:ef7eb2e8f9f7 3910
<> 144:ef7eb2e8f9f7 3911 #if defined( _CMU_PCNTCTRL_PCNT2CLKEN_MASK )
<> 144:ef7eb2e8f9f7 3912 case 2:
<> 144:ef7eb2e8f9f7 3913 setting = CMU->PCNTCTRL & CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0;
<> 144:ef7eb2e8f9f7 3914 break;
<> 144:ef7eb2e8f9f7 3915 #endif
<> 144:ef7eb2e8f9f7 3916 #endif
<> 144:ef7eb2e8f9f7 3917 #endif
<> 144:ef7eb2e8f9f7 3918
<> 144:ef7eb2e8f9f7 3919 default:
<> 144:ef7eb2e8f9f7 3920 setting = 0;
<> 144:ef7eb2e8f9f7 3921 break;
<> 144:ef7eb2e8f9f7 3922 }
<> 144:ef7eb2e8f9f7 3923 return (setting ? true : false);
<> 144:ef7eb2e8f9f7 3924 }
<> 144:ef7eb2e8f9f7 3925
<> 144:ef7eb2e8f9f7 3926
<> 144:ef7eb2e8f9f7 3927 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 3928 * @brief
<> 144:ef7eb2e8f9f7 3929 * Select PCNTn clock.
<> 144:ef7eb2e8f9f7 3930 *
<> 144:ef7eb2e8f9f7 3931 * @param[in] instance
<> 144:ef7eb2e8f9f7 3932 * PCNT instance number to set selected clock source for.
<> 144:ef7eb2e8f9f7 3933 *
<> 144:ef7eb2e8f9f7 3934 * @param[in] external
<> 144:ef7eb2e8f9f7 3935 * Set to true to select external clock, false to select LFBCLK.
<> 144:ef7eb2e8f9f7 3936 *****************************************************************************/
<> 144:ef7eb2e8f9f7 3937 void CMU_PCNTClockExternalSet(unsigned int instance, bool external)
<> 144:ef7eb2e8f9f7 3938 {
<> 144:ef7eb2e8f9f7 3939 #if defined( PCNT_PRESENT )
<> 144:ef7eb2e8f9f7 3940 uint32_t setting = 0;
<> 144:ef7eb2e8f9f7 3941
<> 144:ef7eb2e8f9f7 3942 EFM_ASSERT(instance < PCNT_COUNT);
<> 144:ef7eb2e8f9f7 3943
<> 144:ef7eb2e8f9f7 3944 if (external)
<> 144:ef7eb2e8f9f7 3945 {
<> 144:ef7eb2e8f9f7 3946 setting = 1;
<> 144:ef7eb2e8f9f7 3947 }
<> 144:ef7eb2e8f9f7 3948
<> 144:ef7eb2e8f9f7 3949 BUS_RegBitWrite(&(CMU->PCNTCTRL), (instance * 2) + 1, setting);
<> 144:ef7eb2e8f9f7 3950
<> 144:ef7eb2e8f9f7 3951 #else
<> 144:ef7eb2e8f9f7 3952 (void)instance; /* Unused parameter */
<> 144:ef7eb2e8f9f7 3953 (void)external; /* Unused parameter */
<> 144:ef7eb2e8f9f7 3954 #endif
<> 144:ef7eb2e8f9f7 3955 }
<> 144:ef7eb2e8f9f7 3956
<> 144:ef7eb2e8f9f7 3957
<> 144:ef7eb2e8f9f7 3958 #if defined( _CMU_USHFRCOCONF_BAND_MASK )
<> 144:ef7eb2e8f9f7 3959 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 3960 * @brief
<> 144:ef7eb2e8f9f7 3961 * Get USHFRCO band in use.
<> 144:ef7eb2e8f9f7 3962 *
<> 144:ef7eb2e8f9f7 3963 * @return
<> 144:ef7eb2e8f9f7 3964 * USHFRCO band in use.
<> 144:ef7eb2e8f9f7 3965 ******************************************************************************/
<> 144:ef7eb2e8f9f7 3966 CMU_USHFRCOBand_TypeDef CMU_USHFRCOBandGet(void)
<> 144:ef7eb2e8f9f7 3967 {
<> 144:ef7eb2e8f9f7 3968 return (CMU_USHFRCOBand_TypeDef)((CMU->USHFRCOCONF
<> 144:ef7eb2e8f9f7 3969 & _CMU_USHFRCOCONF_BAND_MASK)
<> 144:ef7eb2e8f9f7 3970 >> _CMU_USHFRCOCONF_BAND_SHIFT);
<> 144:ef7eb2e8f9f7 3971 }
<> 144:ef7eb2e8f9f7 3972 #endif
<> 144:ef7eb2e8f9f7 3973
<> 144:ef7eb2e8f9f7 3974 #if defined( _CMU_USHFRCOCONF_BAND_MASK )
<> 144:ef7eb2e8f9f7 3975 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 3976 * @brief
<> 144:ef7eb2e8f9f7 3977 * Set USHFRCO band to use.
<> 144:ef7eb2e8f9f7 3978 *
<> 144:ef7eb2e8f9f7 3979 * @param[in] band
<> 144:ef7eb2e8f9f7 3980 * USHFRCO band to activate.
<> 144:ef7eb2e8f9f7 3981 ******************************************************************************/
<> 144:ef7eb2e8f9f7 3982 void CMU_USHFRCOBandSet(CMU_USHFRCOBand_TypeDef band)
<> 144:ef7eb2e8f9f7 3983 {
<> 144:ef7eb2e8f9f7 3984 uint32_t tuning;
<> 144:ef7eb2e8f9f7 3985 uint32_t fineTuning;
<> 144:ef7eb2e8f9f7 3986 CMU_Select_TypeDef osc;
<> 144:ef7eb2e8f9f7 3987
<> 144:ef7eb2e8f9f7 3988 /* Cannot switch band if USHFRCO is already selected as HF clock. */
<> 144:ef7eb2e8f9f7 3989 osc = CMU_ClockSelectGet(cmuClock_HF);
<> 144:ef7eb2e8f9f7 3990 EFM_ASSERT((CMU_USHFRCOBandGet() != band) && (osc != cmuSelect_USHFRCO));
<> 144:ef7eb2e8f9f7 3991
<> 144:ef7eb2e8f9f7 3992 /* Read tuning value from calibration table */
<> 144:ef7eb2e8f9f7 3993 switch (band)
<> 144:ef7eb2e8f9f7 3994 {
<> 144:ef7eb2e8f9f7 3995 case cmuUSHFRCOBand_24MHz:
<> 144:ef7eb2e8f9f7 3996 tuning = (DEVINFO->USHFRCOCAL0 & _DEVINFO_USHFRCOCAL0_BAND24_TUNING_MASK)
<> 144:ef7eb2e8f9f7 3997 >> _DEVINFO_USHFRCOCAL0_BAND24_TUNING_SHIFT;
<> 144:ef7eb2e8f9f7 3998 fineTuning = (DEVINFO->USHFRCOCAL0
<> 144:ef7eb2e8f9f7 3999 & _DEVINFO_USHFRCOCAL0_BAND24_FINETUNING_MASK)
<> 144:ef7eb2e8f9f7 4000 >> _DEVINFO_USHFRCOCAL0_BAND24_FINETUNING_SHIFT;
<> 144:ef7eb2e8f9f7 4001 break;
<> 144:ef7eb2e8f9f7 4002
<> 144:ef7eb2e8f9f7 4003 case cmuUSHFRCOBand_48MHz:
<> 144:ef7eb2e8f9f7 4004 tuning = (DEVINFO->USHFRCOCAL0 & _DEVINFO_USHFRCOCAL0_BAND48_TUNING_MASK)
<> 144:ef7eb2e8f9f7 4005 >> _DEVINFO_USHFRCOCAL0_BAND48_TUNING_SHIFT;
<> 144:ef7eb2e8f9f7 4006 fineTuning = (DEVINFO->USHFRCOCAL0
<> 144:ef7eb2e8f9f7 4007 & _DEVINFO_USHFRCOCAL0_BAND48_FINETUNING_MASK)
<> 144:ef7eb2e8f9f7 4008 >> _DEVINFO_USHFRCOCAL0_BAND48_FINETUNING_SHIFT;
<> 144:ef7eb2e8f9f7 4009 /* Enable the clock divider before switching the band from 24 to 48MHz */
<> 144:ef7eb2e8f9f7 4010 BUS_RegBitWrite(&CMU->USHFRCOCONF, _CMU_USHFRCOCONF_USHFRCODIV2DIS_SHIFT, 0);
<> 144:ef7eb2e8f9f7 4011 break;
<> 144:ef7eb2e8f9f7 4012
<> 144:ef7eb2e8f9f7 4013 default:
<> 144:ef7eb2e8f9f7 4014 EFM_ASSERT(0);
<> 144:ef7eb2e8f9f7 4015 return;
<> 144:ef7eb2e8f9f7 4016 }
<> 144:ef7eb2e8f9f7 4017
<> 144:ef7eb2e8f9f7 4018 /* Set band and tuning */
<> 144:ef7eb2e8f9f7 4019 CMU->USHFRCOCONF = (CMU->USHFRCOCONF & ~_CMU_USHFRCOCONF_BAND_MASK)
<> 144:ef7eb2e8f9f7 4020 | (band << _CMU_USHFRCOCONF_BAND_SHIFT);
<> 144:ef7eb2e8f9f7 4021 CMU->USHFRCOCTRL = (CMU->USHFRCOCTRL & ~_CMU_USHFRCOCTRL_TUNING_MASK)
<> 144:ef7eb2e8f9f7 4022 | (tuning << _CMU_USHFRCOCTRL_TUNING_SHIFT);
<> 144:ef7eb2e8f9f7 4023 CMU->USHFRCOTUNE = (CMU->USHFRCOTUNE & ~_CMU_USHFRCOTUNE_FINETUNING_MASK)
<> 144:ef7eb2e8f9f7 4024 | (fineTuning << _CMU_USHFRCOTUNE_FINETUNING_SHIFT);
<> 144:ef7eb2e8f9f7 4025
<> 144:ef7eb2e8f9f7 4026 /* Disable the clock divider after switching the band from 48 to 24MHz */
<> 144:ef7eb2e8f9f7 4027 if (band == cmuUSHFRCOBand_24MHz)
<> 144:ef7eb2e8f9f7 4028 {
<> 144:ef7eb2e8f9f7 4029 BUS_RegBitWrite(&CMU->USHFRCOCONF, _CMU_USHFRCOCONF_USHFRCODIV2DIS_SHIFT, 1);
<> 144:ef7eb2e8f9f7 4030 }
<> 144:ef7eb2e8f9f7 4031 }
<> 144:ef7eb2e8f9f7 4032 #endif
<> 144:ef7eb2e8f9f7 4033
<> 144:ef7eb2e8f9f7 4034
<> 144:ef7eb2e8f9f7 4035
<> 144:ef7eb2e8f9f7 4036 /** @} (end addtogroup CMU) */
<> 150:02e0a0aed4ec 4037 /** @} (end addtogroup emlib) */
<> 144:ef7eb2e8f9f7 4038 #endif /* __EM_CMU_H */