Fawwaz Nadzmy / mbed-STM

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc.h@83:a036322b8637, 2016-03-07 (annotated)

Committer:
mbed_official
Date:
Mon Mar 07 10:00:14 2016 +0000
Revision:
83:a036322b8637
Parent:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Synchronized with git revision ee20d03969aa5c570152f88e8f3d8a4739eed40b



Full URL: https://github.com/mbedmicro/mbed/commit/ee20d03969aa5c570152f88e8f3d8a4739eed40b/



[STM32F7] Update STM32F7Cube_FW version

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32f7xx_hal_rcc.h
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
mbed_official 83:a036322b8637 5 * @version V1.0.4
mbed_official 83:a036322b8637 6 * @date 09-December-2015
bogdanm 0:9b334a45a8ff 7 * @brief Header file of RCC HAL module.
bogdanm 0:9b334a45a8ff 8 ******************************************************************************
bogdanm 0:9b334a45a8ff 9 * @attention
bogdanm 0:9b334a45a8ff 10 *
bogdanm 0:9b334a45a8ff 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 12 *
bogdanm 0:9b334a45a8ff 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 14 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 16 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 19 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 21 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 22 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 23 *
bogdanm 0:9b334a45a8ff 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 34 *
bogdanm 0:9b334a45a8ff 35 ******************************************************************************
bogdanm 0:9b334a45a8ff 36 */
bogdanm 0:9b334a45a8ff 37
bogdanm 0:9b334a45a8ff 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 0:9b334a45a8ff 39 #ifndef __STM32F7xx_HAL_RCC_H
bogdanm 0:9b334a45a8ff 40 #define __STM32F7xx_HAL_RCC_H
bogdanm 0:9b334a45a8ff 41
bogdanm 0:9b334a45a8ff 42 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 43 extern "C" {
bogdanm 0:9b334a45a8ff 44 #endif
bogdanm 0:9b334a45a8ff 45
bogdanm 0:9b334a45a8ff 46 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 47 #include "stm32f7xx_hal_def.h"
bogdanm 0:9b334a45a8ff 48
bogdanm 0:9b334a45a8ff 49 /** @addtogroup STM32F7xx_HAL_Driver
bogdanm 0:9b334a45a8ff 50 * @{
bogdanm 0:9b334a45a8ff 51 */
bogdanm 0:9b334a45a8ff 52
bogdanm 0:9b334a45a8ff 53 /** @addtogroup RCC
bogdanm 0:9b334a45a8ff 54 * @{
bogdanm 0:9b334a45a8ff 55 */
bogdanm 0:9b334a45a8ff 56
bogdanm 0:9b334a45a8ff 57 /* Exported types ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 58
bogdanm 0:9b334a45a8ff 59 /** @defgroup RCC_Exported_Types RCC Exported Types
bogdanm 0:9b334a45a8ff 60 * @{
bogdanm 0:9b334a45a8ff 61 */
bogdanm 0:9b334a45a8ff 62
bogdanm 0:9b334a45a8ff 63 /**
bogdanm 0:9b334a45a8ff 64 * @brief RCC PLL configuration structure definition
bogdanm 0:9b334a45a8ff 65 */
bogdanm 0:9b334a45a8ff 66 typedef struct
bogdanm 0:9b334a45a8ff 67 {
bogdanm 0:9b334a45a8ff 68 uint32_t PLLState; /*!< The new state of the PLL.
bogdanm 0:9b334a45a8ff 69 This parameter can be a value of @ref RCC_PLL_Config */
bogdanm 0:9b334a45a8ff 70
bogdanm 0:9b334a45a8ff 71 uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
bogdanm 0:9b334a45a8ff 72 This parameter must be a value of @ref RCC_PLL_Clock_Source */
bogdanm 0:9b334a45a8ff 73
bogdanm 0:9b334a45a8ff 74 uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
bogdanm 0:9b334a45a8ff 75 This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
bogdanm 0:9b334a45a8ff 76
bogdanm 0:9b334a45a8ff 77 uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
mbed_official 83:a036322b8637 78 This parameter must be a number between Min_Data = 100 and Max_Data = 432 */
bogdanm 0:9b334a45a8ff 79
bogdanm 0:9b334a45a8ff 80 uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK).
bogdanm 0:9b334a45a8ff 81 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
bogdanm 0:9b334a45a8ff 82
bogdanm 0:9b334a45a8ff 83 uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDMMC and RNG clocks.
bogdanm 0:9b334a45a8ff 84 This parameter must be a number between Min_Data = 2 and Max_Data = 15 */
bogdanm 0:9b334a45a8ff 85
bogdanm 0:9b334a45a8ff 86 }RCC_PLLInitTypeDef;
bogdanm 0:9b334a45a8ff 87
bogdanm 0:9b334a45a8ff 88 /**
bogdanm 0:9b334a45a8ff 89 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
bogdanm 0:9b334a45a8ff 90 */
bogdanm 0:9b334a45a8ff 91 typedef struct
bogdanm 0:9b334a45a8ff 92 {
bogdanm 0:9b334a45a8ff 93 uint32_t OscillatorType; /*!< The oscillators to be configured.
bogdanm 0:9b334a45a8ff 94 This parameter can be a value of @ref RCC_Oscillator_Type */
bogdanm 0:9b334a45a8ff 95
bogdanm 0:9b334a45a8ff 96 uint32_t HSEState; /*!< The new state of the HSE.
bogdanm 0:9b334a45a8ff 97 This parameter can be a value of @ref RCC_HSE_Config */
bogdanm 0:9b334a45a8ff 98
bogdanm 0:9b334a45a8ff 99 uint32_t LSEState; /*!< The new state of the LSE.
bogdanm 0:9b334a45a8ff 100 This parameter can be a value of @ref RCC_LSE_Config */
bogdanm 0:9b334a45a8ff 101
bogdanm 0:9b334a45a8ff 102 uint32_t HSIState; /*!< The new state of the HSI.
bogdanm 0:9b334a45a8ff 103 This parameter can be a value of @ref RCC_HSI_Config */
bogdanm 0:9b334a45a8ff 104
bogdanm 0:9b334a45a8ff 105 uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
bogdanm 0:9b334a45a8ff 106 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
bogdanm 0:9b334a45a8ff 107
bogdanm 0:9b334a45a8ff 108 uint32_t LSIState; /*!< The new state of the LSI.
bogdanm 0:9b334a45a8ff 109 This parameter can be a value of @ref RCC_LSI_Config */
bogdanm 0:9b334a45a8ff 110
bogdanm 0:9b334a45a8ff 111 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
bogdanm 0:9b334a45a8ff 112
bogdanm 0:9b334a45a8ff 113 }RCC_OscInitTypeDef;
bogdanm 0:9b334a45a8ff 114
bogdanm 0:9b334a45a8ff 115 /**
bogdanm 0:9b334a45a8ff 116 * @brief RCC System, AHB and APB busses clock configuration structure definition
bogdanm 0:9b334a45a8ff 117 */
bogdanm 0:9b334a45a8ff 118 typedef struct
bogdanm 0:9b334a45a8ff 119 {
bogdanm 0:9b334a45a8ff 120 uint32_t ClockType; /*!< The clock to be configured.
bogdanm 0:9b334a45a8ff 121 This parameter can be a value of @ref RCC_System_Clock_Type */
bogdanm 0:9b334a45a8ff 122
bogdanm 0:9b334a45a8ff 123 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
bogdanm 0:9b334a45a8ff 124 This parameter can be a value of @ref RCC_System_Clock_Source */
bogdanm 0:9b334a45a8ff 125
bogdanm 0:9b334a45a8ff 126 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
bogdanm 0:9b334a45a8ff 127 This parameter can be a value of @ref RCC_AHB_Clock_Source */
bogdanm 0:9b334a45a8ff 128
bogdanm 0:9b334a45a8ff 129 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
bogdanm 0:9b334a45a8ff 130 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
bogdanm 0:9b334a45a8ff 131
bogdanm 0:9b334a45a8ff 132 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
bogdanm 0:9b334a45a8ff 133 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
bogdanm 0:9b334a45a8ff 134
bogdanm 0:9b334a45a8ff 135 }RCC_ClkInitTypeDef;
bogdanm 0:9b334a45a8ff 136
bogdanm 0:9b334a45a8ff 137 /**
bogdanm 0:9b334a45a8ff 138 * @}
bogdanm 0:9b334a45a8ff 139 */
bogdanm 0:9b334a45a8ff 140
bogdanm 0:9b334a45a8ff 141 /* Exported constants --------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 142 /** @defgroup RCC_Exported_Constants RCC Exported Constants
bogdanm 0:9b334a45a8ff 143 * @{
bogdanm 0:9b334a45a8ff 144 */
bogdanm 0:9b334a45a8ff 145
bogdanm 0:9b334a45a8ff 146 /** @defgroup RCC_Oscillator_Type Oscillator Type
bogdanm 0:9b334a45a8ff 147 * @{
bogdanm 0:9b334a45a8ff 148 */
bogdanm 0:9b334a45a8ff 149 #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 150 #define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 151 #define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 152 #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 153 #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 154 /**
bogdanm 0:9b334a45a8ff 155 * @}
bogdanm 0:9b334a45a8ff 156 */
bogdanm 0:9b334a45a8ff 157
bogdanm 0:9b334a45a8ff 158 /** @defgroup RCC_HSE_Config RCC HSE Config
bogdanm 0:9b334a45a8ff 159 * @{
bogdanm 0:9b334a45a8ff 160 */
bogdanm 0:9b334a45a8ff 161 #define RCC_HSE_OFF ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 162 #define RCC_HSE_ON RCC_CR_HSEON
bogdanm 0:9b334a45a8ff 163 #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))
bogdanm 0:9b334a45a8ff 164 /**
bogdanm 0:9b334a45a8ff 165 * @}
bogdanm 0:9b334a45a8ff 166 */
bogdanm 0:9b334a45a8ff 167
bogdanm 0:9b334a45a8ff 168 /** @defgroup RCC_LSE_Config RCC LSE Config
bogdanm 0:9b334a45a8ff 169 * @{
bogdanm 0:9b334a45a8ff 170 */
bogdanm 0:9b334a45a8ff 171 #define RCC_LSE_OFF ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 172 #define RCC_LSE_ON RCC_BDCR_LSEON
bogdanm 0:9b334a45a8ff 173 #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
bogdanm 0:9b334a45a8ff 174 /**
bogdanm 0:9b334a45a8ff 175 * @}
bogdanm 0:9b334a45a8ff 176 */
bogdanm 0:9b334a45a8ff 177
bogdanm 0:9b334a45a8ff 178 /** @defgroup RCC_HSI_Config RCC HSI Config
bogdanm 0:9b334a45a8ff 179 * @{
bogdanm 0:9b334a45a8ff 180 */
bogdanm 0:9b334a45a8ff 181 #define RCC_HSI_OFF ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 182 #define RCC_HSI_ON RCC_CR_HSION
bogdanm 0:9b334a45a8ff 183 /**
bogdanm 0:9b334a45a8ff 184 * @}
bogdanm 0:9b334a45a8ff 185 */
bogdanm 0:9b334a45a8ff 186
bogdanm 0:9b334a45a8ff 187 /** @defgroup RCC_LSI_Config RCC LSI Config
bogdanm 0:9b334a45a8ff 188 * @{
bogdanm 0:9b334a45a8ff 189 */
bogdanm 0:9b334a45a8ff 190 #define RCC_LSI_OFF ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 191 #define RCC_LSI_ON RCC_CSR_LSION
bogdanm 0:9b334a45a8ff 192 /**
bogdanm 0:9b334a45a8ff 193 * @}
bogdanm 0:9b334a45a8ff 194 */
bogdanm 0:9b334a45a8ff 195
bogdanm 0:9b334a45a8ff 196 /** @defgroup RCC_PLL_Config RCC PLL Config
bogdanm 0:9b334a45a8ff 197 * @{
bogdanm 0:9b334a45a8ff 198 */
bogdanm 0:9b334a45a8ff 199 #define RCC_PLL_NONE ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 200 #define RCC_PLL_OFF ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 201 #define RCC_PLL_ON ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 202 /**
bogdanm 0:9b334a45a8ff 203 * @}
bogdanm 0:9b334a45a8ff 204 */
bogdanm 0:9b334a45a8ff 205
bogdanm 0:9b334a45a8ff 206 /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
bogdanm 0:9b334a45a8ff 207 * @{
bogdanm 0:9b334a45a8ff 208 */
bogdanm 0:9b334a45a8ff 209 #define RCC_PLLP_DIV2 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 210 #define RCC_PLLP_DIV4 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 211 #define RCC_PLLP_DIV6 ((uint32_t)0x00000006)
bogdanm 0:9b334a45a8ff 212 #define RCC_PLLP_DIV8 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 213 /**
bogdanm 0:9b334a45a8ff 214 * @}
bogdanm 0:9b334a45a8ff 215 */
bogdanm 0:9b334a45a8ff 216
bogdanm 0:9b334a45a8ff 217 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source
bogdanm 0:9b334a45a8ff 218 * @{
bogdanm 0:9b334a45a8ff 219 */
bogdanm 0:9b334a45a8ff 220 #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
bogdanm 0:9b334a45a8ff 221 #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
bogdanm 0:9b334a45a8ff 222 /**
bogdanm 0:9b334a45a8ff 223 * @}
bogdanm 0:9b334a45a8ff 224 */
bogdanm 0:9b334a45a8ff 225
bogdanm 0:9b334a45a8ff 226 /** @defgroup RCC_System_Clock_Type RCC System Clock Type
bogdanm 0:9b334a45a8ff 227 * @{
bogdanm 0:9b334a45a8ff 228 */
bogdanm 0:9b334a45a8ff 229 #define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 230 #define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 231 #define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 232 #define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 233 /**
bogdanm 0:9b334a45a8ff 234 * @}
bogdanm 0:9b334a45a8ff 235 */
bogdanm 0:9b334a45a8ff 236
bogdanm 0:9b334a45a8ff 237 /** @defgroup RCC_System_Clock_Source RCC System Clock Source
bogdanm 0:9b334a45a8ff 238 * @{
bogdanm 0:9b334a45a8ff 239 */
bogdanm 0:9b334a45a8ff 240 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
bogdanm 0:9b334a45a8ff 241 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
bogdanm 0:9b334a45a8ff 242 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
bogdanm 0:9b334a45a8ff 243 /**
bogdanm 0:9b334a45a8ff 244 * @}
bogdanm 0:9b334a45a8ff 245 */
bogdanm 0:9b334a45a8ff 246
bogdanm 0:9b334a45a8ff 247
bogdanm 0:9b334a45a8ff 248 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
bogdanm 0:9b334a45a8ff 249 * @{
bogdanm 0:9b334a45a8ff 250 */
bogdanm 0:9b334a45a8ff 251 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
bogdanm 0:9b334a45a8ff 252 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
bogdanm 0:9b334a45a8ff 253 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
bogdanm 0:9b334a45a8ff 254 /**
bogdanm 0:9b334a45a8ff 255 * @}
bogdanm 0:9b334a45a8ff 256 */
bogdanm 0:9b334a45a8ff 257
bogdanm 0:9b334a45a8ff 258 /** @defgroup RCC_AHB_Clock_Source RCC AHB Clock Source
bogdanm 0:9b334a45a8ff 259 * @{
bogdanm 0:9b334a45a8ff 260 */
bogdanm 0:9b334a45a8ff 261 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
bogdanm 0:9b334a45a8ff 262 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
bogdanm 0:9b334a45a8ff 263 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
bogdanm 0:9b334a45a8ff 264 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
bogdanm 0:9b334a45a8ff 265 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
bogdanm 0:9b334a45a8ff 266 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
bogdanm 0:9b334a45a8ff 267 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
bogdanm 0:9b334a45a8ff 268 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
bogdanm 0:9b334a45a8ff 269 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
bogdanm 0:9b334a45a8ff 270 /**
bogdanm 0:9b334a45a8ff 271 * @}
bogdanm 0:9b334a45a8ff 272 */
bogdanm 0:9b334a45a8ff 273
bogdanm 0:9b334a45a8ff 274 /** @defgroup RCC_APB1_APB2_Clock_Source RCC APB1/APB2 Clock Source
bogdanm 0:9b334a45a8ff 275 * @{
bogdanm 0:9b334a45a8ff 276 */
bogdanm 0:9b334a45a8ff 277 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
bogdanm 0:9b334a45a8ff 278 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
bogdanm 0:9b334a45a8ff 279 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
bogdanm 0:9b334a45a8ff 280 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
bogdanm 0:9b334a45a8ff 281 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
bogdanm 0:9b334a45a8ff 282 /**
bogdanm 0:9b334a45a8ff 283 * @}
bogdanm 0:9b334a45a8ff 284 */
bogdanm 0:9b334a45a8ff 285
bogdanm 0:9b334a45a8ff 286 /** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source
bogdanm 0:9b334a45a8ff 287 * @{
bogdanm 0:9b334a45a8ff 288 */
bogdanm 0:9b334a45a8ff 289 #define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 290 #define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 291 #define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300)
bogdanm 0:9b334a45a8ff 292 #define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300)
bogdanm 0:9b334a45a8ff 293 #define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300)
bogdanm 0:9b334a45a8ff 294 #define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300)
bogdanm 0:9b334a45a8ff 295 #define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300)
bogdanm 0:9b334a45a8ff 296 #define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300)
bogdanm 0:9b334a45a8ff 297 #define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300)
bogdanm 0:9b334a45a8ff 298 #define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300)
bogdanm 0:9b334a45a8ff 299 #define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300)
bogdanm 0:9b334a45a8ff 300 #define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300)
bogdanm 0:9b334a45a8ff 301 #define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300)
bogdanm 0:9b334a45a8ff 302 #define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300)
bogdanm 0:9b334a45a8ff 303 #define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300)
bogdanm 0:9b334a45a8ff 304 #define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300)
bogdanm 0:9b334a45a8ff 305 #define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300)
bogdanm 0:9b334a45a8ff 306 #define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300)
bogdanm 0:9b334a45a8ff 307 #define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300)
bogdanm 0:9b334a45a8ff 308 #define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300)
bogdanm 0:9b334a45a8ff 309 #define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300)
bogdanm 0:9b334a45a8ff 310 #define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300)
bogdanm 0:9b334a45a8ff 311 #define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300)
bogdanm 0:9b334a45a8ff 312 #define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300)
bogdanm 0:9b334a45a8ff 313 #define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300)
bogdanm 0:9b334a45a8ff 314 #define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300)
bogdanm 0:9b334a45a8ff 315 #define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300)
bogdanm 0:9b334a45a8ff 316 #define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300)
bogdanm 0:9b334a45a8ff 317 #define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300)
bogdanm 0:9b334a45a8ff 318 #define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300)
bogdanm 0:9b334a45a8ff 319 #define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300)
bogdanm 0:9b334a45a8ff 320 #define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300)
bogdanm 0:9b334a45a8ff 321 /**
bogdanm 0:9b334a45a8ff 322 * @}
bogdanm 0:9b334a45a8ff 323 */
bogdanm 0:9b334a45a8ff 324
bogdanm 0:9b334a45a8ff 325
bogdanm 0:9b334a45a8ff 326
bogdanm 0:9b334a45a8ff 327 /** @defgroup RCC_MCO_Index RCC MCO Index
bogdanm 0:9b334a45a8ff 328 * @{
bogdanm 0:9b334a45a8ff 329 */
bogdanm 0:9b334a45a8ff 330 #define RCC_MCO1 ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 331 #define RCC_MCO2 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 332 /**
bogdanm 0:9b334a45a8ff 333 * @}
bogdanm 0:9b334a45a8ff 334 */
bogdanm 0:9b334a45a8ff 335
bogdanm 0:9b334a45a8ff 336 /** @defgroup RCC_MCO1_Clock_Source RCC MCO1 Clock Source
bogdanm 0:9b334a45a8ff 337 * @{
bogdanm 0:9b334a45a8ff 338 */
bogdanm 0:9b334a45a8ff 339 #define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 340 #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
bogdanm 0:9b334a45a8ff 341 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
bogdanm 0:9b334a45a8ff 342 #define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
bogdanm 0:9b334a45a8ff 343 /**
bogdanm 0:9b334a45a8ff 344 * @}
bogdanm 0:9b334a45a8ff 345 */
bogdanm 0:9b334a45a8ff 346
bogdanm 0:9b334a45a8ff 347 /** @defgroup RCC_MCO2_Clock_Source RCC MCO2 Clock Source
bogdanm 0:9b334a45a8ff 348 * @{
bogdanm 0:9b334a45a8ff 349 */
bogdanm 0:9b334a45a8ff 350 #define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 351 #define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0
bogdanm 0:9b334a45a8ff 352 #define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
bogdanm 0:9b334a45a8ff 353 #define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
bogdanm 0:9b334a45a8ff 354 /**
bogdanm 0:9b334a45a8ff 355 * @}
bogdanm 0:9b334a45a8ff 356 */
bogdanm 0:9b334a45a8ff 357
bogdanm 0:9b334a45a8ff 358 /** @defgroup RCC_MCOx_Clock_Prescaler RCC MCO1 Clock Prescaler
bogdanm 0:9b334a45a8ff 359 * @{
bogdanm 0:9b334a45a8ff 360 */
bogdanm 0:9b334a45a8ff 361 #define RCC_MCODIV_1 ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 362 #define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
bogdanm 0:9b334a45a8ff 363 #define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
bogdanm 0:9b334a45a8ff 364 #define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
bogdanm 0:9b334a45a8ff 365 #define RCC_MCODIV_5 RCC_CFGR_MCO1PRE
bogdanm 0:9b334a45a8ff 366 /**
bogdanm 0:9b334a45a8ff 367 * @}
bogdanm 0:9b334a45a8ff 368 */
bogdanm 0:9b334a45a8ff 369
bogdanm 0:9b334a45a8ff 370 /** @defgroup RCC_Interrupt RCC Interrupt
bogdanm 0:9b334a45a8ff 371 * @{
bogdanm 0:9b334a45a8ff 372 */
bogdanm 0:9b334a45a8ff 373 #define RCC_IT_LSIRDY ((uint8_t)0x01)
bogdanm 0:9b334a45a8ff 374 #define RCC_IT_LSERDY ((uint8_t)0x02)
bogdanm 0:9b334a45a8ff 375 #define RCC_IT_HSIRDY ((uint8_t)0x04)
bogdanm 0:9b334a45a8ff 376 #define RCC_IT_HSERDY ((uint8_t)0x08)
bogdanm 0:9b334a45a8ff 377 #define RCC_IT_PLLRDY ((uint8_t)0x10)
bogdanm 0:9b334a45a8ff 378 #define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
bogdanm 0:9b334a45a8ff 379 #define RCC_IT_PLLSAIRDY ((uint8_t)0x40)
bogdanm 0:9b334a45a8ff 380 #define RCC_IT_CSS ((uint8_t)0x80)
bogdanm 0:9b334a45a8ff 381 /**
bogdanm 0:9b334a45a8ff 382 * @}
bogdanm 0:9b334a45a8ff 383 */
bogdanm 0:9b334a45a8ff 384
bogdanm 0:9b334a45a8ff 385 /** @defgroup RCC_Flag RCC Flags
bogdanm 0:9b334a45a8ff 386 * Elements values convention: 0XXYYYYYb
bogdanm 0:9b334a45a8ff 387 * - YYYYY : Flag position in the register
bogdanm 0:9b334a45a8ff 388 * - 0XX : Register index
bogdanm 0:9b334a45a8ff 389 * - 01: CR register
bogdanm 0:9b334a45a8ff 390 * - 10: BDCR register
bogdanm 0:9b334a45a8ff 391 * - 11: CSR register
bogdanm 0:9b334a45a8ff 392 * @{
bogdanm 0:9b334a45a8ff 393 */
bogdanm 0:9b334a45a8ff 394 /* Flags in the CR register */
bogdanm 0:9b334a45a8ff 395 #define RCC_FLAG_HSIRDY ((uint8_t)0x21)
bogdanm 0:9b334a45a8ff 396 #define RCC_FLAG_HSERDY ((uint8_t)0x31)
bogdanm 0:9b334a45a8ff 397 #define RCC_FLAG_PLLRDY ((uint8_t)0x39)
bogdanm 0:9b334a45a8ff 398 #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
bogdanm 0:9b334a45a8ff 399 #define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3C)
bogdanm 0:9b334a45a8ff 400
bogdanm 0:9b334a45a8ff 401 /* Flags in the BDCR register */
bogdanm 0:9b334a45a8ff 402 #define RCC_FLAG_LSERDY ((uint8_t)0x41)
bogdanm 0:9b334a45a8ff 403
bogdanm 0:9b334a45a8ff 404 /* Flags in the CSR register */
bogdanm 0:9b334a45a8ff 405 #define RCC_FLAG_LSIRDY ((uint8_t)0x61)
bogdanm 0:9b334a45a8ff 406 #define RCC_FLAG_BORRST ((uint8_t)0x79)
bogdanm 0:9b334a45a8ff 407 #define RCC_FLAG_PINRST ((uint8_t)0x7A)
bogdanm 0:9b334a45a8ff 408 #define RCC_FLAG_PORRST ((uint8_t)0x7B)
bogdanm 0:9b334a45a8ff 409 #define RCC_FLAG_SFTRST ((uint8_t)0x7C)
bogdanm 0:9b334a45a8ff 410 #define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
bogdanm 0:9b334a45a8ff 411 #define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
bogdanm 0:9b334a45a8ff 412 #define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
bogdanm 0:9b334a45a8ff 413 /**
bogdanm 0:9b334a45a8ff 414 * @}
bogdanm 0:9b334a45a8ff 415 */
bogdanm 0:9b334a45a8ff 416
bogdanm 0:9b334a45a8ff 417 /** @defgroup RCC_LSEDrive_Configuration RCC LSE Drive configurations
bogdanm 0:9b334a45a8ff 418 * @{
bogdanm 0:9b334a45a8ff 419 */
bogdanm 0:9b334a45a8ff 420 #define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 421 #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1
bogdanm 0:9b334a45a8ff 422 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0
bogdanm 0:9b334a45a8ff 423 #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV
bogdanm 0:9b334a45a8ff 424 /**
bogdanm 0:9b334a45a8ff 425 * @}
bogdanm 0:9b334a45a8ff 426 */
bogdanm 0:9b334a45a8ff 427
bogdanm 0:9b334a45a8ff 428 /**
bogdanm 0:9b334a45a8ff 429 * @}
bogdanm 0:9b334a45a8ff 430 */
bogdanm 0:9b334a45a8ff 431
bogdanm 0:9b334a45a8ff 432 /* Exported macro ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 433 /** @defgroup RCC_Exported_Macros RCC Exported Macros
bogdanm 0:9b334a45a8ff 434 * @{
bogdanm 0:9b334a45a8ff 435 */
bogdanm 0:9b334a45a8ff 436
bogdanm 0:9b334a45a8ff 437 /** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
bogdanm 0:9b334a45a8ff 438 * @brief Enable or disable the AHB1 peripheral clock.
bogdanm 0:9b334a45a8ff 439 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 0:9b334a45a8ff 440 * is disabled and the application software has to enable this clock before
bogdanm 0:9b334a45a8ff 441 * using it.
bogdanm 0:9b334a45a8ff 442 * @{
bogdanm 0:9b334a45a8ff 443 */
bogdanm 0:9b334a45a8ff 444 #define __HAL_RCC_CRC_CLK_ENABLE() do { \
mbed_official 83:a036322b8637 445 __IO uint32_t tmpreg = 0x00; \
bogdanm 0:9b334a45a8ff 446 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
bogdanm 0:9b334a45a8ff 447 /* Delay after an RCC peripheral clock enabling */ \
bogdanm 0:9b334a45a8ff 448 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
bogdanm 0:9b334a45a8ff 449 UNUSED(tmpreg); \
bogdanm 0:9b334a45a8ff 450 } while(0)
bogdanm 0:9b334a45a8ff 451
bogdanm 0:9b334a45a8ff 452 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \
mbed_official 83:a036322b8637 453 __IO uint32_t tmpreg = 0x00; \
bogdanm 0:9b334a45a8ff 454 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
bogdanm 0:9b334a45a8ff 455 /* Delay after an RCC peripheral clock enabling */ \
bogdanm 0:9b334a45a8ff 456 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
bogdanm 0:9b334a45a8ff 457 UNUSED(tmpreg); \
bogdanm 0:9b334a45a8ff 458 } while(0)
bogdanm 0:9b334a45a8ff 459
bogdanm 0:9b334a45a8ff 460 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
bogdanm 0:9b334a45a8ff 461 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
bogdanm 0:9b334a45a8ff 462
bogdanm 0:9b334a45a8ff 463 /**
bogdanm 0:9b334a45a8ff 464 * @}
bogdanm 0:9b334a45a8ff 465 */
bogdanm 0:9b334a45a8ff 466
bogdanm 0:9b334a45a8ff 467 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
bogdanm 0:9b334a45a8ff 468 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
bogdanm 0:9b334a45a8ff 469 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 0:9b334a45a8ff 470 * is disabled and the application software has to enable this clock before
bogdanm 0:9b334a45a8ff 471 * using it.
bogdanm 0:9b334a45a8ff 472 * @{
bogdanm 0:9b334a45a8ff 473 */
bogdanm 0:9b334a45a8ff 474 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \
mbed_official 83:a036322b8637 475 __IO uint32_t tmpreg = 0x00; \
bogdanm 0:9b334a45a8ff 476 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
bogdanm 0:9b334a45a8ff 477 /* Delay after an RCC peripheral clock enabling */ \
bogdanm 0:9b334a45a8ff 478 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
bogdanm 0:9b334a45a8ff 479 UNUSED(tmpreg); \
bogdanm 0:9b334a45a8ff 480 } while(0)
bogdanm 0:9b334a45a8ff 481
bogdanm 0:9b334a45a8ff 482 #define __HAL_RCC_PWR_CLK_ENABLE() do { \
mbed_official 83:a036322b8637 483 __IO uint32_t tmpreg = 0x00; \
bogdanm 0:9b334a45a8ff 484 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
bogdanm 0:9b334a45a8ff 485 /* Delay after an RCC peripheral clock enabling */ \
bogdanm 0:9b334a45a8ff 486 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
bogdanm 0:9b334a45a8ff 487 UNUSED(tmpreg); \
bogdanm 0:9b334a45a8ff 488 } while(0)
bogdanm 0:9b334a45a8ff 489
bogdanm 0:9b334a45a8ff 490 #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
bogdanm 0:9b334a45a8ff 491 #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
bogdanm 0:9b334a45a8ff 492 /**
bogdanm 0:9b334a45a8ff 493 * @}
bogdanm 0:9b334a45a8ff 494 */
bogdanm 0:9b334a45a8ff 495
bogdanm 0:9b334a45a8ff 496 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
bogdanm 0:9b334a45a8ff 497 * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
bogdanm 0:9b334a45a8ff 498 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 0:9b334a45a8ff 499 * is disabled and the application software has to enable this clock before
bogdanm 0:9b334a45a8ff 500 * using it.
bogdanm 0:9b334a45a8ff 501 * @{
bogdanm 0:9b334a45a8ff 502 */
bogdanm 0:9b334a45a8ff 503 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
mbed_official 83:a036322b8637 504 __IO uint32_t tmpreg = 0x00; \
bogdanm 0:9b334a45a8ff 505 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
bogdanm 0:9b334a45a8ff 506 /* Delay after an RCC peripheral clock enabling */ \
bogdanm 0:9b334a45a8ff 507 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
bogdanm 0:9b334a45a8ff 508 UNUSED(tmpreg); \
bogdanm 0:9b334a45a8ff 509 } while(0)
bogdanm 0:9b334a45a8ff 510
bogdanm 0:9b334a45a8ff 511 #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
bogdanm 0:9b334a45a8ff 512
bogdanm 0:9b334a45a8ff 513 /**
bogdanm 0:9b334a45a8ff 514 * @}
bogdanm 0:9b334a45a8ff 515 */
bogdanm 0:9b334a45a8ff 516
bogdanm 0:9b334a45a8ff 517 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
bogdanm 0:9b334a45a8ff 518 * @brief Get the enable or disable status of the AHB1 peripheral clock.
bogdanm 0:9b334a45a8ff 519 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 0:9b334a45a8ff 520 * is disabled and the application software has to enable this clock before
bogdanm 0:9b334a45a8ff 521 * using it.
bogdanm 0:9b334a45a8ff 522 * @{
bogdanm 0:9b334a45a8ff 523 */
bogdanm 0:9b334a45a8ff 524 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
bogdanm 0:9b334a45a8ff 525 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) != RESET)
bogdanm 0:9b334a45a8ff 526
bogdanm 0:9b334a45a8ff 527 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
bogdanm 0:9b334a45a8ff 528 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) == RESET)
bogdanm 0:9b334a45a8ff 529 /**
bogdanm 0:9b334a45a8ff 530 * @}
bogdanm 0:9b334a45a8ff 531 */
bogdanm 0:9b334a45a8ff 532
bogdanm 0:9b334a45a8ff 533 /** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
bogdanm 0:9b334a45a8ff 534 * @brief Get the enable or disable status of the APB1 peripheral clock.
bogdanm 0:9b334a45a8ff 535 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 0:9b334a45a8ff 536 * is disabled and the application software has to enable this clock before
bogdanm 0:9b334a45a8ff 537 * using it.
bogdanm 0:9b334a45a8ff 538 * @{
bogdanm 0:9b334a45a8ff 539 */
bogdanm 0:9b334a45a8ff 540 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
bogdanm 0:9b334a45a8ff 541 #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
bogdanm 0:9b334a45a8ff 542
bogdanm 0:9b334a45a8ff 543 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
bogdanm 0:9b334a45a8ff 544 #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
bogdanm 0:9b334a45a8ff 545 /**
bogdanm 0:9b334a45a8ff 546 * @}
bogdanm 0:9b334a45a8ff 547 */
bogdanm 0:9b334a45a8ff 548
bogdanm 0:9b334a45a8ff 549 /** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
bogdanm 0:9b334a45a8ff 550 * @brief EGet the enable or disable status of the APB2 peripheral clock.
bogdanm 0:9b334a45a8ff 551 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 0:9b334a45a8ff 552 * is disabled and the application software has to enable this clock before
bogdanm 0:9b334a45a8ff 553 * using it.
bogdanm 0:9b334a45a8ff 554 * @{
bogdanm 0:9b334a45a8ff 555 */
bogdanm 0:9b334a45a8ff 556 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
bogdanm 0:9b334a45a8ff 557 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
bogdanm 0:9b334a45a8ff 558 /**
bogdanm 0:9b334a45a8ff 559 * @}
bogdanm 0:9b334a45a8ff 560 */
bogdanm 0:9b334a45a8ff 561
bogdanm 0:9b334a45a8ff 562 /** @defgroup RCC_Peripheral_Clock_Force_Release RCC Peripheral Clock Force Release
bogdanm 0:9b334a45a8ff 563 * @brief Force or release AHB peripheral reset.
bogdanm 0:9b334a45a8ff 564 * @{
bogdanm 0:9b334a45a8ff 565 */
bogdanm 0:9b334a45a8ff 566 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFF)
bogdanm 0:9b334a45a8ff 567 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
bogdanm 0:9b334a45a8ff 568 #define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
bogdanm 0:9b334a45a8ff 569
bogdanm 0:9b334a45a8ff 570 #define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00)
bogdanm 0:9b334a45a8ff 571 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
bogdanm 0:9b334a45a8ff 572 #define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
bogdanm 0:9b334a45a8ff 573 /**
bogdanm 0:9b334a45a8ff 574 * @}
bogdanm 0:9b334a45a8ff 575 */
bogdanm 0:9b334a45a8ff 576
bogdanm 0:9b334a45a8ff 577 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
bogdanm 0:9b334a45a8ff 578 * @brief Force or release APB1 peripheral reset.
bogdanm 0:9b334a45a8ff 579 * @{
bogdanm 0:9b334a45a8ff 580 */
bogdanm 0:9b334a45a8ff 581 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
bogdanm 0:9b334a45a8ff 582 #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
bogdanm 0:9b334a45a8ff 583 #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
bogdanm 0:9b334a45a8ff 584
bogdanm 0:9b334a45a8ff 585 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
bogdanm 0:9b334a45a8ff 586 #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
bogdanm 0:9b334a45a8ff 587 #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
bogdanm 0:9b334a45a8ff 588 /**
bogdanm 0:9b334a45a8ff 589 * @}
bogdanm 0:9b334a45a8ff 590 */
bogdanm 0:9b334a45a8ff 591
bogdanm 0:9b334a45a8ff 592 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
bogdanm 0:9b334a45a8ff 593 * @brief Force or release APB2 peripheral reset.
bogdanm 0:9b334a45a8ff 594 * @{
bogdanm 0:9b334a45a8ff 595 */
bogdanm 0:9b334a45a8ff 596 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
bogdanm 0:9b334a45a8ff 597 #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
bogdanm 0:9b334a45a8ff 598
bogdanm 0:9b334a45a8ff 599 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
bogdanm 0:9b334a45a8ff 600 #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
bogdanm 0:9b334a45a8ff 601
bogdanm 0:9b334a45a8ff 602 /**
bogdanm 0:9b334a45a8ff 603 * @}
bogdanm 0:9b334a45a8ff 604 */
bogdanm 0:9b334a45a8ff 605
bogdanm 0:9b334a45a8ff 606 /** @defgroup RCC_Peripheral_Clock_Sleep_Enable_Disable RCC Peripheral Clock Sleep Enable Disable
bogdanm 0:9b334a45a8ff 607 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm 0:9b334a45a8ff 608 * power consumption.
bogdanm 0:9b334a45a8ff 609 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm 0:9b334a45a8ff 610 * @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm 0:9b334a45a8ff 611 * @{
bogdanm 0:9b334a45a8ff 612 */
bogdanm 0:9b334a45a8ff 613 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
bogdanm 0:9b334a45a8ff 614 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
bogdanm 0:9b334a45a8ff 615
bogdanm 0:9b334a45a8ff 616 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
bogdanm 0:9b334a45a8ff 617 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
bogdanm 0:9b334a45a8ff 618
bogdanm 0:9b334a45a8ff 619 /** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
bogdanm 0:9b334a45a8ff 620 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm 0:9b334a45a8ff 621 * power consumption.
bogdanm 0:9b334a45a8ff 622 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm 0:9b334a45a8ff 623 * @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm 0:9b334a45a8ff 624 */
bogdanm 0:9b334a45a8ff 625 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
bogdanm 0:9b334a45a8ff 626 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
bogdanm 0:9b334a45a8ff 627
bogdanm 0:9b334a45a8ff 628 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
bogdanm 0:9b334a45a8ff 629 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
bogdanm 0:9b334a45a8ff 630
bogdanm 0:9b334a45a8ff 631 /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
bogdanm 0:9b334a45a8ff 632 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm 0:9b334a45a8ff 633 * power consumption.
bogdanm 0:9b334a45a8ff 634 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm 0:9b334a45a8ff 635 * @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm 0:9b334a45a8ff 636 */
bogdanm 0:9b334a45a8ff 637 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
bogdanm 0:9b334a45a8ff 638 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
bogdanm 0:9b334a45a8ff 639
bogdanm 0:9b334a45a8ff 640 /**
bogdanm 0:9b334a45a8ff 641 * @}
bogdanm 0:9b334a45a8ff 642 */
bogdanm 0:9b334a45a8ff 643
bogdanm 0:9b334a45a8ff 644 /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enable Disable Status
bogdanm 0:9b334a45a8ff 645 * @brief Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode.
bogdanm 0:9b334a45a8ff 646 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm 0:9b334a45a8ff 647 * power consumption.
bogdanm 0:9b334a45a8ff 648 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm 0:9b334a45a8ff 649 * @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm 0:9b334a45a8ff 650 * @{
bogdanm 0:9b334a45a8ff 651 */
bogdanm 0:9b334a45a8ff 652 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) != RESET)
bogdanm 0:9b334a45a8ff 653 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) != RESET)
bogdanm 0:9b334a45a8ff 654
bogdanm 0:9b334a45a8ff 655 #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) == RESET)
bogdanm 0:9b334a45a8ff 656 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) == RESET)
bogdanm 0:9b334a45a8ff 657 /**
bogdanm 0:9b334a45a8ff 658 * @}
bogdanm 0:9b334a45a8ff 659 */
bogdanm 0:9b334a45a8ff 660
bogdanm 0:9b334a45a8ff 661 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enable Disable Status
bogdanm 0:9b334a45a8ff 662 * @brief Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode.
bogdanm 0:9b334a45a8ff 663 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm 0:9b334a45a8ff 664 * power consumption.
bogdanm 0:9b334a45a8ff 665 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm 0:9b334a45a8ff 666 * @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm 0:9b334a45a8ff 667 * @{
bogdanm 0:9b334a45a8ff 668 */
bogdanm 0:9b334a45a8ff 669 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) != RESET)
bogdanm 0:9b334a45a8ff 670 #define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) != RESET)
bogdanm 0:9b334a45a8ff 671
bogdanm 0:9b334a45a8ff 672 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) == RESET)
bogdanm 0:9b334a45a8ff 673 #define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) == RESET)
bogdanm 0:9b334a45a8ff 674 /**
bogdanm 0:9b334a45a8ff 675 * @}
bogdanm 0:9b334a45a8ff 676 */
bogdanm 0:9b334a45a8ff 677
bogdanm 0:9b334a45a8ff 678 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enable Disable Status
bogdanm 0:9b334a45a8ff 679 * @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode.
bogdanm 0:9b334a45a8ff 680 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm 0:9b334a45a8ff 681 * power consumption.
bogdanm 0:9b334a45a8ff 682 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm 0:9b334a45a8ff 683 * @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm 0:9b334a45a8ff 684 * @{
bogdanm 0:9b334a45a8ff 685 */
bogdanm 0:9b334a45a8ff 686 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) != RESET)
bogdanm 0:9b334a45a8ff 687 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) == RESET)
bogdanm 0:9b334a45a8ff 688 /**
bogdanm 0:9b334a45a8ff 689 * @}
bogdanm 0:9b334a45a8ff 690 */
bogdanm 0:9b334a45a8ff 691
bogdanm 0:9b334a45a8ff 692 /** @defgroup RCC_HSI_Configuration HSI Configuration
bogdanm 0:9b334a45a8ff 693 * @{
bogdanm 0:9b334a45a8ff 694 */
bogdanm 0:9b334a45a8ff 695
bogdanm 0:9b334a45a8ff 696 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
bogdanm 0:9b334a45a8ff 697 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
bogdanm 0:9b334a45a8ff 698 * It is used (enabled by hardware) as system clock source after startup
bogdanm 0:9b334a45a8ff 699 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
bogdanm 0:9b334a45a8ff 700 * of the HSE used directly or indirectly as system clock (if the Clock
bogdanm 0:9b334a45a8ff 701 * Security System CSS is enabled).
bogdanm 0:9b334a45a8ff 702 * @note HSI can not be stopped if it is used as system clock source. In this case,
bogdanm 0:9b334a45a8ff 703 * you have to select another source of the system clock then stop the HSI.
bogdanm 0:9b334a45a8ff 704 * @note After enabling the HSI, the application software should wait on HSIRDY
bogdanm 0:9b334a45a8ff 705 * flag to be set indicating that HSI clock is stable and can be used as
bogdanm 0:9b334a45a8ff 706 * system clock source.
bogdanm 0:9b334a45a8ff 707 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
bogdanm 0:9b334a45a8ff 708 * clock cycles.
bogdanm 0:9b334a45a8ff 709 */
bogdanm 0:9b334a45a8ff 710 #define __HAL_RCC_HSI_ENABLE() (RCC->CR |= (RCC_CR_HSION))
bogdanm 0:9b334a45a8ff 711 #define __HAL_RCC_HSI_DISABLE() (RCC->CR &= ~(RCC_CR_HSION))
bogdanm 0:9b334a45a8ff 712
bogdanm 0:9b334a45a8ff 713 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
bogdanm 0:9b334a45a8ff 714 * @note The calibration is used to compensate for the variations in voltage
bogdanm 0:9b334a45a8ff 715 * and temperature that influence the frequency of the internal HSI RC.
bogdanm 0:9b334a45a8ff 716 * @param __HSICALIBRATIONVALUE__: specifies the calibration trimming value.
bogdanm 0:9b334a45a8ff 717 * This parameter must be a number between 0 and 0x1F.
bogdanm 0:9b334a45a8ff 718 */
bogdanm 0:9b334a45a8ff 719 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) (MODIFY_REG(RCC->CR,\
bogdanm 0:9b334a45a8ff 720 RCC_CR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << POSITION_VAL(RCC_CR_HSITRIM)))
bogdanm 0:9b334a45a8ff 721 /**
bogdanm 0:9b334a45a8ff 722 * @}
bogdanm 0:9b334a45a8ff 723 */
bogdanm 0:9b334a45a8ff 724
bogdanm 0:9b334a45a8ff 725 /** @defgroup RCC_LSI_Configuration LSI Configuration
bogdanm 0:9b334a45a8ff 726 * @{
bogdanm 0:9b334a45a8ff 727 */
bogdanm 0:9b334a45a8ff 728
bogdanm 0:9b334a45a8ff 729 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
bogdanm 0:9b334a45a8ff 730 * @note After enabling the LSI, the application software should wait on
bogdanm 0:9b334a45a8ff 731 * LSIRDY flag to be set indicating that LSI clock is stable and can
bogdanm 0:9b334a45a8ff 732 * be used to clock the IWDG and/or the RTC.
bogdanm 0:9b334a45a8ff 733 * @note LSI can not be disabled if the IWDG is running.
bogdanm 0:9b334a45a8ff 734 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
bogdanm 0:9b334a45a8ff 735 * clock cycles.
bogdanm 0:9b334a45a8ff 736 */
bogdanm 0:9b334a45a8ff 737 #define __HAL_RCC_LSI_ENABLE() (RCC->CSR |= (RCC_CSR_LSION))
bogdanm 0:9b334a45a8ff 738 #define __HAL_RCC_LSI_DISABLE() (RCC->CSR &= ~(RCC_CSR_LSION))
bogdanm 0:9b334a45a8ff 739 /**
bogdanm 0:9b334a45a8ff 740 * @}
bogdanm 0:9b334a45a8ff 741 */
bogdanm 0:9b334a45a8ff 742
bogdanm 0:9b334a45a8ff 743 /** @defgroup RCC_HSE_Configuration HSE Configuration
bogdanm 0:9b334a45a8ff 744 * @{
bogdanm 0:9b334a45a8ff 745 */
bogdanm 0:9b334a45a8ff 746 /**
bogdanm 0:9b334a45a8ff 747 * @brief Macro to configure the External High Speed oscillator (__HSE__).
bogdanm 0:9b334a45a8ff 748 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
bogdanm 0:9b334a45a8ff 749 * software should wait on HSERDY flag to be set indicating that HSE clock
bogdanm 0:9b334a45a8ff 750 * is stable and can be used to clock the PLL and/or system clock.
bogdanm 0:9b334a45a8ff 751 * @note HSE state can not be changed if it is used directly or through the
bogdanm 0:9b334a45a8ff 752 * PLL as system clock. In this case, you have to select another source
bogdanm 0:9b334a45a8ff 753 * of the system clock then change the HSE state (ex. disable it).
bogdanm 0:9b334a45a8ff 754 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
bogdanm 0:9b334a45a8ff 755 * @note This function reset the CSSON bit, so if the clock security system(CSS)
bogdanm 0:9b334a45a8ff 756 * was previously enabled you have to enable it again after calling this
bogdanm 0:9b334a45a8ff 757 * function.
bogdanm 0:9b334a45a8ff 758 * @param __STATE__: specifies the new state of the HSE.
bogdanm 0:9b334a45a8ff 759 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 760 * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
bogdanm 0:9b334a45a8ff 761 * 6 HSE oscillator clock cycles.
bogdanm 0:9b334a45a8ff 762 * @arg RCC_HSE_ON: turn ON the HSE oscillator.
bogdanm 0:9b334a45a8ff 763 * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
bogdanm 0:9b334a45a8ff 764 */
bogdanm 0:9b334a45a8ff 765 #define __HAL_RCC_HSE_CONFIG(__STATE__) \
bogdanm 0:9b334a45a8ff 766 do { \
bogdanm 0:9b334a45a8ff 767 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
bogdanm 0:9b334a45a8ff 768 if((__STATE__) == RCC_HSE_ON) \
bogdanm 0:9b334a45a8ff 769 { \
bogdanm 0:9b334a45a8ff 770 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
bogdanm 0:9b334a45a8ff 771 SET_BIT(RCC->CR, RCC_CR_HSEON); \
bogdanm 0:9b334a45a8ff 772 } \
bogdanm 0:9b334a45a8ff 773 else if((__STATE__) == RCC_HSE_BYPASS) \
bogdanm 0:9b334a45a8ff 774 { \
bogdanm 0:9b334a45a8ff 775 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
bogdanm 0:9b334a45a8ff 776 SET_BIT(RCC->CR, RCC_CR_HSEON); \
bogdanm 0:9b334a45a8ff 777 } \
bogdanm 0:9b334a45a8ff 778 else \
bogdanm 0:9b334a45a8ff 779 { \
bogdanm 0:9b334a45a8ff 780 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
bogdanm 0:9b334a45a8ff 781 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
bogdanm 0:9b334a45a8ff 782 } \
bogdanm 0:9b334a45a8ff 783 } while(0)
bogdanm 0:9b334a45a8ff 784 /**
bogdanm 0:9b334a45a8ff 785 * @}
bogdanm 0:9b334a45a8ff 786 */
bogdanm 0:9b334a45a8ff 787
bogdanm 0:9b334a45a8ff 788 /** @defgroup RCC_LSE_Configuration LSE Configuration
bogdanm 0:9b334a45a8ff 789 * @{
bogdanm 0:9b334a45a8ff 790 */
bogdanm 0:9b334a45a8ff 791
bogdanm 0:9b334a45a8ff 792 /**
bogdanm 0:9b334a45a8ff 793 * @brief Macro to configure the External Low Speed oscillator (LSE).
bogdanm 0:9b334a45a8ff 794 * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
bogdanm 0:9b334a45a8ff 795 * User should request a transition to LSE Off first and then LSE On or LSE Bypass.
bogdanm 0:9b334a45a8ff 796 * @note As the LSE is in the Backup domain and write access is denied to
bogdanm 0:9b334a45a8ff 797 * this domain after reset, you have to enable write access using
bogdanm 0:9b334a45a8ff 798 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
bogdanm 0:9b334a45a8ff 799 * (to be done once after reset).
bogdanm 0:9b334a45a8ff 800 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
bogdanm 0:9b334a45a8ff 801 * software should wait on LSERDY flag to be set indicating that LSE clock
bogdanm 0:9b334a45a8ff 802 * is stable and can be used to clock the RTC.
bogdanm 0:9b334a45a8ff 803 * @param __STATE__: specifies the new state of the LSE.
bogdanm 0:9b334a45a8ff 804 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 805 * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
bogdanm 0:9b334a45a8ff 806 * 6 LSE oscillator clock cycles.
bogdanm 0:9b334a45a8ff 807 * @arg RCC_LSE_ON: turn ON the LSE oscillator.
bogdanm 0:9b334a45a8ff 808 * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
bogdanm 0:9b334a45a8ff 809 */
bogdanm 0:9b334a45a8ff 810 #define __HAL_RCC_LSE_CONFIG(__STATE__) \
bogdanm 0:9b334a45a8ff 811 do { \
bogdanm 0:9b334a45a8ff 812 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
bogdanm 0:9b334a45a8ff 813 if((__STATE__) == RCC_LSE_ON) \
bogdanm 0:9b334a45a8ff 814 { \
bogdanm 0:9b334a45a8ff 815 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
bogdanm 0:9b334a45a8ff 816 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
bogdanm 0:9b334a45a8ff 817 } \
bogdanm 0:9b334a45a8ff 818 else if((__STATE__) == RCC_LSE_BYPASS) \
bogdanm 0:9b334a45a8ff 819 { \
bogdanm 0:9b334a45a8ff 820 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
bogdanm 0:9b334a45a8ff 821 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
bogdanm 0:9b334a45a8ff 822 } \
bogdanm 0:9b334a45a8ff 823 else \
bogdanm 0:9b334a45a8ff 824 { \
bogdanm 0:9b334a45a8ff 825 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
bogdanm 0:9b334a45a8ff 826 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
bogdanm 0:9b334a45a8ff 827 } \
bogdanm 0:9b334a45a8ff 828 } while(0)
bogdanm 0:9b334a45a8ff 829 /**
bogdanm 0:9b334a45a8ff 830 * @}
bogdanm 0:9b334a45a8ff 831 */
bogdanm 0:9b334a45a8ff 832
bogdanm 0:9b334a45a8ff 833 /** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration
bogdanm 0:9b334a45a8ff 834 * @{
bogdanm 0:9b334a45a8ff 835 */
bogdanm 0:9b334a45a8ff 836
bogdanm 0:9b334a45a8ff 837 /** @brief Macros to enable or disable the RTC clock.
bogdanm 0:9b334a45a8ff 838 * @note These macros must be used only after the RTC clock source was selected.
bogdanm 0:9b334a45a8ff 839 */
bogdanm 0:9b334a45a8ff 840 #define __HAL_RCC_RTC_ENABLE() (RCC->BDCR |= (RCC_BDCR_RTCEN))
bogdanm 0:9b334a45a8ff 841 #define __HAL_RCC_RTC_DISABLE() (RCC->BDCR &= ~(RCC_BDCR_RTCEN))
bogdanm 0:9b334a45a8ff 842
bogdanm 0:9b334a45a8ff 843 /** @brief Macros to configure the RTC clock (RTCCLK).
bogdanm 0:9b334a45a8ff 844 * @note As the RTC clock configuration bits are in the Backup domain and write
bogdanm 0:9b334a45a8ff 845 * access is denied to this domain after reset, you have to enable write
bogdanm 0:9b334a45a8ff 846 * access using the Power Backup Access macro before to configure
bogdanm 0:9b334a45a8ff 847 * the RTC clock source (to be done once after reset).
bogdanm 0:9b334a45a8ff 848 * @note Once the RTC clock is configured it can't be changed unless the
bogdanm 0:9b334a45a8ff 849 * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
bogdanm 0:9b334a45a8ff 850 * a Power On Reset (POR).
bogdanm 0:9b334a45a8ff 851 * @param __RTCCLKSource__: specifies the RTC clock source.
bogdanm 0:9b334a45a8ff 852 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 853 * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
bogdanm 0:9b334a45a8ff 854 * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
bogdanm 0:9b334a45a8ff 855 * @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected
bogdanm 0:9b334a45a8ff 856 * as RTC clock, where x:[2,31]
bogdanm 0:9b334a45a8ff 857 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
bogdanm 0:9b334a45a8ff 858 * work in STOP and STANDBY modes, and can be used as wakeup source.
bogdanm 0:9b334a45a8ff 859 * However, when the HSE clock is used as RTC clock source, the RTC
bogdanm 0:9b334a45a8ff 860 * cannot be used in STOP and STANDBY modes.
bogdanm 0:9b334a45a8ff 861 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
bogdanm 0:9b334a45a8ff 862 * RTC clock source).
bogdanm 0:9b334a45a8ff 863 */
bogdanm 0:9b334a45a8ff 864 #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
bogdanm 0:9b334a45a8ff 865 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
bogdanm 0:9b334a45a8ff 866
bogdanm 0:9b334a45a8ff 867 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
bogdanm 0:9b334a45a8ff 868 RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFF); \
bogdanm 0:9b334a45a8ff 869 } while (0)
bogdanm 0:9b334a45a8ff 870
bogdanm 0:9b334a45a8ff 871 /** @brief Macros to force or release the Backup domain reset.
bogdanm 0:9b334a45a8ff 872 * @note This function resets the RTC peripheral (including the backup registers)
bogdanm 0:9b334a45a8ff 873 * and the RTC clock source selection in RCC_CSR register.
bogdanm 0:9b334a45a8ff 874 * @note The BKPSRAM is not affected by this reset.
bogdanm 0:9b334a45a8ff 875 */
bogdanm 0:9b334a45a8ff 876 #define __HAL_RCC_BACKUPRESET_FORCE() (RCC->BDCR |= (RCC_BDCR_BDRST))
bogdanm 0:9b334a45a8ff 877 #define __HAL_RCC_BACKUPRESET_RELEASE() (RCC->BDCR &= ~(RCC_BDCR_BDRST))
bogdanm 0:9b334a45a8ff 878 /**
bogdanm 0:9b334a45a8ff 879 * @}
bogdanm 0:9b334a45a8ff 880 */
bogdanm 0:9b334a45a8ff 881
bogdanm 0:9b334a45a8ff 882 /** @defgroup RCC_PLL_Configuration PLL Configuration
bogdanm 0:9b334a45a8ff 883 * @{
bogdanm 0:9b334a45a8ff 884 */
bogdanm 0:9b334a45a8ff 885
bogdanm 0:9b334a45a8ff 886 /** @brief Macros to enable or disable the main PLL.
bogdanm 0:9b334a45a8ff 887 * @note After enabling the main PLL, the application software should wait on
bogdanm 0:9b334a45a8ff 888 * PLLRDY flag to be set indicating that PLL clock is stable and can
bogdanm 0:9b334a45a8ff 889 * be used as system clock source.
bogdanm 0:9b334a45a8ff 890 * @note The main PLL can not be disabled if it is used as system clock source
bogdanm 0:9b334a45a8ff 891 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
bogdanm 0:9b334a45a8ff 892 */
bogdanm 0:9b334a45a8ff 893 #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
bogdanm 0:9b334a45a8ff 894 #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
bogdanm 0:9b334a45a8ff 895
bogdanm 0:9b334a45a8ff 896
bogdanm 0:9b334a45a8ff 897 /** @brief Macro to configure the main PLL clock source, multiplication and division factors.
bogdanm 0:9b334a45a8ff 898 * @note This function must be used only when the main PLL is disabled.
bogdanm 0:9b334a45a8ff 899 * @param __RCC_PLLSource__: specifies the PLL entry clock source.
bogdanm 0:9b334a45a8ff 900 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 901 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
bogdanm 0:9b334a45a8ff 902 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
bogdanm 0:9b334a45a8ff 903 * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
bogdanm 0:9b334a45a8ff 904 * @param __PLLM__: specifies the division factor for PLL VCO input clock
bogdanm 0:9b334a45a8ff 905 * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
bogdanm 0:9b334a45a8ff 906 * @note You have to set the PLLM parameter correctly to ensure that the VCO input
bogdanm 0:9b334a45a8ff 907 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
bogdanm 0:9b334a45a8ff 908 * of 2 MHz to limit PLL jitter.
bogdanm 0:9b334a45a8ff 909 * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
mbed_official 83:a036322b8637 910 * This parameter must be a number between Min_Data = 100 and Max_Data = 432.
bogdanm 0:9b334a45a8ff 911 * @note You have to set the PLLN parameter correctly to ensure that the VCO
mbed_official 83:a036322b8637 912 * output frequency is between 100 and 432 MHz.
bogdanm 0:9b334a45a8ff 913 * @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
bogdanm 0:9b334a45a8ff 914 * This parameter must be a number in the range {2, 4, 6, or 8}.
bogdanm 0:9b334a45a8ff 915 * @note You have to set the PLLP parameter correctly to not exceed 216 MHz on
bogdanm 0:9b334a45a8ff 916 * the System clock frequency.
bogdanm 0:9b334a45a8ff 917 * @param __PLLQ__: specifies the division factor for OTG FS, SDMMC and RNG clocks
bogdanm 0:9b334a45a8ff 918 * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
bogdanm 0:9b334a45a8ff 919 * @note If the USB OTG FS is used in your application, you have to set the
bogdanm 0:9b334a45a8ff 920 * PLLQ parameter correctly to have 48 MHz clock for the USB. However,
bogdanm 0:9b334a45a8ff 921 * the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work
bogdanm 0:9b334a45a8ff 922 * correctly.
bogdanm 0:9b334a45a8ff 923 */
bogdanm 0:9b334a45a8ff 924 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__)\
bogdanm 0:9b334a45a8ff 925 (RCC->PLLCFGR = (0x20000000 | (__PLLM__) | ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \
bogdanm 0:9b334a45a8ff 926 ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | (__RCC_PLLSource__) | \
bogdanm 0:9b334a45a8ff 927 ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))
bogdanm 0:9b334a45a8ff 928
bogdanm 0:9b334a45a8ff 929 /** @brief Macro to configure the PLL clock source.
bogdanm 0:9b334a45a8ff 930 * @note This function must be used only when the main PLL is disabled.
bogdanm 0:9b334a45a8ff 931 * @param __PLLSOURCE__: specifies the PLL entry clock source.
bogdanm 0:9b334a45a8ff 932 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 933 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
bogdanm 0:9b334a45a8ff 934 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
bogdanm 0:9b334a45a8ff 935 *
bogdanm 0:9b334a45a8ff 936 */
bogdanm 0:9b334a45a8ff 937 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
bogdanm 0:9b334a45a8ff 938
bogdanm 0:9b334a45a8ff 939 /** @brief Macro to configure the PLL multiplication factor.
bogdanm 0:9b334a45a8ff 940 * @note This function must be used only when the main PLL is disabled.
bogdanm 0:9b334a45a8ff 941 * @param __PLLM__: specifies the division factor for PLL VCO input clock
bogdanm 0:9b334a45a8ff 942 * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
bogdanm 0:9b334a45a8ff 943 * @note You have to set the PLLM parameter correctly to ensure that the VCO input
bogdanm 0:9b334a45a8ff 944 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
bogdanm 0:9b334a45a8ff 945 * of 2 MHz to limit PLL jitter.
bogdanm 0:9b334a45a8ff 946 *
bogdanm 0:9b334a45a8ff 947 */
bogdanm 0:9b334a45a8ff 948 #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
bogdanm 0:9b334a45a8ff 949 /**
bogdanm 0:9b334a45a8ff 950 * @}
bogdanm 0:9b334a45a8ff 951 */
bogdanm 0:9b334a45a8ff 952
bogdanm 0:9b334a45a8ff 953 /** @defgroup RCC_PLL_I2S_Configuration PLL I2S Configuration
bogdanm 0:9b334a45a8ff 954 * @{
bogdanm 0:9b334a45a8ff 955 */
bogdanm 0:9b334a45a8ff 956
bogdanm 0:9b334a45a8ff 957 /** @brief Macro to configure the I2S clock source (I2SCLK).
bogdanm 0:9b334a45a8ff 958 * @note This function must be called before enabling the I2S APB clock.
bogdanm 0:9b334a45a8ff 959 * @param __SOURCE__: specifies the I2S clock source.
bogdanm 0:9b334a45a8ff 960 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 961 * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
bogdanm 0:9b334a45a8ff 962 * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
bogdanm 0:9b334a45a8ff 963 * used as I2S clock source.
bogdanm 0:9b334a45a8ff 964 */
bogdanm 0:9b334a45a8ff 965 #define __HAL_RCC_I2S_CONFIG(__SOURCE__) do {RCC->CFGR &= ~(RCC_CFGR_I2SSRC); \
mbed_official 83:a036322b8637 966 RCC->CFGR |= (__SOURCE__); \
mbed_official 83:a036322b8637 967 }while(0)
bogdanm 0:9b334a45a8ff 968
bogdanm 0:9b334a45a8ff 969 /** @brief Macros to enable or disable the PLLI2S.
bogdanm 0:9b334a45a8ff 970 * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
bogdanm 0:9b334a45a8ff 971 */
bogdanm 0:9b334a45a8ff 972 #define __HAL_RCC_PLLI2S_ENABLE() (RCC->CR |= (RCC_CR_PLLI2SON))
bogdanm 0:9b334a45a8ff 973 #define __HAL_RCC_PLLI2S_DISABLE() (RCC->CR &= ~(RCC_CR_PLLI2SON))
bogdanm 0:9b334a45a8ff 974 /**
bogdanm 0:9b334a45a8ff 975 * @}
bogdanm 0:9b334a45a8ff 976 */
bogdanm 0:9b334a45a8ff 977
bogdanm 0:9b334a45a8ff 978 /** @defgroup RCC_Get_Clock_source Get Clock source
bogdanm 0:9b334a45a8ff 979 * @{
bogdanm 0:9b334a45a8ff 980 */
bogdanm 0:9b334a45a8ff 981 /**
bogdanm 0:9b334a45a8ff 982 * @brief Macro to configure the system clock source.
bogdanm 0:9b334a45a8ff 983 * @param __RCC_SYSCLKSOURCE__: specifies the system clock source.
bogdanm 0:9b334a45a8ff 984 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 985 * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
bogdanm 0:9b334a45a8ff 986 * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
bogdanm 0:9b334a45a8ff 987 * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
bogdanm 0:9b334a45a8ff 988 */
bogdanm 0:9b334a45a8ff 989 #define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
bogdanm 0:9b334a45a8ff 990
bogdanm 0:9b334a45a8ff 991 /** @brief Macro to get the clock source used as system clock.
bogdanm 0:9b334a45a8ff 992 * @retval The clock source used as system clock. The returned value can be one
bogdanm 0:9b334a45a8ff 993 * of the following:
bogdanm 0:9b334a45a8ff 994 * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
bogdanm 0:9b334a45a8ff 995 * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
bogdanm 0:9b334a45a8ff 996 * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
bogdanm 0:9b334a45a8ff 997 */
bogdanm 0:9b334a45a8ff 998 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
bogdanm 0:9b334a45a8ff 999
bogdanm 0:9b334a45a8ff 1000 /**
bogdanm 0:9b334a45a8ff 1001 * @brief Macro to configures the External Low Speed oscillator (LSE) drive capability.
bogdanm 0:9b334a45a8ff 1002 * @note As the LSE is in the Backup domain and write access is denied to
bogdanm 0:9b334a45a8ff 1003 * this domain after reset, you have to enable write access using
bogdanm 0:9b334a45a8ff 1004 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
bogdanm 0:9b334a45a8ff 1005 * (to be done once after reset).
bogdanm 0:9b334a45a8ff 1006 * @param __RCC_LSEDRIVE__: specifies the new state of the LSE drive capability.
bogdanm 0:9b334a45a8ff 1007 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1008 * @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability.
bogdanm 0:9b334a45a8ff 1009 * @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability.
bogdanm 0:9b334a45a8ff 1010 * @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability.
bogdanm 0:9b334a45a8ff 1011 * @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability.
bogdanm 0:9b334a45a8ff 1012 * @retval None
bogdanm 0:9b334a45a8ff 1013 */
bogdanm 0:9b334a45a8ff 1014 #define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) \
bogdanm 0:9b334a45a8ff 1015 (MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) ))
bogdanm 0:9b334a45a8ff 1016
bogdanm 0:9b334a45a8ff 1017 /** @brief Macro to get the oscillator used as PLL clock source.
bogdanm 0:9b334a45a8ff 1018 * @retval The oscillator used as PLL clock source. The returned value can be one
bogdanm 0:9b334a45a8ff 1019 * of the following:
bogdanm 0:9b334a45a8ff 1020 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
bogdanm 0:9b334a45a8ff 1021 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
bogdanm 0:9b334a45a8ff 1022 */
bogdanm 0:9b334a45a8ff 1023 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
bogdanm 0:9b334a45a8ff 1024 /**
bogdanm 0:9b334a45a8ff 1025 * @}
bogdanm 0:9b334a45a8ff 1026 */
mbed_official 83:a036322b8637 1027
mbed_official 83:a036322b8637 1028 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
mbed_official 83:a036322b8637 1029 * @{
mbed_official 83:a036322b8637 1030 */
mbed_official 83:a036322b8637 1031
mbed_official 83:a036322b8637 1032 /** @brief Macro to configure the MCO1 clock.
mbed_official 83:a036322b8637 1033 * @param __MCOCLKSOURCE__ specifies the MCO clock source.
mbed_official 83:a036322b8637 1034 * This parameter can be one of the following values:
mbed_official 83:a036322b8637 1035 * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
mbed_official 83:a036322b8637 1036 * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
mbed_official 83:a036322b8637 1037 * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
mbed_official 83:a036322b8637 1038 * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
mbed_official 83:a036322b8637 1039 * @param __MCODIV__ specifies the MCO clock prescaler.
mbed_official 83:a036322b8637 1040 * This parameter can be one of the following values:
mbed_official 83:a036322b8637 1041 * @arg RCC_MCODIV_1: no division applied to MCOx clock
mbed_official 83:a036322b8637 1042 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
mbed_official 83:a036322b8637 1043 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
mbed_official 83:a036322b8637 1044 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
mbed_official 83:a036322b8637 1045 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
mbed_official 83:a036322b8637 1046 */
bogdanm 0:9b334a45a8ff 1047
mbed_official 83:a036322b8637 1048 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
mbed_official 83:a036322b8637 1049 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
mbed_official 83:a036322b8637 1050
mbed_official 83:a036322b8637 1051 /** @brief Macro to configure the MCO2 clock.
mbed_official 83:a036322b8637 1052 * @param __MCOCLKSOURCE__ specifies the MCO clock source.
mbed_official 83:a036322b8637 1053 * This parameter can be one of the following values:
mbed_official 83:a036322b8637 1054 * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
mbed_official 83:a036322b8637 1055 * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source
mbed_official 83:a036322b8637 1056 * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
mbed_official 83:a036322b8637 1057 * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
mbed_official 83:a036322b8637 1058 * @param __MCODIV__ specifies the MCO clock prescaler.
mbed_official 83:a036322b8637 1059 * This parameter can be one of the following values:
mbed_official 83:a036322b8637 1060 * @arg RCC_MCODIV_1: no division applied to MCOx clock
mbed_official 83:a036322b8637 1061 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
mbed_official 83:a036322b8637 1062 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
mbed_official 83:a036322b8637 1063 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
mbed_official 83:a036322b8637 1064 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
mbed_official 83:a036322b8637 1065 */
mbed_official 83:a036322b8637 1066
mbed_official 83:a036322b8637 1067 #define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
mbed_official 83:a036322b8637 1068 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3)));
mbed_official 83:a036322b8637 1069 /**
mbed_official 83:a036322b8637 1070 * @}
mbed_official 83:a036322b8637 1071 */
mbed_official 83:a036322b8637 1072
bogdanm 0:9b334a45a8ff 1073 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
bogdanm 0:9b334a45a8ff 1074 * @brief macros to manage the specified RCC Flags and interrupts.
bogdanm 0:9b334a45a8ff 1075 * @{
bogdanm 0:9b334a45a8ff 1076 */
bogdanm 0:9b334a45a8ff 1077
bogdanm 0:9b334a45a8ff 1078 /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
bogdanm 0:9b334a45a8ff 1079 * the selected interrupts).
bogdanm 0:9b334a45a8ff 1080 * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
bogdanm 0:9b334a45a8ff 1081 * This parameter can be any combination of the following values:
bogdanm 0:9b334a45a8ff 1082 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
bogdanm 0:9b334a45a8ff 1083 * @arg RCC_IT_LSERDY: LSE ready interrupt.
bogdanm 0:9b334a45a8ff 1084 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
bogdanm 0:9b334a45a8ff 1085 * @arg RCC_IT_HSERDY: HSE ready interrupt.
bogdanm 0:9b334a45a8ff 1086 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
bogdanm 0:9b334a45a8ff 1087 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
bogdanm 0:9b334a45a8ff 1088 */
bogdanm 0:9b334a45a8ff 1089 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
bogdanm 0:9b334a45a8ff 1090
bogdanm 0:9b334a45a8ff 1091 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
bogdanm 0:9b334a45a8ff 1092 * the selected interrupts).
bogdanm 0:9b334a45a8ff 1093 * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
bogdanm 0:9b334a45a8ff 1094 * This parameter can be any combination of the following values:
bogdanm 0:9b334a45a8ff 1095 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
bogdanm 0:9b334a45a8ff 1096 * @arg RCC_IT_LSERDY: LSE ready interrupt.
bogdanm 0:9b334a45a8ff 1097 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
bogdanm 0:9b334a45a8ff 1098 * @arg RCC_IT_HSERDY: HSE ready interrupt.
bogdanm 0:9b334a45a8ff 1099 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
bogdanm 0:9b334a45a8ff 1100 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
bogdanm 0:9b334a45a8ff 1101 */
bogdanm 0:9b334a45a8ff 1102 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
bogdanm 0:9b334a45a8ff 1103
bogdanm 0:9b334a45a8ff 1104 /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
bogdanm 0:9b334a45a8ff 1105 * bits to clear the selected interrupt pending bits.
bogdanm 0:9b334a45a8ff 1106 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
bogdanm 0:9b334a45a8ff 1107 * This parameter can be any combination of the following values:
bogdanm 0:9b334a45a8ff 1108 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
bogdanm 0:9b334a45a8ff 1109 * @arg RCC_IT_LSERDY: LSE ready interrupt.
bogdanm 0:9b334a45a8ff 1110 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
bogdanm 0:9b334a45a8ff 1111 * @arg RCC_IT_HSERDY: HSE ready interrupt.
bogdanm 0:9b334a45a8ff 1112 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
bogdanm 0:9b334a45a8ff 1113 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
bogdanm 0:9b334a45a8ff 1114 * @arg RCC_IT_CSS: Clock Security System interrupt
bogdanm 0:9b334a45a8ff 1115 */
bogdanm 0:9b334a45a8ff 1116 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
bogdanm 0:9b334a45a8ff 1117
bogdanm 0:9b334a45a8ff 1118 /** @brief Check the RCC's interrupt has occurred or not.
bogdanm 0:9b334a45a8ff 1119 * @param __INTERRUPT__: specifies the RCC interrupt source to check.
bogdanm 0:9b334a45a8ff 1120 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1121 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
bogdanm 0:9b334a45a8ff 1122 * @arg RCC_IT_LSERDY: LSE ready interrupt.
bogdanm 0:9b334a45a8ff 1123 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
bogdanm 0:9b334a45a8ff 1124 * @arg RCC_IT_HSERDY: HSE ready interrupt.
bogdanm 0:9b334a45a8ff 1125 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
bogdanm 0:9b334a45a8ff 1126 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
bogdanm 0:9b334a45a8ff 1127 * @arg RCC_IT_CSS: Clock Security System interrupt
bogdanm 0:9b334a45a8ff 1128 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
bogdanm 0:9b334a45a8ff 1129 */
bogdanm 0:9b334a45a8ff 1130 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
bogdanm 0:9b334a45a8ff 1131
bogdanm 0:9b334a45a8ff 1132 /** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
bogdanm 0:9b334a45a8ff 1133 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
bogdanm 0:9b334a45a8ff 1134 */
bogdanm 0:9b334a45a8ff 1135 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
bogdanm 0:9b334a45a8ff 1136
bogdanm 0:9b334a45a8ff 1137 /** @brief Check RCC flag is set or not.
bogdanm 0:9b334a45a8ff 1138 * @param __FLAG__: specifies the flag to check.
bogdanm 0:9b334a45a8ff 1139 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1140 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
bogdanm 0:9b334a45a8ff 1141 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
bogdanm 0:9b334a45a8ff 1142 * @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
bogdanm 0:9b334a45a8ff 1143 * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.
bogdanm 0:9b334a45a8ff 1144 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
bogdanm 0:9b334a45a8ff 1145 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
bogdanm 0:9b334a45a8ff 1146 * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
bogdanm 0:9b334a45a8ff 1147 * @arg RCC_FLAG_PINRST: Pin reset.
bogdanm 0:9b334a45a8ff 1148 * @arg RCC_FLAG_PORRST: POR/PDR reset.
bogdanm 0:9b334a45a8ff 1149 * @arg RCC_FLAG_SFTRST: Software reset.
bogdanm 0:9b334a45a8ff 1150 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
bogdanm 0:9b334a45a8ff 1151 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
bogdanm 0:9b334a45a8ff 1152 * @arg RCC_FLAG_LPWRRST: Low Power reset.
bogdanm 0:9b334a45a8ff 1153 * @retval The new state of __FLAG__ (TRUE or FALSE).
bogdanm 0:9b334a45a8ff 1154 */
bogdanm 0:9b334a45a8ff 1155 #define RCC_FLAG_MASK ((uint8_t)0x1F)
bogdanm 0:9b334a45a8ff 1156 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0)
bogdanm 0:9b334a45a8ff 1157
bogdanm 0:9b334a45a8ff 1158 /**
bogdanm 0:9b334a45a8ff 1159 * @}
bogdanm 0:9b334a45a8ff 1160 */
bogdanm 0:9b334a45a8ff 1161
bogdanm 0:9b334a45a8ff 1162 /**
bogdanm 0:9b334a45a8ff 1163 * @}
bogdanm 0:9b334a45a8ff 1164 */
bogdanm 0:9b334a45a8ff 1165
bogdanm 0:9b334a45a8ff 1166 /* Include RCC HAL Extension module */
bogdanm 0:9b334a45a8ff 1167 #include "stm32f7xx_hal_rcc_ex.h"
bogdanm 0:9b334a45a8ff 1168
bogdanm 0:9b334a45a8ff 1169 /* Exported functions --------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 1170 /** @addtogroup RCC_Exported_Functions
bogdanm 0:9b334a45a8ff 1171 * @{
bogdanm 0:9b334a45a8ff 1172 */
bogdanm 0:9b334a45a8ff 1173
bogdanm 0:9b334a45a8ff 1174 /** @addtogroup RCC_Exported_Functions_Group1
bogdanm 0:9b334a45a8ff 1175 * @{
bogdanm 0:9b334a45a8ff 1176 */
bogdanm 0:9b334a45a8ff 1177 /* Initialization and de-initialization functions ******************************/
bogdanm 0:9b334a45a8ff 1178 void HAL_RCC_DeInit(void);
bogdanm 0:9b334a45a8ff 1179 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
bogdanm 0:9b334a45a8ff 1180 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
bogdanm 0:9b334a45a8ff 1181 /**
bogdanm 0:9b334a45a8ff 1182 * @}
bogdanm 0:9b334a45a8ff 1183 */
bogdanm 0:9b334a45a8ff 1184
bogdanm 0:9b334a45a8ff 1185 /** @addtogroup RCC_Exported_Functions_Group2
bogdanm 0:9b334a45a8ff 1186 * @{
bogdanm 0:9b334a45a8ff 1187 */
bogdanm 0:9b334a45a8ff 1188 /* Peripheral Control functions ************************************************/
bogdanm 0:9b334a45a8ff 1189 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
bogdanm 0:9b334a45a8ff 1190 void HAL_RCC_EnableCSS(void);
bogdanm 0:9b334a45a8ff 1191 void HAL_RCC_DisableCSS(void);
bogdanm 0:9b334a45a8ff 1192 uint32_t HAL_RCC_GetSysClockFreq(void);
bogdanm 0:9b334a45a8ff 1193 uint32_t HAL_RCC_GetHCLKFreq(void);
bogdanm 0:9b334a45a8ff 1194 uint32_t HAL_RCC_GetPCLK1Freq(void);
bogdanm 0:9b334a45a8ff 1195 uint32_t HAL_RCC_GetPCLK2Freq(void);
bogdanm 0:9b334a45a8ff 1196 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
bogdanm 0:9b334a45a8ff 1197 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
bogdanm 0:9b334a45a8ff 1198
bogdanm 0:9b334a45a8ff 1199 /* CSS NMI IRQ handler */
bogdanm 0:9b334a45a8ff 1200 void HAL_RCC_NMI_IRQHandler(void);
bogdanm 0:9b334a45a8ff 1201
bogdanm 0:9b334a45a8ff 1202 /* User Callbacks in non blocking mode (IT mode) */
bogdanm 0:9b334a45a8ff 1203 void HAL_RCC_CSSCallback(void);
bogdanm 0:9b334a45a8ff 1204 /**
bogdanm 0:9b334a45a8ff 1205 * @}
bogdanm 0:9b334a45a8ff 1206 */
bogdanm 0:9b334a45a8ff 1207
bogdanm 0:9b334a45a8ff 1208 /**
bogdanm 0:9b334a45a8ff 1209 * @}
bogdanm 0:9b334a45a8ff 1210 */
bogdanm 0:9b334a45a8ff 1211
bogdanm 0:9b334a45a8ff 1212 /* Private types -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 1213 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 1214 /* Private constants ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 1215 /** @defgroup RCC_Private_Constants RCC Private Constants
bogdanm 0:9b334a45a8ff 1216 * @{
bogdanm 0:9b334a45a8ff 1217 */
bogdanm 0:9b334a45a8ff 1218 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
bogdanm 0:9b334a45a8ff 1219 #define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
bogdanm 0:9b334a45a8ff 1220 #define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
bogdanm 0:9b334a45a8ff 1221 #define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
bogdanm 0:9b334a45a8ff 1222 #define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
bogdanm 0:9b334a45a8ff 1223
bogdanm 0:9b334a45a8ff 1224 /** @defgroup RCC_BitAddress_Alias RCC BitAddress Alias
bogdanm 0:9b334a45a8ff 1225 * @brief RCC registers bit address alias
bogdanm 0:9b334a45a8ff 1226 * @{
bogdanm 0:9b334a45a8ff 1227 */
bogdanm 0:9b334a45a8ff 1228 /* CIR register byte 2 (Bits[15:8]) base address */
bogdanm 0:9b334a45a8ff 1229 #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01))
bogdanm 0:9b334a45a8ff 1230
bogdanm 0:9b334a45a8ff 1231 /* CIR register byte 3 (Bits[23:16]) base address */
bogdanm 0:9b334a45a8ff 1232 #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))
bogdanm 0:9b334a45a8ff 1233
bogdanm 0:9b334a45a8ff 1234 #define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100)
bogdanm 0:9b334a45a8ff 1235 #define RCC_LSE_TIMEOUT_VALUE ((uint32_t)5000)
bogdanm 0:9b334a45a8ff 1236 /**
bogdanm 0:9b334a45a8ff 1237 * @}
bogdanm 0:9b334a45a8ff 1238 */
bogdanm 0:9b334a45a8ff 1239 /**
bogdanm 0:9b334a45a8ff 1240 * @}
bogdanm 0:9b334a45a8ff 1241 */
bogdanm 0:9b334a45a8ff 1242
bogdanm 0:9b334a45a8ff 1243 /* Private macros ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 1244 /** @addtogroup RCC_Private_Macros RCC Private Macros
bogdanm 0:9b334a45a8ff 1245 * @{
bogdanm 0:9b334a45a8ff 1246 */
bogdanm 0:9b334a45a8ff 1247
bogdanm 0:9b334a45a8ff 1248 /** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters
bogdanm 0:9b334a45a8ff 1249 * @{
bogdanm 0:9b334a45a8ff 1250 */
bogdanm 0:9b334a45a8ff 1251 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15)
bogdanm 0:9b334a45a8ff 1252
bogdanm 0:9b334a45a8ff 1253 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
bogdanm 0:9b334a45a8ff 1254 ((HSE) == RCC_HSE_BYPASS))
bogdanm 0:9b334a45a8ff 1255
bogdanm 0:9b334a45a8ff 1256 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
bogdanm 0:9b334a45a8ff 1257 ((LSE) == RCC_LSE_BYPASS))
bogdanm 0:9b334a45a8ff 1258
bogdanm 0:9b334a45a8ff 1259 #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
bogdanm 0:9b334a45a8ff 1260
bogdanm 0:9b334a45a8ff 1261 #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
bogdanm 0:9b334a45a8ff 1262
bogdanm 0:9b334a45a8ff 1263 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
bogdanm 0:9b334a45a8ff 1264
bogdanm 0:9b334a45a8ff 1265 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
bogdanm 0:9b334a45a8ff 1266 ((SOURCE) == RCC_PLLSOURCE_HSE))
bogdanm 0:9b334a45a8ff 1267
bogdanm 0:9b334a45a8ff 1268 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
bogdanm 0:9b334a45a8ff 1269 ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
bogdanm 0:9b334a45a8ff 1270 ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
bogdanm 0:9b334a45a8ff 1271 #define IS_RCC_PLLM_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 63))
bogdanm 0:9b334a45a8ff 1272
mbed_official 83:a036322b8637 1273 #define IS_RCC_PLLN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
bogdanm 0:9b334a45a8ff 1274
bogdanm 0:9b334a45a8ff 1275 #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == RCC_PLLP_DIV2) || ((VALUE) == RCC_PLLP_DIV4) || \
bogdanm 0:9b334a45a8ff 1276 ((VALUE) == RCC_PLLP_DIV6) || ((VALUE) == RCC_PLLP_DIV8))
bogdanm 0:9b334a45a8ff 1277 #define IS_RCC_PLLQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
bogdanm 0:9b334a45a8ff 1278
bogdanm 0:9b334a45a8ff 1279 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \
bogdanm 0:9b334a45a8ff 1280 ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \
bogdanm 0:9b334a45a8ff 1281 ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \
bogdanm 0:9b334a45a8ff 1282 ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \
bogdanm 0:9b334a45a8ff 1283 ((HCLK) == RCC_SYSCLK_DIV512))
bogdanm 0:9b334a45a8ff 1284
bogdanm 0:9b334a45a8ff 1285 #define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15))
bogdanm 0:9b334a45a8ff 1286
bogdanm 0:9b334a45a8ff 1287 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \
bogdanm 0:9b334a45a8ff 1288 ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \
bogdanm 0:9b334a45a8ff 1289 ((PCLK) == RCC_HCLK_DIV16))
bogdanm 0:9b334a45a8ff 1290
bogdanm 0:9b334a45a8ff 1291 #define IS_RCC_MCO(MCOX) (((MCOX) == RCC_MCO1) || ((MCOX) == RCC_MCO2))
bogdanm 0:9b334a45a8ff 1292
bogdanm 0:9b334a45a8ff 1293
bogdanm 0:9b334a45a8ff 1294 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
bogdanm 0:9b334a45a8ff 1295 ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
bogdanm 0:9b334a45a8ff 1296
bogdanm 0:9b334a45a8ff 1297 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \
bogdanm 0:9b334a45a8ff 1298 ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
bogdanm 0:9b334a45a8ff 1299
bogdanm 0:9b334a45a8ff 1300 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
bogdanm 0:9b334a45a8ff 1301 ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
bogdanm 0:9b334a45a8ff 1302 ((DIV) == RCC_MCODIV_5))
bogdanm 0:9b334a45a8ff 1303 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
bogdanm 0:9b334a45a8ff 1304
bogdanm 0:9b334a45a8ff 1305 #define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_LSE) || ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \
bogdanm 0:9b334a45a8ff 1306 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV3) || \
bogdanm 0:9b334a45a8ff 1307 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV5) || \
bogdanm 0:9b334a45a8ff 1308 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV6) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV7) || \
bogdanm 0:9b334a45a8ff 1309 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV9) || \
bogdanm 0:9b334a45a8ff 1310 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV10) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV11) || \
bogdanm 0:9b334a45a8ff 1311 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV12) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV13) || \
bogdanm 0:9b334a45a8ff 1312 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV14) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV15) || \
bogdanm 0:9b334a45a8ff 1313 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV17) || \
bogdanm 0:9b334a45a8ff 1314 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV18) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV19) || \
bogdanm 0:9b334a45a8ff 1315 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV20) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV21) || \
bogdanm 0:9b334a45a8ff 1316 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV22) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV23) || \
bogdanm 0:9b334a45a8ff 1317 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV24) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV25) || \
bogdanm 0:9b334a45a8ff 1318 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV26) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV27) || \
bogdanm 0:9b334a45a8ff 1319 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV28) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV29) || \
bogdanm 0:9b334a45a8ff 1320 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV30) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV31))
bogdanm 0:9b334a45a8ff 1321
bogdanm 0:9b334a45a8ff 1322
bogdanm 0:9b334a45a8ff 1323 #define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDRIVE_LOW) || \
mbed_official 83:a036322b8637 1324 ((DRIVE) == RCC_LSEDRIVE_MEDIUMLOW) || \
mbed_official 83:a036322b8637 1325 ((DRIVE) == RCC_LSEDRIVE_MEDIUMHIGH) || \
mbed_official 83:a036322b8637 1326 ((DRIVE) == RCC_LSEDRIVE_HIGH))
bogdanm 0:9b334a45a8ff 1327 /**
bogdanm 0:9b334a45a8ff 1328 * @}
bogdanm 0:9b334a45a8ff 1329 */
bogdanm 0:9b334a45a8ff 1330
bogdanm 0:9b334a45a8ff 1331 /**
bogdanm 0:9b334a45a8ff 1332 * @}
bogdanm 0:9b334a45a8ff 1333 */
bogdanm 0:9b334a45a8ff 1334
bogdanm 0:9b334a45a8ff 1335 /**
bogdanm 0:9b334a45a8ff 1336 * @}
bogdanm 0:9b334a45a8ff 1337 */
bogdanm 0:9b334a45a8ff 1338
bogdanm 0:9b334a45a8ff 1339 /**
bogdanm 0:9b334a45a8ff 1340 * @}
bogdanm 0:9b334a45a8ff 1341 */
bogdanm 0:9b334a45a8ff 1342
bogdanm 0:9b334a45a8ff 1343 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 1344 }
bogdanm 0:9b334a45a8ff 1345 #endif
bogdanm 0:9b334a45a8ff 1346
bogdanm 0:9b334a45a8ff 1347 #endif /* __STM32F7xx_HAL_RCC_H */
bogdanm 0:9b334a45a8ff 1348
bogdanm 0:9b334a45a8ff 1349 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/