Fawwaz Nadzmy / mbed-STM

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/hal/TARGET_WIZNET/TARGET_W7500x/gpio_irq_api.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /* mbed Microcontroller Library
bogdanm 0:9b334a45a8ff 2 *******************************************************************************
bogdanm 0:9b334a45a8ff 3 * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved.
bogdanm 0:9b334a45a8ff 4 * All rights reserved.
bogdanm 0:9b334a45a8ff 5 *
bogdanm 0:9b334a45a8ff 6 * Redistribution and use in source and binary forms, with or without
bogdanm 0:9b334a45a8ff 7 * modification, are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 8 *
bogdanm 0:9b334a45a8ff 9 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 10 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 11 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 12 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 13 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 14 * 3. Neither the name of ARM Limited nor the names of its contributors
bogdanm 0:9b334a45a8ff 15 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 16 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 17 *
bogdanm 0:9b334a45a8ff 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 21 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 25 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 28 *******************************************************************************
bogdanm 0:9b334a45a8ff 29 */
bogdanm 0:9b334a45a8ff 30
bogdanm 0:9b334a45a8ff 31 #include <stddef.h>
bogdanm 0:9b334a45a8ff 32 #include "cmsis.h"
bogdanm 0:9b334a45a8ff 33 #include "gpio_irq_api.h"
bogdanm 0:9b334a45a8ff 34 #include "pinmap.h"
bogdanm 0:9b334a45a8ff 35 #include "mbed_error.h"
bogdanm 0:9b334a45a8ff 36
bogdanm 0:9b334a45a8ff 37 #define EDGE_NONE (0)
bogdanm 0:9b334a45a8ff 38 #define EDGE_RISE (1)
bogdanm 0:9b334a45a8ff 39 #define EDGE_FALL (2)
bogdanm 0:9b334a45a8ff 40 #define EDGE_BOTH (3)
bogdanm 0:9b334a45a8ff 41
bogdanm 0:9b334a45a8ff 42 static gpio_irq_handler irq_handler;
bogdanm 0:9b334a45a8ff 43
bogdanm 0:9b334a45a8ff 44 static uint32_t channel_ids[4][16];
bogdanm 0:9b334a45a8ff 45
bogdanm 0:9b334a45a8ff 46 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 47 extern "C"{
bogdanm 0:9b334a45a8ff 48 #endif
bogdanm 0:9b334a45a8ff 49 void port_generic_handler(GPIO_TypeDef* GPIOx, uint32_t port_num);
bogdanm 0:9b334a45a8ff 50
bogdanm 0:9b334a45a8ff 51 void PORT0_Handler(void)
bogdanm 0:9b334a45a8ff 52 {
bogdanm 0:9b334a45a8ff 53 port_generic_handler(GPIOA, 0);
bogdanm 0:9b334a45a8ff 54 }
bogdanm 0:9b334a45a8ff 55
bogdanm 0:9b334a45a8ff 56 void PORT1_Handler(void)
bogdanm 0:9b334a45a8ff 57 {
bogdanm 0:9b334a45a8ff 58 port_generic_handler(GPIOB, 1);
bogdanm 0:9b334a45a8ff 59 }
bogdanm 0:9b334a45a8ff 60
bogdanm 0:9b334a45a8ff 61 void PORT2_Handler(void)
bogdanm 0:9b334a45a8ff 62 {
bogdanm 0:9b334a45a8ff 63 port_generic_handler(GPIOC, 2);
bogdanm 0:9b334a45a8ff 64 }
bogdanm 0:9b334a45a8ff 65
bogdanm 0:9b334a45a8ff 66 void PORT3_Handler(void)
bogdanm 0:9b334a45a8ff 67 {
bogdanm 0:9b334a45a8ff 68 port_generic_handler(GPIOD, 3);
bogdanm 0:9b334a45a8ff 69 }
bogdanm 0:9b334a45a8ff 70
bogdanm 0:9b334a45a8ff 71 void port_generic_handler(GPIO_TypeDef* GPIOx, uint32_t port_num)
bogdanm 0:9b334a45a8ff 72 {
bogdanm 0:9b334a45a8ff 73 int i = 0;
bogdanm 0:9b334a45a8ff 74 int loop = 16;
bogdanm 0:9b334a45a8ff 75
bogdanm 0:9b334a45a8ff 76 if(GPIOx == GPIOD) loop = 5;
bogdanm 0:9b334a45a8ff 77
bogdanm 0:9b334a45a8ff 78 for(i=0; i<loop; i++)
bogdanm 0:9b334a45a8ff 79 {
bogdanm 0:9b334a45a8ff 80 if(GPIOx->Interrupt.INTSTATUS & (1 << i))
bogdanm 0:9b334a45a8ff 81 {
bogdanm 0:9b334a45a8ff 82 GPIOx->Interrupt.INTCLEAR |= (1 << i);
bogdanm 0:9b334a45a8ff 83 if(GPIOx->INTPOLSET >> i) //rising
bogdanm 0:9b334a45a8ff 84 irq_handler(channel_ids[port_num][i], IRQ_RISE);
bogdanm 0:9b334a45a8ff 85 else //falling
bogdanm 0:9b334a45a8ff 86 irq_handler(channel_ids[port_num][i], IRQ_FALL);
bogdanm 0:9b334a45a8ff 87 }
bogdanm 0:9b334a45a8ff 88 }
bogdanm 0:9b334a45a8ff 89 }
bogdanm 0:9b334a45a8ff 90
bogdanm 0:9b334a45a8ff 91 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 92 }
bogdanm 0:9b334a45a8ff 93 #endif
bogdanm 0:9b334a45a8ff 94
bogdanm 0:9b334a45a8ff 95
bogdanm 0:9b334a45a8ff 96 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
bogdanm 0:9b334a45a8ff 97 {
bogdanm 0:9b334a45a8ff 98 obj->port_num = WIZ_PORT(pin);
bogdanm 0:9b334a45a8ff 99 obj->pin_num = WIZ_PIN_NUM(pin);
bogdanm 0:9b334a45a8ff 100 obj->pin_index = WIZ_PIN_INDEX(pin);
bogdanm 0:9b334a45a8ff 101
bogdanm 0:9b334a45a8ff 102 if (pin == NC) return -1;
bogdanm 0:9b334a45a8ff 103
bogdanm 0:9b334a45a8ff 104 if(obj->port_num == 0)
bogdanm 0:9b334a45a8ff 105 obj->irq_n = PORT0_IRQn;
bogdanm 0:9b334a45a8ff 106 else if(obj->port_num == 1)
bogdanm 0:9b334a45a8ff 107 obj->irq_n = PORT1_IRQn;
bogdanm 0:9b334a45a8ff 108 else if(obj->port_num == 2)
bogdanm 0:9b334a45a8ff 109 obj->irq_n = PORT2_IRQn;
bogdanm 0:9b334a45a8ff 110 else
bogdanm 0:9b334a45a8ff 111 obj->irq_n = PORT3_IRQn;
bogdanm 0:9b334a45a8ff 112
bogdanm 0:9b334a45a8ff 113 //obj->event = EDGE_FALL;
bogdanm 0:9b334a45a8ff 114 obj->pin = pin;
bogdanm 0:9b334a45a8ff 115
bogdanm 0:9b334a45a8ff 116 // Enable EXTI interrupt
bogdanm 0:9b334a45a8ff 117 NVIC_EnableIRQ(obj->irq_n);
bogdanm 0:9b334a45a8ff 118
bogdanm 0:9b334a45a8ff 119 channel_ids[obj->port_num][obj->pin_num] = id;
bogdanm 0:9b334a45a8ff 120
bogdanm 0:9b334a45a8ff 121 irq_handler = handler;
bogdanm 0:9b334a45a8ff 122
bogdanm 0:9b334a45a8ff 123 return 0;
bogdanm 0:9b334a45a8ff 124 }
bogdanm 0:9b334a45a8ff 125
bogdanm 0:9b334a45a8ff 126 void gpio_irq_free(gpio_irq_t *obj)
bogdanm 0:9b334a45a8ff 127 {
bogdanm 0:9b334a45a8ff 128 channel_ids[obj->port_num][obj->pin_num] = 0;
bogdanm 0:9b334a45a8ff 129
bogdanm 0:9b334a45a8ff 130 obj->event = EDGE_NONE;
bogdanm 0:9b334a45a8ff 131 }
bogdanm 0:9b334a45a8ff 132
bogdanm 0:9b334a45a8ff 133 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
bogdanm 0:9b334a45a8ff 134 {
bogdanm 0:9b334a45a8ff 135 GPIO_TypeDef *gpio = (GPIO_TypeDef *)Get_GPIO_BaseAddress(obj->port_num);
bogdanm 0:9b334a45a8ff 136
bogdanm 0:9b334a45a8ff 137 if (enable) {
bogdanm 0:9b334a45a8ff 138 if (event == IRQ_RISE) {
bogdanm 0:9b334a45a8ff 139 gpio->INTPOLSET |= obj->pin_index;
bogdanm 0:9b334a45a8ff 140 obj->event = EDGE_RISE;
bogdanm 0:9b334a45a8ff 141 obj->rise_null = 0;
bogdanm 0:9b334a45a8ff 142 }
bogdanm 0:9b334a45a8ff 143 else if (event == IRQ_FALL) {
bogdanm 0:9b334a45a8ff 144 gpio->INTPOLSET &= ~obj->pin_index;
bogdanm 0:9b334a45a8ff 145 obj->event = EDGE_FALL;
bogdanm 0:9b334a45a8ff 146 obj->fall_null = 0;
bogdanm 0:9b334a45a8ff 147 }
bogdanm 0:9b334a45a8ff 148 gpio->INTTYPESET |= obj->pin_index;
bogdanm 0:9b334a45a8ff 149 gpio->INTENSET |= obj->pin_index;
bogdanm 0:9b334a45a8ff 150
bogdanm 0:9b334a45a8ff 151
bogdanm 0:9b334a45a8ff 152 } else {
bogdanm 0:9b334a45a8ff 153 if (event == IRQ_RISE) {
bogdanm 0:9b334a45a8ff 154 obj->rise_null = 1;
bogdanm 0:9b334a45a8ff 155 if(obj->fall_null)
bogdanm 0:9b334a45a8ff 156 gpio->INTENCLR |= obj->pin_index;
bogdanm 0:9b334a45a8ff 157 }
bogdanm 0:9b334a45a8ff 158 else if (event == IRQ_FALL) {
bogdanm 0:9b334a45a8ff 159 obj->fall_null = 1;
bogdanm 0:9b334a45a8ff 160 if(obj->rise_null)
bogdanm 0:9b334a45a8ff 161 gpio->INTENCLR |= obj->pin_index;
bogdanm 0:9b334a45a8ff 162 }
bogdanm 0:9b334a45a8ff 163 }
bogdanm 0:9b334a45a8ff 164 }
bogdanm 0:9b334a45a8ff 165
bogdanm 0:9b334a45a8ff 166 void gpio_irq_enable(gpio_irq_t *obj)
bogdanm 0:9b334a45a8ff 167 {
bogdanm 0:9b334a45a8ff 168 NVIC_EnableIRQ(obj->irq_n);
bogdanm 0:9b334a45a8ff 169 }
bogdanm 0:9b334a45a8ff 170
bogdanm 0:9b334a45a8ff 171 void gpio_irq_disable(gpio_irq_t *obj)
bogdanm 0:9b334a45a8ff 172 {
bogdanm 0:9b334a45a8ff 173 NVIC_DisableIRQ(obj->irq_n);
bogdanm 0:9b334a45a8ff 174 obj->event = EDGE_NONE;
bogdanm 0:9b334a45a8ff 175 }