mbed library sources. Supersedes mbed-src.
Fork of mbed-dev by
targets/hal/TARGET_NXP/TARGET_LPC13XX/gpio_irq_api.c@0:9b334a45a8ff, 2015-10-01 (annotated)
- Committer:
- bogdanm
- Date:
- Thu Oct 01 15:25:22 2015 +0300
- Revision:
- 0:9b334a45a8ff
- Child:
- 144:ef7eb2e8f9f7
Initial commit on mbed-dev
Replaces mbed-src (now inactive)
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
bogdanm | 0:9b334a45a8ff | 1 | /* mbed Microcontroller Library |
bogdanm | 0:9b334a45a8ff | 2 | * Copyright (c) 2006-2013 ARM Limited |
bogdanm | 0:9b334a45a8ff | 3 | * |
bogdanm | 0:9b334a45a8ff | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
bogdanm | 0:9b334a45a8ff | 5 | * you may not use this file except in compliance with the License. |
bogdanm | 0:9b334a45a8ff | 6 | * You may obtain a copy of the License at |
bogdanm | 0:9b334a45a8ff | 7 | * |
bogdanm | 0:9b334a45a8ff | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
bogdanm | 0:9b334a45a8ff | 9 | * |
bogdanm | 0:9b334a45a8ff | 10 | * Unless required by applicable law or agreed to in writing, software |
bogdanm | 0:9b334a45a8ff | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
bogdanm | 0:9b334a45a8ff | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
bogdanm | 0:9b334a45a8ff | 13 | * See the License for the specific language governing permissions and |
bogdanm | 0:9b334a45a8ff | 14 | * limitations under the License. |
bogdanm | 0:9b334a45a8ff | 15 | */ |
bogdanm | 0:9b334a45a8ff | 16 | #include <stddef.h> |
bogdanm | 0:9b334a45a8ff | 17 | #include "cmsis.h" |
bogdanm | 0:9b334a45a8ff | 18 | #include "gpio_irq_api.h" |
bogdanm | 0:9b334a45a8ff | 19 | #include "mbed_error.h" |
bogdanm | 0:9b334a45a8ff | 20 | |
bogdanm | 0:9b334a45a8ff | 21 | #define CHANNEL_NUM 8 |
bogdanm | 0:9b334a45a8ff | 22 | #define LPC_GPIO_X LPC_GPIO_PIN_INT |
bogdanm | 0:9b334a45a8ff | 23 | #define PININT_IRQ 0 |
bogdanm | 0:9b334a45a8ff | 24 | |
bogdanm | 0:9b334a45a8ff | 25 | static uint32_t channel_ids[CHANNEL_NUM] = {0}; |
bogdanm | 0:9b334a45a8ff | 26 | static gpio_irq_handler irq_handler; |
bogdanm | 0:9b334a45a8ff | 27 | |
bogdanm | 0:9b334a45a8ff | 28 | static inline void handle_interrupt_in(uint32_t channel) { |
bogdanm | 0:9b334a45a8ff | 29 | uint32_t ch_bit = (1 << channel); |
bogdanm | 0:9b334a45a8ff | 30 | // Return immediately if: |
bogdanm | 0:9b334a45a8ff | 31 | // * The interrupt was already served |
bogdanm | 0:9b334a45a8ff | 32 | // * There is no user handler |
bogdanm | 0:9b334a45a8ff | 33 | // * It is a level interrupt, not an edge interrupt |
bogdanm | 0:9b334a45a8ff | 34 | if ( ((LPC_GPIO_X->IST & ch_bit) == 0) || |
bogdanm | 0:9b334a45a8ff | 35 | (channel_ids[channel] == 0 ) || |
bogdanm | 0:9b334a45a8ff | 36 | (LPC_GPIO_X->ISEL & ch_bit ) ) return; |
bogdanm | 0:9b334a45a8ff | 37 | |
bogdanm | 0:9b334a45a8ff | 38 | if ((LPC_GPIO_X->IENR & ch_bit) && (LPC_GPIO_X->RISE & ch_bit)) { |
bogdanm | 0:9b334a45a8ff | 39 | irq_handler(channel_ids[channel], IRQ_RISE); |
bogdanm | 0:9b334a45a8ff | 40 | LPC_GPIO_X->RISE = ch_bit; |
bogdanm | 0:9b334a45a8ff | 41 | } |
bogdanm | 0:9b334a45a8ff | 42 | if ((LPC_GPIO_X->IENF & ch_bit) && (LPC_GPIO_X->FALL & ch_bit)) { |
bogdanm | 0:9b334a45a8ff | 43 | irq_handler(channel_ids[channel], IRQ_FALL); |
bogdanm | 0:9b334a45a8ff | 44 | } |
bogdanm | 0:9b334a45a8ff | 45 | LPC_GPIO_X->IST = ch_bit; |
bogdanm | 0:9b334a45a8ff | 46 | } |
bogdanm | 0:9b334a45a8ff | 47 | |
bogdanm | 0:9b334a45a8ff | 48 | void gpio_irq0(void) {handle_interrupt_in(0);} |
bogdanm | 0:9b334a45a8ff | 49 | void gpio_irq1(void) {handle_interrupt_in(1);} |
bogdanm | 0:9b334a45a8ff | 50 | void gpio_irq2(void) {handle_interrupt_in(2);} |
bogdanm | 0:9b334a45a8ff | 51 | void gpio_irq3(void) {handle_interrupt_in(3);} |
bogdanm | 0:9b334a45a8ff | 52 | void gpio_irq4(void) {handle_interrupt_in(4);} |
bogdanm | 0:9b334a45a8ff | 53 | void gpio_irq5(void) {handle_interrupt_in(5);} |
bogdanm | 0:9b334a45a8ff | 54 | void gpio_irq6(void) {handle_interrupt_in(6);} |
bogdanm | 0:9b334a45a8ff | 55 | void gpio_irq7(void) {handle_interrupt_in(7);} |
bogdanm | 0:9b334a45a8ff | 56 | |
bogdanm | 0:9b334a45a8ff | 57 | int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) { |
bogdanm | 0:9b334a45a8ff | 58 | if (pin == NC) return -1; |
bogdanm | 0:9b334a45a8ff | 59 | |
bogdanm | 0:9b334a45a8ff | 60 | irq_handler = handler; |
bogdanm | 0:9b334a45a8ff | 61 | |
bogdanm | 0:9b334a45a8ff | 62 | int found_free_channel = 0; |
bogdanm | 0:9b334a45a8ff | 63 | int i = 0; |
bogdanm | 0:9b334a45a8ff | 64 | for (i=0; i<CHANNEL_NUM; i++) { |
bogdanm | 0:9b334a45a8ff | 65 | if (channel_ids[i] == 0) { |
bogdanm | 0:9b334a45a8ff | 66 | channel_ids[i] = id; |
bogdanm | 0:9b334a45a8ff | 67 | obj->ch = i; |
bogdanm | 0:9b334a45a8ff | 68 | found_free_channel = 1; |
bogdanm | 0:9b334a45a8ff | 69 | break; |
bogdanm | 0:9b334a45a8ff | 70 | } |
bogdanm | 0:9b334a45a8ff | 71 | } |
bogdanm | 0:9b334a45a8ff | 72 | if (!found_free_channel) return -1; |
bogdanm | 0:9b334a45a8ff | 73 | |
bogdanm | 0:9b334a45a8ff | 74 | /* Enable AHB clock to the GPIO domain. */ |
bogdanm | 0:9b334a45a8ff | 75 | LPC_SYSCON->SYSAHBCLKCTRL |= (1<<6); |
bogdanm | 0:9b334a45a8ff | 76 | |
bogdanm | 0:9b334a45a8ff | 77 | /* Enable AHB clock to the FlexInt, GroupedInt domain. */ |
bogdanm | 0:9b334a45a8ff | 78 | LPC_SYSCON->SYSAHBCLKCTRL |= ((1<<19) | (1<<23) | (1<<24)); |
bogdanm | 0:9b334a45a8ff | 79 | |
bogdanm | 0:9b334a45a8ff | 80 | /* To select a pin for any of the eight pin interrupts, write the pin number |
bogdanm | 0:9b334a45a8ff | 81 | * as 0 to 23 for pins PIO0_0 to PIO0_23 and 24 to 55. |
bogdanm | 0:9b334a45a8ff | 82 | * @see: mbed_capi/PinNames.h |
bogdanm | 0:9b334a45a8ff | 83 | */ |
bogdanm | 0:9b334a45a8ff | 84 | LPC_SYSCON->PINSEL[obj->ch] = (pin >> 5) ? (pin - 8) : (pin); |
bogdanm | 0:9b334a45a8ff | 85 | |
bogdanm | 0:9b334a45a8ff | 86 | // Interrupt Wake-Up Enable |
bogdanm | 0:9b334a45a8ff | 87 | LPC_SYSCON->STARTERP0 |= 1 << obj->ch; |
bogdanm | 0:9b334a45a8ff | 88 | |
bogdanm | 0:9b334a45a8ff | 89 | void (*channels_irq)(void) = NULL; |
bogdanm | 0:9b334a45a8ff | 90 | switch (obj->ch) { |
bogdanm | 0:9b334a45a8ff | 91 | case 0: channels_irq = &gpio_irq0; break; |
bogdanm | 0:9b334a45a8ff | 92 | case 1: channels_irq = &gpio_irq1; break; |
bogdanm | 0:9b334a45a8ff | 93 | case 2: channels_irq = &gpio_irq2; break; |
bogdanm | 0:9b334a45a8ff | 94 | case 3: channels_irq = &gpio_irq3; break; |
bogdanm | 0:9b334a45a8ff | 95 | case 4: channels_irq = &gpio_irq4; break; |
bogdanm | 0:9b334a45a8ff | 96 | case 5: channels_irq = &gpio_irq5; break; |
bogdanm | 0:9b334a45a8ff | 97 | case 6: channels_irq = &gpio_irq6; break; |
bogdanm | 0:9b334a45a8ff | 98 | case 7: channels_irq = &gpio_irq7; break; |
bogdanm | 0:9b334a45a8ff | 99 | } |
bogdanm | 0:9b334a45a8ff | 100 | NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq); |
bogdanm | 0:9b334a45a8ff | 101 | NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch)); |
bogdanm | 0:9b334a45a8ff | 102 | |
bogdanm | 0:9b334a45a8ff | 103 | return 0; |
bogdanm | 0:9b334a45a8ff | 104 | } |
bogdanm | 0:9b334a45a8ff | 105 | |
bogdanm | 0:9b334a45a8ff | 106 | void gpio_irq_free(gpio_irq_t *obj) { |
bogdanm | 0:9b334a45a8ff | 107 | channel_ids[obj->ch] = 0; |
bogdanm | 0:9b334a45a8ff | 108 | LPC_SYSCON->STARTERP0 &= ~(1 << obj->ch); |
bogdanm | 0:9b334a45a8ff | 109 | } |
bogdanm | 0:9b334a45a8ff | 110 | |
bogdanm | 0:9b334a45a8ff | 111 | void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) { |
bogdanm | 0:9b334a45a8ff | 112 | unsigned int ch_bit = (1 << obj->ch); |
bogdanm | 0:9b334a45a8ff | 113 | |
bogdanm | 0:9b334a45a8ff | 114 | // Clear interrupt |
bogdanm | 0:9b334a45a8ff | 115 | if (!(LPC_GPIO_X->ISEL & ch_bit)) |
bogdanm | 0:9b334a45a8ff | 116 | LPC_GPIO_X->IST = ch_bit; |
bogdanm | 0:9b334a45a8ff | 117 | |
bogdanm | 0:9b334a45a8ff | 118 | // Edge trigger |
bogdanm | 0:9b334a45a8ff | 119 | LPC_GPIO_X->ISEL &= ~ch_bit; |
bogdanm | 0:9b334a45a8ff | 120 | if (event == IRQ_RISE) { |
bogdanm | 0:9b334a45a8ff | 121 | if (enable) { |
bogdanm | 0:9b334a45a8ff | 122 | LPC_GPIO_X->IENR |= ch_bit; |
bogdanm | 0:9b334a45a8ff | 123 | } else { |
bogdanm | 0:9b334a45a8ff | 124 | LPC_GPIO_X->IENR &= ~ch_bit; |
bogdanm | 0:9b334a45a8ff | 125 | } |
bogdanm | 0:9b334a45a8ff | 126 | } else { |
bogdanm | 0:9b334a45a8ff | 127 | if (enable) { |
bogdanm | 0:9b334a45a8ff | 128 | LPC_GPIO_X->IENF |= ch_bit; |
bogdanm | 0:9b334a45a8ff | 129 | } else { |
bogdanm | 0:9b334a45a8ff | 130 | LPC_GPIO_X->IENF &= ~ch_bit; |
bogdanm | 0:9b334a45a8ff | 131 | } |
bogdanm | 0:9b334a45a8ff | 132 | } |
bogdanm | 0:9b334a45a8ff | 133 | } |
bogdanm | 0:9b334a45a8ff | 134 | |
bogdanm | 0:9b334a45a8ff | 135 | void gpio_irq_enable(gpio_irq_t *obj) { |
bogdanm | 0:9b334a45a8ff | 136 | NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch)); |
bogdanm | 0:9b334a45a8ff | 137 | } |
bogdanm | 0:9b334a45a8ff | 138 | |
bogdanm | 0:9b334a45a8ff | 139 | void gpio_irq_disable(gpio_irq_t *obj) { |
bogdanm | 0:9b334a45a8ff | 140 | NVIC_DisableIRQ((IRQn_Type)(PININT_IRQ + obj->ch)); |
bogdanm | 0:9b334a45a8ff | 141 | } |
bogdanm | 0:9b334a45a8ff | 142 |