Fawwaz Nadzmy / mbed-STM

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_NXP/TARGET_LPC23XX/system_LPC23xx.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /* mbed Microcontroller Library
bogdanm 0:9b334a45a8ff 2 * Copyright (C) 2008-2009 ARM Limited. All rights reserved.
bogdanm 0:9b334a45a8ff 3 *
bogdanm 0:9b334a45a8ff 4 * ARM7 version of CMSIS-like functionality - not advised for use outside mbed!
bogdanm 0:9b334a45a8ff 5 */
bogdanm 0:9b334a45a8ff 6
bogdanm 0:9b334a45a8ff 7 #include <stdint.h>
bogdanm 0:9b334a45a8ff 8 #include "LPC23xx.h"
bogdanm 0:9b334a45a8ff 9
bogdanm 0:9b334a45a8ff 10 #define CLOCK_SETUP 1
bogdanm 0:9b334a45a8ff 11 #define SCS_Val 0x00000020
bogdanm 0:9b334a45a8ff 12 #define CLKSRCSEL_Val 0x00000001
bogdanm 0:9b334a45a8ff 13
bogdanm 0:9b334a45a8ff 14 #define PLL0_SETUP 1
bogdanm 0:9b334a45a8ff 15 #define PLL0CFG_Val 0x00000013
bogdanm 0:9b334a45a8ff 16 #define CCLKCFG_Val 0x00000007
bogdanm 0:9b334a45a8ff 17 #define USBCLKCFG_Val 0x00000009
bogdanm 0:9b334a45a8ff 18 #define PCLKSEL0_Val 0x00000000
bogdanm 0:9b334a45a8ff 19 #define PCLKSEL1_Val 0x00000000
bogdanm 0:9b334a45a8ff 20 #define PCONP_Val 0x042887DE
bogdanm 0:9b334a45a8ff 21 #define CLKOUTCFG_Val 0x00000000
bogdanm 0:9b334a45a8ff 22 #define MAMCR_Val 0x00000001 // there is a bug in the MAM so it should never be fully enabled (only disabled or partially enabled)
bogdanm 0:9b334a45a8ff 23 #define MAMTIM_Val 0x00000004
bogdanm 0:9b334a45a8ff 24
bogdanm 0:9b334a45a8ff 25 /*----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 26 DEFINES
bogdanm 0:9b334a45a8ff 27 *----------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 28
bogdanm 0:9b334a45a8ff 29 #define XTAL (12000000UL) /* Oscillator frequency */
bogdanm 0:9b334a45a8ff 30 #define OSC_CLK ( XTAL) /* Main oscillator frequency */
bogdanm 0:9b334a45a8ff 31 #define RTC_CLK ( 32000UL) /* RTC oscillator frequency */
bogdanm 0:9b334a45a8ff 32 #define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */
bogdanm 0:9b334a45a8ff 33
bogdanm 0:9b334a45a8ff 34 /* F_cco0 = (2 * M * F_in) / N */
bogdanm 0:9b334a45a8ff 35 #define __M (((PLL0CFG_Val ) & 0x7FFF) + 1)
bogdanm 0:9b334a45a8ff 36 #define __N (((PLL0CFG_Val >> 16) & 0x00FF) + 1)
bogdanm 0:9b334a45a8ff 37 #define __FCCO(__F_IN) ((2 * __M * __F_IN) / __N)
bogdanm 0:9b334a45a8ff 38 #define __CCLK_DIV (((CCLKCFG_Val ) & 0x00FF) + 1)
bogdanm 0:9b334a45a8ff 39
bogdanm 0:9b334a45a8ff 40 /* Determine core clock frequency according to settings */
bogdanm 0:9b334a45a8ff 41 #if (PLL0_SETUP)
bogdanm 0:9b334a45a8ff 42 #if ((CLKSRCSEL_Val & 0x03) == 1)
bogdanm 0:9b334a45a8ff 43 #define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV)
bogdanm 0:9b334a45a8ff 44 #elif ((CLKSRCSEL_Val & 0x03) == 2)
bogdanm 0:9b334a45a8ff 45 #define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV)
bogdanm 0:9b334a45a8ff 46 #else
bogdanm 0:9b334a45a8ff 47 #define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV)
bogdanm 0:9b334a45a8ff 48 #endif
bogdanm 0:9b334a45a8ff 49 #endif
bogdanm 0:9b334a45a8ff 50
bogdanm 0:9b334a45a8ff 51
bogdanm 0:9b334a45a8ff 52 /*----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 53 Clock Variable definitions
bogdanm 0:9b334a45a8ff 54 *----------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 55 uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/
bogdanm 0:9b334a45a8ff 56
bogdanm 0:9b334a45a8ff 57 /*----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 58 Clock functions
bogdanm 0:9b334a45a8ff 59 *----------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 60 void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
bogdanm 0:9b334a45a8ff 61 {
bogdanm 0:9b334a45a8ff 62 /* Determine clock frequency according to clock register values */
bogdanm 0:9b334a45a8ff 63 if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */
bogdanm 0:9b334a45a8ff 64 switch (LPC_SC->CLKSRCSEL & 0x03) {
bogdanm 0:9b334a45a8ff 65 case 0: /* Int. RC oscillator => PLL0 */
bogdanm 0:9b334a45a8ff 66 case 3: /* Reserved, default to Int. RC */
bogdanm 0:9b334a45a8ff 67 SystemCoreClock = (IRC_OSC *
bogdanm 0:9b334a45a8ff 68 (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
bogdanm 0:9b334a45a8ff 69 (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)) /
bogdanm 0:9b334a45a8ff 70 ((LPC_SC->CCLKCFG & 0xFF)+ 1));
bogdanm 0:9b334a45a8ff 71 break;
bogdanm 0:9b334a45a8ff 72 case 1: /* Main oscillator => PLL0 */
bogdanm 0:9b334a45a8ff 73 SystemCoreClock = (OSC_CLK *
bogdanm 0:9b334a45a8ff 74 (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
bogdanm 0:9b334a45a8ff 75 (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)) /
bogdanm 0:9b334a45a8ff 76 ((LPC_SC->CCLKCFG & 0xFF)+ 1));
bogdanm 0:9b334a45a8ff 77 break;
bogdanm 0:9b334a45a8ff 78 case 2: /* RTC oscillator => PLL0 */
bogdanm 0:9b334a45a8ff 79 SystemCoreClock = (RTC_CLK *
bogdanm 0:9b334a45a8ff 80 (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
bogdanm 0:9b334a45a8ff 81 (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)) /
bogdanm 0:9b334a45a8ff 82 ((LPC_SC->CCLKCFG & 0xFF)+ 1));
bogdanm 0:9b334a45a8ff 83 break;
bogdanm 0:9b334a45a8ff 84 }
bogdanm 0:9b334a45a8ff 85 } else {
bogdanm 0:9b334a45a8ff 86 switch (LPC_SC->CLKSRCSEL & 0x03) {
bogdanm 0:9b334a45a8ff 87 case 0: /* Int. RC oscillator => PLL0 */
bogdanm 0:9b334a45a8ff 88 case 3: /* Reserved, default to Int. RC */
bogdanm 0:9b334a45a8ff 89 SystemCoreClock = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
bogdanm 0:9b334a45a8ff 90 break;
bogdanm 0:9b334a45a8ff 91 case 1: /* Main oscillator => PLL0 */
bogdanm 0:9b334a45a8ff 92 SystemCoreClock = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
bogdanm 0:9b334a45a8ff 93 break;
bogdanm 0:9b334a45a8ff 94 case 2: /* RTC oscillator => PLL0 */
bogdanm 0:9b334a45a8ff 95 SystemCoreClock = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
bogdanm 0:9b334a45a8ff 96 break;
bogdanm 0:9b334a45a8ff 97 }
bogdanm 0:9b334a45a8ff 98 }
bogdanm 0:9b334a45a8ff 99 }
bogdanm 0:9b334a45a8ff 100
bogdanm 0:9b334a45a8ff 101 /**
bogdanm 0:9b334a45a8ff 102 * Initialize the system
bogdanm 0:9b334a45a8ff 103 *
bogdanm 0:9b334a45a8ff 104 * @param none
bogdanm 0:9b334a45a8ff 105 * @return none
bogdanm 0:9b334a45a8ff 106 *
bogdanm 0:9b334a45a8ff 107 * @brief Setup the microcontroller system.
bogdanm 0:9b334a45a8ff 108 * Initialize the System and update the SystemFrequency variable.
bogdanm 0:9b334a45a8ff 109 */
bogdanm 0:9b334a45a8ff 110 void SystemInit (void)
bogdanm 0:9b334a45a8ff 111 {
bogdanm 0:9b334a45a8ff 112 #if (CLOCK_SETUP) /* Clock Setup */
bogdanm 0:9b334a45a8ff 113 LPC_SC->SCS = SCS_Val;
bogdanm 0:9b334a45a8ff 114 if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */
bogdanm 0:9b334a45a8ff 115 while ((LPC_SC->SCS & (1 << 6)) == 0); /* Wait for Oscillator to be ready */
bogdanm 0:9b334a45a8ff 116 }
bogdanm 0:9b334a45a8ff 117
bogdanm 0:9b334a45a8ff 118 LPC_SC->CCLKCFG = CCLKCFG_Val; /* Setup Clock Divider */
bogdanm 0:9b334a45a8ff 119
bogdanm 0:9b334a45a8ff 120 #if (PLL0_SETUP)
bogdanm 0:9b334a45a8ff 121 LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for PLL0 */
bogdanm 0:9b334a45a8ff 122 LPC_SC->PLL0CFG = PLL0CFG_Val;
bogdanm 0:9b334a45a8ff 123 LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */
bogdanm 0:9b334a45a8ff 124 LPC_SC->PLL0FEED = 0xAA;
bogdanm 0:9b334a45a8ff 125 LPC_SC->PLL0FEED = 0x55;
bogdanm 0:9b334a45a8ff 126 while (!(LPC_SC->PLL0STAT & (1 << 26))); /* Wait for PLOCK0 */
bogdanm 0:9b334a45a8ff 127
bogdanm 0:9b334a45a8ff 128 LPC_SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */
bogdanm 0:9b334a45a8ff 129 LPC_SC->PLL0FEED = 0xAA;
bogdanm 0:9b334a45a8ff 130 LPC_SC->PLL0FEED = 0x55;
bogdanm 0:9b334a45a8ff 131 #endif
bogdanm 0:9b334a45a8ff 132
bogdanm 0:9b334a45a8ff 133 LPC_SC->USBCLKCFG = USBCLKCFG_Val; /* Setup USB Clock Divider */
bogdanm 0:9b334a45a8ff 134 #endif
bogdanm 0:9b334a45a8ff 135
bogdanm 0:9b334a45a8ff 136 LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */
bogdanm 0:9b334a45a8ff 137 LPC_SC->PCLKSEL1 = PCLKSEL1_Val;
bogdanm 0:9b334a45a8ff 138
bogdanm 0:9b334a45a8ff 139 LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */
bogdanm 0:9b334a45a8ff 140
bogdanm 0:9b334a45a8ff 141 // Setup MAM
bogdanm 0:9b334a45a8ff 142 LPC_SC->MAMTIM = MAMTIM_Val;
bogdanm 0:9b334a45a8ff 143 LPC_SC->MAMCR = MAMCR_Val;
bogdanm 0:9b334a45a8ff 144 }