Fawwaz Nadzmy / mbed-STM

mbed library sources. Supersedes mbed-src.

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targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_vcmp.h@153:9398a535854b, 2016-12-22 (annotated)

Committer:
fwndz
Date:
Thu Dec 22 05:12:40 2016 +0000
Revision:
153:9398a535854b
Parent:
150:02e0a0aed4ec 
device target maximize

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 150:02e0a0aed4ec 1 /**************************************************************************//**
<> 150:02e0a0aed4ec 2 * @file efm32wg_vcmp.h
<> 150:02e0a0aed4ec 3 * @brief EFM32WG_VCMP register and bit field definitions
<> 150:02e0a0aed4ec 4 * @version 5.0.0
<> 150:02e0a0aed4ec 5 ******************************************************************************
<> 150:02e0a0aed4ec 6 * @section License
<> 150:02e0a0aed4ec 7 * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 150:02e0a0aed4ec 8 ******************************************************************************
<> 150:02e0a0aed4ec 9 *
<> 150:02e0a0aed4ec 10 * Permission is granted to anyone to use this software for any purpose,
<> 150:02e0a0aed4ec 11 * including commercial applications, and to alter it and redistribute it
<> 150:02e0a0aed4ec 12 * freely, subject to the following restrictions:
<> 150:02e0a0aed4ec 13 *
<> 150:02e0a0aed4ec 14 * 1. The origin of this software must not be misrepresented; you must not
<> 150:02e0a0aed4ec 15 * claim that you wrote the original software.@n
<> 150:02e0a0aed4ec 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 150:02e0a0aed4ec 17 * misrepresented as being the original software.@n
<> 150:02e0a0aed4ec 18 * 3. This notice may not be removed or altered from any source distribution.
<> 150:02e0a0aed4ec 19 *
<> 150:02e0a0aed4ec 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 150:02e0a0aed4ec 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 150:02e0a0aed4ec 22 * providing the Software "AS IS", with no express or implied warranties of any
<> 150:02e0a0aed4ec 23 * kind, including, but not limited to, any implied warranties of
<> 150:02e0a0aed4ec 24 * merchantability or fitness for any particular purpose or warranties against
<> 150:02e0a0aed4ec 25 * infringement of any proprietary rights of a third party.
<> 150:02e0a0aed4ec 26 *
<> 150:02e0a0aed4ec 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 150:02e0a0aed4ec 28 * incidental, or special damages, or any other relief, or for any claim by
<> 150:02e0a0aed4ec 29 * any third party, arising from your use of this Software.
<> 150:02e0a0aed4ec 30 *
<> 150:02e0a0aed4ec 31 *****************************************************************************/
<> 150:02e0a0aed4ec 32 /**************************************************************************//**
<> 150:02e0a0aed4ec 33 * @addtogroup Parts
<> 150:02e0a0aed4ec 34 * @{
<> 150:02e0a0aed4ec 35 ******************************************************************************/
<> 150:02e0a0aed4ec 36 /**************************************************************************//**
<> 150:02e0a0aed4ec 37 * @defgroup EFM32WG_VCMP
<> 150:02e0a0aed4ec 38 * @{
<> 150:02e0a0aed4ec 39 * @brief EFM32WG_VCMP Register Declaration
<> 150:02e0a0aed4ec 40 *****************************************************************************/
<> 150:02e0a0aed4ec 41 typedef struct
<> 150:02e0a0aed4ec 42 {
<> 150:02e0a0aed4ec 43 __IOM uint32_t CTRL; /**< Control Register */
<> 150:02e0a0aed4ec 44 __IOM uint32_t INPUTSEL; /**< Input Selection Register */
<> 150:02e0a0aed4ec 45 __IM uint32_t STATUS; /**< Status Register */
<> 150:02e0a0aed4ec 46 __IOM uint32_t IEN; /**< Interrupt Enable Register */
<> 150:02e0a0aed4ec 47 __IM uint32_t IF; /**< Interrupt Flag Register */
<> 150:02e0a0aed4ec 48 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
<> 150:02e0a0aed4ec 49 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
<> 150:02e0a0aed4ec 50 } VCMP_TypeDef; /** @} */
<> 150:02e0a0aed4ec 51
<> 150:02e0a0aed4ec 52 /**************************************************************************//**
<> 150:02e0a0aed4ec 53 * @defgroup EFM32WG_VCMP_BitFields
<> 150:02e0a0aed4ec 54 * @{
<> 150:02e0a0aed4ec 55 *****************************************************************************/
<> 150:02e0a0aed4ec 56
<> 150:02e0a0aed4ec 57 /* Bit fields for VCMP CTRL */
<> 150:02e0a0aed4ec 58 #define _VCMP_CTRL_RESETVALUE 0x47000000UL /**< Default value for VCMP_CTRL */
<> 150:02e0a0aed4ec 59 #define _VCMP_CTRL_MASK 0x4F030715UL /**< Mask for VCMP_CTRL */
<> 150:02e0a0aed4ec 60 #define VCMP_CTRL_EN (0x1UL << 0) /**< Voltage Supply Comparator Enable */
<> 150:02e0a0aed4ec 61 #define _VCMP_CTRL_EN_SHIFT 0 /**< Shift value for VCMP_EN */
<> 150:02e0a0aed4ec 62 #define _VCMP_CTRL_EN_MASK 0x1UL /**< Bit mask for VCMP_EN */
<> 150:02e0a0aed4ec 63 #define _VCMP_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_CTRL */
<> 150:02e0a0aed4ec 64 #define VCMP_CTRL_EN_DEFAULT (_VCMP_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for VCMP_CTRL */
<> 150:02e0a0aed4ec 65 #define VCMP_CTRL_INACTVAL (0x1UL << 2) /**< Inactive Value */
<> 150:02e0a0aed4ec 66 #define _VCMP_CTRL_INACTVAL_SHIFT 2 /**< Shift value for VCMP_INACTVAL */
<> 150:02e0a0aed4ec 67 #define _VCMP_CTRL_INACTVAL_MASK 0x4UL /**< Bit mask for VCMP_INACTVAL */
<> 150:02e0a0aed4ec 68 #define _VCMP_CTRL_INACTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_CTRL */
<> 150:02e0a0aed4ec 69 #define VCMP_CTRL_INACTVAL_DEFAULT (_VCMP_CTRL_INACTVAL_DEFAULT << 2) /**< Shifted mode DEFAULT for VCMP_CTRL */
<> 150:02e0a0aed4ec 70 #define VCMP_CTRL_HYSTEN (0x1UL << 4) /**< Hysteresis Enable */
<> 150:02e0a0aed4ec 71 #define _VCMP_CTRL_HYSTEN_SHIFT 4 /**< Shift value for VCMP_HYSTEN */
<> 150:02e0a0aed4ec 72 #define _VCMP_CTRL_HYSTEN_MASK 0x10UL /**< Bit mask for VCMP_HYSTEN */
<> 150:02e0a0aed4ec 73 #define _VCMP_CTRL_HYSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_CTRL */
<> 150:02e0a0aed4ec 74 #define VCMP_CTRL_HYSTEN_DEFAULT (_VCMP_CTRL_HYSTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for VCMP_CTRL */
<> 150:02e0a0aed4ec 75 #define _VCMP_CTRL_WARMTIME_SHIFT 8 /**< Shift value for VCMP_WARMTIME */
<> 150:02e0a0aed4ec 76 #define _VCMP_CTRL_WARMTIME_MASK 0x700UL /**< Bit mask for VCMP_WARMTIME */
<> 150:02e0a0aed4ec 77 #define _VCMP_CTRL_WARMTIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_CTRL */
<> 150:02e0a0aed4ec 78 #define _VCMP_CTRL_WARMTIME_4CYCLES 0x00000000UL /**< Mode 4CYCLES for VCMP_CTRL */
<> 150:02e0a0aed4ec 79 #define _VCMP_CTRL_WARMTIME_8CYCLES 0x00000001UL /**< Mode 8CYCLES for VCMP_CTRL */
<> 150:02e0a0aed4ec 80 #define _VCMP_CTRL_WARMTIME_16CYCLES 0x00000002UL /**< Mode 16CYCLES for VCMP_CTRL */
<> 150:02e0a0aed4ec 81 #define _VCMP_CTRL_WARMTIME_32CYCLES 0x00000003UL /**< Mode 32CYCLES for VCMP_CTRL */
<> 150:02e0a0aed4ec 82 #define _VCMP_CTRL_WARMTIME_64CYCLES 0x00000004UL /**< Mode 64CYCLES for VCMP_CTRL */
<> 150:02e0a0aed4ec 83 #define _VCMP_CTRL_WARMTIME_128CYCLES 0x00000005UL /**< Mode 128CYCLES for VCMP_CTRL */
<> 150:02e0a0aed4ec 84 #define _VCMP_CTRL_WARMTIME_256CYCLES 0x00000006UL /**< Mode 256CYCLES for VCMP_CTRL */
<> 150:02e0a0aed4ec 85 #define _VCMP_CTRL_WARMTIME_512CYCLES 0x00000007UL /**< Mode 512CYCLES for VCMP_CTRL */
<> 150:02e0a0aed4ec 86 #define VCMP_CTRL_WARMTIME_DEFAULT (_VCMP_CTRL_WARMTIME_DEFAULT << 8) /**< Shifted mode DEFAULT for VCMP_CTRL */
<> 150:02e0a0aed4ec 87 #define VCMP_CTRL_WARMTIME_4CYCLES (_VCMP_CTRL_WARMTIME_4CYCLES << 8) /**< Shifted mode 4CYCLES for VCMP_CTRL */
<> 150:02e0a0aed4ec 88 #define VCMP_CTRL_WARMTIME_8CYCLES (_VCMP_CTRL_WARMTIME_8CYCLES << 8) /**< Shifted mode 8CYCLES for VCMP_CTRL */
<> 150:02e0a0aed4ec 89 #define VCMP_CTRL_WARMTIME_16CYCLES (_VCMP_CTRL_WARMTIME_16CYCLES << 8) /**< Shifted mode 16CYCLES for VCMP_CTRL */
<> 150:02e0a0aed4ec 90 #define VCMP_CTRL_WARMTIME_32CYCLES (_VCMP_CTRL_WARMTIME_32CYCLES << 8) /**< Shifted mode 32CYCLES for VCMP_CTRL */
<> 150:02e0a0aed4ec 91 #define VCMP_CTRL_WARMTIME_64CYCLES (_VCMP_CTRL_WARMTIME_64CYCLES << 8) /**< Shifted mode 64CYCLES for VCMP_CTRL */
<> 150:02e0a0aed4ec 92 #define VCMP_CTRL_WARMTIME_128CYCLES (_VCMP_CTRL_WARMTIME_128CYCLES << 8) /**< Shifted mode 128CYCLES for VCMP_CTRL */
<> 150:02e0a0aed4ec 93 #define VCMP_CTRL_WARMTIME_256CYCLES (_VCMP_CTRL_WARMTIME_256CYCLES << 8) /**< Shifted mode 256CYCLES for VCMP_CTRL */
<> 150:02e0a0aed4ec 94 #define VCMP_CTRL_WARMTIME_512CYCLES (_VCMP_CTRL_WARMTIME_512CYCLES << 8) /**< Shifted mode 512CYCLES for VCMP_CTRL */
<> 150:02e0a0aed4ec 95 #define VCMP_CTRL_IRISE (0x1UL << 16) /**< Rising Edge Interrupt Sense */
<> 150:02e0a0aed4ec 96 #define _VCMP_CTRL_IRISE_SHIFT 16 /**< Shift value for VCMP_IRISE */
<> 150:02e0a0aed4ec 97 #define _VCMP_CTRL_IRISE_MASK 0x10000UL /**< Bit mask for VCMP_IRISE */
<> 150:02e0a0aed4ec 98 #define _VCMP_CTRL_IRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_CTRL */
<> 150:02e0a0aed4ec 99 #define VCMP_CTRL_IRISE_DEFAULT (_VCMP_CTRL_IRISE_DEFAULT << 16) /**< Shifted mode DEFAULT for VCMP_CTRL */
<> 150:02e0a0aed4ec 100 #define VCMP_CTRL_IFALL (0x1UL << 17) /**< Falling Edge Interrupt Sense */
<> 150:02e0a0aed4ec 101 #define _VCMP_CTRL_IFALL_SHIFT 17 /**< Shift value for VCMP_IFALL */
<> 150:02e0a0aed4ec 102 #define _VCMP_CTRL_IFALL_MASK 0x20000UL /**< Bit mask for VCMP_IFALL */
<> 150:02e0a0aed4ec 103 #define _VCMP_CTRL_IFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_CTRL */
<> 150:02e0a0aed4ec 104 #define VCMP_CTRL_IFALL_DEFAULT (_VCMP_CTRL_IFALL_DEFAULT << 17) /**< Shifted mode DEFAULT for VCMP_CTRL */
<> 150:02e0a0aed4ec 105 #define _VCMP_CTRL_BIASPROG_SHIFT 24 /**< Shift value for VCMP_BIASPROG */
<> 150:02e0a0aed4ec 106 #define _VCMP_CTRL_BIASPROG_MASK 0xF000000UL /**< Bit mask for VCMP_BIASPROG */
<> 150:02e0a0aed4ec 107 #define _VCMP_CTRL_BIASPROG_DEFAULT 0x00000007UL /**< Mode DEFAULT for VCMP_CTRL */
<> 150:02e0a0aed4ec 108 #define VCMP_CTRL_BIASPROG_DEFAULT (_VCMP_CTRL_BIASPROG_DEFAULT << 24) /**< Shifted mode DEFAULT for VCMP_CTRL */
<> 150:02e0a0aed4ec 109 #define VCMP_CTRL_HALFBIAS (0x1UL << 30) /**< Half Bias Current */
<> 150:02e0a0aed4ec 110 #define _VCMP_CTRL_HALFBIAS_SHIFT 30 /**< Shift value for VCMP_HALFBIAS */
<> 150:02e0a0aed4ec 111 #define _VCMP_CTRL_HALFBIAS_MASK 0x40000000UL /**< Bit mask for VCMP_HALFBIAS */
<> 150:02e0a0aed4ec 112 #define _VCMP_CTRL_HALFBIAS_DEFAULT 0x00000001UL /**< Mode DEFAULT for VCMP_CTRL */
<> 150:02e0a0aed4ec 113 #define VCMP_CTRL_HALFBIAS_DEFAULT (_VCMP_CTRL_HALFBIAS_DEFAULT << 30) /**< Shifted mode DEFAULT for VCMP_CTRL */
<> 150:02e0a0aed4ec 114
<> 150:02e0a0aed4ec 115 /* Bit fields for VCMP INPUTSEL */
<> 150:02e0a0aed4ec 116 #define _VCMP_INPUTSEL_RESETVALUE 0x00000000UL /**< Default value for VCMP_INPUTSEL */
<> 150:02e0a0aed4ec 117 #define _VCMP_INPUTSEL_MASK 0x0000013FUL /**< Mask for VCMP_INPUTSEL */
<> 150:02e0a0aed4ec 118 #define _VCMP_INPUTSEL_TRIGLEVEL_SHIFT 0 /**< Shift value for VCMP_TRIGLEVEL */
<> 150:02e0a0aed4ec 119 #define _VCMP_INPUTSEL_TRIGLEVEL_MASK 0x3FUL /**< Bit mask for VCMP_TRIGLEVEL */
<> 150:02e0a0aed4ec 120 #define _VCMP_INPUTSEL_TRIGLEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_INPUTSEL */
<> 150:02e0a0aed4ec 121 #define VCMP_INPUTSEL_TRIGLEVEL_DEFAULT (_VCMP_INPUTSEL_TRIGLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for VCMP_INPUTSEL */
<> 150:02e0a0aed4ec 122 #define VCMP_INPUTSEL_LPREF (0x1UL << 8) /**< Low Power Reference */
<> 150:02e0a0aed4ec 123 #define _VCMP_INPUTSEL_LPREF_SHIFT 8 /**< Shift value for VCMP_LPREF */
<> 150:02e0a0aed4ec 124 #define _VCMP_INPUTSEL_LPREF_MASK 0x100UL /**< Bit mask for VCMP_LPREF */
<> 150:02e0a0aed4ec 125 #define _VCMP_INPUTSEL_LPREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_INPUTSEL */
<> 150:02e0a0aed4ec 126 #define VCMP_INPUTSEL_LPREF_DEFAULT (_VCMP_INPUTSEL_LPREF_DEFAULT << 8) /**< Shifted mode DEFAULT for VCMP_INPUTSEL */
<> 150:02e0a0aed4ec 127
<> 150:02e0a0aed4ec 128 /* Bit fields for VCMP STATUS */
<> 150:02e0a0aed4ec 129 #define _VCMP_STATUS_RESETVALUE 0x00000000UL /**< Default value for VCMP_STATUS */
<> 150:02e0a0aed4ec 130 #define _VCMP_STATUS_MASK 0x00000003UL /**< Mask for VCMP_STATUS */
<> 150:02e0a0aed4ec 131 #define VCMP_STATUS_VCMPACT (0x1UL << 0) /**< Voltage Supply Comparator Active */
<> 150:02e0a0aed4ec 132 #define _VCMP_STATUS_VCMPACT_SHIFT 0 /**< Shift value for VCMP_VCMPACT */
<> 150:02e0a0aed4ec 133 #define _VCMP_STATUS_VCMPACT_MASK 0x1UL /**< Bit mask for VCMP_VCMPACT */
<> 150:02e0a0aed4ec 134 #define _VCMP_STATUS_VCMPACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_STATUS */
<> 150:02e0a0aed4ec 135 #define VCMP_STATUS_VCMPACT_DEFAULT (_VCMP_STATUS_VCMPACT_DEFAULT << 0) /**< Shifted mode DEFAULT for VCMP_STATUS */
<> 150:02e0a0aed4ec 136 #define VCMP_STATUS_VCMPOUT (0x1UL << 1) /**< Voltage Supply Comparator Output */
<> 150:02e0a0aed4ec 137 #define _VCMP_STATUS_VCMPOUT_SHIFT 1 /**< Shift value for VCMP_VCMPOUT */
<> 150:02e0a0aed4ec 138 #define _VCMP_STATUS_VCMPOUT_MASK 0x2UL /**< Bit mask for VCMP_VCMPOUT */
<> 150:02e0a0aed4ec 139 #define _VCMP_STATUS_VCMPOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_STATUS */
<> 150:02e0a0aed4ec 140 #define VCMP_STATUS_VCMPOUT_DEFAULT (_VCMP_STATUS_VCMPOUT_DEFAULT << 1) /**< Shifted mode DEFAULT for VCMP_STATUS */
<> 150:02e0a0aed4ec 141
<> 150:02e0a0aed4ec 142 /* Bit fields for VCMP IEN */
<> 150:02e0a0aed4ec 143 #define _VCMP_IEN_RESETVALUE 0x00000000UL /**< Default value for VCMP_IEN */
<> 150:02e0a0aed4ec 144 #define _VCMP_IEN_MASK 0x00000003UL /**< Mask for VCMP_IEN */
<> 150:02e0a0aed4ec 145 #define VCMP_IEN_EDGE (0x1UL << 0) /**< Edge Trigger Interrupt Enable */
<> 150:02e0a0aed4ec 146 #define _VCMP_IEN_EDGE_SHIFT 0 /**< Shift value for VCMP_EDGE */
<> 150:02e0a0aed4ec 147 #define _VCMP_IEN_EDGE_MASK 0x1UL /**< Bit mask for VCMP_EDGE */
<> 150:02e0a0aed4ec 148 #define _VCMP_IEN_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IEN */
<> 150:02e0a0aed4ec 149 #define VCMP_IEN_EDGE_DEFAULT (_VCMP_IEN_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for VCMP_IEN */
<> 150:02e0a0aed4ec 150 #define VCMP_IEN_WARMUP (0x1UL << 1) /**< Warm-up Interrupt Enable */
<> 150:02e0a0aed4ec 151 #define _VCMP_IEN_WARMUP_SHIFT 1 /**< Shift value for VCMP_WARMUP */
<> 150:02e0a0aed4ec 152 #define _VCMP_IEN_WARMUP_MASK 0x2UL /**< Bit mask for VCMP_WARMUP */
<> 150:02e0a0aed4ec 153 #define _VCMP_IEN_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IEN */
<> 150:02e0a0aed4ec 154 #define VCMP_IEN_WARMUP_DEFAULT (_VCMP_IEN_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for VCMP_IEN */
<> 150:02e0a0aed4ec 155
<> 150:02e0a0aed4ec 156 /* Bit fields for VCMP IF */
<> 150:02e0a0aed4ec 157 #define _VCMP_IF_RESETVALUE 0x00000000UL /**< Default value for VCMP_IF */
<> 150:02e0a0aed4ec 158 #define _VCMP_IF_MASK 0x00000003UL /**< Mask for VCMP_IF */
<> 150:02e0a0aed4ec 159 #define VCMP_IF_EDGE (0x1UL << 0) /**< Edge Triggered Interrupt Flag */
<> 150:02e0a0aed4ec 160 #define _VCMP_IF_EDGE_SHIFT 0 /**< Shift value for VCMP_EDGE */
<> 150:02e0a0aed4ec 161 #define _VCMP_IF_EDGE_MASK 0x1UL /**< Bit mask for VCMP_EDGE */
<> 150:02e0a0aed4ec 162 #define _VCMP_IF_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IF */
<> 150:02e0a0aed4ec 163 #define VCMP_IF_EDGE_DEFAULT (_VCMP_IF_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for VCMP_IF */
<> 150:02e0a0aed4ec 164 #define VCMP_IF_WARMUP (0x1UL << 1) /**< Warm-up Interrupt Flag */
<> 150:02e0a0aed4ec 165 #define _VCMP_IF_WARMUP_SHIFT 1 /**< Shift value for VCMP_WARMUP */
<> 150:02e0a0aed4ec 166 #define _VCMP_IF_WARMUP_MASK 0x2UL /**< Bit mask for VCMP_WARMUP */
<> 150:02e0a0aed4ec 167 #define _VCMP_IF_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IF */
<> 150:02e0a0aed4ec 168 #define VCMP_IF_WARMUP_DEFAULT (_VCMP_IF_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for VCMP_IF */
<> 150:02e0a0aed4ec 169
<> 150:02e0a0aed4ec 170 /* Bit fields for VCMP IFS */
<> 150:02e0a0aed4ec 171 #define _VCMP_IFS_RESETVALUE 0x00000000UL /**< Default value for VCMP_IFS */
<> 150:02e0a0aed4ec 172 #define _VCMP_IFS_MASK 0x00000003UL /**< Mask for VCMP_IFS */
<> 150:02e0a0aed4ec 173 #define VCMP_IFS_EDGE (0x1UL << 0) /**< Edge Triggered Interrupt Flag Set */
<> 150:02e0a0aed4ec 174 #define _VCMP_IFS_EDGE_SHIFT 0 /**< Shift value for VCMP_EDGE */
<> 150:02e0a0aed4ec 175 #define _VCMP_IFS_EDGE_MASK 0x1UL /**< Bit mask for VCMP_EDGE */
<> 150:02e0a0aed4ec 176 #define _VCMP_IFS_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IFS */
<> 150:02e0a0aed4ec 177 #define VCMP_IFS_EDGE_DEFAULT (_VCMP_IFS_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for VCMP_IFS */
<> 150:02e0a0aed4ec 178 #define VCMP_IFS_WARMUP (0x1UL << 1) /**< Warm-up Interrupt Flag Set */
<> 150:02e0a0aed4ec 179 #define _VCMP_IFS_WARMUP_SHIFT 1 /**< Shift value for VCMP_WARMUP */
<> 150:02e0a0aed4ec 180 #define _VCMP_IFS_WARMUP_MASK 0x2UL /**< Bit mask for VCMP_WARMUP */
<> 150:02e0a0aed4ec 181 #define _VCMP_IFS_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IFS */
<> 150:02e0a0aed4ec 182 #define VCMP_IFS_WARMUP_DEFAULT (_VCMP_IFS_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for VCMP_IFS */
<> 150:02e0a0aed4ec 183
<> 150:02e0a0aed4ec 184 /* Bit fields for VCMP IFC */
<> 150:02e0a0aed4ec 185 #define _VCMP_IFC_RESETVALUE 0x00000000UL /**< Default value for VCMP_IFC */
<> 150:02e0a0aed4ec 186 #define _VCMP_IFC_MASK 0x00000003UL /**< Mask for VCMP_IFC */
<> 150:02e0a0aed4ec 187 #define VCMP_IFC_EDGE (0x1UL << 0) /**< Edge Triggered Interrupt Flag Clear */
<> 150:02e0a0aed4ec 188 #define _VCMP_IFC_EDGE_SHIFT 0 /**< Shift value for VCMP_EDGE */
<> 150:02e0a0aed4ec 189 #define _VCMP_IFC_EDGE_MASK 0x1UL /**< Bit mask for VCMP_EDGE */
<> 150:02e0a0aed4ec 190 #define _VCMP_IFC_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IFC */
<> 150:02e0a0aed4ec 191 #define VCMP_IFC_EDGE_DEFAULT (_VCMP_IFC_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for VCMP_IFC */
<> 150:02e0a0aed4ec 192 #define VCMP_IFC_WARMUP (0x1UL << 1) /**< Warm-up Interrupt Flag Clear */
<> 150:02e0a0aed4ec 193 #define _VCMP_IFC_WARMUP_SHIFT 1 /**< Shift value for VCMP_WARMUP */
<> 150:02e0a0aed4ec 194 #define _VCMP_IFC_WARMUP_MASK 0x2UL /**< Bit mask for VCMP_WARMUP */
<> 150:02e0a0aed4ec 195 #define _VCMP_IFC_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IFC */
<> 150:02e0a0aed4ec 196 #define VCMP_IFC_WARMUP_DEFAULT (_VCMP_IFC_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for VCMP_IFC */
<> 150:02e0a0aed4ec 197
<> 150:02e0a0aed4ec 198 /** @} End of group EFM32WG_VCMP */
<> 150:02e0a0aed4ec 199 /** @} End of group Parts */
<> 150:02e0a0aed4ec 200