Fawwaz Nadzmy / mbed-STM

mbed library sources. Supersedes mbed-src.

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targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_usb.h@153:9398a535854b, 2016-12-22 (annotated)

Committer:
fwndz
Date:
Thu Dec 22 05:12:40 2016 +0000
Revision:
153:9398a535854b
Parent:
150:02e0a0aed4ec 
device target maximize

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 150:02e0a0aed4ec 1 /**************************************************************************//**
<> 150:02e0a0aed4ec 2 * @file efm32wg_usb.h
<> 150:02e0a0aed4ec 3 * @brief EFM32WG_USB register and bit field definitions
<> 150:02e0a0aed4ec 4 * @version 5.0.0
<> 150:02e0a0aed4ec 5 ******************************************************************************
<> 150:02e0a0aed4ec 6 * @section License
<> 150:02e0a0aed4ec 7 * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 150:02e0a0aed4ec 8 ******************************************************************************
<> 150:02e0a0aed4ec 9 *
<> 150:02e0a0aed4ec 10 * Permission is granted to anyone to use this software for any purpose,
<> 150:02e0a0aed4ec 11 * including commercial applications, and to alter it and redistribute it
<> 150:02e0a0aed4ec 12 * freely, subject to the following restrictions:
<> 150:02e0a0aed4ec 13 *
<> 150:02e0a0aed4ec 14 * 1. The origin of this software must not be misrepresented; you must not
<> 150:02e0a0aed4ec 15 * claim that you wrote the original software.@n
<> 150:02e0a0aed4ec 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 150:02e0a0aed4ec 17 * misrepresented as being the original software.@n
<> 150:02e0a0aed4ec 18 * 3. This notice may not be removed or altered from any source distribution.
<> 150:02e0a0aed4ec 19 *
<> 150:02e0a0aed4ec 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 150:02e0a0aed4ec 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 150:02e0a0aed4ec 22 * providing the Software "AS IS", with no express or implied warranties of any
<> 150:02e0a0aed4ec 23 * kind, including, but not limited to, any implied warranties of
<> 150:02e0a0aed4ec 24 * merchantability or fitness for any particular purpose or warranties against
<> 150:02e0a0aed4ec 25 * infringement of any proprietary rights of a third party.
<> 150:02e0a0aed4ec 26 *
<> 150:02e0a0aed4ec 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 150:02e0a0aed4ec 28 * incidental, or special damages, or any other relief, or for any claim by
<> 150:02e0a0aed4ec 29 * any third party, arising from your use of this Software.
<> 150:02e0a0aed4ec 30 *
<> 150:02e0a0aed4ec 31 *****************************************************************************/
<> 150:02e0a0aed4ec 32 /**************************************************************************//**
<> 150:02e0a0aed4ec 33 * @addtogroup Parts
<> 150:02e0a0aed4ec 34 * @{
<> 150:02e0a0aed4ec 35 ******************************************************************************/
<> 150:02e0a0aed4ec 36 /**************************************************************************//**
<> 150:02e0a0aed4ec 37 * @defgroup EFM32WG_USB
<> 150:02e0a0aed4ec 38 * @{
<> 150:02e0a0aed4ec 39 * @brief EFM32WG_USB Register Declaration
<> 150:02e0a0aed4ec 40 *****************************************************************************/
<> 150:02e0a0aed4ec 41 typedef struct
<> 150:02e0a0aed4ec 42 {
<> 150:02e0a0aed4ec 43 __IOM uint32_t CTRL; /**< System Control Register */
<> 150:02e0a0aed4ec 44 __IM uint32_t STATUS; /**< System Status Register */
<> 150:02e0a0aed4ec 45 __IM uint32_t IF; /**< Interrupt Flag Register */
<> 150:02e0a0aed4ec 46 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
<> 150:02e0a0aed4ec 47 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
<> 150:02e0a0aed4ec 48 __IOM uint32_t IEN; /**< Interrupt Enable Register */
<> 150:02e0a0aed4ec 49 __IOM uint32_t ROUTE; /**< I/O Routing Register */
<> 150:02e0a0aed4ec 50
<> 150:02e0a0aed4ec 51 uint32_t RESERVED0[61433]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 52 __IOM uint32_t GOTGCTL; /**< OTG Control and Status Register */
<> 150:02e0a0aed4ec 53 __IOM uint32_t GOTGINT; /**< OTG Interrupt Register */
<> 150:02e0a0aed4ec 54 __IOM uint32_t GAHBCFG; /**< AHB Configuration Register */
<> 150:02e0a0aed4ec 55 __IOM uint32_t GUSBCFG; /**< USB Configuration Register */
<> 150:02e0a0aed4ec 56 __IOM uint32_t GRSTCTL; /**< Reset Register */
<> 150:02e0a0aed4ec 57 __IOM uint32_t GINTSTS; /**< Interrupt Register */
<> 150:02e0a0aed4ec 58 __IOM uint32_t GINTMSK; /**< Interrupt Mask Register */
<> 150:02e0a0aed4ec 59 __IM uint32_t GRXSTSR; /**< Receive Status Debug Read Register */
<> 150:02e0a0aed4ec 60 __IM uint32_t GRXSTSP; /**< Receive Status Read and Pop Register */
<> 150:02e0a0aed4ec 61 __IOM uint32_t GRXFSIZ; /**< Receive FIFO Size Register */
<> 150:02e0a0aed4ec 62 __IOM uint32_t GNPTXFSIZ; /**< Non-periodic Transmit FIFO Size Register */
<> 150:02e0a0aed4ec 63 __IM uint32_t GNPTXSTS; /**< Non-periodic Transmit FIFO/Queue Status Register */
<> 150:02e0a0aed4ec 64 uint32_t RESERVED1[11]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 65 __IOM uint32_t GDFIFOCFG; /**< Global DFIFO Configuration Register */
<> 150:02e0a0aed4ec 66
<> 150:02e0a0aed4ec 67 uint32_t RESERVED2[40]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 68 __IOM uint32_t HPTXFSIZ; /**< Host Periodic Transmit FIFO Size Register */
<> 150:02e0a0aed4ec 69 __IOM uint32_t DIEPTXF1; /**< Device IN Endpoint Transmit FIFO 1 Size Register */
<> 150:02e0a0aed4ec 70 __IOM uint32_t DIEPTXF2; /**< Device IN Endpoint Transmit FIFO 2 Size Register */
<> 150:02e0a0aed4ec 71 __IOM uint32_t DIEPTXF3; /**< Device IN Endpoint Transmit FIFO 3 Size Register */
<> 150:02e0a0aed4ec 72 __IOM uint32_t DIEPTXF4; /**< Device IN Endpoint Transmit FIFO 4 Size Register */
<> 150:02e0a0aed4ec 73 __IOM uint32_t DIEPTXF5; /**< Device IN Endpoint Transmit FIFO 5 Size Register */
<> 150:02e0a0aed4ec 74 __IOM uint32_t DIEPTXF6; /**< Device IN Endpoint Transmit FIFO 6 Size Register */
<> 150:02e0a0aed4ec 75
<> 150:02e0a0aed4ec 76 uint32_t RESERVED3[185]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 77 __IOM uint32_t HCFG; /**< Host Configuration Register */
<> 150:02e0a0aed4ec 78 __IOM uint32_t HFIR; /**< Host Frame Interval Register */
<> 150:02e0a0aed4ec 79 __IM uint32_t HFNUM; /**< Host Frame Number/Frame Time Remaining Register */
<> 150:02e0a0aed4ec 80 uint32_t RESERVED4[1]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 81 __IM uint32_t HPTXSTS; /**< Host Periodic Transmit FIFO/Queue Status Register */
<> 150:02e0a0aed4ec 82 __IM uint32_t HAINT; /**< Host All Channels Interrupt Register */
<> 150:02e0a0aed4ec 83 __IOM uint32_t HAINTMSK; /**< Host All Channels Interrupt Mask Register */
<> 150:02e0a0aed4ec 84 uint32_t RESERVED5[9]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 85 __IOM uint32_t HPRT; /**< Host Port Control and Status Register */
<> 150:02e0a0aed4ec 86
<> 150:02e0a0aed4ec 87 uint32_t RESERVED6[47]; /**< Reserved registers */
<> 150:02e0a0aed4ec 88 USB_HC_TypeDef HC[14]; /**< Host Channel Registers */
<> 150:02e0a0aed4ec 89
<> 150:02e0a0aed4ec 90 uint32_t RESERVED7[80]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 91 __IOM uint32_t DCFG; /**< Device Configuration Register */
<> 150:02e0a0aed4ec 92 __IOM uint32_t DCTL; /**< Device Control Register */
<> 150:02e0a0aed4ec 93 __IM uint32_t DSTS; /**< Device Status Register */
<> 150:02e0a0aed4ec 94 uint32_t RESERVED8[1]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 95 __IOM uint32_t DIEPMSK; /**< Device IN Endpoint Common Interrupt Mask Register */
<> 150:02e0a0aed4ec 96 __IOM uint32_t DOEPMSK; /**< Device OUT Endpoint Common Interrupt Mask Register */
<> 150:02e0a0aed4ec 97 __IM uint32_t DAINT; /**< Device All Endpoints Interrupt Register */
<> 150:02e0a0aed4ec 98 __IOM uint32_t DAINTMSK; /**< Device All Endpoints Interrupt Mask Register */
<> 150:02e0a0aed4ec 99 uint32_t RESERVED9[2]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 100 __IOM uint32_t DVBUSDIS; /**< Device VBUS Discharge Time Register */
<> 150:02e0a0aed4ec 101 __IOM uint32_t DVBUSPULSE; /**< Device VBUS Pulsing Time Register */
<> 150:02e0a0aed4ec 102
<> 150:02e0a0aed4ec 103 uint32_t RESERVED10[1]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 104 __IOM uint32_t DIEPEMPMSK; /**< Device IN Endpoint FIFO Empty Interrupt Mask Register */
<> 150:02e0a0aed4ec 105
<> 150:02e0a0aed4ec 106 uint32_t RESERVED11[50]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 107 __IOM uint32_t DIEP0CTL; /**< Device IN Endpoint 0 Control Register */
<> 150:02e0a0aed4ec 108 uint32_t RESERVED12[1]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 109 __IOM uint32_t DIEP0INT; /**< Device IN Endpoint 0 Interrupt Register */
<> 150:02e0a0aed4ec 110 uint32_t RESERVED13[1]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 111 __IOM uint32_t DIEP0TSIZ; /**< Device IN Endpoint 0 Transfer Size Register */
<> 150:02e0a0aed4ec 112 __IOM uint32_t DIEP0DMAADDR; /**< Device IN Endpoint 0 DMA Address Register */
<> 150:02e0a0aed4ec 113 __IM uint32_t DIEP0TXFSTS; /**< Device IN Endpoint 0 Transmit FIFO Status Register */
<> 150:02e0a0aed4ec 114
<> 150:02e0a0aed4ec 115 uint32_t RESERVED14[1]; /**< Reserved registers */
<> 150:02e0a0aed4ec 116 USB_DIEP_TypeDef DIEP[6]; /**< Device IN Endpoint x+1 Registers */
<> 150:02e0a0aed4ec 117
<> 150:02e0a0aed4ec 118 uint32_t RESERVED15[72]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 119 __IOM uint32_t DOEP0CTL; /**< Device OUT Endpoint 0 Control Register */
<> 150:02e0a0aed4ec 120 uint32_t RESERVED16[1]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 121 __IOM uint32_t DOEP0INT; /**< Device OUT Endpoint 0 Interrupt Register */
<> 150:02e0a0aed4ec 122 uint32_t RESERVED17[1]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 123 __IOM uint32_t DOEP0TSIZ; /**< Device OUT Endpoint 0 Transfer Size Register */
<> 150:02e0a0aed4ec 124 __IOM uint32_t DOEP0DMAADDR; /**< Device OUT Endpoint 0 DMA Address Register */
<> 150:02e0a0aed4ec 125
<> 150:02e0a0aed4ec 126 uint32_t RESERVED18[2]; /**< Reserved registers */
<> 150:02e0a0aed4ec 127 USB_DOEP_TypeDef DOEP[6]; /**< Device OUT Endpoint x+1 Registers */
<> 150:02e0a0aed4ec 128
<> 150:02e0a0aed4ec 129 uint32_t RESERVED19[136]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 130 __IOM uint32_t PCGCCTL; /**< Power and Clock Gating Control Register */
<> 150:02e0a0aed4ec 131
<> 150:02e0a0aed4ec 132 uint32_t RESERVED20[127]; /**< Reserved registers */
<> 150:02e0a0aed4ec 133 __IOM uint32_t FIFO0D[512]; /**< Device EP 0/Host Channel 0 FIFO */
<> 150:02e0a0aed4ec 134
<> 150:02e0a0aed4ec 135 uint32_t RESERVED21[512]; /**< Reserved registers */
<> 150:02e0a0aed4ec 136 __IOM uint32_t FIFO1D[512]; /**< Device EP 1/Host Channel 1 FIFO */
<> 150:02e0a0aed4ec 137
<> 150:02e0a0aed4ec 138 uint32_t RESERVED22[512]; /**< Reserved registers */
<> 150:02e0a0aed4ec 139 __IOM uint32_t FIFO2D[512]; /**< Device EP 2/Host Channel 2 FIFO */
<> 150:02e0a0aed4ec 140
<> 150:02e0a0aed4ec 141 uint32_t RESERVED23[512]; /**< Reserved registers */
<> 150:02e0a0aed4ec 142 __IOM uint32_t FIFO3D[512]; /**< Device EP 3/Host Channel 3 FIFO */
<> 150:02e0a0aed4ec 143
<> 150:02e0a0aed4ec 144 uint32_t RESERVED24[512]; /**< Reserved registers */
<> 150:02e0a0aed4ec 145 __IOM uint32_t FIFO4D[512]; /**< Device EP 4/Host Channel 4 FIFO */
<> 150:02e0a0aed4ec 146
<> 150:02e0a0aed4ec 147 uint32_t RESERVED25[512]; /**< Reserved registers */
<> 150:02e0a0aed4ec 148 __IOM uint32_t FIFO5D[512]; /**< Device EP 5/Host Channel 5 FIFO */
<> 150:02e0a0aed4ec 149
<> 150:02e0a0aed4ec 150 uint32_t RESERVED26[512]; /**< Reserved registers */
<> 150:02e0a0aed4ec 151 __IOM uint32_t FIFO6D[512]; /**< Device EP 6/Host Channel 6 FIFO */
<> 150:02e0a0aed4ec 152
<> 150:02e0a0aed4ec 153 uint32_t RESERVED27[512]; /**< Reserved registers */
<> 150:02e0a0aed4ec 154 __IOM uint32_t FIFO7D[512]; /**< Host Channel 7 FIFO */
<> 150:02e0a0aed4ec 155
<> 150:02e0a0aed4ec 156 uint32_t RESERVED28[512]; /**< Reserved registers */
<> 150:02e0a0aed4ec 157 __IOM uint32_t FIFO8D[512]; /**< Host Channel 8 FIFO */
<> 150:02e0a0aed4ec 158
<> 150:02e0a0aed4ec 159 uint32_t RESERVED29[512]; /**< Reserved registers */
<> 150:02e0a0aed4ec 160 __IOM uint32_t FIFO9D[512]; /**< Host Channel 9 FIFO */
<> 150:02e0a0aed4ec 161
<> 150:02e0a0aed4ec 162 uint32_t RESERVED30[512]; /**< Reserved registers */
<> 150:02e0a0aed4ec 163 __IOM uint32_t FIFO10D[512]; /**< Host Channel 10 FIFO */
<> 150:02e0a0aed4ec 164
<> 150:02e0a0aed4ec 165 uint32_t RESERVED31[512]; /**< Reserved registers */
<> 150:02e0a0aed4ec 166 __IOM uint32_t FIFO11D[512]; /**< Host Channel 11 FIFO */
<> 150:02e0a0aed4ec 167
<> 150:02e0a0aed4ec 168 uint32_t RESERVED32[512]; /**< Reserved registers */
<> 150:02e0a0aed4ec 169 __IOM uint32_t FIFO12D[512]; /**< Host Channel 12 FIFO */
<> 150:02e0a0aed4ec 170
<> 150:02e0a0aed4ec 171 uint32_t RESERVED33[512]; /**< Reserved registers */
<> 150:02e0a0aed4ec 172 __IOM uint32_t FIFO13D[512]; /**< Host Channel 13 FIFO */
<> 150:02e0a0aed4ec 173
<> 150:02e0a0aed4ec 174 uint32_t RESERVED34[17920]; /**< Reserved registers */
<> 150:02e0a0aed4ec 175 __IOM uint32_t FIFORAM[512]; /**< Direct Access to Data FIFO RAM for Debugging (2 KB) */
<> 150:02e0a0aed4ec 176 } USB_TypeDef; /** @} */
<> 150:02e0a0aed4ec 177
<> 150:02e0a0aed4ec 178 /**************************************************************************//**
<> 150:02e0a0aed4ec 179 * @defgroup EFM32WG_USB_BitFields
<> 150:02e0a0aed4ec 180 * @{
<> 150:02e0a0aed4ec 181 *****************************************************************************/
<> 150:02e0a0aed4ec 182
<> 150:02e0a0aed4ec 183 /* Bit fields for USB CTRL */
<> 150:02e0a0aed4ec 184 #define _USB_CTRL_RESETVALUE 0x00000000UL /**< Default value for USB_CTRL */
<> 150:02e0a0aed4ec 185 #define _USB_CTRL_MASK 0x03330003UL /**< Mask for USB_CTRL */
<> 150:02e0a0aed4ec 186 #define USB_CTRL_VBUSENAP (0x1UL << 0) /**< VBUSEN Active Polarity */
<> 150:02e0a0aed4ec 187 #define _USB_CTRL_VBUSENAP_SHIFT 0 /**< Shift value for USB_VBUSENAP */
<> 150:02e0a0aed4ec 188 #define _USB_CTRL_VBUSENAP_MASK 0x1UL /**< Bit mask for USB_VBUSENAP */
<> 150:02e0a0aed4ec 189 #define _USB_CTRL_VBUSENAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_CTRL */
<> 150:02e0a0aed4ec 190 #define _USB_CTRL_VBUSENAP_LOW 0x00000000UL /**< Mode LOW for USB_CTRL */
<> 150:02e0a0aed4ec 191 #define _USB_CTRL_VBUSENAP_HIGH 0x00000001UL /**< Mode HIGH for USB_CTRL */
<> 150:02e0a0aed4ec 192 #define USB_CTRL_VBUSENAP_DEFAULT (_USB_CTRL_VBUSENAP_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_CTRL */
<> 150:02e0a0aed4ec 193 #define USB_CTRL_VBUSENAP_LOW (_USB_CTRL_VBUSENAP_LOW << 0) /**< Shifted mode LOW for USB_CTRL */
<> 150:02e0a0aed4ec 194 #define USB_CTRL_VBUSENAP_HIGH (_USB_CTRL_VBUSENAP_HIGH << 0) /**< Shifted mode HIGH for USB_CTRL */
<> 150:02e0a0aed4ec 195 #define USB_CTRL_DMPUAP (0x1UL << 1) /**< DMPU Active Polarity */
<> 150:02e0a0aed4ec 196 #define _USB_CTRL_DMPUAP_SHIFT 1 /**< Shift value for USB_DMPUAP */
<> 150:02e0a0aed4ec 197 #define _USB_CTRL_DMPUAP_MASK 0x2UL /**< Bit mask for USB_DMPUAP */
<> 150:02e0a0aed4ec 198 #define _USB_CTRL_DMPUAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_CTRL */
<> 150:02e0a0aed4ec 199 #define _USB_CTRL_DMPUAP_LOW 0x00000000UL /**< Mode LOW for USB_CTRL */
<> 150:02e0a0aed4ec 200 #define _USB_CTRL_DMPUAP_HIGH 0x00000001UL /**< Mode HIGH for USB_CTRL */
<> 150:02e0a0aed4ec 201 #define USB_CTRL_DMPUAP_DEFAULT (_USB_CTRL_DMPUAP_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_CTRL */
<> 150:02e0a0aed4ec 202 #define USB_CTRL_DMPUAP_LOW (_USB_CTRL_DMPUAP_LOW << 1) /**< Shifted mode LOW for USB_CTRL */
<> 150:02e0a0aed4ec 203 #define USB_CTRL_DMPUAP_HIGH (_USB_CTRL_DMPUAP_HIGH << 1) /**< Shifted mode HIGH for USB_CTRL */
<> 150:02e0a0aed4ec 204 #define USB_CTRL_VREGDIS (0x1UL << 16) /**< Voltage Regulator Disable */
<> 150:02e0a0aed4ec 205 #define _USB_CTRL_VREGDIS_SHIFT 16 /**< Shift value for USB_VREGDIS */
<> 150:02e0a0aed4ec 206 #define _USB_CTRL_VREGDIS_MASK 0x10000UL /**< Bit mask for USB_VREGDIS */
<> 150:02e0a0aed4ec 207 #define _USB_CTRL_VREGDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_CTRL */
<> 150:02e0a0aed4ec 208 #define USB_CTRL_VREGDIS_DEFAULT (_USB_CTRL_VREGDIS_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_CTRL */
<> 150:02e0a0aed4ec 209 #define USB_CTRL_VREGOSEN (0x1UL << 17) /**< VREGO Sense Enable */
<> 150:02e0a0aed4ec 210 #define _USB_CTRL_VREGOSEN_SHIFT 17 /**< Shift value for USB_VREGOSEN */
<> 150:02e0a0aed4ec 211 #define _USB_CTRL_VREGOSEN_MASK 0x20000UL /**< Bit mask for USB_VREGOSEN */
<> 150:02e0a0aed4ec 212 #define _USB_CTRL_VREGOSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_CTRL */
<> 150:02e0a0aed4ec 213 #define USB_CTRL_VREGOSEN_DEFAULT (_USB_CTRL_VREGOSEN_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_CTRL */
<> 150:02e0a0aed4ec 214 #define _USB_CTRL_BIASPROGEM01_SHIFT 20 /**< Shift value for USB_BIASPROGEM01 */
<> 150:02e0a0aed4ec 215 #define _USB_CTRL_BIASPROGEM01_MASK 0x300000UL /**< Bit mask for USB_BIASPROGEM01 */
<> 150:02e0a0aed4ec 216 #define _USB_CTRL_BIASPROGEM01_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_CTRL */
<> 150:02e0a0aed4ec 217 #define USB_CTRL_BIASPROGEM01_DEFAULT (_USB_CTRL_BIASPROGEM01_DEFAULT << 20) /**< Shifted mode DEFAULT for USB_CTRL */
<> 150:02e0a0aed4ec 218 #define _USB_CTRL_BIASPROGEM23_SHIFT 24 /**< Shift value for USB_BIASPROGEM23 */
<> 150:02e0a0aed4ec 219 #define _USB_CTRL_BIASPROGEM23_MASK 0x3000000UL /**< Bit mask for USB_BIASPROGEM23 */
<> 150:02e0a0aed4ec 220 #define _USB_CTRL_BIASPROGEM23_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_CTRL */
<> 150:02e0a0aed4ec 221 #define USB_CTRL_BIASPROGEM23_DEFAULT (_USB_CTRL_BIASPROGEM23_DEFAULT << 24) /**< Shifted mode DEFAULT for USB_CTRL */
<> 150:02e0a0aed4ec 222
<> 150:02e0a0aed4ec 223 /* Bit fields for USB STATUS */
<> 150:02e0a0aed4ec 224 #define _USB_STATUS_RESETVALUE 0x00000000UL /**< Default value for USB_STATUS */
<> 150:02e0a0aed4ec 225 #define _USB_STATUS_MASK 0x00000001UL /**< Mask for USB_STATUS */
<> 150:02e0a0aed4ec 226 #define USB_STATUS_VREGOS (0x1UL << 0) /**< VREGO Sense Output */
<> 150:02e0a0aed4ec 227 #define _USB_STATUS_VREGOS_SHIFT 0 /**< Shift value for USB_VREGOS */
<> 150:02e0a0aed4ec 228 #define _USB_STATUS_VREGOS_MASK 0x1UL /**< Bit mask for USB_VREGOS */
<> 150:02e0a0aed4ec 229 #define _USB_STATUS_VREGOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_STATUS */
<> 150:02e0a0aed4ec 230 #define USB_STATUS_VREGOS_DEFAULT (_USB_STATUS_VREGOS_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_STATUS */
<> 150:02e0a0aed4ec 231
<> 150:02e0a0aed4ec 232 /* Bit fields for USB IF */
<> 150:02e0a0aed4ec 233 #define _USB_IF_RESETVALUE 0x00000003UL /**< Default value for USB_IF */
<> 150:02e0a0aed4ec 234 #define _USB_IF_MASK 0x00000003UL /**< Mask for USB_IF */
<> 150:02e0a0aed4ec 235 #define USB_IF_VREGOSH (0x1UL << 0) /**< VREGO Sense High Interrupt Flag */
<> 150:02e0a0aed4ec 236 #define _USB_IF_VREGOSH_SHIFT 0 /**< Shift value for USB_VREGOSH */
<> 150:02e0a0aed4ec 237 #define _USB_IF_VREGOSH_MASK 0x1UL /**< Bit mask for USB_VREGOSH */
<> 150:02e0a0aed4ec 238 #define _USB_IF_VREGOSH_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_IF */
<> 150:02e0a0aed4ec 239 #define USB_IF_VREGOSH_DEFAULT (_USB_IF_VREGOSH_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_IF */
<> 150:02e0a0aed4ec 240 #define USB_IF_VREGOSL (0x1UL << 1) /**< VREGO Sense Low Interrupt Flag */
<> 150:02e0a0aed4ec 241 #define _USB_IF_VREGOSL_SHIFT 1 /**< Shift value for USB_VREGOSL */
<> 150:02e0a0aed4ec 242 #define _USB_IF_VREGOSL_MASK 0x2UL /**< Bit mask for USB_VREGOSL */
<> 150:02e0a0aed4ec 243 #define _USB_IF_VREGOSL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_IF */
<> 150:02e0a0aed4ec 244 #define USB_IF_VREGOSL_DEFAULT (_USB_IF_VREGOSL_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_IF */
<> 150:02e0a0aed4ec 245
<> 150:02e0a0aed4ec 246 /* Bit fields for USB IFS */
<> 150:02e0a0aed4ec 247 #define _USB_IFS_RESETVALUE 0x00000000UL /**< Default value for USB_IFS */
<> 150:02e0a0aed4ec 248 #define _USB_IFS_MASK 0x00000003UL /**< Mask for USB_IFS */
<> 150:02e0a0aed4ec 249 #define USB_IFS_VREGOSH (0x1UL << 0) /**< Set VREGO Sense High Interrupt Flag */
<> 150:02e0a0aed4ec 250 #define _USB_IFS_VREGOSH_SHIFT 0 /**< Shift value for USB_VREGOSH */
<> 150:02e0a0aed4ec 251 #define _USB_IFS_VREGOSH_MASK 0x1UL /**< Bit mask for USB_VREGOSH */
<> 150:02e0a0aed4ec 252 #define _USB_IFS_VREGOSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IFS */
<> 150:02e0a0aed4ec 253 #define USB_IFS_VREGOSH_DEFAULT (_USB_IFS_VREGOSH_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_IFS */
<> 150:02e0a0aed4ec 254 #define USB_IFS_VREGOSL (0x1UL << 1) /**< Set VREGO Sense Low Interrupt Flag */
<> 150:02e0a0aed4ec 255 #define _USB_IFS_VREGOSL_SHIFT 1 /**< Shift value for USB_VREGOSL */
<> 150:02e0a0aed4ec 256 #define _USB_IFS_VREGOSL_MASK 0x2UL /**< Bit mask for USB_VREGOSL */
<> 150:02e0a0aed4ec 257 #define _USB_IFS_VREGOSL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IFS */
<> 150:02e0a0aed4ec 258 #define USB_IFS_VREGOSL_DEFAULT (_USB_IFS_VREGOSL_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_IFS */
<> 150:02e0a0aed4ec 259
<> 150:02e0a0aed4ec 260 /* Bit fields for USB IFC */
<> 150:02e0a0aed4ec 261 #define _USB_IFC_RESETVALUE 0x00000000UL /**< Default value for USB_IFC */
<> 150:02e0a0aed4ec 262 #define _USB_IFC_MASK 0x00000003UL /**< Mask for USB_IFC */
<> 150:02e0a0aed4ec 263 #define USB_IFC_VREGOSH (0x1UL << 0) /**< Clear VREGO Sense High Interrupt Flag */
<> 150:02e0a0aed4ec 264 #define _USB_IFC_VREGOSH_SHIFT 0 /**< Shift value for USB_VREGOSH */
<> 150:02e0a0aed4ec 265 #define _USB_IFC_VREGOSH_MASK 0x1UL /**< Bit mask for USB_VREGOSH */
<> 150:02e0a0aed4ec 266 #define _USB_IFC_VREGOSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IFC */
<> 150:02e0a0aed4ec 267 #define USB_IFC_VREGOSH_DEFAULT (_USB_IFC_VREGOSH_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_IFC */
<> 150:02e0a0aed4ec 268 #define USB_IFC_VREGOSL (0x1UL << 1) /**< Clear VREGO Sense Low Interrupt Flag */
<> 150:02e0a0aed4ec 269 #define _USB_IFC_VREGOSL_SHIFT 1 /**< Shift value for USB_VREGOSL */
<> 150:02e0a0aed4ec 270 #define _USB_IFC_VREGOSL_MASK 0x2UL /**< Bit mask for USB_VREGOSL */
<> 150:02e0a0aed4ec 271 #define _USB_IFC_VREGOSL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IFC */
<> 150:02e0a0aed4ec 272 #define USB_IFC_VREGOSL_DEFAULT (_USB_IFC_VREGOSL_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_IFC */
<> 150:02e0a0aed4ec 273
<> 150:02e0a0aed4ec 274 /* Bit fields for USB IEN */
<> 150:02e0a0aed4ec 275 #define _USB_IEN_RESETVALUE 0x00000000UL /**< Default value for USB_IEN */
<> 150:02e0a0aed4ec 276 #define _USB_IEN_MASK 0x00000003UL /**< Mask for USB_IEN */
<> 150:02e0a0aed4ec 277 #define USB_IEN_VREGOSH (0x1UL << 0) /**< VREGO Sense High Interrupt Enable */
<> 150:02e0a0aed4ec 278 #define _USB_IEN_VREGOSH_SHIFT 0 /**< Shift value for USB_VREGOSH */
<> 150:02e0a0aed4ec 279 #define _USB_IEN_VREGOSH_MASK 0x1UL /**< Bit mask for USB_VREGOSH */
<> 150:02e0a0aed4ec 280 #define _USB_IEN_VREGOSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IEN */
<> 150:02e0a0aed4ec 281 #define USB_IEN_VREGOSH_DEFAULT (_USB_IEN_VREGOSH_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_IEN */
<> 150:02e0a0aed4ec 282 #define USB_IEN_VREGOSL (0x1UL << 1) /**< VREGO Sense Low Interrupt Enable */
<> 150:02e0a0aed4ec 283 #define _USB_IEN_VREGOSL_SHIFT 1 /**< Shift value for USB_VREGOSL */
<> 150:02e0a0aed4ec 284 #define _USB_IEN_VREGOSL_MASK 0x2UL /**< Bit mask for USB_VREGOSL */
<> 150:02e0a0aed4ec 285 #define _USB_IEN_VREGOSL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IEN */
<> 150:02e0a0aed4ec 286 #define USB_IEN_VREGOSL_DEFAULT (_USB_IEN_VREGOSL_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_IEN */
<> 150:02e0a0aed4ec 287
<> 150:02e0a0aed4ec 288 /* Bit fields for USB ROUTE */
<> 150:02e0a0aed4ec 289 #define _USB_ROUTE_RESETVALUE 0x00000000UL /**< Default value for USB_ROUTE */
<> 150:02e0a0aed4ec 290 #define _USB_ROUTE_MASK 0x00000007UL /**< Mask for USB_ROUTE */
<> 150:02e0a0aed4ec 291 #define USB_ROUTE_PHYPEN (0x1UL << 0) /**< USB PHY Pin Enable */
<> 150:02e0a0aed4ec 292 #define _USB_ROUTE_PHYPEN_SHIFT 0 /**< Shift value for USB_PHYPEN */
<> 150:02e0a0aed4ec 293 #define _USB_ROUTE_PHYPEN_MASK 0x1UL /**< Bit mask for USB_PHYPEN */
<> 150:02e0a0aed4ec 294 #define _USB_ROUTE_PHYPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_ROUTE */
<> 150:02e0a0aed4ec 295 #define USB_ROUTE_PHYPEN_DEFAULT (_USB_ROUTE_PHYPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_ROUTE */
<> 150:02e0a0aed4ec 296 #define USB_ROUTE_VBUSENPEN (0x1UL << 1) /**< VBUSEN Pin Enable */
<> 150:02e0a0aed4ec 297 #define _USB_ROUTE_VBUSENPEN_SHIFT 1 /**< Shift value for USB_VBUSENPEN */
<> 150:02e0a0aed4ec 298 #define _USB_ROUTE_VBUSENPEN_MASK 0x2UL /**< Bit mask for USB_VBUSENPEN */
<> 150:02e0a0aed4ec 299 #define _USB_ROUTE_VBUSENPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_ROUTE */
<> 150:02e0a0aed4ec 300 #define USB_ROUTE_VBUSENPEN_DEFAULT (_USB_ROUTE_VBUSENPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_ROUTE */
<> 150:02e0a0aed4ec 301 #define USB_ROUTE_DMPUPEN (0x1UL << 2) /**< DMPU Pin Enable */
<> 150:02e0a0aed4ec 302 #define _USB_ROUTE_DMPUPEN_SHIFT 2 /**< Shift value for USB_DMPUPEN */
<> 150:02e0a0aed4ec 303 #define _USB_ROUTE_DMPUPEN_MASK 0x4UL /**< Bit mask for USB_DMPUPEN */
<> 150:02e0a0aed4ec 304 #define _USB_ROUTE_DMPUPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_ROUTE */
<> 150:02e0a0aed4ec 305 #define USB_ROUTE_DMPUPEN_DEFAULT (_USB_ROUTE_DMPUPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_ROUTE */
<> 150:02e0a0aed4ec 306
<> 150:02e0a0aed4ec 307 /* Bit fields for USB GOTGCTL */
<> 150:02e0a0aed4ec 308 #define _USB_GOTGCTL_RESETVALUE 0x00010000UL /**< Default value for USB_GOTGCTL */
<> 150:02e0a0aed4ec 309 #define _USB_GOTGCTL_MASK 0x001F0FFFUL /**< Mask for USB_GOTGCTL */
<> 150:02e0a0aed4ec 310 #define USB_GOTGCTL_SESREQSCS (0x1UL << 0) /**< Session Request Success device only */
<> 150:02e0a0aed4ec 311 #define _USB_GOTGCTL_SESREQSCS_SHIFT 0 /**< Shift value for USB_SESREQSCS */
<> 150:02e0a0aed4ec 312 #define _USB_GOTGCTL_SESREQSCS_MASK 0x1UL /**< Bit mask for USB_SESREQSCS */
<> 150:02e0a0aed4ec 313 #define _USB_GOTGCTL_SESREQSCS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */
<> 150:02e0a0aed4ec 314 #define USB_GOTGCTL_SESREQSCS_DEFAULT (_USB_GOTGCTL_SESREQSCS_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GOTGCTL */
<> 150:02e0a0aed4ec 315 #define USB_GOTGCTL_SESREQ (0x1UL << 1) /**< Session Request device only */
<> 150:02e0a0aed4ec 316 #define _USB_GOTGCTL_SESREQ_SHIFT 1 /**< Shift value for USB_SESREQ */
<> 150:02e0a0aed4ec 317 #define _USB_GOTGCTL_SESREQ_MASK 0x2UL /**< Bit mask for USB_SESREQ */
<> 150:02e0a0aed4ec 318 #define _USB_GOTGCTL_SESREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */
<> 150:02e0a0aed4ec 319 #define USB_GOTGCTL_SESREQ_DEFAULT (_USB_GOTGCTL_SESREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_GOTGCTL */
<> 150:02e0a0aed4ec 320 #define USB_GOTGCTL_VBVALIDOVEN (0x1UL << 2) /**< VBUS-Valid Override Enable */
<> 150:02e0a0aed4ec 321 #define _USB_GOTGCTL_VBVALIDOVEN_SHIFT 2 /**< Shift value for USB_VBVALIDOVEN */
<> 150:02e0a0aed4ec 322 #define _USB_GOTGCTL_VBVALIDOVEN_MASK 0x4UL /**< Bit mask for USB_VBVALIDOVEN */
<> 150:02e0a0aed4ec 323 #define _USB_GOTGCTL_VBVALIDOVEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */
<> 150:02e0a0aed4ec 324 #define USB_GOTGCTL_VBVALIDOVEN_DEFAULT (_USB_GOTGCTL_VBVALIDOVEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_GOTGCTL */
<> 150:02e0a0aed4ec 325 #define USB_GOTGCTL_VBVALIDOVVAL (0x1UL << 3) /**< VBUS Valid Override Value */
<> 150:02e0a0aed4ec 326 #define _USB_GOTGCTL_VBVALIDOVVAL_SHIFT 3 /**< Shift value for USB_VBVALIDOVVAL */
<> 150:02e0a0aed4ec 327 #define _USB_GOTGCTL_VBVALIDOVVAL_MASK 0x8UL /**< Bit mask for USB_VBVALIDOVVAL */
<> 150:02e0a0aed4ec 328 #define _USB_GOTGCTL_VBVALIDOVVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */
<> 150:02e0a0aed4ec 329 #define USB_GOTGCTL_VBVALIDOVVAL_DEFAULT (_USB_GOTGCTL_VBVALIDOVVAL_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_GOTGCTL */
<> 150:02e0a0aed4ec 330 #define USB_GOTGCTL_BVALIDOVEN (0x1UL << 4) /**< BValid Override Enable */
<> 150:02e0a0aed4ec 331 #define _USB_GOTGCTL_BVALIDOVEN_SHIFT 4 /**< Shift value for USB_BVALIDOVEN */
<> 150:02e0a0aed4ec 332 #define _USB_GOTGCTL_BVALIDOVEN_MASK 0x10UL /**< Bit mask for USB_BVALIDOVEN */
<> 150:02e0a0aed4ec 333 #define _USB_GOTGCTL_BVALIDOVEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */
<> 150:02e0a0aed4ec 334 #define USB_GOTGCTL_BVALIDOVEN_DEFAULT (_USB_GOTGCTL_BVALIDOVEN_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_GOTGCTL */
<> 150:02e0a0aed4ec 335 #define USB_GOTGCTL_BVALIDOVVAL (0x1UL << 5) /**< Bvalid Override Value */
<> 150:02e0a0aed4ec 336 #define _USB_GOTGCTL_BVALIDOVVAL_SHIFT 5 /**< Shift value for USB_BVALIDOVVAL */
<> 150:02e0a0aed4ec 337 #define _USB_GOTGCTL_BVALIDOVVAL_MASK 0x20UL /**< Bit mask for USB_BVALIDOVVAL */
<> 150:02e0a0aed4ec 338 #define _USB_GOTGCTL_BVALIDOVVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */
<> 150:02e0a0aed4ec 339 #define USB_GOTGCTL_BVALIDOVVAL_DEFAULT (_USB_GOTGCTL_BVALIDOVVAL_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_GOTGCTL */
<> 150:02e0a0aed4ec 340 #define USB_GOTGCTL_AVALIDOVEN (0x1UL << 6) /**< AValid Override Enable */
<> 150:02e0a0aed4ec 341 #define _USB_GOTGCTL_AVALIDOVEN_SHIFT 6 /**< Shift value for USB_AVALIDOVEN */
<> 150:02e0a0aed4ec 342 #define _USB_GOTGCTL_AVALIDOVEN_MASK 0x40UL /**< Bit mask for USB_AVALIDOVEN */
<> 150:02e0a0aed4ec 343 #define _USB_GOTGCTL_AVALIDOVEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */
<> 150:02e0a0aed4ec 344 #define USB_GOTGCTL_AVALIDOVEN_DEFAULT (_USB_GOTGCTL_AVALIDOVEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_GOTGCTL */
<> 150:02e0a0aed4ec 345 #define USB_GOTGCTL_AVALIDOVVAL (0x1UL << 7) /**< Avalid Override Value */
<> 150:02e0a0aed4ec 346 #define _USB_GOTGCTL_AVALIDOVVAL_SHIFT 7 /**< Shift value for USB_AVALIDOVVAL */
<> 150:02e0a0aed4ec 347 #define _USB_GOTGCTL_AVALIDOVVAL_MASK 0x80UL /**< Bit mask for USB_AVALIDOVVAL */
<> 150:02e0a0aed4ec 348 #define _USB_GOTGCTL_AVALIDOVVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */
<> 150:02e0a0aed4ec 349 #define USB_GOTGCTL_AVALIDOVVAL_DEFAULT (_USB_GOTGCTL_AVALIDOVVAL_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_GOTGCTL */
<> 150:02e0a0aed4ec 350 #define USB_GOTGCTL_HSTNEGSCS (0x1UL << 8) /**< Host Negotiation Success device only */
<> 150:02e0a0aed4ec 351 #define _USB_GOTGCTL_HSTNEGSCS_SHIFT 8 /**< Shift value for USB_HSTNEGSCS */
<> 150:02e0a0aed4ec 352 #define _USB_GOTGCTL_HSTNEGSCS_MASK 0x100UL /**< Bit mask for USB_HSTNEGSCS */
<> 150:02e0a0aed4ec 353 #define _USB_GOTGCTL_HSTNEGSCS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */
<> 150:02e0a0aed4ec 354 #define USB_GOTGCTL_HSTNEGSCS_DEFAULT (_USB_GOTGCTL_HSTNEGSCS_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_GOTGCTL */
<> 150:02e0a0aed4ec 355 #define USB_GOTGCTL_HNPREQ (0x1UL << 9) /**< HNP Request device only */
<> 150:02e0a0aed4ec 356 #define _USB_GOTGCTL_HNPREQ_SHIFT 9 /**< Shift value for USB_HNPREQ */
<> 150:02e0a0aed4ec 357 #define _USB_GOTGCTL_HNPREQ_MASK 0x200UL /**< Bit mask for USB_HNPREQ */
<> 150:02e0a0aed4ec 358 #define _USB_GOTGCTL_HNPREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */
<> 150:02e0a0aed4ec 359 #define USB_GOTGCTL_HNPREQ_DEFAULT (_USB_GOTGCTL_HNPREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for USB_GOTGCTL */
<> 150:02e0a0aed4ec 360 #define USB_GOTGCTL_HSTSETHNPEN (0x1UL << 10) /**< Host Set HNP Enable host only */
<> 150:02e0a0aed4ec 361 #define _USB_GOTGCTL_HSTSETHNPEN_SHIFT 10 /**< Shift value for USB_HSTSETHNPEN */
<> 150:02e0a0aed4ec 362 #define _USB_GOTGCTL_HSTSETHNPEN_MASK 0x400UL /**< Bit mask for USB_HSTSETHNPEN */
<> 150:02e0a0aed4ec 363 #define _USB_GOTGCTL_HSTSETHNPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */
<> 150:02e0a0aed4ec 364 #define USB_GOTGCTL_HSTSETHNPEN_DEFAULT (_USB_GOTGCTL_HSTSETHNPEN_DEFAULT << 10) /**< Shifted mode DEFAULT for USB_GOTGCTL */
<> 150:02e0a0aed4ec 365 #define USB_GOTGCTL_DEVHNPEN (0x1UL << 11) /**< Device HNP Enabled device only */
<> 150:02e0a0aed4ec 366 #define _USB_GOTGCTL_DEVHNPEN_SHIFT 11 /**< Shift value for USB_DEVHNPEN */
<> 150:02e0a0aed4ec 367 #define _USB_GOTGCTL_DEVHNPEN_MASK 0x800UL /**< Bit mask for USB_DEVHNPEN */
<> 150:02e0a0aed4ec 368 #define _USB_GOTGCTL_DEVHNPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */
<> 150:02e0a0aed4ec 369 #define USB_GOTGCTL_DEVHNPEN_DEFAULT (_USB_GOTGCTL_DEVHNPEN_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_GOTGCTL */
<> 150:02e0a0aed4ec 370 #define USB_GOTGCTL_CONIDSTS (0x1UL << 16) /**< Connector ID Status host and device */
<> 150:02e0a0aed4ec 371 #define _USB_GOTGCTL_CONIDSTS_SHIFT 16 /**< Shift value for USB_CONIDSTS */
<> 150:02e0a0aed4ec 372 #define _USB_GOTGCTL_CONIDSTS_MASK 0x10000UL /**< Bit mask for USB_CONIDSTS */
<> 150:02e0a0aed4ec 373 #define _USB_GOTGCTL_CONIDSTS_A 0x00000000UL /**< Mode A for USB_GOTGCTL */
<> 150:02e0a0aed4ec 374 #define _USB_GOTGCTL_CONIDSTS_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_GOTGCTL */
<> 150:02e0a0aed4ec 375 #define _USB_GOTGCTL_CONIDSTS_B 0x00000001UL /**< Mode B for USB_GOTGCTL */
<> 150:02e0a0aed4ec 376 #define USB_GOTGCTL_CONIDSTS_A (_USB_GOTGCTL_CONIDSTS_A << 16) /**< Shifted mode A for USB_GOTGCTL */
<> 150:02e0a0aed4ec 377 #define USB_GOTGCTL_CONIDSTS_DEFAULT (_USB_GOTGCTL_CONIDSTS_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_GOTGCTL */
<> 150:02e0a0aed4ec 378 #define USB_GOTGCTL_CONIDSTS_B (_USB_GOTGCTL_CONIDSTS_B << 16) /**< Shifted mode B for USB_GOTGCTL */
<> 150:02e0a0aed4ec 379 #define USB_GOTGCTL_DBNCTIME (0x1UL << 17) /**< Long/Short Debounce Time host only */
<> 150:02e0a0aed4ec 380 #define _USB_GOTGCTL_DBNCTIME_SHIFT 17 /**< Shift value for USB_DBNCTIME */
<> 150:02e0a0aed4ec 381 #define _USB_GOTGCTL_DBNCTIME_MASK 0x20000UL /**< Bit mask for USB_DBNCTIME */
<> 150:02e0a0aed4ec 382 #define _USB_GOTGCTL_DBNCTIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */
<> 150:02e0a0aed4ec 383 #define _USB_GOTGCTL_DBNCTIME_LONG 0x00000000UL /**< Mode LONG for USB_GOTGCTL */
<> 150:02e0a0aed4ec 384 #define _USB_GOTGCTL_DBNCTIME_SHORT 0x00000001UL /**< Mode SHORT for USB_GOTGCTL */
<> 150:02e0a0aed4ec 385 #define USB_GOTGCTL_DBNCTIME_DEFAULT (_USB_GOTGCTL_DBNCTIME_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_GOTGCTL */
<> 150:02e0a0aed4ec 386 #define USB_GOTGCTL_DBNCTIME_LONG (_USB_GOTGCTL_DBNCTIME_LONG << 17) /**< Shifted mode LONG for USB_GOTGCTL */
<> 150:02e0a0aed4ec 387 #define USB_GOTGCTL_DBNCTIME_SHORT (_USB_GOTGCTL_DBNCTIME_SHORT << 17) /**< Shifted mode SHORT for USB_GOTGCTL */
<> 150:02e0a0aed4ec 388 #define USB_GOTGCTL_ASESVLD (0x1UL << 18) /**< A-Session Valid host only */
<> 150:02e0a0aed4ec 389 #define _USB_GOTGCTL_ASESVLD_SHIFT 18 /**< Shift value for USB_ASESVLD */
<> 150:02e0a0aed4ec 390 #define _USB_GOTGCTL_ASESVLD_MASK 0x40000UL /**< Bit mask for USB_ASESVLD */
<> 150:02e0a0aed4ec 391 #define _USB_GOTGCTL_ASESVLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */
<> 150:02e0a0aed4ec 392 #define USB_GOTGCTL_ASESVLD_DEFAULT (_USB_GOTGCTL_ASESVLD_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_GOTGCTL */
<> 150:02e0a0aed4ec 393 #define USB_GOTGCTL_BSESVLD (0x1UL << 19) /**< B-Session Valid device only */
<> 150:02e0a0aed4ec 394 #define _USB_GOTGCTL_BSESVLD_SHIFT 19 /**< Shift value for USB_BSESVLD */
<> 150:02e0a0aed4ec 395 #define _USB_GOTGCTL_BSESVLD_MASK 0x80000UL /**< Bit mask for USB_BSESVLD */
<> 150:02e0a0aed4ec 396 #define _USB_GOTGCTL_BSESVLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */
<> 150:02e0a0aed4ec 397 #define USB_GOTGCTL_BSESVLD_DEFAULT (_USB_GOTGCTL_BSESVLD_DEFAULT << 19) /**< Shifted mode DEFAULT for USB_GOTGCTL */
<> 150:02e0a0aed4ec 398 #define USB_GOTGCTL_OTGVER (0x1UL << 20) /**< OTG Version */
<> 150:02e0a0aed4ec 399 #define _USB_GOTGCTL_OTGVER_SHIFT 20 /**< Shift value for USB_OTGVER */
<> 150:02e0a0aed4ec 400 #define _USB_GOTGCTL_OTGVER_MASK 0x100000UL /**< Bit mask for USB_OTGVER */
<> 150:02e0a0aed4ec 401 #define _USB_GOTGCTL_OTGVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */
<> 150:02e0a0aed4ec 402 #define _USB_GOTGCTL_OTGVER_OTG13 0x00000000UL /**< Mode OTG13 for USB_GOTGCTL */
<> 150:02e0a0aed4ec 403 #define _USB_GOTGCTL_OTGVER_OTG20 0x00000001UL /**< Mode OTG20 for USB_GOTGCTL */
<> 150:02e0a0aed4ec 404 #define USB_GOTGCTL_OTGVER_DEFAULT (_USB_GOTGCTL_OTGVER_DEFAULT << 20) /**< Shifted mode DEFAULT for USB_GOTGCTL */
<> 150:02e0a0aed4ec 405 #define USB_GOTGCTL_OTGVER_OTG13 (_USB_GOTGCTL_OTGVER_OTG13 << 20) /**< Shifted mode OTG13 for USB_GOTGCTL */
<> 150:02e0a0aed4ec 406 #define USB_GOTGCTL_OTGVER_OTG20 (_USB_GOTGCTL_OTGVER_OTG20 << 20) /**< Shifted mode OTG20 for USB_GOTGCTL */
<> 150:02e0a0aed4ec 407
<> 150:02e0a0aed4ec 408 /* Bit fields for USB GOTGINT */
<> 150:02e0a0aed4ec 409 #define _USB_GOTGINT_RESETVALUE 0x00000000UL /**< Default value for USB_GOTGINT */
<> 150:02e0a0aed4ec 410 #define _USB_GOTGINT_MASK 0x000E0304UL /**< Mask for USB_GOTGINT */
<> 150:02e0a0aed4ec 411 #define USB_GOTGINT_SESENDDET (0x1UL << 2) /**< Session End Detected host and device */
<> 150:02e0a0aed4ec 412 #define _USB_GOTGINT_SESENDDET_SHIFT 2 /**< Shift value for USB_SESENDDET */
<> 150:02e0a0aed4ec 413 #define _USB_GOTGINT_SESENDDET_MASK 0x4UL /**< Bit mask for USB_SESENDDET */
<> 150:02e0a0aed4ec 414 #define _USB_GOTGINT_SESENDDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGINT */
<> 150:02e0a0aed4ec 415 #define USB_GOTGINT_SESENDDET_DEFAULT (_USB_GOTGINT_SESENDDET_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_GOTGINT */
<> 150:02e0a0aed4ec 416 #define USB_GOTGINT_SESREQSUCSTSCHNG (0x1UL << 8) /**< Session Request Success Status Change host and device */
<> 150:02e0a0aed4ec 417 #define _USB_GOTGINT_SESREQSUCSTSCHNG_SHIFT 8 /**< Shift value for USB_SESREQSUCSTSCHNG */
<> 150:02e0a0aed4ec 418 #define _USB_GOTGINT_SESREQSUCSTSCHNG_MASK 0x100UL /**< Bit mask for USB_SESREQSUCSTSCHNG */
<> 150:02e0a0aed4ec 419 #define _USB_GOTGINT_SESREQSUCSTSCHNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGINT */
<> 150:02e0a0aed4ec 420 #define USB_GOTGINT_SESREQSUCSTSCHNG_DEFAULT (_USB_GOTGINT_SESREQSUCSTSCHNG_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_GOTGINT */
<> 150:02e0a0aed4ec 421 #define USB_GOTGINT_HSTNEGSUCSTSCHNG (0x1UL << 9) /**< Host Negotiation Success Status Change host and device */
<> 150:02e0a0aed4ec 422 #define _USB_GOTGINT_HSTNEGSUCSTSCHNG_SHIFT 9 /**< Shift value for USB_HSTNEGSUCSTSCHNG */
<> 150:02e0a0aed4ec 423 #define _USB_GOTGINT_HSTNEGSUCSTSCHNG_MASK 0x200UL /**< Bit mask for USB_HSTNEGSUCSTSCHNG */
<> 150:02e0a0aed4ec 424 #define _USB_GOTGINT_HSTNEGSUCSTSCHNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGINT */
<> 150:02e0a0aed4ec 425 #define USB_GOTGINT_HSTNEGSUCSTSCHNG_DEFAULT (_USB_GOTGINT_HSTNEGSUCSTSCHNG_DEFAULT << 9) /**< Shifted mode DEFAULT for USB_GOTGINT */
<> 150:02e0a0aed4ec 426 #define USB_GOTGINT_HSTNEGDET (0x1UL << 17) /**< Host Negotiation Detected host and device */
<> 150:02e0a0aed4ec 427 #define _USB_GOTGINT_HSTNEGDET_SHIFT 17 /**< Shift value for USB_HSTNEGDET */
<> 150:02e0a0aed4ec 428 #define _USB_GOTGINT_HSTNEGDET_MASK 0x20000UL /**< Bit mask for USB_HSTNEGDET */
<> 150:02e0a0aed4ec 429 #define _USB_GOTGINT_HSTNEGDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGINT */
<> 150:02e0a0aed4ec 430 #define USB_GOTGINT_HSTNEGDET_DEFAULT (_USB_GOTGINT_HSTNEGDET_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_GOTGINT */
<> 150:02e0a0aed4ec 431 #define USB_GOTGINT_ADEVTOUTCHG (0x1UL << 18) /**< A-Device Timeout Change host and device */
<> 150:02e0a0aed4ec 432 #define _USB_GOTGINT_ADEVTOUTCHG_SHIFT 18 /**< Shift value for USB_ADEVTOUTCHG */
<> 150:02e0a0aed4ec 433 #define _USB_GOTGINT_ADEVTOUTCHG_MASK 0x40000UL /**< Bit mask for USB_ADEVTOUTCHG */
<> 150:02e0a0aed4ec 434 #define _USB_GOTGINT_ADEVTOUTCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGINT */
<> 150:02e0a0aed4ec 435 #define USB_GOTGINT_ADEVTOUTCHG_DEFAULT (_USB_GOTGINT_ADEVTOUTCHG_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_GOTGINT */
<> 150:02e0a0aed4ec 436 #define USB_GOTGINT_DBNCEDONE (0x1UL << 19) /**< Debounce Done host only */
<> 150:02e0a0aed4ec 437 #define _USB_GOTGINT_DBNCEDONE_SHIFT 19 /**< Shift value for USB_DBNCEDONE */
<> 150:02e0a0aed4ec 438 #define _USB_GOTGINT_DBNCEDONE_MASK 0x80000UL /**< Bit mask for USB_DBNCEDONE */
<> 150:02e0a0aed4ec 439 #define _USB_GOTGINT_DBNCEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGINT */
<> 150:02e0a0aed4ec 440 #define USB_GOTGINT_DBNCEDONE_DEFAULT (_USB_GOTGINT_DBNCEDONE_DEFAULT << 19) /**< Shifted mode DEFAULT for USB_GOTGINT */
<> 150:02e0a0aed4ec 441
<> 150:02e0a0aed4ec 442 /* Bit fields for USB GAHBCFG */
<> 150:02e0a0aed4ec 443 #define _USB_GAHBCFG_RESETVALUE 0x00000000UL /**< Default value for USB_GAHBCFG */
<> 150:02e0a0aed4ec 444 #define _USB_GAHBCFG_MASK 0x006001BFUL /**< Mask for USB_GAHBCFG */
<> 150:02e0a0aed4ec 445 #define USB_GAHBCFG_GLBLINTRMSK (0x1UL << 0) /**< Global Interrupt Mask host and device */
<> 150:02e0a0aed4ec 446 #define _USB_GAHBCFG_GLBLINTRMSK_SHIFT 0 /**< Shift value for USB_GLBLINTRMSK */
<> 150:02e0a0aed4ec 447 #define _USB_GAHBCFG_GLBLINTRMSK_MASK 0x1UL /**< Bit mask for USB_GLBLINTRMSK */
<> 150:02e0a0aed4ec 448 #define _USB_GAHBCFG_GLBLINTRMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GAHBCFG */
<> 150:02e0a0aed4ec 449 #define USB_GAHBCFG_GLBLINTRMSK_DEFAULT (_USB_GAHBCFG_GLBLINTRMSK_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GAHBCFG */
<> 150:02e0a0aed4ec 450 #define _USB_GAHBCFG_HBSTLEN_SHIFT 1 /**< Shift value for USB_HBSTLEN */
<> 150:02e0a0aed4ec 451 #define _USB_GAHBCFG_HBSTLEN_MASK 0x1EUL /**< Bit mask for USB_HBSTLEN */
<> 150:02e0a0aed4ec 452 #define _USB_GAHBCFG_HBSTLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GAHBCFG */
<> 150:02e0a0aed4ec 453 #define _USB_GAHBCFG_HBSTLEN_SINGLE 0x00000000UL /**< Mode SINGLE for USB_GAHBCFG */
<> 150:02e0a0aed4ec 454 #define _USB_GAHBCFG_HBSTLEN_INCR 0x00000001UL /**< Mode INCR for USB_GAHBCFG */
<> 150:02e0a0aed4ec 455 #define _USB_GAHBCFG_HBSTLEN_INCR4 0x00000003UL /**< Mode INCR4 for USB_GAHBCFG */
<> 150:02e0a0aed4ec 456 #define _USB_GAHBCFG_HBSTLEN_INCR8 0x00000005UL /**< Mode INCR8 for USB_GAHBCFG */
<> 150:02e0a0aed4ec 457 #define _USB_GAHBCFG_HBSTLEN_INCR16 0x00000007UL /**< Mode INCR16 for USB_GAHBCFG */
<> 150:02e0a0aed4ec 458 #define USB_GAHBCFG_HBSTLEN_DEFAULT (_USB_GAHBCFG_HBSTLEN_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_GAHBCFG */
<> 150:02e0a0aed4ec 459 #define USB_GAHBCFG_HBSTLEN_SINGLE (_USB_GAHBCFG_HBSTLEN_SINGLE << 1) /**< Shifted mode SINGLE for USB_GAHBCFG */
<> 150:02e0a0aed4ec 460 #define USB_GAHBCFG_HBSTLEN_INCR (_USB_GAHBCFG_HBSTLEN_INCR << 1) /**< Shifted mode INCR for USB_GAHBCFG */
<> 150:02e0a0aed4ec 461 #define USB_GAHBCFG_HBSTLEN_INCR4 (_USB_GAHBCFG_HBSTLEN_INCR4 << 1) /**< Shifted mode INCR4 for USB_GAHBCFG */
<> 150:02e0a0aed4ec 462 #define USB_GAHBCFG_HBSTLEN_INCR8 (_USB_GAHBCFG_HBSTLEN_INCR8 << 1) /**< Shifted mode INCR8 for USB_GAHBCFG */
<> 150:02e0a0aed4ec 463 #define USB_GAHBCFG_HBSTLEN_INCR16 (_USB_GAHBCFG_HBSTLEN_INCR16 << 1) /**< Shifted mode INCR16 for USB_GAHBCFG */
<> 150:02e0a0aed4ec 464 #define USB_GAHBCFG_DMAEN (0x1UL << 5) /**< DMA Enable host and device */
<> 150:02e0a0aed4ec 465 #define _USB_GAHBCFG_DMAEN_SHIFT 5 /**< Shift value for USB_DMAEN */
<> 150:02e0a0aed4ec 466 #define _USB_GAHBCFG_DMAEN_MASK 0x20UL /**< Bit mask for USB_DMAEN */
<> 150:02e0a0aed4ec 467 #define _USB_GAHBCFG_DMAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GAHBCFG */
<> 150:02e0a0aed4ec 468 #define USB_GAHBCFG_DMAEN_DEFAULT (_USB_GAHBCFG_DMAEN_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_GAHBCFG */
<> 150:02e0a0aed4ec 469 #define USB_GAHBCFG_NPTXFEMPLVL (0x1UL << 7) /**< Non-Periodic TxFIFO Empty Level host and device */
<> 150:02e0a0aed4ec 470 #define _USB_GAHBCFG_NPTXFEMPLVL_SHIFT 7 /**< Shift value for USB_NPTXFEMPLVL */
<> 150:02e0a0aed4ec 471 #define _USB_GAHBCFG_NPTXFEMPLVL_MASK 0x80UL /**< Bit mask for USB_NPTXFEMPLVL */
<> 150:02e0a0aed4ec 472 #define _USB_GAHBCFG_NPTXFEMPLVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GAHBCFG */
<> 150:02e0a0aed4ec 473 #define _USB_GAHBCFG_NPTXFEMPLVL_HALFEMPTY 0x00000000UL /**< Mode HALFEMPTY for USB_GAHBCFG */
<> 150:02e0a0aed4ec 474 #define _USB_GAHBCFG_NPTXFEMPLVL_EMPTY 0x00000001UL /**< Mode EMPTY for USB_GAHBCFG */
<> 150:02e0a0aed4ec 475 #define USB_GAHBCFG_NPTXFEMPLVL_DEFAULT (_USB_GAHBCFG_NPTXFEMPLVL_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_GAHBCFG */
<> 150:02e0a0aed4ec 476 #define USB_GAHBCFG_NPTXFEMPLVL_HALFEMPTY (_USB_GAHBCFG_NPTXFEMPLVL_HALFEMPTY << 7) /**< Shifted mode HALFEMPTY for USB_GAHBCFG */
<> 150:02e0a0aed4ec 477 #define USB_GAHBCFG_NPTXFEMPLVL_EMPTY (_USB_GAHBCFG_NPTXFEMPLVL_EMPTY << 7) /**< Shifted mode EMPTY for USB_GAHBCFG */
<> 150:02e0a0aed4ec 478 #define USB_GAHBCFG_PTXFEMPLVL (0x1UL << 8) /**< Periodic TxFIFO Empty Level host only */
<> 150:02e0a0aed4ec 479 #define _USB_GAHBCFG_PTXFEMPLVL_SHIFT 8 /**< Shift value for USB_PTXFEMPLVL */
<> 150:02e0a0aed4ec 480 #define _USB_GAHBCFG_PTXFEMPLVL_MASK 0x100UL /**< Bit mask for USB_PTXFEMPLVL */
<> 150:02e0a0aed4ec 481 #define _USB_GAHBCFG_PTXFEMPLVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GAHBCFG */
<> 150:02e0a0aed4ec 482 #define _USB_GAHBCFG_PTXFEMPLVL_HALFEMPTY 0x00000000UL /**< Mode HALFEMPTY for USB_GAHBCFG */
<> 150:02e0a0aed4ec 483 #define _USB_GAHBCFG_PTXFEMPLVL_EMPTY 0x00000001UL /**< Mode EMPTY for USB_GAHBCFG */
<> 150:02e0a0aed4ec 484 #define USB_GAHBCFG_PTXFEMPLVL_DEFAULT (_USB_GAHBCFG_PTXFEMPLVL_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_GAHBCFG */
<> 150:02e0a0aed4ec 485 #define USB_GAHBCFG_PTXFEMPLVL_HALFEMPTY (_USB_GAHBCFG_PTXFEMPLVL_HALFEMPTY << 8) /**< Shifted mode HALFEMPTY for USB_GAHBCFG */
<> 150:02e0a0aed4ec 486 #define USB_GAHBCFG_PTXFEMPLVL_EMPTY (_USB_GAHBCFG_PTXFEMPLVL_EMPTY << 8) /**< Shifted mode EMPTY for USB_GAHBCFG */
<> 150:02e0a0aed4ec 487 #define USB_GAHBCFG_REMMEMSUPP (0x1UL << 21) /**< Remote Memory Support */
<> 150:02e0a0aed4ec 488 #define _USB_GAHBCFG_REMMEMSUPP_SHIFT 21 /**< Shift value for USB_REMMEMSUPP */
<> 150:02e0a0aed4ec 489 #define _USB_GAHBCFG_REMMEMSUPP_MASK 0x200000UL /**< Bit mask for USB_REMMEMSUPP */
<> 150:02e0a0aed4ec 490 #define _USB_GAHBCFG_REMMEMSUPP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GAHBCFG */
<> 150:02e0a0aed4ec 491 #define USB_GAHBCFG_REMMEMSUPP_DEFAULT (_USB_GAHBCFG_REMMEMSUPP_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_GAHBCFG */
<> 150:02e0a0aed4ec 492 #define USB_GAHBCFG_NOTIALLDMAWRIT (0x1UL << 22) /**< Notify All DMA Writes */
<> 150:02e0a0aed4ec 493 #define _USB_GAHBCFG_NOTIALLDMAWRIT_SHIFT 22 /**< Shift value for USB_NOTIALLDMAWRIT */
<> 150:02e0a0aed4ec 494 #define _USB_GAHBCFG_NOTIALLDMAWRIT_MASK 0x400000UL /**< Bit mask for USB_NOTIALLDMAWRIT */
<> 150:02e0a0aed4ec 495 #define _USB_GAHBCFG_NOTIALLDMAWRIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GAHBCFG */
<> 150:02e0a0aed4ec 496 #define USB_GAHBCFG_NOTIALLDMAWRIT_DEFAULT (_USB_GAHBCFG_NOTIALLDMAWRIT_DEFAULT << 22) /**< Shifted mode DEFAULT for USB_GAHBCFG */
<> 150:02e0a0aed4ec 497
<> 150:02e0a0aed4ec 498 /* Bit fields for USB GUSBCFG */
<> 150:02e0a0aed4ec 499 #define _USB_GUSBCFG_RESETVALUE 0x00001440UL /**< Default value for USB_GUSBCFG */
<> 150:02e0a0aed4ec 500 #define _USB_GUSBCFG_MASK 0xF0403F27UL /**< Mask for USB_GUSBCFG */
<> 150:02e0a0aed4ec 501 #define _USB_GUSBCFG_TOUTCAL_SHIFT 0 /**< Shift value for USB_TOUTCAL */
<> 150:02e0a0aed4ec 502 #define _USB_GUSBCFG_TOUTCAL_MASK 0x7UL /**< Bit mask for USB_TOUTCAL */
<> 150:02e0a0aed4ec 503 #define _USB_GUSBCFG_TOUTCAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GUSBCFG */
<> 150:02e0a0aed4ec 504 #define USB_GUSBCFG_TOUTCAL_DEFAULT (_USB_GUSBCFG_TOUTCAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GUSBCFG */
<> 150:02e0a0aed4ec 505 #define USB_GUSBCFG_FSINTF (0x1UL << 5) /**< Full-Speed Serial Interface Select host and device */
<> 150:02e0a0aed4ec 506 #define _USB_GUSBCFG_FSINTF_SHIFT 5 /**< Shift value for USB_FSINTF */
<> 150:02e0a0aed4ec 507 #define _USB_GUSBCFG_FSINTF_MASK 0x20UL /**< Bit mask for USB_FSINTF */
<> 150:02e0a0aed4ec 508 #define _USB_GUSBCFG_FSINTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GUSBCFG */
<> 150:02e0a0aed4ec 509 #define USB_GUSBCFG_FSINTF_DEFAULT (_USB_GUSBCFG_FSINTF_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_GUSBCFG */
<> 150:02e0a0aed4ec 510 #define USB_GUSBCFG_SRPCAP (0x1UL << 8) /**< SRP-Capable host and device */
<> 150:02e0a0aed4ec 511 #define _USB_GUSBCFG_SRPCAP_SHIFT 8 /**< Shift value for USB_SRPCAP */
<> 150:02e0a0aed4ec 512 #define _USB_GUSBCFG_SRPCAP_MASK 0x100UL /**< Bit mask for USB_SRPCAP */
<> 150:02e0a0aed4ec 513 #define _USB_GUSBCFG_SRPCAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GUSBCFG */
<> 150:02e0a0aed4ec 514 #define USB_GUSBCFG_SRPCAP_DEFAULT (_USB_GUSBCFG_SRPCAP_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_GUSBCFG */
<> 150:02e0a0aed4ec 515 #define USB_GUSBCFG_HNPCAP (0x1UL << 9) /**< HNP-Capable host and device */
<> 150:02e0a0aed4ec 516 #define _USB_GUSBCFG_HNPCAP_SHIFT 9 /**< Shift value for USB_HNPCAP */
<> 150:02e0a0aed4ec 517 #define _USB_GUSBCFG_HNPCAP_MASK 0x200UL /**< Bit mask for USB_HNPCAP */
<> 150:02e0a0aed4ec 518 #define _USB_GUSBCFG_HNPCAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GUSBCFG */
<> 150:02e0a0aed4ec 519 #define USB_GUSBCFG_HNPCAP_DEFAULT (_USB_GUSBCFG_HNPCAP_DEFAULT << 9) /**< Shifted mode DEFAULT for USB_GUSBCFG */
<> 150:02e0a0aed4ec 520 #define _USB_GUSBCFG_USBTRDTIM_SHIFT 10 /**< Shift value for USB_USBTRDTIM */
<> 150:02e0a0aed4ec 521 #define _USB_GUSBCFG_USBTRDTIM_MASK 0x3C00UL /**< Bit mask for USB_USBTRDTIM */
<> 150:02e0a0aed4ec 522 #define _USB_GUSBCFG_USBTRDTIM_DEFAULT 0x00000005UL /**< Mode DEFAULT for USB_GUSBCFG */
<> 150:02e0a0aed4ec 523 #define USB_GUSBCFG_USBTRDTIM_DEFAULT (_USB_GUSBCFG_USBTRDTIM_DEFAULT << 10) /**< Shifted mode DEFAULT for USB_GUSBCFG */
<> 150:02e0a0aed4ec 524 #define USB_GUSBCFG_TERMSELDLPULSE (0x1UL << 22) /**< TermSel DLine Pulsing Selection device only */
<> 150:02e0a0aed4ec 525 #define _USB_GUSBCFG_TERMSELDLPULSE_SHIFT 22 /**< Shift value for USB_TERMSELDLPULSE */
<> 150:02e0a0aed4ec 526 #define _USB_GUSBCFG_TERMSELDLPULSE_MASK 0x400000UL /**< Bit mask for USB_TERMSELDLPULSE */
<> 150:02e0a0aed4ec 527 #define _USB_GUSBCFG_TERMSELDLPULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GUSBCFG */
<> 150:02e0a0aed4ec 528 #define _USB_GUSBCFG_TERMSELDLPULSE_TXVALID 0x00000000UL /**< Mode TXVALID for USB_GUSBCFG */
<> 150:02e0a0aed4ec 529 #define _USB_GUSBCFG_TERMSELDLPULSE_TERMSEL 0x00000001UL /**< Mode TERMSEL for USB_GUSBCFG */
<> 150:02e0a0aed4ec 530 #define USB_GUSBCFG_TERMSELDLPULSE_DEFAULT (_USB_GUSBCFG_TERMSELDLPULSE_DEFAULT << 22) /**< Shifted mode DEFAULT for USB_GUSBCFG */
<> 150:02e0a0aed4ec 531 #define USB_GUSBCFG_TERMSELDLPULSE_TXVALID (_USB_GUSBCFG_TERMSELDLPULSE_TXVALID << 22) /**< Shifted mode TXVALID for USB_GUSBCFG */
<> 150:02e0a0aed4ec 532 #define USB_GUSBCFG_TERMSELDLPULSE_TERMSEL (_USB_GUSBCFG_TERMSELDLPULSE_TERMSEL << 22) /**< Shifted mode TERMSEL for USB_GUSBCFG */
<> 150:02e0a0aed4ec 533 #define USB_GUSBCFG_TXENDDELAY (0x1UL << 28) /**< Tx End Delay device only */
<> 150:02e0a0aed4ec 534 #define _USB_GUSBCFG_TXENDDELAY_SHIFT 28 /**< Shift value for USB_TXENDDELAY */
<> 150:02e0a0aed4ec 535 #define _USB_GUSBCFG_TXENDDELAY_MASK 0x10000000UL /**< Bit mask for USB_TXENDDELAY */
<> 150:02e0a0aed4ec 536 #define _USB_GUSBCFG_TXENDDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GUSBCFG */
<> 150:02e0a0aed4ec 537 #define USB_GUSBCFG_TXENDDELAY_DEFAULT (_USB_GUSBCFG_TXENDDELAY_DEFAULT << 28) /**< Shifted mode DEFAULT for USB_GUSBCFG */
<> 150:02e0a0aed4ec 538 #define USB_GUSBCFG_FORCEHSTMODE (0x1UL << 29) /**< Force Host Mode host and device */
<> 150:02e0a0aed4ec 539 #define _USB_GUSBCFG_FORCEHSTMODE_SHIFT 29 /**< Shift value for USB_FORCEHSTMODE */
<> 150:02e0a0aed4ec 540 #define _USB_GUSBCFG_FORCEHSTMODE_MASK 0x20000000UL /**< Bit mask for USB_FORCEHSTMODE */
<> 150:02e0a0aed4ec 541 #define _USB_GUSBCFG_FORCEHSTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GUSBCFG */
<> 150:02e0a0aed4ec 542 #define USB_GUSBCFG_FORCEHSTMODE_DEFAULT (_USB_GUSBCFG_FORCEHSTMODE_DEFAULT << 29) /**< Shifted mode DEFAULT for USB_GUSBCFG */
<> 150:02e0a0aed4ec 543 #define USB_GUSBCFG_FORCEDEVMODE (0x1UL << 30) /**< Force Device Mode host and device */
<> 150:02e0a0aed4ec 544 #define _USB_GUSBCFG_FORCEDEVMODE_SHIFT 30 /**< Shift value for USB_FORCEDEVMODE */
<> 150:02e0a0aed4ec 545 #define _USB_GUSBCFG_FORCEDEVMODE_MASK 0x40000000UL /**< Bit mask for USB_FORCEDEVMODE */
<> 150:02e0a0aed4ec 546 #define _USB_GUSBCFG_FORCEDEVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GUSBCFG */
<> 150:02e0a0aed4ec 547 #define USB_GUSBCFG_FORCEDEVMODE_DEFAULT (_USB_GUSBCFG_FORCEDEVMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for USB_GUSBCFG */
<> 150:02e0a0aed4ec 548 #define USB_GUSBCFG_CORRUPTTXPKT (0x1UL << 31) /**< Corrupt Tx packet host and device */
<> 150:02e0a0aed4ec 549 #define _USB_GUSBCFG_CORRUPTTXPKT_SHIFT 31 /**< Shift value for USB_CORRUPTTXPKT */
<> 150:02e0a0aed4ec 550 #define _USB_GUSBCFG_CORRUPTTXPKT_MASK 0x80000000UL /**< Bit mask for USB_CORRUPTTXPKT */
<> 150:02e0a0aed4ec 551 #define _USB_GUSBCFG_CORRUPTTXPKT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GUSBCFG */
<> 150:02e0a0aed4ec 552 #define USB_GUSBCFG_CORRUPTTXPKT_DEFAULT (_USB_GUSBCFG_CORRUPTTXPKT_DEFAULT << 31) /**< Shifted mode DEFAULT for USB_GUSBCFG */
<> 150:02e0a0aed4ec 553
<> 150:02e0a0aed4ec 554 /* Bit fields for USB GRSTCTL */
<> 150:02e0a0aed4ec 555 #define _USB_GRSTCTL_RESETVALUE 0x80000000UL /**< Default value for USB_GRSTCTL */
<> 150:02e0a0aed4ec 556 #define _USB_GRSTCTL_MASK 0xC00007F5UL /**< Mask for USB_GRSTCTL */
<> 150:02e0a0aed4ec 557 #define USB_GRSTCTL_CSFTRST (0x1UL << 0) /**< Core Soft Reset host and device */
<> 150:02e0a0aed4ec 558 #define _USB_GRSTCTL_CSFTRST_SHIFT 0 /**< Shift value for USB_CSFTRST */
<> 150:02e0a0aed4ec 559 #define _USB_GRSTCTL_CSFTRST_MASK 0x1UL /**< Bit mask for USB_CSFTRST */
<> 150:02e0a0aed4ec 560 #define _USB_GRSTCTL_CSFTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRSTCTL */
<> 150:02e0a0aed4ec 561 #define USB_GRSTCTL_CSFTRST_DEFAULT (_USB_GRSTCTL_CSFTRST_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GRSTCTL */
<> 150:02e0a0aed4ec 562 #define USB_GRSTCTL_FRMCNTRRST (0x1UL << 2) /**< Host Frame Counter Reset host only */
<> 150:02e0a0aed4ec 563 #define _USB_GRSTCTL_FRMCNTRRST_SHIFT 2 /**< Shift value for USB_FRMCNTRRST */
<> 150:02e0a0aed4ec 564 #define _USB_GRSTCTL_FRMCNTRRST_MASK 0x4UL /**< Bit mask for USB_FRMCNTRRST */
<> 150:02e0a0aed4ec 565 #define _USB_GRSTCTL_FRMCNTRRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRSTCTL */
<> 150:02e0a0aed4ec 566 #define USB_GRSTCTL_FRMCNTRRST_DEFAULT (_USB_GRSTCTL_FRMCNTRRST_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_GRSTCTL */
<> 150:02e0a0aed4ec 567 #define USB_GRSTCTL_RXFFLSH (0x1UL << 4) /**< RxFIFO Flush host and device */
<> 150:02e0a0aed4ec 568 #define _USB_GRSTCTL_RXFFLSH_SHIFT 4 /**< Shift value for USB_RXFFLSH */
<> 150:02e0a0aed4ec 569 #define _USB_GRSTCTL_RXFFLSH_MASK 0x10UL /**< Bit mask for USB_RXFFLSH */
<> 150:02e0a0aed4ec 570 #define _USB_GRSTCTL_RXFFLSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRSTCTL */
<> 150:02e0a0aed4ec 571 #define USB_GRSTCTL_RXFFLSH_DEFAULT (_USB_GRSTCTL_RXFFLSH_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_GRSTCTL */
<> 150:02e0a0aed4ec 572 #define USB_GRSTCTL_TXFFLSH (0x1UL << 5) /**< TxFIFO Flush host and device */
<> 150:02e0a0aed4ec 573 #define _USB_GRSTCTL_TXFFLSH_SHIFT 5 /**< Shift value for USB_TXFFLSH */
<> 150:02e0a0aed4ec 574 #define _USB_GRSTCTL_TXFFLSH_MASK 0x20UL /**< Bit mask for USB_TXFFLSH */
<> 150:02e0a0aed4ec 575 #define _USB_GRSTCTL_TXFFLSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRSTCTL */
<> 150:02e0a0aed4ec 576 #define USB_GRSTCTL_TXFFLSH_DEFAULT (_USB_GRSTCTL_TXFFLSH_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_GRSTCTL */
<> 150:02e0a0aed4ec 577 #define _USB_GRSTCTL_TXFNUM_SHIFT 6 /**< Shift value for USB_TXFNUM */
<> 150:02e0a0aed4ec 578 #define _USB_GRSTCTL_TXFNUM_MASK 0x7C0UL /**< Bit mask for USB_TXFNUM */
<> 150:02e0a0aed4ec 579 #define _USB_GRSTCTL_TXFNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRSTCTL */
<> 150:02e0a0aed4ec 580 #define _USB_GRSTCTL_TXFNUM_F0 0x00000000UL /**< Mode F0 for USB_GRSTCTL */
<> 150:02e0a0aed4ec 581 #define _USB_GRSTCTL_TXFNUM_F1 0x00000001UL /**< Mode F1 for USB_GRSTCTL */
<> 150:02e0a0aed4ec 582 #define _USB_GRSTCTL_TXFNUM_F2 0x00000002UL /**< Mode F2 for USB_GRSTCTL */
<> 150:02e0a0aed4ec 583 #define _USB_GRSTCTL_TXFNUM_F3 0x00000003UL /**< Mode F3 for USB_GRSTCTL */
<> 150:02e0a0aed4ec 584 #define _USB_GRSTCTL_TXFNUM_F4 0x00000004UL /**< Mode F4 for USB_GRSTCTL */
<> 150:02e0a0aed4ec 585 #define _USB_GRSTCTL_TXFNUM_F5 0x00000005UL /**< Mode F5 for USB_GRSTCTL */
<> 150:02e0a0aed4ec 586 #define _USB_GRSTCTL_TXFNUM_F6 0x00000006UL /**< Mode F6 for USB_GRSTCTL */
<> 150:02e0a0aed4ec 587 #define _USB_GRSTCTL_TXFNUM_FALL 0x00000010UL /**< Mode FALL for USB_GRSTCTL */
<> 150:02e0a0aed4ec 588 #define USB_GRSTCTL_TXFNUM_DEFAULT (_USB_GRSTCTL_TXFNUM_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_GRSTCTL */
<> 150:02e0a0aed4ec 589 #define USB_GRSTCTL_TXFNUM_F0 (_USB_GRSTCTL_TXFNUM_F0 << 6) /**< Shifted mode F0 for USB_GRSTCTL */
<> 150:02e0a0aed4ec 590 #define USB_GRSTCTL_TXFNUM_F1 (_USB_GRSTCTL_TXFNUM_F1 << 6) /**< Shifted mode F1 for USB_GRSTCTL */
<> 150:02e0a0aed4ec 591 #define USB_GRSTCTL_TXFNUM_F2 (_USB_GRSTCTL_TXFNUM_F2 << 6) /**< Shifted mode F2 for USB_GRSTCTL */
<> 150:02e0a0aed4ec 592 #define USB_GRSTCTL_TXFNUM_F3 (_USB_GRSTCTL_TXFNUM_F3 << 6) /**< Shifted mode F3 for USB_GRSTCTL */
<> 150:02e0a0aed4ec 593 #define USB_GRSTCTL_TXFNUM_F4 (_USB_GRSTCTL_TXFNUM_F4 << 6) /**< Shifted mode F4 for USB_GRSTCTL */
<> 150:02e0a0aed4ec 594 #define USB_GRSTCTL_TXFNUM_F5 (_USB_GRSTCTL_TXFNUM_F5 << 6) /**< Shifted mode F5 for USB_GRSTCTL */
<> 150:02e0a0aed4ec 595 #define USB_GRSTCTL_TXFNUM_F6 (_USB_GRSTCTL_TXFNUM_F6 << 6) /**< Shifted mode F6 for USB_GRSTCTL */
<> 150:02e0a0aed4ec 596 #define USB_GRSTCTL_TXFNUM_FALL (_USB_GRSTCTL_TXFNUM_FALL << 6) /**< Shifted mode FALL for USB_GRSTCTL */
<> 150:02e0a0aed4ec 597 #define USB_GRSTCTL_DMAREQ (0x1UL << 30) /**< DMA Request Signal host and device */
<> 150:02e0a0aed4ec 598 #define _USB_GRSTCTL_DMAREQ_SHIFT 30 /**< Shift value for USB_DMAREQ */
<> 150:02e0a0aed4ec 599 #define _USB_GRSTCTL_DMAREQ_MASK 0x40000000UL /**< Bit mask for USB_DMAREQ */
<> 150:02e0a0aed4ec 600 #define _USB_GRSTCTL_DMAREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRSTCTL */
<> 150:02e0a0aed4ec 601 #define USB_GRSTCTL_DMAREQ_DEFAULT (_USB_GRSTCTL_DMAREQ_DEFAULT << 30) /**< Shifted mode DEFAULT for USB_GRSTCTL */
<> 150:02e0a0aed4ec 602 #define USB_GRSTCTL_AHBIDLE (0x1UL << 31) /**< AHB Master Idle host and device */
<> 150:02e0a0aed4ec 603 #define _USB_GRSTCTL_AHBIDLE_SHIFT 31 /**< Shift value for USB_AHBIDLE */
<> 150:02e0a0aed4ec 604 #define _USB_GRSTCTL_AHBIDLE_MASK 0x80000000UL /**< Bit mask for USB_AHBIDLE */
<> 150:02e0a0aed4ec 605 #define _USB_GRSTCTL_AHBIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_GRSTCTL */
<> 150:02e0a0aed4ec 606 #define USB_GRSTCTL_AHBIDLE_DEFAULT (_USB_GRSTCTL_AHBIDLE_DEFAULT << 31) /**< Shifted mode DEFAULT for USB_GRSTCTL */
<> 150:02e0a0aed4ec 607
<> 150:02e0a0aed4ec 608 /* Bit fields for USB GINTSTS */
<> 150:02e0a0aed4ec 609 #define _USB_GINTSTS_RESETVALUE 0x14000020UL /**< Default value for USB_GINTSTS */
<> 150:02e0a0aed4ec 610 #define _USB_GINTSTS_MASK 0xF7FCFCFFUL /**< Mask for USB_GINTSTS */
<> 150:02e0a0aed4ec 611 #define USB_GINTSTS_CURMOD (0x1UL << 0) /**< Current Mode of Operation host and device */
<> 150:02e0a0aed4ec 612 #define _USB_GINTSTS_CURMOD_SHIFT 0 /**< Shift value for USB_CURMOD */
<> 150:02e0a0aed4ec 613 #define _USB_GINTSTS_CURMOD_MASK 0x1UL /**< Bit mask for USB_CURMOD */
<> 150:02e0a0aed4ec 614 #define _USB_GINTSTS_CURMOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
<> 150:02e0a0aed4ec 615 #define _USB_GINTSTS_CURMOD_DEVICE 0x00000000UL /**< Mode DEVICE for USB_GINTSTS */
<> 150:02e0a0aed4ec 616 #define _USB_GINTSTS_CURMOD_HOST 0x00000001UL /**< Mode HOST for USB_GINTSTS */
<> 150:02e0a0aed4ec 617 #define USB_GINTSTS_CURMOD_DEFAULT (_USB_GINTSTS_CURMOD_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GINTSTS */
<> 150:02e0a0aed4ec 618 #define USB_GINTSTS_CURMOD_DEVICE (_USB_GINTSTS_CURMOD_DEVICE << 0) /**< Shifted mode DEVICE for USB_GINTSTS */
<> 150:02e0a0aed4ec 619 #define USB_GINTSTS_CURMOD_HOST (_USB_GINTSTS_CURMOD_HOST << 0) /**< Shifted mode HOST for USB_GINTSTS */
<> 150:02e0a0aed4ec 620 #define USB_GINTSTS_MODEMIS (0x1UL << 1) /**< Mode Mismatch Interrupt host and device */
<> 150:02e0a0aed4ec 621 #define _USB_GINTSTS_MODEMIS_SHIFT 1 /**< Shift value for USB_MODEMIS */
<> 150:02e0a0aed4ec 622 #define _USB_GINTSTS_MODEMIS_MASK 0x2UL /**< Bit mask for USB_MODEMIS */
<> 150:02e0a0aed4ec 623 #define _USB_GINTSTS_MODEMIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
<> 150:02e0a0aed4ec 624 #define USB_GINTSTS_MODEMIS_DEFAULT (_USB_GINTSTS_MODEMIS_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_GINTSTS */
<> 150:02e0a0aed4ec 625 #define USB_GINTSTS_OTGINT (0x1UL << 2) /**< OTG Interrupt host and device */
<> 150:02e0a0aed4ec 626 #define _USB_GINTSTS_OTGINT_SHIFT 2 /**< Shift value for USB_OTGINT */
<> 150:02e0a0aed4ec 627 #define _USB_GINTSTS_OTGINT_MASK 0x4UL /**< Bit mask for USB_OTGINT */
<> 150:02e0a0aed4ec 628 #define _USB_GINTSTS_OTGINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
<> 150:02e0a0aed4ec 629 #define USB_GINTSTS_OTGINT_DEFAULT (_USB_GINTSTS_OTGINT_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_GINTSTS */
<> 150:02e0a0aed4ec 630 #define USB_GINTSTS_SOF (0x1UL << 3) /**< Start of Frame host and device */
<> 150:02e0a0aed4ec 631 #define _USB_GINTSTS_SOF_SHIFT 3 /**< Shift value for USB_SOF */
<> 150:02e0a0aed4ec 632 #define _USB_GINTSTS_SOF_MASK 0x8UL /**< Bit mask for USB_SOF */
<> 150:02e0a0aed4ec 633 #define _USB_GINTSTS_SOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
<> 150:02e0a0aed4ec 634 #define USB_GINTSTS_SOF_DEFAULT (_USB_GINTSTS_SOF_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_GINTSTS */
<> 150:02e0a0aed4ec 635 #define USB_GINTSTS_RXFLVL (0x1UL << 4) /**< RxFIFO Non-Empty host and device */
<> 150:02e0a0aed4ec 636 #define _USB_GINTSTS_RXFLVL_SHIFT 4 /**< Shift value for USB_RXFLVL */
<> 150:02e0a0aed4ec 637 #define _USB_GINTSTS_RXFLVL_MASK 0x10UL /**< Bit mask for USB_RXFLVL */
<> 150:02e0a0aed4ec 638 #define _USB_GINTSTS_RXFLVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
<> 150:02e0a0aed4ec 639 #define USB_GINTSTS_RXFLVL_DEFAULT (_USB_GINTSTS_RXFLVL_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_GINTSTS */
<> 150:02e0a0aed4ec 640 #define USB_GINTSTS_NPTXFEMP (0x1UL << 5) /**< Non-Periodic TxFIFO Empty host only */
<> 150:02e0a0aed4ec 641 #define _USB_GINTSTS_NPTXFEMP_SHIFT 5 /**< Shift value for USB_NPTXFEMP */
<> 150:02e0a0aed4ec 642 #define _USB_GINTSTS_NPTXFEMP_MASK 0x20UL /**< Bit mask for USB_NPTXFEMP */
<> 150:02e0a0aed4ec 643 #define _USB_GINTSTS_NPTXFEMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_GINTSTS */
<> 150:02e0a0aed4ec 644 #define USB_GINTSTS_NPTXFEMP_DEFAULT (_USB_GINTSTS_NPTXFEMP_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_GINTSTS */
<> 150:02e0a0aed4ec 645 #define USB_GINTSTS_GINNAKEFF (0x1UL << 6) /**< Global IN Non-periodic NAK Effective device only */
<> 150:02e0a0aed4ec 646 #define _USB_GINTSTS_GINNAKEFF_SHIFT 6 /**< Shift value for USB_GINNAKEFF */
<> 150:02e0a0aed4ec 647 #define _USB_GINTSTS_GINNAKEFF_MASK 0x40UL /**< Bit mask for USB_GINNAKEFF */
<> 150:02e0a0aed4ec 648 #define _USB_GINTSTS_GINNAKEFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
<> 150:02e0a0aed4ec 649 #define USB_GINTSTS_GINNAKEFF_DEFAULT (_USB_GINTSTS_GINNAKEFF_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_GINTSTS */
<> 150:02e0a0aed4ec 650 #define USB_GINTSTS_GOUTNAKEFF (0x1UL << 7) /**< Global OUT NAK Effective device only */
<> 150:02e0a0aed4ec 651 #define _USB_GINTSTS_GOUTNAKEFF_SHIFT 7 /**< Shift value for USB_GOUTNAKEFF */
<> 150:02e0a0aed4ec 652 #define _USB_GINTSTS_GOUTNAKEFF_MASK 0x80UL /**< Bit mask for USB_GOUTNAKEFF */
<> 150:02e0a0aed4ec 653 #define _USB_GINTSTS_GOUTNAKEFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
<> 150:02e0a0aed4ec 654 #define USB_GINTSTS_GOUTNAKEFF_DEFAULT (_USB_GINTSTS_GOUTNAKEFF_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_GINTSTS */
<> 150:02e0a0aed4ec 655 #define USB_GINTSTS_ERLYSUSP (0x1UL << 10) /**< Early Suspend device only */
<> 150:02e0a0aed4ec 656 #define _USB_GINTSTS_ERLYSUSP_SHIFT 10 /**< Shift value for USB_ERLYSUSP */
<> 150:02e0a0aed4ec 657 #define _USB_GINTSTS_ERLYSUSP_MASK 0x400UL /**< Bit mask for USB_ERLYSUSP */
<> 150:02e0a0aed4ec 658 #define _USB_GINTSTS_ERLYSUSP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
<> 150:02e0a0aed4ec 659 #define USB_GINTSTS_ERLYSUSP_DEFAULT (_USB_GINTSTS_ERLYSUSP_DEFAULT << 10) /**< Shifted mode DEFAULT for USB_GINTSTS */
<> 150:02e0a0aed4ec 660 #define USB_GINTSTS_USBSUSP (0x1UL << 11) /**< USB Suspend device only */
<> 150:02e0a0aed4ec 661 #define _USB_GINTSTS_USBSUSP_SHIFT 11 /**< Shift value for USB_USBSUSP */
<> 150:02e0a0aed4ec 662 #define _USB_GINTSTS_USBSUSP_MASK 0x800UL /**< Bit mask for USB_USBSUSP */
<> 150:02e0a0aed4ec 663 #define _USB_GINTSTS_USBSUSP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
<> 150:02e0a0aed4ec 664 #define USB_GINTSTS_USBSUSP_DEFAULT (_USB_GINTSTS_USBSUSP_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_GINTSTS */
<> 150:02e0a0aed4ec 665 #define USB_GINTSTS_USBRST (0x1UL << 12) /**< USB Reset device only */
<> 150:02e0a0aed4ec 666 #define _USB_GINTSTS_USBRST_SHIFT 12 /**< Shift value for USB_USBRST */
<> 150:02e0a0aed4ec 667 #define _USB_GINTSTS_USBRST_MASK 0x1000UL /**< Bit mask for USB_USBRST */
<> 150:02e0a0aed4ec 668 #define _USB_GINTSTS_USBRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
<> 150:02e0a0aed4ec 669 #define USB_GINTSTS_USBRST_DEFAULT (_USB_GINTSTS_USBRST_DEFAULT << 12) /**< Shifted mode DEFAULT for USB_GINTSTS */
<> 150:02e0a0aed4ec 670 #define USB_GINTSTS_ENUMDONE (0x1UL << 13) /**< Enumeration Done device only */
<> 150:02e0a0aed4ec 671 #define _USB_GINTSTS_ENUMDONE_SHIFT 13 /**< Shift value for USB_ENUMDONE */
<> 150:02e0a0aed4ec 672 #define _USB_GINTSTS_ENUMDONE_MASK 0x2000UL /**< Bit mask for USB_ENUMDONE */
<> 150:02e0a0aed4ec 673 #define _USB_GINTSTS_ENUMDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
<> 150:02e0a0aed4ec 674 #define USB_GINTSTS_ENUMDONE_DEFAULT (_USB_GINTSTS_ENUMDONE_DEFAULT << 13) /**< Shifted mode DEFAULT for USB_GINTSTS */
<> 150:02e0a0aed4ec 675 #define USB_GINTSTS_ISOOUTDROP (0x1UL << 14) /**< Isochronous OUT Packet Dropped Interrupt device only */
<> 150:02e0a0aed4ec 676 #define _USB_GINTSTS_ISOOUTDROP_SHIFT 14 /**< Shift value for USB_ISOOUTDROP */
<> 150:02e0a0aed4ec 677 #define _USB_GINTSTS_ISOOUTDROP_MASK 0x4000UL /**< Bit mask for USB_ISOOUTDROP */
<> 150:02e0a0aed4ec 678 #define _USB_GINTSTS_ISOOUTDROP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
<> 150:02e0a0aed4ec 679 #define USB_GINTSTS_ISOOUTDROP_DEFAULT (_USB_GINTSTS_ISOOUTDROP_DEFAULT << 14) /**< Shifted mode DEFAULT for USB_GINTSTS */
<> 150:02e0a0aed4ec 680 #define USB_GINTSTS_EOPF (0x1UL << 15) /**< End of Periodic Frame Interrupt */
<> 150:02e0a0aed4ec 681 #define _USB_GINTSTS_EOPF_SHIFT 15 /**< Shift value for USB_EOPF */
<> 150:02e0a0aed4ec 682 #define _USB_GINTSTS_EOPF_MASK 0x8000UL /**< Bit mask for USB_EOPF */
<> 150:02e0a0aed4ec 683 #define _USB_GINTSTS_EOPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
<> 150:02e0a0aed4ec 684 #define USB_GINTSTS_EOPF_DEFAULT (_USB_GINTSTS_EOPF_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_GINTSTS */
<> 150:02e0a0aed4ec 685 #define USB_GINTSTS_IEPINT (0x1UL << 18) /**< IN Endpoints Interrupt device only */
<> 150:02e0a0aed4ec 686 #define _USB_GINTSTS_IEPINT_SHIFT 18 /**< Shift value for USB_IEPINT */
<> 150:02e0a0aed4ec 687 #define _USB_GINTSTS_IEPINT_MASK 0x40000UL /**< Bit mask for USB_IEPINT */
<> 150:02e0a0aed4ec 688 #define _USB_GINTSTS_IEPINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
<> 150:02e0a0aed4ec 689 #define USB_GINTSTS_IEPINT_DEFAULT (_USB_GINTSTS_IEPINT_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_GINTSTS */
<> 150:02e0a0aed4ec 690 #define USB_GINTSTS_OEPINT (0x1UL << 19) /**< OUT Endpoints Interrupt device only */
<> 150:02e0a0aed4ec 691 #define _USB_GINTSTS_OEPINT_SHIFT 19 /**< Shift value for USB_OEPINT */
<> 150:02e0a0aed4ec 692 #define _USB_GINTSTS_OEPINT_MASK 0x80000UL /**< Bit mask for USB_OEPINT */
<> 150:02e0a0aed4ec 693 #define _USB_GINTSTS_OEPINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
<> 150:02e0a0aed4ec 694 #define USB_GINTSTS_OEPINT_DEFAULT (_USB_GINTSTS_OEPINT_DEFAULT << 19) /**< Shifted mode DEFAULT for USB_GINTSTS */
<> 150:02e0a0aed4ec 695 #define USB_GINTSTS_INCOMPISOIN (0x1UL << 20) /**< Incomplete Isochronous IN Transfer device only */
<> 150:02e0a0aed4ec 696 #define _USB_GINTSTS_INCOMPISOIN_SHIFT 20 /**< Shift value for USB_INCOMPISOIN */
<> 150:02e0a0aed4ec 697 #define _USB_GINTSTS_INCOMPISOIN_MASK 0x100000UL /**< Bit mask for USB_INCOMPISOIN */
<> 150:02e0a0aed4ec 698 #define _USB_GINTSTS_INCOMPISOIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
<> 150:02e0a0aed4ec 699 #define USB_GINTSTS_INCOMPISOIN_DEFAULT (_USB_GINTSTS_INCOMPISOIN_DEFAULT << 20) /**< Shifted mode DEFAULT for USB_GINTSTS */
<> 150:02e0a0aed4ec 700 #define USB_GINTSTS_INCOMPLP (0x1UL << 21) /**< Incomplete Periodic Transfer host and device */
<> 150:02e0a0aed4ec 701 #define _USB_GINTSTS_INCOMPLP_SHIFT 21 /**< Shift value for USB_INCOMPLP */
<> 150:02e0a0aed4ec 702 #define _USB_GINTSTS_INCOMPLP_MASK 0x200000UL /**< Bit mask for USB_INCOMPLP */
<> 150:02e0a0aed4ec 703 #define _USB_GINTSTS_INCOMPLP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
<> 150:02e0a0aed4ec 704 #define USB_GINTSTS_INCOMPLP_DEFAULT (_USB_GINTSTS_INCOMPLP_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_GINTSTS */
<> 150:02e0a0aed4ec 705 #define USB_GINTSTS_FETSUSP (0x1UL << 22) /**< Data Fetch Suspended device only */
<> 150:02e0a0aed4ec 706 #define _USB_GINTSTS_FETSUSP_SHIFT 22 /**< Shift value for USB_FETSUSP */
<> 150:02e0a0aed4ec 707 #define _USB_GINTSTS_FETSUSP_MASK 0x400000UL /**< Bit mask for USB_FETSUSP */
<> 150:02e0a0aed4ec 708 #define _USB_GINTSTS_FETSUSP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
<> 150:02e0a0aed4ec 709 #define USB_GINTSTS_FETSUSP_DEFAULT (_USB_GINTSTS_FETSUSP_DEFAULT << 22) /**< Shifted mode DEFAULT for USB_GINTSTS */
<> 150:02e0a0aed4ec 710 #define USB_GINTSTS_RESETDET (0x1UL << 23) /**< Reset detected Interrupt device only */
<> 150:02e0a0aed4ec 711 #define _USB_GINTSTS_RESETDET_SHIFT 23 /**< Shift value for USB_RESETDET */
<> 150:02e0a0aed4ec 712 #define _USB_GINTSTS_RESETDET_MASK 0x800000UL /**< Bit mask for USB_RESETDET */
<> 150:02e0a0aed4ec 713 #define _USB_GINTSTS_RESETDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
<> 150:02e0a0aed4ec 714 #define USB_GINTSTS_RESETDET_DEFAULT (_USB_GINTSTS_RESETDET_DEFAULT << 23) /**< Shifted mode DEFAULT for USB_GINTSTS */
<> 150:02e0a0aed4ec 715 #define USB_GINTSTS_PRTINT (0x1UL << 24) /**< Host Port Interrupt host only */
<> 150:02e0a0aed4ec 716 #define _USB_GINTSTS_PRTINT_SHIFT 24 /**< Shift value for USB_PRTINT */
<> 150:02e0a0aed4ec 717 #define _USB_GINTSTS_PRTINT_MASK 0x1000000UL /**< Bit mask for USB_PRTINT */
<> 150:02e0a0aed4ec 718 #define _USB_GINTSTS_PRTINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
<> 150:02e0a0aed4ec 719 #define USB_GINTSTS_PRTINT_DEFAULT (_USB_GINTSTS_PRTINT_DEFAULT << 24) /**< Shifted mode DEFAULT for USB_GINTSTS */
<> 150:02e0a0aed4ec 720 #define USB_GINTSTS_HCHINT (0x1UL << 25) /**< Host Channels Interrupt host only */
<> 150:02e0a0aed4ec 721 #define _USB_GINTSTS_HCHINT_SHIFT 25 /**< Shift value for USB_HCHINT */
<> 150:02e0a0aed4ec 722 #define _USB_GINTSTS_HCHINT_MASK 0x2000000UL /**< Bit mask for USB_HCHINT */
<> 150:02e0a0aed4ec 723 #define _USB_GINTSTS_HCHINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
<> 150:02e0a0aed4ec 724 #define USB_GINTSTS_HCHINT_DEFAULT (_USB_GINTSTS_HCHINT_DEFAULT << 25) /**< Shifted mode DEFAULT for USB_GINTSTS */
<> 150:02e0a0aed4ec 725 #define USB_GINTSTS_PTXFEMP (0x1UL << 26) /**< Periodic TxFIFO Empty host only */
<> 150:02e0a0aed4ec 726 #define _USB_GINTSTS_PTXFEMP_SHIFT 26 /**< Shift value for USB_PTXFEMP */
<> 150:02e0a0aed4ec 727 #define _USB_GINTSTS_PTXFEMP_MASK 0x4000000UL /**< Bit mask for USB_PTXFEMP */
<> 150:02e0a0aed4ec 728 #define _USB_GINTSTS_PTXFEMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_GINTSTS */
<> 150:02e0a0aed4ec 729 #define USB_GINTSTS_PTXFEMP_DEFAULT (_USB_GINTSTS_PTXFEMP_DEFAULT << 26) /**< Shifted mode DEFAULT for USB_GINTSTS */
<> 150:02e0a0aed4ec 730 #define USB_GINTSTS_CONIDSTSCHNG (0x1UL << 28) /**< Connector ID Status Change host and device */
<> 150:02e0a0aed4ec 731 #define _USB_GINTSTS_CONIDSTSCHNG_SHIFT 28 /**< Shift value for USB_CONIDSTSCHNG */
<> 150:02e0a0aed4ec 732 #define _USB_GINTSTS_CONIDSTSCHNG_MASK 0x10000000UL /**< Bit mask for USB_CONIDSTSCHNG */
<> 150:02e0a0aed4ec 733 #define _USB_GINTSTS_CONIDSTSCHNG_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_GINTSTS */
<> 150:02e0a0aed4ec 734 #define USB_GINTSTS_CONIDSTSCHNG_DEFAULT (_USB_GINTSTS_CONIDSTSCHNG_DEFAULT << 28) /**< Shifted mode DEFAULT for USB_GINTSTS */
<> 150:02e0a0aed4ec 735 #define USB_GINTSTS_DISCONNINT (0x1UL << 29) /**< Disconnect Detected Interrupt host only */
<> 150:02e0a0aed4ec 736 #define _USB_GINTSTS_DISCONNINT_SHIFT 29 /**< Shift value for USB_DISCONNINT */
<> 150:02e0a0aed4ec 737 #define _USB_GINTSTS_DISCONNINT_MASK 0x20000000UL /**< Bit mask for USB_DISCONNINT */
<> 150:02e0a0aed4ec 738 #define _USB_GINTSTS_DISCONNINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
<> 150:02e0a0aed4ec 739 #define USB_GINTSTS_DISCONNINT_DEFAULT (_USB_GINTSTS_DISCONNINT_DEFAULT << 29) /**< Shifted mode DEFAULT for USB_GINTSTS */
<> 150:02e0a0aed4ec 740 #define USB_GINTSTS_SESSREQINT (0x1UL << 30) /**< Session Request/New Session Detected Interrupt host and device */
<> 150:02e0a0aed4ec 741 #define _USB_GINTSTS_SESSREQINT_SHIFT 30 /**< Shift value for USB_SESSREQINT */
<> 150:02e0a0aed4ec 742 #define _USB_GINTSTS_SESSREQINT_MASK 0x40000000UL /**< Bit mask for USB_SESSREQINT */
<> 150:02e0a0aed4ec 743 #define _USB_GINTSTS_SESSREQINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
<> 150:02e0a0aed4ec 744 #define USB_GINTSTS_SESSREQINT_DEFAULT (_USB_GINTSTS_SESSREQINT_DEFAULT << 30) /**< Shifted mode DEFAULT for USB_GINTSTS */
<> 150:02e0a0aed4ec 745 #define USB_GINTSTS_WKUPINT (0x1UL << 31) /**< Resume/Remote Wakeup Detected Interrupt host and device */
<> 150:02e0a0aed4ec 746 #define _USB_GINTSTS_WKUPINT_SHIFT 31 /**< Shift value for USB_WKUPINT */
<> 150:02e0a0aed4ec 747 #define _USB_GINTSTS_WKUPINT_MASK 0x80000000UL /**< Bit mask for USB_WKUPINT */
<> 150:02e0a0aed4ec 748 #define _USB_GINTSTS_WKUPINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
<> 150:02e0a0aed4ec 749 #define USB_GINTSTS_WKUPINT_DEFAULT (_USB_GINTSTS_WKUPINT_DEFAULT << 31) /**< Shifted mode DEFAULT for USB_GINTSTS */
<> 150:02e0a0aed4ec 750
<> 150:02e0a0aed4ec 751 /* Bit fields for USB GINTMSK */
<> 150:02e0a0aed4ec 752 #define _USB_GINTMSK_RESETVALUE 0x00000000UL /**< Default value for USB_GINTMSK */
<> 150:02e0a0aed4ec 753 #define _USB_GINTMSK_MASK 0xF7FCFCFEUL /**< Mask for USB_GINTMSK */
<> 150:02e0a0aed4ec 754 #define USB_GINTMSK_MODEMISMSK (0x1UL << 1) /**< Mode Mismatch Interrupt Mask host and device */
<> 150:02e0a0aed4ec 755 #define _USB_GINTMSK_MODEMISMSK_SHIFT 1 /**< Shift value for USB_MODEMISMSK */
<> 150:02e0a0aed4ec 756 #define _USB_GINTMSK_MODEMISMSK_MASK 0x2UL /**< Bit mask for USB_MODEMISMSK */
<> 150:02e0a0aed4ec 757 #define _USB_GINTMSK_MODEMISMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
<> 150:02e0a0aed4ec 758 #define USB_GINTMSK_MODEMISMSK_DEFAULT (_USB_GINTMSK_MODEMISMSK_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_GINTMSK */
<> 150:02e0a0aed4ec 759 #define USB_GINTMSK_OTGINTMSK (0x1UL << 2) /**< OTG Interrupt Mask host and device */
<> 150:02e0a0aed4ec 760 #define _USB_GINTMSK_OTGINTMSK_SHIFT 2 /**< Shift value for USB_OTGINTMSK */
<> 150:02e0a0aed4ec 761 #define _USB_GINTMSK_OTGINTMSK_MASK 0x4UL /**< Bit mask for USB_OTGINTMSK */
<> 150:02e0a0aed4ec 762 #define _USB_GINTMSK_OTGINTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
<> 150:02e0a0aed4ec 763 #define USB_GINTMSK_OTGINTMSK_DEFAULT (_USB_GINTMSK_OTGINTMSK_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_GINTMSK */
<> 150:02e0a0aed4ec 764 #define USB_GINTMSK_SOFMSK (0x1UL << 3) /**< Start of Frame Mask host and device */
<> 150:02e0a0aed4ec 765 #define _USB_GINTMSK_SOFMSK_SHIFT 3 /**< Shift value for USB_SOFMSK */
<> 150:02e0a0aed4ec 766 #define _USB_GINTMSK_SOFMSK_MASK 0x8UL /**< Bit mask for USB_SOFMSK */
<> 150:02e0a0aed4ec 767 #define _USB_GINTMSK_SOFMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
<> 150:02e0a0aed4ec 768 #define USB_GINTMSK_SOFMSK_DEFAULT (_USB_GINTMSK_SOFMSK_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_GINTMSK */
<> 150:02e0a0aed4ec 769 #define USB_GINTMSK_RXFLVLMSK (0x1UL << 4) /**< Receive FIFO Non-Empty Mask host and device */
<> 150:02e0a0aed4ec 770 #define _USB_GINTMSK_RXFLVLMSK_SHIFT 4 /**< Shift value for USB_RXFLVLMSK */
<> 150:02e0a0aed4ec 771 #define _USB_GINTMSK_RXFLVLMSK_MASK 0x10UL /**< Bit mask for USB_RXFLVLMSK */
<> 150:02e0a0aed4ec 772 #define _USB_GINTMSK_RXFLVLMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
<> 150:02e0a0aed4ec 773 #define USB_GINTMSK_RXFLVLMSK_DEFAULT (_USB_GINTMSK_RXFLVLMSK_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_GINTMSK */
<> 150:02e0a0aed4ec 774 #define USB_GINTMSK_NPTXFEMPMSK (0x1UL << 5) /**< Non-Periodic TxFIFO Empty Mask host only */
<> 150:02e0a0aed4ec 775 #define _USB_GINTMSK_NPTXFEMPMSK_SHIFT 5 /**< Shift value for USB_NPTXFEMPMSK */
<> 150:02e0a0aed4ec 776 #define _USB_GINTMSK_NPTXFEMPMSK_MASK 0x20UL /**< Bit mask for USB_NPTXFEMPMSK */
<> 150:02e0a0aed4ec 777 #define _USB_GINTMSK_NPTXFEMPMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
<> 150:02e0a0aed4ec 778 #define USB_GINTMSK_NPTXFEMPMSK_DEFAULT (_USB_GINTMSK_NPTXFEMPMSK_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_GINTMSK */
<> 150:02e0a0aed4ec 779 #define USB_GINTMSK_GINNAKEFFMSK (0x1UL << 6) /**< Global Non-periodic IN NAK Effective Mask device only */
<> 150:02e0a0aed4ec 780 #define _USB_GINTMSK_GINNAKEFFMSK_SHIFT 6 /**< Shift value for USB_GINNAKEFFMSK */
<> 150:02e0a0aed4ec 781 #define _USB_GINTMSK_GINNAKEFFMSK_MASK 0x40UL /**< Bit mask for USB_GINNAKEFFMSK */
<> 150:02e0a0aed4ec 782 #define _USB_GINTMSK_GINNAKEFFMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
<> 150:02e0a0aed4ec 783 #define USB_GINTMSK_GINNAKEFFMSK_DEFAULT (_USB_GINTMSK_GINNAKEFFMSK_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_GINTMSK */
<> 150:02e0a0aed4ec 784 #define USB_GINTMSK_GOUTNAKEFFMSK (0x1UL << 7) /**< Global OUT NAK Effective Mask device only */
<> 150:02e0a0aed4ec 785 #define _USB_GINTMSK_GOUTNAKEFFMSK_SHIFT 7 /**< Shift value for USB_GOUTNAKEFFMSK */
<> 150:02e0a0aed4ec 786 #define _USB_GINTMSK_GOUTNAKEFFMSK_MASK 0x80UL /**< Bit mask for USB_GOUTNAKEFFMSK */
<> 150:02e0a0aed4ec 787 #define _USB_GINTMSK_GOUTNAKEFFMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
<> 150:02e0a0aed4ec 788 #define USB_GINTMSK_GOUTNAKEFFMSK_DEFAULT (_USB_GINTMSK_GOUTNAKEFFMSK_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_GINTMSK */
<> 150:02e0a0aed4ec 789 #define USB_GINTMSK_ERLYSUSPMSK (0x1UL << 10) /**< Early Suspend Mask device only */
<> 150:02e0a0aed4ec 790 #define _USB_GINTMSK_ERLYSUSPMSK_SHIFT 10 /**< Shift value for USB_ERLYSUSPMSK */
<> 150:02e0a0aed4ec 791 #define _USB_GINTMSK_ERLYSUSPMSK_MASK 0x400UL /**< Bit mask for USB_ERLYSUSPMSK */
<> 150:02e0a0aed4ec 792 #define _USB_GINTMSK_ERLYSUSPMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
<> 150:02e0a0aed4ec 793 #define USB_GINTMSK_ERLYSUSPMSK_DEFAULT (_USB_GINTMSK_ERLYSUSPMSK_DEFAULT << 10) /**< Shifted mode DEFAULT for USB_GINTMSK */
<> 150:02e0a0aed4ec 794 #define USB_GINTMSK_USBSUSPMSK (0x1UL << 11) /**< USB Suspend Mask device only */
<> 150:02e0a0aed4ec 795 #define _USB_GINTMSK_USBSUSPMSK_SHIFT 11 /**< Shift value for USB_USBSUSPMSK */
<> 150:02e0a0aed4ec 796 #define _USB_GINTMSK_USBSUSPMSK_MASK 0x800UL /**< Bit mask for USB_USBSUSPMSK */
<> 150:02e0a0aed4ec 797 #define _USB_GINTMSK_USBSUSPMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
<> 150:02e0a0aed4ec 798 #define USB_GINTMSK_USBSUSPMSK_DEFAULT (_USB_GINTMSK_USBSUSPMSK_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_GINTMSK */
<> 150:02e0a0aed4ec 799 #define USB_GINTMSK_USBRSTMSK (0x1UL << 12) /**< USB Reset Mask device only */
<> 150:02e0a0aed4ec 800 #define _USB_GINTMSK_USBRSTMSK_SHIFT 12 /**< Shift value for USB_USBRSTMSK */
<> 150:02e0a0aed4ec 801 #define _USB_GINTMSK_USBRSTMSK_MASK 0x1000UL /**< Bit mask for USB_USBRSTMSK */
<> 150:02e0a0aed4ec 802 #define _USB_GINTMSK_USBRSTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
<> 150:02e0a0aed4ec 803 #define USB_GINTMSK_USBRSTMSK_DEFAULT (_USB_GINTMSK_USBRSTMSK_DEFAULT << 12) /**< Shifted mode DEFAULT for USB_GINTMSK */
<> 150:02e0a0aed4ec 804 #define USB_GINTMSK_ENUMDONEMSK (0x1UL << 13) /**< Enumeration Done Mask device only */
<> 150:02e0a0aed4ec 805 #define _USB_GINTMSK_ENUMDONEMSK_SHIFT 13 /**< Shift value for USB_ENUMDONEMSK */
<> 150:02e0a0aed4ec 806 #define _USB_GINTMSK_ENUMDONEMSK_MASK 0x2000UL /**< Bit mask for USB_ENUMDONEMSK */
<> 150:02e0a0aed4ec 807 #define _USB_GINTMSK_ENUMDONEMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
<> 150:02e0a0aed4ec 808 #define USB_GINTMSK_ENUMDONEMSK_DEFAULT (_USB_GINTMSK_ENUMDONEMSK_DEFAULT << 13) /**< Shifted mode DEFAULT for USB_GINTMSK */
<> 150:02e0a0aed4ec 809 #define USB_GINTMSK_ISOOUTDROPMSK (0x1UL << 14) /**< Isochronous OUT Packet Dropped Interrupt Mask device only */
<> 150:02e0a0aed4ec 810 #define _USB_GINTMSK_ISOOUTDROPMSK_SHIFT 14 /**< Shift value for USB_ISOOUTDROPMSK */
<> 150:02e0a0aed4ec 811 #define _USB_GINTMSK_ISOOUTDROPMSK_MASK 0x4000UL /**< Bit mask for USB_ISOOUTDROPMSK */
<> 150:02e0a0aed4ec 812 #define _USB_GINTMSK_ISOOUTDROPMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
<> 150:02e0a0aed4ec 813 #define USB_GINTMSK_ISOOUTDROPMSK_DEFAULT (_USB_GINTMSK_ISOOUTDROPMSK_DEFAULT << 14) /**< Shifted mode DEFAULT for USB_GINTMSK */
<> 150:02e0a0aed4ec 814 #define USB_GINTMSK_EOPFMSK (0x1UL << 15) /**< End of Periodic Frame Interrupt Mask device only */
<> 150:02e0a0aed4ec 815 #define _USB_GINTMSK_EOPFMSK_SHIFT 15 /**< Shift value for USB_EOPFMSK */
<> 150:02e0a0aed4ec 816 #define _USB_GINTMSK_EOPFMSK_MASK 0x8000UL /**< Bit mask for USB_EOPFMSK */
<> 150:02e0a0aed4ec 817 #define _USB_GINTMSK_EOPFMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
<> 150:02e0a0aed4ec 818 #define USB_GINTMSK_EOPFMSK_DEFAULT (_USB_GINTMSK_EOPFMSK_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_GINTMSK */
<> 150:02e0a0aed4ec 819 #define USB_GINTMSK_IEPINTMSK (0x1UL << 18) /**< IN Endpoints Interrupt Mask device only */
<> 150:02e0a0aed4ec 820 #define _USB_GINTMSK_IEPINTMSK_SHIFT 18 /**< Shift value for USB_IEPINTMSK */
<> 150:02e0a0aed4ec 821 #define _USB_GINTMSK_IEPINTMSK_MASK 0x40000UL /**< Bit mask for USB_IEPINTMSK */
<> 150:02e0a0aed4ec 822 #define _USB_GINTMSK_IEPINTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
<> 150:02e0a0aed4ec 823 #define USB_GINTMSK_IEPINTMSK_DEFAULT (_USB_GINTMSK_IEPINTMSK_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_GINTMSK */
<> 150:02e0a0aed4ec 824 #define USB_GINTMSK_OEPINTMSK (0x1UL << 19) /**< OUT Endpoints Interrupt Mask device only */
<> 150:02e0a0aed4ec 825 #define _USB_GINTMSK_OEPINTMSK_SHIFT 19 /**< Shift value for USB_OEPINTMSK */
<> 150:02e0a0aed4ec 826 #define _USB_GINTMSK_OEPINTMSK_MASK 0x80000UL /**< Bit mask for USB_OEPINTMSK */
<> 150:02e0a0aed4ec 827 #define _USB_GINTMSK_OEPINTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
<> 150:02e0a0aed4ec 828 #define USB_GINTMSK_OEPINTMSK_DEFAULT (_USB_GINTMSK_OEPINTMSK_DEFAULT << 19) /**< Shifted mode DEFAULT for USB_GINTMSK */
<> 150:02e0a0aed4ec 829 #define USB_GINTMSK_INCOMPISOINMSK (0x1UL << 20) /**< Incomplete Isochronous IN Transfer Mask device only */
<> 150:02e0a0aed4ec 830 #define _USB_GINTMSK_INCOMPISOINMSK_SHIFT 20 /**< Shift value for USB_INCOMPISOINMSK */
<> 150:02e0a0aed4ec 831 #define _USB_GINTMSK_INCOMPISOINMSK_MASK 0x100000UL /**< Bit mask for USB_INCOMPISOINMSK */
<> 150:02e0a0aed4ec 832 #define _USB_GINTMSK_INCOMPISOINMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
<> 150:02e0a0aed4ec 833 #define USB_GINTMSK_INCOMPISOINMSK_DEFAULT (_USB_GINTMSK_INCOMPISOINMSK_DEFAULT << 20) /**< Shifted mode DEFAULT for USB_GINTMSK */
<> 150:02e0a0aed4ec 834 #define USB_GINTMSK_INCOMPLPMSK (0x1UL << 21) /**< Incomplete Periodic Transfer Mask host and device */
<> 150:02e0a0aed4ec 835 #define _USB_GINTMSK_INCOMPLPMSK_SHIFT 21 /**< Shift value for USB_INCOMPLPMSK */
<> 150:02e0a0aed4ec 836 #define _USB_GINTMSK_INCOMPLPMSK_MASK 0x200000UL /**< Bit mask for USB_INCOMPLPMSK */
<> 150:02e0a0aed4ec 837 #define _USB_GINTMSK_INCOMPLPMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
<> 150:02e0a0aed4ec 838 #define USB_GINTMSK_INCOMPLPMSK_DEFAULT (_USB_GINTMSK_INCOMPLPMSK_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_GINTMSK */
<> 150:02e0a0aed4ec 839 #define USB_GINTMSK_FETSUSPMSK (0x1UL << 22) /**< Data Fetch Suspended Mask device only */
<> 150:02e0a0aed4ec 840 #define _USB_GINTMSK_FETSUSPMSK_SHIFT 22 /**< Shift value for USB_FETSUSPMSK */
<> 150:02e0a0aed4ec 841 #define _USB_GINTMSK_FETSUSPMSK_MASK 0x400000UL /**< Bit mask for USB_FETSUSPMSK */
<> 150:02e0a0aed4ec 842 #define _USB_GINTMSK_FETSUSPMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
<> 150:02e0a0aed4ec 843 #define USB_GINTMSK_FETSUSPMSK_DEFAULT (_USB_GINTMSK_FETSUSPMSK_DEFAULT << 22) /**< Shifted mode DEFAULT for USB_GINTMSK */
<> 150:02e0a0aed4ec 844 #define USB_GINTMSK_RESETDETMSK (0x1UL << 23) /**< Reset detected Interrupt Mask device only */
<> 150:02e0a0aed4ec 845 #define _USB_GINTMSK_RESETDETMSK_SHIFT 23 /**< Shift value for USB_RESETDETMSK */
<> 150:02e0a0aed4ec 846 #define _USB_GINTMSK_RESETDETMSK_MASK 0x800000UL /**< Bit mask for USB_RESETDETMSK */
<> 150:02e0a0aed4ec 847 #define _USB_GINTMSK_RESETDETMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
<> 150:02e0a0aed4ec 848 #define USB_GINTMSK_RESETDETMSK_DEFAULT (_USB_GINTMSK_RESETDETMSK_DEFAULT << 23) /**< Shifted mode DEFAULT for USB_GINTMSK */
<> 150:02e0a0aed4ec 849 #define USB_GINTMSK_PRTINTMSK (0x1UL << 24) /**< Host Port Interrupt Mask host only */
<> 150:02e0a0aed4ec 850 #define _USB_GINTMSK_PRTINTMSK_SHIFT 24 /**< Shift value for USB_PRTINTMSK */
<> 150:02e0a0aed4ec 851 #define _USB_GINTMSK_PRTINTMSK_MASK 0x1000000UL /**< Bit mask for USB_PRTINTMSK */
<> 150:02e0a0aed4ec 852 #define _USB_GINTMSK_PRTINTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
<> 150:02e0a0aed4ec 853 #define USB_GINTMSK_PRTINTMSK_DEFAULT (_USB_GINTMSK_PRTINTMSK_DEFAULT << 24) /**< Shifted mode DEFAULT for USB_GINTMSK */
<> 150:02e0a0aed4ec 854 #define USB_GINTMSK_HCHINTMSK (0x1UL << 25) /**< Host Channels Interrupt Mask host only */
<> 150:02e0a0aed4ec 855 #define _USB_GINTMSK_HCHINTMSK_SHIFT 25 /**< Shift value for USB_HCHINTMSK */
<> 150:02e0a0aed4ec 856 #define _USB_GINTMSK_HCHINTMSK_MASK 0x2000000UL /**< Bit mask for USB_HCHINTMSK */
<> 150:02e0a0aed4ec 857 #define _USB_GINTMSK_HCHINTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
<> 150:02e0a0aed4ec 858 #define USB_GINTMSK_HCHINTMSK_DEFAULT (_USB_GINTMSK_HCHINTMSK_DEFAULT << 25) /**< Shifted mode DEFAULT for USB_GINTMSK */
<> 150:02e0a0aed4ec 859 #define USB_GINTMSK_PTXFEMPMSK (0x1UL << 26) /**< Periodic TxFIFO Empty Mask host only */
<> 150:02e0a0aed4ec 860 #define _USB_GINTMSK_PTXFEMPMSK_SHIFT 26 /**< Shift value for USB_PTXFEMPMSK */
<> 150:02e0a0aed4ec 861 #define _USB_GINTMSK_PTXFEMPMSK_MASK 0x4000000UL /**< Bit mask for USB_PTXFEMPMSK */
<> 150:02e0a0aed4ec 862 #define _USB_GINTMSK_PTXFEMPMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
<> 150:02e0a0aed4ec 863 #define USB_GINTMSK_PTXFEMPMSK_DEFAULT (_USB_GINTMSK_PTXFEMPMSK_DEFAULT << 26) /**< Shifted mode DEFAULT for USB_GINTMSK */
<> 150:02e0a0aed4ec 864 #define USB_GINTMSK_CONIDSTSCHNGMSK (0x1UL << 28) /**< Connector ID Status Change Mask host and device */
<> 150:02e0a0aed4ec 865 #define _USB_GINTMSK_CONIDSTSCHNGMSK_SHIFT 28 /**< Shift value for USB_CONIDSTSCHNGMSK */
<> 150:02e0a0aed4ec 866 #define _USB_GINTMSK_CONIDSTSCHNGMSK_MASK 0x10000000UL /**< Bit mask for USB_CONIDSTSCHNGMSK */
<> 150:02e0a0aed4ec 867 #define _USB_GINTMSK_CONIDSTSCHNGMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
<> 150:02e0a0aed4ec 868 #define USB_GINTMSK_CONIDSTSCHNGMSK_DEFAULT (_USB_GINTMSK_CONIDSTSCHNGMSK_DEFAULT << 28) /**< Shifted mode DEFAULT for USB_GINTMSK */
<> 150:02e0a0aed4ec 869 #define USB_GINTMSK_DISCONNINTMSK (0x1UL << 29) /**< Disconnect Detected Interrupt Mask host and device */
<> 150:02e0a0aed4ec 870 #define _USB_GINTMSK_DISCONNINTMSK_SHIFT 29 /**< Shift value for USB_DISCONNINTMSK */
<> 150:02e0a0aed4ec 871 #define _USB_GINTMSK_DISCONNINTMSK_MASK 0x20000000UL /**< Bit mask for USB_DISCONNINTMSK */
<> 150:02e0a0aed4ec 872 #define _USB_GINTMSK_DISCONNINTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
<> 150:02e0a0aed4ec 873 #define USB_GINTMSK_DISCONNINTMSK_DEFAULT (_USB_GINTMSK_DISCONNINTMSK_DEFAULT << 29) /**< Shifted mode DEFAULT for USB_GINTMSK */
<> 150:02e0a0aed4ec 874 #define USB_GINTMSK_SESSREQINTMSK (0x1UL << 30) /**< Session Request/New Session Detected Interrupt Mask host and device */
<> 150:02e0a0aed4ec 875 #define _USB_GINTMSK_SESSREQINTMSK_SHIFT 30 /**< Shift value for USB_SESSREQINTMSK */
<> 150:02e0a0aed4ec 876 #define _USB_GINTMSK_SESSREQINTMSK_MASK 0x40000000UL /**< Bit mask for USB_SESSREQINTMSK */
<> 150:02e0a0aed4ec 877 #define _USB_GINTMSK_SESSREQINTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
<> 150:02e0a0aed4ec 878 #define USB_GINTMSK_SESSREQINTMSK_DEFAULT (_USB_GINTMSK_SESSREQINTMSK_DEFAULT << 30) /**< Shifted mode DEFAULT for USB_GINTMSK */
<> 150:02e0a0aed4ec 879 #define USB_GINTMSK_WKUPINTMSK (0x1UL << 31) /**< Resume/Remote Wakeup Detected Interrupt Mask host and device */
<> 150:02e0a0aed4ec 880 #define _USB_GINTMSK_WKUPINTMSK_SHIFT 31 /**< Shift value for USB_WKUPINTMSK */
<> 150:02e0a0aed4ec 881 #define _USB_GINTMSK_WKUPINTMSK_MASK 0x80000000UL /**< Bit mask for USB_WKUPINTMSK */
<> 150:02e0a0aed4ec 882 #define _USB_GINTMSK_WKUPINTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
<> 150:02e0a0aed4ec 883 #define USB_GINTMSK_WKUPINTMSK_DEFAULT (_USB_GINTMSK_WKUPINTMSK_DEFAULT << 31) /**< Shifted mode DEFAULT for USB_GINTMSK */
<> 150:02e0a0aed4ec 884
<> 150:02e0a0aed4ec 885 /* Bit fields for USB GRXSTSR */
<> 150:02e0a0aed4ec 886 #define _USB_GRXSTSR_RESETVALUE 0x00000000UL /**< Default value for USB_GRXSTSR */
<> 150:02e0a0aed4ec 887 #define _USB_GRXSTSR_MASK 0x01FFFFFFUL /**< Mask for USB_GRXSTSR */
<> 150:02e0a0aed4ec 888 #define _USB_GRXSTSR_CHEPNUM_SHIFT 0 /**< Shift value for USB_CHEPNUM */
<> 150:02e0a0aed4ec 889 #define _USB_GRXSTSR_CHEPNUM_MASK 0xFUL /**< Bit mask for USB_CHEPNUM */
<> 150:02e0a0aed4ec 890 #define _USB_GRXSTSR_CHEPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRXSTSR */
<> 150:02e0a0aed4ec 891 #define USB_GRXSTSR_CHEPNUM_DEFAULT (_USB_GRXSTSR_CHEPNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GRXSTSR */
<> 150:02e0a0aed4ec 892 #define _USB_GRXSTSR_BCNT_SHIFT 4 /**< Shift value for USB_BCNT */
<> 150:02e0a0aed4ec 893 #define _USB_GRXSTSR_BCNT_MASK 0x7FF0UL /**< Bit mask for USB_BCNT */
<> 150:02e0a0aed4ec 894 #define _USB_GRXSTSR_BCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRXSTSR */
<> 150:02e0a0aed4ec 895 #define USB_GRXSTSR_BCNT_DEFAULT (_USB_GRXSTSR_BCNT_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_GRXSTSR */
<> 150:02e0a0aed4ec 896 #define _USB_GRXSTSR_DPID_SHIFT 15 /**< Shift value for USB_DPID */
<> 150:02e0a0aed4ec 897 #define _USB_GRXSTSR_DPID_MASK 0x18000UL /**< Bit mask for USB_DPID */
<> 150:02e0a0aed4ec 898 #define _USB_GRXSTSR_DPID_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRXSTSR */
<> 150:02e0a0aed4ec 899 #define _USB_GRXSTSR_DPID_DATA0 0x00000000UL /**< Mode DATA0 for USB_GRXSTSR */
<> 150:02e0a0aed4ec 900 #define _USB_GRXSTSR_DPID_DATA1 0x00000001UL /**< Mode DATA1 for USB_GRXSTSR */
<> 150:02e0a0aed4ec 901 #define _USB_GRXSTSR_DPID_DATA2 0x00000002UL /**< Mode DATA2 for USB_GRXSTSR */
<> 150:02e0a0aed4ec 902 #define _USB_GRXSTSR_DPID_MDATA 0x00000003UL /**< Mode MDATA for USB_GRXSTSR */
<> 150:02e0a0aed4ec 903 #define USB_GRXSTSR_DPID_DEFAULT (_USB_GRXSTSR_DPID_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_GRXSTSR */
<> 150:02e0a0aed4ec 904 #define USB_GRXSTSR_DPID_DATA0 (_USB_GRXSTSR_DPID_DATA0 << 15) /**< Shifted mode DATA0 for USB_GRXSTSR */
<> 150:02e0a0aed4ec 905 #define USB_GRXSTSR_DPID_DATA1 (_USB_GRXSTSR_DPID_DATA1 << 15) /**< Shifted mode DATA1 for USB_GRXSTSR */
<> 150:02e0a0aed4ec 906 #define USB_GRXSTSR_DPID_DATA2 (_USB_GRXSTSR_DPID_DATA2 << 15) /**< Shifted mode DATA2 for USB_GRXSTSR */
<> 150:02e0a0aed4ec 907 #define USB_GRXSTSR_DPID_MDATA (_USB_GRXSTSR_DPID_MDATA << 15) /**< Shifted mode MDATA for USB_GRXSTSR */
<> 150:02e0a0aed4ec 908 #define _USB_GRXSTSR_PKTSTS_SHIFT 17 /**< Shift value for USB_PKTSTS */
<> 150:02e0a0aed4ec 909 #define _USB_GRXSTSR_PKTSTS_MASK 0x1E0000UL /**< Bit mask for USB_PKTSTS */
<> 150:02e0a0aed4ec 910 #define _USB_GRXSTSR_PKTSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRXSTSR */
<> 150:02e0a0aed4ec 911 #define _USB_GRXSTSR_PKTSTS_GOUTNAK 0x00000001UL /**< Mode GOUTNAK for USB_GRXSTSR */
<> 150:02e0a0aed4ec 912 #define _USB_GRXSTSR_PKTSTS_PKTRCV 0x00000002UL /**< Mode PKTRCV for USB_GRXSTSR */
<> 150:02e0a0aed4ec 913 #define _USB_GRXSTSR_PKTSTS_XFERCOMPL 0x00000003UL /**< Mode XFERCOMPL for USB_GRXSTSR */
<> 150:02e0a0aed4ec 914 #define _USB_GRXSTSR_PKTSTS_SETUPCOMPL 0x00000004UL /**< Mode SETUPCOMPL for USB_GRXSTSR */
<> 150:02e0a0aed4ec 915 #define _USB_GRXSTSR_PKTSTS_TGLERR 0x00000005UL /**< Mode TGLERR for USB_GRXSTSR */
<> 150:02e0a0aed4ec 916 #define _USB_GRXSTSR_PKTSTS_SETUPRCV 0x00000006UL /**< Mode SETUPRCV for USB_GRXSTSR */
<> 150:02e0a0aed4ec 917 #define _USB_GRXSTSR_PKTSTS_CHLT 0x00000007UL /**< Mode CHLT for USB_GRXSTSR */
<> 150:02e0a0aed4ec 918 #define USB_GRXSTSR_PKTSTS_DEFAULT (_USB_GRXSTSR_PKTSTS_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_GRXSTSR */
<> 150:02e0a0aed4ec 919 #define USB_GRXSTSR_PKTSTS_GOUTNAK (_USB_GRXSTSR_PKTSTS_GOUTNAK << 17) /**< Shifted mode GOUTNAK for USB_GRXSTSR */
<> 150:02e0a0aed4ec 920 #define USB_GRXSTSR_PKTSTS_PKTRCV (_USB_GRXSTSR_PKTSTS_PKTRCV << 17) /**< Shifted mode PKTRCV for USB_GRXSTSR */
<> 150:02e0a0aed4ec 921 #define USB_GRXSTSR_PKTSTS_XFERCOMPL (_USB_GRXSTSR_PKTSTS_XFERCOMPL << 17) /**< Shifted mode XFERCOMPL for USB_GRXSTSR */
<> 150:02e0a0aed4ec 922 #define USB_GRXSTSR_PKTSTS_SETUPCOMPL (_USB_GRXSTSR_PKTSTS_SETUPCOMPL << 17) /**< Shifted mode SETUPCOMPL for USB_GRXSTSR */
<> 150:02e0a0aed4ec 923 #define USB_GRXSTSR_PKTSTS_TGLERR (_USB_GRXSTSR_PKTSTS_TGLERR << 17) /**< Shifted mode TGLERR for USB_GRXSTSR */
<> 150:02e0a0aed4ec 924 #define USB_GRXSTSR_PKTSTS_SETUPRCV (_USB_GRXSTSR_PKTSTS_SETUPRCV << 17) /**< Shifted mode SETUPRCV for USB_GRXSTSR */
<> 150:02e0a0aed4ec 925 #define USB_GRXSTSR_PKTSTS_CHLT (_USB_GRXSTSR_PKTSTS_CHLT << 17) /**< Shifted mode CHLT for USB_GRXSTSR */
<> 150:02e0a0aed4ec 926 #define _USB_GRXSTSR_FN_SHIFT 21 /**< Shift value for USB_FN */
<> 150:02e0a0aed4ec 927 #define _USB_GRXSTSR_FN_MASK 0x1E00000UL /**< Bit mask for USB_FN */
<> 150:02e0a0aed4ec 928 #define _USB_GRXSTSR_FN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRXSTSR */
<> 150:02e0a0aed4ec 929 #define USB_GRXSTSR_FN_DEFAULT (_USB_GRXSTSR_FN_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_GRXSTSR */
<> 150:02e0a0aed4ec 930
<> 150:02e0a0aed4ec 931 /* Bit fields for USB GRXSTSP */
<> 150:02e0a0aed4ec 932 #define _USB_GRXSTSP_RESETVALUE 0x00000000UL /**< Default value for USB_GRXSTSP */
<> 150:02e0a0aed4ec 933 #define _USB_GRXSTSP_MASK 0x01FFFFFFUL /**< Mask for USB_GRXSTSP */
<> 150:02e0a0aed4ec 934 #define _USB_GRXSTSP_CHEPNUM_SHIFT 0 /**< Shift value for USB_CHEPNUM */
<> 150:02e0a0aed4ec 935 #define _USB_GRXSTSP_CHEPNUM_MASK 0xFUL /**< Bit mask for USB_CHEPNUM */
<> 150:02e0a0aed4ec 936 #define _USB_GRXSTSP_CHEPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRXSTSP */
<> 150:02e0a0aed4ec 937 #define USB_GRXSTSP_CHEPNUM_DEFAULT (_USB_GRXSTSP_CHEPNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GRXSTSP */
<> 150:02e0a0aed4ec 938 #define _USB_GRXSTSP_BCNT_SHIFT 4 /**< Shift value for USB_BCNT */
<> 150:02e0a0aed4ec 939 #define _USB_GRXSTSP_BCNT_MASK 0x7FF0UL /**< Bit mask for USB_BCNT */
<> 150:02e0a0aed4ec 940 #define _USB_GRXSTSP_BCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRXSTSP */
<> 150:02e0a0aed4ec 941 #define USB_GRXSTSP_BCNT_DEFAULT (_USB_GRXSTSP_BCNT_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_GRXSTSP */
<> 150:02e0a0aed4ec 942 #define _USB_GRXSTSP_DPID_SHIFT 15 /**< Shift value for USB_DPID */
<> 150:02e0a0aed4ec 943 #define _USB_GRXSTSP_DPID_MASK 0x18000UL /**< Bit mask for USB_DPID */
<> 150:02e0a0aed4ec 944 #define _USB_GRXSTSP_DPID_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRXSTSP */
<> 150:02e0a0aed4ec 945 #define _USB_GRXSTSP_DPID_DATA0 0x00000000UL /**< Mode DATA0 for USB_GRXSTSP */
<> 150:02e0a0aed4ec 946 #define _USB_GRXSTSP_DPID_DATA1 0x00000001UL /**< Mode DATA1 for USB_GRXSTSP */
<> 150:02e0a0aed4ec 947 #define _USB_GRXSTSP_DPID_DATA2 0x00000002UL /**< Mode DATA2 for USB_GRXSTSP */
<> 150:02e0a0aed4ec 948 #define _USB_GRXSTSP_DPID_MDATA 0x00000003UL /**< Mode MDATA for USB_GRXSTSP */
<> 150:02e0a0aed4ec 949 #define USB_GRXSTSP_DPID_DEFAULT (_USB_GRXSTSP_DPID_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_GRXSTSP */
<> 150:02e0a0aed4ec 950 #define USB_GRXSTSP_DPID_DATA0 (_USB_GRXSTSP_DPID_DATA0 << 15) /**< Shifted mode DATA0 for USB_GRXSTSP */
<> 150:02e0a0aed4ec 951 #define USB_GRXSTSP_DPID_DATA1 (_USB_GRXSTSP_DPID_DATA1 << 15) /**< Shifted mode DATA1 for USB_GRXSTSP */
<> 150:02e0a0aed4ec 952 #define USB_GRXSTSP_DPID_DATA2 (_USB_GRXSTSP_DPID_DATA2 << 15) /**< Shifted mode DATA2 for USB_GRXSTSP */
<> 150:02e0a0aed4ec 953 #define USB_GRXSTSP_DPID_MDATA (_USB_GRXSTSP_DPID_MDATA << 15) /**< Shifted mode MDATA for USB_GRXSTSP */
<> 150:02e0a0aed4ec 954 #define _USB_GRXSTSP_PKTSTS_SHIFT 17 /**< Shift value for USB_PKTSTS */
<> 150:02e0a0aed4ec 955 #define _USB_GRXSTSP_PKTSTS_MASK 0x1E0000UL /**< Bit mask for USB_PKTSTS */
<> 150:02e0a0aed4ec 956 #define _USB_GRXSTSP_PKTSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRXSTSP */
<> 150:02e0a0aed4ec 957 #define _USB_GRXSTSP_PKTSTS_GOUTNAK 0x00000001UL /**< Mode GOUTNAK for USB_GRXSTSP */
<> 150:02e0a0aed4ec 958 #define _USB_GRXSTSP_PKTSTS_PKTRCV 0x00000002UL /**< Mode PKTRCV for USB_GRXSTSP */
<> 150:02e0a0aed4ec 959 #define _USB_GRXSTSP_PKTSTS_XFERCOMPL 0x00000003UL /**< Mode XFERCOMPL for USB_GRXSTSP */
<> 150:02e0a0aed4ec 960 #define _USB_GRXSTSP_PKTSTS_SETUPCOMPL 0x00000004UL /**< Mode SETUPCOMPL for USB_GRXSTSP */
<> 150:02e0a0aed4ec 961 #define _USB_GRXSTSP_PKTSTS_TGLERR 0x00000005UL /**< Mode TGLERR for USB_GRXSTSP */
<> 150:02e0a0aed4ec 962 #define _USB_GRXSTSP_PKTSTS_SETUPRCV 0x00000006UL /**< Mode SETUPRCV for USB_GRXSTSP */
<> 150:02e0a0aed4ec 963 #define _USB_GRXSTSP_PKTSTS_CHLT 0x00000007UL /**< Mode CHLT for USB_GRXSTSP */
<> 150:02e0a0aed4ec 964 #define USB_GRXSTSP_PKTSTS_DEFAULT (_USB_GRXSTSP_PKTSTS_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_GRXSTSP */
<> 150:02e0a0aed4ec 965 #define USB_GRXSTSP_PKTSTS_GOUTNAK (_USB_GRXSTSP_PKTSTS_GOUTNAK << 17) /**< Shifted mode GOUTNAK for USB_GRXSTSP */
<> 150:02e0a0aed4ec 966 #define USB_GRXSTSP_PKTSTS_PKTRCV (_USB_GRXSTSP_PKTSTS_PKTRCV << 17) /**< Shifted mode PKTRCV for USB_GRXSTSP */
<> 150:02e0a0aed4ec 967 #define USB_GRXSTSP_PKTSTS_XFERCOMPL (_USB_GRXSTSP_PKTSTS_XFERCOMPL << 17) /**< Shifted mode XFERCOMPL for USB_GRXSTSP */
<> 150:02e0a0aed4ec 968 #define USB_GRXSTSP_PKTSTS_SETUPCOMPL (_USB_GRXSTSP_PKTSTS_SETUPCOMPL << 17) /**< Shifted mode SETUPCOMPL for USB_GRXSTSP */
<> 150:02e0a0aed4ec 969 #define USB_GRXSTSP_PKTSTS_TGLERR (_USB_GRXSTSP_PKTSTS_TGLERR << 17) /**< Shifted mode TGLERR for USB_GRXSTSP */
<> 150:02e0a0aed4ec 970 #define USB_GRXSTSP_PKTSTS_SETUPRCV (_USB_GRXSTSP_PKTSTS_SETUPRCV << 17) /**< Shifted mode SETUPRCV for USB_GRXSTSP */
<> 150:02e0a0aed4ec 971 #define USB_GRXSTSP_PKTSTS_CHLT (_USB_GRXSTSP_PKTSTS_CHLT << 17) /**< Shifted mode CHLT for USB_GRXSTSP */
<> 150:02e0a0aed4ec 972 #define _USB_GRXSTSP_FN_SHIFT 21 /**< Shift value for USB_FN */
<> 150:02e0a0aed4ec 973 #define _USB_GRXSTSP_FN_MASK 0x1E00000UL /**< Bit mask for USB_FN */
<> 150:02e0a0aed4ec 974 #define _USB_GRXSTSP_FN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRXSTSP */
<> 150:02e0a0aed4ec 975 #define USB_GRXSTSP_FN_DEFAULT (_USB_GRXSTSP_FN_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_GRXSTSP */
<> 150:02e0a0aed4ec 976
<> 150:02e0a0aed4ec 977 /* Bit fields for USB GRXFSIZ */
<> 150:02e0a0aed4ec 978 #define _USB_GRXFSIZ_RESETVALUE 0x00000200UL /**< Default value for USB_GRXFSIZ */
<> 150:02e0a0aed4ec 979 #define _USB_GRXFSIZ_MASK 0x000003FFUL /**< Mask for USB_GRXFSIZ */
<> 150:02e0a0aed4ec 980 #define _USB_GRXFSIZ_RXFDEP_SHIFT 0 /**< Shift value for USB_RXFDEP */
<> 150:02e0a0aed4ec 981 #define _USB_GRXFSIZ_RXFDEP_MASK 0x3FFUL /**< Bit mask for USB_RXFDEP */
<> 150:02e0a0aed4ec 982 #define _USB_GRXFSIZ_RXFDEP_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_GRXFSIZ */
<> 150:02e0a0aed4ec 983 #define USB_GRXFSIZ_RXFDEP_DEFAULT (_USB_GRXFSIZ_RXFDEP_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GRXFSIZ */
<> 150:02e0a0aed4ec 984
<> 150:02e0a0aed4ec 985 /* Bit fields for USB GNPTXFSIZ */
<> 150:02e0a0aed4ec 986 #define _USB_GNPTXFSIZ_RESETVALUE 0x02000200UL /**< Default value for USB_GNPTXFSIZ */
<> 150:02e0a0aed4ec 987 #define _USB_GNPTXFSIZ_MASK 0xFFFF03FFUL /**< Mask for USB_GNPTXFSIZ */
<> 150:02e0a0aed4ec 988 #define _USB_GNPTXFSIZ_NPTXFSTADDR_SHIFT 0 /**< Shift value for USB_NPTXFSTADDR */
<> 150:02e0a0aed4ec 989 #define _USB_GNPTXFSIZ_NPTXFSTADDR_MASK 0x3FFUL /**< Bit mask for USB_NPTXFSTADDR */
<> 150:02e0a0aed4ec 990 #define _USB_GNPTXFSIZ_NPTXFSTADDR_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_GNPTXFSIZ */
<> 150:02e0a0aed4ec 991 #define USB_GNPTXFSIZ_NPTXFSTADDR_DEFAULT (_USB_GNPTXFSIZ_NPTXFSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GNPTXFSIZ */
<> 150:02e0a0aed4ec 992 #define _USB_GNPTXFSIZ_NPTXFINEPTXF0DEP_SHIFT 16 /**< Shift value for USB_NPTXFINEPTXF0DEP */
<> 150:02e0a0aed4ec 993 #define _USB_GNPTXFSIZ_NPTXFINEPTXF0DEP_MASK 0xFFFF0000UL /**< Bit mask for USB_NPTXFINEPTXF0DEP */
<> 150:02e0a0aed4ec 994 #define _USB_GNPTXFSIZ_NPTXFINEPTXF0DEP_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_GNPTXFSIZ */
<> 150:02e0a0aed4ec 995 #define USB_GNPTXFSIZ_NPTXFINEPTXF0DEP_DEFAULT (_USB_GNPTXFSIZ_NPTXFINEPTXF0DEP_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_GNPTXFSIZ */
<> 150:02e0a0aed4ec 996
<> 150:02e0a0aed4ec 997 /* Bit fields for USB GNPTXSTS */
<> 150:02e0a0aed4ec 998 #define _USB_GNPTXSTS_RESETVALUE 0x00080200UL /**< Default value for USB_GNPTXSTS */
<> 150:02e0a0aed4ec 999 #define _USB_GNPTXSTS_MASK 0x7FFFFFFFUL /**< Mask for USB_GNPTXSTS */
<> 150:02e0a0aed4ec 1000 #define _USB_GNPTXSTS_NPTXFSPCAVAIL_SHIFT 0 /**< Shift value for USB_NPTXFSPCAVAIL */
<> 150:02e0a0aed4ec 1001 #define _USB_GNPTXSTS_NPTXFSPCAVAIL_MASK 0xFFFFUL /**< Bit mask for USB_NPTXFSPCAVAIL */
<> 150:02e0a0aed4ec 1002 #define _USB_GNPTXSTS_NPTXFSPCAVAIL_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_GNPTXSTS */
<> 150:02e0a0aed4ec 1003 #define USB_GNPTXSTS_NPTXFSPCAVAIL_DEFAULT (_USB_GNPTXSTS_NPTXFSPCAVAIL_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GNPTXSTS */
<> 150:02e0a0aed4ec 1004 #define _USB_GNPTXSTS_NPTXQSPCAVAIL_SHIFT 16 /**< Shift value for USB_NPTXQSPCAVAIL */
<> 150:02e0a0aed4ec 1005 #define _USB_GNPTXSTS_NPTXQSPCAVAIL_MASK 0xFF0000UL /**< Bit mask for USB_NPTXQSPCAVAIL */
<> 150:02e0a0aed4ec 1006 #define _USB_GNPTXSTS_NPTXQSPCAVAIL_DEFAULT 0x00000008UL /**< Mode DEFAULT for USB_GNPTXSTS */
<> 150:02e0a0aed4ec 1007 #define USB_GNPTXSTS_NPTXQSPCAVAIL_DEFAULT (_USB_GNPTXSTS_NPTXQSPCAVAIL_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_GNPTXSTS */
<> 150:02e0a0aed4ec 1008 #define _USB_GNPTXSTS_NPTXQTOP_SHIFT 24 /**< Shift value for USB_NPTXQTOP */
<> 150:02e0a0aed4ec 1009 #define _USB_GNPTXSTS_NPTXQTOP_MASK 0x7F000000UL /**< Bit mask for USB_NPTXQTOP */
<> 150:02e0a0aed4ec 1010 #define _USB_GNPTXSTS_NPTXQTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GNPTXSTS */
<> 150:02e0a0aed4ec 1011 #define USB_GNPTXSTS_NPTXQTOP_DEFAULT (_USB_GNPTXSTS_NPTXQTOP_DEFAULT << 24) /**< Shifted mode DEFAULT for USB_GNPTXSTS */
<> 150:02e0a0aed4ec 1012
<> 150:02e0a0aed4ec 1013 /* Bit fields for USB GDFIFOCFG */
<> 150:02e0a0aed4ec 1014 #define _USB_GDFIFOCFG_RESETVALUE 0x01F20200UL /**< Default value for USB_GDFIFOCFG */
<> 150:02e0a0aed4ec 1015 #define _USB_GDFIFOCFG_MASK 0xFFFFFFFFUL /**< Mask for USB_GDFIFOCFG */
<> 150:02e0a0aed4ec 1016 #define _USB_GDFIFOCFG_GDFIFOCFG_SHIFT 0 /**< Shift value for USB_GDFIFOCFG */
<> 150:02e0a0aed4ec 1017 #define _USB_GDFIFOCFG_GDFIFOCFG_MASK 0xFFFFUL /**< Bit mask for USB_GDFIFOCFG */
<> 150:02e0a0aed4ec 1018 #define _USB_GDFIFOCFG_GDFIFOCFG_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_GDFIFOCFG */
<> 150:02e0a0aed4ec 1019 #define USB_GDFIFOCFG_GDFIFOCFG_DEFAULT (_USB_GDFIFOCFG_GDFIFOCFG_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GDFIFOCFG */
<> 150:02e0a0aed4ec 1020 #define _USB_GDFIFOCFG_EPINFOBASEADDR_SHIFT 16 /**< Shift value for USB_EPINFOBASEADDR */
<> 150:02e0a0aed4ec 1021 #define _USB_GDFIFOCFG_EPINFOBASEADDR_MASK 0xFFFF0000UL /**< Bit mask for USB_EPINFOBASEADDR */
<> 150:02e0a0aed4ec 1022 #define _USB_GDFIFOCFG_EPINFOBASEADDR_DEFAULT 0x000001F2UL /**< Mode DEFAULT for USB_GDFIFOCFG */
<> 150:02e0a0aed4ec 1023 #define USB_GDFIFOCFG_EPINFOBASEADDR_DEFAULT (_USB_GDFIFOCFG_EPINFOBASEADDR_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_GDFIFOCFG */
<> 150:02e0a0aed4ec 1024
<> 150:02e0a0aed4ec 1025 /* Bit fields for USB HPTXFSIZ */
<> 150:02e0a0aed4ec 1026 #define _USB_HPTXFSIZ_RESETVALUE 0x02000400UL /**< Default value for USB_HPTXFSIZ */
<> 150:02e0a0aed4ec 1027 #define _USB_HPTXFSIZ_MASK 0x03FF07FFUL /**< Mask for USB_HPTXFSIZ */
<> 150:02e0a0aed4ec 1028 #define _USB_HPTXFSIZ_PTXFSTADDR_SHIFT 0 /**< Shift value for USB_PTXFSTADDR */
<> 150:02e0a0aed4ec 1029 #define _USB_HPTXFSIZ_PTXFSTADDR_MASK 0x7FFUL /**< Bit mask for USB_PTXFSTADDR */
<> 150:02e0a0aed4ec 1030 #define _USB_HPTXFSIZ_PTXFSTADDR_DEFAULT 0x00000400UL /**< Mode DEFAULT for USB_HPTXFSIZ */
<> 150:02e0a0aed4ec 1031 #define USB_HPTXFSIZ_PTXFSTADDR_DEFAULT (_USB_HPTXFSIZ_PTXFSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_HPTXFSIZ */
<> 150:02e0a0aed4ec 1032 #define _USB_HPTXFSIZ_PTXFSIZE_SHIFT 16 /**< Shift value for USB_PTXFSIZE */
<> 150:02e0a0aed4ec 1033 #define _USB_HPTXFSIZ_PTXFSIZE_MASK 0x3FF0000UL /**< Bit mask for USB_PTXFSIZE */
<> 150:02e0a0aed4ec 1034 #define _USB_HPTXFSIZ_PTXFSIZE_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_HPTXFSIZ */
<> 150:02e0a0aed4ec 1035 #define USB_HPTXFSIZ_PTXFSIZE_DEFAULT (_USB_HPTXFSIZ_PTXFSIZE_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_HPTXFSIZ */
<> 150:02e0a0aed4ec 1036
<> 150:02e0a0aed4ec 1037 /* Bit fields for USB DIEPTXF1 */
<> 150:02e0a0aed4ec 1038 #define _USB_DIEPTXF1_RESETVALUE 0x02000400UL /**< Default value for USB_DIEPTXF1 */
<> 150:02e0a0aed4ec 1039 #define _USB_DIEPTXF1_MASK 0x03FF07FFUL /**< Mask for USB_DIEPTXF1 */
<> 150:02e0a0aed4ec 1040 #define _USB_DIEPTXF1_INEPNTXFSTADDR_SHIFT 0 /**< Shift value for USB_INEPNTXFSTADDR */
<> 150:02e0a0aed4ec 1041 #define _USB_DIEPTXF1_INEPNTXFSTADDR_MASK 0x7FFUL /**< Bit mask for USB_INEPNTXFSTADDR */
<> 150:02e0a0aed4ec 1042 #define _USB_DIEPTXF1_INEPNTXFSTADDR_DEFAULT 0x00000400UL /**< Mode DEFAULT for USB_DIEPTXF1 */
<> 150:02e0a0aed4ec 1043 #define USB_DIEPTXF1_INEPNTXFSTADDR_DEFAULT (_USB_DIEPTXF1_INEPNTXFSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEPTXF1 */
<> 150:02e0a0aed4ec 1044 #define _USB_DIEPTXF1_INEPNTXFDEP_SHIFT 16 /**< Shift value for USB_INEPNTXFDEP */
<> 150:02e0a0aed4ec 1045 #define _USB_DIEPTXF1_INEPNTXFDEP_MASK 0x3FF0000UL /**< Bit mask for USB_INEPNTXFDEP */
<> 150:02e0a0aed4ec 1046 #define _USB_DIEPTXF1_INEPNTXFDEP_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_DIEPTXF1 */
<> 150:02e0a0aed4ec 1047 #define USB_DIEPTXF1_INEPNTXFDEP_DEFAULT (_USB_DIEPTXF1_INEPNTXFDEP_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_DIEPTXF1 */
<> 150:02e0a0aed4ec 1048
<> 150:02e0a0aed4ec 1049 /* Bit fields for USB DIEPTXF2 */
<> 150:02e0a0aed4ec 1050 #define _USB_DIEPTXF2_RESETVALUE 0x02000600UL /**< Default value for USB_DIEPTXF2 */
<> 150:02e0a0aed4ec 1051 #define _USB_DIEPTXF2_MASK 0x03FF07FFUL /**< Mask for USB_DIEPTXF2 */
<> 150:02e0a0aed4ec 1052 #define _USB_DIEPTXF2_INEPNTXFSTADDR_SHIFT 0 /**< Shift value for USB_INEPNTXFSTADDR */
<> 150:02e0a0aed4ec 1053 #define _USB_DIEPTXF2_INEPNTXFSTADDR_MASK 0x7FFUL /**< Bit mask for USB_INEPNTXFSTADDR */
<> 150:02e0a0aed4ec 1054 #define _USB_DIEPTXF2_INEPNTXFSTADDR_DEFAULT 0x00000600UL /**< Mode DEFAULT for USB_DIEPTXF2 */
<> 150:02e0a0aed4ec 1055 #define USB_DIEPTXF2_INEPNTXFSTADDR_DEFAULT (_USB_DIEPTXF2_INEPNTXFSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEPTXF2 */
<> 150:02e0a0aed4ec 1056 #define _USB_DIEPTXF2_INEPNTXFDEP_SHIFT 16 /**< Shift value for USB_INEPNTXFDEP */
<> 150:02e0a0aed4ec 1057 #define _USB_DIEPTXF2_INEPNTXFDEP_MASK 0x3FF0000UL /**< Bit mask for USB_INEPNTXFDEP */
<> 150:02e0a0aed4ec 1058 #define _USB_DIEPTXF2_INEPNTXFDEP_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_DIEPTXF2 */
<> 150:02e0a0aed4ec 1059 #define USB_DIEPTXF2_INEPNTXFDEP_DEFAULT (_USB_DIEPTXF2_INEPNTXFDEP_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_DIEPTXF2 */
<> 150:02e0a0aed4ec 1060
<> 150:02e0a0aed4ec 1061 /* Bit fields for USB DIEPTXF3 */
<> 150:02e0a0aed4ec 1062 #define _USB_DIEPTXF3_RESETVALUE 0x02000800UL /**< Default value for USB_DIEPTXF3 */
<> 150:02e0a0aed4ec 1063 #define _USB_DIEPTXF3_MASK 0x03FF0FFFUL /**< Mask for USB_DIEPTXF3 */
<> 150:02e0a0aed4ec 1064 #define _USB_DIEPTXF3_INEPNTXFSTADDR_SHIFT 0 /**< Shift value for USB_INEPNTXFSTADDR */
<> 150:02e0a0aed4ec 1065 #define _USB_DIEPTXF3_INEPNTXFSTADDR_MASK 0xFFFUL /**< Bit mask for USB_INEPNTXFSTADDR */
<> 150:02e0a0aed4ec 1066 #define _USB_DIEPTXF3_INEPNTXFSTADDR_DEFAULT 0x00000800UL /**< Mode DEFAULT for USB_DIEPTXF3 */
<> 150:02e0a0aed4ec 1067 #define USB_DIEPTXF3_INEPNTXFSTADDR_DEFAULT (_USB_DIEPTXF3_INEPNTXFSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEPTXF3 */
<> 150:02e0a0aed4ec 1068 #define _USB_DIEPTXF3_INEPNTXFDEP_SHIFT 16 /**< Shift value for USB_INEPNTXFDEP */
<> 150:02e0a0aed4ec 1069 #define _USB_DIEPTXF3_INEPNTXFDEP_MASK 0x3FF0000UL /**< Bit mask for USB_INEPNTXFDEP */
<> 150:02e0a0aed4ec 1070 #define _USB_DIEPTXF3_INEPNTXFDEP_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_DIEPTXF3 */
<> 150:02e0a0aed4ec 1071 #define USB_DIEPTXF3_INEPNTXFDEP_DEFAULT (_USB_DIEPTXF3_INEPNTXFDEP_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_DIEPTXF3 */
<> 150:02e0a0aed4ec 1072
<> 150:02e0a0aed4ec 1073 /* Bit fields for USB DIEPTXF4 */
<> 150:02e0a0aed4ec 1074 #define _USB_DIEPTXF4_RESETVALUE 0x02000A00UL /**< Default value for USB_DIEPTXF4 */
<> 150:02e0a0aed4ec 1075 #define _USB_DIEPTXF4_MASK 0x03FF0FFFUL /**< Mask for USB_DIEPTXF4 */
<> 150:02e0a0aed4ec 1076 #define _USB_DIEPTXF4_INEPNTXFSTADDR_SHIFT 0 /**< Shift value for USB_INEPNTXFSTADDR */
<> 150:02e0a0aed4ec 1077 #define _USB_DIEPTXF4_INEPNTXFSTADDR_MASK 0xFFFUL /**< Bit mask for USB_INEPNTXFSTADDR */
<> 150:02e0a0aed4ec 1078 #define _USB_DIEPTXF4_INEPNTXFSTADDR_DEFAULT 0x00000A00UL /**< Mode DEFAULT for USB_DIEPTXF4 */
<> 150:02e0a0aed4ec 1079 #define USB_DIEPTXF4_INEPNTXFSTADDR_DEFAULT (_USB_DIEPTXF4_INEPNTXFSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEPTXF4 */
<> 150:02e0a0aed4ec 1080 #define _USB_DIEPTXF4_INEPNTXFDEP_SHIFT 16 /**< Shift value for USB_INEPNTXFDEP */
<> 150:02e0a0aed4ec 1081 #define _USB_DIEPTXF4_INEPNTXFDEP_MASK 0x3FF0000UL /**< Bit mask for USB_INEPNTXFDEP */
<> 150:02e0a0aed4ec 1082 #define _USB_DIEPTXF4_INEPNTXFDEP_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_DIEPTXF4 */
<> 150:02e0a0aed4ec 1083 #define USB_DIEPTXF4_INEPNTXFDEP_DEFAULT (_USB_DIEPTXF4_INEPNTXFDEP_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_DIEPTXF4 */
<> 150:02e0a0aed4ec 1084
<> 150:02e0a0aed4ec 1085 /* Bit fields for USB DIEPTXF5 */
<> 150:02e0a0aed4ec 1086 #define _USB_DIEPTXF5_RESETVALUE 0x02000C00UL /**< Default value for USB_DIEPTXF5 */
<> 150:02e0a0aed4ec 1087 #define _USB_DIEPTXF5_MASK 0x03FF0FFFUL /**< Mask for USB_DIEPTXF5 */
<> 150:02e0a0aed4ec 1088 #define _USB_DIEPTXF5_INEPNTXFSTADDR_SHIFT 0 /**< Shift value for USB_INEPNTXFSTADDR */
<> 150:02e0a0aed4ec 1089 #define _USB_DIEPTXF5_INEPNTXFSTADDR_MASK 0xFFFUL /**< Bit mask for USB_INEPNTXFSTADDR */
<> 150:02e0a0aed4ec 1090 #define _USB_DIEPTXF5_INEPNTXFSTADDR_DEFAULT 0x00000C00UL /**< Mode DEFAULT for USB_DIEPTXF5 */
<> 150:02e0a0aed4ec 1091 #define USB_DIEPTXF5_INEPNTXFSTADDR_DEFAULT (_USB_DIEPTXF5_INEPNTXFSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEPTXF5 */
<> 150:02e0a0aed4ec 1092 #define _USB_DIEPTXF5_INEPNTXFDEP_SHIFT 16 /**< Shift value for USB_INEPNTXFDEP */
<> 150:02e0a0aed4ec 1093 #define _USB_DIEPTXF5_INEPNTXFDEP_MASK 0x3FF0000UL /**< Bit mask for USB_INEPNTXFDEP */
<> 150:02e0a0aed4ec 1094 #define _USB_DIEPTXF5_INEPNTXFDEP_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_DIEPTXF5 */
<> 150:02e0a0aed4ec 1095 #define USB_DIEPTXF5_INEPNTXFDEP_DEFAULT (_USB_DIEPTXF5_INEPNTXFDEP_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_DIEPTXF5 */
<> 150:02e0a0aed4ec 1096
<> 150:02e0a0aed4ec 1097 /* Bit fields for USB DIEPTXF6 */
<> 150:02e0a0aed4ec 1098 #define _USB_DIEPTXF6_RESETVALUE 0x02000E00UL /**< Default value for USB_DIEPTXF6 */
<> 150:02e0a0aed4ec 1099 #define _USB_DIEPTXF6_MASK 0x03FF0FFFUL /**< Mask for USB_DIEPTXF6 */
<> 150:02e0a0aed4ec 1100 #define _USB_DIEPTXF6_INEPNTXFSTADDR_SHIFT 0 /**< Shift value for USB_INEPNTXFSTADDR */
<> 150:02e0a0aed4ec 1101 #define _USB_DIEPTXF6_INEPNTXFSTADDR_MASK 0xFFFUL /**< Bit mask for USB_INEPNTXFSTADDR */
<> 150:02e0a0aed4ec 1102 #define _USB_DIEPTXF6_INEPNTXFSTADDR_DEFAULT 0x00000E00UL /**< Mode DEFAULT for USB_DIEPTXF6 */
<> 150:02e0a0aed4ec 1103 #define USB_DIEPTXF6_INEPNTXFSTADDR_DEFAULT (_USB_DIEPTXF6_INEPNTXFSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEPTXF6 */
<> 150:02e0a0aed4ec 1104 #define _USB_DIEPTXF6_INEPNTXFDEP_SHIFT 16 /**< Shift value for USB_INEPNTXFDEP */
<> 150:02e0a0aed4ec 1105 #define _USB_DIEPTXF6_INEPNTXFDEP_MASK 0x3FF0000UL /**< Bit mask for USB_INEPNTXFDEP */
<> 150:02e0a0aed4ec 1106 #define _USB_DIEPTXF6_INEPNTXFDEP_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_DIEPTXF6 */
<> 150:02e0a0aed4ec 1107 #define USB_DIEPTXF6_INEPNTXFDEP_DEFAULT (_USB_DIEPTXF6_INEPNTXFDEP_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_DIEPTXF6 */
<> 150:02e0a0aed4ec 1108
<> 150:02e0a0aed4ec 1109 /* Bit fields for USB HCFG */
<> 150:02e0a0aed4ec 1110 #define _USB_HCFG_RESETVALUE 0x00200000UL /**< Default value for USB_HCFG */
<> 150:02e0a0aed4ec 1111 #define _USB_HCFG_MASK 0x8000FF87UL /**< Mask for USB_HCFG */
<> 150:02e0a0aed4ec 1112 #define _USB_HCFG_FSLSPCLKSEL_SHIFT 0 /**< Shift value for USB_FSLSPCLKSEL */
<> 150:02e0a0aed4ec 1113 #define _USB_HCFG_FSLSPCLKSEL_MASK 0x3UL /**< Bit mask for USB_FSLSPCLKSEL */
<> 150:02e0a0aed4ec 1114 #define _USB_HCFG_FSLSPCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HCFG */
<> 150:02e0a0aed4ec 1115 #define _USB_HCFG_FSLSPCLKSEL_DIV1 0x00000001UL /**< Mode DIV1 for USB_HCFG */
<> 150:02e0a0aed4ec 1116 #define _USB_HCFG_FSLSPCLKSEL_DIV8 0x00000002UL /**< Mode DIV8 for USB_HCFG */
<> 150:02e0a0aed4ec 1117 #define USB_HCFG_FSLSPCLKSEL_DEFAULT (_USB_HCFG_FSLSPCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_HCFG */
<> 150:02e0a0aed4ec 1118 #define USB_HCFG_FSLSPCLKSEL_DIV1 (_USB_HCFG_FSLSPCLKSEL_DIV1 << 0) /**< Shifted mode DIV1 for USB_HCFG */
<> 150:02e0a0aed4ec 1119 #define USB_HCFG_FSLSPCLKSEL_DIV8 (_USB_HCFG_FSLSPCLKSEL_DIV8 << 0) /**< Shifted mode DIV8 for USB_HCFG */
<> 150:02e0a0aed4ec 1120 #define USB_HCFG_FSLSSUPP (0x1UL << 2) /**< FS- and LS-Only Support */
<> 150:02e0a0aed4ec 1121 #define _USB_HCFG_FSLSSUPP_SHIFT 2 /**< Shift value for USB_FSLSSUPP */
<> 150:02e0a0aed4ec 1122 #define _USB_HCFG_FSLSSUPP_MASK 0x4UL /**< Bit mask for USB_FSLSSUPP */
<> 150:02e0a0aed4ec 1123 #define _USB_HCFG_FSLSSUPP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HCFG */
<> 150:02e0a0aed4ec 1124 #define _USB_HCFG_FSLSSUPP_HSFSLS 0x00000000UL /**< Mode HSFSLS for USB_HCFG */
<> 150:02e0a0aed4ec 1125 #define _USB_HCFG_FSLSSUPP_FSLS 0x00000001UL /**< Mode FSLS for USB_HCFG */
<> 150:02e0a0aed4ec 1126 #define USB_HCFG_FSLSSUPP_DEFAULT (_USB_HCFG_FSLSSUPP_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_HCFG */
<> 150:02e0a0aed4ec 1127 #define USB_HCFG_FSLSSUPP_HSFSLS (_USB_HCFG_FSLSSUPP_HSFSLS << 2) /**< Shifted mode HSFSLS for USB_HCFG */
<> 150:02e0a0aed4ec 1128 #define USB_HCFG_FSLSSUPP_FSLS (_USB_HCFG_FSLSSUPP_FSLS << 2) /**< Shifted mode FSLS for USB_HCFG */
<> 150:02e0a0aed4ec 1129 #define USB_HCFG_ENA32KHZS (0x1UL << 7) /**< Enable 32 KHz Suspend mode */
<> 150:02e0a0aed4ec 1130 #define _USB_HCFG_ENA32KHZS_SHIFT 7 /**< Shift value for USB_ENA32KHZS */
<> 150:02e0a0aed4ec 1131 #define _USB_HCFG_ENA32KHZS_MASK 0x80UL /**< Bit mask for USB_ENA32KHZS */
<> 150:02e0a0aed4ec 1132 #define _USB_HCFG_ENA32KHZS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HCFG */
<> 150:02e0a0aed4ec 1133 #define USB_HCFG_ENA32KHZS_DEFAULT (_USB_HCFG_ENA32KHZS_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_HCFG */
<> 150:02e0a0aed4ec 1134 #define _USB_HCFG_RESVALID_SHIFT 8 /**< Shift value for USB_RESVALID */
<> 150:02e0a0aed4ec 1135 #define _USB_HCFG_RESVALID_MASK 0xFF00UL /**< Bit mask for USB_RESVALID */
<> 150:02e0a0aed4ec 1136 #define _USB_HCFG_RESVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HCFG */
<> 150:02e0a0aed4ec 1137 #define USB_HCFG_RESVALID_DEFAULT (_USB_HCFG_RESVALID_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_HCFG */
<> 150:02e0a0aed4ec 1138 #define USB_HCFG_MODECHTIMEN (0x1UL << 31) /**< Mode Change Time */
<> 150:02e0a0aed4ec 1139 #define _USB_HCFG_MODECHTIMEN_SHIFT 31 /**< Shift value for USB_MODECHTIMEN */
<> 150:02e0a0aed4ec 1140 #define _USB_HCFG_MODECHTIMEN_MASK 0x80000000UL /**< Bit mask for USB_MODECHTIMEN */
<> 150:02e0a0aed4ec 1141 #define _USB_HCFG_MODECHTIMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HCFG */
<> 150:02e0a0aed4ec 1142 #define USB_HCFG_MODECHTIMEN_DEFAULT (_USB_HCFG_MODECHTIMEN_DEFAULT << 31) /**< Shifted mode DEFAULT for USB_HCFG */
<> 150:02e0a0aed4ec 1143
<> 150:02e0a0aed4ec 1144 /* Bit fields for USB HFIR */
<> 150:02e0a0aed4ec 1145 #define _USB_HFIR_RESETVALUE 0x000017D7UL /**< Default value for USB_HFIR */
<> 150:02e0a0aed4ec 1146 #define _USB_HFIR_MASK 0x0001FFFFUL /**< Mask for USB_HFIR */
<> 150:02e0a0aed4ec 1147 #define _USB_HFIR_FRINT_SHIFT 0 /**< Shift value for USB_FRINT */
<> 150:02e0a0aed4ec 1148 #define _USB_HFIR_FRINT_MASK 0xFFFFUL /**< Bit mask for USB_FRINT */
<> 150:02e0a0aed4ec 1149 #define _USB_HFIR_FRINT_DEFAULT 0x000017D7UL /**< Mode DEFAULT for USB_HFIR */
<> 150:02e0a0aed4ec 1150 #define USB_HFIR_FRINT_DEFAULT (_USB_HFIR_FRINT_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_HFIR */
<> 150:02e0a0aed4ec 1151 #define USB_HFIR_HFIRRLDCTRL (0x1UL << 16) /**< Reload Control */
<> 150:02e0a0aed4ec 1152 #define _USB_HFIR_HFIRRLDCTRL_SHIFT 16 /**< Shift value for USB_HFIRRLDCTRL */
<> 150:02e0a0aed4ec 1153 #define _USB_HFIR_HFIRRLDCTRL_MASK 0x10000UL /**< Bit mask for USB_HFIRRLDCTRL */
<> 150:02e0a0aed4ec 1154 #define _USB_HFIR_HFIRRLDCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HFIR */
<> 150:02e0a0aed4ec 1155 #define _USB_HFIR_HFIRRLDCTRL_STATIC 0x00000000UL /**< Mode STATIC for USB_HFIR */
<> 150:02e0a0aed4ec 1156 #define _USB_HFIR_HFIRRLDCTRL_DYNAMIC 0x00000001UL /**< Mode DYNAMIC for USB_HFIR */
<> 150:02e0a0aed4ec 1157 #define USB_HFIR_HFIRRLDCTRL_DEFAULT (_USB_HFIR_HFIRRLDCTRL_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_HFIR */
<> 150:02e0a0aed4ec 1158 #define USB_HFIR_HFIRRLDCTRL_STATIC (_USB_HFIR_HFIRRLDCTRL_STATIC << 16) /**< Shifted mode STATIC for USB_HFIR */
<> 150:02e0a0aed4ec 1159 #define USB_HFIR_HFIRRLDCTRL_DYNAMIC (_USB_HFIR_HFIRRLDCTRL_DYNAMIC << 16) /**< Shifted mode DYNAMIC for USB_HFIR */
<> 150:02e0a0aed4ec 1160
<> 150:02e0a0aed4ec 1161 /* Bit fields for USB HFNUM */
<> 150:02e0a0aed4ec 1162 #define _USB_HFNUM_RESETVALUE 0x00003FFFUL /**< Default value for USB_HFNUM */
<> 150:02e0a0aed4ec 1163 #define _USB_HFNUM_MASK 0xFFFFFFFFUL /**< Mask for USB_HFNUM */
<> 150:02e0a0aed4ec 1164 #define _USB_HFNUM_FRNUM_SHIFT 0 /**< Shift value for USB_FRNUM */
<> 150:02e0a0aed4ec 1165 #define _USB_HFNUM_FRNUM_MASK 0xFFFFUL /**< Bit mask for USB_FRNUM */
<> 150:02e0a0aed4ec 1166 #define _USB_HFNUM_FRNUM_DEFAULT 0x00003FFFUL /**< Mode DEFAULT for USB_HFNUM */
<> 150:02e0a0aed4ec 1167 #define USB_HFNUM_FRNUM_DEFAULT (_USB_HFNUM_FRNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_HFNUM */
<> 150:02e0a0aed4ec 1168 #define _USB_HFNUM_FRREM_SHIFT 16 /**< Shift value for USB_FRREM */
<> 150:02e0a0aed4ec 1169 #define _USB_HFNUM_FRREM_MASK 0xFFFF0000UL /**< Bit mask for USB_FRREM */
<> 150:02e0a0aed4ec 1170 #define _USB_HFNUM_FRREM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HFNUM */
<> 150:02e0a0aed4ec 1171 #define USB_HFNUM_FRREM_DEFAULT (_USB_HFNUM_FRREM_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_HFNUM */
<> 150:02e0a0aed4ec 1172
<> 150:02e0a0aed4ec 1173 /* Bit fields for USB HPTXSTS */
<> 150:02e0a0aed4ec 1174 #define _USB_HPTXSTS_RESETVALUE 0x00080200UL /**< Default value for USB_HPTXSTS */
<> 150:02e0a0aed4ec 1175 #define _USB_HPTXSTS_MASK 0xFFFFFFFFUL /**< Mask for USB_HPTXSTS */
<> 150:02e0a0aed4ec 1176 #define _USB_HPTXSTS_PTXFSPCAVAIL_SHIFT 0 /**< Shift value for USB_PTXFSPCAVAIL */
<> 150:02e0a0aed4ec 1177 #define _USB_HPTXSTS_PTXFSPCAVAIL_MASK 0xFFFFUL /**< Bit mask for USB_PTXFSPCAVAIL */
<> 150:02e0a0aed4ec 1178 #define _USB_HPTXSTS_PTXFSPCAVAIL_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_HPTXSTS */
<> 150:02e0a0aed4ec 1179 #define USB_HPTXSTS_PTXFSPCAVAIL_DEFAULT (_USB_HPTXSTS_PTXFSPCAVAIL_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_HPTXSTS */
<> 150:02e0a0aed4ec 1180 #define _USB_HPTXSTS_PTXQSPCAVAIL_SHIFT 16 /**< Shift value for USB_PTXQSPCAVAIL */
<> 150:02e0a0aed4ec 1181 #define _USB_HPTXSTS_PTXQSPCAVAIL_MASK 0xFF0000UL /**< Bit mask for USB_PTXQSPCAVAIL */
<> 150:02e0a0aed4ec 1182 #define _USB_HPTXSTS_PTXQSPCAVAIL_DEFAULT 0x00000008UL /**< Mode DEFAULT for USB_HPTXSTS */
<> 150:02e0a0aed4ec 1183 #define USB_HPTXSTS_PTXQSPCAVAIL_DEFAULT (_USB_HPTXSTS_PTXQSPCAVAIL_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_HPTXSTS */
<> 150:02e0a0aed4ec 1184 #define _USB_HPTXSTS_PTXQTOP_SHIFT 24 /**< Shift value for USB_PTXQTOP */
<> 150:02e0a0aed4ec 1185 #define _USB_HPTXSTS_PTXQTOP_MASK 0xFF000000UL /**< Bit mask for USB_PTXQTOP */
<> 150:02e0a0aed4ec 1186 #define _USB_HPTXSTS_PTXQTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HPTXSTS */
<> 150:02e0a0aed4ec 1187 #define USB_HPTXSTS_PTXQTOP_DEFAULT (_USB_HPTXSTS_PTXQTOP_DEFAULT << 24) /**< Shifted mode DEFAULT for USB_HPTXSTS */
<> 150:02e0a0aed4ec 1188
<> 150:02e0a0aed4ec 1189 /* Bit fields for USB HAINT */
<> 150:02e0a0aed4ec 1190 #define _USB_HAINT_RESETVALUE 0x00000000UL /**< Default value for USB_HAINT */
<> 150:02e0a0aed4ec 1191 #define _USB_HAINT_MASK 0x00003FFFUL /**< Mask for USB_HAINT */
<> 150:02e0a0aed4ec 1192 #define _USB_HAINT_HAINT_SHIFT 0 /**< Shift value for USB_HAINT */
<> 150:02e0a0aed4ec 1193 #define _USB_HAINT_HAINT_MASK 0x3FFFUL /**< Bit mask for USB_HAINT */
<> 150:02e0a0aed4ec 1194 #define _USB_HAINT_HAINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HAINT */
<> 150:02e0a0aed4ec 1195 #define USB_HAINT_HAINT_DEFAULT (_USB_HAINT_HAINT_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_HAINT */
<> 150:02e0a0aed4ec 1196
<> 150:02e0a0aed4ec 1197 /* Bit fields for USB HAINTMSK */
<> 150:02e0a0aed4ec 1198 #define _USB_HAINTMSK_RESETVALUE 0x00000000UL /**< Default value for USB_HAINTMSK */
<> 150:02e0a0aed4ec 1199 #define _USB_HAINTMSK_MASK 0x00003FFFUL /**< Mask for USB_HAINTMSK */
<> 150:02e0a0aed4ec 1200 #define _USB_HAINTMSK_HAINTMSK_SHIFT 0 /**< Shift value for USB_HAINTMSK */
<> 150:02e0a0aed4ec 1201 #define _USB_HAINTMSK_HAINTMSK_MASK 0x3FFFUL /**< Bit mask for USB_HAINTMSK */
<> 150:02e0a0aed4ec 1202 #define _USB_HAINTMSK_HAINTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HAINTMSK */
<> 150:02e0a0aed4ec 1203 #define USB_HAINTMSK_HAINTMSK_DEFAULT (_USB_HAINTMSK_HAINTMSK_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_HAINTMSK */
<> 150:02e0a0aed4ec 1204
<> 150:02e0a0aed4ec 1205 /* Bit fields for USB HPRT */
<> 150:02e0a0aed4ec 1206 #define _USB_HPRT_RESETVALUE 0x00000000UL /**< Default value for USB_HPRT */
<> 150:02e0a0aed4ec 1207 #define _USB_HPRT_MASK 0x0007FDFFUL /**< Mask for USB_HPRT */
<> 150:02e0a0aed4ec 1208 #define USB_HPRT_PRTCONNSTS (0x1UL << 0) /**< Port Connect Status */
<> 150:02e0a0aed4ec 1209 #define _USB_HPRT_PRTCONNSTS_SHIFT 0 /**< Shift value for USB_PRTCONNSTS */
<> 150:02e0a0aed4ec 1210 #define _USB_HPRT_PRTCONNSTS_MASK 0x1UL /**< Bit mask for USB_PRTCONNSTS */
<> 150:02e0a0aed4ec 1211 #define _USB_HPRT_PRTCONNSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HPRT */
<> 150:02e0a0aed4ec 1212 #define USB_HPRT_PRTCONNSTS_DEFAULT (_USB_HPRT_PRTCONNSTS_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_HPRT */
<> 150:02e0a0aed4ec 1213 #define USB_HPRT_PRTCONNDET (0x1UL << 1) /**< Port Connect Detected */
<> 150:02e0a0aed4ec 1214 #define _USB_HPRT_PRTCONNDET_SHIFT 1 /**< Shift value for USB_PRTCONNDET */
<> 150:02e0a0aed4ec 1215 #define _USB_HPRT_PRTCONNDET_MASK 0x2UL /**< Bit mask for USB_PRTCONNDET */
<> 150:02e0a0aed4ec 1216 #define _USB_HPRT_PRTCONNDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HPRT */
<> 150:02e0a0aed4ec 1217 #define USB_HPRT_PRTCONNDET_DEFAULT (_USB_HPRT_PRTCONNDET_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_HPRT */
<> 150:02e0a0aed4ec 1218 #define USB_HPRT_PRTENA (0x1UL << 2) /**< Port Enable */
<> 150:02e0a0aed4ec 1219 #define _USB_HPRT_PRTENA_SHIFT 2 /**< Shift value for USB_PRTENA */
<> 150:02e0a0aed4ec 1220 #define _USB_HPRT_PRTENA_MASK 0x4UL /**< Bit mask for USB_PRTENA */
<> 150:02e0a0aed4ec 1221 #define _USB_HPRT_PRTENA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HPRT */
<> 150:02e0a0aed4ec 1222 #define USB_HPRT_PRTENA_DEFAULT (_USB_HPRT_PRTENA_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_HPRT */
<> 150:02e0a0aed4ec 1223 #define USB_HPRT_PRTENCHNG (0x1UL << 3) /**< Port Enable/Disable Change */
<> 150:02e0a0aed4ec 1224 #define _USB_HPRT_PRTENCHNG_SHIFT 3 /**< Shift value for USB_PRTENCHNG */
<> 150:02e0a0aed4ec 1225 #define _USB_HPRT_PRTENCHNG_MASK 0x8UL /**< Bit mask for USB_PRTENCHNG */
<> 150:02e0a0aed4ec 1226 #define _USB_HPRT_PRTENCHNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HPRT */
<> 150:02e0a0aed4ec 1227 #define USB_HPRT_PRTENCHNG_DEFAULT (_USB_HPRT_PRTENCHNG_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_HPRT */
<> 150:02e0a0aed4ec 1228 #define USB_HPRT_PRTOVRCURRACT (0x1UL << 4) /**< Port Overcurrent Active */
<> 150:02e0a0aed4ec 1229 #define _USB_HPRT_PRTOVRCURRACT_SHIFT 4 /**< Shift value for USB_PRTOVRCURRACT */
<> 150:02e0a0aed4ec 1230 #define _USB_HPRT_PRTOVRCURRACT_MASK 0x10UL /**< Bit mask for USB_PRTOVRCURRACT */
<> 150:02e0a0aed4ec 1231 #define _USB_HPRT_PRTOVRCURRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HPRT */
<> 150:02e0a0aed4ec 1232 #define USB_HPRT_PRTOVRCURRACT_DEFAULT (_USB_HPRT_PRTOVRCURRACT_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_HPRT */
<> 150:02e0a0aed4ec 1233 #define USB_HPRT_PRTOVRCURRCHNG (0x1UL << 5) /**< Port Overcurrent Change */
<> 150:02e0a0aed4ec 1234 #define _USB_HPRT_PRTOVRCURRCHNG_SHIFT 5 /**< Shift value for USB_PRTOVRCURRCHNG */
<> 150:02e0a0aed4ec 1235 #define _USB_HPRT_PRTOVRCURRCHNG_MASK 0x20UL /**< Bit mask for USB_PRTOVRCURRCHNG */
<> 150:02e0a0aed4ec 1236 #define _USB_HPRT_PRTOVRCURRCHNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HPRT */
<> 150:02e0a0aed4ec 1237 #define USB_HPRT_PRTOVRCURRCHNG_DEFAULT (_USB_HPRT_PRTOVRCURRCHNG_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_HPRT */
<> 150:02e0a0aed4ec 1238 #define USB_HPRT_PRTRES (0x1UL << 6) /**< Port Resume */
<> 150:02e0a0aed4ec 1239 #define _USB_HPRT_PRTRES_SHIFT 6 /**< Shift value for USB_PRTRES */
<> 150:02e0a0aed4ec 1240 #define _USB_HPRT_PRTRES_MASK 0x40UL /**< Bit mask for USB_PRTRES */
<> 150:02e0a0aed4ec 1241 #define _USB_HPRT_PRTRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HPRT */
<> 150:02e0a0aed4ec 1242 #define USB_HPRT_PRTRES_DEFAULT (_USB_HPRT_PRTRES_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_HPRT */
<> 150:02e0a0aed4ec 1243 #define USB_HPRT_PRTSUSP (0x1UL << 7) /**< Port Suspend */
<> 150:02e0a0aed4ec 1244 #define _USB_HPRT_PRTSUSP_SHIFT 7 /**< Shift value for USB_PRTSUSP */
<> 150:02e0a0aed4ec 1245 #define _USB_HPRT_PRTSUSP_MASK 0x80UL /**< Bit mask for USB_PRTSUSP */
<> 150:02e0a0aed4ec 1246 #define _USB_HPRT_PRTSUSP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HPRT */
<> 150:02e0a0aed4ec 1247 #define USB_HPRT_PRTSUSP_DEFAULT (_USB_HPRT_PRTSUSP_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_HPRT */
<> 150:02e0a0aed4ec 1248 #define USB_HPRT_PRTRST (0x1UL << 8) /**< Port Reset */
<> 150:02e0a0aed4ec 1249 #define _USB_HPRT_PRTRST_SHIFT 8 /**< Shift value for USB_PRTRST */
<> 150:02e0a0aed4ec 1250 #define _USB_HPRT_PRTRST_MASK 0x100UL /**< Bit mask for USB_PRTRST */
<> 150:02e0a0aed4ec 1251 #define _USB_HPRT_PRTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HPRT */
<> 150:02e0a0aed4ec 1252 #define USB_HPRT_PRTRST_DEFAULT (_USB_HPRT_PRTRST_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_HPRT */
<> 150:02e0a0aed4ec 1253 #define _USB_HPRT_PRTLNSTS_SHIFT 10 /**< Shift value for USB_PRTLNSTS */
<> 150:02e0a0aed4ec 1254 #define _USB_HPRT_PRTLNSTS_MASK 0xC00UL /**< Bit mask for USB_PRTLNSTS */
<> 150:02e0a0aed4ec 1255 #define _USB_HPRT_PRTLNSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HPRT */
<> 150:02e0a0aed4ec 1256 #define USB_HPRT_PRTLNSTS_DEFAULT (_USB_HPRT_PRTLNSTS_DEFAULT << 10) /**< Shifted mode DEFAULT for USB_HPRT */
<> 150:02e0a0aed4ec 1257 #define USB_HPRT_PRTPWR (0x1UL << 12) /**< Port Power */
<> 150:02e0a0aed4ec 1258 #define _USB_HPRT_PRTPWR_SHIFT 12 /**< Shift value for USB_PRTPWR */
<> 150:02e0a0aed4ec 1259 #define _USB_HPRT_PRTPWR_MASK 0x1000UL /**< Bit mask for USB_PRTPWR */
<> 150:02e0a0aed4ec 1260 #define _USB_HPRT_PRTPWR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HPRT */
<> 150:02e0a0aed4ec 1261 #define _USB_HPRT_PRTPWR_OFF 0x00000000UL /**< Mode OFF for USB_HPRT */
<> 150:02e0a0aed4ec 1262 #define _USB_HPRT_PRTPWR_ON 0x00000001UL /**< Mode ON for USB_HPRT */
<> 150:02e0a0aed4ec 1263 #define USB_HPRT_PRTPWR_DEFAULT (_USB_HPRT_PRTPWR_DEFAULT << 12) /**< Shifted mode DEFAULT for USB_HPRT */
<> 150:02e0a0aed4ec 1264 #define USB_HPRT_PRTPWR_OFF (_USB_HPRT_PRTPWR_OFF << 12) /**< Shifted mode OFF for USB_HPRT */
<> 150:02e0a0aed4ec 1265 #define USB_HPRT_PRTPWR_ON (_USB_HPRT_PRTPWR_ON << 12) /**< Shifted mode ON for USB_HPRT */
<> 150:02e0a0aed4ec 1266 #define _USB_HPRT_PRTTSTCTL_SHIFT 13 /**< Shift value for USB_PRTTSTCTL */
<> 150:02e0a0aed4ec 1267 #define _USB_HPRT_PRTTSTCTL_MASK 0x1E000UL /**< Bit mask for USB_PRTTSTCTL */
<> 150:02e0a0aed4ec 1268 #define _USB_HPRT_PRTTSTCTL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HPRT */
<> 150:02e0a0aed4ec 1269 #define _USB_HPRT_PRTTSTCTL_DISABLE 0x00000000UL /**< Mode DISABLE for USB_HPRT */
<> 150:02e0a0aed4ec 1270 #define _USB_HPRT_PRTTSTCTL_J 0x00000001UL /**< Mode J for USB_HPRT */
<> 150:02e0a0aed4ec 1271 #define _USB_HPRT_PRTTSTCTL_K 0x00000002UL /**< Mode K for USB_HPRT */
<> 150:02e0a0aed4ec 1272 #define _USB_HPRT_PRTTSTCTL_SE0NAK 0x00000003UL /**< Mode SE0NAK for USB_HPRT */
<> 150:02e0a0aed4ec 1273 #define _USB_HPRT_PRTTSTCTL_PACKET 0x00000004UL /**< Mode PACKET for USB_HPRT */
<> 150:02e0a0aed4ec 1274 #define _USB_HPRT_PRTTSTCTL_FORCE 0x00000005UL /**< Mode FORCE for USB_HPRT */
<> 150:02e0a0aed4ec 1275 #define USB_HPRT_PRTTSTCTL_DEFAULT (_USB_HPRT_PRTTSTCTL_DEFAULT << 13) /**< Shifted mode DEFAULT for USB_HPRT */
<> 150:02e0a0aed4ec 1276 #define USB_HPRT_PRTTSTCTL_DISABLE (_USB_HPRT_PRTTSTCTL_DISABLE << 13) /**< Shifted mode DISABLE for USB_HPRT */
<> 150:02e0a0aed4ec 1277 #define USB_HPRT_PRTTSTCTL_J (_USB_HPRT_PRTTSTCTL_J << 13) /**< Shifted mode J for USB_HPRT */
<> 150:02e0a0aed4ec 1278 #define USB_HPRT_PRTTSTCTL_K (_USB_HPRT_PRTTSTCTL_K << 13) /**< Shifted mode K for USB_HPRT */
<> 150:02e0a0aed4ec 1279 #define USB_HPRT_PRTTSTCTL_SE0NAK (_USB_HPRT_PRTTSTCTL_SE0NAK << 13) /**< Shifted mode SE0NAK for USB_HPRT */
<> 150:02e0a0aed4ec 1280 #define USB_HPRT_PRTTSTCTL_PACKET (_USB_HPRT_PRTTSTCTL_PACKET << 13) /**< Shifted mode PACKET for USB_HPRT */
<> 150:02e0a0aed4ec 1281 #define USB_HPRT_PRTTSTCTL_FORCE (_USB_HPRT_PRTTSTCTL_FORCE << 13) /**< Shifted mode FORCE for USB_HPRT */
<> 150:02e0a0aed4ec 1282 #define _USB_HPRT_PRTSPD_SHIFT 17 /**< Shift value for USB_PRTSPD */
<> 150:02e0a0aed4ec 1283 #define _USB_HPRT_PRTSPD_MASK 0x60000UL /**< Bit mask for USB_PRTSPD */
<> 150:02e0a0aed4ec 1284 #define _USB_HPRT_PRTSPD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HPRT */
<> 150:02e0a0aed4ec 1285 #define _USB_HPRT_PRTSPD_HS 0x00000000UL /**< Mode HS for USB_HPRT */
<> 150:02e0a0aed4ec 1286 #define _USB_HPRT_PRTSPD_FS 0x00000001UL /**< Mode FS for USB_HPRT */
<> 150:02e0a0aed4ec 1287 #define _USB_HPRT_PRTSPD_LS 0x00000002UL /**< Mode LS for USB_HPRT */
<> 150:02e0a0aed4ec 1288 #define USB_HPRT_PRTSPD_DEFAULT (_USB_HPRT_PRTSPD_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_HPRT */
<> 150:02e0a0aed4ec 1289 #define USB_HPRT_PRTSPD_HS (_USB_HPRT_PRTSPD_HS << 17) /**< Shifted mode HS for USB_HPRT */
<> 150:02e0a0aed4ec 1290 #define USB_HPRT_PRTSPD_FS (_USB_HPRT_PRTSPD_FS << 17) /**< Shifted mode FS for USB_HPRT */
<> 150:02e0a0aed4ec 1291 #define USB_HPRT_PRTSPD_LS (_USB_HPRT_PRTSPD_LS << 17) /**< Shifted mode LS for USB_HPRT */
<> 150:02e0a0aed4ec 1292
<> 150:02e0a0aed4ec 1293 /* Bit fields for USB HC_CHAR */
<> 150:02e0a0aed4ec 1294 #define _USB_HC_CHAR_RESETVALUE 0x00000000UL /**< Default value for USB_HC_CHAR */
<> 150:02e0a0aed4ec 1295 #define _USB_HC_CHAR_MASK 0xFFFEFFFFUL /**< Mask for USB_HC_CHAR */
<> 150:02e0a0aed4ec 1296 #define _USB_HC_CHAR_MPS_SHIFT 0 /**< Shift value for USB_MPS */
<> 150:02e0a0aed4ec 1297 #define _USB_HC_CHAR_MPS_MASK 0x7FFUL /**< Bit mask for USB_MPS */
<> 150:02e0a0aed4ec 1298 #define _USB_HC_CHAR_MPS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_CHAR */
<> 150:02e0a0aed4ec 1299 #define USB_HC_CHAR_MPS_DEFAULT (_USB_HC_CHAR_MPS_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_HC_CHAR */
<> 150:02e0a0aed4ec 1300 #define _USB_HC_CHAR_EPNUM_SHIFT 11 /**< Shift value for USB_EPNUM */
<> 150:02e0a0aed4ec 1301 #define _USB_HC_CHAR_EPNUM_MASK 0x7800UL /**< Bit mask for USB_EPNUM */
<> 150:02e0a0aed4ec 1302 #define _USB_HC_CHAR_EPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_CHAR */
<> 150:02e0a0aed4ec 1303 #define USB_HC_CHAR_EPNUM_DEFAULT (_USB_HC_CHAR_EPNUM_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_HC_CHAR */
<> 150:02e0a0aed4ec 1304 #define USB_HC_CHAR_EPDIR (0x1UL << 15) /**< Endpoint Direction */
<> 150:02e0a0aed4ec 1305 #define _USB_HC_CHAR_EPDIR_SHIFT 15 /**< Shift value for USB_EPDIR */
<> 150:02e0a0aed4ec 1306 #define _USB_HC_CHAR_EPDIR_MASK 0x8000UL /**< Bit mask for USB_EPDIR */
<> 150:02e0a0aed4ec 1307 #define _USB_HC_CHAR_EPDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_CHAR */
<> 150:02e0a0aed4ec 1308 #define _USB_HC_CHAR_EPDIR_OUT 0x00000000UL /**< Mode OUT for USB_HC_CHAR */
<> 150:02e0a0aed4ec 1309 #define _USB_HC_CHAR_EPDIR_IN 0x00000001UL /**< Mode IN for USB_HC_CHAR */
<> 150:02e0a0aed4ec 1310 #define USB_HC_CHAR_EPDIR_DEFAULT (_USB_HC_CHAR_EPDIR_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_HC_CHAR */
<> 150:02e0a0aed4ec 1311 #define USB_HC_CHAR_EPDIR_OUT (_USB_HC_CHAR_EPDIR_OUT << 15) /**< Shifted mode OUT for USB_HC_CHAR */
<> 150:02e0a0aed4ec 1312 #define USB_HC_CHAR_EPDIR_IN (_USB_HC_CHAR_EPDIR_IN << 15) /**< Shifted mode IN for USB_HC_CHAR */
<> 150:02e0a0aed4ec 1313 #define USB_HC_CHAR_LSPDDEV (0x1UL << 17) /**< Low-Speed Device */
<> 150:02e0a0aed4ec 1314 #define _USB_HC_CHAR_LSPDDEV_SHIFT 17 /**< Shift value for USB_LSPDDEV */
<> 150:02e0a0aed4ec 1315 #define _USB_HC_CHAR_LSPDDEV_MASK 0x20000UL /**< Bit mask for USB_LSPDDEV */
<> 150:02e0a0aed4ec 1316 #define _USB_HC_CHAR_LSPDDEV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_CHAR */
<> 150:02e0a0aed4ec 1317 #define USB_HC_CHAR_LSPDDEV_DEFAULT (_USB_HC_CHAR_LSPDDEV_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_HC_CHAR */
<> 150:02e0a0aed4ec 1318 #define _USB_HC_CHAR_EPTYPE_SHIFT 18 /**< Shift value for USB_EPTYPE */
<> 150:02e0a0aed4ec 1319 #define _USB_HC_CHAR_EPTYPE_MASK 0xC0000UL /**< Bit mask for USB_EPTYPE */
<> 150:02e0a0aed4ec 1320 #define _USB_HC_CHAR_EPTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_CHAR */
<> 150:02e0a0aed4ec 1321 #define _USB_HC_CHAR_EPTYPE_CONTROL 0x00000000UL /**< Mode CONTROL for USB_HC_CHAR */
<> 150:02e0a0aed4ec 1322 #define _USB_HC_CHAR_EPTYPE_ISO 0x00000001UL /**< Mode ISO for USB_HC_CHAR */
<> 150:02e0a0aed4ec 1323 #define _USB_HC_CHAR_EPTYPE_BULK 0x00000002UL /**< Mode BULK for USB_HC_CHAR */
<> 150:02e0a0aed4ec 1324 #define _USB_HC_CHAR_EPTYPE_INT 0x00000003UL /**< Mode INT for USB_HC_CHAR */
<> 150:02e0a0aed4ec 1325 #define USB_HC_CHAR_EPTYPE_DEFAULT (_USB_HC_CHAR_EPTYPE_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_HC_CHAR */
<> 150:02e0a0aed4ec 1326 #define USB_HC_CHAR_EPTYPE_CONTROL (_USB_HC_CHAR_EPTYPE_CONTROL << 18) /**< Shifted mode CONTROL for USB_HC_CHAR */
<> 150:02e0a0aed4ec 1327 #define USB_HC_CHAR_EPTYPE_ISO (_USB_HC_CHAR_EPTYPE_ISO << 18) /**< Shifted mode ISO for USB_HC_CHAR */
<> 150:02e0a0aed4ec 1328 #define USB_HC_CHAR_EPTYPE_BULK (_USB_HC_CHAR_EPTYPE_BULK << 18) /**< Shifted mode BULK for USB_HC_CHAR */
<> 150:02e0a0aed4ec 1329 #define USB_HC_CHAR_EPTYPE_INT (_USB_HC_CHAR_EPTYPE_INT << 18) /**< Shifted mode INT for USB_HC_CHAR */
<> 150:02e0a0aed4ec 1330 #define _USB_HC_CHAR_MC_SHIFT 20 /**< Shift value for USB_MC */
<> 150:02e0a0aed4ec 1331 #define _USB_HC_CHAR_MC_MASK 0x300000UL /**< Bit mask for USB_MC */
<> 150:02e0a0aed4ec 1332 #define _USB_HC_CHAR_MC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_CHAR */
<> 150:02e0a0aed4ec 1333 #define USB_HC_CHAR_MC_DEFAULT (_USB_HC_CHAR_MC_DEFAULT << 20) /**< Shifted mode DEFAULT for USB_HC_CHAR */
<> 150:02e0a0aed4ec 1334 #define _USB_HC_CHAR_DEVADDR_SHIFT 22 /**< Shift value for USB_DEVADDR */
<> 150:02e0a0aed4ec 1335 #define _USB_HC_CHAR_DEVADDR_MASK 0x1FC00000UL /**< Bit mask for USB_DEVADDR */
<> 150:02e0a0aed4ec 1336 #define _USB_HC_CHAR_DEVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_CHAR */
<> 150:02e0a0aed4ec 1337 #define USB_HC_CHAR_DEVADDR_DEFAULT (_USB_HC_CHAR_DEVADDR_DEFAULT << 22) /**< Shifted mode DEFAULT for USB_HC_CHAR */
<> 150:02e0a0aed4ec 1338 #define USB_HC_CHAR_ODDFRM (0x1UL << 29) /**< Odd Frame */
<> 150:02e0a0aed4ec 1339 #define _USB_HC_CHAR_ODDFRM_SHIFT 29 /**< Shift value for USB_ODDFRM */
<> 150:02e0a0aed4ec 1340 #define _USB_HC_CHAR_ODDFRM_MASK 0x20000000UL /**< Bit mask for USB_ODDFRM */
<> 150:02e0a0aed4ec 1341 #define _USB_HC_CHAR_ODDFRM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_CHAR */
<> 150:02e0a0aed4ec 1342 #define USB_HC_CHAR_ODDFRM_DEFAULT (_USB_HC_CHAR_ODDFRM_DEFAULT << 29) /**< Shifted mode DEFAULT for USB_HC_CHAR */
<> 150:02e0a0aed4ec 1343 #define USB_HC_CHAR_CHDIS (0x1UL << 30) /**< Channel Disable */
<> 150:02e0a0aed4ec 1344 #define _USB_HC_CHAR_CHDIS_SHIFT 30 /**< Shift value for USB_CHDIS */
<> 150:02e0a0aed4ec 1345 #define _USB_HC_CHAR_CHDIS_MASK 0x40000000UL /**< Bit mask for USB_CHDIS */
<> 150:02e0a0aed4ec 1346 #define _USB_HC_CHAR_CHDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_CHAR */
<> 150:02e0a0aed4ec 1347 #define USB_HC_CHAR_CHDIS_DEFAULT (_USB_HC_CHAR_CHDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for USB_HC_CHAR */
<> 150:02e0a0aed4ec 1348 #define USB_HC_CHAR_CHENA (0x1UL << 31) /**< Channel Enable */
<> 150:02e0a0aed4ec 1349 #define _USB_HC_CHAR_CHENA_SHIFT 31 /**< Shift value for USB_CHENA */
<> 150:02e0a0aed4ec 1350 #define _USB_HC_CHAR_CHENA_MASK 0x80000000UL /**< Bit mask for USB_CHENA */
<> 150:02e0a0aed4ec 1351 #define _USB_HC_CHAR_CHENA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_CHAR */
<> 150:02e0a0aed4ec 1352 #define USB_HC_CHAR_CHENA_DEFAULT (_USB_HC_CHAR_CHENA_DEFAULT << 31) /**< Shifted mode DEFAULT for USB_HC_CHAR */
<> 150:02e0a0aed4ec 1353
<> 150:02e0a0aed4ec 1354 /* Bit fields for USB HC_INT */
<> 150:02e0a0aed4ec 1355 #define _USB_HC_INT_RESETVALUE 0x00000000UL /**< Default value for USB_HC_INT */
<> 150:02e0a0aed4ec 1356 #define _USB_HC_INT_MASK 0x000007BFUL /**< Mask for USB_HC_INT */
<> 150:02e0a0aed4ec 1357 #define USB_HC_INT_XFERCOMPL (0x1UL << 0) /**< Transfer Completed */
<> 150:02e0a0aed4ec 1358 #define _USB_HC_INT_XFERCOMPL_SHIFT 0 /**< Shift value for USB_XFERCOMPL */
<> 150:02e0a0aed4ec 1359 #define _USB_HC_INT_XFERCOMPL_MASK 0x1UL /**< Bit mask for USB_XFERCOMPL */
<> 150:02e0a0aed4ec 1360 #define _USB_HC_INT_XFERCOMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INT */
<> 150:02e0a0aed4ec 1361 #define USB_HC_INT_XFERCOMPL_DEFAULT (_USB_HC_INT_XFERCOMPL_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_HC_INT */
<> 150:02e0a0aed4ec 1362 #define USB_HC_INT_CHHLTD (0x1UL << 1) /**< Channel Halted */
<> 150:02e0a0aed4ec 1363 #define _USB_HC_INT_CHHLTD_SHIFT 1 /**< Shift value for USB_CHHLTD */
<> 150:02e0a0aed4ec 1364 #define _USB_HC_INT_CHHLTD_MASK 0x2UL /**< Bit mask for USB_CHHLTD */
<> 150:02e0a0aed4ec 1365 #define _USB_HC_INT_CHHLTD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INT */
<> 150:02e0a0aed4ec 1366 #define USB_HC_INT_CHHLTD_DEFAULT (_USB_HC_INT_CHHLTD_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_HC_INT */
<> 150:02e0a0aed4ec 1367 #define USB_HC_INT_AHBERR (0x1UL << 2) /**< AHB Error */
<> 150:02e0a0aed4ec 1368 #define _USB_HC_INT_AHBERR_SHIFT 2 /**< Shift value for USB_AHBERR */
<> 150:02e0a0aed4ec 1369 #define _USB_HC_INT_AHBERR_MASK 0x4UL /**< Bit mask for USB_AHBERR */
<> 150:02e0a0aed4ec 1370 #define _USB_HC_INT_AHBERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INT */
<> 150:02e0a0aed4ec 1371 #define USB_HC_INT_AHBERR_DEFAULT (_USB_HC_INT_AHBERR_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_HC_INT */
<> 150:02e0a0aed4ec 1372 #define USB_HC_INT_STALL (0x1UL << 3) /**< STALL Response Received Interrupt */
<> 150:02e0a0aed4ec 1373 #define _USB_HC_INT_STALL_SHIFT 3 /**< Shift value for USB_STALL */
<> 150:02e0a0aed4ec 1374 #define _USB_HC_INT_STALL_MASK 0x8UL /**< Bit mask for USB_STALL */
<> 150:02e0a0aed4ec 1375 #define _USB_HC_INT_STALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INT */
<> 150:02e0a0aed4ec 1376 #define USB_HC_INT_STALL_DEFAULT (_USB_HC_INT_STALL_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_HC_INT */
<> 150:02e0a0aed4ec 1377 #define USB_HC_INT_NAK (0x1UL << 4) /**< NAK Response Received Interrupt */
<> 150:02e0a0aed4ec 1378 #define _USB_HC_INT_NAK_SHIFT 4 /**< Shift value for USB_NAK */
<> 150:02e0a0aed4ec 1379 #define _USB_HC_INT_NAK_MASK 0x10UL /**< Bit mask for USB_NAK */
<> 150:02e0a0aed4ec 1380 #define _USB_HC_INT_NAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INT */
<> 150:02e0a0aed4ec 1381 #define USB_HC_INT_NAK_DEFAULT (_USB_HC_INT_NAK_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_HC_INT */
<> 150:02e0a0aed4ec 1382 #define USB_HC_INT_ACK (0x1UL << 5) /**< ACK Response Received/Transmitted Interrupt */
<> 150:02e0a0aed4ec 1383 #define _USB_HC_INT_ACK_SHIFT 5 /**< Shift value for USB_ACK */
<> 150:02e0a0aed4ec 1384 #define _USB_HC_INT_ACK_MASK 0x20UL /**< Bit mask for USB_ACK */
<> 150:02e0a0aed4ec 1385 #define _USB_HC_INT_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INT */
<> 150:02e0a0aed4ec 1386 #define USB_HC_INT_ACK_DEFAULT (_USB_HC_INT_ACK_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_HC_INT */
<> 150:02e0a0aed4ec 1387 #define USB_HC_INT_XACTERR (0x1UL << 7) /**< Transaction Error */
<> 150:02e0a0aed4ec 1388 #define _USB_HC_INT_XACTERR_SHIFT 7 /**< Shift value for USB_XACTERR */
<> 150:02e0a0aed4ec 1389 #define _USB_HC_INT_XACTERR_MASK 0x80UL /**< Bit mask for USB_XACTERR */
<> 150:02e0a0aed4ec 1390 #define _USB_HC_INT_XACTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INT */
<> 150:02e0a0aed4ec 1391 #define USB_HC_INT_XACTERR_DEFAULT (_USB_HC_INT_XACTERR_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_HC_INT */
<> 150:02e0a0aed4ec 1392 #define USB_HC_INT_BBLERR (0x1UL << 8) /**< Babble Error */
<> 150:02e0a0aed4ec 1393 #define _USB_HC_INT_BBLERR_SHIFT 8 /**< Shift value for USB_BBLERR */
<> 150:02e0a0aed4ec 1394 #define _USB_HC_INT_BBLERR_MASK 0x100UL /**< Bit mask for USB_BBLERR */
<> 150:02e0a0aed4ec 1395 #define _USB_HC_INT_BBLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INT */
<> 150:02e0a0aed4ec 1396 #define USB_HC_INT_BBLERR_DEFAULT (_USB_HC_INT_BBLERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_HC_INT */
<> 150:02e0a0aed4ec 1397 #define USB_HC_INT_FRMOVRUN (0x1UL << 9) /**< Frame Overrun */
<> 150:02e0a0aed4ec 1398 #define _USB_HC_INT_FRMOVRUN_SHIFT 9 /**< Shift value for USB_FRMOVRUN */
<> 150:02e0a0aed4ec 1399 #define _USB_HC_INT_FRMOVRUN_MASK 0x200UL /**< Bit mask for USB_FRMOVRUN */
<> 150:02e0a0aed4ec 1400 #define _USB_HC_INT_FRMOVRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INT */
<> 150:02e0a0aed4ec 1401 #define USB_HC_INT_FRMOVRUN_DEFAULT (_USB_HC_INT_FRMOVRUN_DEFAULT << 9) /**< Shifted mode DEFAULT for USB_HC_INT */
<> 150:02e0a0aed4ec 1402 #define USB_HC_INT_DATATGLERR (0x1UL << 10) /**< Data Toggle Error */
<> 150:02e0a0aed4ec 1403 #define _USB_HC_INT_DATATGLERR_SHIFT 10 /**< Shift value for USB_DATATGLERR */
<> 150:02e0a0aed4ec 1404 #define _USB_HC_INT_DATATGLERR_MASK 0x400UL /**< Bit mask for USB_DATATGLERR */
<> 150:02e0a0aed4ec 1405 #define _USB_HC_INT_DATATGLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INT */
<> 150:02e0a0aed4ec 1406 #define USB_HC_INT_DATATGLERR_DEFAULT (_USB_HC_INT_DATATGLERR_DEFAULT << 10) /**< Shifted mode DEFAULT for USB_HC_INT */
<> 150:02e0a0aed4ec 1407
<> 150:02e0a0aed4ec 1408 /* Bit fields for USB HC_INTMSK */
<> 150:02e0a0aed4ec 1409 #define _USB_HC_INTMSK_RESETVALUE 0x00000000UL /**< Default value for USB_HC_INTMSK */
<> 150:02e0a0aed4ec 1410 #define _USB_HC_INTMSK_MASK 0x000007BFUL /**< Mask for USB_HC_INTMSK */
<> 150:02e0a0aed4ec 1411 #define USB_HC_INTMSK_XFERCOMPLMSK (0x1UL << 0) /**< Transfer Completed Mask */
<> 150:02e0a0aed4ec 1412 #define _USB_HC_INTMSK_XFERCOMPLMSK_SHIFT 0 /**< Shift value for USB_XFERCOMPLMSK */
<> 150:02e0a0aed4ec 1413 #define _USB_HC_INTMSK_XFERCOMPLMSK_MASK 0x1UL /**< Bit mask for USB_XFERCOMPLMSK */
<> 150:02e0a0aed4ec 1414 #define _USB_HC_INTMSK_XFERCOMPLMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INTMSK */
<> 150:02e0a0aed4ec 1415 #define USB_HC_INTMSK_XFERCOMPLMSK_DEFAULT (_USB_HC_INTMSK_XFERCOMPLMSK_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_HC_INTMSK */
<> 150:02e0a0aed4ec 1416 #define USB_HC_INTMSK_CHHLTDMSK (0x1UL << 1) /**< Channel Halted Mask */
<> 150:02e0a0aed4ec 1417 #define _USB_HC_INTMSK_CHHLTDMSK_SHIFT 1 /**< Shift value for USB_CHHLTDMSK */
<> 150:02e0a0aed4ec 1418 #define _USB_HC_INTMSK_CHHLTDMSK_MASK 0x2UL /**< Bit mask for USB_CHHLTDMSK */
<> 150:02e0a0aed4ec 1419 #define _USB_HC_INTMSK_CHHLTDMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INTMSK */
<> 150:02e0a0aed4ec 1420 #define USB_HC_INTMSK_CHHLTDMSK_DEFAULT (_USB_HC_INTMSK_CHHLTDMSK_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_HC_INTMSK */
<> 150:02e0a0aed4ec 1421 #define USB_HC_INTMSK_AHBERRMSK (0x1UL << 2) /**< AHB Error Mask */
<> 150:02e0a0aed4ec 1422 #define _USB_HC_INTMSK_AHBERRMSK_SHIFT 2 /**< Shift value for USB_AHBERRMSK */
<> 150:02e0a0aed4ec 1423 #define _USB_HC_INTMSK_AHBERRMSK_MASK 0x4UL /**< Bit mask for USB_AHBERRMSK */
<> 150:02e0a0aed4ec 1424 #define _USB_HC_INTMSK_AHBERRMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INTMSK */
<> 150:02e0a0aed4ec 1425 #define USB_HC_INTMSK_AHBERRMSK_DEFAULT (_USB_HC_INTMSK_AHBERRMSK_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_HC_INTMSK */
<> 150:02e0a0aed4ec 1426 #define USB_HC_INTMSK_STALLMSK (0x1UL << 3) /**< STALL Response Received Interrupt Mask */
<> 150:02e0a0aed4ec 1427 #define _USB_HC_INTMSK_STALLMSK_SHIFT 3 /**< Shift value for USB_STALLMSK */
<> 150:02e0a0aed4ec 1428 #define _USB_HC_INTMSK_STALLMSK_MASK 0x8UL /**< Bit mask for USB_STALLMSK */
<> 150:02e0a0aed4ec 1429 #define _USB_HC_INTMSK_STALLMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INTMSK */
<> 150:02e0a0aed4ec 1430 #define USB_HC_INTMSK_STALLMSK_DEFAULT (_USB_HC_INTMSK_STALLMSK_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_HC_INTMSK */
<> 150:02e0a0aed4ec 1431 #define USB_HC_INTMSK_NAKMSK (0x1UL << 4) /**< NAK Response Received Interrupt Mask */
<> 150:02e0a0aed4ec 1432 #define _USB_HC_INTMSK_NAKMSK_SHIFT 4 /**< Shift value for USB_NAKMSK */
<> 150:02e0a0aed4ec 1433 #define _USB_HC_INTMSK_NAKMSK_MASK 0x10UL /**< Bit mask for USB_NAKMSK */
<> 150:02e0a0aed4ec 1434 #define _USB_HC_INTMSK_NAKMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INTMSK */
<> 150:02e0a0aed4ec 1435 #define USB_HC_INTMSK_NAKMSK_DEFAULT (_USB_HC_INTMSK_NAKMSK_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_HC_INTMSK */
<> 150:02e0a0aed4ec 1436 #define USB_HC_INTMSK_ACKMSK (0x1UL << 5) /**< ACK Response Received/Transmitted Interrupt Mask */
<> 150:02e0a0aed4ec 1437 #define _USB_HC_INTMSK_ACKMSK_SHIFT 5 /**< Shift value for USB_ACKMSK */
<> 150:02e0a0aed4ec 1438 #define _USB_HC_INTMSK_ACKMSK_MASK 0x20UL /**< Bit mask for USB_ACKMSK */
<> 150:02e0a0aed4ec 1439 #define _USB_HC_INTMSK_ACKMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INTMSK */
<> 150:02e0a0aed4ec 1440 #define USB_HC_INTMSK_ACKMSK_DEFAULT (_USB_HC_INTMSK_ACKMSK_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_HC_INTMSK */
<> 150:02e0a0aed4ec 1441 #define USB_HC_INTMSK_XACTERRMSK (0x1UL << 7) /**< Transaction Error Mask */
<> 150:02e0a0aed4ec 1442 #define _USB_HC_INTMSK_XACTERRMSK_SHIFT 7 /**< Shift value for USB_XACTERRMSK */
<> 150:02e0a0aed4ec 1443 #define _USB_HC_INTMSK_XACTERRMSK_MASK 0x80UL /**< Bit mask for USB_XACTERRMSK */
<> 150:02e0a0aed4ec 1444 #define _USB_HC_INTMSK_XACTERRMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INTMSK */
<> 150:02e0a0aed4ec 1445 #define USB_HC_INTMSK_XACTERRMSK_DEFAULT (_USB_HC_INTMSK_XACTERRMSK_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_HC_INTMSK */
<> 150:02e0a0aed4ec 1446 #define USB_HC_INTMSK_BBLERRMSK (0x1UL << 8) /**< Babble Error Mask */
<> 150:02e0a0aed4ec 1447 #define _USB_HC_INTMSK_BBLERRMSK_SHIFT 8 /**< Shift value for USB_BBLERRMSK */
<> 150:02e0a0aed4ec 1448 #define _USB_HC_INTMSK_BBLERRMSK_MASK 0x100UL /**< Bit mask for USB_BBLERRMSK */
<> 150:02e0a0aed4ec 1449 #define _USB_HC_INTMSK_BBLERRMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INTMSK */
<> 150:02e0a0aed4ec 1450 #define USB_HC_INTMSK_BBLERRMSK_DEFAULT (_USB_HC_INTMSK_BBLERRMSK_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_HC_INTMSK */
<> 150:02e0a0aed4ec 1451 #define USB_HC_INTMSK_FRMOVRUNMSK (0x1UL << 9) /**< Frame Overrun Mask */
<> 150:02e0a0aed4ec 1452 #define _USB_HC_INTMSK_FRMOVRUNMSK_SHIFT 9 /**< Shift value for USB_FRMOVRUNMSK */
<> 150:02e0a0aed4ec 1453 #define _USB_HC_INTMSK_FRMOVRUNMSK_MASK 0x200UL /**< Bit mask for USB_FRMOVRUNMSK */
<> 150:02e0a0aed4ec 1454 #define _USB_HC_INTMSK_FRMOVRUNMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INTMSK */
<> 150:02e0a0aed4ec 1455 #define USB_HC_INTMSK_FRMOVRUNMSK_DEFAULT (_USB_HC_INTMSK_FRMOVRUNMSK_DEFAULT << 9) /**< Shifted mode DEFAULT for USB_HC_INTMSK */
<> 150:02e0a0aed4ec 1456 #define USB_HC_INTMSK_DATATGLERRMSK (0x1UL << 10) /**< Data Toggle Error Mask */
<> 150:02e0a0aed4ec 1457 #define _USB_HC_INTMSK_DATATGLERRMSK_SHIFT 10 /**< Shift value for USB_DATATGLERRMSK */
<> 150:02e0a0aed4ec 1458 #define _USB_HC_INTMSK_DATATGLERRMSK_MASK 0x400UL /**< Bit mask for USB_DATATGLERRMSK */
<> 150:02e0a0aed4ec 1459 #define _USB_HC_INTMSK_DATATGLERRMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INTMSK */
<> 150:02e0a0aed4ec 1460 #define USB_HC_INTMSK_DATATGLERRMSK_DEFAULT (_USB_HC_INTMSK_DATATGLERRMSK_DEFAULT << 10) /**< Shifted mode DEFAULT for USB_HC_INTMSK */
<> 150:02e0a0aed4ec 1461
<> 150:02e0a0aed4ec 1462 /* Bit fields for USB HC_TSIZ */
<> 150:02e0a0aed4ec 1463 #define _USB_HC_TSIZ_RESETVALUE 0x00000000UL /**< Default value for USB_HC_TSIZ */
<> 150:02e0a0aed4ec 1464 #define _USB_HC_TSIZ_MASK 0x7FFFFFFFUL /**< Mask for USB_HC_TSIZ */
<> 150:02e0a0aed4ec 1465 #define _USB_HC_TSIZ_XFERSIZE_SHIFT 0 /**< Shift value for USB_XFERSIZE */
<> 150:02e0a0aed4ec 1466 #define _USB_HC_TSIZ_XFERSIZE_MASK 0x7FFFFUL /**< Bit mask for USB_XFERSIZE */
<> 150:02e0a0aed4ec 1467 #define _USB_HC_TSIZ_XFERSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_TSIZ */
<> 150:02e0a0aed4ec 1468 #define USB_HC_TSIZ_XFERSIZE_DEFAULT (_USB_HC_TSIZ_XFERSIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_HC_TSIZ */
<> 150:02e0a0aed4ec 1469 #define _USB_HC_TSIZ_PKTCNT_SHIFT 19 /**< Shift value for USB_PKTCNT */
<> 150:02e0a0aed4ec 1470 #define _USB_HC_TSIZ_PKTCNT_MASK 0x1FF80000UL /**< Bit mask for USB_PKTCNT */
<> 150:02e0a0aed4ec 1471 #define _USB_HC_TSIZ_PKTCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_TSIZ */
<> 150:02e0a0aed4ec 1472 #define USB_HC_TSIZ_PKTCNT_DEFAULT (_USB_HC_TSIZ_PKTCNT_DEFAULT << 19) /**< Shifted mode DEFAULT for USB_HC_TSIZ */
<> 150:02e0a0aed4ec 1473 #define _USB_HC_TSIZ_PID_SHIFT 29 /**< Shift value for USB_PID */
<> 150:02e0a0aed4ec 1474 #define _USB_HC_TSIZ_PID_MASK 0x60000000UL /**< Bit mask for USB_PID */
<> 150:02e0a0aed4ec 1475 #define _USB_HC_TSIZ_PID_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_TSIZ */
<> 150:02e0a0aed4ec 1476 #define _USB_HC_TSIZ_PID_DATA0 0x00000000UL /**< Mode DATA0 for USB_HC_TSIZ */
<> 150:02e0a0aed4ec 1477 #define _USB_HC_TSIZ_PID_DATA2 0x00000001UL /**< Mode DATA2 for USB_HC_TSIZ */
<> 150:02e0a0aed4ec 1478 #define _USB_HC_TSIZ_PID_DATA1 0x00000002UL /**< Mode DATA1 for USB_HC_TSIZ */
<> 150:02e0a0aed4ec 1479 #define _USB_HC_TSIZ_PID_MDATA 0x00000003UL /**< Mode MDATA for USB_HC_TSIZ */
<> 150:02e0a0aed4ec 1480 #define USB_HC_TSIZ_PID_DEFAULT (_USB_HC_TSIZ_PID_DEFAULT << 29) /**< Shifted mode DEFAULT for USB_HC_TSIZ */
<> 150:02e0a0aed4ec 1481 #define USB_HC_TSIZ_PID_DATA0 (_USB_HC_TSIZ_PID_DATA0 << 29) /**< Shifted mode DATA0 for USB_HC_TSIZ */
<> 150:02e0a0aed4ec 1482 #define USB_HC_TSIZ_PID_DATA2 (_USB_HC_TSIZ_PID_DATA2 << 29) /**< Shifted mode DATA2 for USB_HC_TSIZ */
<> 150:02e0a0aed4ec 1483 #define USB_HC_TSIZ_PID_DATA1 (_USB_HC_TSIZ_PID_DATA1 << 29) /**< Shifted mode DATA1 for USB_HC_TSIZ */
<> 150:02e0a0aed4ec 1484 #define USB_HC_TSIZ_PID_MDATA (_USB_HC_TSIZ_PID_MDATA << 29) /**< Shifted mode MDATA for USB_HC_TSIZ */
<> 150:02e0a0aed4ec 1485
<> 150:02e0a0aed4ec 1486 /* Bit fields for USB HC_DMAADDR */
<> 150:02e0a0aed4ec 1487 #define _USB_HC_DMAADDR_RESETVALUE 0x00000000UL /**< Default value for USB_HC_DMAADDR */
<> 150:02e0a0aed4ec 1488 #define _USB_HC_DMAADDR_MASK 0xFFFFFFFFUL /**< Mask for USB_HC_DMAADDR */
<> 150:02e0a0aed4ec 1489 #define _USB_HC_DMAADDR_DMAADDR_SHIFT 0 /**< Shift value for USB_DMAADDR */
<> 150:02e0a0aed4ec 1490 #define _USB_HC_DMAADDR_DMAADDR_MASK 0xFFFFFFFFUL /**< Bit mask for USB_DMAADDR */
<> 150:02e0a0aed4ec 1491 #define _USB_HC_DMAADDR_DMAADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_DMAADDR */
<> 150:02e0a0aed4ec 1492 #define USB_HC_DMAADDR_DMAADDR_DEFAULT (_USB_HC_DMAADDR_DMAADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_HC_DMAADDR */
<> 150:02e0a0aed4ec 1493
<> 150:02e0a0aed4ec 1494 /* Bit fields for USB DCFG */
<> 150:02e0a0aed4ec 1495 #define _USB_DCFG_RESETVALUE 0x08200000UL /**< Default value for USB_DCFG */
<> 150:02e0a0aed4ec 1496 #define _USB_DCFG_MASK 0xFC001FFFUL /**< Mask for USB_DCFG */
<> 150:02e0a0aed4ec 1497 #define _USB_DCFG_DEVSPD_SHIFT 0 /**< Shift value for USB_DEVSPD */
<> 150:02e0a0aed4ec 1498 #define _USB_DCFG_DEVSPD_MASK 0x3UL /**< Bit mask for USB_DEVSPD */
<> 150:02e0a0aed4ec 1499 #define _USB_DCFG_DEVSPD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCFG */
<> 150:02e0a0aed4ec 1500 #define _USB_DCFG_DEVSPD_LS 0x00000002UL /**< Mode LS for USB_DCFG */
<> 150:02e0a0aed4ec 1501 #define _USB_DCFG_DEVSPD_FS 0x00000003UL /**< Mode FS for USB_DCFG */
<> 150:02e0a0aed4ec 1502 #define USB_DCFG_DEVSPD_DEFAULT (_USB_DCFG_DEVSPD_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DCFG */
<> 150:02e0a0aed4ec 1503 #define USB_DCFG_DEVSPD_LS (_USB_DCFG_DEVSPD_LS << 0) /**< Shifted mode LS for USB_DCFG */
<> 150:02e0a0aed4ec 1504 #define USB_DCFG_DEVSPD_FS (_USB_DCFG_DEVSPD_FS << 0) /**< Shifted mode FS for USB_DCFG */
<> 150:02e0a0aed4ec 1505 #define USB_DCFG_NZSTSOUTHSHK (0x1UL << 2) /**< Non-Zero-Length Status OUT Handshake */
<> 150:02e0a0aed4ec 1506 #define _USB_DCFG_NZSTSOUTHSHK_SHIFT 2 /**< Shift value for USB_NZSTSOUTHSHK */
<> 150:02e0a0aed4ec 1507 #define _USB_DCFG_NZSTSOUTHSHK_MASK 0x4UL /**< Bit mask for USB_NZSTSOUTHSHK */
<> 150:02e0a0aed4ec 1508 #define _USB_DCFG_NZSTSOUTHSHK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCFG */
<> 150:02e0a0aed4ec 1509 #define USB_DCFG_NZSTSOUTHSHK_DEFAULT (_USB_DCFG_NZSTSOUTHSHK_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_DCFG */
<> 150:02e0a0aed4ec 1510 #define USB_DCFG_ENA32KHZSUSP (0x1UL << 3) /**< Enable 32 KHz Suspend mode */
<> 150:02e0a0aed4ec 1511 #define _USB_DCFG_ENA32KHZSUSP_SHIFT 3 /**< Shift value for USB_ENA32KHZSUSP */
<> 150:02e0a0aed4ec 1512 #define _USB_DCFG_ENA32KHZSUSP_MASK 0x8UL /**< Bit mask for USB_ENA32KHZSUSP */
<> 150:02e0a0aed4ec 1513 #define _USB_DCFG_ENA32KHZSUSP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCFG */
<> 150:02e0a0aed4ec 1514 #define USB_DCFG_ENA32KHZSUSP_DEFAULT (_USB_DCFG_ENA32KHZSUSP_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_DCFG */
<> 150:02e0a0aed4ec 1515 #define _USB_DCFG_DEVADDR_SHIFT 4 /**< Shift value for USB_DEVADDR */
<> 150:02e0a0aed4ec 1516 #define _USB_DCFG_DEVADDR_MASK 0x7F0UL /**< Bit mask for USB_DEVADDR */
<> 150:02e0a0aed4ec 1517 #define _USB_DCFG_DEVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCFG */
<> 150:02e0a0aed4ec 1518 #define USB_DCFG_DEVADDR_DEFAULT (_USB_DCFG_DEVADDR_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_DCFG */
<> 150:02e0a0aed4ec 1519 #define _USB_DCFG_PERFRINT_SHIFT 11 /**< Shift value for USB_PERFRINT */
<> 150:02e0a0aed4ec 1520 #define _USB_DCFG_PERFRINT_MASK 0x1800UL /**< Bit mask for USB_PERFRINT */
<> 150:02e0a0aed4ec 1521 #define _USB_DCFG_PERFRINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCFG */
<> 150:02e0a0aed4ec 1522 #define _USB_DCFG_PERFRINT_80PCNT 0x00000000UL /**< Mode 80PCNT for USB_DCFG */
<> 150:02e0a0aed4ec 1523 #define _USB_DCFG_PERFRINT_85PCNT 0x00000001UL /**< Mode 85PCNT for USB_DCFG */
<> 150:02e0a0aed4ec 1524 #define _USB_DCFG_PERFRINT_90PCNT 0x00000002UL /**< Mode 90PCNT for USB_DCFG */
<> 150:02e0a0aed4ec 1525 #define _USB_DCFG_PERFRINT_95PCNT 0x00000003UL /**< Mode 95PCNT for USB_DCFG */
<> 150:02e0a0aed4ec 1526 #define USB_DCFG_PERFRINT_DEFAULT (_USB_DCFG_PERFRINT_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_DCFG */
<> 150:02e0a0aed4ec 1527 #define USB_DCFG_PERFRINT_80PCNT (_USB_DCFG_PERFRINT_80PCNT << 11) /**< Shifted mode 80PCNT for USB_DCFG */
<> 150:02e0a0aed4ec 1528 #define USB_DCFG_PERFRINT_85PCNT (_USB_DCFG_PERFRINT_85PCNT << 11) /**< Shifted mode 85PCNT for USB_DCFG */
<> 150:02e0a0aed4ec 1529 #define USB_DCFG_PERFRINT_90PCNT (_USB_DCFG_PERFRINT_90PCNT << 11) /**< Shifted mode 90PCNT for USB_DCFG */
<> 150:02e0a0aed4ec 1530 #define USB_DCFG_PERFRINT_95PCNT (_USB_DCFG_PERFRINT_95PCNT << 11) /**< Shifted mode 95PCNT for USB_DCFG */
<> 150:02e0a0aed4ec 1531 #define _USB_DCFG_RESVALID_SHIFT 26 /**< Shift value for USB_RESVALID */
<> 150:02e0a0aed4ec 1532 #define _USB_DCFG_RESVALID_MASK 0xFC000000UL /**< Bit mask for USB_RESVALID */
<> 150:02e0a0aed4ec 1533 #define _USB_DCFG_RESVALID_DEFAULT 0x00000002UL /**< Mode DEFAULT for USB_DCFG */
<> 150:02e0a0aed4ec 1534 #define USB_DCFG_RESVALID_DEFAULT (_USB_DCFG_RESVALID_DEFAULT << 26) /**< Shifted mode DEFAULT for USB_DCFG */
<> 150:02e0a0aed4ec 1535
<> 150:02e0a0aed4ec 1536 /* Bit fields for USB DCTL */
<> 150:02e0a0aed4ec 1537 #define _USB_DCTL_RESETVALUE 0x00000000UL /**< Default value for USB_DCTL */
<> 150:02e0a0aed4ec 1538 #define _USB_DCTL_MASK 0x00018FFFUL /**< Mask for USB_DCTL */
<> 150:02e0a0aed4ec 1539 #define USB_DCTL_RMTWKUPSIG (0x1UL << 0) /**< Remote Wakeup Signaling */
<> 150:02e0a0aed4ec 1540 #define _USB_DCTL_RMTWKUPSIG_SHIFT 0 /**< Shift value for USB_RMTWKUPSIG */
<> 150:02e0a0aed4ec 1541 #define _USB_DCTL_RMTWKUPSIG_MASK 0x1UL /**< Bit mask for USB_RMTWKUPSIG */
<> 150:02e0a0aed4ec 1542 #define _USB_DCTL_RMTWKUPSIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCTL */
<> 150:02e0a0aed4ec 1543 #define USB_DCTL_RMTWKUPSIG_DEFAULT (_USB_DCTL_RMTWKUPSIG_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DCTL */
<> 150:02e0a0aed4ec 1544 #define USB_DCTL_SFTDISCON (0x1UL << 1) /**< Soft Disconnect */
<> 150:02e0a0aed4ec 1545 #define _USB_DCTL_SFTDISCON_SHIFT 1 /**< Shift value for USB_SFTDISCON */
<> 150:02e0a0aed4ec 1546 #define _USB_DCTL_SFTDISCON_MASK 0x2UL /**< Bit mask for USB_SFTDISCON */
<> 150:02e0a0aed4ec 1547 #define _USB_DCTL_SFTDISCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCTL */
<> 150:02e0a0aed4ec 1548 #define USB_DCTL_SFTDISCON_DEFAULT (_USB_DCTL_SFTDISCON_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_DCTL */
<> 150:02e0a0aed4ec 1549 #define USB_DCTL_GNPINNAKSTS (0x1UL << 2) /**< Global Non-periodic IN NAK Status */
<> 150:02e0a0aed4ec 1550 #define _USB_DCTL_GNPINNAKSTS_SHIFT 2 /**< Shift value for USB_GNPINNAKSTS */
<> 150:02e0a0aed4ec 1551 #define _USB_DCTL_GNPINNAKSTS_MASK 0x4UL /**< Bit mask for USB_GNPINNAKSTS */
<> 150:02e0a0aed4ec 1552 #define _USB_DCTL_GNPINNAKSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCTL */
<> 150:02e0a0aed4ec 1553 #define USB_DCTL_GNPINNAKSTS_DEFAULT (_USB_DCTL_GNPINNAKSTS_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_DCTL */
<> 150:02e0a0aed4ec 1554 #define USB_DCTL_GOUTNAKSTS (0x1UL << 3) /**< Global OUT NAK Status */
<> 150:02e0a0aed4ec 1555 #define _USB_DCTL_GOUTNAKSTS_SHIFT 3 /**< Shift value for USB_GOUTNAKSTS */
<> 150:02e0a0aed4ec 1556 #define _USB_DCTL_GOUTNAKSTS_MASK 0x8UL /**< Bit mask for USB_GOUTNAKSTS */
<> 150:02e0a0aed4ec 1557 #define _USB_DCTL_GOUTNAKSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCTL */
<> 150:02e0a0aed4ec 1558 #define USB_DCTL_GOUTNAKSTS_DEFAULT (_USB_DCTL_GOUTNAKSTS_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_DCTL */
<> 150:02e0a0aed4ec 1559 #define _USB_DCTL_TSTCTL_SHIFT 4 /**< Shift value for USB_TSTCTL */
<> 150:02e0a0aed4ec 1560 #define _USB_DCTL_TSTCTL_MASK 0x70UL /**< Bit mask for USB_TSTCTL */
<> 150:02e0a0aed4ec 1561 #define _USB_DCTL_TSTCTL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCTL */
<> 150:02e0a0aed4ec 1562 #define _USB_DCTL_TSTCTL_DISABLE 0x00000000UL /**< Mode DISABLE for USB_DCTL */
<> 150:02e0a0aed4ec 1563 #define _USB_DCTL_TSTCTL_J 0x00000001UL /**< Mode J for USB_DCTL */
<> 150:02e0a0aed4ec 1564 #define _USB_DCTL_TSTCTL_K 0x00000002UL /**< Mode K for USB_DCTL */
<> 150:02e0a0aed4ec 1565 #define _USB_DCTL_TSTCTL_SE0NAK 0x00000003UL /**< Mode SE0NAK for USB_DCTL */
<> 150:02e0a0aed4ec 1566 #define _USB_DCTL_TSTCTL_PACKET 0x00000004UL /**< Mode PACKET for USB_DCTL */
<> 150:02e0a0aed4ec 1567 #define _USB_DCTL_TSTCTL_FORCE 0x00000005UL /**< Mode FORCE for USB_DCTL */
<> 150:02e0a0aed4ec 1568 #define USB_DCTL_TSTCTL_DEFAULT (_USB_DCTL_TSTCTL_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_DCTL */
<> 150:02e0a0aed4ec 1569 #define USB_DCTL_TSTCTL_DISABLE (_USB_DCTL_TSTCTL_DISABLE << 4) /**< Shifted mode DISABLE for USB_DCTL */
<> 150:02e0a0aed4ec 1570 #define USB_DCTL_TSTCTL_J (_USB_DCTL_TSTCTL_J << 4) /**< Shifted mode J for USB_DCTL */
<> 150:02e0a0aed4ec 1571 #define USB_DCTL_TSTCTL_K (_USB_DCTL_TSTCTL_K << 4) /**< Shifted mode K for USB_DCTL */
<> 150:02e0a0aed4ec 1572 #define USB_DCTL_TSTCTL_SE0NAK (_USB_DCTL_TSTCTL_SE0NAK << 4) /**< Shifted mode SE0NAK for USB_DCTL */
<> 150:02e0a0aed4ec 1573 #define USB_DCTL_TSTCTL_PACKET (_USB_DCTL_TSTCTL_PACKET << 4) /**< Shifted mode PACKET for USB_DCTL */
<> 150:02e0a0aed4ec 1574 #define USB_DCTL_TSTCTL_FORCE (_USB_DCTL_TSTCTL_FORCE << 4) /**< Shifted mode FORCE for USB_DCTL */
<> 150:02e0a0aed4ec 1575 #define USB_DCTL_SGNPINNAK (0x1UL << 7) /**< Set Global Non-periodic IN NAK */
<> 150:02e0a0aed4ec 1576 #define _USB_DCTL_SGNPINNAK_SHIFT 7 /**< Shift value for USB_SGNPINNAK */
<> 150:02e0a0aed4ec 1577 #define _USB_DCTL_SGNPINNAK_MASK 0x80UL /**< Bit mask for USB_SGNPINNAK */
<> 150:02e0a0aed4ec 1578 #define _USB_DCTL_SGNPINNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCTL */
<> 150:02e0a0aed4ec 1579 #define USB_DCTL_SGNPINNAK_DEFAULT (_USB_DCTL_SGNPINNAK_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_DCTL */
<> 150:02e0a0aed4ec 1580 #define USB_DCTL_CGNPINNAK (0x1UL << 8) /**< Clear Global Non-periodic IN NAK */
<> 150:02e0a0aed4ec 1581 #define _USB_DCTL_CGNPINNAK_SHIFT 8 /**< Shift value for USB_CGNPINNAK */
<> 150:02e0a0aed4ec 1582 #define _USB_DCTL_CGNPINNAK_MASK 0x100UL /**< Bit mask for USB_CGNPINNAK */
<> 150:02e0a0aed4ec 1583 #define _USB_DCTL_CGNPINNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCTL */
<> 150:02e0a0aed4ec 1584 #define USB_DCTL_CGNPINNAK_DEFAULT (_USB_DCTL_CGNPINNAK_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_DCTL */
<> 150:02e0a0aed4ec 1585 #define USB_DCTL_SGOUTNAK (0x1UL << 9) /**< Set Global OUT NAK */
<> 150:02e0a0aed4ec 1586 #define _USB_DCTL_SGOUTNAK_SHIFT 9 /**< Shift value for USB_SGOUTNAK */
<> 150:02e0a0aed4ec 1587 #define _USB_DCTL_SGOUTNAK_MASK 0x200UL /**< Bit mask for USB_SGOUTNAK */
<> 150:02e0a0aed4ec 1588 #define _USB_DCTL_SGOUTNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCTL */
<> 150:02e0a0aed4ec 1589 #define USB_DCTL_SGOUTNAK_DEFAULT (_USB_DCTL_SGOUTNAK_DEFAULT << 9) /**< Shifted mode DEFAULT for USB_DCTL */
<> 150:02e0a0aed4ec 1590 #define USB_DCTL_CGOUTNAK (0x1UL << 10) /**< Clear Global OUT NAK */
<> 150:02e0a0aed4ec 1591 #define _USB_DCTL_CGOUTNAK_SHIFT 10 /**< Shift value for USB_CGOUTNAK */
<> 150:02e0a0aed4ec 1592 #define _USB_DCTL_CGOUTNAK_MASK 0x400UL /**< Bit mask for USB_CGOUTNAK */
<> 150:02e0a0aed4ec 1593 #define _USB_DCTL_CGOUTNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCTL */
<> 150:02e0a0aed4ec 1594 #define USB_DCTL_CGOUTNAK_DEFAULT (_USB_DCTL_CGOUTNAK_DEFAULT << 10) /**< Shifted mode DEFAULT for USB_DCTL */
<> 150:02e0a0aed4ec 1595 #define USB_DCTL_PWRONPRGDONE (0x1UL << 11) /**< Power-On Programming Done */
<> 150:02e0a0aed4ec 1596 #define _USB_DCTL_PWRONPRGDONE_SHIFT 11 /**< Shift value for USB_PWRONPRGDONE */
<> 150:02e0a0aed4ec 1597 #define _USB_DCTL_PWRONPRGDONE_MASK 0x800UL /**< Bit mask for USB_PWRONPRGDONE */
<> 150:02e0a0aed4ec 1598 #define _USB_DCTL_PWRONPRGDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCTL */
<> 150:02e0a0aed4ec 1599 #define USB_DCTL_PWRONPRGDONE_DEFAULT (_USB_DCTL_PWRONPRGDONE_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_DCTL */
<> 150:02e0a0aed4ec 1600 #define USB_DCTL_IGNRFRMNUM (0x1UL << 15) /**< Ignore Frame number For Isochronous End points */
<> 150:02e0a0aed4ec 1601 #define _USB_DCTL_IGNRFRMNUM_SHIFT 15 /**< Shift value for USB_IGNRFRMNUM */
<> 150:02e0a0aed4ec 1602 #define _USB_DCTL_IGNRFRMNUM_MASK 0x8000UL /**< Bit mask for USB_IGNRFRMNUM */
<> 150:02e0a0aed4ec 1603 #define _USB_DCTL_IGNRFRMNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCTL */
<> 150:02e0a0aed4ec 1604 #define USB_DCTL_IGNRFRMNUM_DEFAULT (_USB_DCTL_IGNRFRMNUM_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_DCTL */
<> 150:02e0a0aed4ec 1605 #define USB_DCTL_NAKONBBLE (0x1UL << 16) /**< NAK on Babble Error */
<> 150:02e0a0aed4ec 1606 #define _USB_DCTL_NAKONBBLE_SHIFT 16 /**< Shift value for USB_NAKONBBLE */
<> 150:02e0a0aed4ec 1607 #define _USB_DCTL_NAKONBBLE_MASK 0x10000UL /**< Bit mask for USB_NAKONBBLE */
<> 150:02e0a0aed4ec 1608 #define _USB_DCTL_NAKONBBLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCTL */
<> 150:02e0a0aed4ec 1609 #define USB_DCTL_NAKONBBLE_DEFAULT (_USB_DCTL_NAKONBBLE_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_DCTL */
<> 150:02e0a0aed4ec 1610
<> 150:02e0a0aed4ec 1611 /* Bit fields for USB DSTS */
<> 150:02e0a0aed4ec 1612 #define _USB_DSTS_RESETVALUE 0x00000002UL /**< Default value for USB_DSTS */
<> 150:02e0a0aed4ec 1613 #define _USB_DSTS_MASK 0x003FFF0FUL /**< Mask for USB_DSTS */
<> 150:02e0a0aed4ec 1614 #define USB_DSTS_SUSPSTS (0x1UL << 0) /**< Suspend Status */
<> 150:02e0a0aed4ec 1615 #define _USB_DSTS_SUSPSTS_SHIFT 0 /**< Shift value for USB_SUSPSTS */
<> 150:02e0a0aed4ec 1616 #define _USB_DSTS_SUSPSTS_MASK 0x1UL /**< Bit mask for USB_SUSPSTS */
<> 150:02e0a0aed4ec 1617 #define _USB_DSTS_SUSPSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DSTS */
<> 150:02e0a0aed4ec 1618 #define USB_DSTS_SUSPSTS_DEFAULT (_USB_DSTS_SUSPSTS_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DSTS */
<> 150:02e0a0aed4ec 1619 #define _USB_DSTS_ENUMSPD_SHIFT 1 /**< Shift value for USB_ENUMSPD */
<> 150:02e0a0aed4ec 1620 #define _USB_DSTS_ENUMSPD_MASK 0x6UL /**< Bit mask for USB_ENUMSPD */
<> 150:02e0a0aed4ec 1621 #define _USB_DSTS_ENUMSPD_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_DSTS */
<> 150:02e0a0aed4ec 1622 #define _USB_DSTS_ENUMSPD_LS 0x00000002UL /**< Mode LS for USB_DSTS */
<> 150:02e0a0aed4ec 1623 #define _USB_DSTS_ENUMSPD_FS 0x00000003UL /**< Mode FS for USB_DSTS */
<> 150:02e0a0aed4ec 1624 #define USB_DSTS_ENUMSPD_DEFAULT (_USB_DSTS_ENUMSPD_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_DSTS */
<> 150:02e0a0aed4ec 1625 #define USB_DSTS_ENUMSPD_LS (_USB_DSTS_ENUMSPD_LS << 1) /**< Shifted mode LS for USB_DSTS */
<> 150:02e0a0aed4ec 1626 #define USB_DSTS_ENUMSPD_FS (_USB_DSTS_ENUMSPD_FS << 1) /**< Shifted mode FS for USB_DSTS */
<> 150:02e0a0aed4ec 1627 #define USB_DSTS_ERRTICERR (0x1UL << 3) /**< Erratic Error */
<> 150:02e0a0aed4ec 1628 #define _USB_DSTS_ERRTICERR_SHIFT 3 /**< Shift value for USB_ERRTICERR */
<> 150:02e0a0aed4ec 1629 #define _USB_DSTS_ERRTICERR_MASK 0x8UL /**< Bit mask for USB_ERRTICERR */
<> 150:02e0a0aed4ec 1630 #define _USB_DSTS_ERRTICERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DSTS */
<> 150:02e0a0aed4ec 1631 #define USB_DSTS_ERRTICERR_DEFAULT (_USB_DSTS_ERRTICERR_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_DSTS */
<> 150:02e0a0aed4ec 1632 #define _USB_DSTS_SOFFN_SHIFT 8 /**< Shift value for USB_SOFFN */
<> 150:02e0a0aed4ec 1633 #define _USB_DSTS_SOFFN_MASK 0x3FFF00UL /**< Bit mask for USB_SOFFN */
<> 150:02e0a0aed4ec 1634 #define _USB_DSTS_SOFFN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DSTS */
<> 150:02e0a0aed4ec 1635 #define USB_DSTS_SOFFN_DEFAULT (_USB_DSTS_SOFFN_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_DSTS */
<> 150:02e0a0aed4ec 1636
<> 150:02e0a0aed4ec 1637 /* Bit fields for USB DIEPMSK */
<> 150:02e0a0aed4ec 1638 #define _USB_DIEPMSK_RESETVALUE 0x00000000UL /**< Default value for USB_DIEPMSK */
<> 150:02e0a0aed4ec 1639 #define _USB_DIEPMSK_MASK 0x0000215FUL /**< Mask for USB_DIEPMSK */
<> 150:02e0a0aed4ec 1640 #define USB_DIEPMSK_XFERCOMPLMSK (0x1UL << 0) /**< Transfer Completed Interrupt Mask */
<> 150:02e0a0aed4ec 1641 #define _USB_DIEPMSK_XFERCOMPLMSK_SHIFT 0 /**< Shift value for USB_XFERCOMPLMSK */
<> 150:02e0a0aed4ec 1642 #define _USB_DIEPMSK_XFERCOMPLMSK_MASK 0x1UL /**< Bit mask for USB_XFERCOMPLMSK */
<> 150:02e0a0aed4ec 1643 #define _USB_DIEPMSK_XFERCOMPLMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEPMSK */
<> 150:02e0a0aed4ec 1644 #define USB_DIEPMSK_XFERCOMPLMSK_DEFAULT (_USB_DIEPMSK_XFERCOMPLMSK_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEPMSK */
<> 150:02e0a0aed4ec 1645 #define USB_DIEPMSK_EPDISBLDMSK (0x1UL << 1) /**< Endpoint Disabled Interrupt Mask */
<> 150:02e0a0aed4ec 1646 #define _USB_DIEPMSK_EPDISBLDMSK_SHIFT 1 /**< Shift value for USB_EPDISBLDMSK */
<> 150:02e0a0aed4ec 1647 #define _USB_DIEPMSK_EPDISBLDMSK_MASK 0x2UL /**< Bit mask for USB_EPDISBLDMSK */
<> 150:02e0a0aed4ec 1648 #define _USB_DIEPMSK_EPDISBLDMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEPMSK */
<> 150:02e0a0aed4ec 1649 #define USB_DIEPMSK_EPDISBLDMSK_DEFAULT (_USB_DIEPMSK_EPDISBLDMSK_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_DIEPMSK */
<> 150:02e0a0aed4ec 1650 #define USB_DIEPMSK_AHBERRMSK (0x1UL << 2) /**< AHB Error Mask */
<> 150:02e0a0aed4ec 1651 #define _USB_DIEPMSK_AHBERRMSK_SHIFT 2 /**< Shift value for USB_AHBERRMSK */
<> 150:02e0a0aed4ec 1652 #define _USB_DIEPMSK_AHBERRMSK_MASK 0x4UL /**< Bit mask for USB_AHBERRMSK */
<> 150:02e0a0aed4ec 1653 #define _USB_DIEPMSK_AHBERRMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEPMSK */
<> 150:02e0a0aed4ec 1654 #define USB_DIEPMSK_AHBERRMSK_DEFAULT (_USB_DIEPMSK_AHBERRMSK_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_DIEPMSK */
<> 150:02e0a0aed4ec 1655 #define USB_DIEPMSK_TIMEOUTMSK (0x1UL << 3) /**< Timeout Condition Mask */
<> 150:02e0a0aed4ec 1656 #define _USB_DIEPMSK_TIMEOUTMSK_SHIFT 3 /**< Shift value for USB_TIMEOUTMSK */
<> 150:02e0a0aed4ec 1657 #define _USB_DIEPMSK_TIMEOUTMSK_MASK 0x8UL /**< Bit mask for USB_TIMEOUTMSK */
<> 150:02e0a0aed4ec 1658 #define _USB_DIEPMSK_TIMEOUTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEPMSK */
<> 150:02e0a0aed4ec 1659 #define USB_DIEPMSK_TIMEOUTMSK_DEFAULT (_USB_DIEPMSK_TIMEOUTMSK_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_DIEPMSK */
<> 150:02e0a0aed4ec 1660 #define USB_DIEPMSK_INTKNTXFEMPMSK (0x1UL << 4) /**< IN Token Received When TxFIFO Empty Mask */
<> 150:02e0a0aed4ec 1661 #define _USB_DIEPMSK_INTKNTXFEMPMSK_SHIFT 4 /**< Shift value for USB_INTKNTXFEMPMSK */
<> 150:02e0a0aed4ec 1662 #define _USB_DIEPMSK_INTKNTXFEMPMSK_MASK 0x10UL /**< Bit mask for USB_INTKNTXFEMPMSK */
<> 150:02e0a0aed4ec 1663 #define _USB_DIEPMSK_INTKNTXFEMPMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEPMSK */
<> 150:02e0a0aed4ec 1664 #define USB_DIEPMSK_INTKNTXFEMPMSK_DEFAULT (_USB_DIEPMSK_INTKNTXFEMPMSK_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_DIEPMSK */
<> 150:02e0a0aed4ec 1665 #define USB_DIEPMSK_INEPNAKEFFMSK (0x1UL << 6) /**< IN Endpoint NAK Effective Mask */
<> 150:02e0a0aed4ec 1666 #define _USB_DIEPMSK_INEPNAKEFFMSK_SHIFT 6 /**< Shift value for USB_INEPNAKEFFMSK */
<> 150:02e0a0aed4ec 1667 #define _USB_DIEPMSK_INEPNAKEFFMSK_MASK 0x40UL /**< Bit mask for USB_INEPNAKEFFMSK */
<> 150:02e0a0aed4ec 1668 #define _USB_DIEPMSK_INEPNAKEFFMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEPMSK */
<> 150:02e0a0aed4ec 1669 #define USB_DIEPMSK_INEPNAKEFFMSK_DEFAULT (_USB_DIEPMSK_INEPNAKEFFMSK_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_DIEPMSK */
<> 150:02e0a0aed4ec 1670 #define USB_DIEPMSK_TXFIFOUNDRNMSK (0x1UL << 8) /**< Fifo Underrun Mask */
<> 150:02e0a0aed4ec 1671 #define _USB_DIEPMSK_TXFIFOUNDRNMSK_SHIFT 8 /**< Shift value for USB_TXFIFOUNDRNMSK */
<> 150:02e0a0aed4ec 1672 #define _USB_DIEPMSK_TXFIFOUNDRNMSK_MASK 0x100UL /**< Bit mask for USB_TXFIFOUNDRNMSK */
<> 150:02e0a0aed4ec 1673 #define _USB_DIEPMSK_TXFIFOUNDRNMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEPMSK */
<> 150:02e0a0aed4ec 1674 #define USB_DIEPMSK_TXFIFOUNDRNMSK_DEFAULT (_USB_DIEPMSK_TXFIFOUNDRNMSK_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_DIEPMSK */
<> 150:02e0a0aed4ec 1675 #define USB_DIEPMSK_NAKMSK (0x1UL << 13) /**< NAK interrupt Mask */
<> 150:02e0a0aed4ec 1676 #define _USB_DIEPMSK_NAKMSK_SHIFT 13 /**< Shift value for USB_NAKMSK */
<> 150:02e0a0aed4ec 1677 #define _USB_DIEPMSK_NAKMSK_MASK 0x2000UL /**< Bit mask for USB_NAKMSK */
<> 150:02e0a0aed4ec 1678 #define _USB_DIEPMSK_NAKMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEPMSK */
<> 150:02e0a0aed4ec 1679 #define USB_DIEPMSK_NAKMSK_DEFAULT (_USB_DIEPMSK_NAKMSK_DEFAULT << 13) /**< Shifted mode DEFAULT for USB_DIEPMSK */
<> 150:02e0a0aed4ec 1680
<> 150:02e0a0aed4ec 1681 /* Bit fields for USB DOEPMSK */
<> 150:02e0a0aed4ec 1682 #define _USB_DOEPMSK_RESETVALUE 0x00000000UL /**< Default value for USB_DOEPMSK */
<> 150:02e0a0aed4ec 1683 #define _USB_DOEPMSK_MASK 0x0000315FUL /**< Mask for USB_DOEPMSK */
<> 150:02e0a0aed4ec 1684 #define USB_DOEPMSK_XFERCOMPLMSK (0x1UL << 0) /**< Transfer Completed Interrupt Mask */
<> 150:02e0a0aed4ec 1685 #define _USB_DOEPMSK_XFERCOMPLMSK_SHIFT 0 /**< Shift value for USB_XFERCOMPLMSK */
<> 150:02e0a0aed4ec 1686 #define _USB_DOEPMSK_XFERCOMPLMSK_MASK 0x1UL /**< Bit mask for USB_XFERCOMPLMSK */
<> 150:02e0a0aed4ec 1687 #define _USB_DOEPMSK_XFERCOMPLMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEPMSK */
<> 150:02e0a0aed4ec 1688 #define USB_DOEPMSK_XFERCOMPLMSK_DEFAULT (_USB_DOEPMSK_XFERCOMPLMSK_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DOEPMSK */
<> 150:02e0a0aed4ec 1689 #define USB_DOEPMSK_EPDISBLDMSK (0x1UL << 1) /**< Endpoint Disabled Interrupt Mask */
<> 150:02e0a0aed4ec 1690 #define _USB_DOEPMSK_EPDISBLDMSK_SHIFT 1 /**< Shift value for USB_EPDISBLDMSK */
<> 150:02e0a0aed4ec 1691 #define _USB_DOEPMSK_EPDISBLDMSK_MASK 0x2UL /**< Bit mask for USB_EPDISBLDMSK */
<> 150:02e0a0aed4ec 1692 #define _USB_DOEPMSK_EPDISBLDMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEPMSK */
<> 150:02e0a0aed4ec 1693 #define USB_DOEPMSK_EPDISBLDMSK_DEFAULT (_USB_DOEPMSK_EPDISBLDMSK_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_DOEPMSK */
<> 150:02e0a0aed4ec 1694 #define USB_DOEPMSK_AHBERRMSK (0x1UL << 2) /**< AHB Error */
<> 150:02e0a0aed4ec 1695 #define _USB_DOEPMSK_AHBERRMSK_SHIFT 2 /**< Shift value for USB_AHBERRMSK */
<> 150:02e0a0aed4ec 1696 #define _USB_DOEPMSK_AHBERRMSK_MASK 0x4UL /**< Bit mask for USB_AHBERRMSK */
<> 150:02e0a0aed4ec 1697 #define _USB_DOEPMSK_AHBERRMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEPMSK */
<> 150:02e0a0aed4ec 1698 #define USB_DOEPMSK_AHBERRMSK_DEFAULT (_USB_DOEPMSK_AHBERRMSK_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_DOEPMSK */
<> 150:02e0a0aed4ec 1699 #define USB_DOEPMSK_SETUPMSK (0x1UL << 3) /**< SETUP Phase Done Mask */
<> 150:02e0a0aed4ec 1700 #define _USB_DOEPMSK_SETUPMSK_SHIFT 3 /**< Shift value for USB_SETUPMSK */
<> 150:02e0a0aed4ec 1701 #define _USB_DOEPMSK_SETUPMSK_MASK 0x8UL /**< Bit mask for USB_SETUPMSK */
<> 150:02e0a0aed4ec 1702 #define _USB_DOEPMSK_SETUPMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEPMSK */
<> 150:02e0a0aed4ec 1703 #define USB_DOEPMSK_SETUPMSK_DEFAULT (_USB_DOEPMSK_SETUPMSK_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_DOEPMSK */
<> 150:02e0a0aed4ec 1704 #define USB_DOEPMSK_OUTTKNEPDISMSK (0x1UL << 4) /**< OUT Token Received when Endpoint Disabled Mask */
<> 150:02e0a0aed4ec 1705 #define _USB_DOEPMSK_OUTTKNEPDISMSK_SHIFT 4 /**< Shift value for USB_OUTTKNEPDISMSK */
<> 150:02e0a0aed4ec 1706 #define _USB_DOEPMSK_OUTTKNEPDISMSK_MASK 0x10UL /**< Bit mask for USB_OUTTKNEPDISMSK */
<> 150:02e0a0aed4ec 1707 #define _USB_DOEPMSK_OUTTKNEPDISMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEPMSK */
<> 150:02e0a0aed4ec 1708 #define USB_DOEPMSK_OUTTKNEPDISMSK_DEFAULT (_USB_DOEPMSK_OUTTKNEPDISMSK_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_DOEPMSK */
<> 150:02e0a0aed4ec 1709 #define USB_DOEPMSK_BACK2BACKSETUP (0x1UL << 6) /**< Back-to-Back SETUP Packets Received Mask */
<> 150:02e0a0aed4ec 1710 #define _USB_DOEPMSK_BACK2BACKSETUP_SHIFT 6 /**< Shift value for USB_BACK2BACKSETUP */
<> 150:02e0a0aed4ec 1711 #define _USB_DOEPMSK_BACK2BACKSETUP_MASK 0x40UL /**< Bit mask for USB_BACK2BACKSETUP */
<> 150:02e0a0aed4ec 1712 #define _USB_DOEPMSK_BACK2BACKSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEPMSK */
<> 150:02e0a0aed4ec 1713 #define USB_DOEPMSK_BACK2BACKSETUP_DEFAULT (_USB_DOEPMSK_BACK2BACKSETUP_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_DOEPMSK */
<> 150:02e0a0aed4ec 1714 #define USB_DOEPMSK_OUTPKTERRMSK (0x1UL << 8) /**< OUT Packet Error Mask */
<> 150:02e0a0aed4ec 1715 #define _USB_DOEPMSK_OUTPKTERRMSK_SHIFT 8 /**< Shift value for USB_OUTPKTERRMSK */
<> 150:02e0a0aed4ec 1716 #define _USB_DOEPMSK_OUTPKTERRMSK_MASK 0x100UL /**< Bit mask for USB_OUTPKTERRMSK */
<> 150:02e0a0aed4ec 1717 #define _USB_DOEPMSK_OUTPKTERRMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEPMSK */
<> 150:02e0a0aed4ec 1718 #define USB_DOEPMSK_OUTPKTERRMSK_DEFAULT (_USB_DOEPMSK_OUTPKTERRMSK_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_DOEPMSK */
<> 150:02e0a0aed4ec 1719 #define USB_DOEPMSK_BBLEERRMSK (0x1UL << 12) /**< Babble Error interrupt Mask */
<> 150:02e0a0aed4ec 1720 #define _USB_DOEPMSK_BBLEERRMSK_SHIFT 12 /**< Shift value for USB_BBLEERRMSK */
<> 150:02e0a0aed4ec 1721 #define _USB_DOEPMSK_BBLEERRMSK_MASK 0x1000UL /**< Bit mask for USB_BBLEERRMSK */
<> 150:02e0a0aed4ec 1722 #define _USB_DOEPMSK_BBLEERRMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEPMSK */
<> 150:02e0a0aed4ec 1723 #define USB_DOEPMSK_BBLEERRMSK_DEFAULT (_USB_DOEPMSK_BBLEERRMSK_DEFAULT << 12) /**< Shifted mode DEFAULT for USB_DOEPMSK */
<> 150:02e0a0aed4ec 1724 #define USB_DOEPMSK_NAKMSK (0x1UL << 13) /**< NAK interrupt Mask */
<> 150:02e0a0aed4ec 1725 #define _USB_DOEPMSK_NAKMSK_SHIFT 13 /**< Shift value for USB_NAKMSK */
<> 150:02e0a0aed4ec 1726 #define _USB_DOEPMSK_NAKMSK_MASK 0x2000UL /**< Bit mask for USB_NAKMSK */
<> 150:02e0a0aed4ec 1727 #define _USB_DOEPMSK_NAKMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEPMSK */
<> 150:02e0a0aed4ec 1728 #define USB_DOEPMSK_NAKMSK_DEFAULT (_USB_DOEPMSK_NAKMSK_DEFAULT << 13) /**< Shifted mode DEFAULT for USB_DOEPMSK */
<> 150:02e0a0aed4ec 1729
<> 150:02e0a0aed4ec 1730 /* Bit fields for USB DAINT */
<> 150:02e0a0aed4ec 1731 #define _USB_DAINT_RESETVALUE 0x00000000UL /**< Default value for USB_DAINT */
<> 150:02e0a0aed4ec 1732 #define _USB_DAINT_MASK 0x007F007FUL /**< Mask for USB_DAINT */
<> 150:02e0a0aed4ec 1733 #define USB_DAINT_INEPINT0 (0x1UL << 0) /**< IN Endpoint 0 Interrupt Bit */
<> 150:02e0a0aed4ec 1734 #define _USB_DAINT_INEPINT0_SHIFT 0 /**< Shift value for USB_INEPINT0 */
<> 150:02e0a0aed4ec 1735 #define _USB_DAINT_INEPINT0_MASK 0x1UL /**< Bit mask for USB_INEPINT0 */
<> 150:02e0a0aed4ec 1736 #define _USB_DAINT_INEPINT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */
<> 150:02e0a0aed4ec 1737 #define USB_DAINT_INEPINT0_DEFAULT (_USB_DAINT_INEPINT0_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DAINT */
<> 150:02e0a0aed4ec 1738 #define USB_DAINT_INEPINT1 (0x1UL << 1) /**< IN Endpoint 1 Interrupt Bit */
<> 150:02e0a0aed4ec 1739 #define _USB_DAINT_INEPINT1_SHIFT 1 /**< Shift value for USB_INEPINT1 */
<> 150:02e0a0aed4ec 1740 #define _USB_DAINT_INEPINT1_MASK 0x2UL /**< Bit mask for USB_INEPINT1 */
<> 150:02e0a0aed4ec 1741 #define _USB_DAINT_INEPINT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */
<> 150:02e0a0aed4ec 1742 #define USB_DAINT_INEPINT1_DEFAULT (_USB_DAINT_INEPINT1_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_DAINT */
<> 150:02e0a0aed4ec 1743 #define USB_DAINT_INEPINT2 (0x1UL << 2) /**< IN Endpoint 2 Interrupt Bit */
<> 150:02e0a0aed4ec 1744 #define _USB_DAINT_INEPINT2_SHIFT 2 /**< Shift value for USB_INEPINT2 */
<> 150:02e0a0aed4ec 1745 #define _USB_DAINT_INEPINT2_MASK 0x4UL /**< Bit mask for USB_INEPINT2 */
<> 150:02e0a0aed4ec 1746 #define _USB_DAINT_INEPINT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */
<> 150:02e0a0aed4ec 1747 #define USB_DAINT_INEPINT2_DEFAULT (_USB_DAINT_INEPINT2_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_DAINT */
<> 150:02e0a0aed4ec 1748 #define USB_DAINT_INEPINT3 (0x1UL << 3) /**< IN Endpoint 3 Interrupt Bit */
<> 150:02e0a0aed4ec 1749 #define _USB_DAINT_INEPINT3_SHIFT 3 /**< Shift value for USB_INEPINT3 */
<> 150:02e0a0aed4ec 1750 #define _USB_DAINT_INEPINT3_MASK 0x8UL /**< Bit mask for USB_INEPINT3 */
<> 150:02e0a0aed4ec 1751 #define _USB_DAINT_INEPINT3_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */
<> 150:02e0a0aed4ec 1752 #define USB_DAINT_INEPINT3_DEFAULT (_USB_DAINT_INEPINT3_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_DAINT */
<> 150:02e0a0aed4ec 1753 #define USB_DAINT_INEPINT4 (0x1UL << 4) /**< IN Endpoint 4 Interrupt Bit */
<> 150:02e0a0aed4ec 1754 #define _USB_DAINT_INEPINT4_SHIFT 4 /**< Shift value for USB_INEPINT4 */
<> 150:02e0a0aed4ec 1755 #define _USB_DAINT_INEPINT4_MASK 0x10UL /**< Bit mask for USB_INEPINT4 */
<> 150:02e0a0aed4ec 1756 #define _USB_DAINT_INEPINT4_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */
<> 150:02e0a0aed4ec 1757 #define USB_DAINT_INEPINT4_DEFAULT (_USB_DAINT_INEPINT4_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_DAINT */
<> 150:02e0a0aed4ec 1758 #define USB_DAINT_INEPINT5 (0x1UL << 5) /**< IN Endpoint 5 Interrupt Bit */
<> 150:02e0a0aed4ec 1759 #define _USB_DAINT_INEPINT5_SHIFT 5 /**< Shift value for USB_INEPINT5 */
<> 150:02e0a0aed4ec 1760 #define _USB_DAINT_INEPINT5_MASK 0x20UL /**< Bit mask for USB_INEPINT5 */
<> 150:02e0a0aed4ec 1761 #define _USB_DAINT_INEPINT5_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */
<> 150:02e0a0aed4ec 1762 #define USB_DAINT_INEPINT5_DEFAULT (_USB_DAINT_INEPINT5_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_DAINT */
<> 150:02e0a0aed4ec 1763 #define USB_DAINT_INEPINT6 (0x1UL << 6) /**< IN Endpoint 6 Interrupt Bit */
<> 150:02e0a0aed4ec 1764 #define _USB_DAINT_INEPINT6_SHIFT 6 /**< Shift value for USB_INEPINT6 */
<> 150:02e0a0aed4ec 1765 #define _USB_DAINT_INEPINT6_MASK 0x40UL /**< Bit mask for USB_INEPINT6 */
<> 150:02e0a0aed4ec 1766 #define _USB_DAINT_INEPINT6_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */
<> 150:02e0a0aed4ec 1767 #define USB_DAINT_INEPINT6_DEFAULT (_USB_DAINT_INEPINT6_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_DAINT */
<> 150:02e0a0aed4ec 1768 #define USB_DAINT_OUTEPINT0 (0x1UL << 16) /**< OUT Endpoint 0 Interrupt Bit */
<> 150:02e0a0aed4ec 1769 #define _USB_DAINT_OUTEPINT0_SHIFT 16 /**< Shift value for USB_OUTEPINT0 */
<> 150:02e0a0aed4ec 1770 #define _USB_DAINT_OUTEPINT0_MASK 0x10000UL /**< Bit mask for USB_OUTEPINT0 */
<> 150:02e0a0aed4ec 1771 #define _USB_DAINT_OUTEPINT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */
<> 150:02e0a0aed4ec 1772 #define USB_DAINT_OUTEPINT0_DEFAULT (_USB_DAINT_OUTEPINT0_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_DAINT */
<> 150:02e0a0aed4ec 1773 #define USB_DAINT_OUTEPINT1 (0x1UL << 17) /**< OUT Endpoint 1 Interrupt Bit */
<> 150:02e0a0aed4ec 1774 #define _USB_DAINT_OUTEPINT1_SHIFT 17 /**< Shift value for USB_OUTEPINT1 */
<> 150:02e0a0aed4ec 1775 #define _USB_DAINT_OUTEPINT1_MASK 0x20000UL /**< Bit mask for USB_OUTEPINT1 */
<> 150:02e0a0aed4ec 1776 #define _USB_DAINT_OUTEPINT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */
<> 150:02e0a0aed4ec 1777 #define USB_DAINT_OUTEPINT1_DEFAULT (_USB_DAINT_OUTEPINT1_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_DAINT */
<> 150:02e0a0aed4ec 1778 #define USB_DAINT_OUTEPINT2 (0x1UL << 18) /**< OUT Endpoint 2 Interrupt Bit */
<> 150:02e0a0aed4ec 1779 #define _USB_DAINT_OUTEPINT2_SHIFT 18 /**< Shift value for USB_OUTEPINT2 */
<> 150:02e0a0aed4ec 1780 #define _USB_DAINT_OUTEPINT2_MASK 0x40000UL /**< Bit mask for USB_OUTEPINT2 */
<> 150:02e0a0aed4ec 1781 #define _USB_DAINT_OUTEPINT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */
<> 150:02e0a0aed4ec 1782 #define USB_DAINT_OUTEPINT2_DEFAULT (_USB_DAINT_OUTEPINT2_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_DAINT */
<> 150:02e0a0aed4ec 1783 #define USB_DAINT_OUTEPINT3 (0x1UL << 19) /**< OUT Endpoint 3 Interrupt Bit */
<> 150:02e0a0aed4ec 1784 #define _USB_DAINT_OUTEPINT3_SHIFT 19 /**< Shift value for USB_OUTEPINT3 */
<> 150:02e0a0aed4ec 1785 #define _USB_DAINT_OUTEPINT3_MASK 0x80000UL /**< Bit mask for USB_OUTEPINT3 */
<> 150:02e0a0aed4ec 1786 #define _USB_DAINT_OUTEPINT3_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */
<> 150:02e0a0aed4ec 1787 #define USB_DAINT_OUTEPINT3_DEFAULT (_USB_DAINT_OUTEPINT3_DEFAULT << 19) /**< Shifted mode DEFAULT for USB_DAINT */
<> 150:02e0a0aed4ec 1788 #define USB_DAINT_OUTEPINT4 (0x1UL << 20) /**< OUT Endpoint 4 Interrupt Bit */
<> 150:02e0a0aed4ec 1789 #define _USB_DAINT_OUTEPINT4_SHIFT 20 /**< Shift value for USB_OUTEPINT4 */
<> 150:02e0a0aed4ec 1790 #define _USB_DAINT_OUTEPINT4_MASK 0x100000UL /**< Bit mask for USB_OUTEPINT4 */
<> 150:02e0a0aed4ec 1791 #define _USB_DAINT_OUTEPINT4_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */
<> 150:02e0a0aed4ec 1792 #define USB_DAINT_OUTEPINT4_DEFAULT (_USB_DAINT_OUTEPINT4_DEFAULT << 20) /**< Shifted mode DEFAULT for USB_DAINT */
<> 150:02e0a0aed4ec 1793 #define USB_DAINT_OUTEPINT5 (0x1UL << 21) /**< OUT Endpoint 5 Interrupt Bit */
<> 150:02e0a0aed4ec 1794 #define _USB_DAINT_OUTEPINT5_SHIFT 21 /**< Shift value for USB_OUTEPINT5 */
<> 150:02e0a0aed4ec 1795 #define _USB_DAINT_OUTEPINT5_MASK 0x200000UL /**< Bit mask for USB_OUTEPINT5 */
<> 150:02e0a0aed4ec 1796 #define _USB_DAINT_OUTEPINT5_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */
<> 150:02e0a0aed4ec 1797 #define USB_DAINT_OUTEPINT5_DEFAULT (_USB_DAINT_OUTEPINT5_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_DAINT */
<> 150:02e0a0aed4ec 1798 #define USB_DAINT_OUTEPINT6 (0x1UL << 22) /**< OUT Endpoint 6 Interrupt Bit */
<> 150:02e0a0aed4ec 1799 #define _USB_DAINT_OUTEPINT6_SHIFT 22 /**< Shift value for USB_OUTEPINT6 */
<> 150:02e0a0aed4ec 1800 #define _USB_DAINT_OUTEPINT6_MASK 0x400000UL /**< Bit mask for USB_OUTEPINT6 */
<> 150:02e0a0aed4ec 1801 #define _USB_DAINT_OUTEPINT6_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */
<> 150:02e0a0aed4ec 1802 #define USB_DAINT_OUTEPINT6_DEFAULT (_USB_DAINT_OUTEPINT6_DEFAULT << 22) /**< Shifted mode DEFAULT for USB_DAINT */
<> 150:02e0a0aed4ec 1803
<> 150:02e0a0aed4ec 1804 /* Bit fields for USB DAINTMSK */
<> 150:02e0a0aed4ec 1805 #define _USB_DAINTMSK_RESETVALUE 0x00000000UL /**< Default value for USB_DAINTMSK */
<> 150:02e0a0aed4ec 1806 #define _USB_DAINTMSK_MASK 0x007F007FUL /**< Mask for USB_DAINTMSK */
<> 150:02e0a0aed4ec 1807 #define USB_DAINTMSK_INEPMSK0 (0x1UL << 0) /**< IN Endpoint 0 Interrupt mask Bit */
<> 150:02e0a0aed4ec 1808 #define _USB_DAINTMSK_INEPMSK0_SHIFT 0 /**< Shift value for USB_INEPMSK0 */
<> 150:02e0a0aed4ec 1809 #define _USB_DAINTMSK_INEPMSK0_MASK 0x1UL /**< Bit mask for USB_INEPMSK0 */
<> 150:02e0a0aed4ec 1810 #define _USB_DAINTMSK_INEPMSK0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */
<> 150:02e0a0aed4ec 1811 #define USB_DAINTMSK_INEPMSK0_DEFAULT (_USB_DAINTMSK_INEPMSK0_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DAINTMSK */
<> 150:02e0a0aed4ec 1812 #define USB_DAINTMSK_INEPMSK1 (0x1UL << 1) /**< IN Endpoint 1 Interrupt mask Bit */
<> 150:02e0a0aed4ec 1813 #define _USB_DAINTMSK_INEPMSK1_SHIFT 1 /**< Shift value for USB_INEPMSK1 */
<> 150:02e0a0aed4ec 1814 #define _USB_DAINTMSK_INEPMSK1_MASK 0x2UL /**< Bit mask for USB_INEPMSK1 */
<> 150:02e0a0aed4ec 1815 #define _USB_DAINTMSK_INEPMSK1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */
<> 150:02e0a0aed4ec 1816 #define USB_DAINTMSK_INEPMSK1_DEFAULT (_USB_DAINTMSK_INEPMSK1_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_DAINTMSK */
<> 150:02e0a0aed4ec 1817 #define USB_DAINTMSK_INEPMSK2 (0x1UL << 2) /**< IN Endpoint 2 Interrupt mask Bit */
<> 150:02e0a0aed4ec 1818 #define _USB_DAINTMSK_INEPMSK2_SHIFT 2 /**< Shift value for USB_INEPMSK2 */
<> 150:02e0a0aed4ec 1819 #define _USB_DAINTMSK_INEPMSK2_MASK 0x4UL /**< Bit mask for USB_INEPMSK2 */
<> 150:02e0a0aed4ec 1820 #define _USB_DAINTMSK_INEPMSK2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */
<> 150:02e0a0aed4ec 1821 #define USB_DAINTMSK_INEPMSK2_DEFAULT (_USB_DAINTMSK_INEPMSK2_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_DAINTMSK */
<> 150:02e0a0aed4ec 1822 #define USB_DAINTMSK_INEPMSK3 (0x1UL << 3) /**< IN Endpoint 3 Interrupt mask Bit */
<> 150:02e0a0aed4ec 1823 #define _USB_DAINTMSK_INEPMSK3_SHIFT 3 /**< Shift value for USB_INEPMSK3 */
<> 150:02e0a0aed4ec 1824 #define _USB_DAINTMSK_INEPMSK3_MASK 0x8UL /**< Bit mask for USB_INEPMSK3 */
<> 150:02e0a0aed4ec 1825 #define _USB_DAINTMSK_INEPMSK3_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */
<> 150:02e0a0aed4ec 1826 #define USB_DAINTMSK_INEPMSK3_DEFAULT (_USB_DAINTMSK_INEPMSK3_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_DAINTMSK */
<> 150:02e0a0aed4ec 1827 #define USB_DAINTMSK_INEPMSK4 (0x1UL << 4) /**< IN Endpoint 4 Interrupt mask Bit */
<> 150:02e0a0aed4ec 1828 #define _USB_DAINTMSK_INEPMSK4_SHIFT 4 /**< Shift value for USB_INEPMSK4 */
<> 150:02e0a0aed4ec 1829 #define _USB_DAINTMSK_INEPMSK4_MASK 0x10UL /**< Bit mask for USB_INEPMSK4 */
<> 150:02e0a0aed4ec 1830 #define _USB_DAINTMSK_INEPMSK4_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */
<> 150:02e0a0aed4ec 1831 #define USB_DAINTMSK_INEPMSK4_DEFAULT (_USB_DAINTMSK_INEPMSK4_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_DAINTMSK */
<> 150:02e0a0aed4ec 1832 #define USB_DAINTMSK_INEPMSK5 (0x1UL << 5) /**< IN Endpoint 5 Interrupt mask Bit */
<> 150:02e0a0aed4ec 1833 #define _USB_DAINTMSK_INEPMSK5_SHIFT 5 /**< Shift value for USB_INEPMSK5 */
<> 150:02e0a0aed4ec 1834 #define _USB_DAINTMSK_INEPMSK5_MASK 0x20UL /**< Bit mask for USB_INEPMSK5 */
<> 150:02e0a0aed4ec 1835 #define _USB_DAINTMSK_INEPMSK5_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */
<> 150:02e0a0aed4ec 1836 #define USB_DAINTMSK_INEPMSK5_DEFAULT (_USB_DAINTMSK_INEPMSK5_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_DAINTMSK */
<> 150:02e0a0aed4ec 1837 #define USB_DAINTMSK_INEPMSK6 (0x1UL << 6) /**< IN Endpoint 6 Interrupt mask Bit */
<> 150:02e0a0aed4ec 1838 #define _USB_DAINTMSK_INEPMSK6_SHIFT 6 /**< Shift value for USB_INEPMSK6 */
<> 150:02e0a0aed4ec 1839 #define _USB_DAINTMSK_INEPMSK6_MASK 0x40UL /**< Bit mask for USB_INEPMSK6 */
<> 150:02e0a0aed4ec 1840 #define _USB_DAINTMSK_INEPMSK6_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */
<> 150:02e0a0aed4ec 1841 #define USB_DAINTMSK_INEPMSK6_DEFAULT (_USB_DAINTMSK_INEPMSK6_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_DAINTMSK */
<> 150:02e0a0aed4ec 1842 #define USB_DAINTMSK_OUTEPMSK0 (0x1UL << 16) /**< OUT Endpoint 0 Interrupt mask Bit */
<> 150:02e0a0aed4ec 1843 #define _USB_DAINTMSK_OUTEPMSK0_SHIFT 16 /**< Shift value for USB_OUTEPMSK0 */
<> 150:02e0a0aed4ec 1844 #define _USB_DAINTMSK_OUTEPMSK0_MASK 0x10000UL /**< Bit mask for USB_OUTEPMSK0 */
<> 150:02e0a0aed4ec 1845 #define _USB_DAINTMSK_OUTEPMSK0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */
<> 150:02e0a0aed4ec 1846 #define USB_DAINTMSK_OUTEPMSK0_DEFAULT (_USB_DAINTMSK_OUTEPMSK0_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_DAINTMSK */
<> 150:02e0a0aed4ec 1847 #define USB_DAINTMSK_OUTEPMSK1 (0x1UL << 17) /**< OUT Endpoint 1 Interrupt mask Bit */
<> 150:02e0a0aed4ec 1848 #define _USB_DAINTMSK_OUTEPMSK1_SHIFT 17 /**< Shift value for USB_OUTEPMSK1 */
<> 150:02e0a0aed4ec 1849 #define _USB_DAINTMSK_OUTEPMSK1_MASK 0x20000UL /**< Bit mask for USB_OUTEPMSK1 */
<> 150:02e0a0aed4ec 1850 #define _USB_DAINTMSK_OUTEPMSK1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */
<> 150:02e0a0aed4ec 1851 #define USB_DAINTMSK_OUTEPMSK1_DEFAULT (_USB_DAINTMSK_OUTEPMSK1_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_DAINTMSK */
<> 150:02e0a0aed4ec 1852 #define USB_DAINTMSK_OUTEPMSK2 (0x1UL << 18) /**< OUT Endpoint 2 Interrupt mask Bit */
<> 150:02e0a0aed4ec 1853 #define _USB_DAINTMSK_OUTEPMSK2_SHIFT 18 /**< Shift value for USB_OUTEPMSK2 */
<> 150:02e0a0aed4ec 1854 #define _USB_DAINTMSK_OUTEPMSK2_MASK 0x40000UL /**< Bit mask for USB_OUTEPMSK2 */
<> 150:02e0a0aed4ec 1855 #define _USB_DAINTMSK_OUTEPMSK2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */
<> 150:02e0a0aed4ec 1856 #define USB_DAINTMSK_OUTEPMSK2_DEFAULT (_USB_DAINTMSK_OUTEPMSK2_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_DAINTMSK */
<> 150:02e0a0aed4ec 1857 #define USB_DAINTMSK_OUTEPMSK3 (0x1UL << 19) /**< OUT Endpoint 3 Interrupt mask Bit */
<> 150:02e0a0aed4ec 1858 #define _USB_DAINTMSK_OUTEPMSK3_SHIFT 19 /**< Shift value for USB_OUTEPMSK3 */
<> 150:02e0a0aed4ec 1859 #define _USB_DAINTMSK_OUTEPMSK3_MASK 0x80000UL /**< Bit mask for USB_OUTEPMSK3 */
<> 150:02e0a0aed4ec 1860 #define _USB_DAINTMSK_OUTEPMSK3_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */
<> 150:02e0a0aed4ec 1861 #define USB_DAINTMSK_OUTEPMSK3_DEFAULT (_USB_DAINTMSK_OUTEPMSK3_DEFAULT << 19) /**< Shifted mode DEFAULT for USB_DAINTMSK */
<> 150:02e0a0aed4ec 1862 #define USB_DAINTMSK_OUTEPMSK4 (0x1UL << 20) /**< OUT Endpoint 4 Interrupt mask Bit */
<> 150:02e0a0aed4ec 1863 #define _USB_DAINTMSK_OUTEPMSK4_SHIFT 20 /**< Shift value for USB_OUTEPMSK4 */
<> 150:02e0a0aed4ec 1864 #define _USB_DAINTMSK_OUTEPMSK4_MASK 0x100000UL /**< Bit mask for USB_OUTEPMSK4 */
<> 150:02e0a0aed4ec 1865 #define _USB_DAINTMSK_OUTEPMSK4_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */
<> 150:02e0a0aed4ec 1866 #define USB_DAINTMSK_OUTEPMSK4_DEFAULT (_USB_DAINTMSK_OUTEPMSK4_DEFAULT << 20) /**< Shifted mode DEFAULT for USB_DAINTMSK */
<> 150:02e0a0aed4ec 1867 #define USB_DAINTMSK_OUTEPMSK5 (0x1UL << 21) /**< OUT Endpoint 5 Interrupt mask Bit */
<> 150:02e0a0aed4ec 1868 #define _USB_DAINTMSK_OUTEPMSK5_SHIFT 21 /**< Shift value for USB_OUTEPMSK5 */
<> 150:02e0a0aed4ec 1869 #define _USB_DAINTMSK_OUTEPMSK5_MASK 0x200000UL /**< Bit mask for USB_OUTEPMSK5 */
<> 150:02e0a0aed4ec 1870 #define _USB_DAINTMSK_OUTEPMSK5_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */
<> 150:02e0a0aed4ec 1871 #define USB_DAINTMSK_OUTEPMSK5_DEFAULT (_USB_DAINTMSK_OUTEPMSK5_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_DAINTMSK */
<> 150:02e0a0aed4ec 1872 #define USB_DAINTMSK_OUTEPMSK6 (0x1UL << 22) /**< OUT Endpoint 6 Interrupt mask Bit */
<> 150:02e0a0aed4ec 1873 #define _USB_DAINTMSK_OUTEPMSK6_SHIFT 22 /**< Shift value for USB_OUTEPMSK6 */
<> 150:02e0a0aed4ec 1874 #define _USB_DAINTMSK_OUTEPMSK6_MASK 0x400000UL /**< Bit mask for USB_OUTEPMSK6 */
<> 150:02e0a0aed4ec 1875 #define _USB_DAINTMSK_OUTEPMSK6_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */
<> 150:02e0a0aed4ec 1876 #define USB_DAINTMSK_OUTEPMSK6_DEFAULT (_USB_DAINTMSK_OUTEPMSK6_DEFAULT << 22) /**< Shifted mode DEFAULT for USB_DAINTMSK */
<> 150:02e0a0aed4ec 1877
<> 150:02e0a0aed4ec 1878 /* Bit fields for USB DVBUSDIS */
<> 150:02e0a0aed4ec 1879 #define _USB_DVBUSDIS_RESETVALUE 0x000017D7UL /**< Default value for USB_DVBUSDIS */
<> 150:02e0a0aed4ec 1880 #define _USB_DVBUSDIS_MASK 0x0000FFFFUL /**< Mask for USB_DVBUSDIS */
<> 150:02e0a0aed4ec 1881 #define _USB_DVBUSDIS_DVBUSDIS_SHIFT 0 /**< Shift value for USB_DVBUSDIS */
<> 150:02e0a0aed4ec 1882 #define _USB_DVBUSDIS_DVBUSDIS_MASK 0xFFFFUL /**< Bit mask for USB_DVBUSDIS */
<> 150:02e0a0aed4ec 1883 #define _USB_DVBUSDIS_DVBUSDIS_DEFAULT 0x000017D7UL /**< Mode DEFAULT for USB_DVBUSDIS */
<> 150:02e0a0aed4ec 1884 #define USB_DVBUSDIS_DVBUSDIS_DEFAULT (_USB_DVBUSDIS_DVBUSDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DVBUSDIS */
<> 150:02e0a0aed4ec 1885
<> 150:02e0a0aed4ec 1886 /* Bit fields for USB DVBUSPULSE */
<> 150:02e0a0aed4ec 1887 #define _USB_DVBUSPULSE_RESETVALUE 0x000005B8UL /**< Default value for USB_DVBUSPULSE */
<> 150:02e0a0aed4ec 1888 #define _USB_DVBUSPULSE_MASK 0x00000FFFUL /**< Mask for USB_DVBUSPULSE */
<> 150:02e0a0aed4ec 1889 #define _USB_DVBUSPULSE_DVBUSPULSE_SHIFT 0 /**< Shift value for USB_DVBUSPULSE */
<> 150:02e0a0aed4ec 1890 #define _USB_DVBUSPULSE_DVBUSPULSE_MASK 0xFFFUL /**< Bit mask for USB_DVBUSPULSE */
<> 150:02e0a0aed4ec 1891 #define _USB_DVBUSPULSE_DVBUSPULSE_DEFAULT 0x000005B8UL /**< Mode DEFAULT for USB_DVBUSPULSE */
<> 150:02e0a0aed4ec 1892 #define USB_DVBUSPULSE_DVBUSPULSE_DEFAULT (_USB_DVBUSPULSE_DVBUSPULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DVBUSPULSE */
<> 150:02e0a0aed4ec 1893
<> 150:02e0a0aed4ec 1894 /* Bit fields for USB DIEPEMPMSK */
<> 150:02e0a0aed4ec 1895 #define _USB_DIEPEMPMSK_RESETVALUE 0x00000000UL /**< Default value for USB_DIEPEMPMSK */
<> 150:02e0a0aed4ec 1896 #define _USB_DIEPEMPMSK_MASK 0x0000FFFFUL /**< Mask for USB_DIEPEMPMSK */
<> 150:02e0a0aed4ec 1897 #define _USB_DIEPEMPMSK_DIEPEMPMSK_SHIFT 0 /**< Shift value for USB_DIEPEMPMSK */
<> 150:02e0a0aed4ec 1898 #define _USB_DIEPEMPMSK_DIEPEMPMSK_MASK 0xFFFFUL /**< Bit mask for USB_DIEPEMPMSK */
<> 150:02e0a0aed4ec 1899 #define _USB_DIEPEMPMSK_DIEPEMPMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEPEMPMSK */
<> 150:02e0a0aed4ec 1900 #define USB_DIEPEMPMSK_DIEPEMPMSK_DEFAULT (_USB_DIEPEMPMSK_DIEPEMPMSK_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEPEMPMSK */
<> 150:02e0a0aed4ec 1901
<> 150:02e0a0aed4ec 1902 /* Bit fields for USB DIEP0CTL */
<> 150:02e0a0aed4ec 1903 #define _USB_DIEP0CTL_RESETVALUE 0x00008000UL /**< Default value for USB_DIEP0CTL */
<> 150:02e0a0aed4ec 1904 #define _USB_DIEP0CTL_MASK 0xCFEE8003UL /**< Mask for USB_DIEP0CTL */
<> 150:02e0a0aed4ec 1905 #define _USB_DIEP0CTL_MPS_SHIFT 0 /**< Shift value for USB_MPS */
<> 150:02e0a0aed4ec 1906 #define _USB_DIEP0CTL_MPS_MASK 0x3UL /**< Bit mask for USB_MPS */
<> 150:02e0a0aed4ec 1907 #define _USB_DIEP0CTL_MPS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0CTL */
<> 150:02e0a0aed4ec 1908 #define _USB_DIEP0CTL_MPS_64B 0x00000000UL /**< Mode 64B for USB_DIEP0CTL */
<> 150:02e0a0aed4ec 1909 #define _USB_DIEP0CTL_MPS_32B 0x00000001UL /**< Mode 32B for USB_DIEP0CTL */
<> 150:02e0a0aed4ec 1910 #define _USB_DIEP0CTL_MPS_16B 0x00000002UL /**< Mode 16B for USB_DIEP0CTL */
<> 150:02e0a0aed4ec 1911 #define _USB_DIEP0CTL_MPS_8B 0x00000003UL /**< Mode 8B for USB_DIEP0CTL */
<> 150:02e0a0aed4ec 1912 #define USB_DIEP0CTL_MPS_DEFAULT (_USB_DIEP0CTL_MPS_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEP0CTL */
<> 150:02e0a0aed4ec 1913 #define USB_DIEP0CTL_MPS_64B (_USB_DIEP0CTL_MPS_64B << 0) /**< Shifted mode 64B for USB_DIEP0CTL */
<> 150:02e0a0aed4ec 1914 #define USB_DIEP0CTL_MPS_32B (_USB_DIEP0CTL_MPS_32B << 0) /**< Shifted mode 32B for USB_DIEP0CTL */
<> 150:02e0a0aed4ec 1915 #define USB_DIEP0CTL_MPS_16B (_USB_DIEP0CTL_MPS_16B << 0) /**< Shifted mode 16B for USB_DIEP0CTL */
<> 150:02e0a0aed4ec 1916 #define USB_DIEP0CTL_MPS_8B (_USB_DIEP0CTL_MPS_8B << 0) /**< Shifted mode 8B for USB_DIEP0CTL */
<> 150:02e0a0aed4ec 1917 #define USB_DIEP0CTL_USBACTEP (0x1UL << 15) /**< USB Active Endpoint */
<> 150:02e0a0aed4ec 1918 #define _USB_DIEP0CTL_USBACTEP_SHIFT 15 /**< Shift value for USB_USBACTEP */
<> 150:02e0a0aed4ec 1919 #define _USB_DIEP0CTL_USBACTEP_MASK 0x8000UL /**< Bit mask for USB_USBACTEP */
<> 150:02e0a0aed4ec 1920 #define _USB_DIEP0CTL_USBACTEP_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_DIEP0CTL */
<> 150:02e0a0aed4ec 1921 #define USB_DIEP0CTL_USBACTEP_DEFAULT (_USB_DIEP0CTL_USBACTEP_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_DIEP0CTL */
<> 150:02e0a0aed4ec 1922 #define USB_DIEP0CTL_NAKSTS (0x1UL << 17) /**< NAK Status */
<> 150:02e0a0aed4ec 1923 #define _USB_DIEP0CTL_NAKSTS_SHIFT 17 /**< Shift value for USB_NAKSTS */
<> 150:02e0a0aed4ec 1924 #define _USB_DIEP0CTL_NAKSTS_MASK 0x20000UL /**< Bit mask for USB_NAKSTS */
<> 150:02e0a0aed4ec 1925 #define _USB_DIEP0CTL_NAKSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0CTL */
<> 150:02e0a0aed4ec 1926 #define USB_DIEP0CTL_NAKSTS_DEFAULT (_USB_DIEP0CTL_NAKSTS_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_DIEP0CTL */
<> 150:02e0a0aed4ec 1927 #define _USB_DIEP0CTL_EPTYPE_SHIFT 18 /**< Shift value for USB_EPTYPE */
<> 150:02e0a0aed4ec 1928 #define _USB_DIEP0CTL_EPTYPE_MASK 0xC0000UL /**< Bit mask for USB_EPTYPE */
<> 150:02e0a0aed4ec 1929 #define _USB_DIEP0CTL_EPTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0CTL */
<> 150:02e0a0aed4ec 1930 #define USB_DIEP0CTL_EPTYPE_DEFAULT (_USB_DIEP0CTL_EPTYPE_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_DIEP0CTL */
<> 150:02e0a0aed4ec 1931 #define USB_DIEP0CTL_STALL (0x1UL << 21) /**< Handshake */
<> 150:02e0a0aed4ec 1932 #define _USB_DIEP0CTL_STALL_SHIFT 21 /**< Shift value for USB_STALL */
<> 150:02e0a0aed4ec 1933 #define _USB_DIEP0CTL_STALL_MASK 0x200000UL /**< Bit mask for USB_STALL */
<> 150:02e0a0aed4ec 1934 #define _USB_DIEP0CTL_STALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0CTL */
<> 150:02e0a0aed4ec 1935 #define USB_DIEP0CTL_STALL_DEFAULT (_USB_DIEP0CTL_STALL_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_DIEP0CTL */
<> 150:02e0a0aed4ec 1936 #define _USB_DIEP0CTL_TXFNUM_SHIFT 22 /**< Shift value for USB_TXFNUM */
<> 150:02e0a0aed4ec 1937 #define _USB_DIEP0CTL_TXFNUM_MASK 0x3C00000UL /**< Bit mask for USB_TXFNUM */
<> 150:02e0a0aed4ec 1938 #define _USB_DIEP0CTL_TXFNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0CTL */
<> 150:02e0a0aed4ec 1939 #define USB_DIEP0CTL_TXFNUM_DEFAULT (_USB_DIEP0CTL_TXFNUM_DEFAULT << 22) /**< Shifted mode DEFAULT for USB_DIEP0CTL */
<> 150:02e0a0aed4ec 1940 #define USB_DIEP0CTL_CNAK (0x1UL << 26) /**< Clear NAK */
<> 150:02e0a0aed4ec 1941 #define _USB_DIEP0CTL_CNAK_SHIFT 26 /**< Shift value for USB_CNAK */
<> 150:02e0a0aed4ec 1942 #define _USB_DIEP0CTL_CNAK_MASK 0x4000000UL /**< Bit mask for USB_CNAK */
<> 150:02e0a0aed4ec 1943 #define _USB_DIEP0CTL_CNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0CTL */
<> 150:02e0a0aed4ec 1944 #define USB_DIEP0CTL_CNAK_DEFAULT (_USB_DIEP0CTL_CNAK_DEFAULT << 26) /**< Shifted mode DEFAULT for USB_DIEP0CTL */
<> 150:02e0a0aed4ec 1945 #define USB_DIEP0CTL_SNAK (0x1UL << 27) /**< Set NAK */
<> 150:02e0a0aed4ec 1946 #define _USB_DIEP0CTL_SNAK_SHIFT 27 /**< Shift value for USB_SNAK */
<> 150:02e0a0aed4ec 1947 #define _USB_DIEP0CTL_SNAK_MASK 0x8000000UL /**< Bit mask for USB_SNAK */
<> 150:02e0a0aed4ec 1948 #define _USB_DIEP0CTL_SNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0CTL */
<> 150:02e0a0aed4ec 1949 #define USB_DIEP0CTL_SNAK_DEFAULT (_USB_DIEP0CTL_SNAK_DEFAULT << 27) /**< Shifted mode DEFAULT for USB_DIEP0CTL */
<> 150:02e0a0aed4ec 1950 #define USB_DIEP0CTL_EPDIS (0x1UL << 30) /**< Endpoint Disable */
<> 150:02e0a0aed4ec 1951 #define _USB_DIEP0CTL_EPDIS_SHIFT 30 /**< Shift value for USB_EPDIS */
<> 150:02e0a0aed4ec 1952 #define _USB_DIEP0CTL_EPDIS_MASK 0x40000000UL /**< Bit mask for USB_EPDIS */
<> 150:02e0a0aed4ec 1953 #define _USB_DIEP0CTL_EPDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0CTL */
<> 150:02e0a0aed4ec 1954 #define USB_DIEP0CTL_EPDIS_DEFAULT (_USB_DIEP0CTL_EPDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for USB_DIEP0CTL */
<> 150:02e0a0aed4ec 1955 #define USB_DIEP0CTL_EPENA (0x1UL << 31) /**< Endpoint Enable */
<> 150:02e0a0aed4ec 1956 #define _USB_DIEP0CTL_EPENA_SHIFT 31 /**< Shift value for USB_EPENA */
<> 150:02e0a0aed4ec 1957 #define _USB_DIEP0CTL_EPENA_MASK 0x80000000UL /**< Bit mask for USB_EPENA */
<> 150:02e0a0aed4ec 1958 #define _USB_DIEP0CTL_EPENA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0CTL */
<> 150:02e0a0aed4ec 1959 #define USB_DIEP0CTL_EPENA_DEFAULT (_USB_DIEP0CTL_EPENA_DEFAULT << 31) /**< Shifted mode DEFAULT for USB_DIEP0CTL */
<> 150:02e0a0aed4ec 1960
<> 150:02e0a0aed4ec 1961 /* Bit fields for USB DIEP0INT */
<> 150:02e0a0aed4ec 1962 #define _USB_DIEP0INT_RESETVALUE 0x00000080UL /**< Default value for USB_DIEP0INT */
<> 150:02e0a0aed4ec 1963 #define _USB_DIEP0INT_MASK 0x000038DFUL /**< Mask for USB_DIEP0INT */
<> 150:02e0a0aed4ec 1964 #define USB_DIEP0INT_XFERCOMPL (0x1UL << 0) /**< Transfer Completed Interrupt */
<> 150:02e0a0aed4ec 1965 #define _USB_DIEP0INT_XFERCOMPL_SHIFT 0 /**< Shift value for USB_XFERCOMPL */
<> 150:02e0a0aed4ec 1966 #define _USB_DIEP0INT_XFERCOMPL_MASK 0x1UL /**< Bit mask for USB_XFERCOMPL */
<> 150:02e0a0aed4ec 1967 #define _USB_DIEP0INT_XFERCOMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0INT */
<> 150:02e0a0aed4ec 1968 #define USB_DIEP0INT_XFERCOMPL_DEFAULT (_USB_DIEP0INT_XFERCOMPL_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEP0INT */
<> 150:02e0a0aed4ec 1969 #define USB_DIEP0INT_EPDISBLD (0x1UL << 1) /**< Endpoint Disabled Interrupt */
<> 150:02e0a0aed4ec 1970 #define _USB_DIEP0INT_EPDISBLD_SHIFT 1 /**< Shift value for USB_EPDISBLD */
<> 150:02e0a0aed4ec 1971 #define _USB_DIEP0INT_EPDISBLD_MASK 0x2UL /**< Bit mask for USB_EPDISBLD */
<> 150:02e0a0aed4ec 1972 #define _USB_DIEP0INT_EPDISBLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0INT */
<> 150:02e0a0aed4ec 1973 #define USB_DIEP0INT_EPDISBLD_DEFAULT (_USB_DIEP0INT_EPDISBLD_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_DIEP0INT */
<> 150:02e0a0aed4ec 1974 #define USB_DIEP0INT_AHBERR (0x1UL << 2) /**< AHB Error */
<> 150:02e0a0aed4ec 1975 #define _USB_DIEP0INT_AHBERR_SHIFT 2 /**< Shift value for USB_AHBERR */
<> 150:02e0a0aed4ec 1976 #define _USB_DIEP0INT_AHBERR_MASK 0x4UL /**< Bit mask for USB_AHBERR */
<> 150:02e0a0aed4ec 1977 #define _USB_DIEP0INT_AHBERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0INT */
<> 150:02e0a0aed4ec 1978 #define USB_DIEP0INT_AHBERR_DEFAULT (_USB_DIEP0INT_AHBERR_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_DIEP0INT */
<> 150:02e0a0aed4ec 1979 #define USB_DIEP0INT_TIMEOUT (0x1UL << 3) /**< Timeout Condition */
<> 150:02e0a0aed4ec 1980 #define _USB_DIEP0INT_TIMEOUT_SHIFT 3 /**< Shift value for USB_TIMEOUT */
<> 150:02e0a0aed4ec 1981 #define _USB_DIEP0INT_TIMEOUT_MASK 0x8UL /**< Bit mask for USB_TIMEOUT */
<> 150:02e0a0aed4ec 1982 #define _USB_DIEP0INT_TIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0INT */
<> 150:02e0a0aed4ec 1983 #define USB_DIEP0INT_TIMEOUT_DEFAULT (_USB_DIEP0INT_TIMEOUT_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_DIEP0INT */
<> 150:02e0a0aed4ec 1984 #define USB_DIEP0INT_INTKNTXFEMP (0x1UL << 4) /**< IN Token Received When TxFIFO is Empty */
<> 150:02e0a0aed4ec 1985 #define _USB_DIEP0INT_INTKNTXFEMP_SHIFT 4 /**< Shift value for USB_INTKNTXFEMP */
<> 150:02e0a0aed4ec 1986 #define _USB_DIEP0INT_INTKNTXFEMP_MASK 0x10UL /**< Bit mask for USB_INTKNTXFEMP */
<> 150:02e0a0aed4ec 1987 #define _USB_DIEP0INT_INTKNTXFEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0INT */
<> 150:02e0a0aed4ec 1988 #define USB_DIEP0INT_INTKNTXFEMP_DEFAULT (_USB_DIEP0INT_INTKNTXFEMP_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_DIEP0INT */
<> 150:02e0a0aed4ec 1989 #define USB_DIEP0INT_INEPNAKEFF (0x1UL << 6) /**< IN Endpoint NAK Effective */
<> 150:02e0a0aed4ec 1990 #define _USB_DIEP0INT_INEPNAKEFF_SHIFT 6 /**< Shift value for USB_INEPNAKEFF */
<> 150:02e0a0aed4ec 1991 #define _USB_DIEP0INT_INEPNAKEFF_MASK 0x40UL /**< Bit mask for USB_INEPNAKEFF */
<> 150:02e0a0aed4ec 1992 #define _USB_DIEP0INT_INEPNAKEFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0INT */
<> 150:02e0a0aed4ec 1993 #define USB_DIEP0INT_INEPNAKEFF_DEFAULT (_USB_DIEP0INT_INEPNAKEFF_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_DIEP0INT */
<> 150:02e0a0aed4ec 1994 #define USB_DIEP0INT_TXFEMP (0x1UL << 7) /**< Transmit FIFO Empty */
<> 150:02e0a0aed4ec 1995 #define _USB_DIEP0INT_TXFEMP_SHIFT 7 /**< Shift value for USB_TXFEMP */
<> 150:02e0a0aed4ec 1996 #define _USB_DIEP0INT_TXFEMP_MASK 0x80UL /**< Bit mask for USB_TXFEMP */
<> 150:02e0a0aed4ec 1997 #define _USB_DIEP0INT_TXFEMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_DIEP0INT */
<> 150:02e0a0aed4ec 1998 #define USB_DIEP0INT_TXFEMP_DEFAULT (_USB_DIEP0INT_TXFEMP_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_DIEP0INT */
<> 150:02e0a0aed4ec 1999 #define USB_DIEP0INT_PKTDRPSTS (0x1UL << 11) /**< Packet Drop Status */
<> 150:02e0a0aed4ec 2000 #define _USB_DIEP0INT_PKTDRPSTS_SHIFT 11 /**< Shift value for USB_PKTDRPSTS */
<> 150:02e0a0aed4ec 2001 #define _USB_DIEP0INT_PKTDRPSTS_MASK 0x800UL /**< Bit mask for USB_PKTDRPSTS */
<> 150:02e0a0aed4ec 2002 #define _USB_DIEP0INT_PKTDRPSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0INT */
<> 150:02e0a0aed4ec 2003 #define USB_DIEP0INT_PKTDRPSTS_DEFAULT (_USB_DIEP0INT_PKTDRPSTS_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_DIEP0INT */
<> 150:02e0a0aed4ec 2004 #define USB_DIEP0INT_BBLEERR (0x1UL << 12) /**< NAK Interrupt */
<> 150:02e0a0aed4ec 2005 #define _USB_DIEP0INT_BBLEERR_SHIFT 12 /**< Shift value for USB_BBLEERR */
<> 150:02e0a0aed4ec 2006 #define _USB_DIEP0INT_BBLEERR_MASK 0x1000UL /**< Bit mask for USB_BBLEERR */
<> 150:02e0a0aed4ec 2007 #define _USB_DIEP0INT_BBLEERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0INT */
<> 150:02e0a0aed4ec 2008 #define USB_DIEP0INT_BBLEERR_DEFAULT (_USB_DIEP0INT_BBLEERR_DEFAULT << 12) /**< Shifted mode DEFAULT for USB_DIEP0INT */
<> 150:02e0a0aed4ec 2009 #define USB_DIEP0INT_NAKINTRPT (0x1UL << 13) /**< NAK Interrupt */
<> 150:02e0a0aed4ec 2010 #define _USB_DIEP0INT_NAKINTRPT_SHIFT 13 /**< Shift value for USB_NAKINTRPT */
<> 150:02e0a0aed4ec 2011 #define _USB_DIEP0INT_NAKINTRPT_MASK 0x2000UL /**< Bit mask for USB_NAKINTRPT */
<> 150:02e0a0aed4ec 2012 #define _USB_DIEP0INT_NAKINTRPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0INT */
<> 150:02e0a0aed4ec 2013 #define USB_DIEP0INT_NAKINTRPT_DEFAULT (_USB_DIEP0INT_NAKINTRPT_DEFAULT << 13) /**< Shifted mode DEFAULT for USB_DIEP0INT */
<> 150:02e0a0aed4ec 2014
<> 150:02e0a0aed4ec 2015 /* Bit fields for USB DIEP0TSIZ */
<> 150:02e0a0aed4ec 2016 #define _USB_DIEP0TSIZ_RESETVALUE 0x00000000UL /**< Default value for USB_DIEP0TSIZ */
<> 150:02e0a0aed4ec 2017 #define _USB_DIEP0TSIZ_MASK 0x0018007FUL /**< Mask for USB_DIEP0TSIZ */
<> 150:02e0a0aed4ec 2018 #define _USB_DIEP0TSIZ_XFERSIZE_SHIFT 0 /**< Shift value for USB_XFERSIZE */
<> 150:02e0a0aed4ec 2019 #define _USB_DIEP0TSIZ_XFERSIZE_MASK 0x7FUL /**< Bit mask for USB_XFERSIZE */
<> 150:02e0a0aed4ec 2020 #define _USB_DIEP0TSIZ_XFERSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0TSIZ */
<> 150:02e0a0aed4ec 2021 #define USB_DIEP0TSIZ_XFERSIZE_DEFAULT (_USB_DIEP0TSIZ_XFERSIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEP0TSIZ */
<> 150:02e0a0aed4ec 2022 #define _USB_DIEP0TSIZ_PKTCNT_SHIFT 19 /**< Shift value for USB_PKTCNT */
<> 150:02e0a0aed4ec 2023 #define _USB_DIEP0TSIZ_PKTCNT_MASK 0x180000UL /**< Bit mask for USB_PKTCNT */
<> 150:02e0a0aed4ec 2024 #define _USB_DIEP0TSIZ_PKTCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0TSIZ */
<> 150:02e0a0aed4ec 2025 #define USB_DIEP0TSIZ_PKTCNT_DEFAULT (_USB_DIEP0TSIZ_PKTCNT_DEFAULT << 19) /**< Shifted mode DEFAULT for USB_DIEP0TSIZ */
<> 150:02e0a0aed4ec 2026
<> 150:02e0a0aed4ec 2027 /* Bit fields for USB DIEP0DMAADDR */
<> 150:02e0a0aed4ec 2028 #define _USB_DIEP0DMAADDR_RESETVALUE 0x00000000UL /**< Default value for USB_DIEP0DMAADDR */
<> 150:02e0a0aed4ec 2029 #define _USB_DIEP0DMAADDR_MASK 0xFFFFFFFFUL /**< Mask for USB_DIEP0DMAADDR */
<> 150:02e0a0aed4ec 2030 #define _USB_DIEP0DMAADDR_DIEP0DMAADDR_SHIFT 0 /**< Shift value for USB_DIEP0DMAADDR */
<> 150:02e0a0aed4ec 2031 #define _USB_DIEP0DMAADDR_DIEP0DMAADDR_MASK 0xFFFFFFFFUL /**< Bit mask for USB_DIEP0DMAADDR */
<> 150:02e0a0aed4ec 2032 #define _USB_DIEP0DMAADDR_DIEP0DMAADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0DMAADDR */
<> 150:02e0a0aed4ec 2033 #define USB_DIEP0DMAADDR_DIEP0DMAADDR_DEFAULT (_USB_DIEP0DMAADDR_DIEP0DMAADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEP0DMAADDR */
<> 150:02e0a0aed4ec 2034
<> 150:02e0a0aed4ec 2035 /* Bit fields for USB DIEP0TXFSTS */
<> 150:02e0a0aed4ec 2036 #define _USB_DIEP0TXFSTS_RESETVALUE 0x00000200UL /**< Default value for USB_DIEP0TXFSTS */
<> 150:02e0a0aed4ec 2037 #define _USB_DIEP0TXFSTS_MASK 0x0000FFFFUL /**< Mask for USB_DIEP0TXFSTS */
<> 150:02e0a0aed4ec 2038 #define _USB_DIEP0TXFSTS_SPCAVAIL_SHIFT 0 /**< Shift value for USB_SPCAVAIL */
<> 150:02e0a0aed4ec 2039 #define _USB_DIEP0TXFSTS_SPCAVAIL_MASK 0xFFFFUL /**< Bit mask for USB_SPCAVAIL */
<> 150:02e0a0aed4ec 2040 #define _USB_DIEP0TXFSTS_SPCAVAIL_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_DIEP0TXFSTS */
<> 150:02e0a0aed4ec 2041 #define USB_DIEP0TXFSTS_SPCAVAIL_DEFAULT (_USB_DIEP0TXFSTS_SPCAVAIL_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEP0TXFSTS */
<> 150:02e0a0aed4ec 2042
<> 150:02e0a0aed4ec 2043 /* Bit fields for USB DIEP_CTL */
<> 150:02e0a0aed4ec 2044 #define _USB_DIEP_CTL_RESETVALUE 0x00000000UL /**< Default value for USB_DIEP_CTL */
<> 150:02e0a0aed4ec 2045 #define _USB_DIEP_CTL_MASK 0xFFEF87FFUL /**< Mask for USB_DIEP_CTL */
<> 150:02e0a0aed4ec 2046 #define _USB_DIEP_CTL_MPS_SHIFT 0 /**< Shift value for USB_MPS */
<> 150:02e0a0aed4ec 2047 #define _USB_DIEP_CTL_MPS_MASK 0x7FFUL /**< Bit mask for USB_MPS */
<> 150:02e0a0aed4ec 2048 #define _USB_DIEP_CTL_MPS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */
<> 150:02e0a0aed4ec 2049 #define USB_DIEP_CTL_MPS_DEFAULT (_USB_DIEP_CTL_MPS_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEP_CTL */
<> 150:02e0a0aed4ec 2050 #define USB_DIEP_CTL_USBACTEP (0x1UL << 15) /**< USB Active Endpoint */
<> 150:02e0a0aed4ec 2051 #define _USB_DIEP_CTL_USBACTEP_SHIFT 15 /**< Shift value for USB_USBACTEP */
<> 150:02e0a0aed4ec 2052 #define _USB_DIEP_CTL_USBACTEP_MASK 0x8000UL /**< Bit mask for USB_USBACTEP */
<> 150:02e0a0aed4ec 2053 #define _USB_DIEP_CTL_USBACTEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */
<> 150:02e0a0aed4ec 2054 #define USB_DIEP_CTL_USBACTEP_DEFAULT (_USB_DIEP_CTL_USBACTEP_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_DIEP_CTL */
<> 150:02e0a0aed4ec 2055 #define USB_DIEP_CTL_DPIDEOF (0x1UL << 16) /**< Endpoint Data PID / Even or Odd Frame */
<> 150:02e0a0aed4ec 2056 #define _USB_DIEP_CTL_DPIDEOF_SHIFT 16 /**< Shift value for USB_DPIDEOF */
<> 150:02e0a0aed4ec 2057 #define _USB_DIEP_CTL_DPIDEOF_MASK 0x10000UL /**< Bit mask for USB_DPIDEOF */
<> 150:02e0a0aed4ec 2058 #define _USB_DIEP_CTL_DPIDEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */
<> 150:02e0a0aed4ec 2059 #define _USB_DIEP_CTL_DPIDEOF_DATA0EVEN 0x00000000UL /**< Mode DATA0EVEN for USB_DIEP_CTL */
<> 150:02e0a0aed4ec 2060 #define _USB_DIEP_CTL_DPIDEOF_DATA1ODD 0x00000001UL /**< Mode DATA1ODD for USB_DIEP_CTL */
<> 150:02e0a0aed4ec 2061 #define USB_DIEP_CTL_DPIDEOF_DEFAULT (_USB_DIEP_CTL_DPIDEOF_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_DIEP_CTL */
<> 150:02e0a0aed4ec 2062 #define USB_DIEP_CTL_DPIDEOF_DATA0EVEN (_USB_DIEP_CTL_DPIDEOF_DATA0EVEN << 16) /**< Shifted mode DATA0EVEN for USB_DIEP_CTL */
<> 150:02e0a0aed4ec 2063 #define USB_DIEP_CTL_DPIDEOF_DATA1ODD (_USB_DIEP_CTL_DPIDEOF_DATA1ODD << 16) /**< Shifted mode DATA1ODD for USB_DIEP_CTL */
<> 150:02e0a0aed4ec 2064 #define USB_DIEP_CTL_NAKSTS (0x1UL << 17) /**< NAK Status */
<> 150:02e0a0aed4ec 2065 #define _USB_DIEP_CTL_NAKSTS_SHIFT 17 /**< Shift value for USB_NAKSTS */
<> 150:02e0a0aed4ec 2066 #define _USB_DIEP_CTL_NAKSTS_MASK 0x20000UL /**< Bit mask for USB_NAKSTS */
<> 150:02e0a0aed4ec 2067 #define _USB_DIEP_CTL_NAKSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */
<> 150:02e0a0aed4ec 2068 #define USB_DIEP_CTL_NAKSTS_DEFAULT (_USB_DIEP_CTL_NAKSTS_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_DIEP_CTL */
<> 150:02e0a0aed4ec 2069 #define _USB_DIEP_CTL_EPTYPE_SHIFT 18 /**< Shift value for USB_EPTYPE */
<> 150:02e0a0aed4ec 2070 #define _USB_DIEP_CTL_EPTYPE_MASK 0xC0000UL /**< Bit mask for USB_EPTYPE */
<> 150:02e0a0aed4ec 2071 #define _USB_DIEP_CTL_EPTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */
<> 150:02e0a0aed4ec 2072 #define _USB_DIEP_CTL_EPTYPE_CONTROL 0x00000000UL /**< Mode CONTROL for USB_DIEP_CTL */
<> 150:02e0a0aed4ec 2073 #define _USB_DIEP_CTL_EPTYPE_ISO 0x00000001UL /**< Mode ISO for USB_DIEP_CTL */
<> 150:02e0a0aed4ec 2074 #define _USB_DIEP_CTL_EPTYPE_BULK 0x00000002UL /**< Mode BULK for USB_DIEP_CTL */
<> 150:02e0a0aed4ec 2075 #define _USB_DIEP_CTL_EPTYPE_INT 0x00000003UL /**< Mode INT for USB_DIEP_CTL */
<> 150:02e0a0aed4ec 2076 #define USB_DIEP_CTL_EPTYPE_DEFAULT (_USB_DIEP_CTL_EPTYPE_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_DIEP_CTL */
<> 150:02e0a0aed4ec 2077 #define USB_DIEP_CTL_EPTYPE_CONTROL (_USB_DIEP_CTL_EPTYPE_CONTROL << 18) /**< Shifted mode CONTROL for USB_DIEP_CTL */
<> 150:02e0a0aed4ec 2078 #define USB_DIEP_CTL_EPTYPE_ISO (_USB_DIEP_CTL_EPTYPE_ISO << 18) /**< Shifted mode ISO for USB_DIEP_CTL */
<> 150:02e0a0aed4ec 2079 #define USB_DIEP_CTL_EPTYPE_BULK (_USB_DIEP_CTL_EPTYPE_BULK << 18) /**< Shifted mode BULK for USB_DIEP_CTL */
<> 150:02e0a0aed4ec 2080 #define USB_DIEP_CTL_EPTYPE_INT (_USB_DIEP_CTL_EPTYPE_INT << 18) /**< Shifted mode INT for USB_DIEP_CTL */
<> 150:02e0a0aed4ec 2081 #define USB_DIEP_CTL_STALL (0x1UL << 21) /**< Handshake */
<> 150:02e0a0aed4ec 2082 #define _USB_DIEP_CTL_STALL_SHIFT 21 /**< Shift value for USB_STALL */
<> 150:02e0a0aed4ec 2083 #define _USB_DIEP_CTL_STALL_MASK 0x200000UL /**< Bit mask for USB_STALL */
<> 150:02e0a0aed4ec 2084 #define _USB_DIEP_CTL_STALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */
<> 150:02e0a0aed4ec 2085 #define USB_DIEP_CTL_STALL_DEFAULT (_USB_DIEP_CTL_STALL_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_DIEP_CTL */
<> 150:02e0a0aed4ec 2086 #define _USB_DIEP_CTL_TXFNUM_SHIFT 22 /**< Shift value for USB_TXFNUM */
<> 150:02e0a0aed4ec 2087 #define _USB_DIEP_CTL_TXFNUM_MASK 0x3C00000UL /**< Bit mask for USB_TXFNUM */
<> 150:02e0a0aed4ec 2088 #define _USB_DIEP_CTL_TXFNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */
<> 150:02e0a0aed4ec 2089 #define USB_DIEP_CTL_TXFNUM_DEFAULT (_USB_DIEP_CTL_TXFNUM_DEFAULT << 22) /**< Shifted mode DEFAULT for USB_DIEP_CTL */
<> 150:02e0a0aed4ec 2090 #define USB_DIEP_CTL_CNAK (0x1UL << 26) /**< Clear NAK */
<> 150:02e0a0aed4ec 2091 #define _USB_DIEP_CTL_CNAK_SHIFT 26 /**< Shift value for USB_CNAK */
<> 150:02e0a0aed4ec 2092 #define _USB_DIEP_CTL_CNAK_MASK 0x4000000UL /**< Bit mask for USB_CNAK */
<> 150:02e0a0aed4ec 2093 #define _USB_DIEP_CTL_CNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */
<> 150:02e0a0aed4ec 2094 #define USB_DIEP_CTL_CNAK_DEFAULT (_USB_DIEP_CTL_CNAK_DEFAULT << 26) /**< Shifted mode DEFAULT for USB_DIEP_CTL */
<> 150:02e0a0aed4ec 2095 #define USB_DIEP_CTL_SNAK (0x1UL << 27) /**< Set NAK */
<> 150:02e0a0aed4ec 2096 #define _USB_DIEP_CTL_SNAK_SHIFT 27 /**< Shift value for USB_SNAK */
<> 150:02e0a0aed4ec 2097 #define _USB_DIEP_CTL_SNAK_MASK 0x8000000UL /**< Bit mask for USB_SNAK */
<> 150:02e0a0aed4ec 2098 #define _USB_DIEP_CTL_SNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */
<> 150:02e0a0aed4ec 2099 #define USB_DIEP_CTL_SNAK_DEFAULT (_USB_DIEP_CTL_SNAK_DEFAULT << 27) /**< Shifted mode DEFAULT for USB_DIEP_CTL */
<> 150:02e0a0aed4ec 2100 #define USB_DIEP_CTL_SETD0PIDEF (0x1UL << 28) /**< Set DATA0 PID / Even Frame */
<> 150:02e0a0aed4ec 2101 #define _USB_DIEP_CTL_SETD0PIDEF_SHIFT 28 /**< Shift value for USB_SETD0PIDEF */
<> 150:02e0a0aed4ec 2102 #define _USB_DIEP_CTL_SETD0PIDEF_MASK 0x10000000UL /**< Bit mask for USB_SETD0PIDEF */
<> 150:02e0a0aed4ec 2103 #define _USB_DIEP_CTL_SETD0PIDEF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */
<> 150:02e0a0aed4ec 2104 #define USB_DIEP_CTL_SETD0PIDEF_DEFAULT (_USB_DIEP_CTL_SETD0PIDEF_DEFAULT << 28) /**< Shifted mode DEFAULT for USB_DIEP_CTL */
<> 150:02e0a0aed4ec 2105 #define USB_DIEP_CTL_SETD1PIDOF (0x1UL << 29) /**< Set DATA1 PID / Odd Frame */
<> 150:02e0a0aed4ec 2106 #define _USB_DIEP_CTL_SETD1PIDOF_SHIFT 29 /**< Shift value for USB_SETD1PIDOF */
<> 150:02e0a0aed4ec 2107 #define _USB_DIEP_CTL_SETD1PIDOF_MASK 0x20000000UL /**< Bit mask for USB_SETD1PIDOF */
<> 150:02e0a0aed4ec 2108 #define _USB_DIEP_CTL_SETD1PIDOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */
<> 150:02e0a0aed4ec 2109 #define USB_DIEP_CTL_SETD1PIDOF_DEFAULT (_USB_DIEP_CTL_SETD1PIDOF_DEFAULT << 29) /**< Shifted mode DEFAULT for USB_DIEP_CTL */
<> 150:02e0a0aed4ec 2110 #define USB_DIEP_CTL_EPDIS (0x1UL << 30) /**< Endpoint Disable */
<> 150:02e0a0aed4ec 2111 #define _USB_DIEP_CTL_EPDIS_SHIFT 30 /**< Shift value for USB_EPDIS */
<> 150:02e0a0aed4ec 2112 #define _USB_DIEP_CTL_EPDIS_MASK 0x40000000UL /**< Bit mask for USB_EPDIS */
<> 150:02e0a0aed4ec 2113 #define _USB_DIEP_CTL_EPDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */
<> 150:02e0a0aed4ec 2114 #define USB_DIEP_CTL_EPDIS_DEFAULT (_USB_DIEP_CTL_EPDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for USB_DIEP_CTL */
<> 150:02e0a0aed4ec 2115 #define USB_DIEP_CTL_EPENA (0x1UL << 31) /**< Endpoint Enable */
<> 150:02e0a0aed4ec 2116 #define _USB_DIEP_CTL_EPENA_SHIFT 31 /**< Shift value for USB_EPENA */
<> 150:02e0a0aed4ec 2117 #define _USB_DIEP_CTL_EPENA_MASK 0x80000000UL /**< Bit mask for USB_EPENA */
<> 150:02e0a0aed4ec 2118 #define _USB_DIEP_CTL_EPENA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */
<> 150:02e0a0aed4ec 2119 #define USB_DIEP_CTL_EPENA_DEFAULT (_USB_DIEP_CTL_EPENA_DEFAULT << 31) /**< Shifted mode DEFAULT for USB_DIEP_CTL */
<> 150:02e0a0aed4ec 2120
<> 150:02e0a0aed4ec 2121 /* Bit fields for USB DIEP_INT */
<> 150:02e0a0aed4ec 2122 #define _USB_DIEP_INT_RESETVALUE 0x00000080UL /**< Default value for USB_DIEP_INT */
<> 150:02e0a0aed4ec 2123 #define _USB_DIEP_INT_MASK 0x000038DFUL /**< Mask for USB_DIEP_INT */
<> 150:02e0a0aed4ec 2124 #define USB_DIEP_INT_XFERCOMPL (0x1UL << 0) /**< Transfer Completed Interrupt */
<> 150:02e0a0aed4ec 2125 #define _USB_DIEP_INT_XFERCOMPL_SHIFT 0 /**< Shift value for USB_XFERCOMPL */
<> 150:02e0a0aed4ec 2126 #define _USB_DIEP_INT_XFERCOMPL_MASK 0x1UL /**< Bit mask for USB_XFERCOMPL */
<> 150:02e0a0aed4ec 2127 #define _USB_DIEP_INT_XFERCOMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_INT */
<> 150:02e0a0aed4ec 2128 #define USB_DIEP_INT_XFERCOMPL_DEFAULT (_USB_DIEP_INT_XFERCOMPL_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEP_INT */
<> 150:02e0a0aed4ec 2129 #define USB_DIEP_INT_EPDISBLD (0x1UL << 1) /**< Endpoint Disabled Interrupt */
<> 150:02e0a0aed4ec 2130 #define _USB_DIEP_INT_EPDISBLD_SHIFT 1 /**< Shift value for USB_EPDISBLD */
<> 150:02e0a0aed4ec 2131 #define _USB_DIEP_INT_EPDISBLD_MASK 0x2UL /**< Bit mask for USB_EPDISBLD */
<> 150:02e0a0aed4ec 2132 #define _USB_DIEP_INT_EPDISBLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_INT */
<> 150:02e0a0aed4ec 2133 #define USB_DIEP_INT_EPDISBLD_DEFAULT (_USB_DIEP_INT_EPDISBLD_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_DIEP_INT */
<> 150:02e0a0aed4ec 2134 #define USB_DIEP_INT_AHBERR (0x1UL << 2) /**< AHB Error */
<> 150:02e0a0aed4ec 2135 #define _USB_DIEP_INT_AHBERR_SHIFT 2 /**< Shift value for USB_AHBERR */
<> 150:02e0a0aed4ec 2136 #define _USB_DIEP_INT_AHBERR_MASK 0x4UL /**< Bit mask for USB_AHBERR */
<> 150:02e0a0aed4ec 2137 #define _USB_DIEP_INT_AHBERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_INT */
<> 150:02e0a0aed4ec 2138 #define USB_DIEP_INT_AHBERR_DEFAULT (_USB_DIEP_INT_AHBERR_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_DIEP_INT */
<> 150:02e0a0aed4ec 2139 #define USB_DIEP_INT_TIMEOUT (0x1UL << 3) /**< Timeout Condition */
<> 150:02e0a0aed4ec 2140 #define _USB_DIEP_INT_TIMEOUT_SHIFT 3 /**< Shift value for USB_TIMEOUT */
<> 150:02e0a0aed4ec 2141 #define _USB_DIEP_INT_TIMEOUT_MASK 0x8UL /**< Bit mask for USB_TIMEOUT */
<> 150:02e0a0aed4ec 2142 #define _USB_DIEP_INT_TIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_INT */
<> 150:02e0a0aed4ec 2143 #define USB_DIEP_INT_TIMEOUT_DEFAULT (_USB_DIEP_INT_TIMEOUT_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_DIEP_INT */
<> 150:02e0a0aed4ec 2144 #define USB_DIEP_INT_INTKNTXFEMP (0x1UL << 4) /**< IN Token Received When TxFIFO is Empty */
<> 150:02e0a0aed4ec 2145 #define _USB_DIEP_INT_INTKNTXFEMP_SHIFT 4 /**< Shift value for USB_INTKNTXFEMP */
<> 150:02e0a0aed4ec 2146 #define _USB_DIEP_INT_INTKNTXFEMP_MASK 0x10UL /**< Bit mask for USB_INTKNTXFEMP */
<> 150:02e0a0aed4ec 2147 #define _USB_DIEP_INT_INTKNTXFEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_INT */
<> 150:02e0a0aed4ec 2148 #define USB_DIEP_INT_INTKNTXFEMP_DEFAULT (_USB_DIEP_INT_INTKNTXFEMP_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_DIEP_INT */
<> 150:02e0a0aed4ec 2149 #define USB_DIEP_INT_INEPNAKEFF (0x1UL << 6) /**< IN Endpoint NAK Effective */
<> 150:02e0a0aed4ec 2150 #define _USB_DIEP_INT_INEPNAKEFF_SHIFT 6 /**< Shift value for USB_INEPNAKEFF */
<> 150:02e0a0aed4ec 2151 #define _USB_DIEP_INT_INEPNAKEFF_MASK 0x40UL /**< Bit mask for USB_INEPNAKEFF */
<> 150:02e0a0aed4ec 2152 #define _USB_DIEP_INT_INEPNAKEFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_INT */
<> 150:02e0a0aed4ec 2153 #define USB_DIEP_INT_INEPNAKEFF_DEFAULT (_USB_DIEP_INT_INEPNAKEFF_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_DIEP_INT */
<> 150:02e0a0aed4ec 2154 #define USB_DIEP_INT_TXFEMP (0x1UL << 7) /**< Transmit FIFO Empty */
<> 150:02e0a0aed4ec 2155 #define _USB_DIEP_INT_TXFEMP_SHIFT 7 /**< Shift value for USB_TXFEMP */
<> 150:02e0a0aed4ec 2156 #define _USB_DIEP_INT_TXFEMP_MASK 0x80UL /**< Bit mask for USB_TXFEMP */
<> 150:02e0a0aed4ec 2157 #define _USB_DIEP_INT_TXFEMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_DIEP_INT */
<> 150:02e0a0aed4ec 2158 #define USB_DIEP_INT_TXFEMP_DEFAULT (_USB_DIEP_INT_TXFEMP_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_DIEP_INT */
<> 150:02e0a0aed4ec 2159 #define USB_DIEP_INT_PKTDRPSTS (0x1UL << 11) /**< Packet Drop Status */
<> 150:02e0a0aed4ec 2160 #define _USB_DIEP_INT_PKTDRPSTS_SHIFT 11 /**< Shift value for USB_PKTDRPSTS */
<> 150:02e0a0aed4ec 2161 #define _USB_DIEP_INT_PKTDRPSTS_MASK 0x800UL /**< Bit mask for USB_PKTDRPSTS */
<> 150:02e0a0aed4ec 2162 #define _USB_DIEP_INT_PKTDRPSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_INT */
<> 150:02e0a0aed4ec 2163 #define USB_DIEP_INT_PKTDRPSTS_DEFAULT (_USB_DIEP_INT_PKTDRPSTS_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_DIEP_INT */
<> 150:02e0a0aed4ec 2164 #define USB_DIEP_INT_BBLEERR (0x1UL << 12) /**< NAK Interrupt */
<> 150:02e0a0aed4ec 2165 #define _USB_DIEP_INT_BBLEERR_SHIFT 12 /**< Shift value for USB_BBLEERR */
<> 150:02e0a0aed4ec 2166 #define _USB_DIEP_INT_BBLEERR_MASK 0x1000UL /**< Bit mask for USB_BBLEERR */
<> 150:02e0a0aed4ec 2167 #define _USB_DIEP_INT_BBLEERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_INT */
<> 150:02e0a0aed4ec 2168 #define USB_DIEP_INT_BBLEERR_DEFAULT (_USB_DIEP_INT_BBLEERR_DEFAULT << 12) /**< Shifted mode DEFAULT for USB_DIEP_INT */
<> 150:02e0a0aed4ec 2169 #define USB_DIEP_INT_NAKINTRPT (0x1UL << 13) /**< NAK Interrupt */
<> 150:02e0a0aed4ec 2170 #define _USB_DIEP_INT_NAKINTRPT_SHIFT 13 /**< Shift value for USB_NAKINTRPT */
<> 150:02e0a0aed4ec 2171 #define _USB_DIEP_INT_NAKINTRPT_MASK 0x2000UL /**< Bit mask for USB_NAKINTRPT */
<> 150:02e0a0aed4ec 2172 #define _USB_DIEP_INT_NAKINTRPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_INT */
<> 150:02e0a0aed4ec 2173 #define USB_DIEP_INT_NAKINTRPT_DEFAULT (_USB_DIEP_INT_NAKINTRPT_DEFAULT << 13) /**< Shifted mode DEFAULT for USB_DIEP_INT */
<> 150:02e0a0aed4ec 2174
<> 150:02e0a0aed4ec 2175 /* Bit fields for USB DIEP_TSIZ */
<> 150:02e0a0aed4ec 2176 #define _USB_DIEP_TSIZ_RESETVALUE 0x00000000UL /**< Default value for USB_DIEP_TSIZ */
<> 150:02e0a0aed4ec 2177 #define _USB_DIEP_TSIZ_MASK 0x7FFFFFFFUL /**< Mask for USB_DIEP_TSIZ */
<> 150:02e0a0aed4ec 2178 #define _USB_DIEP_TSIZ_XFERSIZE_SHIFT 0 /**< Shift value for USB_XFERSIZE */
<> 150:02e0a0aed4ec 2179 #define _USB_DIEP_TSIZ_XFERSIZE_MASK 0x7FFFFUL /**< Bit mask for USB_XFERSIZE */
<> 150:02e0a0aed4ec 2180 #define _USB_DIEP_TSIZ_XFERSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_TSIZ */
<> 150:02e0a0aed4ec 2181 #define USB_DIEP_TSIZ_XFERSIZE_DEFAULT (_USB_DIEP_TSIZ_XFERSIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEP_TSIZ */
<> 150:02e0a0aed4ec 2182 #define _USB_DIEP_TSIZ_PKTCNT_SHIFT 19 /**< Shift value for USB_PKTCNT */
<> 150:02e0a0aed4ec 2183 #define _USB_DIEP_TSIZ_PKTCNT_MASK 0x1FF80000UL /**< Bit mask for USB_PKTCNT */
<> 150:02e0a0aed4ec 2184 #define _USB_DIEP_TSIZ_PKTCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_TSIZ */
<> 150:02e0a0aed4ec 2185 #define USB_DIEP_TSIZ_PKTCNT_DEFAULT (_USB_DIEP_TSIZ_PKTCNT_DEFAULT << 19) /**< Shifted mode DEFAULT for USB_DIEP_TSIZ */
<> 150:02e0a0aed4ec 2186 #define _USB_DIEP_TSIZ_MC_SHIFT 29 /**< Shift value for USB_MC */
<> 150:02e0a0aed4ec 2187 #define _USB_DIEP_TSIZ_MC_MASK 0x60000000UL /**< Bit mask for USB_MC */
<> 150:02e0a0aed4ec 2188 #define _USB_DIEP_TSIZ_MC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_TSIZ */
<> 150:02e0a0aed4ec 2189 #define USB_DIEP_TSIZ_MC_DEFAULT (_USB_DIEP_TSIZ_MC_DEFAULT << 29) /**< Shifted mode DEFAULT for USB_DIEP_TSIZ */
<> 150:02e0a0aed4ec 2190
<> 150:02e0a0aed4ec 2191 /* Bit fields for USB DIEP_DMAADDR */
<> 150:02e0a0aed4ec 2192 #define _USB_DIEP_DMAADDR_RESETVALUE 0x00000000UL /**< Default value for USB_DIEP_DMAADDR */
<> 150:02e0a0aed4ec 2193 #define _USB_DIEP_DMAADDR_MASK 0xFFFFFFFFUL /**< Mask for USB_DIEP_DMAADDR */
<> 150:02e0a0aed4ec 2194 #define _USB_DIEP_DMAADDR_DMAADDR_SHIFT 0 /**< Shift value for USB_DMAADDR */
<> 150:02e0a0aed4ec 2195 #define _USB_DIEP_DMAADDR_DMAADDR_MASK 0xFFFFFFFFUL /**< Bit mask for USB_DMAADDR */
<> 150:02e0a0aed4ec 2196 #define _USB_DIEP_DMAADDR_DMAADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_DMAADDR */
<> 150:02e0a0aed4ec 2197 #define USB_DIEP_DMAADDR_DMAADDR_DEFAULT (_USB_DIEP_DMAADDR_DMAADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEP_DMAADDR */
<> 150:02e0a0aed4ec 2198
<> 150:02e0a0aed4ec 2199 /* Bit fields for USB DIEP_TXFSTS */
<> 150:02e0a0aed4ec 2200 #define _USB_DIEP_TXFSTS_RESETVALUE 0x00000200UL /**< Default value for USB_DIEP_TXFSTS */
<> 150:02e0a0aed4ec 2201 #define _USB_DIEP_TXFSTS_MASK 0x0000FFFFUL /**< Mask for USB_DIEP_TXFSTS */
<> 150:02e0a0aed4ec 2202 #define _USB_DIEP_TXFSTS_SPCAVAIL_SHIFT 0 /**< Shift value for USB_SPCAVAIL */
<> 150:02e0a0aed4ec 2203 #define _USB_DIEP_TXFSTS_SPCAVAIL_MASK 0xFFFFUL /**< Bit mask for USB_SPCAVAIL */
<> 150:02e0a0aed4ec 2204 #define _USB_DIEP_TXFSTS_SPCAVAIL_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_DIEP_TXFSTS */
<> 150:02e0a0aed4ec 2205 #define USB_DIEP_TXFSTS_SPCAVAIL_DEFAULT (_USB_DIEP_TXFSTS_SPCAVAIL_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEP_TXFSTS */
<> 150:02e0a0aed4ec 2206
<> 150:02e0a0aed4ec 2207 /* Bit fields for USB DOEP0CTL */
<> 150:02e0a0aed4ec 2208 #define _USB_DOEP0CTL_RESETVALUE 0x00008000UL /**< Default value for USB_DOEP0CTL */
<> 150:02e0a0aed4ec 2209 #define _USB_DOEP0CTL_MASK 0xCC3E8003UL /**< Mask for USB_DOEP0CTL */
<> 150:02e0a0aed4ec 2210 #define _USB_DOEP0CTL_MPS_SHIFT 0 /**< Shift value for USB_MPS */
<> 150:02e0a0aed4ec 2211 #define _USB_DOEP0CTL_MPS_MASK 0x3UL /**< Bit mask for USB_MPS */
<> 150:02e0a0aed4ec 2212 #define _USB_DOEP0CTL_MPS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0CTL */
<> 150:02e0a0aed4ec 2213 #define _USB_DOEP0CTL_MPS_64B 0x00000000UL /**< Mode 64B for USB_DOEP0CTL */
<> 150:02e0a0aed4ec 2214 #define _USB_DOEP0CTL_MPS_32B 0x00000001UL /**< Mode 32B for USB_DOEP0CTL */
<> 150:02e0a0aed4ec 2215 #define _USB_DOEP0CTL_MPS_16B 0x00000002UL /**< Mode 16B for USB_DOEP0CTL */
<> 150:02e0a0aed4ec 2216 #define _USB_DOEP0CTL_MPS_8B 0x00000003UL /**< Mode 8B for USB_DOEP0CTL */
<> 150:02e0a0aed4ec 2217 #define USB_DOEP0CTL_MPS_DEFAULT (_USB_DOEP0CTL_MPS_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DOEP0CTL */
<> 150:02e0a0aed4ec 2218 #define USB_DOEP0CTL_MPS_64B (_USB_DOEP0CTL_MPS_64B << 0) /**< Shifted mode 64B for USB_DOEP0CTL */
<> 150:02e0a0aed4ec 2219 #define USB_DOEP0CTL_MPS_32B (_USB_DOEP0CTL_MPS_32B << 0) /**< Shifted mode 32B for USB_DOEP0CTL */
<> 150:02e0a0aed4ec 2220 #define USB_DOEP0CTL_MPS_16B (_USB_DOEP0CTL_MPS_16B << 0) /**< Shifted mode 16B for USB_DOEP0CTL */
<> 150:02e0a0aed4ec 2221 #define USB_DOEP0CTL_MPS_8B (_USB_DOEP0CTL_MPS_8B << 0) /**< Shifted mode 8B for USB_DOEP0CTL */
<> 150:02e0a0aed4ec 2222 #define USB_DOEP0CTL_USBACTEP (0x1UL << 15) /**< USB Active Endpoint */
<> 150:02e0a0aed4ec 2223 #define _USB_DOEP0CTL_USBACTEP_SHIFT 15 /**< Shift value for USB_USBACTEP */
<> 150:02e0a0aed4ec 2224 #define _USB_DOEP0CTL_USBACTEP_MASK 0x8000UL /**< Bit mask for USB_USBACTEP */
<> 150:02e0a0aed4ec 2225 #define _USB_DOEP0CTL_USBACTEP_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_DOEP0CTL */
<> 150:02e0a0aed4ec 2226 #define USB_DOEP0CTL_USBACTEP_DEFAULT (_USB_DOEP0CTL_USBACTEP_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_DOEP0CTL */
<> 150:02e0a0aed4ec 2227 #define USB_DOEP0CTL_NAKSTS (0x1UL << 17) /**< NAK Status */
<> 150:02e0a0aed4ec 2228 #define _USB_DOEP0CTL_NAKSTS_SHIFT 17 /**< Shift value for USB_NAKSTS */
<> 150:02e0a0aed4ec 2229 #define _USB_DOEP0CTL_NAKSTS_MASK 0x20000UL /**< Bit mask for USB_NAKSTS */
<> 150:02e0a0aed4ec 2230 #define _USB_DOEP0CTL_NAKSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0CTL */
<> 150:02e0a0aed4ec 2231 #define USB_DOEP0CTL_NAKSTS_DEFAULT (_USB_DOEP0CTL_NAKSTS_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_DOEP0CTL */
<> 150:02e0a0aed4ec 2232 #define _USB_DOEP0CTL_EPTYPE_SHIFT 18 /**< Shift value for USB_EPTYPE */
<> 150:02e0a0aed4ec 2233 #define _USB_DOEP0CTL_EPTYPE_MASK 0xC0000UL /**< Bit mask for USB_EPTYPE */
<> 150:02e0a0aed4ec 2234 #define _USB_DOEP0CTL_EPTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0CTL */
<> 150:02e0a0aed4ec 2235 #define USB_DOEP0CTL_EPTYPE_DEFAULT (_USB_DOEP0CTL_EPTYPE_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_DOEP0CTL */
<> 150:02e0a0aed4ec 2236 #define USB_DOEP0CTL_SNP (0x1UL << 20) /**< Snoop Mode */
<> 150:02e0a0aed4ec 2237 #define _USB_DOEP0CTL_SNP_SHIFT 20 /**< Shift value for USB_SNP */
<> 150:02e0a0aed4ec 2238 #define _USB_DOEP0CTL_SNP_MASK 0x100000UL /**< Bit mask for USB_SNP */
<> 150:02e0a0aed4ec 2239 #define _USB_DOEP0CTL_SNP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0CTL */
<> 150:02e0a0aed4ec 2240 #define USB_DOEP0CTL_SNP_DEFAULT (_USB_DOEP0CTL_SNP_DEFAULT << 20) /**< Shifted mode DEFAULT for USB_DOEP0CTL */
<> 150:02e0a0aed4ec 2241 #define USB_DOEP0CTL_STALL (0x1UL << 21) /**< Handshake */
<> 150:02e0a0aed4ec 2242 #define _USB_DOEP0CTL_STALL_SHIFT 21 /**< Shift value for USB_STALL */
<> 150:02e0a0aed4ec 2243 #define _USB_DOEP0CTL_STALL_MASK 0x200000UL /**< Bit mask for USB_STALL */
<> 150:02e0a0aed4ec 2244 #define _USB_DOEP0CTL_STALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0CTL */
<> 150:02e0a0aed4ec 2245 #define USB_DOEP0CTL_STALL_DEFAULT (_USB_DOEP0CTL_STALL_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_DOEP0CTL */
<> 150:02e0a0aed4ec 2246 #define USB_DOEP0CTL_CNAK (0x1UL << 26) /**< Clear NAK */
<> 150:02e0a0aed4ec 2247 #define _USB_DOEP0CTL_CNAK_SHIFT 26 /**< Shift value for USB_CNAK */
<> 150:02e0a0aed4ec 2248 #define _USB_DOEP0CTL_CNAK_MASK 0x4000000UL /**< Bit mask for USB_CNAK */
<> 150:02e0a0aed4ec 2249 #define _USB_DOEP0CTL_CNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0CTL */
<> 150:02e0a0aed4ec 2250 #define USB_DOEP0CTL_CNAK_DEFAULT (_USB_DOEP0CTL_CNAK_DEFAULT << 26) /**< Shifted mode DEFAULT for USB_DOEP0CTL */
<> 150:02e0a0aed4ec 2251 #define USB_DOEP0CTL_SNAK (0x1UL << 27) /**< Set NAK */
<> 150:02e0a0aed4ec 2252 #define _USB_DOEP0CTL_SNAK_SHIFT 27 /**< Shift value for USB_SNAK */
<> 150:02e0a0aed4ec 2253 #define _USB_DOEP0CTL_SNAK_MASK 0x8000000UL /**< Bit mask for USB_SNAK */
<> 150:02e0a0aed4ec 2254 #define _USB_DOEP0CTL_SNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0CTL */
<> 150:02e0a0aed4ec 2255 #define USB_DOEP0CTL_SNAK_DEFAULT (_USB_DOEP0CTL_SNAK_DEFAULT << 27) /**< Shifted mode DEFAULT for USB_DOEP0CTL */
<> 150:02e0a0aed4ec 2256 #define USB_DOEP0CTL_EPDIS (0x1UL << 30) /**< Endpoint Disable */
<> 150:02e0a0aed4ec 2257 #define _USB_DOEP0CTL_EPDIS_SHIFT 30 /**< Shift value for USB_EPDIS */
<> 150:02e0a0aed4ec 2258 #define _USB_DOEP0CTL_EPDIS_MASK 0x40000000UL /**< Bit mask for USB_EPDIS */
<> 150:02e0a0aed4ec 2259 #define _USB_DOEP0CTL_EPDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0CTL */
<> 150:02e0a0aed4ec 2260 #define USB_DOEP0CTL_EPDIS_DEFAULT (_USB_DOEP0CTL_EPDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for USB_DOEP0CTL */
<> 150:02e0a0aed4ec 2261 #define USB_DOEP0CTL_EPENA (0x1UL << 31) /**< Endpoint Enable */
<> 150:02e0a0aed4ec 2262 #define _USB_DOEP0CTL_EPENA_SHIFT 31 /**< Shift value for USB_EPENA */
<> 150:02e0a0aed4ec 2263 #define _USB_DOEP0CTL_EPENA_MASK 0x80000000UL /**< Bit mask for USB_EPENA */
<> 150:02e0a0aed4ec 2264 #define _USB_DOEP0CTL_EPENA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0CTL */
<> 150:02e0a0aed4ec 2265 #define USB_DOEP0CTL_EPENA_DEFAULT (_USB_DOEP0CTL_EPENA_DEFAULT << 31) /**< Shifted mode DEFAULT for USB_DOEP0CTL */
<> 150:02e0a0aed4ec 2266
<> 150:02e0a0aed4ec 2267 /* Bit fields for USB DOEP0INT */
<> 150:02e0a0aed4ec 2268 #define _USB_DOEP0INT_RESETVALUE 0x00000000UL /**< Default value for USB_DOEP0INT */
<> 150:02e0a0aed4ec 2269 #define _USB_DOEP0INT_MASK 0x0000385FUL /**< Mask for USB_DOEP0INT */
<> 150:02e0a0aed4ec 2270 #define USB_DOEP0INT_XFERCOMPL (0x1UL << 0) /**< Transfer Completed Interrupt */
<> 150:02e0a0aed4ec 2271 #define _USB_DOEP0INT_XFERCOMPL_SHIFT 0 /**< Shift value for USB_XFERCOMPL */
<> 150:02e0a0aed4ec 2272 #define _USB_DOEP0INT_XFERCOMPL_MASK 0x1UL /**< Bit mask for USB_XFERCOMPL */
<> 150:02e0a0aed4ec 2273 #define _USB_DOEP0INT_XFERCOMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0INT */
<> 150:02e0a0aed4ec 2274 #define USB_DOEP0INT_XFERCOMPL_DEFAULT (_USB_DOEP0INT_XFERCOMPL_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DOEP0INT */
<> 150:02e0a0aed4ec 2275 #define USB_DOEP0INT_EPDISBLD (0x1UL << 1) /**< Endpoint Disabled Interrupt */
<> 150:02e0a0aed4ec 2276 #define _USB_DOEP0INT_EPDISBLD_SHIFT 1 /**< Shift value for USB_EPDISBLD */
<> 150:02e0a0aed4ec 2277 #define _USB_DOEP0INT_EPDISBLD_MASK 0x2UL /**< Bit mask for USB_EPDISBLD */
<> 150:02e0a0aed4ec 2278 #define _USB_DOEP0INT_EPDISBLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0INT */
<> 150:02e0a0aed4ec 2279 #define USB_DOEP0INT_EPDISBLD_DEFAULT (_USB_DOEP0INT_EPDISBLD_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_DOEP0INT */
<> 150:02e0a0aed4ec 2280 #define USB_DOEP0INT_AHBERR (0x1UL << 2) /**< AHB Error */
<> 150:02e0a0aed4ec 2281 #define _USB_DOEP0INT_AHBERR_SHIFT 2 /**< Shift value for USB_AHBERR */
<> 150:02e0a0aed4ec 2282 #define _USB_DOEP0INT_AHBERR_MASK 0x4UL /**< Bit mask for USB_AHBERR */
<> 150:02e0a0aed4ec 2283 #define _USB_DOEP0INT_AHBERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0INT */
<> 150:02e0a0aed4ec 2284 #define USB_DOEP0INT_AHBERR_DEFAULT (_USB_DOEP0INT_AHBERR_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_DOEP0INT */
<> 150:02e0a0aed4ec 2285 #define USB_DOEP0INT_SETUP (0x1UL << 3) /**< Setup Phase Done */
<> 150:02e0a0aed4ec 2286 #define _USB_DOEP0INT_SETUP_SHIFT 3 /**< Shift value for USB_SETUP */
<> 150:02e0a0aed4ec 2287 #define _USB_DOEP0INT_SETUP_MASK 0x8UL /**< Bit mask for USB_SETUP */
<> 150:02e0a0aed4ec 2288 #define _USB_DOEP0INT_SETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0INT */
<> 150:02e0a0aed4ec 2289 #define USB_DOEP0INT_SETUP_DEFAULT (_USB_DOEP0INT_SETUP_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_DOEP0INT */
<> 150:02e0a0aed4ec 2290 #define USB_DOEP0INT_OUTTKNEPDIS (0x1UL << 4) /**< OUT Token Received When Endpoint Disabled */
<> 150:02e0a0aed4ec 2291 #define _USB_DOEP0INT_OUTTKNEPDIS_SHIFT 4 /**< Shift value for USB_OUTTKNEPDIS */
<> 150:02e0a0aed4ec 2292 #define _USB_DOEP0INT_OUTTKNEPDIS_MASK 0x10UL /**< Bit mask for USB_OUTTKNEPDIS */
<> 150:02e0a0aed4ec 2293 #define _USB_DOEP0INT_OUTTKNEPDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0INT */
<> 150:02e0a0aed4ec 2294 #define USB_DOEP0INT_OUTTKNEPDIS_DEFAULT (_USB_DOEP0INT_OUTTKNEPDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_DOEP0INT */
<> 150:02e0a0aed4ec 2295 #define USB_DOEP0INT_BACK2BACKSETUP (0x1UL << 6) /**< Back-to-Back SETUP Packets Received */
<> 150:02e0a0aed4ec 2296 #define _USB_DOEP0INT_BACK2BACKSETUP_SHIFT 6 /**< Shift value for USB_BACK2BACKSETUP */
<> 150:02e0a0aed4ec 2297 #define _USB_DOEP0INT_BACK2BACKSETUP_MASK 0x40UL /**< Bit mask for USB_BACK2BACKSETUP */
<> 150:02e0a0aed4ec 2298 #define _USB_DOEP0INT_BACK2BACKSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0INT */
<> 150:02e0a0aed4ec 2299 #define USB_DOEP0INT_BACK2BACKSETUP_DEFAULT (_USB_DOEP0INT_BACK2BACKSETUP_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_DOEP0INT */
<> 150:02e0a0aed4ec 2300 #define USB_DOEP0INT_PKTDRPSTS (0x1UL << 11) /**< Packet Drop Status */
<> 150:02e0a0aed4ec 2301 #define _USB_DOEP0INT_PKTDRPSTS_SHIFT 11 /**< Shift value for USB_PKTDRPSTS */
<> 150:02e0a0aed4ec 2302 #define _USB_DOEP0INT_PKTDRPSTS_MASK 0x800UL /**< Bit mask for USB_PKTDRPSTS */
<> 150:02e0a0aed4ec 2303 #define _USB_DOEP0INT_PKTDRPSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0INT */
<> 150:02e0a0aed4ec 2304 #define USB_DOEP0INT_PKTDRPSTS_DEFAULT (_USB_DOEP0INT_PKTDRPSTS_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_DOEP0INT */
<> 150:02e0a0aed4ec 2305 #define USB_DOEP0INT_BBLEERR (0x1UL << 12) /**< NAK Interrupt */
<> 150:02e0a0aed4ec 2306 #define _USB_DOEP0INT_BBLEERR_SHIFT 12 /**< Shift value for USB_BBLEERR */
<> 150:02e0a0aed4ec 2307 #define _USB_DOEP0INT_BBLEERR_MASK 0x1000UL /**< Bit mask for USB_BBLEERR */
<> 150:02e0a0aed4ec 2308 #define _USB_DOEP0INT_BBLEERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0INT */
<> 150:02e0a0aed4ec 2309 #define USB_DOEP0INT_BBLEERR_DEFAULT (_USB_DOEP0INT_BBLEERR_DEFAULT << 12) /**< Shifted mode DEFAULT for USB_DOEP0INT */
<> 150:02e0a0aed4ec 2310 #define USB_DOEP0INT_NAKINTRPT (0x1UL << 13) /**< NAK Interrupt */
<> 150:02e0a0aed4ec 2311 #define _USB_DOEP0INT_NAKINTRPT_SHIFT 13 /**< Shift value for USB_NAKINTRPT */
<> 150:02e0a0aed4ec 2312 #define _USB_DOEP0INT_NAKINTRPT_MASK 0x2000UL /**< Bit mask for USB_NAKINTRPT */
<> 150:02e0a0aed4ec 2313 #define _USB_DOEP0INT_NAKINTRPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0INT */
<> 150:02e0a0aed4ec 2314 #define USB_DOEP0INT_NAKINTRPT_DEFAULT (_USB_DOEP0INT_NAKINTRPT_DEFAULT << 13) /**< Shifted mode DEFAULT for USB_DOEP0INT */
<> 150:02e0a0aed4ec 2315
<> 150:02e0a0aed4ec 2316 /* Bit fields for USB DOEP0TSIZ */
<> 150:02e0a0aed4ec 2317 #define _USB_DOEP0TSIZ_RESETVALUE 0x00000000UL /**< Default value for USB_DOEP0TSIZ */
<> 150:02e0a0aed4ec 2318 #define _USB_DOEP0TSIZ_MASK 0x6008007FUL /**< Mask for USB_DOEP0TSIZ */
<> 150:02e0a0aed4ec 2319 #define _USB_DOEP0TSIZ_XFERSIZE_SHIFT 0 /**< Shift value for USB_XFERSIZE */
<> 150:02e0a0aed4ec 2320 #define _USB_DOEP0TSIZ_XFERSIZE_MASK 0x7FUL /**< Bit mask for USB_XFERSIZE */
<> 150:02e0a0aed4ec 2321 #define _USB_DOEP0TSIZ_XFERSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0TSIZ */
<> 150:02e0a0aed4ec 2322 #define USB_DOEP0TSIZ_XFERSIZE_DEFAULT (_USB_DOEP0TSIZ_XFERSIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DOEP0TSIZ */
<> 150:02e0a0aed4ec 2323 #define USB_DOEP0TSIZ_PKTCNT (0x1UL << 19) /**< Packet Count */
<> 150:02e0a0aed4ec 2324 #define _USB_DOEP0TSIZ_PKTCNT_SHIFT 19 /**< Shift value for USB_PKTCNT */
<> 150:02e0a0aed4ec 2325 #define _USB_DOEP0TSIZ_PKTCNT_MASK 0x80000UL /**< Bit mask for USB_PKTCNT */
<> 150:02e0a0aed4ec 2326 #define _USB_DOEP0TSIZ_PKTCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0TSIZ */
<> 150:02e0a0aed4ec 2327 #define USB_DOEP0TSIZ_PKTCNT_DEFAULT (_USB_DOEP0TSIZ_PKTCNT_DEFAULT << 19) /**< Shifted mode DEFAULT for USB_DOEP0TSIZ */
<> 150:02e0a0aed4ec 2328 #define _USB_DOEP0TSIZ_SUPCNT_SHIFT 29 /**< Shift value for USB_SUPCNT */
<> 150:02e0a0aed4ec 2329 #define _USB_DOEP0TSIZ_SUPCNT_MASK 0x60000000UL /**< Bit mask for USB_SUPCNT */
<> 150:02e0a0aed4ec 2330 #define _USB_DOEP0TSIZ_SUPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0TSIZ */
<> 150:02e0a0aed4ec 2331 #define USB_DOEP0TSIZ_SUPCNT_DEFAULT (_USB_DOEP0TSIZ_SUPCNT_DEFAULT << 29) /**< Shifted mode DEFAULT for USB_DOEP0TSIZ */
<> 150:02e0a0aed4ec 2332
<> 150:02e0a0aed4ec 2333 /* Bit fields for USB DOEP0DMAADDR */
<> 150:02e0a0aed4ec 2334 #define _USB_DOEP0DMAADDR_RESETVALUE 0x00000000UL /**< Default value for USB_DOEP0DMAADDR */
<> 150:02e0a0aed4ec 2335 #define _USB_DOEP0DMAADDR_MASK 0xFFFFFFFFUL /**< Mask for USB_DOEP0DMAADDR */
<> 150:02e0a0aed4ec 2336 #define _USB_DOEP0DMAADDR_DOEP0DMAADDR_SHIFT 0 /**< Shift value for USB_DOEP0DMAADDR */
<> 150:02e0a0aed4ec 2337 #define _USB_DOEP0DMAADDR_DOEP0DMAADDR_MASK 0xFFFFFFFFUL /**< Bit mask for USB_DOEP0DMAADDR */
<> 150:02e0a0aed4ec 2338 #define _USB_DOEP0DMAADDR_DOEP0DMAADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0DMAADDR */
<> 150:02e0a0aed4ec 2339 #define USB_DOEP0DMAADDR_DOEP0DMAADDR_DEFAULT (_USB_DOEP0DMAADDR_DOEP0DMAADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DOEP0DMAADDR */
<> 150:02e0a0aed4ec 2340
<> 150:02e0a0aed4ec 2341 /* Bit fields for USB DOEP_CTL */
<> 150:02e0a0aed4ec 2342 #define _USB_DOEP_CTL_RESETVALUE 0x00000000UL /**< Default value for USB_DOEP_CTL */
<> 150:02e0a0aed4ec 2343 #define _USB_DOEP_CTL_MASK 0xFC3F87FFUL /**< Mask for USB_DOEP_CTL */
<> 150:02e0a0aed4ec 2344 #define _USB_DOEP_CTL_MPS_SHIFT 0 /**< Shift value for USB_MPS */
<> 150:02e0a0aed4ec 2345 #define _USB_DOEP_CTL_MPS_MASK 0x7FFUL /**< Bit mask for USB_MPS */
<> 150:02e0a0aed4ec 2346 #define _USB_DOEP_CTL_MPS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */
<> 150:02e0a0aed4ec 2347 #define USB_DOEP_CTL_MPS_DEFAULT (_USB_DOEP_CTL_MPS_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DOEP_CTL */
<> 150:02e0a0aed4ec 2348 #define USB_DOEP_CTL_USBACTEP (0x1UL << 15) /**< USB Active Endpoint */
<> 150:02e0a0aed4ec 2349 #define _USB_DOEP_CTL_USBACTEP_SHIFT 15 /**< Shift value for USB_USBACTEP */
<> 150:02e0a0aed4ec 2350 #define _USB_DOEP_CTL_USBACTEP_MASK 0x8000UL /**< Bit mask for USB_USBACTEP */
<> 150:02e0a0aed4ec 2351 #define _USB_DOEP_CTL_USBACTEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */
<> 150:02e0a0aed4ec 2352 #define USB_DOEP_CTL_USBACTEP_DEFAULT (_USB_DOEP_CTL_USBACTEP_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_DOEP_CTL */
<> 150:02e0a0aed4ec 2353 #define USB_DOEP_CTL_DPIDEOF (0x1UL << 16) /**< Endpoint Data PID / Even-odd Frame */
<> 150:02e0a0aed4ec 2354 #define _USB_DOEP_CTL_DPIDEOF_SHIFT 16 /**< Shift value for USB_DPIDEOF */
<> 150:02e0a0aed4ec 2355 #define _USB_DOEP_CTL_DPIDEOF_MASK 0x10000UL /**< Bit mask for USB_DPIDEOF */
<> 150:02e0a0aed4ec 2356 #define _USB_DOEP_CTL_DPIDEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */
<> 150:02e0a0aed4ec 2357 #define _USB_DOEP_CTL_DPIDEOF_DATA0EVEN 0x00000000UL /**< Mode DATA0EVEN for USB_DOEP_CTL */
<> 150:02e0a0aed4ec 2358 #define _USB_DOEP_CTL_DPIDEOF_DATA1ODD 0x00000001UL /**< Mode DATA1ODD for USB_DOEP_CTL */
<> 150:02e0a0aed4ec 2359 #define USB_DOEP_CTL_DPIDEOF_DEFAULT (_USB_DOEP_CTL_DPIDEOF_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_DOEP_CTL */
<> 150:02e0a0aed4ec 2360 #define USB_DOEP_CTL_DPIDEOF_DATA0EVEN (_USB_DOEP_CTL_DPIDEOF_DATA0EVEN << 16) /**< Shifted mode DATA0EVEN for USB_DOEP_CTL */
<> 150:02e0a0aed4ec 2361 #define USB_DOEP_CTL_DPIDEOF_DATA1ODD (_USB_DOEP_CTL_DPIDEOF_DATA1ODD << 16) /**< Shifted mode DATA1ODD for USB_DOEP_CTL */
<> 150:02e0a0aed4ec 2362 #define USB_DOEP_CTL_NAKSTS (0x1UL << 17) /**< NAK Status */
<> 150:02e0a0aed4ec 2363 #define _USB_DOEP_CTL_NAKSTS_SHIFT 17 /**< Shift value for USB_NAKSTS */
<> 150:02e0a0aed4ec 2364 #define _USB_DOEP_CTL_NAKSTS_MASK 0x20000UL /**< Bit mask for USB_NAKSTS */
<> 150:02e0a0aed4ec 2365 #define _USB_DOEP_CTL_NAKSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */
<> 150:02e0a0aed4ec 2366 #define USB_DOEP_CTL_NAKSTS_DEFAULT (_USB_DOEP_CTL_NAKSTS_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_DOEP_CTL */
<> 150:02e0a0aed4ec 2367 #define _USB_DOEP_CTL_EPTYPE_SHIFT 18 /**< Shift value for USB_EPTYPE */
<> 150:02e0a0aed4ec 2368 #define _USB_DOEP_CTL_EPTYPE_MASK 0xC0000UL /**< Bit mask for USB_EPTYPE */
<> 150:02e0a0aed4ec 2369 #define _USB_DOEP_CTL_EPTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */
<> 150:02e0a0aed4ec 2370 #define _USB_DOEP_CTL_EPTYPE_CONTROL 0x00000000UL /**< Mode CONTROL for USB_DOEP_CTL */
<> 150:02e0a0aed4ec 2371 #define _USB_DOEP_CTL_EPTYPE_ISO 0x00000001UL /**< Mode ISO for USB_DOEP_CTL */
<> 150:02e0a0aed4ec 2372 #define _USB_DOEP_CTL_EPTYPE_BULK 0x00000002UL /**< Mode BULK for USB_DOEP_CTL */
<> 150:02e0a0aed4ec 2373 #define _USB_DOEP_CTL_EPTYPE_INT 0x00000003UL /**< Mode INT for USB_DOEP_CTL */
<> 150:02e0a0aed4ec 2374 #define USB_DOEP_CTL_EPTYPE_DEFAULT (_USB_DOEP_CTL_EPTYPE_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_DOEP_CTL */
<> 150:02e0a0aed4ec 2375 #define USB_DOEP_CTL_EPTYPE_CONTROL (_USB_DOEP_CTL_EPTYPE_CONTROL << 18) /**< Shifted mode CONTROL for USB_DOEP_CTL */
<> 150:02e0a0aed4ec 2376 #define USB_DOEP_CTL_EPTYPE_ISO (_USB_DOEP_CTL_EPTYPE_ISO << 18) /**< Shifted mode ISO for USB_DOEP_CTL */
<> 150:02e0a0aed4ec 2377 #define USB_DOEP_CTL_EPTYPE_BULK (_USB_DOEP_CTL_EPTYPE_BULK << 18) /**< Shifted mode BULK for USB_DOEP_CTL */
<> 150:02e0a0aed4ec 2378 #define USB_DOEP_CTL_EPTYPE_INT (_USB_DOEP_CTL_EPTYPE_INT << 18) /**< Shifted mode INT for USB_DOEP_CTL */
<> 150:02e0a0aed4ec 2379 #define USB_DOEP_CTL_SNP (0x1UL << 20) /**< Snoop Mode */
<> 150:02e0a0aed4ec 2380 #define _USB_DOEP_CTL_SNP_SHIFT 20 /**< Shift value for USB_SNP */
<> 150:02e0a0aed4ec 2381 #define _USB_DOEP_CTL_SNP_MASK 0x100000UL /**< Bit mask for USB_SNP */
<> 150:02e0a0aed4ec 2382 #define _USB_DOEP_CTL_SNP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */
<> 150:02e0a0aed4ec 2383 #define USB_DOEP_CTL_SNP_DEFAULT (_USB_DOEP_CTL_SNP_DEFAULT << 20) /**< Shifted mode DEFAULT for USB_DOEP_CTL */
<> 150:02e0a0aed4ec 2384 #define USB_DOEP_CTL_STALL (0x1UL << 21) /**< STALL Handshake */
<> 150:02e0a0aed4ec 2385 #define _USB_DOEP_CTL_STALL_SHIFT 21 /**< Shift value for USB_STALL */
<> 150:02e0a0aed4ec 2386 #define _USB_DOEP_CTL_STALL_MASK 0x200000UL /**< Bit mask for USB_STALL */
<> 150:02e0a0aed4ec 2387 #define _USB_DOEP_CTL_STALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */
<> 150:02e0a0aed4ec 2388 #define USB_DOEP_CTL_STALL_DEFAULT (_USB_DOEP_CTL_STALL_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_DOEP_CTL */
<> 150:02e0a0aed4ec 2389 #define USB_DOEP_CTL_CNAK (0x1UL << 26) /**< Clear NAK */
<> 150:02e0a0aed4ec 2390 #define _USB_DOEP_CTL_CNAK_SHIFT 26 /**< Shift value for USB_CNAK */
<> 150:02e0a0aed4ec 2391 #define _USB_DOEP_CTL_CNAK_MASK 0x4000000UL /**< Bit mask for USB_CNAK */
<> 150:02e0a0aed4ec 2392 #define _USB_DOEP_CTL_CNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */
<> 150:02e0a0aed4ec 2393 #define USB_DOEP_CTL_CNAK_DEFAULT (_USB_DOEP_CTL_CNAK_DEFAULT << 26) /**< Shifted mode DEFAULT for USB_DOEP_CTL */
<> 150:02e0a0aed4ec 2394 #define USB_DOEP_CTL_SNAK (0x1UL << 27) /**< Set NAK */
<> 150:02e0a0aed4ec 2395 #define _USB_DOEP_CTL_SNAK_SHIFT 27 /**< Shift value for USB_SNAK */
<> 150:02e0a0aed4ec 2396 #define _USB_DOEP_CTL_SNAK_MASK 0x8000000UL /**< Bit mask for USB_SNAK */
<> 150:02e0a0aed4ec 2397 #define _USB_DOEP_CTL_SNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */
<> 150:02e0a0aed4ec 2398 #define USB_DOEP_CTL_SNAK_DEFAULT (_USB_DOEP_CTL_SNAK_DEFAULT << 27) /**< Shifted mode DEFAULT for USB_DOEP_CTL */
<> 150:02e0a0aed4ec 2399 #define USB_DOEP_CTL_SETD0PIDEF (0x1UL << 28) /**< Set DATA0 PID / Even Frame */
<> 150:02e0a0aed4ec 2400 #define _USB_DOEP_CTL_SETD0PIDEF_SHIFT 28 /**< Shift value for USB_SETD0PIDEF */
<> 150:02e0a0aed4ec 2401 #define _USB_DOEP_CTL_SETD0PIDEF_MASK 0x10000000UL /**< Bit mask for USB_SETD0PIDEF */
<> 150:02e0a0aed4ec 2402 #define _USB_DOEP_CTL_SETD0PIDEF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */
<> 150:02e0a0aed4ec 2403 #define USB_DOEP_CTL_SETD0PIDEF_DEFAULT (_USB_DOEP_CTL_SETD0PIDEF_DEFAULT << 28) /**< Shifted mode DEFAULT for USB_DOEP_CTL */
<> 150:02e0a0aed4ec 2404 #define USB_DOEP_CTL_SETD1PIDOF (0x1UL << 29) /**< Set DATA1 PID / Odd Frame */
<> 150:02e0a0aed4ec 2405 #define _USB_DOEP_CTL_SETD1PIDOF_SHIFT 29 /**< Shift value for USB_SETD1PIDOF */
<> 150:02e0a0aed4ec 2406 #define _USB_DOEP_CTL_SETD1PIDOF_MASK 0x20000000UL /**< Bit mask for USB_SETD1PIDOF */
<> 150:02e0a0aed4ec 2407 #define _USB_DOEP_CTL_SETD1PIDOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */
<> 150:02e0a0aed4ec 2408 #define USB_DOEP_CTL_SETD1PIDOF_DEFAULT (_USB_DOEP_CTL_SETD1PIDOF_DEFAULT << 29) /**< Shifted mode DEFAULT for USB_DOEP_CTL */
<> 150:02e0a0aed4ec 2409 #define USB_DOEP_CTL_EPDIS (0x1UL << 30) /**< Endpoint Disable */
<> 150:02e0a0aed4ec 2410 #define _USB_DOEP_CTL_EPDIS_SHIFT 30 /**< Shift value for USB_EPDIS */
<> 150:02e0a0aed4ec 2411 #define _USB_DOEP_CTL_EPDIS_MASK 0x40000000UL /**< Bit mask for USB_EPDIS */
<> 150:02e0a0aed4ec 2412 #define _USB_DOEP_CTL_EPDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */
<> 150:02e0a0aed4ec 2413 #define USB_DOEP_CTL_EPDIS_DEFAULT (_USB_DOEP_CTL_EPDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for USB_DOEP_CTL */
<> 150:02e0a0aed4ec 2414 #define USB_DOEP_CTL_EPENA (0x1UL << 31) /**< Endpoint Enable */
<> 150:02e0a0aed4ec 2415 #define _USB_DOEP_CTL_EPENA_SHIFT 31 /**< Shift value for USB_EPENA */
<> 150:02e0a0aed4ec 2416 #define _USB_DOEP_CTL_EPENA_MASK 0x80000000UL /**< Bit mask for USB_EPENA */
<> 150:02e0a0aed4ec 2417 #define _USB_DOEP_CTL_EPENA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */
<> 150:02e0a0aed4ec 2418 #define USB_DOEP_CTL_EPENA_DEFAULT (_USB_DOEP_CTL_EPENA_DEFAULT << 31) /**< Shifted mode DEFAULT for USB_DOEP_CTL */
<> 150:02e0a0aed4ec 2419
<> 150:02e0a0aed4ec 2420 /* Bit fields for USB DOEP_INT */
<> 150:02e0a0aed4ec 2421 #define _USB_DOEP_INT_RESETVALUE 0x00000000UL /**< Default value for USB_DOEP_INT */
<> 150:02e0a0aed4ec 2422 #define _USB_DOEP_INT_MASK 0x0000385FUL /**< Mask for USB_DOEP_INT */
<> 150:02e0a0aed4ec 2423 #define USB_DOEP_INT_XFERCOMPL (0x1UL << 0) /**< Transfer Completed Interrupt */
<> 150:02e0a0aed4ec 2424 #define _USB_DOEP_INT_XFERCOMPL_SHIFT 0 /**< Shift value for USB_XFERCOMPL */
<> 150:02e0a0aed4ec 2425 #define _USB_DOEP_INT_XFERCOMPL_MASK 0x1UL /**< Bit mask for USB_XFERCOMPL */
<> 150:02e0a0aed4ec 2426 #define _USB_DOEP_INT_XFERCOMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_INT */
<> 150:02e0a0aed4ec 2427 #define USB_DOEP_INT_XFERCOMPL_DEFAULT (_USB_DOEP_INT_XFERCOMPL_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DOEP_INT */
<> 150:02e0a0aed4ec 2428 #define USB_DOEP_INT_EPDISBLD (0x1UL << 1) /**< Endpoint Disabled Interrupt */
<> 150:02e0a0aed4ec 2429 #define _USB_DOEP_INT_EPDISBLD_SHIFT 1 /**< Shift value for USB_EPDISBLD */
<> 150:02e0a0aed4ec 2430 #define _USB_DOEP_INT_EPDISBLD_MASK 0x2UL /**< Bit mask for USB_EPDISBLD */
<> 150:02e0a0aed4ec 2431 #define _USB_DOEP_INT_EPDISBLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_INT */
<> 150:02e0a0aed4ec 2432 #define USB_DOEP_INT_EPDISBLD_DEFAULT (_USB_DOEP_INT_EPDISBLD_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_DOEP_INT */
<> 150:02e0a0aed4ec 2433 #define USB_DOEP_INT_AHBERR (0x1UL << 2) /**< AHB Error */
<> 150:02e0a0aed4ec 2434 #define _USB_DOEP_INT_AHBERR_SHIFT 2 /**< Shift value for USB_AHBERR */
<> 150:02e0a0aed4ec 2435 #define _USB_DOEP_INT_AHBERR_MASK 0x4UL /**< Bit mask for USB_AHBERR */
<> 150:02e0a0aed4ec 2436 #define _USB_DOEP_INT_AHBERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_INT */
<> 150:02e0a0aed4ec 2437 #define USB_DOEP_INT_AHBERR_DEFAULT (_USB_DOEP_INT_AHBERR_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_DOEP_INT */
<> 150:02e0a0aed4ec 2438 #define USB_DOEP_INT_SETUP (0x1UL << 3) /**< Setup Phase Done */
<> 150:02e0a0aed4ec 2439 #define _USB_DOEP_INT_SETUP_SHIFT 3 /**< Shift value for USB_SETUP */
<> 150:02e0a0aed4ec 2440 #define _USB_DOEP_INT_SETUP_MASK 0x8UL /**< Bit mask for USB_SETUP */
<> 150:02e0a0aed4ec 2441 #define _USB_DOEP_INT_SETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_INT */
<> 150:02e0a0aed4ec 2442 #define USB_DOEP_INT_SETUP_DEFAULT (_USB_DOEP_INT_SETUP_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_DOEP_INT */
<> 150:02e0a0aed4ec 2443 #define USB_DOEP_INT_OUTTKNEPDIS (0x1UL << 4) /**< OUT Token Received When Endpoint Disabled */
<> 150:02e0a0aed4ec 2444 #define _USB_DOEP_INT_OUTTKNEPDIS_SHIFT 4 /**< Shift value for USB_OUTTKNEPDIS */
<> 150:02e0a0aed4ec 2445 #define _USB_DOEP_INT_OUTTKNEPDIS_MASK 0x10UL /**< Bit mask for USB_OUTTKNEPDIS */
<> 150:02e0a0aed4ec 2446 #define _USB_DOEP_INT_OUTTKNEPDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_INT */
<> 150:02e0a0aed4ec 2447 #define USB_DOEP_INT_OUTTKNEPDIS_DEFAULT (_USB_DOEP_INT_OUTTKNEPDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_DOEP_INT */
<> 150:02e0a0aed4ec 2448 #define USB_DOEP_INT_BACK2BACKSETUP (0x1UL << 6) /**< Back-to-Back SETUP Packets Received */
<> 150:02e0a0aed4ec 2449 #define _USB_DOEP_INT_BACK2BACKSETUP_SHIFT 6 /**< Shift value for USB_BACK2BACKSETUP */
<> 150:02e0a0aed4ec 2450 #define _USB_DOEP_INT_BACK2BACKSETUP_MASK 0x40UL /**< Bit mask for USB_BACK2BACKSETUP */
<> 150:02e0a0aed4ec 2451 #define _USB_DOEP_INT_BACK2BACKSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_INT */
<> 150:02e0a0aed4ec 2452 #define USB_DOEP_INT_BACK2BACKSETUP_DEFAULT (_USB_DOEP_INT_BACK2BACKSETUP_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_DOEP_INT */
<> 150:02e0a0aed4ec 2453 #define USB_DOEP_INT_PKTDRPSTS (0x1UL << 11) /**< Packet Drop Status */
<> 150:02e0a0aed4ec 2454 #define _USB_DOEP_INT_PKTDRPSTS_SHIFT 11 /**< Shift value for USB_PKTDRPSTS */
<> 150:02e0a0aed4ec 2455 #define _USB_DOEP_INT_PKTDRPSTS_MASK 0x800UL /**< Bit mask for USB_PKTDRPSTS */
<> 150:02e0a0aed4ec 2456 #define _USB_DOEP_INT_PKTDRPSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_INT */
<> 150:02e0a0aed4ec 2457 #define USB_DOEP_INT_PKTDRPSTS_DEFAULT (_USB_DOEP_INT_PKTDRPSTS_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_DOEP_INT */
<> 150:02e0a0aed4ec 2458 #define USB_DOEP_INT_BBLEERR (0x1UL << 12) /**< Babble Error */
<> 150:02e0a0aed4ec 2459 #define _USB_DOEP_INT_BBLEERR_SHIFT 12 /**< Shift value for USB_BBLEERR */
<> 150:02e0a0aed4ec 2460 #define _USB_DOEP_INT_BBLEERR_MASK 0x1000UL /**< Bit mask for USB_BBLEERR */
<> 150:02e0a0aed4ec 2461 #define _USB_DOEP_INT_BBLEERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_INT */
<> 150:02e0a0aed4ec 2462 #define USB_DOEP_INT_BBLEERR_DEFAULT (_USB_DOEP_INT_BBLEERR_DEFAULT << 12) /**< Shifted mode DEFAULT for USB_DOEP_INT */
<> 150:02e0a0aed4ec 2463 #define USB_DOEP_INT_NAKINTRPT (0x1UL << 13) /**< NAK Interrupt */
<> 150:02e0a0aed4ec 2464 #define _USB_DOEP_INT_NAKINTRPT_SHIFT 13 /**< Shift value for USB_NAKINTRPT */
<> 150:02e0a0aed4ec 2465 #define _USB_DOEP_INT_NAKINTRPT_MASK 0x2000UL /**< Bit mask for USB_NAKINTRPT */
<> 150:02e0a0aed4ec 2466 #define _USB_DOEP_INT_NAKINTRPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_INT */
<> 150:02e0a0aed4ec 2467 #define USB_DOEP_INT_NAKINTRPT_DEFAULT (_USB_DOEP_INT_NAKINTRPT_DEFAULT << 13) /**< Shifted mode DEFAULT for USB_DOEP_INT */
<> 150:02e0a0aed4ec 2468
<> 150:02e0a0aed4ec 2469 /* Bit fields for USB DOEP_TSIZ */
<> 150:02e0a0aed4ec 2470 #define _USB_DOEP_TSIZ_RESETVALUE 0x00000000UL /**< Default value for USB_DOEP_TSIZ */
<> 150:02e0a0aed4ec 2471 #define _USB_DOEP_TSIZ_MASK 0x7FFFFFFFUL /**< Mask for USB_DOEP_TSIZ */
<> 150:02e0a0aed4ec 2472 #define _USB_DOEP_TSIZ_XFERSIZE_SHIFT 0 /**< Shift value for USB_XFERSIZE */
<> 150:02e0a0aed4ec 2473 #define _USB_DOEP_TSIZ_XFERSIZE_MASK 0x7FFFFUL /**< Bit mask for USB_XFERSIZE */
<> 150:02e0a0aed4ec 2474 #define _USB_DOEP_TSIZ_XFERSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_TSIZ */
<> 150:02e0a0aed4ec 2475 #define USB_DOEP_TSIZ_XFERSIZE_DEFAULT (_USB_DOEP_TSIZ_XFERSIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DOEP_TSIZ */
<> 150:02e0a0aed4ec 2476 #define _USB_DOEP_TSIZ_PKTCNT_SHIFT 19 /**< Shift value for USB_PKTCNT */
<> 150:02e0a0aed4ec 2477 #define _USB_DOEP_TSIZ_PKTCNT_MASK 0x1FF80000UL /**< Bit mask for USB_PKTCNT */
<> 150:02e0a0aed4ec 2478 #define _USB_DOEP_TSIZ_PKTCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_TSIZ */
<> 150:02e0a0aed4ec 2479 #define USB_DOEP_TSIZ_PKTCNT_DEFAULT (_USB_DOEP_TSIZ_PKTCNT_DEFAULT << 19) /**< Shifted mode DEFAULT for USB_DOEP_TSIZ */
<> 150:02e0a0aed4ec 2480 #define _USB_DOEP_TSIZ_RXDPIDSUPCNT_SHIFT 29 /**< Shift value for USB_RXDPIDSUPCNT */
<> 150:02e0a0aed4ec 2481 #define _USB_DOEP_TSIZ_RXDPIDSUPCNT_MASK 0x60000000UL /**< Bit mask for USB_RXDPIDSUPCNT */
<> 150:02e0a0aed4ec 2482 #define _USB_DOEP_TSIZ_RXDPIDSUPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_TSIZ */
<> 150:02e0a0aed4ec 2483 #define _USB_DOEP_TSIZ_RXDPIDSUPCNT_DATA0 0x00000000UL /**< Mode DATA0 for USB_DOEP_TSIZ */
<> 150:02e0a0aed4ec 2484 #define _USB_DOEP_TSIZ_RXDPIDSUPCNT_DATA2 0x00000001UL /**< Mode DATA2 for USB_DOEP_TSIZ */
<> 150:02e0a0aed4ec 2485 #define _USB_DOEP_TSIZ_RXDPIDSUPCNT_DATA1 0x00000002UL /**< Mode DATA1 for USB_DOEP_TSIZ */
<> 150:02e0a0aed4ec 2486 #define _USB_DOEP_TSIZ_RXDPIDSUPCNT_MDATA 0x00000003UL /**< Mode MDATA for USB_DOEP_TSIZ */
<> 150:02e0a0aed4ec 2487 #define USB_DOEP_TSIZ_RXDPIDSUPCNT_DEFAULT (_USB_DOEP_TSIZ_RXDPIDSUPCNT_DEFAULT << 29) /**< Shifted mode DEFAULT for USB_DOEP_TSIZ */
<> 150:02e0a0aed4ec 2488 #define USB_DOEP_TSIZ_RXDPIDSUPCNT_DATA0 (_USB_DOEP_TSIZ_RXDPIDSUPCNT_DATA0 << 29) /**< Shifted mode DATA0 for USB_DOEP_TSIZ */
<> 150:02e0a0aed4ec 2489 #define USB_DOEP_TSIZ_RXDPIDSUPCNT_DATA2 (_USB_DOEP_TSIZ_RXDPIDSUPCNT_DATA2 << 29) /**< Shifted mode DATA2 for USB_DOEP_TSIZ */
<> 150:02e0a0aed4ec 2490 #define USB_DOEP_TSIZ_RXDPIDSUPCNT_DATA1 (_USB_DOEP_TSIZ_RXDPIDSUPCNT_DATA1 << 29) /**< Shifted mode DATA1 for USB_DOEP_TSIZ */
<> 150:02e0a0aed4ec 2491 #define USB_DOEP_TSIZ_RXDPIDSUPCNT_MDATA (_USB_DOEP_TSIZ_RXDPIDSUPCNT_MDATA << 29) /**< Shifted mode MDATA for USB_DOEP_TSIZ */
<> 150:02e0a0aed4ec 2492
<> 150:02e0a0aed4ec 2493 /* Bit fields for USB DOEP_DMAADDR */
<> 150:02e0a0aed4ec 2494 #define _USB_DOEP_DMAADDR_RESETVALUE 0x00000000UL /**< Default value for USB_DOEP_DMAADDR */
<> 150:02e0a0aed4ec 2495 #define _USB_DOEP_DMAADDR_MASK 0xFFFFFFFFUL /**< Mask for USB_DOEP_DMAADDR */
<> 150:02e0a0aed4ec 2496 #define _USB_DOEP_DMAADDR_DMAADDR_SHIFT 0 /**< Shift value for USB_DMAADDR */
<> 150:02e0a0aed4ec 2497 #define _USB_DOEP_DMAADDR_DMAADDR_MASK 0xFFFFFFFFUL /**< Bit mask for USB_DMAADDR */
<> 150:02e0a0aed4ec 2498 #define _USB_DOEP_DMAADDR_DMAADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_DMAADDR */
<> 150:02e0a0aed4ec 2499 #define USB_DOEP_DMAADDR_DMAADDR_DEFAULT (_USB_DOEP_DMAADDR_DMAADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DOEP_DMAADDR */
<> 150:02e0a0aed4ec 2500
<> 150:02e0a0aed4ec 2501 /* Bit fields for USB PCGCCTL */
<> 150:02e0a0aed4ec 2502 #define _USB_PCGCCTL_RESETVALUE 0x00000000UL /**< Default value for USB_PCGCCTL */
<> 150:02e0a0aed4ec 2503 #define _USB_PCGCCTL_MASK 0x0000014FUL /**< Mask for USB_PCGCCTL */
<> 150:02e0a0aed4ec 2504 #define USB_PCGCCTL_STOPPCLK (0x1UL << 0) /**< Stop PHY clock */
<> 150:02e0a0aed4ec 2505 #define _USB_PCGCCTL_STOPPCLK_SHIFT 0 /**< Shift value for USB_STOPPCLK */
<> 150:02e0a0aed4ec 2506 #define _USB_PCGCCTL_STOPPCLK_MASK 0x1UL /**< Bit mask for USB_STOPPCLK */
<> 150:02e0a0aed4ec 2507 #define _USB_PCGCCTL_STOPPCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_PCGCCTL */
<> 150:02e0a0aed4ec 2508 #define USB_PCGCCTL_STOPPCLK_DEFAULT (_USB_PCGCCTL_STOPPCLK_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_PCGCCTL */
<> 150:02e0a0aed4ec 2509 #define USB_PCGCCTL_GATEHCLK (0x1UL << 1) /**< Gate HCLK */
<> 150:02e0a0aed4ec 2510 #define _USB_PCGCCTL_GATEHCLK_SHIFT 1 /**< Shift value for USB_GATEHCLK */
<> 150:02e0a0aed4ec 2511 #define _USB_PCGCCTL_GATEHCLK_MASK 0x2UL /**< Bit mask for USB_GATEHCLK */
<> 150:02e0a0aed4ec 2512 #define _USB_PCGCCTL_GATEHCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_PCGCCTL */
<> 150:02e0a0aed4ec 2513 #define USB_PCGCCTL_GATEHCLK_DEFAULT (_USB_PCGCCTL_GATEHCLK_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_PCGCCTL */
<> 150:02e0a0aed4ec 2514 #define USB_PCGCCTL_PWRCLMP (0x1UL << 2) /**< Power Clamp */
<> 150:02e0a0aed4ec 2515 #define _USB_PCGCCTL_PWRCLMP_SHIFT 2 /**< Shift value for USB_PWRCLMP */
<> 150:02e0a0aed4ec 2516 #define _USB_PCGCCTL_PWRCLMP_MASK 0x4UL /**< Bit mask for USB_PWRCLMP */
<> 150:02e0a0aed4ec 2517 #define _USB_PCGCCTL_PWRCLMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_PCGCCTL */
<> 150:02e0a0aed4ec 2518 #define USB_PCGCCTL_PWRCLMP_DEFAULT (_USB_PCGCCTL_PWRCLMP_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_PCGCCTL */
<> 150:02e0a0aed4ec 2519 #define USB_PCGCCTL_RSTPDWNMODULE (0x1UL << 3) /**< Reset Power-Down Modules */
<> 150:02e0a0aed4ec 2520 #define _USB_PCGCCTL_RSTPDWNMODULE_SHIFT 3 /**< Shift value for USB_RSTPDWNMODULE */
<> 150:02e0a0aed4ec 2521 #define _USB_PCGCCTL_RSTPDWNMODULE_MASK 0x8UL /**< Bit mask for USB_RSTPDWNMODULE */
<> 150:02e0a0aed4ec 2522 #define _USB_PCGCCTL_RSTPDWNMODULE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_PCGCCTL */
<> 150:02e0a0aed4ec 2523 #define USB_PCGCCTL_RSTPDWNMODULE_DEFAULT (_USB_PCGCCTL_RSTPDWNMODULE_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_PCGCCTL */
<> 150:02e0a0aed4ec 2524 #define USB_PCGCCTL_PHYSLEEP (0x1UL << 6) /**< PHY In Sleep */
<> 150:02e0a0aed4ec 2525 #define _USB_PCGCCTL_PHYSLEEP_SHIFT 6 /**< Shift value for USB_PHYSLEEP */
<> 150:02e0a0aed4ec 2526 #define _USB_PCGCCTL_PHYSLEEP_MASK 0x40UL /**< Bit mask for USB_PHYSLEEP */
<> 150:02e0a0aed4ec 2527 #define _USB_PCGCCTL_PHYSLEEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_PCGCCTL */
<> 150:02e0a0aed4ec 2528 #define USB_PCGCCTL_PHYSLEEP_DEFAULT (_USB_PCGCCTL_PHYSLEEP_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_PCGCCTL */
<> 150:02e0a0aed4ec 2529 #define USB_PCGCCTL_RESETAFTERSUSP (0x1UL << 8) /**< Reset after suspend */
<> 150:02e0a0aed4ec 2530 #define _USB_PCGCCTL_RESETAFTERSUSP_SHIFT 8 /**< Shift value for USB_RESETAFTERSUSP */
<> 150:02e0a0aed4ec 2531 #define _USB_PCGCCTL_RESETAFTERSUSP_MASK 0x100UL /**< Bit mask for USB_RESETAFTERSUSP */
<> 150:02e0a0aed4ec 2532 #define _USB_PCGCCTL_RESETAFTERSUSP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_PCGCCTL */
<> 150:02e0a0aed4ec 2533 #define USB_PCGCCTL_RESETAFTERSUSP_DEFAULT (_USB_PCGCCTL_RESETAFTERSUSP_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_PCGCCTL */
<> 150:02e0a0aed4ec 2534
<> 150:02e0a0aed4ec 2535 /* Bit fields for USB FIFO0D */
<> 150:02e0a0aed4ec 2536 #define _USB_FIFO0D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO0D */
<> 150:02e0a0aed4ec 2537 #define _USB_FIFO0D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO0D */
<> 150:02e0a0aed4ec 2538 #define _USB_FIFO0D_FIFO0D_SHIFT 0 /**< Shift value for USB_FIFO0D */
<> 150:02e0a0aed4ec 2539 #define _USB_FIFO0D_FIFO0D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO0D */
<> 150:02e0a0aed4ec 2540 #define _USB_FIFO0D_FIFO0D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO0D */
<> 150:02e0a0aed4ec 2541 #define USB_FIFO0D_FIFO0D_DEFAULT (_USB_FIFO0D_FIFO0D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO0D */
<> 150:02e0a0aed4ec 2542
<> 150:02e0a0aed4ec 2543 /* Bit fields for USB FIFO1D */
<> 150:02e0a0aed4ec 2544 #define _USB_FIFO1D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO1D */
<> 150:02e0a0aed4ec 2545 #define _USB_FIFO1D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO1D */
<> 150:02e0a0aed4ec 2546 #define _USB_FIFO1D_FIFO1D_SHIFT 0 /**< Shift value for USB_FIFO1D */
<> 150:02e0a0aed4ec 2547 #define _USB_FIFO1D_FIFO1D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO1D */
<> 150:02e0a0aed4ec 2548 #define _USB_FIFO1D_FIFO1D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO1D */
<> 150:02e0a0aed4ec 2549 #define USB_FIFO1D_FIFO1D_DEFAULT (_USB_FIFO1D_FIFO1D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO1D */
<> 150:02e0a0aed4ec 2550
<> 150:02e0a0aed4ec 2551 /* Bit fields for USB FIFO2D */
<> 150:02e0a0aed4ec 2552 #define _USB_FIFO2D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO2D */
<> 150:02e0a0aed4ec 2553 #define _USB_FIFO2D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO2D */
<> 150:02e0a0aed4ec 2554 #define _USB_FIFO2D_FIFO2D_SHIFT 0 /**< Shift value for USB_FIFO2D */
<> 150:02e0a0aed4ec 2555 #define _USB_FIFO2D_FIFO2D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO2D */
<> 150:02e0a0aed4ec 2556 #define _USB_FIFO2D_FIFO2D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO2D */
<> 150:02e0a0aed4ec 2557 #define USB_FIFO2D_FIFO2D_DEFAULT (_USB_FIFO2D_FIFO2D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO2D */
<> 150:02e0a0aed4ec 2558
<> 150:02e0a0aed4ec 2559 /* Bit fields for USB FIFO3D */
<> 150:02e0a0aed4ec 2560 #define _USB_FIFO3D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO3D */
<> 150:02e0a0aed4ec 2561 #define _USB_FIFO3D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO3D */
<> 150:02e0a0aed4ec 2562 #define _USB_FIFO3D_FIFO3D_SHIFT 0 /**< Shift value for USB_FIFO3D */
<> 150:02e0a0aed4ec 2563 #define _USB_FIFO3D_FIFO3D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO3D */
<> 150:02e0a0aed4ec 2564 #define _USB_FIFO3D_FIFO3D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO3D */
<> 150:02e0a0aed4ec 2565 #define USB_FIFO3D_FIFO3D_DEFAULT (_USB_FIFO3D_FIFO3D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO3D */
<> 150:02e0a0aed4ec 2566
<> 150:02e0a0aed4ec 2567 /* Bit fields for USB FIFO4D */
<> 150:02e0a0aed4ec 2568 #define _USB_FIFO4D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO4D */
<> 150:02e0a0aed4ec 2569 #define _USB_FIFO4D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO4D */
<> 150:02e0a0aed4ec 2570 #define _USB_FIFO4D_FIFO4D_SHIFT 0 /**< Shift value for USB_FIFO4D */
<> 150:02e0a0aed4ec 2571 #define _USB_FIFO4D_FIFO4D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO4D */
<> 150:02e0a0aed4ec 2572 #define _USB_FIFO4D_FIFO4D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO4D */
<> 150:02e0a0aed4ec 2573 #define USB_FIFO4D_FIFO4D_DEFAULT (_USB_FIFO4D_FIFO4D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO4D */
<> 150:02e0a0aed4ec 2574
<> 150:02e0a0aed4ec 2575 /* Bit fields for USB FIFO5D */
<> 150:02e0a0aed4ec 2576 #define _USB_FIFO5D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO5D */
<> 150:02e0a0aed4ec 2577 #define _USB_FIFO5D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO5D */
<> 150:02e0a0aed4ec 2578 #define _USB_FIFO5D_FIFO5D_SHIFT 0 /**< Shift value for USB_FIFO5D */
<> 150:02e0a0aed4ec 2579 #define _USB_FIFO5D_FIFO5D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO5D */
<> 150:02e0a0aed4ec 2580 #define _USB_FIFO5D_FIFO5D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO5D */
<> 150:02e0a0aed4ec 2581 #define USB_FIFO5D_FIFO5D_DEFAULT (_USB_FIFO5D_FIFO5D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO5D */
<> 150:02e0a0aed4ec 2582
<> 150:02e0a0aed4ec 2583 /* Bit fields for USB FIFO6D */
<> 150:02e0a0aed4ec 2584 #define _USB_FIFO6D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO6D */
<> 150:02e0a0aed4ec 2585 #define _USB_FIFO6D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO6D */
<> 150:02e0a0aed4ec 2586 #define _USB_FIFO6D_FIFO6D_SHIFT 0 /**< Shift value for USB_FIFO6D */
<> 150:02e0a0aed4ec 2587 #define _USB_FIFO6D_FIFO6D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO6D */
<> 150:02e0a0aed4ec 2588 #define _USB_FIFO6D_FIFO6D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO6D */
<> 150:02e0a0aed4ec 2589 #define USB_FIFO6D_FIFO6D_DEFAULT (_USB_FIFO6D_FIFO6D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO6D */
<> 150:02e0a0aed4ec 2590
<> 150:02e0a0aed4ec 2591 /* Bit fields for USB FIFO7D */
<> 150:02e0a0aed4ec 2592 #define _USB_FIFO7D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO7D */
<> 150:02e0a0aed4ec 2593 #define _USB_FIFO7D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO7D */
<> 150:02e0a0aed4ec 2594 #define _USB_FIFO7D_FIFO7D_SHIFT 0 /**< Shift value for USB_FIFO7D */
<> 150:02e0a0aed4ec 2595 #define _USB_FIFO7D_FIFO7D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO7D */
<> 150:02e0a0aed4ec 2596 #define _USB_FIFO7D_FIFO7D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO7D */
<> 150:02e0a0aed4ec 2597 #define USB_FIFO7D_FIFO7D_DEFAULT (_USB_FIFO7D_FIFO7D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO7D */
<> 150:02e0a0aed4ec 2598
<> 150:02e0a0aed4ec 2599 /* Bit fields for USB FIFO8D */
<> 150:02e0a0aed4ec 2600 #define _USB_FIFO8D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO8D */
<> 150:02e0a0aed4ec 2601 #define _USB_FIFO8D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO8D */
<> 150:02e0a0aed4ec 2602 #define _USB_FIFO8D_FIFO8D_SHIFT 0 /**< Shift value for USB_FIFO8D */
<> 150:02e0a0aed4ec 2603 #define _USB_FIFO8D_FIFO8D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO8D */
<> 150:02e0a0aed4ec 2604 #define _USB_FIFO8D_FIFO8D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO8D */
<> 150:02e0a0aed4ec 2605 #define USB_FIFO8D_FIFO8D_DEFAULT (_USB_FIFO8D_FIFO8D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO8D */
<> 150:02e0a0aed4ec 2606
<> 150:02e0a0aed4ec 2607 /* Bit fields for USB FIFO9D */
<> 150:02e0a0aed4ec 2608 #define _USB_FIFO9D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO9D */
<> 150:02e0a0aed4ec 2609 #define _USB_FIFO9D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO9D */
<> 150:02e0a0aed4ec 2610 #define _USB_FIFO9D_FIFO9D_SHIFT 0 /**< Shift value for USB_FIFO9D */
<> 150:02e0a0aed4ec 2611 #define _USB_FIFO9D_FIFO9D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO9D */
<> 150:02e0a0aed4ec 2612 #define _USB_FIFO9D_FIFO9D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO9D */
<> 150:02e0a0aed4ec 2613 #define USB_FIFO9D_FIFO9D_DEFAULT (_USB_FIFO9D_FIFO9D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO9D */
<> 150:02e0a0aed4ec 2614
<> 150:02e0a0aed4ec 2615 /* Bit fields for USB FIFO10D */
<> 150:02e0a0aed4ec 2616 #define _USB_FIFO10D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO10D */
<> 150:02e0a0aed4ec 2617 #define _USB_FIFO10D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO10D */
<> 150:02e0a0aed4ec 2618 #define _USB_FIFO10D_FIFO10D_SHIFT 0 /**< Shift value for USB_FIFO10D */
<> 150:02e0a0aed4ec 2619 #define _USB_FIFO10D_FIFO10D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO10D */
<> 150:02e0a0aed4ec 2620 #define _USB_FIFO10D_FIFO10D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO10D */
<> 150:02e0a0aed4ec 2621 #define USB_FIFO10D_FIFO10D_DEFAULT (_USB_FIFO10D_FIFO10D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO10D */
<> 150:02e0a0aed4ec 2622
<> 150:02e0a0aed4ec 2623 /* Bit fields for USB FIFO11D */
<> 150:02e0a0aed4ec 2624 #define _USB_FIFO11D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO11D */
<> 150:02e0a0aed4ec 2625 #define _USB_FIFO11D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO11D */
<> 150:02e0a0aed4ec 2626 #define _USB_FIFO11D_FIFO11D_SHIFT 0 /**< Shift value for USB_FIFO11D */
<> 150:02e0a0aed4ec 2627 #define _USB_FIFO11D_FIFO11D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO11D */
<> 150:02e0a0aed4ec 2628 #define _USB_FIFO11D_FIFO11D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO11D */
<> 150:02e0a0aed4ec 2629 #define USB_FIFO11D_FIFO11D_DEFAULT (_USB_FIFO11D_FIFO11D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO11D */
<> 150:02e0a0aed4ec 2630
<> 150:02e0a0aed4ec 2631 /* Bit fields for USB FIFO12D */
<> 150:02e0a0aed4ec 2632 #define _USB_FIFO12D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO12D */
<> 150:02e0a0aed4ec 2633 #define _USB_FIFO12D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO12D */
<> 150:02e0a0aed4ec 2634 #define _USB_FIFO12D_FIFO12D_SHIFT 0 /**< Shift value for USB_FIFO12D */
<> 150:02e0a0aed4ec 2635 #define _USB_FIFO12D_FIFO12D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO12D */
<> 150:02e0a0aed4ec 2636 #define _USB_FIFO12D_FIFO12D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO12D */
<> 150:02e0a0aed4ec 2637 #define USB_FIFO12D_FIFO12D_DEFAULT (_USB_FIFO12D_FIFO12D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO12D */
<> 150:02e0a0aed4ec 2638
<> 150:02e0a0aed4ec 2639 /* Bit fields for USB FIFO13D */
<> 150:02e0a0aed4ec 2640 #define _USB_FIFO13D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO13D */
<> 150:02e0a0aed4ec 2641 #define _USB_FIFO13D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO13D */
<> 150:02e0a0aed4ec 2642 #define _USB_FIFO13D_FIFO13D_SHIFT 0 /**< Shift value for USB_FIFO13D */
<> 150:02e0a0aed4ec 2643 #define _USB_FIFO13D_FIFO13D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO13D */
<> 150:02e0a0aed4ec 2644 #define _USB_FIFO13D_FIFO13D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO13D */
<> 150:02e0a0aed4ec 2645 #define USB_FIFO13D_FIFO13D_DEFAULT (_USB_FIFO13D_FIFO13D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO13D */
<> 150:02e0a0aed4ec 2646
<> 150:02e0a0aed4ec 2647 /* Bit fields for USB FIFORAM */
<> 150:02e0a0aed4ec 2648 #define _USB_FIFORAM_RESETVALUE 0x00000000UL /**< Default value for USB_FIFORAM */
<> 150:02e0a0aed4ec 2649 #define _USB_FIFORAM_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFORAM */
<> 150:02e0a0aed4ec 2650 #define _USB_FIFORAM_FIFORAM_SHIFT 0 /**< Shift value for USB_FIFORAM */
<> 150:02e0a0aed4ec 2651 #define _USB_FIFORAM_FIFORAM_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFORAM */
<> 150:02e0a0aed4ec 2652 #define _USB_FIFORAM_FIFORAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFORAM */
<> 150:02e0a0aed4ec 2653 #define USB_FIFORAM_FIFORAM_DEFAULT (_USB_FIFORAM_FIFORAM_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFORAM */
<> 150:02e0a0aed4ec 2654
<> 150:02e0a0aed4ec 2655 /** @} End of group EFM32WG_USB */
<> 150:02e0a0aed4ec 2656 /** @} End of group Parts */
<> 150:02e0a0aed4ec 2657