Fawwaz Nadzmy / mbed-STM

mbed library sources. Supersedes mbed-src.

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targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_rtc.h@153:9398a535854b, 2016-12-22 (annotated)

Committer:
fwndz
Date:
Thu Dec 22 05:12:40 2016 +0000
Revision:
153:9398a535854b
Parent:
150:02e0a0aed4ec 
device target maximize

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 150:02e0a0aed4ec 1 /**************************************************************************//**
<> 150:02e0a0aed4ec 2 * @file efm32wg_rtc.h
<> 150:02e0a0aed4ec 3 * @brief EFM32WG_RTC register and bit field definitions
<> 150:02e0a0aed4ec 4 * @version 5.0.0
<> 150:02e0a0aed4ec 5 ******************************************************************************
<> 150:02e0a0aed4ec 6 * @section License
<> 150:02e0a0aed4ec 7 * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 150:02e0a0aed4ec 8 ******************************************************************************
<> 150:02e0a0aed4ec 9 *
<> 150:02e0a0aed4ec 10 * Permission is granted to anyone to use this software for any purpose,
<> 150:02e0a0aed4ec 11 * including commercial applications, and to alter it and redistribute it
<> 150:02e0a0aed4ec 12 * freely, subject to the following restrictions:
<> 150:02e0a0aed4ec 13 *
<> 150:02e0a0aed4ec 14 * 1. The origin of this software must not be misrepresented; you must not
<> 150:02e0a0aed4ec 15 * claim that you wrote the original software.@n
<> 150:02e0a0aed4ec 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 150:02e0a0aed4ec 17 * misrepresented as being the original software.@n
<> 150:02e0a0aed4ec 18 * 3. This notice may not be removed or altered from any source distribution.
<> 150:02e0a0aed4ec 19 *
<> 150:02e0a0aed4ec 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 150:02e0a0aed4ec 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 150:02e0a0aed4ec 22 * providing the Software "AS IS", with no express or implied warranties of any
<> 150:02e0a0aed4ec 23 * kind, including, but not limited to, any implied warranties of
<> 150:02e0a0aed4ec 24 * merchantability or fitness for any particular purpose or warranties against
<> 150:02e0a0aed4ec 25 * infringement of any proprietary rights of a third party.
<> 150:02e0a0aed4ec 26 *
<> 150:02e0a0aed4ec 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 150:02e0a0aed4ec 28 * incidental, or special damages, or any other relief, or for any claim by
<> 150:02e0a0aed4ec 29 * any third party, arising from your use of this Software.
<> 150:02e0a0aed4ec 30 *
<> 150:02e0a0aed4ec 31 *****************************************************************************/
<> 150:02e0a0aed4ec 32 /**************************************************************************//**
<> 150:02e0a0aed4ec 33 * @addtogroup Parts
<> 150:02e0a0aed4ec 34 * @{
<> 150:02e0a0aed4ec 35 ******************************************************************************/
<> 150:02e0a0aed4ec 36 /**************************************************************************//**
<> 150:02e0a0aed4ec 37 * @defgroup EFM32WG_RTC
<> 150:02e0a0aed4ec 38 * @{
<> 150:02e0a0aed4ec 39 * @brief EFM32WG_RTC Register Declaration
<> 150:02e0a0aed4ec 40 *****************************************************************************/
<> 150:02e0a0aed4ec 41 typedef struct
<> 150:02e0a0aed4ec 42 {
<> 150:02e0a0aed4ec 43 __IOM uint32_t CTRL; /**< Control Register */
<> 150:02e0a0aed4ec 44 __IOM uint32_t CNT; /**< Counter Value Register */
<> 150:02e0a0aed4ec 45 __IOM uint32_t COMP0; /**< Compare Value Register 0 */
<> 150:02e0a0aed4ec 46 __IOM uint32_t COMP1; /**< Compare Value Register 1 */
<> 150:02e0a0aed4ec 47 __IM uint32_t IF; /**< Interrupt Flag Register */
<> 150:02e0a0aed4ec 48 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
<> 150:02e0a0aed4ec 49 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
<> 150:02e0a0aed4ec 50 __IOM uint32_t IEN; /**< Interrupt Enable Register */
<> 150:02e0a0aed4ec 51
<> 150:02e0a0aed4ec 52 __IOM uint32_t FREEZE; /**< Freeze Register */
<> 150:02e0a0aed4ec 53 __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
<> 150:02e0a0aed4ec 54 } RTC_TypeDef; /** @} */
<> 150:02e0a0aed4ec 55
<> 150:02e0a0aed4ec 56 /**************************************************************************//**
<> 150:02e0a0aed4ec 57 * @defgroup EFM32WG_RTC_BitFields
<> 150:02e0a0aed4ec 58 * @{
<> 150:02e0a0aed4ec 59 *****************************************************************************/
<> 150:02e0a0aed4ec 60
<> 150:02e0a0aed4ec 61 /* Bit fields for RTC CTRL */
<> 150:02e0a0aed4ec 62 #define _RTC_CTRL_RESETVALUE 0x00000000UL /**< Default value for RTC_CTRL */
<> 150:02e0a0aed4ec 63 #define _RTC_CTRL_MASK 0x00000007UL /**< Mask for RTC_CTRL */
<> 150:02e0a0aed4ec 64 #define RTC_CTRL_EN (0x1UL << 0) /**< RTC Enable */
<> 150:02e0a0aed4ec 65 #define _RTC_CTRL_EN_SHIFT 0 /**< Shift value for RTC_EN */
<> 150:02e0a0aed4ec 66 #define _RTC_CTRL_EN_MASK 0x1UL /**< Bit mask for RTC_EN */
<> 150:02e0a0aed4ec 67 #define _RTC_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_CTRL */
<> 150:02e0a0aed4ec 68 #define RTC_CTRL_EN_DEFAULT (_RTC_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_CTRL */
<> 150:02e0a0aed4ec 69 #define RTC_CTRL_DEBUGRUN (0x1UL << 1) /**< Debug Mode Run Enable */
<> 150:02e0a0aed4ec 70 #define _RTC_CTRL_DEBUGRUN_SHIFT 1 /**< Shift value for RTC_DEBUGRUN */
<> 150:02e0a0aed4ec 71 #define _RTC_CTRL_DEBUGRUN_MASK 0x2UL /**< Bit mask for RTC_DEBUGRUN */
<> 150:02e0a0aed4ec 72 #define _RTC_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_CTRL */
<> 150:02e0a0aed4ec 73 #define RTC_CTRL_DEBUGRUN_DEFAULT (_RTC_CTRL_DEBUGRUN_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_CTRL */
<> 150:02e0a0aed4ec 74 #define RTC_CTRL_COMP0TOP (0x1UL << 2) /**< Compare Channel 0 is Top Value */
<> 150:02e0a0aed4ec 75 #define _RTC_CTRL_COMP0TOP_SHIFT 2 /**< Shift value for RTC_COMP0TOP */
<> 150:02e0a0aed4ec 76 #define _RTC_CTRL_COMP0TOP_MASK 0x4UL /**< Bit mask for RTC_COMP0TOP */
<> 150:02e0a0aed4ec 77 #define _RTC_CTRL_COMP0TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_CTRL */
<> 150:02e0a0aed4ec 78 #define _RTC_CTRL_COMP0TOP_DISABLE 0x00000000UL /**< Mode DISABLE for RTC_CTRL */
<> 150:02e0a0aed4ec 79 #define _RTC_CTRL_COMP0TOP_ENABLE 0x00000001UL /**< Mode ENABLE for RTC_CTRL */
<> 150:02e0a0aed4ec 80 #define RTC_CTRL_COMP0TOP_DEFAULT (_RTC_CTRL_COMP0TOP_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_CTRL */
<> 150:02e0a0aed4ec 81 #define RTC_CTRL_COMP0TOP_DISABLE (_RTC_CTRL_COMP0TOP_DISABLE << 2) /**< Shifted mode DISABLE for RTC_CTRL */
<> 150:02e0a0aed4ec 82 #define RTC_CTRL_COMP0TOP_ENABLE (_RTC_CTRL_COMP0TOP_ENABLE << 2) /**< Shifted mode ENABLE for RTC_CTRL */
<> 150:02e0a0aed4ec 83
<> 150:02e0a0aed4ec 84 /* Bit fields for RTC CNT */
<> 150:02e0a0aed4ec 85 #define _RTC_CNT_RESETVALUE 0x00000000UL /**< Default value for RTC_CNT */
<> 150:02e0a0aed4ec 86 #define _RTC_CNT_MASK 0x00FFFFFFUL /**< Mask for RTC_CNT */
<> 150:02e0a0aed4ec 87 #define _RTC_CNT_CNT_SHIFT 0 /**< Shift value for RTC_CNT */
<> 150:02e0a0aed4ec 88 #define _RTC_CNT_CNT_MASK 0xFFFFFFUL /**< Bit mask for RTC_CNT */
<> 150:02e0a0aed4ec 89 #define _RTC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_CNT */
<> 150:02e0a0aed4ec 90 #define RTC_CNT_CNT_DEFAULT (_RTC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_CNT */
<> 150:02e0a0aed4ec 91
<> 150:02e0a0aed4ec 92 /* Bit fields for RTC COMP0 */
<> 150:02e0a0aed4ec 93 #define _RTC_COMP0_RESETVALUE 0x00000000UL /**< Default value for RTC_COMP0 */
<> 150:02e0a0aed4ec 94 #define _RTC_COMP0_MASK 0x00FFFFFFUL /**< Mask for RTC_COMP0 */
<> 150:02e0a0aed4ec 95 #define _RTC_COMP0_COMP0_SHIFT 0 /**< Shift value for RTC_COMP0 */
<> 150:02e0a0aed4ec 96 #define _RTC_COMP0_COMP0_MASK 0xFFFFFFUL /**< Bit mask for RTC_COMP0 */
<> 150:02e0a0aed4ec 97 #define _RTC_COMP0_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_COMP0 */
<> 150:02e0a0aed4ec 98 #define RTC_COMP0_COMP0_DEFAULT (_RTC_COMP0_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_COMP0 */
<> 150:02e0a0aed4ec 99
<> 150:02e0a0aed4ec 100 /* Bit fields for RTC COMP1 */
<> 150:02e0a0aed4ec 101 #define _RTC_COMP1_RESETVALUE 0x00000000UL /**< Default value for RTC_COMP1 */
<> 150:02e0a0aed4ec 102 #define _RTC_COMP1_MASK 0x00FFFFFFUL /**< Mask for RTC_COMP1 */
<> 150:02e0a0aed4ec 103 #define _RTC_COMP1_COMP1_SHIFT 0 /**< Shift value for RTC_COMP1 */
<> 150:02e0a0aed4ec 104 #define _RTC_COMP1_COMP1_MASK 0xFFFFFFUL /**< Bit mask for RTC_COMP1 */
<> 150:02e0a0aed4ec 105 #define _RTC_COMP1_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_COMP1 */
<> 150:02e0a0aed4ec 106 #define RTC_COMP1_COMP1_DEFAULT (_RTC_COMP1_COMP1_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_COMP1 */
<> 150:02e0a0aed4ec 107
<> 150:02e0a0aed4ec 108 /* Bit fields for RTC IF */
<> 150:02e0a0aed4ec 109 #define _RTC_IF_RESETVALUE 0x00000000UL /**< Default value for RTC_IF */
<> 150:02e0a0aed4ec 110 #define _RTC_IF_MASK 0x00000007UL /**< Mask for RTC_IF */
<> 150:02e0a0aed4ec 111 #define RTC_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */
<> 150:02e0a0aed4ec 112 #define _RTC_IF_OF_SHIFT 0 /**< Shift value for RTC_OF */
<> 150:02e0a0aed4ec 113 #define _RTC_IF_OF_MASK 0x1UL /**< Bit mask for RTC_OF */
<> 150:02e0a0aed4ec 114 #define _RTC_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IF */
<> 150:02e0a0aed4ec 115 #define RTC_IF_OF_DEFAULT (_RTC_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_IF */
<> 150:02e0a0aed4ec 116 #define RTC_IF_COMP0 (0x1UL << 1) /**< Compare Match 0 Interrupt Flag */
<> 150:02e0a0aed4ec 117 #define _RTC_IF_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */
<> 150:02e0a0aed4ec 118 #define _RTC_IF_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */
<> 150:02e0a0aed4ec 119 #define _RTC_IF_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IF */
<> 150:02e0a0aed4ec 120 #define RTC_IF_COMP0_DEFAULT (_RTC_IF_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_IF */
<> 150:02e0a0aed4ec 121 #define RTC_IF_COMP1 (0x1UL << 2) /**< Compare Match 1 Interrupt Flag */
<> 150:02e0a0aed4ec 122 #define _RTC_IF_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */
<> 150:02e0a0aed4ec 123 #define _RTC_IF_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */
<> 150:02e0a0aed4ec 124 #define _RTC_IF_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IF */
<> 150:02e0a0aed4ec 125 #define RTC_IF_COMP1_DEFAULT (_RTC_IF_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_IF */
<> 150:02e0a0aed4ec 126
<> 150:02e0a0aed4ec 127 /* Bit fields for RTC IFS */
<> 150:02e0a0aed4ec 128 #define _RTC_IFS_RESETVALUE 0x00000000UL /**< Default value for RTC_IFS */
<> 150:02e0a0aed4ec 129 #define _RTC_IFS_MASK 0x00000007UL /**< Mask for RTC_IFS */
<> 150:02e0a0aed4ec 130 #define RTC_IFS_OF (0x1UL << 0) /**< Set Overflow Interrupt Flag */
<> 150:02e0a0aed4ec 131 #define _RTC_IFS_OF_SHIFT 0 /**< Shift value for RTC_OF */
<> 150:02e0a0aed4ec 132 #define _RTC_IFS_OF_MASK 0x1UL /**< Bit mask for RTC_OF */
<> 150:02e0a0aed4ec 133 #define _RTC_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFS */
<> 150:02e0a0aed4ec 134 #define RTC_IFS_OF_DEFAULT (_RTC_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_IFS */
<> 150:02e0a0aed4ec 135 #define RTC_IFS_COMP0 (0x1UL << 1) /**< Set Compare match 0 Interrupt Flag */
<> 150:02e0a0aed4ec 136 #define _RTC_IFS_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */
<> 150:02e0a0aed4ec 137 #define _RTC_IFS_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */
<> 150:02e0a0aed4ec 138 #define _RTC_IFS_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFS */
<> 150:02e0a0aed4ec 139 #define RTC_IFS_COMP0_DEFAULT (_RTC_IFS_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_IFS */
<> 150:02e0a0aed4ec 140 #define RTC_IFS_COMP1 (0x1UL << 2) /**< Set Compare match 1 Interrupt Flag */
<> 150:02e0a0aed4ec 141 #define _RTC_IFS_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */
<> 150:02e0a0aed4ec 142 #define _RTC_IFS_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */
<> 150:02e0a0aed4ec 143 #define _RTC_IFS_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFS */
<> 150:02e0a0aed4ec 144 #define RTC_IFS_COMP1_DEFAULT (_RTC_IFS_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_IFS */
<> 150:02e0a0aed4ec 145
<> 150:02e0a0aed4ec 146 /* Bit fields for RTC IFC */
<> 150:02e0a0aed4ec 147 #define _RTC_IFC_RESETVALUE 0x00000000UL /**< Default value for RTC_IFC */
<> 150:02e0a0aed4ec 148 #define _RTC_IFC_MASK 0x00000007UL /**< Mask for RTC_IFC */
<> 150:02e0a0aed4ec 149 #define RTC_IFC_OF (0x1UL << 0) /**< Clear Overflow Interrupt Flag */
<> 150:02e0a0aed4ec 150 #define _RTC_IFC_OF_SHIFT 0 /**< Shift value for RTC_OF */
<> 150:02e0a0aed4ec 151 #define _RTC_IFC_OF_MASK 0x1UL /**< Bit mask for RTC_OF */
<> 150:02e0a0aed4ec 152 #define _RTC_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFC */
<> 150:02e0a0aed4ec 153 #define RTC_IFC_OF_DEFAULT (_RTC_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_IFC */
<> 150:02e0a0aed4ec 154 #define RTC_IFC_COMP0 (0x1UL << 1) /**< Clear Compare match 0 Interrupt Flag */
<> 150:02e0a0aed4ec 155 #define _RTC_IFC_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */
<> 150:02e0a0aed4ec 156 #define _RTC_IFC_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */
<> 150:02e0a0aed4ec 157 #define _RTC_IFC_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFC */
<> 150:02e0a0aed4ec 158 #define RTC_IFC_COMP0_DEFAULT (_RTC_IFC_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_IFC */
<> 150:02e0a0aed4ec 159 #define RTC_IFC_COMP1 (0x1UL << 2) /**< Clear Compare match 1 Interrupt Flag */
<> 150:02e0a0aed4ec 160 #define _RTC_IFC_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */
<> 150:02e0a0aed4ec 161 #define _RTC_IFC_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */
<> 150:02e0a0aed4ec 162 #define _RTC_IFC_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFC */
<> 150:02e0a0aed4ec 163 #define RTC_IFC_COMP1_DEFAULT (_RTC_IFC_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_IFC */
<> 150:02e0a0aed4ec 164
<> 150:02e0a0aed4ec 165 /* Bit fields for RTC IEN */
<> 150:02e0a0aed4ec 166 #define _RTC_IEN_RESETVALUE 0x00000000UL /**< Default value for RTC_IEN */
<> 150:02e0a0aed4ec 167 #define _RTC_IEN_MASK 0x00000007UL /**< Mask for RTC_IEN */
<> 150:02e0a0aed4ec 168 #define RTC_IEN_OF (0x1UL << 0) /**< Overflow Interrupt Enable */
<> 150:02e0a0aed4ec 169 #define _RTC_IEN_OF_SHIFT 0 /**< Shift value for RTC_OF */
<> 150:02e0a0aed4ec 170 #define _RTC_IEN_OF_MASK 0x1UL /**< Bit mask for RTC_OF */
<> 150:02e0a0aed4ec 171 #define _RTC_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IEN */
<> 150:02e0a0aed4ec 172 #define RTC_IEN_OF_DEFAULT (_RTC_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_IEN */
<> 150:02e0a0aed4ec 173 #define RTC_IEN_COMP0 (0x1UL << 1) /**< Compare Match 0 Interrupt Enable */
<> 150:02e0a0aed4ec 174 #define _RTC_IEN_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */
<> 150:02e0a0aed4ec 175 #define _RTC_IEN_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */
<> 150:02e0a0aed4ec 176 #define _RTC_IEN_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IEN */
<> 150:02e0a0aed4ec 177 #define RTC_IEN_COMP0_DEFAULT (_RTC_IEN_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_IEN */
<> 150:02e0a0aed4ec 178 #define RTC_IEN_COMP1 (0x1UL << 2) /**< Compare Match 1 Interrupt Enable */
<> 150:02e0a0aed4ec 179 #define _RTC_IEN_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */
<> 150:02e0a0aed4ec 180 #define _RTC_IEN_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */
<> 150:02e0a0aed4ec 181 #define _RTC_IEN_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IEN */
<> 150:02e0a0aed4ec 182 #define RTC_IEN_COMP1_DEFAULT (_RTC_IEN_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_IEN */
<> 150:02e0a0aed4ec 183
<> 150:02e0a0aed4ec 184 /* Bit fields for RTC FREEZE */
<> 150:02e0a0aed4ec 185 #define _RTC_FREEZE_RESETVALUE 0x00000000UL /**< Default value for RTC_FREEZE */
<> 150:02e0a0aed4ec 186 #define _RTC_FREEZE_MASK 0x00000001UL /**< Mask for RTC_FREEZE */
<> 150:02e0a0aed4ec 187 #define RTC_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */
<> 150:02e0a0aed4ec 188 #define _RTC_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for RTC_REGFREEZE */
<> 150:02e0a0aed4ec 189 #define _RTC_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for RTC_REGFREEZE */
<> 150:02e0a0aed4ec 190 #define _RTC_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_FREEZE */
<> 150:02e0a0aed4ec 191 #define _RTC_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for RTC_FREEZE */
<> 150:02e0a0aed4ec 192 #define _RTC_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for RTC_FREEZE */
<> 150:02e0a0aed4ec 193 #define RTC_FREEZE_REGFREEZE_DEFAULT (_RTC_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_FREEZE */
<> 150:02e0a0aed4ec 194 #define RTC_FREEZE_REGFREEZE_UPDATE (_RTC_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for RTC_FREEZE */
<> 150:02e0a0aed4ec 195 #define RTC_FREEZE_REGFREEZE_FREEZE (_RTC_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for RTC_FREEZE */
<> 150:02e0a0aed4ec 196
<> 150:02e0a0aed4ec 197 /* Bit fields for RTC SYNCBUSY */
<> 150:02e0a0aed4ec 198 #define _RTC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for RTC_SYNCBUSY */
<> 150:02e0a0aed4ec 199 #define _RTC_SYNCBUSY_MASK 0x00000007UL /**< Mask for RTC_SYNCBUSY */
<> 150:02e0a0aed4ec 200 #define RTC_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */
<> 150:02e0a0aed4ec 201 #define _RTC_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for RTC_CTRL */
<> 150:02e0a0aed4ec 202 #define _RTC_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for RTC_CTRL */
<> 150:02e0a0aed4ec 203 #define _RTC_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_SYNCBUSY */
<> 150:02e0a0aed4ec 204 #define RTC_SYNCBUSY_CTRL_DEFAULT (_RTC_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_SYNCBUSY */
<> 150:02e0a0aed4ec 205 #define RTC_SYNCBUSY_COMP0 (0x1UL << 1) /**< COMP0 Register Busy */
<> 150:02e0a0aed4ec 206 #define _RTC_SYNCBUSY_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */
<> 150:02e0a0aed4ec 207 #define _RTC_SYNCBUSY_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */
<> 150:02e0a0aed4ec 208 #define _RTC_SYNCBUSY_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_SYNCBUSY */
<> 150:02e0a0aed4ec 209 #define RTC_SYNCBUSY_COMP0_DEFAULT (_RTC_SYNCBUSY_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_SYNCBUSY */
<> 150:02e0a0aed4ec 210 #define RTC_SYNCBUSY_COMP1 (0x1UL << 2) /**< COMP1 Register Busy */
<> 150:02e0a0aed4ec 211 #define _RTC_SYNCBUSY_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */
<> 150:02e0a0aed4ec 212 #define _RTC_SYNCBUSY_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */
<> 150:02e0a0aed4ec 213 #define _RTC_SYNCBUSY_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_SYNCBUSY */
<> 150:02e0a0aed4ec 214 #define RTC_SYNCBUSY_COMP1_DEFAULT (_RTC_SYNCBUSY_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_SYNCBUSY */
<> 150:02e0a0aed4ec 215
<> 150:02e0a0aed4ec 216 /** @} End of group EFM32WG_RTC */
<> 150:02e0a0aed4ec 217 /** @} End of group Parts */
<> 150:02e0a0aed4ec 218