Fawwaz Nadzmy / mbed-STM

mbed library sources. Supersedes mbed-src.

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targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_rmu.h@153:9398a535854b, 2016-12-22 (annotated)

Committer:
fwndz
Date:
Thu Dec 22 05:12:40 2016 +0000
Revision:
153:9398a535854b
Parent:
150:02e0a0aed4ec 
device target maximize

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 150:02e0a0aed4ec 1 /**************************************************************************//**
<> 150:02e0a0aed4ec 2 * @file efm32wg_rmu.h
<> 150:02e0a0aed4ec 3 * @brief EFM32WG_RMU register and bit field definitions
<> 150:02e0a0aed4ec 4 * @version 5.0.0
<> 150:02e0a0aed4ec 5 ******************************************************************************
<> 150:02e0a0aed4ec 6 * @section License
<> 150:02e0a0aed4ec 7 * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 150:02e0a0aed4ec 8 ******************************************************************************
<> 150:02e0a0aed4ec 9 *
<> 150:02e0a0aed4ec 10 * Permission is granted to anyone to use this software for any purpose,
<> 150:02e0a0aed4ec 11 * including commercial applications, and to alter it and redistribute it
<> 150:02e0a0aed4ec 12 * freely, subject to the following restrictions:
<> 150:02e0a0aed4ec 13 *
<> 150:02e0a0aed4ec 14 * 1. The origin of this software must not be misrepresented; you must not
<> 150:02e0a0aed4ec 15 * claim that you wrote the original software.@n
<> 150:02e0a0aed4ec 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 150:02e0a0aed4ec 17 * misrepresented as being the original software.@n
<> 150:02e0a0aed4ec 18 * 3. This notice may not be removed or altered from any source distribution.
<> 150:02e0a0aed4ec 19 *
<> 150:02e0a0aed4ec 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 150:02e0a0aed4ec 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 150:02e0a0aed4ec 22 * providing the Software "AS IS", with no express or implied warranties of any
<> 150:02e0a0aed4ec 23 * kind, including, but not limited to, any implied warranties of
<> 150:02e0a0aed4ec 24 * merchantability or fitness for any particular purpose or warranties against
<> 150:02e0a0aed4ec 25 * infringement of any proprietary rights of a third party.
<> 150:02e0a0aed4ec 26 *
<> 150:02e0a0aed4ec 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 150:02e0a0aed4ec 28 * incidental, or special damages, or any other relief, or for any claim by
<> 150:02e0a0aed4ec 29 * any third party, arising from your use of this Software.
<> 150:02e0a0aed4ec 30 *
<> 150:02e0a0aed4ec 31 *****************************************************************************/
<> 150:02e0a0aed4ec 32 /**************************************************************************//**
<> 150:02e0a0aed4ec 33 * @addtogroup Parts
<> 150:02e0a0aed4ec 34 * @{
<> 150:02e0a0aed4ec 35 ******************************************************************************/
<> 150:02e0a0aed4ec 36 /**************************************************************************//**
<> 150:02e0a0aed4ec 37 * @defgroup EFM32WG_RMU
<> 150:02e0a0aed4ec 38 * @{
<> 150:02e0a0aed4ec 39 * @brief EFM32WG_RMU Register Declaration
<> 150:02e0a0aed4ec 40 *****************************************************************************/
<> 150:02e0a0aed4ec 41 typedef struct
<> 150:02e0a0aed4ec 42 {
<> 150:02e0a0aed4ec 43 __IOM uint32_t CTRL; /**< Control Register */
<> 150:02e0a0aed4ec 44 __IM uint32_t RSTCAUSE; /**< Reset Cause Register */
<> 150:02e0a0aed4ec 45 __OM uint32_t CMD; /**< Command Register */
<> 150:02e0a0aed4ec 46 } RMU_TypeDef; /** @} */
<> 150:02e0a0aed4ec 47
<> 150:02e0a0aed4ec 48 /**************************************************************************//**
<> 150:02e0a0aed4ec 49 * @defgroup EFM32WG_RMU_BitFields
<> 150:02e0a0aed4ec 50 * @{
<> 150:02e0a0aed4ec 51 *****************************************************************************/
<> 150:02e0a0aed4ec 52
<> 150:02e0a0aed4ec 53 /* Bit fields for RMU CTRL */
<> 150:02e0a0aed4ec 54 #define _RMU_CTRL_RESETVALUE 0x00000002UL /**< Default value for RMU_CTRL */
<> 150:02e0a0aed4ec 55 #define _RMU_CTRL_MASK 0x00000003UL /**< Mask for RMU_CTRL */
<> 150:02e0a0aed4ec 56 #define RMU_CTRL_LOCKUPRDIS (0x1UL << 0) /**< Lockup Reset Disable */
<> 150:02e0a0aed4ec 57 #define _RMU_CTRL_LOCKUPRDIS_SHIFT 0 /**< Shift value for RMU_LOCKUPRDIS */
<> 150:02e0a0aed4ec 58 #define _RMU_CTRL_LOCKUPRDIS_MASK 0x1UL /**< Bit mask for RMU_LOCKUPRDIS */
<> 150:02e0a0aed4ec 59 #define _RMU_CTRL_LOCKUPRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_CTRL */
<> 150:02e0a0aed4ec 60 #define RMU_CTRL_LOCKUPRDIS_DEFAULT (_RMU_CTRL_LOCKUPRDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_CTRL */
<> 150:02e0a0aed4ec 61 #define RMU_CTRL_BURSTEN (0x1UL << 1) /**< Backup domain reset enable */
<> 150:02e0a0aed4ec 62 #define _RMU_CTRL_BURSTEN_SHIFT 1 /**< Shift value for RMU_BURSTEN */
<> 150:02e0a0aed4ec 63 #define _RMU_CTRL_BURSTEN_MASK 0x2UL /**< Bit mask for RMU_BURSTEN */
<> 150:02e0a0aed4ec 64 #define _RMU_CTRL_BURSTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for RMU_CTRL */
<> 150:02e0a0aed4ec 65 #define RMU_CTRL_BURSTEN_DEFAULT (_RMU_CTRL_BURSTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for RMU_CTRL */
<> 150:02e0a0aed4ec 66
<> 150:02e0a0aed4ec 67 /* Bit fields for RMU RSTCAUSE */
<> 150:02e0a0aed4ec 68 #define _RMU_RSTCAUSE_RESETVALUE 0x00000000UL /**< Default value for RMU_RSTCAUSE */
<> 150:02e0a0aed4ec 69 #define _RMU_RSTCAUSE_MASK 0x0000FFFFUL /**< Mask for RMU_RSTCAUSE */
<> 150:02e0a0aed4ec 70 #define RMU_RSTCAUSE_PORST (0x1UL << 0) /**< Power On Reset */
<> 150:02e0a0aed4ec 71 #define _RMU_RSTCAUSE_PORST_SHIFT 0 /**< Shift value for RMU_PORST */
<> 150:02e0a0aed4ec 72 #define _RMU_RSTCAUSE_PORST_MASK 0x1UL /**< Bit mask for RMU_PORST */
<> 150:02e0a0aed4ec 73 #define _RMU_RSTCAUSE_PORST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
<> 150:02e0a0aed4ec 74 #define RMU_RSTCAUSE_PORST_DEFAULT (_RMU_RSTCAUSE_PORST_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
<> 150:02e0a0aed4ec 75 #define RMU_RSTCAUSE_BODUNREGRST (0x1UL << 1) /**< Brown Out Detector Unregulated Domain Reset */
<> 150:02e0a0aed4ec 76 #define _RMU_RSTCAUSE_BODUNREGRST_SHIFT 1 /**< Shift value for RMU_BODUNREGRST */
<> 150:02e0a0aed4ec 77 #define _RMU_RSTCAUSE_BODUNREGRST_MASK 0x2UL /**< Bit mask for RMU_BODUNREGRST */
<> 150:02e0a0aed4ec 78 #define _RMU_RSTCAUSE_BODUNREGRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
<> 150:02e0a0aed4ec 79 #define RMU_RSTCAUSE_BODUNREGRST_DEFAULT (_RMU_RSTCAUSE_BODUNREGRST_DEFAULT << 1) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
<> 150:02e0a0aed4ec 80 #define RMU_RSTCAUSE_BODREGRST (0x1UL << 2) /**< Brown Out Detector Regulated Domain Reset */
<> 150:02e0a0aed4ec 81 #define _RMU_RSTCAUSE_BODREGRST_SHIFT 2 /**< Shift value for RMU_BODREGRST */
<> 150:02e0a0aed4ec 82 #define _RMU_RSTCAUSE_BODREGRST_MASK 0x4UL /**< Bit mask for RMU_BODREGRST */
<> 150:02e0a0aed4ec 83 #define _RMU_RSTCAUSE_BODREGRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
<> 150:02e0a0aed4ec 84 #define RMU_RSTCAUSE_BODREGRST_DEFAULT (_RMU_RSTCAUSE_BODREGRST_DEFAULT << 2) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
<> 150:02e0a0aed4ec 85 #define RMU_RSTCAUSE_EXTRST (0x1UL << 3) /**< External Pin Reset */
<> 150:02e0a0aed4ec 86 #define _RMU_RSTCAUSE_EXTRST_SHIFT 3 /**< Shift value for RMU_EXTRST */
<> 150:02e0a0aed4ec 87 #define _RMU_RSTCAUSE_EXTRST_MASK 0x8UL /**< Bit mask for RMU_EXTRST */
<> 150:02e0a0aed4ec 88 #define _RMU_RSTCAUSE_EXTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
<> 150:02e0a0aed4ec 89 #define RMU_RSTCAUSE_EXTRST_DEFAULT (_RMU_RSTCAUSE_EXTRST_DEFAULT << 3) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
<> 150:02e0a0aed4ec 90 #define RMU_RSTCAUSE_WDOGRST (0x1UL << 4) /**< Watchdog Reset */
<> 150:02e0a0aed4ec 91 #define _RMU_RSTCAUSE_WDOGRST_SHIFT 4 /**< Shift value for RMU_WDOGRST */
<> 150:02e0a0aed4ec 92 #define _RMU_RSTCAUSE_WDOGRST_MASK 0x10UL /**< Bit mask for RMU_WDOGRST */
<> 150:02e0a0aed4ec 93 #define _RMU_RSTCAUSE_WDOGRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
<> 150:02e0a0aed4ec 94 #define RMU_RSTCAUSE_WDOGRST_DEFAULT (_RMU_RSTCAUSE_WDOGRST_DEFAULT << 4) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
<> 150:02e0a0aed4ec 95 #define RMU_RSTCAUSE_LOCKUPRST (0x1UL << 5) /**< LOCKUP Reset */
<> 150:02e0a0aed4ec 96 #define _RMU_RSTCAUSE_LOCKUPRST_SHIFT 5 /**< Shift value for RMU_LOCKUPRST */
<> 150:02e0a0aed4ec 97 #define _RMU_RSTCAUSE_LOCKUPRST_MASK 0x20UL /**< Bit mask for RMU_LOCKUPRST */
<> 150:02e0a0aed4ec 98 #define _RMU_RSTCAUSE_LOCKUPRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
<> 150:02e0a0aed4ec 99 #define RMU_RSTCAUSE_LOCKUPRST_DEFAULT (_RMU_RSTCAUSE_LOCKUPRST_DEFAULT << 5) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
<> 150:02e0a0aed4ec 100 #define RMU_RSTCAUSE_SYSREQRST (0x1UL << 6) /**< System Request Reset */
<> 150:02e0a0aed4ec 101 #define _RMU_RSTCAUSE_SYSREQRST_SHIFT 6 /**< Shift value for RMU_SYSREQRST */
<> 150:02e0a0aed4ec 102 #define _RMU_RSTCAUSE_SYSREQRST_MASK 0x40UL /**< Bit mask for RMU_SYSREQRST */
<> 150:02e0a0aed4ec 103 #define _RMU_RSTCAUSE_SYSREQRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
<> 150:02e0a0aed4ec 104 #define RMU_RSTCAUSE_SYSREQRST_DEFAULT (_RMU_RSTCAUSE_SYSREQRST_DEFAULT << 6) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
<> 150:02e0a0aed4ec 105 #define RMU_RSTCAUSE_EM4RST (0x1UL << 7) /**< EM4 Reset */
<> 150:02e0a0aed4ec 106 #define _RMU_RSTCAUSE_EM4RST_SHIFT 7 /**< Shift value for RMU_EM4RST */
<> 150:02e0a0aed4ec 107 #define _RMU_RSTCAUSE_EM4RST_MASK 0x80UL /**< Bit mask for RMU_EM4RST */
<> 150:02e0a0aed4ec 108 #define _RMU_RSTCAUSE_EM4RST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
<> 150:02e0a0aed4ec 109 #define RMU_RSTCAUSE_EM4RST_DEFAULT (_RMU_RSTCAUSE_EM4RST_DEFAULT << 7) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
<> 150:02e0a0aed4ec 110 #define RMU_RSTCAUSE_EM4WURST (0x1UL << 8) /**< EM4 Wake-up Reset */
<> 150:02e0a0aed4ec 111 #define _RMU_RSTCAUSE_EM4WURST_SHIFT 8 /**< Shift value for RMU_EM4WURST */
<> 150:02e0a0aed4ec 112 #define _RMU_RSTCAUSE_EM4WURST_MASK 0x100UL /**< Bit mask for RMU_EM4WURST */
<> 150:02e0a0aed4ec 113 #define _RMU_RSTCAUSE_EM4WURST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
<> 150:02e0a0aed4ec 114 #define RMU_RSTCAUSE_EM4WURST_DEFAULT (_RMU_RSTCAUSE_EM4WURST_DEFAULT << 8) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
<> 150:02e0a0aed4ec 115 #define RMU_RSTCAUSE_BODAVDD0 (0x1UL << 9) /**< AVDD0 Bod Reset */
<> 150:02e0a0aed4ec 116 #define _RMU_RSTCAUSE_BODAVDD0_SHIFT 9 /**< Shift value for RMU_BODAVDD0 */
<> 150:02e0a0aed4ec 117 #define _RMU_RSTCAUSE_BODAVDD0_MASK 0x200UL /**< Bit mask for RMU_BODAVDD0 */
<> 150:02e0a0aed4ec 118 #define _RMU_RSTCAUSE_BODAVDD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
<> 150:02e0a0aed4ec 119 #define RMU_RSTCAUSE_BODAVDD0_DEFAULT (_RMU_RSTCAUSE_BODAVDD0_DEFAULT << 9) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
<> 150:02e0a0aed4ec 120 #define RMU_RSTCAUSE_BODAVDD1 (0x1UL << 10) /**< AVDD1 Bod Reset */
<> 150:02e0a0aed4ec 121 #define _RMU_RSTCAUSE_BODAVDD1_SHIFT 10 /**< Shift value for RMU_BODAVDD1 */
<> 150:02e0a0aed4ec 122 #define _RMU_RSTCAUSE_BODAVDD1_MASK 0x400UL /**< Bit mask for RMU_BODAVDD1 */
<> 150:02e0a0aed4ec 123 #define _RMU_RSTCAUSE_BODAVDD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
<> 150:02e0a0aed4ec 124 #define RMU_RSTCAUSE_BODAVDD1_DEFAULT (_RMU_RSTCAUSE_BODAVDD1_DEFAULT << 10) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
<> 150:02e0a0aed4ec 125 #define RMU_RSTCAUSE_BUBODVDDDREG (0x1UL << 11) /**< Backup Brown Out Detector, VDD_DREG */
<> 150:02e0a0aed4ec 126 #define _RMU_RSTCAUSE_BUBODVDDDREG_SHIFT 11 /**< Shift value for RMU_BUBODVDDDREG */
<> 150:02e0a0aed4ec 127 #define _RMU_RSTCAUSE_BUBODVDDDREG_MASK 0x800UL /**< Bit mask for RMU_BUBODVDDDREG */
<> 150:02e0a0aed4ec 128 #define _RMU_RSTCAUSE_BUBODVDDDREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
<> 150:02e0a0aed4ec 129 #define RMU_RSTCAUSE_BUBODVDDDREG_DEFAULT (_RMU_RSTCAUSE_BUBODVDDDREG_DEFAULT << 11) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
<> 150:02e0a0aed4ec 130 #define RMU_RSTCAUSE_BUBODBUVIN (0x1UL << 12) /**< Backup Brown Out Detector, BU_VIN */
<> 150:02e0a0aed4ec 131 #define _RMU_RSTCAUSE_BUBODBUVIN_SHIFT 12 /**< Shift value for RMU_BUBODBUVIN */
<> 150:02e0a0aed4ec 132 #define _RMU_RSTCAUSE_BUBODBUVIN_MASK 0x1000UL /**< Bit mask for RMU_BUBODBUVIN */
<> 150:02e0a0aed4ec 133 #define _RMU_RSTCAUSE_BUBODBUVIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
<> 150:02e0a0aed4ec 134 #define RMU_RSTCAUSE_BUBODBUVIN_DEFAULT (_RMU_RSTCAUSE_BUBODBUVIN_DEFAULT << 12) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
<> 150:02e0a0aed4ec 135 #define RMU_RSTCAUSE_BUBODUNREG (0x1UL << 13) /**< Backup Brown Out Detector Unregulated Domain */
<> 150:02e0a0aed4ec 136 #define _RMU_RSTCAUSE_BUBODUNREG_SHIFT 13 /**< Shift value for RMU_BUBODUNREG */
<> 150:02e0a0aed4ec 137 #define _RMU_RSTCAUSE_BUBODUNREG_MASK 0x2000UL /**< Bit mask for RMU_BUBODUNREG */
<> 150:02e0a0aed4ec 138 #define _RMU_RSTCAUSE_BUBODUNREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
<> 150:02e0a0aed4ec 139 #define RMU_RSTCAUSE_BUBODUNREG_DEFAULT (_RMU_RSTCAUSE_BUBODUNREG_DEFAULT << 13) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
<> 150:02e0a0aed4ec 140 #define RMU_RSTCAUSE_BUBODREG (0x1UL << 14) /**< Backup Brown Out Detector Regulated Domain */
<> 150:02e0a0aed4ec 141 #define _RMU_RSTCAUSE_BUBODREG_SHIFT 14 /**< Shift value for RMU_BUBODREG */
<> 150:02e0a0aed4ec 142 #define _RMU_RSTCAUSE_BUBODREG_MASK 0x4000UL /**< Bit mask for RMU_BUBODREG */
<> 150:02e0a0aed4ec 143 #define _RMU_RSTCAUSE_BUBODREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
<> 150:02e0a0aed4ec 144 #define RMU_RSTCAUSE_BUBODREG_DEFAULT (_RMU_RSTCAUSE_BUBODREG_DEFAULT << 14) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
<> 150:02e0a0aed4ec 145 #define RMU_RSTCAUSE_BUMODERST (0x1UL << 15) /**< Backup mode reset */
<> 150:02e0a0aed4ec 146 #define _RMU_RSTCAUSE_BUMODERST_SHIFT 15 /**< Shift value for RMU_BUMODERST */
<> 150:02e0a0aed4ec 147 #define _RMU_RSTCAUSE_BUMODERST_MASK 0x8000UL /**< Bit mask for RMU_BUMODERST */
<> 150:02e0a0aed4ec 148 #define _RMU_RSTCAUSE_BUMODERST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
<> 150:02e0a0aed4ec 149 #define RMU_RSTCAUSE_BUMODERST_DEFAULT (_RMU_RSTCAUSE_BUMODERST_DEFAULT << 15) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
<> 150:02e0a0aed4ec 150
<> 150:02e0a0aed4ec 151 /* Bit fields for RMU CMD */
<> 150:02e0a0aed4ec 152 #define _RMU_CMD_RESETVALUE 0x00000000UL /**< Default value for RMU_CMD */
<> 150:02e0a0aed4ec 153 #define _RMU_CMD_MASK 0x00000001UL /**< Mask for RMU_CMD */
<> 150:02e0a0aed4ec 154 #define RMU_CMD_RCCLR (0x1UL << 0) /**< Reset Cause Clear */
<> 150:02e0a0aed4ec 155 #define _RMU_CMD_RCCLR_SHIFT 0 /**< Shift value for RMU_RCCLR */
<> 150:02e0a0aed4ec 156 #define _RMU_CMD_RCCLR_MASK 0x1UL /**< Bit mask for RMU_RCCLR */
<> 150:02e0a0aed4ec 157 #define _RMU_CMD_RCCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_CMD */
<> 150:02e0a0aed4ec 158 #define RMU_CMD_RCCLR_DEFAULT (_RMU_CMD_RCCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_CMD */
<> 150:02e0a0aed4ec 159
<> 150:02e0a0aed4ec 160 /** @} End of group EFM32WG_RMU */
<> 150:02e0a0aed4ec 161 /** @} End of group Parts */
<> 150:02e0a0aed4ec 162