Fawwaz Nadzmy / mbed-STM

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_msc.h@153:9398a535854b, 2016-12-22 (annotated)

Committer:
fwndz
Date:
Thu Dec 22 05:12:40 2016 +0000
Revision:
153:9398a535854b
Parent:
150:02e0a0aed4ec 
device target maximize

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 150:02e0a0aed4ec 1 /**************************************************************************//**
<> 150:02e0a0aed4ec 2 * @file efm32wg_msc.h
<> 150:02e0a0aed4ec 3 * @brief EFM32WG_MSC register and bit field definitions
<> 150:02e0a0aed4ec 4 * @version 5.0.0
<> 150:02e0a0aed4ec 5 ******************************************************************************
<> 150:02e0a0aed4ec 6 * @section License
<> 150:02e0a0aed4ec 7 * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 150:02e0a0aed4ec 8 ******************************************************************************
<> 150:02e0a0aed4ec 9 *
<> 150:02e0a0aed4ec 10 * Permission is granted to anyone to use this software for any purpose,
<> 150:02e0a0aed4ec 11 * including commercial applications, and to alter it and redistribute it
<> 150:02e0a0aed4ec 12 * freely, subject to the following restrictions:
<> 150:02e0a0aed4ec 13 *
<> 150:02e0a0aed4ec 14 * 1. The origin of this software must not be misrepresented; you must not
<> 150:02e0a0aed4ec 15 * claim that you wrote the original software.@n
<> 150:02e0a0aed4ec 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 150:02e0a0aed4ec 17 * misrepresented as being the original software.@n
<> 150:02e0a0aed4ec 18 * 3. This notice may not be removed or altered from any source distribution.
<> 150:02e0a0aed4ec 19 *
<> 150:02e0a0aed4ec 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 150:02e0a0aed4ec 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 150:02e0a0aed4ec 22 * providing the Software "AS IS", with no express or implied warranties of any
<> 150:02e0a0aed4ec 23 * kind, including, but not limited to, any implied warranties of
<> 150:02e0a0aed4ec 24 * merchantability or fitness for any particular purpose or warranties against
<> 150:02e0a0aed4ec 25 * infringement of any proprietary rights of a third party.
<> 150:02e0a0aed4ec 26 *
<> 150:02e0a0aed4ec 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 150:02e0a0aed4ec 28 * incidental, or special damages, or any other relief, or for any claim by
<> 150:02e0a0aed4ec 29 * any third party, arising from your use of this Software.
<> 150:02e0a0aed4ec 30 *
<> 150:02e0a0aed4ec 31 *****************************************************************************/
<> 150:02e0a0aed4ec 32 /**************************************************************************//**
<> 150:02e0a0aed4ec 33 * @addtogroup Parts
<> 150:02e0a0aed4ec 34 * @{
<> 150:02e0a0aed4ec 35 ******************************************************************************/
<> 150:02e0a0aed4ec 36 /**************************************************************************//**
<> 150:02e0a0aed4ec 37 * @defgroup EFM32WG_MSC
<> 150:02e0a0aed4ec 38 * @{
<> 150:02e0a0aed4ec 39 * @brief EFM32WG_MSC Register Declaration
<> 150:02e0a0aed4ec 40 *****************************************************************************/
<> 150:02e0a0aed4ec 41 typedef struct
<> 150:02e0a0aed4ec 42 {
<> 150:02e0a0aed4ec 43 __IOM uint32_t CTRL; /**< Memory System Control Register */
<> 150:02e0a0aed4ec 44 __IOM uint32_t READCTRL; /**< Read Control Register */
<> 150:02e0a0aed4ec 45 __IOM uint32_t WRITECTRL; /**< Write Control Register */
<> 150:02e0a0aed4ec 46 __IOM uint32_t WRITECMD; /**< Write Command Register */
<> 150:02e0a0aed4ec 47 __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */
<> 150:02e0a0aed4ec 48
<> 150:02e0a0aed4ec 49 uint32_t RESERVED0[1]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 50 __IOM uint32_t WDATA; /**< Write Data Register */
<> 150:02e0a0aed4ec 51 __IM uint32_t STATUS; /**< Status Register */
<> 150:02e0a0aed4ec 52
<> 150:02e0a0aed4ec 53 uint32_t RESERVED1[3]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 54 __IM uint32_t IF; /**< Interrupt Flag Register */
<> 150:02e0a0aed4ec 55 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
<> 150:02e0a0aed4ec 56 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
<> 150:02e0a0aed4ec 57 __IOM uint32_t IEN; /**< Interrupt Enable Register */
<> 150:02e0a0aed4ec 58 __IOM uint32_t LOCK; /**< Configuration Lock Register */
<> 150:02e0a0aed4ec 59 __IOM uint32_t CMD; /**< Command Register */
<> 150:02e0a0aed4ec 60 __IM uint32_t CACHEHITS; /**< Cache Hits Performance Counter */
<> 150:02e0a0aed4ec 61 __IM uint32_t CACHEMISSES; /**< Cache Misses Performance Counter */
<> 150:02e0a0aed4ec 62 uint32_t RESERVED2[1]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 63 __IOM uint32_t TIMEBASE; /**< Flash Write and Erase Timebase */
<> 150:02e0a0aed4ec 64 __IOM uint32_t MASSLOCK; /**< Mass Erase Lock Register */
<> 150:02e0a0aed4ec 65 } MSC_TypeDef; /** @} */
<> 150:02e0a0aed4ec 66
<> 150:02e0a0aed4ec 67 /**************************************************************************//**
<> 150:02e0a0aed4ec 68 * @defgroup EFM32WG_MSC_BitFields
<> 150:02e0a0aed4ec 69 * @{
<> 150:02e0a0aed4ec 70 *****************************************************************************/
<> 150:02e0a0aed4ec 71
<> 150:02e0a0aed4ec 72 /* Bit fields for MSC CTRL */
<> 150:02e0a0aed4ec 73 #define _MSC_CTRL_RESETVALUE 0x00000001UL /**< Default value for MSC_CTRL */
<> 150:02e0a0aed4ec 74 #define _MSC_CTRL_MASK 0x00000001UL /**< Mask for MSC_CTRL */
<> 150:02e0a0aed4ec 75 #define MSC_CTRL_BUSFAULT (0x1UL << 0) /**< Bus Fault Response Enable */
<> 150:02e0a0aed4ec 76 #define _MSC_CTRL_BUSFAULT_SHIFT 0 /**< Shift value for MSC_BUSFAULT */
<> 150:02e0a0aed4ec 77 #define _MSC_CTRL_BUSFAULT_MASK 0x1UL /**< Bit mask for MSC_BUSFAULT */
<> 150:02e0a0aed4ec 78 #define _MSC_CTRL_BUSFAULT_GENERATE 0x00000000UL /**< Mode GENERATE for MSC_CTRL */
<> 150:02e0a0aed4ec 79 #define _MSC_CTRL_BUSFAULT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */
<> 150:02e0a0aed4ec 80 #define _MSC_CTRL_BUSFAULT_IGNORE 0x00000001UL /**< Mode IGNORE for MSC_CTRL */
<> 150:02e0a0aed4ec 81 #define MSC_CTRL_BUSFAULT_GENERATE (_MSC_CTRL_BUSFAULT_GENERATE << 0) /**< Shifted mode GENERATE for MSC_CTRL */
<> 150:02e0a0aed4ec 82 #define MSC_CTRL_BUSFAULT_DEFAULT (_MSC_CTRL_BUSFAULT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CTRL */
<> 150:02e0a0aed4ec 83 #define MSC_CTRL_BUSFAULT_IGNORE (_MSC_CTRL_BUSFAULT_IGNORE << 0) /**< Shifted mode IGNORE for MSC_CTRL */
<> 150:02e0a0aed4ec 84
<> 150:02e0a0aed4ec 85 /* Bit fields for MSC READCTRL */
<> 150:02e0a0aed4ec 86 #define _MSC_READCTRL_RESETVALUE 0x00000001UL /**< Default value for MSC_READCTRL */
<> 150:02e0a0aed4ec 87 #define _MSC_READCTRL_MASK 0x000300FFUL /**< Mask for MSC_READCTRL */
<> 150:02e0a0aed4ec 88 #define _MSC_READCTRL_MODE_SHIFT 0 /**< Shift value for MSC_MODE */
<> 150:02e0a0aed4ec 89 #define _MSC_READCTRL_MODE_MASK 0x7UL /**< Bit mask for MSC_MODE */
<> 150:02e0a0aed4ec 90 #define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */
<> 150:02e0a0aed4ec 91 #define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */
<> 150:02e0a0aed4ec 92 #define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */
<> 150:02e0a0aed4ec 93 #define _MSC_READCTRL_MODE_WS0SCBTP 0x00000002UL /**< Mode WS0SCBTP for MSC_READCTRL */
<> 150:02e0a0aed4ec 94 #define _MSC_READCTRL_MODE_WS1SCBTP 0x00000003UL /**< Mode WS1SCBTP for MSC_READCTRL */
<> 150:02e0a0aed4ec 95 #define _MSC_READCTRL_MODE_WS2 0x00000004UL /**< Mode WS2 for MSC_READCTRL */
<> 150:02e0a0aed4ec 96 #define _MSC_READCTRL_MODE_WS2SCBTP 0x00000005UL /**< Mode WS2SCBTP for MSC_READCTRL */
<> 150:02e0a0aed4ec 97 #define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 0) /**< Shifted mode WS0 for MSC_READCTRL */
<> 150:02e0a0aed4ec 98 #define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_READCTRL */
<> 150:02e0a0aed4ec 99 #define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 0) /**< Shifted mode WS1 for MSC_READCTRL */
<> 150:02e0a0aed4ec 100 #define MSC_READCTRL_MODE_WS0SCBTP (_MSC_READCTRL_MODE_WS0SCBTP << 0) /**< Shifted mode WS0SCBTP for MSC_READCTRL */
<> 150:02e0a0aed4ec 101 #define MSC_READCTRL_MODE_WS1SCBTP (_MSC_READCTRL_MODE_WS1SCBTP << 0) /**< Shifted mode WS1SCBTP for MSC_READCTRL */
<> 150:02e0a0aed4ec 102 #define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 0) /**< Shifted mode WS2 for MSC_READCTRL */
<> 150:02e0a0aed4ec 103 #define MSC_READCTRL_MODE_WS2SCBTP (_MSC_READCTRL_MODE_WS2SCBTP << 0) /**< Shifted mode WS2SCBTP for MSC_READCTRL */
<> 150:02e0a0aed4ec 104 #define MSC_READCTRL_IFCDIS (0x1UL << 3) /**< Internal Flash Cache Disable */
<> 150:02e0a0aed4ec 105 #define _MSC_READCTRL_IFCDIS_SHIFT 3 /**< Shift value for MSC_IFCDIS */
<> 150:02e0a0aed4ec 106 #define _MSC_READCTRL_IFCDIS_MASK 0x8UL /**< Bit mask for MSC_IFCDIS */
<> 150:02e0a0aed4ec 107 #define _MSC_READCTRL_IFCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
<> 150:02e0a0aed4ec 108 #define MSC_READCTRL_IFCDIS_DEFAULT (_MSC_READCTRL_IFCDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_READCTRL */
<> 150:02e0a0aed4ec 109 #define MSC_READCTRL_AIDIS (0x1UL << 4) /**< Automatic Invalidate Disable */
<> 150:02e0a0aed4ec 110 #define _MSC_READCTRL_AIDIS_SHIFT 4 /**< Shift value for MSC_AIDIS */
<> 150:02e0a0aed4ec 111 #define _MSC_READCTRL_AIDIS_MASK 0x10UL /**< Bit mask for MSC_AIDIS */
<> 150:02e0a0aed4ec 112 #define _MSC_READCTRL_AIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
<> 150:02e0a0aed4ec 113 #define MSC_READCTRL_AIDIS_DEFAULT (_MSC_READCTRL_AIDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_READCTRL */
<> 150:02e0a0aed4ec 114 #define MSC_READCTRL_ICCDIS (0x1UL << 5) /**< Interrupt Context Cache Disable */
<> 150:02e0a0aed4ec 115 #define _MSC_READCTRL_ICCDIS_SHIFT 5 /**< Shift value for MSC_ICCDIS */
<> 150:02e0a0aed4ec 116 #define _MSC_READCTRL_ICCDIS_MASK 0x20UL /**< Bit mask for MSC_ICCDIS */
<> 150:02e0a0aed4ec 117 #define _MSC_READCTRL_ICCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
<> 150:02e0a0aed4ec 118 #define MSC_READCTRL_ICCDIS_DEFAULT (_MSC_READCTRL_ICCDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_READCTRL */
<> 150:02e0a0aed4ec 119 #define MSC_READCTRL_EBICDIS (0x1UL << 6) /**< External Bus Interface Cache Disable */
<> 150:02e0a0aed4ec 120 #define _MSC_READCTRL_EBICDIS_SHIFT 6 /**< Shift value for MSC_EBICDIS */
<> 150:02e0a0aed4ec 121 #define _MSC_READCTRL_EBICDIS_MASK 0x40UL /**< Bit mask for MSC_EBICDIS */
<> 150:02e0a0aed4ec 122 #define _MSC_READCTRL_EBICDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
<> 150:02e0a0aed4ec 123 #define MSC_READCTRL_EBICDIS_DEFAULT (_MSC_READCTRL_EBICDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_READCTRL */
<> 150:02e0a0aed4ec 124 #define MSC_READCTRL_RAMCEN (0x1UL << 7) /**< RAM Cache Enable */
<> 150:02e0a0aed4ec 125 #define _MSC_READCTRL_RAMCEN_SHIFT 7 /**< Shift value for MSC_RAMCEN */
<> 150:02e0a0aed4ec 126 #define _MSC_READCTRL_RAMCEN_MASK 0x80UL /**< Bit mask for MSC_RAMCEN */
<> 150:02e0a0aed4ec 127 #define _MSC_READCTRL_RAMCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
<> 150:02e0a0aed4ec 128 #define MSC_READCTRL_RAMCEN_DEFAULT (_MSC_READCTRL_RAMCEN_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_READCTRL */
<> 150:02e0a0aed4ec 129 #define _MSC_READCTRL_BUSSTRATEGY_SHIFT 16 /**< Shift value for MSC_BUSSTRATEGY */
<> 150:02e0a0aed4ec 130 #define _MSC_READCTRL_BUSSTRATEGY_MASK 0x30000UL /**< Bit mask for MSC_BUSSTRATEGY */
<> 150:02e0a0aed4ec 131 #define _MSC_READCTRL_BUSSTRATEGY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
<> 150:02e0a0aed4ec 132 #define _MSC_READCTRL_BUSSTRATEGY_CPU 0x00000000UL /**< Mode CPU for MSC_READCTRL */
<> 150:02e0a0aed4ec 133 #define _MSC_READCTRL_BUSSTRATEGY_DMA 0x00000001UL /**< Mode DMA for MSC_READCTRL */
<> 150:02e0a0aed4ec 134 #define _MSC_READCTRL_BUSSTRATEGY_DMAEM1 0x00000002UL /**< Mode DMAEM1 for MSC_READCTRL */
<> 150:02e0a0aed4ec 135 #define _MSC_READCTRL_BUSSTRATEGY_NONE 0x00000003UL /**< Mode NONE for MSC_READCTRL */
<> 150:02e0a0aed4ec 136 #define MSC_READCTRL_BUSSTRATEGY_DEFAULT (_MSC_READCTRL_BUSSTRATEGY_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_READCTRL */
<> 150:02e0a0aed4ec 137 #define MSC_READCTRL_BUSSTRATEGY_CPU (_MSC_READCTRL_BUSSTRATEGY_CPU << 16) /**< Shifted mode CPU for MSC_READCTRL */
<> 150:02e0a0aed4ec 138 #define MSC_READCTRL_BUSSTRATEGY_DMA (_MSC_READCTRL_BUSSTRATEGY_DMA << 16) /**< Shifted mode DMA for MSC_READCTRL */
<> 150:02e0a0aed4ec 139 #define MSC_READCTRL_BUSSTRATEGY_DMAEM1 (_MSC_READCTRL_BUSSTRATEGY_DMAEM1 << 16) /**< Shifted mode DMAEM1 for MSC_READCTRL */
<> 150:02e0a0aed4ec 140 #define MSC_READCTRL_BUSSTRATEGY_NONE (_MSC_READCTRL_BUSSTRATEGY_NONE << 16) /**< Shifted mode NONE for MSC_READCTRL */
<> 150:02e0a0aed4ec 141
<> 150:02e0a0aed4ec 142 /* Bit fields for MSC WRITECTRL */
<> 150:02e0a0aed4ec 143 #define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */
<> 150:02e0a0aed4ec 144 #define _MSC_WRITECTRL_MASK 0x00000003UL /**< Mask for MSC_WRITECTRL */
<> 150:02e0a0aed4ec 145 #define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */
<> 150:02e0a0aed4ec 146 #define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */
<> 150:02e0a0aed4ec 147 #define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */
<> 150:02e0a0aed4ec 148 #define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */
<> 150:02e0a0aed4ec 149 #define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */
<> 150:02e0a0aed4ec 150 #define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */
<> 150:02e0a0aed4ec 151 #define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */
<> 150:02e0a0aed4ec 152 #define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */
<> 150:02e0a0aed4ec 153 #define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */
<> 150:02e0a0aed4ec 154 #define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */
<> 150:02e0a0aed4ec 155
<> 150:02e0a0aed4ec 156 /* Bit fields for MSC WRITECMD */
<> 150:02e0a0aed4ec 157 #define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */
<> 150:02e0a0aed4ec 158 #define _MSC_WRITECMD_MASK 0x0000113FUL /**< Mask for MSC_WRITECMD */
<> 150:02e0a0aed4ec 159 #define MSC_WRITECMD_LADDRIM (0x1UL << 0) /**< Load MSC_ADDRB into ADDR */
<> 150:02e0a0aed4ec 160 #define _MSC_WRITECMD_LADDRIM_SHIFT 0 /**< Shift value for MSC_LADDRIM */
<> 150:02e0a0aed4ec 161 #define _MSC_WRITECMD_LADDRIM_MASK 0x1UL /**< Bit mask for MSC_LADDRIM */
<> 150:02e0a0aed4ec 162 #define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
<> 150:02e0a0aed4ec 163 #define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECMD */
<> 150:02e0a0aed4ec 164 #define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */
<> 150:02e0a0aed4ec 165 #define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */
<> 150:02e0a0aed4ec 166 #define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */
<> 150:02e0a0aed4ec 167 #define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
<> 150:02e0a0aed4ec 168 #define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */
<> 150:02e0a0aed4ec 169 #define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */
<> 150:02e0a0aed4ec 170 #define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */
<> 150:02e0a0aed4ec 171 #define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */
<> 150:02e0a0aed4ec 172 #define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
<> 150:02e0a0aed4ec 173 #define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */
<> 150:02e0a0aed4ec 174 #define MSC_WRITECMD_WRITEONCE (0x1UL << 3) /**< Word Write-Once Trigger */
<> 150:02e0a0aed4ec 175 #define _MSC_WRITECMD_WRITEONCE_SHIFT 3 /**< Shift value for MSC_WRITEONCE */
<> 150:02e0a0aed4ec 176 #define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL /**< Bit mask for MSC_WRITEONCE */
<> 150:02e0a0aed4ec 177 #define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
<> 150:02e0a0aed4ec 178 #define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECMD */
<> 150:02e0a0aed4ec 179 #define MSC_WRITECMD_WRITETRIG (0x1UL << 4) /**< Word Write Sequence Trigger */
<> 150:02e0a0aed4ec 180 #define _MSC_WRITECMD_WRITETRIG_SHIFT 4 /**< Shift value for MSC_WRITETRIG */
<> 150:02e0a0aed4ec 181 #define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL /**< Bit mask for MSC_WRITETRIG */
<> 150:02e0a0aed4ec 182 #define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
<> 150:02e0a0aed4ec 183 #define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */
<> 150:02e0a0aed4ec 184 #define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort erase sequence */
<> 150:02e0a0aed4ec 185 #define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */
<> 150:02e0a0aed4ec 186 #define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */
<> 150:02e0a0aed4ec 187 #define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
<> 150:02e0a0aed4ec 188 #define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */
<> 150:02e0a0aed4ec 189 #define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass erase region 0 */
<> 150:02e0a0aed4ec 190 #define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */
<> 150:02e0a0aed4ec 191 #define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */
<> 150:02e0a0aed4ec 192 #define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
<> 150:02e0a0aed4ec 193 #define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */
<> 150:02e0a0aed4ec 194 #define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA state */
<> 150:02e0a0aed4ec 195 #define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */
<> 150:02e0a0aed4ec 196 #define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */
<> 150:02e0a0aed4ec 197 #define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
<> 150:02e0a0aed4ec 198 #define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */
<> 150:02e0a0aed4ec 199
<> 150:02e0a0aed4ec 200 /* Bit fields for MSC ADDRB */
<> 150:02e0a0aed4ec 201 #define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */
<> 150:02e0a0aed4ec 202 #define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */
<> 150:02e0a0aed4ec 203 #define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */
<> 150:02e0a0aed4ec 204 #define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */
<> 150:02e0a0aed4ec 205 #define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */
<> 150:02e0a0aed4ec 206 #define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */
<> 150:02e0a0aed4ec 207
<> 150:02e0a0aed4ec 208 /* Bit fields for MSC WDATA */
<> 150:02e0a0aed4ec 209 #define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */
<> 150:02e0a0aed4ec 210 #define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */
<> 150:02e0a0aed4ec 211 #define _MSC_WDATA_WDATA_SHIFT 0 /**< Shift value for MSC_WDATA */
<> 150:02e0a0aed4ec 212 #define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_WDATA */
<> 150:02e0a0aed4ec 213 #define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */
<> 150:02e0a0aed4ec 214 #define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */
<> 150:02e0a0aed4ec 215
<> 150:02e0a0aed4ec 216 /* Bit fields for MSC STATUS */
<> 150:02e0a0aed4ec 217 #define _MSC_STATUS_RESETVALUE 0x00000008UL /**< Default value for MSC_STATUS */
<> 150:02e0a0aed4ec 218 #define _MSC_STATUS_MASK 0x0000007FUL /**< Mask for MSC_STATUS */
<> 150:02e0a0aed4ec 219 #define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */
<> 150:02e0a0aed4ec 220 #define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */
<> 150:02e0a0aed4ec 221 #define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */
<> 150:02e0a0aed4ec 222 #define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
<> 150:02e0a0aed4ec 223 #define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */
<> 150:02e0a0aed4ec 224 #define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */
<> 150:02e0a0aed4ec 225 #define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */
<> 150:02e0a0aed4ec 226 #define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */
<> 150:02e0a0aed4ec 227 #define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
<> 150:02e0a0aed4ec 228 #define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */
<> 150:02e0a0aed4ec 229 #define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */
<> 150:02e0a0aed4ec 230 #define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */
<> 150:02e0a0aed4ec 231 #define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */
<> 150:02e0a0aed4ec 232 #define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
<> 150:02e0a0aed4ec 233 #define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */
<> 150:02e0a0aed4ec 234 #define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */
<> 150:02e0a0aed4ec 235 #define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */
<> 150:02e0a0aed4ec 236 #define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */
<> 150:02e0a0aed4ec 237 #define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */
<> 150:02e0a0aed4ec 238 #define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */
<> 150:02e0a0aed4ec 239 #define MSC_STATUS_WORDTIMEOUT (0x1UL << 4) /**< Flash Write Word Timeout */
<> 150:02e0a0aed4ec 240 #define _MSC_STATUS_WORDTIMEOUT_SHIFT 4 /**< Shift value for MSC_WORDTIMEOUT */
<> 150:02e0a0aed4ec 241 #define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL /**< Bit mask for MSC_WORDTIMEOUT */
<> 150:02e0a0aed4ec 242 #define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
<> 150:02e0a0aed4ec 243 #define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */
<> 150:02e0a0aed4ec 244 #define MSC_STATUS_ERASEABORTED (0x1UL << 5) /**< The Current Flash Erase Operation Aborted */
<> 150:02e0a0aed4ec 245 #define _MSC_STATUS_ERASEABORTED_SHIFT 5 /**< Shift value for MSC_ERASEABORTED */
<> 150:02e0a0aed4ec 246 #define _MSC_STATUS_ERASEABORTED_MASK 0x20UL /**< Bit mask for MSC_ERASEABORTED */
<> 150:02e0a0aed4ec 247 #define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
<> 150:02e0a0aed4ec 248 #define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */
<> 150:02e0a0aed4ec 249 #define MSC_STATUS_PCRUNNING (0x1UL << 6) /**< Performance Counters Running */
<> 150:02e0a0aed4ec 250 #define _MSC_STATUS_PCRUNNING_SHIFT 6 /**< Shift value for MSC_PCRUNNING */
<> 150:02e0a0aed4ec 251 #define _MSC_STATUS_PCRUNNING_MASK 0x40UL /**< Bit mask for MSC_PCRUNNING */
<> 150:02e0a0aed4ec 252 #define _MSC_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
<> 150:02e0a0aed4ec 253 #define MSC_STATUS_PCRUNNING_DEFAULT (_MSC_STATUS_PCRUNNING_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */
<> 150:02e0a0aed4ec 254
<> 150:02e0a0aed4ec 255 /* Bit fields for MSC IF */
<> 150:02e0a0aed4ec 256 #define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */
<> 150:02e0a0aed4ec 257 #define _MSC_IF_MASK 0x0000000FUL /**< Mask for MSC_IF */
<> 150:02e0a0aed4ec 258 #define MSC_IF_ERASE (0x1UL << 0) /**< Erase Done Interrupt Read Flag */
<> 150:02e0a0aed4ec 259 #define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */
<> 150:02e0a0aed4ec 260 #define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */
<> 150:02e0a0aed4ec 261 #define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
<> 150:02e0a0aed4ec 262 #define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */
<> 150:02e0a0aed4ec 263 #define MSC_IF_WRITE (0x1UL << 1) /**< Write Done Interrupt Read Flag */
<> 150:02e0a0aed4ec 264 #define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */
<> 150:02e0a0aed4ec 265 #define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */
<> 150:02e0a0aed4ec 266 #define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
<> 150:02e0a0aed4ec 267 #define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */
<> 150:02e0a0aed4ec 268 #define MSC_IF_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Flag */
<> 150:02e0a0aed4ec 269 #define _MSC_IF_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */
<> 150:02e0a0aed4ec 270 #define _MSC_IF_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */
<> 150:02e0a0aed4ec 271 #define _MSC_IF_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
<> 150:02e0a0aed4ec 272 #define MSC_IF_CHOF_DEFAULT (_MSC_IF_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */
<> 150:02e0a0aed4ec 273 #define MSC_IF_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Flag */
<> 150:02e0a0aed4ec 274 #define _MSC_IF_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */
<> 150:02e0a0aed4ec 275 #define _MSC_IF_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */
<> 150:02e0a0aed4ec 276 #define _MSC_IF_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
<> 150:02e0a0aed4ec 277 #define MSC_IF_CMOF_DEFAULT (_MSC_IF_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IF */
<> 150:02e0a0aed4ec 278
<> 150:02e0a0aed4ec 279 /* Bit fields for MSC IFS */
<> 150:02e0a0aed4ec 280 #define _MSC_IFS_RESETVALUE 0x00000000UL /**< Default value for MSC_IFS */
<> 150:02e0a0aed4ec 281 #define _MSC_IFS_MASK 0x0000000FUL /**< Mask for MSC_IFS */
<> 150:02e0a0aed4ec 282 #define MSC_IFS_ERASE (0x1UL << 0) /**< Erase Done Interrupt Set */
<> 150:02e0a0aed4ec 283 #define _MSC_IFS_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */
<> 150:02e0a0aed4ec 284 #define _MSC_IFS_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */
<> 150:02e0a0aed4ec 285 #define _MSC_IFS_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
<> 150:02e0a0aed4ec 286 #define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFS */
<> 150:02e0a0aed4ec 287 #define MSC_IFS_WRITE (0x1UL << 1) /**< Write Done Interrupt Set */
<> 150:02e0a0aed4ec 288 #define _MSC_IFS_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */
<> 150:02e0a0aed4ec 289 #define _MSC_IFS_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */
<> 150:02e0a0aed4ec 290 #define _MSC_IFS_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
<> 150:02e0a0aed4ec 291 #define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFS */
<> 150:02e0a0aed4ec 292 #define MSC_IFS_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Set */
<> 150:02e0a0aed4ec 293 #define _MSC_IFS_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */
<> 150:02e0a0aed4ec 294 #define _MSC_IFS_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */
<> 150:02e0a0aed4ec 295 #define _MSC_IFS_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
<> 150:02e0a0aed4ec 296 #define MSC_IFS_CHOF_DEFAULT (_MSC_IFS_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFS */
<> 150:02e0a0aed4ec 297 #define MSC_IFS_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Set */
<> 150:02e0a0aed4ec 298 #define _MSC_IFS_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */
<> 150:02e0a0aed4ec 299 #define _MSC_IFS_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */
<> 150:02e0a0aed4ec 300 #define _MSC_IFS_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
<> 150:02e0a0aed4ec 301 #define MSC_IFS_CMOF_DEFAULT (_MSC_IFS_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFS */
<> 150:02e0a0aed4ec 302
<> 150:02e0a0aed4ec 303 /* Bit fields for MSC IFC */
<> 150:02e0a0aed4ec 304 #define _MSC_IFC_RESETVALUE 0x00000000UL /**< Default value for MSC_IFC */
<> 150:02e0a0aed4ec 305 #define _MSC_IFC_MASK 0x0000000FUL /**< Mask for MSC_IFC */
<> 150:02e0a0aed4ec 306 #define MSC_IFC_ERASE (0x1UL << 0) /**< Erase Done Interrupt Clear */
<> 150:02e0a0aed4ec 307 #define _MSC_IFC_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */
<> 150:02e0a0aed4ec 308 #define _MSC_IFC_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */
<> 150:02e0a0aed4ec 309 #define _MSC_IFC_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
<> 150:02e0a0aed4ec 310 #define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFC */
<> 150:02e0a0aed4ec 311 #define MSC_IFC_WRITE (0x1UL << 1) /**< Write Done Interrupt Clear */
<> 150:02e0a0aed4ec 312 #define _MSC_IFC_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */
<> 150:02e0a0aed4ec 313 #define _MSC_IFC_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */
<> 150:02e0a0aed4ec 314 #define _MSC_IFC_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
<> 150:02e0a0aed4ec 315 #define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFC */
<> 150:02e0a0aed4ec 316 #define MSC_IFC_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Clear */
<> 150:02e0a0aed4ec 317 #define _MSC_IFC_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */
<> 150:02e0a0aed4ec 318 #define _MSC_IFC_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */
<> 150:02e0a0aed4ec 319 #define _MSC_IFC_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
<> 150:02e0a0aed4ec 320 #define MSC_IFC_CHOF_DEFAULT (_MSC_IFC_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFC */
<> 150:02e0a0aed4ec 321 #define MSC_IFC_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Clear */
<> 150:02e0a0aed4ec 322 #define _MSC_IFC_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */
<> 150:02e0a0aed4ec 323 #define _MSC_IFC_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */
<> 150:02e0a0aed4ec 324 #define _MSC_IFC_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
<> 150:02e0a0aed4ec 325 #define MSC_IFC_CMOF_DEFAULT (_MSC_IFC_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFC */
<> 150:02e0a0aed4ec 326
<> 150:02e0a0aed4ec 327 /* Bit fields for MSC IEN */
<> 150:02e0a0aed4ec 328 #define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */
<> 150:02e0a0aed4ec 329 #define _MSC_IEN_MASK 0x0000000FUL /**< Mask for MSC_IEN */
<> 150:02e0a0aed4ec 330 #define MSC_IEN_ERASE (0x1UL << 0) /**< Erase Done Interrupt Enable */
<> 150:02e0a0aed4ec 331 #define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */
<> 150:02e0a0aed4ec 332 #define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */
<> 150:02e0a0aed4ec 333 #define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
<> 150:02e0a0aed4ec 334 #define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */
<> 150:02e0a0aed4ec 335 #define MSC_IEN_WRITE (0x1UL << 1) /**< Write Done Interrupt Enable */
<> 150:02e0a0aed4ec 336 #define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */
<> 150:02e0a0aed4ec 337 #define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */
<> 150:02e0a0aed4ec 338 #define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
<> 150:02e0a0aed4ec 339 #define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */
<> 150:02e0a0aed4ec 340 #define MSC_IEN_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Enable */
<> 150:02e0a0aed4ec 341 #define _MSC_IEN_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */
<> 150:02e0a0aed4ec 342 #define _MSC_IEN_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */
<> 150:02e0a0aed4ec 343 #define _MSC_IEN_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
<> 150:02e0a0aed4ec 344 #define MSC_IEN_CHOF_DEFAULT (_MSC_IEN_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */
<> 150:02e0a0aed4ec 345 #define MSC_IEN_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Enable */
<> 150:02e0a0aed4ec 346 #define _MSC_IEN_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */
<> 150:02e0a0aed4ec 347 #define _MSC_IEN_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */
<> 150:02e0a0aed4ec 348 #define _MSC_IEN_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
<> 150:02e0a0aed4ec 349 #define MSC_IEN_CMOF_DEFAULT (_MSC_IEN_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IEN */
<> 150:02e0a0aed4ec 350
<> 150:02e0a0aed4ec 351 /* Bit fields for MSC LOCK */
<> 150:02e0a0aed4ec 352 #define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */
<> 150:02e0a0aed4ec 353 #define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */
<> 150:02e0a0aed4ec 354 #define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */
<> 150:02e0a0aed4ec 355 #define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */
<> 150:02e0a0aed4ec 356 #define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */
<> 150:02e0a0aed4ec 357 #define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */
<> 150:02e0a0aed4ec 358 #define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */
<> 150:02e0a0aed4ec 359 #define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */
<> 150:02e0a0aed4ec 360 #define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */
<> 150:02e0a0aed4ec 361 #define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */
<> 150:02e0a0aed4ec 362 #define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */
<> 150:02e0a0aed4ec 363 #define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */
<> 150:02e0a0aed4ec 364 #define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */
<> 150:02e0a0aed4ec 365 #define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */
<> 150:02e0a0aed4ec 366
<> 150:02e0a0aed4ec 367 /* Bit fields for MSC CMD */
<> 150:02e0a0aed4ec 368 #define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */
<> 150:02e0a0aed4ec 369 #define _MSC_CMD_MASK 0x00000007UL /**< Mask for MSC_CMD */
<> 150:02e0a0aed4ec 370 #define MSC_CMD_INVCACHE (0x1UL << 0) /**< Invalidate Instruction Cache */
<> 150:02e0a0aed4ec 371 #define _MSC_CMD_INVCACHE_SHIFT 0 /**< Shift value for MSC_INVCACHE */
<> 150:02e0a0aed4ec 372 #define _MSC_CMD_INVCACHE_MASK 0x1UL /**< Bit mask for MSC_INVCACHE */
<> 150:02e0a0aed4ec 373 #define _MSC_CMD_INVCACHE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */
<> 150:02e0a0aed4ec 374 #define MSC_CMD_INVCACHE_DEFAULT (_MSC_CMD_INVCACHE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */
<> 150:02e0a0aed4ec 375 #define MSC_CMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */
<> 150:02e0a0aed4ec 376 #define _MSC_CMD_STARTPC_SHIFT 1 /**< Shift value for MSC_STARTPC */
<> 150:02e0a0aed4ec 377 #define _MSC_CMD_STARTPC_MASK 0x2UL /**< Bit mask for MSC_STARTPC */
<> 150:02e0a0aed4ec 378 #define _MSC_CMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */
<> 150:02e0a0aed4ec 379 #define MSC_CMD_STARTPC_DEFAULT (_MSC_CMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CMD */
<> 150:02e0a0aed4ec 380 #define MSC_CMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */
<> 150:02e0a0aed4ec 381 #define _MSC_CMD_STOPPC_SHIFT 2 /**< Shift value for MSC_STOPPC */
<> 150:02e0a0aed4ec 382 #define _MSC_CMD_STOPPC_MASK 0x4UL /**< Bit mask for MSC_STOPPC */
<> 150:02e0a0aed4ec 383 #define _MSC_CMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */
<> 150:02e0a0aed4ec 384 #define MSC_CMD_STOPPC_DEFAULT (_MSC_CMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CMD */
<> 150:02e0a0aed4ec 385
<> 150:02e0a0aed4ec 386 /* Bit fields for MSC CACHEHITS */
<> 150:02e0a0aed4ec 387 #define _MSC_CACHEHITS_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEHITS */
<> 150:02e0a0aed4ec 388 #define _MSC_CACHEHITS_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEHITS */
<> 150:02e0a0aed4ec 389 #define _MSC_CACHEHITS_CACHEHITS_SHIFT 0 /**< Shift value for MSC_CACHEHITS */
<> 150:02e0a0aed4ec 390 #define _MSC_CACHEHITS_CACHEHITS_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEHITS */
<> 150:02e0a0aed4ec 391 #define _MSC_CACHEHITS_CACHEHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEHITS */
<> 150:02e0a0aed4ec 392 #define MSC_CACHEHITS_CACHEHITS_DEFAULT (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEHITS */
<> 150:02e0a0aed4ec 393
<> 150:02e0a0aed4ec 394 /* Bit fields for MSC CACHEMISSES */
<> 150:02e0a0aed4ec 395 #define _MSC_CACHEMISSES_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEMISSES */
<> 150:02e0a0aed4ec 396 #define _MSC_CACHEMISSES_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEMISSES */
<> 150:02e0a0aed4ec 397 #define _MSC_CACHEMISSES_CACHEMISSES_SHIFT 0 /**< Shift value for MSC_CACHEMISSES */
<> 150:02e0a0aed4ec 398 #define _MSC_CACHEMISSES_CACHEMISSES_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEMISSES */
<> 150:02e0a0aed4ec 399 #define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEMISSES */
<> 150:02e0a0aed4ec 400 #define MSC_CACHEMISSES_CACHEMISSES_DEFAULT (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEMISSES */
<> 150:02e0a0aed4ec 401
<> 150:02e0a0aed4ec 402 /* Bit fields for MSC TIMEBASE */
<> 150:02e0a0aed4ec 403 #define _MSC_TIMEBASE_RESETVALUE 0x00000010UL /**< Default value for MSC_TIMEBASE */
<> 150:02e0a0aed4ec 404 #define _MSC_TIMEBASE_MASK 0x0001003FUL /**< Mask for MSC_TIMEBASE */
<> 150:02e0a0aed4ec 405 #define _MSC_TIMEBASE_BASE_SHIFT 0 /**< Shift value for MSC_BASE */
<> 150:02e0a0aed4ec 406 #define _MSC_TIMEBASE_BASE_MASK 0x3FUL /**< Bit mask for MSC_BASE */
<> 150:02e0a0aed4ec 407 #define _MSC_TIMEBASE_BASE_DEFAULT 0x00000010UL /**< Mode DEFAULT for MSC_TIMEBASE */
<> 150:02e0a0aed4ec 408 #define MSC_TIMEBASE_BASE_DEFAULT (_MSC_TIMEBASE_BASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_TIMEBASE */
<> 150:02e0a0aed4ec 409 #define MSC_TIMEBASE_PERIOD (0x1UL << 16) /**< Sets the timebase period */
<> 150:02e0a0aed4ec 410 #define _MSC_TIMEBASE_PERIOD_SHIFT 16 /**< Shift value for MSC_PERIOD */
<> 150:02e0a0aed4ec 411 #define _MSC_TIMEBASE_PERIOD_MASK 0x10000UL /**< Bit mask for MSC_PERIOD */
<> 150:02e0a0aed4ec 412 #define _MSC_TIMEBASE_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_TIMEBASE */
<> 150:02e0a0aed4ec 413 #define _MSC_TIMEBASE_PERIOD_1US 0x00000000UL /**< Mode 1US for MSC_TIMEBASE */
<> 150:02e0a0aed4ec 414 #define _MSC_TIMEBASE_PERIOD_5US 0x00000001UL /**< Mode 5US for MSC_TIMEBASE */
<> 150:02e0a0aed4ec 415 #define MSC_TIMEBASE_PERIOD_DEFAULT (_MSC_TIMEBASE_PERIOD_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_TIMEBASE */
<> 150:02e0a0aed4ec 416 #define MSC_TIMEBASE_PERIOD_1US (_MSC_TIMEBASE_PERIOD_1US << 16) /**< Shifted mode 1US for MSC_TIMEBASE */
<> 150:02e0a0aed4ec 417 #define MSC_TIMEBASE_PERIOD_5US (_MSC_TIMEBASE_PERIOD_5US << 16) /**< Shifted mode 5US for MSC_TIMEBASE */
<> 150:02e0a0aed4ec 418
<> 150:02e0a0aed4ec 419 /* Bit fields for MSC MASSLOCK */
<> 150:02e0a0aed4ec 420 #define _MSC_MASSLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_MASSLOCK */
<> 150:02e0a0aed4ec 421 #define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */
<> 150:02e0a0aed4ec 422 #define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */
<> 150:02e0a0aed4ec 423 #define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */
<> 150:02e0a0aed4ec 424 #define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */
<> 150:02e0a0aed4ec 425 #define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */
<> 150:02e0a0aed4ec 426 #define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */
<> 150:02e0a0aed4ec 427 #define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */
<> 150:02e0a0aed4ec 428 #define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */
<> 150:02e0a0aed4ec 429 #define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */
<> 150:02e0a0aed4ec 430 #define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */
<> 150:02e0a0aed4ec 431 #define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */
<> 150:02e0a0aed4ec 432 #define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */
<> 150:02e0a0aed4ec 433 #define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */
<> 150:02e0a0aed4ec 434
<> 150:02e0a0aed4ec 435 /** @} End of group EFM32WG_MSC */
<> 150:02e0a0aed4ec 436 /** @} End of group Parts */
<> 150:02e0a0aed4ec 437