Fawwaz Nadzmy / mbed-STM

mbed library sources. Supersedes mbed-src.

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targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_leuart.h@153:9398a535854b, 2016-12-22 (annotated)

Committer:
fwndz
Date:
Thu Dec 22 05:12:40 2016 +0000
Revision:
153:9398a535854b
Parent:
150:02e0a0aed4ec 
device target maximize

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 150:02e0a0aed4ec 1 /**************************************************************************//**
<> 150:02e0a0aed4ec 2 * @file efm32wg_leuart.h
<> 150:02e0a0aed4ec 3 * @brief EFM32WG_LEUART register and bit field definitions
<> 150:02e0a0aed4ec 4 * @version 5.0.0
<> 150:02e0a0aed4ec 5 ******************************************************************************
<> 150:02e0a0aed4ec 6 * @section License
<> 150:02e0a0aed4ec 7 * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 150:02e0a0aed4ec 8 ******************************************************************************
<> 150:02e0a0aed4ec 9 *
<> 150:02e0a0aed4ec 10 * Permission is granted to anyone to use this software for any purpose,
<> 150:02e0a0aed4ec 11 * including commercial applications, and to alter it and redistribute it
<> 150:02e0a0aed4ec 12 * freely, subject to the following restrictions:
<> 150:02e0a0aed4ec 13 *
<> 150:02e0a0aed4ec 14 * 1. The origin of this software must not be misrepresented; you must not
<> 150:02e0a0aed4ec 15 * claim that you wrote the original software.@n
<> 150:02e0a0aed4ec 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 150:02e0a0aed4ec 17 * misrepresented as being the original software.@n
<> 150:02e0a0aed4ec 18 * 3. This notice may not be removed or altered from any source distribution.
<> 150:02e0a0aed4ec 19 *
<> 150:02e0a0aed4ec 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 150:02e0a0aed4ec 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 150:02e0a0aed4ec 22 * providing the Software "AS IS", with no express or implied warranties of any
<> 150:02e0a0aed4ec 23 * kind, including, but not limited to, any implied warranties of
<> 150:02e0a0aed4ec 24 * merchantability or fitness for any particular purpose or warranties against
<> 150:02e0a0aed4ec 25 * infringement of any proprietary rights of a third party.
<> 150:02e0a0aed4ec 26 *
<> 150:02e0a0aed4ec 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 150:02e0a0aed4ec 28 * incidental, or special damages, or any other relief, or for any claim by
<> 150:02e0a0aed4ec 29 * any third party, arising from your use of this Software.
<> 150:02e0a0aed4ec 30 *
<> 150:02e0a0aed4ec 31 *****************************************************************************/
<> 150:02e0a0aed4ec 32 /**************************************************************************//**
<> 150:02e0a0aed4ec 33 * @addtogroup Parts
<> 150:02e0a0aed4ec 34 * @{
<> 150:02e0a0aed4ec 35 ******************************************************************************/
<> 150:02e0a0aed4ec 36 /**************************************************************************//**
<> 150:02e0a0aed4ec 37 * @defgroup EFM32WG_LEUART
<> 150:02e0a0aed4ec 38 * @{
<> 150:02e0a0aed4ec 39 * @brief EFM32WG_LEUART Register Declaration
<> 150:02e0a0aed4ec 40 *****************************************************************************/
<> 150:02e0a0aed4ec 41 typedef struct
<> 150:02e0a0aed4ec 42 {
<> 150:02e0a0aed4ec 43 __IOM uint32_t CTRL; /**< Control Register */
<> 150:02e0a0aed4ec 44 __IOM uint32_t CMD; /**< Command Register */
<> 150:02e0a0aed4ec 45 __IM uint32_t STATUS; /**< Status Register */
<> 150:02e0a0aed4ec 46 __IOM uint32_t CLKDIV; /**< Clock Control Register */
<> 150:02e0a0aed4ec 47 __IOM uint32_t STARTFRAME; /**< Start Frame Register */
<> 150:02e0a0aed4ec 48 __IOM uint32_t SIGFRAME; /**< Signal Frame Register */
<> 150:02e0a0aed4ec 49 __IM uint32_t RXDATAX; /**< Receive Buffer Data Extended Register */
<> 150:02e0a0aed4ec 50 __IM uint32_t RXDATA; /**< Receive Buffer Data Register */
<> 150:02e0a0aed4ec 51 __IM uint32_t RXDATAXP; /**< Receive Buffer Data Extended Peek Register */
<> 150:02e0a0aed4ec 52 __IOM uint32_t TXDATAX; /**< Transmit Buffer Data Extended Register */
<> 150:02e0a0aed4ec 53 __IOM uint32_t TXDATA; /**< Transmit Buffer Data Register */
<> 150:02e0a0aed4ec 54 __IM uint32_t IF; /**< Interrupt Flag Register */
<> 150:02e0a0aed4ec 55 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
<> 150:02e0a0aed4ec 56 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
<> 150:02e0a0aed4ec 57 __IOM uint32_t IEN; /**< Interrupt Enable Register */
<> 150:02e0a0aed4ec 58 __IOM uint32_t PULSECTRL; /**< Pulse Control Register */
<> 150:02e0a0aed4ec 59
<> 150:02e0a0aed4ec 60 __IOM uint32_t FREEZE; /**< Freeze Register */
<> 150:02e0a0aed4ec 61 __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
<> 150:02e0a0aed4ec 62
<> 150:02e0a0aed4ec 63 uint32_t RESERVED0[3]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 64 __IOM uint32_t ROUTE; /**< I/O Routing Register */
<> 150:02e0a0aed4ec 65 uint32_t RESERVED1[21]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 66 __IOM uint32_t INPUT; /**< LEUART Input Register */
<> 150:02e0a0aed4ec 67 } LEUART_TypeDef; /** @} */
<> 150:02e0a0aed4ec 68
<> 150:02e0a0aed4ec 69 /**************************************************************************//**
<> 150:02e0a0aed4ec 70 * @defgroup EFM32WG_LEUART_BitFields
<> 150:02e0a0aed4ec 71 * @{
<> 150:02e0a0aed4ec 72 *****************************************************************************/
<> 150:02e0a0aed4ec 73
<> 150:02e0a0aed4ec 74 /* Bit fields for LEUART CTRL */
<> 150:02e0a0aed4ec 75 #define _LEUART_CTRL_RESETVALUE 0x00000000UL /**< Default value for LEUART_CTRL */
<> 150:02e0a0aed4ec 76 #define _LEUART_CTRL_MASK 0x0000FFFFUL /**< Mask for LEUART_CTRL */
<> 150:02e0a0aed4ec 77 #define LEUART_CTRL_AUTOTRI (0x1UL << 0) /**< Automatic Transmitter Tristate */
<> 150:02e0a0aed4ec 78 #define _LEUART_CTRL_AUTOTRI_SHIFT 0 /**< Shift value for LEUART_AUTOTRI */
<> 150:02e0a0aed4ec 79 #define _LEUART_CTRL_AUTOTRI_MASK 0x1UL /**< Bit mask for LEUART_AUTOTRI */
<> 150:02e0a0aed4ec 80 #define _LEUART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
<> 150:02e0a0aed4ec 81 #define LEUART_CTRL_AUTOTRI_DEFAULT (_LEUART_CTRL_AUTOTRI_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_CTRL */
<> 150:02e0a0aed4ec 82 #define LEUART_CTRL_DATABITS (0x1UL << 1) /**< Data-Bit Mode */
<> 150:02e0a0aed4ec 83 #define _LEUART_CTRL_DATABITS_SHIFT 1 /**< Shift value for LEUART_DATABITS */
<> 150:02e0a0aed4ec 84 #define _LEUART_CTRL_DATABITS_MASK 0x2UL /**< Bit mask for LEUART_DATABITS */
<> 150:02e0a0aed4ec 85 #define _LEUART_CTRL_DATABITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
<> 150:02e0a0aed4ec 86 #define _LEUART_CTRL_DATABITS_EIGHT 0x00000000UL /**< Mode EIGHT for LEUART_CTRL */
<> 150:02e0a0aed4ec 87 #define _LEUART_CTRL_DATABITS_NINE 0x00000001UL /**< Mode NINE for LEUART_CTRL */
<> 150:02e0a0aed4ec 88 #define LEUART_CTRL_DATABITS_DEFAULT (_LEUART_CTRL_DATABITS_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_CTRL */
<> 150:02e0a0aed4ec 89 #define LEUART_CTRL_DATABITS_EIGHT (_LEUART_CTRL_DATABITS_EIGHT << 1) /**< Shifted mode EIGHT for LEUART_CTRL */
<> 150:02e0a0aed4ec 90 #define LEUART_CTRL_DATABITS_NINE (_LEUART_CTRL_DATABITS_NINE << 1) /**< Shifted mode NINE for LEUART_CTRL */
<> 150:02e0a0aed4ec 91 #define _LEUART_CTRL_PARITY_SHIFT 2 /**< Shift value for LEUART_PARITY */
<> 150:02e0a0aed4ec 92 #define _LEUART_CTRL_PARITY_MASK 0xCUL /**< Bit mask for LEUART_PARITY */
<> 150:02e0a0aed4ec 93 #define _LEUART_CTRL_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
<> 150:02e0a0aed4ec 94 #define _LEUART_CTRL_PARITY_NONE 0x00000000UL /**< Mode NONE for LEUART_CTRL */
<> 150:02e0a0aed4ec 95 #define _LEUART_CTRL_PARITY_EVEN 0x00000002UL /**< Mode EVEN for LEUART_CTRL */
<> 150:02e0a0aed4ec 96 #define _LEUART_CTRL_PARITY_ODD 0x00000003UL /**< Mode ODD for LEUART_CTRL */
<> 150:02e0a0aed4ec 97 #define LEUART_CTRL_PARITY_DEFAULT (_LEUART_CTRL_PARITY_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_CTRL */
<> 150:02e0a0aed4ec 98 #define LEUART_CTRL_PARITY_NONE (_LEUART_CTRL_PARITY_NONE << 2) /**< Shifted mode NONE for LEUART_CTRL */
<> 150:02e0a0aed4ec 99 #define LEUART_CTRL_PARITY_EVEN (_LEUART_CTRL_PARITY_EVEN << 2) /**< Shifted mode EVEN for LEUART_CTRL */
<> 150:02e0a0aed4ec 100 #define LEUART_CTRL_PARITY_ODD (_LEUART_CTRL_PARITY_ODD << 2) /**< Shifted mode ODD for LEUART_CTRL */
<> 150:02e0a0aed4ec 101 #define LEUART_CTRL_STOPBITS (0x1UL << 4) /**< Stop-Bit Mode */
<> 150:02e0a0aed4ec 102 #define _LEUART_CTRL_STOPBITS_SHIFT 4 /**< Shift value for LEUART_STOPBITS */
<> 150:02e0a0aed4ec 103 #define _LEUART_CTRL_STOPBITS_MASK 0x10UL /**< Bit mask for LEUART_STOPBITS */
<> 150:02e0a0aed4ec 104 #define _LEUART_CTRL_STOPBITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
<> 150:02e0a0aed4ec 105 #define _LEUART_CTRL_STOPBITS_ONE 0x00000000UL /**< Mode ONE for LEUART_CTRL */
<> 150:02e0a0aed4ec 106 #define _LEUART_CTRL_STOPBITS_TWO 0x00000001UL /**< Mode TWO for LEUART_CTRL */
<> 150:02e0a0aed4ec 107 #define LEUART_CTRL_STOPBITS_DEFAULT (_LEUART_CTRL_STOPBITS_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_CTRL */
<> 150:02e0a0aed4ec 108 #define LEUART_CTRL_STOPBITS_ONE (_LEUART_CTRL_STOPBITS_ONE << 4) /**< Shifted mode ONE for LEUART_CTRL */
<> 150:02e0a0aed4ec 109 #define LEUART_CTRL_STOPBITS_TWO (_LEUART_CTRL_STOPBITS_TWO << 4) /**< Shifted mode TWO for LEUART_CTRL */
<> 150:02e0a0aed4ec 110 #define LEUART_CTRL_INV (0x1UL << 5) /**< Invert Input And Output */
<> 150:02e0a0aed4ec 111 #define _LEUART_CTRL_INV_SHIFT 5 /**< Shift value for LEUART_INV */
<> 150:02e0a0aed4ec 112 #define _LEUART_CTRL_INV_MASK 0x20UL /**< Bit mask for LEUART_INV */
<> 150:02e0a0aed4ec 113 #define _LEUART_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
<> 150:02e0a0aed4ec 114 #define LEUART_CTRL_INV_DEFAULT (_LEUART_CTRL_INV_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_CTRL */
<> 150:02e0a0aed4ec 115 #define LEUART_CTRL_ERRSDMA (0x1UL << 6) /**< Clear RX DMA On Error */
<> 150:02e0a0aed4ec 116 #define _LEUART_CTRL_ERRSDMA_SHIFT 6 /**< Shift value for LEUART_ERRSDMA */
<> 150:02e0a0aed4ec 117 #define _LEUART_CTRL_ERRSDMA_MASK 0x40UL /**< Bit mask for LEUART_ERRSDMA */
<> 150:02e0a0aed4ec 118 #define _LEUART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
<> 150:02e0a0aed4ec 119 #define LEUART_CTRL_ERRSDMA_DEFAULT (_LEUART_CTRL_ERRSDMA_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_CTRL */
<> 150:02e0a0aed4ec 120 #define LEUART_CTRL_LOOPBK (0x1UL << 7) /**< Loopback Enable */
<> 150:02e0a0aed4ec 121 #define _LEUART_CTRL_LOOPBK_SHIFT 7 /**< Shift value for LEUART_LOOPBK */
<> 150:02e0a0aed4ec 122 #define _LEUART_CTRL_LOOPBK_MASK 0x80UL /**< Bit mask for LEUART_LOOPBK */
<> 150:02e0a0aed4ec 123 #define _LEUART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
<> 150:02e0a0aed4ec 124 #define LEUART_CTRL_LOOPBK_DEFAULT (_LEUART_CTRL_LOOPBK_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_CTRL */
<> 150:02e0a0aed4ec 125 #define LEUART_CTRL_SFUBRX (0x1UL << 8) /**< Start-Frame UnBlock RX */
<> 150:02e0a0aed4ec 126 #define _LEUART_CTRL_SFUBRX_SHIFT 8 /**< Shift value for LEUART_SFUBRX */
<> 150:02e0a0aed4ec 127 #define _LEUART_CTRL_SFUBRX_MASK 0x100UL /**< Bit mask for LEUART_SFUBRX */
<> 150:02e0a0aed4ec 128 #define _LEUART_CTRL_SFUBRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
<> 150:02e0a0aed4ec 129 #define LEUART_CTRL_SFUBRX_DEFAULT (_LEUART_CTRL_SFUBRX_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_CTRL */
<> 150:02e0a0aed4ec 130 #define LEUART_CTRL_MPM (0x1UL << 9) /**< Multi-Processor Mode */
<> 150:02e0a0aed4ec 131 #define _LEUART_CTRL_MPM_SHIFT 9 /**< Shift value for LEUART_MPM */
<> 150:02e0a0aed4ec 132 #define _LEUART_CTRL_MPM_MASK 0x200UL /**< Bit mask for LEUART_MPM */
<> 150:02e0a0aed4ec 133 #define _LEUART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
<> 150:02e0a0aed4ec 134 #define LEUART_CTRL_MPM_DEFAULT (_LEUART_CTRL_MPM_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_CTRL */
<> 150:02e0a0aed4ec 135 #define LEUART_CTRL_MPAB (0x1UL << 10) /**< Multi-Processor Address-Bit */
<> 150:02e0a0aed4ec 136 #define _LEUART_CTRL_MPAB_SHIFT 10 /**< Shift value for LEUART_MPAB */
<> 150:02e0a0aed4ec 137 #define _LEUART_CTRL_MPAB_MASK 0x400UL /**< Bit mask for LEUART_MPAB */
<> 150:02e0a0aed4ec 138 #define _LEUART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
<> 150:02e0a0aed4ec 139 #define LEUART_CTRL_MPAB_DEFAULT (_LEUART_CTRL_MPAB_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_CTRL */
<> 150:02e0a0aed4ec 140 #define LEUART_CTRL_BIT8DV (0x1UL << 11) /**< Bit 8 Default Value */
<> 150:02e0a0aed4ec 141 #define _LEUART_CTRL_BIT8DV_SHIFT 11 /**< Shift value for LEUART_BIT8DV */
<> 150:02e0a0aed4ec 142 #define _LEUART_CTRL_BIT8DV_MASK 0x800UL /**< Bit mask for LEUART_BIT8DV */
<> 150:02e0a0aed4ec 143 #define _LEUART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
<> 150:02e0a0aed4ec 144 #define LEUART_CTRL_BIT8DV_DEFAULT (_LEUART_CTRL_BIT8DV_DEFAULT << 11) /**< Shifted mode DEFAULT for LEUART_CTRL */
<> 150:02e0a0aed4ec 145 #define LEUART_CTRL_RXDMAWU (0x1UL << 12) /**< RX DMA Wakeup */
<> 150:02e0a0aed4ec 146 #define _LEUART_CTRL_RXDMAWU_SHIFT 12 /**< Shift value for LEUART_RXDMAWU */
<> 150:02e0a0aed4ec 147 #define _LEUART_CTRL_RXDMAWU_MASK 0x1000UL /**< Bit mask for LEUART_RXDMAWU */
<> 150:02e0a0aed4ec 148 #define _LEUART_CTRL_RXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
<> 150:02e0a0aed4ec 149 #define LEUART_CTRL_RXDMAWU_DEFAULT (_LEUART_CTRL_RXDMAWU_DEFAULT << 12) /**< Shifted mode DEFAULT for LEUART_CTRL */
<> 150:02e0a0aed4ec 150 #define LEUART_CTRL_TXDMAWU (0x1UL << 13) /**< TX DMA Wakeup */
<> 150:02e0a0aed4ec 151 #define _LEUART_CTRL_TXDMAWU_SHIFT 13 /**< Shift value for LEUART_TXDMAWU */
<> 150:02e0a0aed4ec 152 #define _LEUART_CTRL_TXDMAWU_MASK 0x2000UL /**< Bit mask for LEUART_TXDMAWU */
<> 150:02e0a0aed4ec 153 #define _LEUART_CTRL_TXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
<> 150:02e0a0aed4ec 154 #define LEUART_CTRL_TXDMAWU_DEFAULT (_LEUART_CTRL_TXDMAWU_DEFAULT << 13) /**< Shifted mode DEFAULT for LEUART_CTRL */
<> 150:02e0a0aed4ec 155 #define _LEUART_CTRL_TXDELAY_SHIFT 14 /**< Shift value for LEUART_TXDELAY */
<> 150:02e0a0aed4ec 156 #define _LEUART_CTRL_TXDELAY_MASK 0xC000UL /**< Bit mask for LEUART_TXDELAY */
<> 150:02e0a0aed4ec 157 #define _LEUART_CTRL_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
<> 150:02e0a0aed4ec 158 #define _LEUART_CTRL_TXDELAY_NONE 0x00000000UL /**< Mode NONE for LEUART_CTRL */
<> 150:02e0a0aed4ec 159 #define _LEUART_CTRL_TXDELAY_SINGLE 0x00000001UL /**< Mode SINGLE for LEUART_CTRL */
<> 150:02e0a0aed4ec 160 #define _LEUART_CTRL_TXDELAY_DOUBLE 0x00000002UL /**< Mode DOUBLE for LEUART_CTRL */
<> 150:02e0a0aed4ec 161 #define _LEUART_CTRL_TXDELAY_TRIPLE 0x00000003UL /**< Mode TRIPLE for LEUART_CTRL */
<> 150:02e0a0aed4ec 162 #define LEUART_CTRL_TXDELAY_DEFAULT (_LEUART_CTRL_TXDELAY_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_CTRL */
<> 150:02e0a0aed4ec 163 #define LEUART_CTRL_TXDELAY_NONE (_LEUART_CTRL_TXDELAY_NONE << 14) /**< Shifted mode NONE for LEUART_CTRL */
<> 150:02e0a0aed4ec 164 #define LEUART_CTRL_TXDELAY_SINGLE (_LEUART_CTRL_TXDELAY_SINGLE << 14) /**< Shifted mode SINGLE for LEUART_CTRL */
<> 150:02e0a0aed4ec 165 #define LEUART_CTRL_TXDELAY_DOUBLE (_LEUART_CTRL_TXDELAY_DOUBLE << 14) /**< Shifted mode DOUBLE for LEUART_CTRL */
<> 150:02e0a0aed4ec 166 #define LEUART_CTRL_TXDELAY_TRIPLE (_LEUART_CTRL_TXDELAY_TRIPLE << 14) /**< Shifted mode TRIPLE for LEUART_CTRL */
<> 150:02e0a0aed4ec 167
<> 150:02e0a0aed4ec 168 /* Bit fields for LEUART CMD */
<> 150:02e0a0aed4ec 169 #define _LEUART_CMD_RESETVALUE 0x00000000UL /**< Default value for LEUART_CMD */
<> 150:02e0a0aed4ec 170 #define _LEUART_CMD_MASK 0x000000FFUL /**< Mask for LEUART_CMD */
<> 150:02e0a0aed4ec 171 #define LEUART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */
<> 150:02e0a0aed4ec 172 #define _LEUART_CMD_RXEN_SHIFT 0 /**< Shift value for LEUART_RXEN */
<> 150:02e0a0aed4ec 173 #define _LEUART_CMD_RXEN_MASK 0x1UL /**< Bit mask for LEUART_RXEN */
<> 150:02e0a0aed4ec 174 #define _LEUART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
<> 150:02e0a0aed4ec 175 #define LEUART_CMD_RXEN_DEFAULT (_LEUART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_CMD */
<> 150:02e0a0aed4ec 176 #define LEUART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */
<> 150:02e0a0aed4ec 177 #define _LEUART_CMD_RXDIS_SHIFT 1 /**< Shift value for LEUART_RXDIS */
<> 150:02e0a0aed4ec 178 #define _LEUART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for LEUART_RXDIS */
<> 150:02e0a0aed4ec 179 #define _LEUART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
<> 150:02e0a0aed4ec 180 #define LEUART_CMD_RXDIS_DEFAULT (_LEUART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_CMD */
<> 150:02e0a0aed4ec 181 #define LEUART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */
<> 150:02e0a0aed4ec 182 #define _LEUART_CMD_TXEN_SHIFT 2 /**< Shift value for LEUART_TXEN */
<> 150:02e0a0aed4ec 183 #define _LEUART_CMD_TXEN_MASK 0x4UL /**< Bit mask for LEUART_TXEN */
<> 150:02e0a0aed4ec 184 #define _LEUART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
<> 150:02e0a0aed4ec 185 #define LEUART_CMD_TXEN_DEFAULT (_LEUART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_CMD */
<> 150:02e0a0aed4ec 186 #define LEUART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */
<> 150:02e0a0aed4ec 187 #define _LEUART_CMD_TXDIS_SHIFT 3 /**< Shift value for LEUART_TXDIS */
<> 150:02e0a0aed4ec 188 #define _LEUART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for LEUART_TXDIS */
<> 150:02e0a0aed4ec 189 #define _LEUART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
<> 150:02e0a0aed4ec 190 #define LEUART_CMD_TXDIS_DEFAULT (_LEUART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_CMD */
<> 150:02e0a0aed4ec 191 #define LEUART_CMD_RXBLOCKEN (0x1UL << 4) /**< Receiver Block Enable */
<> 150:02e0a0aed4ec 192 #define _LEUART_CMD_RXBLOCKEN_SHIFT 4 /**< Shift value for LEUART_RXBLOCKEN */
<> 150:02e0a0aed4ec 193 #define _LEUART_CMD_RXBLOCKEN_MASK 0x10UL /**< Bit mask for LEUART_RXBLOCKEN */
<> 150:02e0a0aed4ec 194 #define _LEUART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
<> 150:02e0a0aed4ec 195 #define LEUART_CMD_RXBLOCKEN_DEFAULT (_LEUART_CMD_RXBLOCKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_CMD */
<> 150:02e0a0aed4ec 196 #define LEUART_CMD_RXBLOCKDIS (0x1UL << 5) /**< Receiver Block Disable */
<> 150:02e0a0aed4ec 197 #define _LEUART_CMD_RXBLOCKDIS_SHIFT 5 /**< Shift value for LEUART_RXBLOCKDIS */
<> 150:02e0a0aed4ec 198 #define _LEUART_CMD_RXBLOCKDIS_MASK 0x20UL /**< Bit mask for LEUART_RXBLOCKDIS */
<> 150:02e0a0aed4ec 199 #define _LEUART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
<> 150:02e0a0aed4ec 200 #define LEUART_CMD_RXBLOCKDIS_DEFAULT (_LEUART_CMD_RXBLOCKDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_CMD */
<> 150:02e0a0aed4ec 201 #define LEUART_CMD_CLEARTX (0x1UL << 6) /**< Clear TX */
<> 150:02e0a0aed4ec 202 #define _LEUART_CMD_CLEARTX_SHIFT 6 /**< Shift value for LEUART_CLEARTX */
<> 150:02e0a0aed4ec 203 #define _LEUART_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for LEUART_CLEARTX */
<> 150:02e0a0aed4ec 204 #define _LEUART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
<> 150:02e0a0aed4ec 205 #define LEUART_CMD_CLEARTX_DEFAULT (_LEUART_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_CMD */
<> 150:02e0a0aed4ec 206 #define LEUART_CMD_CLEARRX (0x1UL << 7) /**< Clear RX */
<> 150:02e0a0aed4ec 207 #define _LEUART_CMD_CLEARRX_SHIFT 7 /**< Shift value for LEUART_CLEARRX */
<> 150:02e0a0aed4ec 208 #define _LEUART_CMD_CLEARRX_MASK 0x80UL /**< Bit mask for LEUART_CLEARRX */
<> 150:02e0a0aed4ec 209 #define _LEUART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
<> 150:02e0a0aed4ec 210 #define LEUART_CMD_CLEARRX_DEFAULT (_LEUART_CMD_CLEARRX_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_CMD */
<> 150:02e0a0aed4ec 211
<> 150:02e0a0aed4ec 212 /* Bit fields for LEUART STATUS */
<> 150:02e0a0aed4ec 213 #define _LEUART_STATUS_RESETVALUE 0x00000010UL /**< Default value for LEUART_STATUS */
<> 150:02e0a0aed4ec 214 #define _LEUART_STATUS_MASK 0x0000003FUL /**< Mask for LEUART_STATUS */
<> 150:02e0a0aed4ec 215 #define LEUART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */
<> 150:02e0a0aed4ec 216 #define _LEUART_STATUS_RXENS_SHIFT 0 /**< Shift value for LEUART_RXENS */
<> 150:02e0a0aed4ec 217 #define _LEUART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for LEUART_RXENS */
<> 150:02e0a0aed4ec 218 #define _LEUART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */
<> 150:02e0a0aed4ec 219 #define LEUART_STATUS_RXENS_DEFAULT (_LEUART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_STATUS */
<> 150:02e0a0aed4ec 220 #define LEUART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */
<> 150:02e0a0aed4ec 221 #define _LEUART_STATUS_TXENS_SHIFT 1 /**< Shift value for LEUART_TXENS */
<> 150:02e0a0aed4ec 222 #define _LEUART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for LEUART_TXENS */
<> 150:02e0a0aed4ec 223 #define _LEUART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */
<> 150:02e0a0aed4ec 224 #define LEUART_STATUS_TXENS_DEFAULT (_LEUART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_STATUS */
<> 150:02e0a0aed4ec 225 #define LEUART_STATUS_RXBLOCK (0x1UL << 2) /**< Block Incoming Data */
<> 150:02e0a0aed4ec 226 #define _LEUART_STATUS_RXBLOCK_SHIFT 2 /**< Shift value for LEUART_RXBLOCK */
<> 150:02e0a0aed4ec 227 #define _LEUART_STATUS_RXBLOCK_MASK 0x4UL /**< Bit mask for LEUART_RXBLOCK */
<> 150:02e0a0aed4ec 228 #define _LEUART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */
<> 150:02e0a0aed4ec 229 #define LEUART_STATUS_RXBLOCK_DEFAULT (_LEUART_STATUS_RXBLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_STATUS */
<> 150:02e0a0aed4ec 230 #define LEUART_STATUS_TXC (0x1UL << 3) /**< TX Complete */
<> 150:02e0a0aed4ec 231 #define _LEUART_STATUS_TXC_SHIFT 3 /**< Shift value for LEUART_TXC */
<> 150:02e0a0aed4ec 232 #define _LEUART_STATUS_TXC_MASK 0x8UL /**< Bit mask for LEUART_TXC */
<> 150:02e0a0aed4ec 233 #define _LEUART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */
<> 150:02e0a0aed4ec 234 #define LEUART_STATUS_TXC_DEFAULT (_LEUART_STATUS_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_STATUS */
<> 150:02e0a0aed4ec 235 #define LEUART_STATUS_TXBL (0x1UL << 4) /**< TX Buffer Level */
<> 150:02e0a0aed4ec 236 #define _LEUART_STATUS_TXBL_SHIFT 4 /**< Shift value for LEUART_TXBL */
<> 150:02e0a0aed4ec 237 #define _LEUART_STATUS_TXBL_MASK 0x10UL /**< Bit mask for LEUART_TXBL */
<> 150:02e0a0aed4ec 238 #define _LEUART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for LEUART_STATUS */
<> 150:02e0a0aed4ec 239 #define LEUART_STATUS_TXBL_DEFAULT (_LEUART_STATUS_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_STATUS */
<> 150:02e0a0aed4ec 240 #define LEUART_STATUS_RXDATAV (0x1UL << 5) /**< RX Data Valid */
<> 150:02e0a0aed4ec 241 #define _LEUART_STATUS_RXDATAV_SHIFT 5 /**< Shift value for LEUART_RXDATAV */
<> 150:02e0a0aed4ec 242 #define _LEUART_STATUS_RXDATAV_MASK 0x20UL /**< Bit mask for LEUART_RXDATAV */
<> 150:02e0a0aed4ec 243 #define _LEUART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */
<> 150:02e0a0aed4ec 244 #define LEUART_STATUS_RXDATAV_DEFAULT (_LEUART_STATUS_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_STATUS */
<> 150:02e0a0aed4ec 245
<> 150:02e0a0aed4ec 246 /* Bit fields for LEUART CLKDIV */
<> 150:02e0a0aed4ec 247 #define _LEUART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for LEUART_CLKDIV */
<> 150:02e0a0aed4ec 248 #define _LEUART_CLKDIV_MASK 0x00007FF8UL /**< Mask for LEUART_CLKDIV */
<> 150:02e0a0aed4ec 249 #define _LEUART_CLKDIV_DIV_SHIFT 3 /**< Shift value for LEUART_DIV */
<> 150:02e0a0aed4ec 250 #define _LEUART_CLKDIV_DIV_MASK 0x7FF8UL /**< Bit mask for LEUART_DIV */
<> 150:02e0a0aed4ec 251 #define _LEUART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CLKDIV */
<> 150:02e0a0aed4ec 252 #define LEUART_CLKDIV_DIV_DEFAULT (_LEUART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_CLKDIV */
<> 150:02e0a0aed4ec 253
<> 150:02e0a0aed4ec 254 /* Bit fields for LEUART STARTFRAME */
<> 150:02e0a0aed4ec 255 #define _LEUART_STARTFRAME_RESETVALUE 0x00000000UL /**< Default value for LEUART_STARTFRAME */
<> 150:02e0a0aed4ec 256 #define _LEUART_STARTFRAME_MASK 0x000001FFUL /**< Mask for LEUART_STARTFRAME */
<> 150:02e0a0aed4ec 257 #define _LEUART_STARTFRAME_STARTFRAME_SHIFT 0 /**< Shift value for LEUART_STARTFRAME */
<> 150:02e0a0aed4ec 258 #define _LEUART_STARTFRAME_STARTFRAME_MASK 0x1FFUL /**< Bit mask for LEUART_STARTFRAME */
<> 150:02e0a0aed4ec 259 #define _LEUART_STARTFRAME_STARTFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STARTFRAME */
<> 150:02e0a0aed4ec 260 #define LEUART_STARTFRAME_STARTFRAME_DEFAULT (_LEUART_STARTFRAME_STARTFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_STARTFRAME */
<> 150:02e0a0aed4ec 261
<> 150:02e0a0aed4ec 262 /* Bit fields for LEUART SIGFRAME */
<> 150:02e0a0aed4ec 263 #define _LEUART_SIGFRAME_RESETVALUE 0x00000000UL /**< Default value for LEUART_SIGFRAME */
<> 150:02e0a0aed4ec 264 #define _LEUART_SIGFRAME_MASK 0x000001FFUL /**< Mask for LEUART_SIGFRAME */
<> 150:02e0a0aed4ec 265 #define _LEUART_SIGFRAME_SIGFRAME_SHIFT 0 /**< Shift value for LEUART_SIGFRAME */
<> 150:02e0a0aed4ec 266 #define _LEUART_SIGFRAME_SIGFRAME_MASK 0x1FFUL /**< Bit mask for LEUART_SIGFRAME */
<> 150:02e0a0aed4ec 267 #define _LEUART_SIGFRAME_SIGFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SIGFRAME */
<> 150:02e0a0aed4ec 268 #define LEUART_SIGFRAME_SIGFRAME_DEFAULT (_LEUART_SIGFRAME_SIGFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_SIGFRAME */
<> 150:02e0a0aed4ec 269
<> 150:02e0a0aed4ec 270 /* Bit fields for LEUART RXDATAX */
<> 150:02e0a0aed4ec 271 #define _LEUART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for LEUART_RXDATAX */
<> 150:02e0a0aed4ec 272 #define _LEUART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for LEUART_RXDATAX */
<> 150:02e0a0aed4ec 273 #define _LEUART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for LEUART_RXDATA */
<> 150:02e0a0aed4ec 274 #define _LEUART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for LEUART_RXDATA */
<> 150:02e0a0aed4ec 275 #define _LEUART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAX */
<> 150:02e0a0aed4ec 276 #define LEUART_RXDATAX_RXDATA_DEFAULT (_LEUART_RXDATAX_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_RXDATAX */
<> 150:02e0a0aed4ec 277 #define LEUART_RXDATAX_PERR (0x1UL << 14) /**< Receive Data Parity Error */
<> 150:02e0a0aed4ec 278 #define _LEUART_RXDATAX_PERR_SHIFT 14 /**< Shift value for LEUART_PERR */
<> 150:02e0a0aed4ec 279 #define _LEUART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for LEUART_PERR */
<> 150:02e0a0aed4ec 280 #define _LEUART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAX */
<> 150:02e0a0aed4ec 281 #define LEUART_RXDATAX_PERR_DEFAULT (_LEUART_RXDATAX_PERR_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_RXDATAX */
<> 150:02e0a0aed4ec 282 #define LEUART_RXDATAX_FERR (0x1UL << 15) /**< Receive Data Framing Error */
<> 150:02e0a0aed4ec 283 #define _LEUART_RXDATAX_FERR_SHIFT 15 /**< Shift value for LEUART_FERR */
<> 150:02e0a0aed4ec 284 #define _LEUART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for LEUART_FERR */
<> 150:02e0a0aed4ec 285 #define _LEUART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAX */
<> 150:02e0a0aed4ec 286 #define LEUART_RXDATAX_FERR_DEFAULT (_LEUART_RXDATAX_FERR_DEFAULT << 15) /**< Shifted mode DEFAULT for LEUART_RXDATAX */
<> 150:02e0a0aed4ec 287
<> 150:02e0a0aed4ec 288 /* Bit fields for LEUART RXDATA */
<> 150:02e0a0aed4ec 289 #define _LEUART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for LEUART_RXDATA */
<> 150:02e0a0aed4ec 290 #define _LEUART_RXDATA_MASK 0x000000FFUL /**< Mask for LEUART_RXDATA */
<> 150:02e0a0aed4ec 291 #define _LEUART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for LEUART_RXDATA */
<> 150:02e0a0aed4ec 292 #define _LEUART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for LEUART_RXDATA */
<> 150:02e0a0aed4ec 293 #define _LEUART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATA */
<> 150:02e0a0aed4ec 294 #define LEUART_RXDATA_RXDATA_DEFAULT (_LEUART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_RXDATA */
<> 150:02e0a0aed4ec 295
<> 150:02e0a0aed4ec 296 /* Bit fields for LEUART RXDATAXP */
<> 150:02e0a0aed4ec 297 #define _LEUART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for LEUART_RXDATAXP */
<> 150:02e0a0aed4ec 298 #define _LEUART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for LEUART_RXDATAXP */
<> 150:02e0a0aed4ec 299 #define _LEUART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for LEUART_RXDATAP */
<> 150:02e0a0aed4ec 300 #define _LEUART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for LEUART_RXDATAP */
<> 150:02e0a0aed4ec 301 #define _LEUART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAXP */
<> 150:02e0a0aed4ec 302 #define LEUART_RXDATAXP_RXDATAP_DEFAULT (_LEUART_RXDATAXP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */
<> 150:02e0a0aed4ec 303 #define LEUART_RXDATAXP_PERRP (0x1UL << 14) /**< Receive Data Parity Error Peek */
<> 150:02e0a0aed4ec 304 #define _LEUART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for LEUART_PERRP */
<> 150:02e0a0aed4ec 305 #define _LEUART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for LEUART_PERRP */
<> 150:02e0a0aed4ec 306 #define _LEUART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAXP */
<> 150:02e0a0aed4ec 307 #define LEUART_RXDATAXP_PERRP_DEFAULT (_LEUART_RXDATAXP_PERRP_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */
<> 150:02e0a0aed4ec 308 #define LEUART_RXDATAXP_FERRP (0x1UL << 15) /**< Receive Data Framing Error Peek */
<> 150:02e0a0aed4ec 309 #define _LEUART_RXDATAXP_FERRP_SHIFT 15 /**< Shift value for LEUART_FERRP */
<> 150:02e0a0aed4ec 310 #define _LEUART_RXDATAXP_FERRP_MASK 0x8000UL /**< Bit mask for LEUART_FERRP */
<> 150:02e0a0aed4ec 311 #define _LEUART_RXDATAXP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAXP */
<> 150:02e0a0aed4ec 312 #define LEUART_RXDATAXP_FERRP_DEFAULT (_LEUART_RXDATAXP_FERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */
<> 150:02e0a0aed4ec 313
<> 150:02e0a0aed4ec 314 /* Bit fields for LEUART TXDATAX */
<> 150:02e0a0aed4ec 315 #define _LEUART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for LEUART_TXDATAX */
<> 150:02e0a0aed4ec 316 #define _LEUART_TXDATAX_MASK 0x0000E1FFUL /**< Mask for LEUART_TXDATAX */
<> 150:02e0a0aed4ec 317 #define _LEUART_TXDATAX_TXDATA_SHIFT 0 /**< Shift value for LEUART_TXDATA */
<> 150:02e0a0aed4ec 318 #define _LEUART_TXDATAX_TXDATA_MASK 0x1FFUL /**< Bit mask for LEUART_TXDATA */
<> 150:02e0a0aed4ec 319 #define _LEUART_TXDATAX_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */
<> 150:02e0a0aed4ec 320 #define LEUART_TXDATAX_TXDATA_DEFAULT (_LEUART_TXDATAX_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_TXDATAX */
<> 150:02e0a0aed4ec 321 #define LEUART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data As Break */
<> 150:02e0a0aed4ec 322 #define _LEUART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for LEUART_TXBREAK */
<> 150:02e0a0aed4ec 323 #define _LEUART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for LEUART_TXBREAK */
<> 150:02e0a0aed4ec 324 #define _LEUART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */
<> 150:02e0a0aed4ec 325 #define LEUART_TXDATAX_TXBREAK_DEFAULT (_LEUART_TXDATAX_TXBREAK_DEFAULT << 13) /**< Shifted mode DEFAULT for LEUART_TXDATAX */
<> 150:02e0a0aed4ec 326 #define LEUART_TXDATAX_TXDISAT (0x1UL << 14) /**< Disable TX After Transmission */
<> 150:02e0a0aed4ec 327 #define _LEUART_TXDATAX_TXDISAT_SHIFT 14 /**< Shift value for LEUART_TXDISAT */
<> 150:02e0a0aed4ec 328 #define _LEUART_TXDATAX_TXDISAT_MASK 0x4000UL /**< Bit mask for LEUART_TXDISAT */
<> 150:02e0a0aed4ec 329 #define _LEUART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */
<> 150:02e0a0aed4ec 330 #define LEUART_TXDATAX_TXDISAT_DEFAULT (_LEUART_TXDATAX_TXDISAT_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_TXDATAX */
<> 150:02e0a0aed4ec 331 #define LEUART_TXDATAX_RXENAT (0x1UL << 15) /**< Enable RX After Transmission */
<> 150:02e0a0aed4ec 332 #define _LEUART_TXDATAX_RXENAT_SHIFT 15 /**< Shift value for LEUART_RXENAT */
<> 150:02e0a0aed4ec 333 #define _LEUART_TXDATAX_RXENAT_MASK 0x8000UL /**< Bit mask for LEUART_RXENAT */
<> 150:02e0a0aed4ec 334 #define _LEUART_TXDATAX_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */
<> 150:02e0a0aed4ec 335 #define LEUART_TXDATAX_RXENAT_DEFAULT (_LEUART_TXDATAX_RXENAT_DEFAULT << 15) /**< Shifted mode DEFAULT for LEUART_TXDATAX */
<> 150:02e0a0aed4ec 336
<> 150:02e0a0aed4ec 337 /* Bit fields for LEUART TXDATA */
<> 150:02e0a0aed4ec 338 #define _LEUART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for LEUART_TXDATA */
<> 150:02e0a0aed4ec 339 #define _LEUART_TXDATA_MASK 0x000000FFUL /**< Mask for LEUART_TXDATA */
<> 150:02e0a0aed4ec 340 #define _LEUART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for LEUART_TXDATA */
<> 150:02e0a0aed4ec 341 #define _LEUART_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for LEUART_TXDATA */
<> 150:02e0a0aed4ec 342 #define _LEUART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATA */
<> 150:02e0a0aed4ec 343 #define LEUART_TXDATA_TXDATA_DEFAULT (_LEUART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_TXDATA */
<> 150:02e0a0aed4ec 344
<> 150:02e0a0aed4ec 345 /* Bit fields for LEUART IF */
<> 150:02e0a0aed4ec 346 #define _LEUART_IF_RESETVALUE 0x00000002UL /**< Default value for LEUART_IF */
<> 150:02e0a0aed4ec 347 #define _LEUART_IF_MASK 0x000007FFUL /**< Mask for LEUART_IF */
<> 150:02e0a0aed4ec 348 #define LEUART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */
<> 150:02e0a0aed4ec 349 #define _LEUART_IF_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */
<> 150:02e0a0aed4ec 350 #define _LEUART_IF_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */
<> 150:02e0a0aed4ec 351 #define _LEUART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
<> 150:02e0a0aed4ec 352 #define LEUART_IF_TXC_DEFAULT (_LEUART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IF */
<> 150:02e0a0aed4ec 353 #define LEUART_IF_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Flag */
<> 150:02e0a0aed4ec 354 #define _LEUART_IF_TXBL_SHIFT 1 /**< Shift value for LEUART_TXBL */
<> 150:02e0a0aed4ec 355 #define _LEUART_IF_TXBL_MASK 0x2UL /**< Bit mask for LEUART_TXBL */
<> 150:02e0a0aed4ec 356 #define _LEUART_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for LEUART_IF */
<> 150:02e0a0aed4ec 357 #define LEUART_IF_TXBL_DEFAULT (_LEUART_IF_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_IF */
<> 150:02e0a0aed4ec 358 #define LEUART_IF_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Flag */
<> 150:02e0a0aed4ec 359 #define _LEUART_IF_RXDATAV_SHIFT 2 /**< Shift value for LEUART_RXDATAV */
<> 150:02e0a0aed4ec 360 #define _LEUART_IF_RXDATAV_MASK 0x4UL /**< Bit mask for LEUART_RXDATAV */
<> 150:02e0a0aed4ec 361 #define _LEUART_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
<> 150:02e0a0aed4ec 362 #define LEUART_IF_RXDATAV_DEFAULT (_LEUART_IF_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_IF */
<> 150:02e0a0aed4ec 363 #define LEUART_IF_RXOF (0x1UL << 3) /**< RX Overflow Interrupt Flag */
<> 150:02e0a0aed4ec 364 #define _LEUART_IF_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */
<> 150:02e0a0aed4ec 365 #define _LEUART_IF_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */
<> 150:02e0a0aed4ec 366 #define _LEUART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
<> 150:02e0a0aed4ec 367 #define LEUART_IF_RXOF_DEFAULT (_LEUART_IF_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IF */
<> 150:02e0a0aed4ec 368 #define LEUART_IF_RXUF (0x1UL << 4) /**< RX Underflow Interrupt Flag */
<> 150:02e0a0aed4ec 369 #define _LEUART_IF_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */
<> 150:02e0a0aed4ec 370 #define _LEUART_IF_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */
<> 150:02e0a0aed4ec 371 #define _LEUART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
<> 150:02e0a0aed4ec 372 #define LEUART_IF_RXUF_DEFAULT (_LEUART_IF_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IF */
<> 150:02e0a0aed4ec 373 #define LEUART_IF_TXOF (0x1UL << 5) /**< TX Overflow Interrupt Flag */
<> 150:02e0a0aed4ec 374 #define _LEUART_IF_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */
<> 150:02e0a0aed4ec 375 #define _LEUART_IF_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */
<> 150:02e0a0aed4ec 376 #define _LEUART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
<> 150:02e0a0aed4ec 377 #define LEUART_IF_TXOF_DEFAULT (_LEUART_IF_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IF */
<> 150:02e0a0aed4ec 378 #define LEUART_IF_PERR (0x1UL << 6) /**< Parity Error Interrupt Flag */
<> 150:02e0a0aed4ec 379 #define _LEUART_IF_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */
<> 150:02e0a0aed4ec 380 #define _LEUART_IF_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */
<> 150:02e0a0aed4ec 381 #define _LEUART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
<> 150:02e0a0aed4ec 382 #define LEUART_IF_PERR_DEFAULT (_LEUART_IF_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IF */
<> 150:02e0a0aed4ec 383 #define LEUART_IF_FERR (0x1UL << 7) /**< Framing Error Interrupt Flag */
<> 150:02e0a0aed4ec 384 #define _LEUART_IF_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */
<> 150:02e0a0aed4ec 385 #define _LEUART_IF_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */
<> 150:02e0a0aed4ec 386 #define _LEUART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
<> 150:02e0a0aed4ec 387 #define LEUART_IF_FERR_DEFAULT (_LEUART_IF_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IF */
<> 150:02e0a0aed4ec 388 #define LEUART_IF_MPAF (0x1UL << 8) /**< Multi-Processor Address Frame Interrupt Flag */
<> 150:02e0a0aed4ec 389 #define _LEUART_IF_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */
<> 150:02e0a0aed4ec 390 #define _LEUART_IF_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */
<> 150:02e0a0aed4ec 391 #define _LEUART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
<> 150:02e0a0aed4ec 392 #define LEUART_IF_MPAF_DEFAULT (_LEUART_IF_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IF */
<> 150:02e0a0aed4ec 393 #define LEUART_IF_STARTF (0x1UL << 9) /**< Start Frame Interrupt Flag */
<> 150:02e0a0aed4ec 394 #define _LEUART_IF_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */
<> 150:02e0a0aed4ec 395 #define _LEUART_IF_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */
<> 150:02e0a0aed4ec 396 #define _LEUART_IF_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
<> 150:02e0a0aed4ec 397 #define LEUART_IF_STARTF_DEFAULT (_LEUART_IF_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IF */
<> 150:02e0a0aed4ec 398 #define LEUART_IF_SIGF (0x1UL << 10) /**< Signal Frame Interrupt Flag */
<> 150:02e0a0aed4ec 399 #define _LEUART_IF_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */
<> 150:02e0a0aed4ec 400 #define _LEUART_IF_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */
<> 150:02e0a0aed4ec 401 #define _LEUART_IF_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
<> 150:02e0a0aed4ec 402 #define LEUART_IF_SIGF_DEFAULT (_LEUART_IF_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IF */
<> 150:02e0a0aed4ec 403
<> 150:02e0a0aed4ec 404 /* Bit fields for LEUART IFS */
<> 150:02e0a0aed4ec 405 #define _LEUART_IFS_RESETVALUE 0x00000000UL /**< Default value for LEUART_IFS */
<> 150:02e0a0aed4ec 406 #define _LEUART_IFS_MASK 0x000007F9UL /**< Mask for LEUART_IFS */
<> 150:02e0a0aed4ec 407 #define LEUART_IFS_TXC (0x1UL << 0) /**< Set TX Complete Interrupt Flag */
<> 150:02e0a0aed4ec 408 #define _LEUART_IFS_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */
<> 150:02e0a0aed4ec 409 #define _LEUART_IFS_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */
<> 150:02e0a0aed4ec 410 #define _LEUART_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
<> 150:02e0a0aed4ec 411 #define LEUART_IFS_TXC_DEFAULT (_LEUART_IFS_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IFS */
<> 150:02e0a0aed4ec 412 #define LEUART_IFS_RXOF (0x1UL << 3) /**< Set RX Overflow Interrupt Flag */
<> 150:02e0a0aed4ec 413 #define _LEUART_IFS_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */
<> 150:02e0a0aed4ec 414 #define _LEUART_IFS_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */
<> 150:02e0a0aed4ec 415 #define _LEUART_IFS_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
<> 150:02e0a0aed4ec 416 #define LEUART_IFS_RXOF_DEFAULT (_LEUART_IFS_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IFS */
<> 150:02e0a0aed4ec 417 #define LEUART_IFS_RXUF (0x1UL << 4) /**< Set RX Underflow Interrupt Flag */
<> 150:02e0a0aed4ec 418 #define _LEUART_IFS_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */
<> 150:02e0a0aed4ec 419 #define _LEUART_IFS_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */
<> 150:02e0a0aed4ec 420 #define _LEUART_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
<> 150:02e0a0aed4ec 421 #define LEUART_IFS_RXUF_DEFAULT (_LEUART_IFS_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IFS */
<> 150:02e0a0aed4ec 422 #define LEUART_IFS_TXOF (0x1UL << 5) /**< Set TX Overflow Interrupt Flag */
<> 150:02e0a0aed4ec 423 #define _LEUART_IFS_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */
<> 150:02e0a0aed4ec 424 #define _LEUART_IFS_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */
<> 150:02e0a0aed4ec 425 #define _LEUART_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
<> 150:02e0a0aed4ec 426 #define LEUART_IFS_TXOF_DEFAULT (_LEUART_IFS_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IFS */
<> 150:02e0a0aed4ec 427 #define LEUART_IFS_PERR (0x1UL << 6) /**< Set Parity Error Interrupt Flag */
<> 150:02e0a0aed4ec 428 #define _LEUART_IFS_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */
<> 150:02e0a0aed4ec 429 #define _LEUART_IFS_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */
<> 150:02e0a0aed4ec 430 #define _LEUART_IFS_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
<> 150:02e0a0aed4ec 431 #define LEUART_IFS_PERR_DEFAULT (_LEUART_IFS_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IFS */
<> 150:02e0a0aed4ec 432 #define LEUART_IFS_FERR (0x1UL << 7) /**< Set Framing Error Interrupt Flag */
<> 150:02e0a0aed4ec 433 #define _LEUART_IFS_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */
<> 150:02e0a0aed4ec 434 #define _LEUART_IFS_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */
<> 150:02e0a0aed4ec 435 #define _LEUART_IFS_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
<> 150:02e0a0aed4ec 436 #define LEUART_IFS_FERR_DEFAULT (_LEUART_IFS_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IFS */
<> 150:02e0a0aed4ec 437 #define LEUART_IFS_MPAF (0x1UL << 8) /**< Set Multi-Processor Address Frame Interrupt Flag */
<> 150:02e0a0aed4ec 438 #define _LEUART_IFS_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */
<> 150:02e0a0aed4ec 439 #define _LEUART_IFS_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */
<> 150:02e0a0aed4ec 440 #define _LEUART_IFS_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
<> 150:02e0a0aed4ec 441 #define LEUART_IFS_MPAF_DEFAULT (_LEUART_IFS_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IFS */
<> 150:02e0a0aed4ec 442 #define LEUART_IFS_STARTF (0x1UL << 9) /**< Set Start Frame Interrupt Flag */
<> 150:02e0a0aed4ec 443 #define _LEUART_IFS_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */
<> 150:02e0a0aed4ec 444 #define _LEUART_IFS_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */
<> 150:02e0a0aed4ec 445 #define _LEUART_IFS_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
<> 150:02e0a0aed4ec 446 #define LEUART_IFS_STARTF_DEFAULT (_LEUART_IFS_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IFS */
<> 150:02e0a0aed4ec 447 #define LEUART_IFS_SIGF (0x1UL << 10) /**< Set Signal Frame Interrupt Flag */
<> 150:02e0a0aed4ec 448 #define _LEUART_IFS_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */
<> 150:02e0a0aed4ec 449 #define _LEUART_IFS_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */
<> 150:02e0a0aed4ec 450 #define _LEUART_IFS_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
<> 150:02e0a0aed4ec 451 #define LEUART_IFS_SIGF_DEFAULT (_LEUART_IFS_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IFS */
<> 150:02e0a0aed4ec 452
<> 150:02e0a0aed4ec 453 /* Bit fields for LEUART IFC */
<> 150:02e0a0aed4ec 454 #define _LEUART_IFC_RESETVALUE 0x00000000UL /**< Default value for LEUART_IFC */
<> 150:02e0a0aed4ec 455 #define _LEUART_IFC_MASK 0x000007F9UL /**< Mask for LEUART_IFC */
<> 150:02e0a0aed4ec 456 #define LEUART_IFC_TXC (0x1UL << 0) /**< Clear TX Complete Interrupt Flag */
<> 150:02e0a0aed4ec 457 #define _LEUART_IFC_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */
<> 150:02e0a0aed4ec 458 #define _LEUART_IFC_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */
<> 150:02e0a0aed4ec 459 #define _LEUART_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
<> 150:02e0a0aed4ec 460 #define LEUART_IFC_TXC_DEFAULT (_LEUART_IFC_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IFC */
<> 150:02e0a0aed4ec 461 #define LEUART_IFC_RXOF (0x1UL << 3) /**< Clear RX Overflow Interrupt Flag */
<> 150:02e0a0aed4ec 462 #define _LEUART_IFC_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */
<> 150:02e0a0aed4ec 463 #define _LEUART_IFC_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */
<> 150:02e0a0aed4ec 464 #define _LEUART_IFC_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
<> 150:02e0a0aed4ec 465 #define LEUART_IFC_RXOF_DEFAULT (_LEUART_IFC_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IFC */
<> 150:02e0a0aed4ec 466 #define LEUART_IFC_RXUF (0x1UL << 4) /**< Clear RX Underflow Interrupt Flag */
<> 150:02e0a0aed4ec 467 #define _LEUART_IFC_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */
<> 150:02e0a0aed4ec 468 #define _LEUART_IFC_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */
<> 150:02e0a0aed4ec 469 #define _LEUART_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
<> 150:02e0a0aed4ec 470 #define LEUART_IFC_RXUF_DEFAULT (_LEUART_IFC_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IFC */
<> 150:02e0a0aed4ec 471 #define LEUART_IFC_TXOF (0x1UL << 5) /**< Clear TX Overflow Interrupt Flag */
<> 150:02e0a0aed4ec 472 #define _LEUART_IFC_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */
<> 150:02e0a0aed4ec 473 #define _LEUART_IFC_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */
<> 150:02e0a0aed4ec 474 #define _LEUART_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
<> 150:02e0a0aed4ec 475 #define LEUART_IFC_TXOF_DEFAULT (_LEUART_IFC_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IFC */
<> 150:02e0a0aed4ec 476 #define LEUART_IFC_PERR (0x1UL << 6) /**< Clear Parity Error Interrupt Flag */
<> 150:02e0a0aed4ec 477 #define _LEUART_IFC_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */
<> 150:02e0a0aed4ec 478 #define _LEUART_IFC_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */
<> 150:02e0a0aed4ec 479 #define _LEUART_IFC_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
<> 150:02e0a0aed4ec 480 #define LEUART_IFC_PERR_DEFAULT (_LEUART_IFC_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IFC */
<> 150:02e0a0aed4ec 481 #define LEUART_IFC_FERR (0x1UL << 7) /**< Clear Framing Error Interrupt Flag */
<> 150:02e0a0aed4ec 482 #define _LEUART_IFC_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */
<> 150:02e0a0aed4ec 483 #define _LEUART_IFC_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */
<> 150:02e0a0aed4ec 484 #define _LEUART_IFC_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
<> 150:02e0a0aed4ec 485 #define LEUART_IFC_FERR_DEFAULT (_LEUART_IFC_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IFC */
<> 150:02e0a0aed4ec 486 #define LEUART_IFC_MPAF (0x1UL << 8) /**< Clear Multi-Processor Address Frame Interrupt Flag */
<> 150:02e0a0aed4ec 487 #define _LEUART_IFC_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */
<> 150:02e0a0aed4ec 488 #define _LEUART_IFC_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */
<> 150:02e0a0aed4ec 489 #define _LEUART_IFC_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
<> 150:02e0a0aed4ec 490 #define LEUART_IFC_MPAF_DEFAULT (_LEUART_IFC_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IFC */
<> 150:02e0a0aed4ec 491 #define LEUART_IFC_STARTF (0x1UL << 9) /**< Clear Start-Frame Interrupt Flag */
<> 150:02e0a0aed4ec 492 #define _LEUART_IFC_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */
<> 150:02e0a0aed4ec 493 #define _LEUART_IFC_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */
<> 150:02e0a0aed4ec 494 #define _LEUART_IFC_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
<> 150:02e0a0aed4ec 495 #define LEUART_IFC_STARTF_DEFAULT (_LEUART_IFC_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IFC */
<> 150:02e0a0aed4ec 496 #define LEUART_IFC_SIGF (0x1UL << 10) /**< Clear Signal-Frame Interrupt Flag */
<> 150:02e0a0aed4ec 497 #define _LEUART_IFC_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */
<> 150:02e0a0aed4ec 498 #define _LEUART_IFC_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */
<> 150:02e0a0aed4ec 499 #define _LEUART_IFC_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
<> 150:02e0a0aed4ec 500 #define LEUART_IFC_SIGF_DEFAULT (_LEUART_IFC_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IFC */
<> 150:02e0a0aed4ec 501
<> 150:02e0a0aed4ec 502 /* Bit fields for LEUART IEN */
<> 150:02e0a0aed4ec 503 #define _LEUART_IEN_RESETVALUE 0x00000000UL /**< Default value for LEUART_IEN */
<> 150:02e0a0aed4ec 504 #define _LEUART_IEN_MASK 0x000007FFUL /**< Mask for LEUART_IEN */
<> 150:02e0a0aed4ec 505 #define LEUART_IEN_TXC (0x1UL << 0) /**< TX Complete Interrupt Enable */
<> 150:02e0a0aed4ec 506 #define _LEUART_IEN_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */
<> 150:02e0a0aed4ec 507 #define _LEUART_IEN_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */
<> 150:02e0a0aed4ec 508 #define _LEUART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
<> 150:02e0a0aed4ec 509 #define LEUART_IEN_TXC_DEFAULT (_LEUART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IEN */
<> 150:02e0a0aed4ec 510 #define LEUART_IEN_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Enable */
<> 150:02e0a0aed4ec 511 #define _LEUART_IEN_TXBL_SHIFT 1 /**< Shift value for LEUART_TXBL */
<> 150:02e0a0aed4ec 512 #define _LEUART_IEN_TXBL_MASK 0x2UL /**< Bit mask for LEUART_TXBL */
<> 150:02e0a0aed4ec 513 #define _LEUART_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
<> 150:02e0a0aed4ec 514 #define LEUART_IEN_TXBL_DEFAULT (_LEUART_IEN_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_IEN */
<> 150:02e0a0aed4ec 515 #define LEUART_IEN_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Enable */
<> 150:02e0a0aed4ec 516 #define _LEUART_IEN_RXDATAV_SHIFT 2 /**< Shift value for LEUART_RXDATAV */
<> 150:02e0a0aed4ec 517 #define _LEUART_IEN_RXDATAV_MASK 0x4UL /**< Bit mask for LEUART_RXDATAV */
<> 150:02e0a0aed4ec 518 #define _LEUART_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
<> 150:02e0a0aed4ec 519 #define LEUART_IEN_RXDATAV_DEFAULT (_LEUART_IEN_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_IEN */
<> 150:02e0a0aed4ec 520 #define LEUART_IEN_RXOF (0x1UL << 3) /**< RX Overflow Interrupt Enable */
<> 150:02e0a0aed4ec 521 #define _LEUART_IEN_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */
<> 150:02e0a0aed4ec 522 #define _LEUART_IEN_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */
<> 150:02e0a0aed4ec 523 #define _LEUART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
<> 150:02e0a0aed4ec 524 #define LEUART_IEN_RXOF_DEFAULT (_LEUART_IEN_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IEN */
<> 150:02e0a0aed4ec 525 #define LEUART_IEN_RXUF (0x1UL << 4) /**< RX Underflow Interrupt Enable */
<> 150:02e0a0aed4ec 526 #define _LEUART_IEN_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */
<> 150:02e0a0aed4ec 527 #define _LEUART_IEN_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */
<> 150:02e0a0aed4ec 528 #define _LEUART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
<> 150:02e0a0aed4ec 529 #define LEUART_IEN_RXUF_DEFAULT (_LEUART_IEN_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IEN */
<> 150:02e0a0aed4ec 530 #define LEUART_IEN_TXOF (0x1UL << 5) /**< TX Overflow Interrupt Enable */
<> 150:02e0a0aed4ec 531 #define _LEUART_IEN_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */
<> 150:02e0a0aed4ec 532 #define _LEUART_IEN_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */
<> 150:02e0a0aed4ec 533 #define _LEUART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
<> 150:02e0a0aed4ec 534 #define LEUART_IEN_TXOF_DEFAULT (_LEUART_IEN_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IEN */
<> 150:02e0a0aed4ec 535 #define LEUART_IEN_PERR (0x1UL << 6) /**< Parity Error Interrupt Enable */
<> 150:02e0a0aed4ec 536 #define _LEUART_IEN_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */
<> 150:02e0a0aed4ec 537 #define _LEUART_IEN_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */
<> 150:02e0a0aed4ec 538 #define _LEUART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
<> 150:02e0a0aed4ec 539 #define LEUART_IEN_PERR_DEFAULT (_LEUART_IEN_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IEN */
<> 150:02e0a0aed4ec 540 #define LEUART_IEN_FERR (0x1UL << 7) /**< Framing Error Interrupt Enable */
<> 150:02e0a0aed4ec 541 #define _LEUART_IEN_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */
<> 150:02e0a0aed4ec 542 #define _LEUART_IEN_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */
<> 150:02e0a0aed4ec 543 #define _LEUART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
<> 150:02e0a0aed4ec 544 #define LEUART_IEN_FERR_DEFAULT (_LEUART_IEN_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IEN */
<> 150:02e0a0aed4ec 545 #define LEUART_IEN_MPAF (0x1UL << 8) /**< Multi-Processor Address Frame Interrupt Enable */
<> 150:02e0a0aed4ec 546 #define _LEUART_IEN_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */
<> 150:02e0a0aed4ec 547 #define _LEUART_IEN_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */
<> 150:02e0a0aed4ec 548 #define _LEUART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
<> 150:02e0a0aed4ec 549 #define LEUART_IEN_MPAF_DEFAULT (_LEUART_IEN_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IEN */
<> 150:02e0a0aed4ec 550 #define LEUART_IEN_STARTF (0x1UL << 9) /**< Start Frame Interrupt Enable */
<> 150:02e0a0aed4ec 551 #define _LEUART_IEN_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */
<> 150:02e0a0aed4ec 552 #define _LEUART_IEN_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */
<> 150:02e0a0aed4ec 553 #define _LEUART_IEN_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
<> 150:02e0a0aed4ec 554 #define LEUART_IEN_STARTF_DEFAULT (_LEUART_IEN_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IEN */
<> 150:02e0a0aed4ec 555 #define LEUART_IEN_SIGF (0x1UL << 10) /**< Signal Frame Interrupt Enable */
<> 150:02e0a0aed4ec 556 #define _LEUART_IEN_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */
<> 150:02e0a0aed4ec 557 #define _LEUART_IEN_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */
<> 150:02e0a0aed4ec 558 #define _LEUART_IEN_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
<> 150:02e0a0aed4ec 559 #define LEUART_IEN_SIGF_DEFAULT (_LEUART_IEN_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IEN */
<> 150:02e0a0aed4ec 560
<> 150:02e0a0aed4ec 561 /* Bit fields for LEUART PULSECTRL */
<> 150:02e0a0aed4ec 562 #define _LEUART_PULSECTRL_RESETVALUE 0x00000000UL /**< Default value for LEUART_PULSECTRL */
<> 150:02e0a0aed4ec 563 #define _LEUART_PULSECTRL_MASK 0x0000003FUL /**< Mask for LEUART_PULSECTRL */
<> 150:02e0a0aed4ec 564 #define _LEUART_PULSECTRL_PULSEW_SHIFT 0 /**< Shift value for LEUART_PULSEW */
<> 150:02e0a0aed4ec 565 #define _LEUART_PULSECTRL_PULSEW_MASK 0xFUL /**< Bit mask for LEUART_PULSEW */
<> 150:02e0a0aed4ec 566 #define _LEUART_PULSECTRL_PULSEW_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_PULSECTRL */
<> 150:02e0a0aed4ec 567 #define LEUART_PULSECTRL_PULSEW_DEFAULT (_LEUART_PULSECTRL_PULSEW_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */
<> 150:02e0a0aed4ec 568 #define LEUART_PULSECTRL_PULSEEN (0x1UL << 4) /**< Pulse Generator/Extender Enable */
<> 150:02e0a0aed4ec 569 #define _LEUART_PULSECTRL_PULSEEN_SHIFT 4 /**< Shift value for LEUART_PULSEEN */
<> 150:02e0a0aed4ec 570 #define _LEUART_PULSECTRL_PULSEEN_MASK 0x10UL /**< Bit mask for LEUART_PULSEEN */
<> 150:02e0a0aed4ec 571 #define _LEUART_PULSECTRL_PULSEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_PULSECTRL */
<> 150:02e0a0aed4ec 572 #define LEUART_PULSECTRL_PULSEEN_DEFAULT (_LEUART_PULSECTRL_PULSEEN_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */
<> 150:02e0a0aed4ec 573 #define LEUART_PULSECTRL_PULSEFILT (0x1UL << 5) /**< Pulse Filter */
<> 150:02e0a0aed4ec 574 #define _LEUART_PULSECTRL_PULSEFILT_SHIFT 5 /**< Shift value for LEUART_PULSEFILT */
<> 150:02e0a0aed4ec 575 #define _LEUART_PULSECTRL_PULSEFILT_MASK 0x20UL /**< Bit mask for LEUART_PULSEFILT */
<> 150:02e0a0aed4ec 576 #define _LEUART_PULSECTRL_PULSEFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_PULSECTRL */
<> 150:02e0a0aed4ec 577 #define LEUART_PULSECTRL_PULSEFILT_DEFAULT (_LEUART_PULSECTRL_PULSEFILT_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */
<> 150:02e0a0aed4ec 578
<> 150:02e0a0aed4ec 579 /* Bit fields for LEUART FREEZE */
<> 150:02e0a0aed4ec 580 #define _LEUART_FREEZE_RESETVALUE 0x00000000UL /**< Default value for LEUART_FREEZE */
<> 150:02e0a0aed4ec 581 #define _LEUART_FREEZE_MASK 0x00000001UL /**< Mask for LEUART_FREEZE */
<> 150:02e0a0aed4ec 582 #define LEUART_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */
<> 150:02e0a0aed4ec 583 #define _LEUART_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for LEUART_REGFREEZE */
<> 150:02e0a0aed4ec 584 #define _LEUART_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for LEUART_REGFREEZE */
<> 150:02e0a0aed4ec 585 #define _LEUART_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_FREEZE */
<> 150:02e0a0aed4ec 586 #define _LEUART_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for LEUART_FREEZE */
<> 150:02e0a0aed4ec 587 #define _LEUART_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for LEUART_FREEZE */
<> 150:02e0a0aed4ec 588 #define LEUART_FREEZE_REGFREEZE_DEFAULT (_LEUART_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_FREEZE */
<> 150:02e0a0aed4ec 589 #define LEUART_FREEZE_REGFREEZE_UPDATE (_LEUART_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for LEUART_FREEZE */
<> 150:02e0a0aed4ec 590 #define LEUART_FREEZE_REGFREEZE_FREEZE (_LEUART_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for LEUART_FREEZE */
<> 150:02e0a0aed4ec 591
<> 150:02e0a0aed4ec 592 /* Bit fields for LEUART SYNCBUSY */
<> 150:02e0a0aed4ec 593 #define _LEUART_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LEUART_SYNCBUSY */
<> 150:02e0a0aed4ec 594 #define _LEUART_SYNCBUSY_MASK 0x000000FFUL /**< Mask for LEUART_SYNCBUSY */
<> 150:02e0a0aed4ec 595 #define LEUART_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */
<> 150:02e0a0aed4ec 596 #define _LEUART_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for LEUART_CTRL */
<> 150:02e0a0aed4ec 597 #define _LEUART_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for LEUART_CTRL */
<> 150:02e0a0aed4ec 598 #define _LEUART_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
<> 150:02e0a0aed4ec 599 #define LEUART_SYNCBUSY_CTRL_DEFAULT (_LEUART_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
<> 150:02e0a0aed4ec 600 #define LEUART_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */
<> 150:02e0a0aed4ec 601 #define _LEUART_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for LEUART_CMD */
<> 150:02e0a0aed4ec 602 #define _LEUART_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for LEUART_CMD */
<> 150:02e0a0aed4ec 603 #define _LEUART_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
<> 150:02e0a0aed4ec 604 #define LEUART_SYNCBUSY_CMD_DEFAULT (_LEUART_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
<> 150:02e0a0aed4ec 605 #define LEUART_SYNCBUSY_CLKDIV (0x1UL << 2) /**< CLKDIV Register Busy */
<> 150:02e0a0aed4ec 606 #define _LEUART_SYNCBUSY_CLKDIV_SHIFT 2 /**< Shift value for LEUART_CLKDIV */
<> 150:02e0a0aed4ec 607 #define _LEUART_SYNCBUSY_CLKDIV_MASK 0x4UL /**< Bit mask for LEUART_CLKDIV */
<> 150:02e0a0aed4ec 608 #define _LEUART_SYNCBUSY_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
<> 150:02e0a0aed4ec 609 #define LEUART_SYNCBUSY_CLKDIV_DEFAULT (_LEUART_SYNCBUSY_CLKDIV_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
<> 150:02e0a0aed4ec 610 #define LEUART_SYNCBUSY_STARTFRAME (0x1UL << 3) /**< STARTFRAME Register Busy */
<> 150:02e0a0aed4ec 611 #define _LEUART_SYNCBUSY_STARTFRAME_SHIFT 3 /**< Shift value for LEUART_STARTFRAME */
<> 150:02e0a0aed4ec 612 #define _LEUART_SYNCBUSY_STARTFRAME_MASK 0x8UL /**< Bit mask for LEUART_STARTFRAME */
<> 150:02e0a0aed4ec 613 #define _LEUART_SYNCBUSY_STARTFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
<> 150:02e0a0aed4ec 614 #define LEUART_SYNCBUSY_STARTFRAME_DEFAULT (_LEUART_SYNCBUSY_STARTFRAME_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
<> 150:02e0a0aed4ec 615 #define LEUART_SYNCBUSY_SIGFRAME (0x1UL << 4) /**< SIGFRAME Register Busy */
<> 150:02e0a0aed4ec 616 #define _LEUART_SYNCBUSY_SIGFRAME_SHIFT 4 /**< Shift value for LEUART_SIGFRAME */
<> 150:02e0a0aed4ec 617 #define _LEUART_SYNCBUSY_SIGFRAME_MASK 0x10UL /**< Bit mask for LEUART_SIGFRAME */
<> 150:02e0a0aed4ec 618 #define _LEUART_SYNCBUSY_SIGFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
<> 150:02e0a0aed4ec 619 #define LEUART_SYNCBUSY_SIGFRAME_DEFAULT (_LEUART_SYNCBUSY_SIGFRAME_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
<> 150:02e0a0aed4ec 620 #define LEUART_SYNCBUSY_TXDATAX (0x1UL << 5) /**< TXDATAX Register Busy */
<> 150:02e0a0aed4ec 621 #define _LEUART_SYNCBUSY_TXDATAX_SHIFT 5 /**< Shift value for LEUART_TXDATAX */
<> 150:02e0a0aed4ec 622 #define _LEUART_SYNCBUSY_TXDATAX_MASK 0x20UL /**< Bit mask for LEUART_TXDATAX */
<> 150:02e0a0aed4ec 623 #define _LEUART_SYNCBUSY_TXDATAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
<> 150:02e0a0aed4ec 624 #define LEUART_SYNCBUSY_TXDATAX_DEFAULT (_LEUART_SYNCBUSY_TXDATAX_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
<> 150:02e0a0aed4ec 625 #define LEUART_SYNCBUSY_TXDATA (0x1UL << 6) /**< TXDATA Register Busy */
<> 150:02e0a0aed4ec 626 #define _LEUART_SYNCBUSY_TXDATA_SHIFT 6 /**< Shift value for LEUART_TXDATA */
<> 150:02e0a0aed4ec 627 #define _LEUART_SYNCBUSY_TXDATA_MASK 0x40UL /**< Bit mask for LEUART_TXDATA */
<> 150:02e0a0aed4ec 628 #define _LEUART_SYNCBUSY_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
<> 150:02e0a0aed4ec 629 #define LEUART_SYNCBUSY_TXDATA_DEFAULT (_LEUART_SYNCBUSY_TXDATA_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
<> 150:02e0a0aed4ec 630 #define LEUART_SYNCBUSY_PULSECTRL (0x1UL << 7) /**< PULSECTRL Register Busy */
<> 150:02e0a0aed4ec 631 #define _LEUART_SYNCBUSY_PULSECTRL_SHIFT 7 /**< Shift value for LEUART_PULSECTRL */
<> 150:02e0a0aed4ec 632 #define _LEUART_SYNCBUSY_PULSECTRL_MASK 0x80UL /**< Bit mask for LEUART_PULSECTRL */
<> 150:02e0a0aed4ec 633 #define _LEUART_SYNCBUSY_PULSECTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
<> 150:02e0a0aed4ec 634 #define LEUART_SYNCBUSY_PULSECTRL_DEFAULT (_LEUART_SYNCBUSY_PULSECTRL_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
<> 150:02e0a0aed4ec 635
<> 150:02e0a0aed4ec 636 /* Bit fields for LEUART ROUTE */
<> 150:02e0a0aed4ec 637 #define _LEUART_ROUTE_RESETVALUE 0x00000000UL /**< Default value for LEUART_ROUTE */
<> 150:02e0a0aed4ec 638 #define _LEUART_ROUTE_MASK 0x00000703UL /**< Mask for LEUART_ROUTE */
<> 150:02e0a0aed4ec 639 #define LEUART_ROUTE_RXPEN (0x1UL << 0) /**< RX Pin Enable */
<> 150:02e0a0aed4ec 640 #define _LEUART_ROUTE_RXPEN_SHIFT 0 /**< Shift value for LEUART_RXPEN */
<> 150:02e0a0aed4ec 641 #define _LEUART_ROUTE_RXPEN_MASK 0x1UL /**< Bit mask for LEUART_RXPEN */
<> 150:02e0a0aed4ec 642 #define _LEUART_ROUTE_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTE */
<> 150:02e0a0aed4ec 643 #define LEUART_ROUTE_RXPEN_DEFAULT (_LEUART_ROUTE_RXPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_ROUTE */
<> 150:02e0a0aed4ec 644 #define LEUART_ROUTE_TXPEN (0x1UL << 1) /**< TX Pin Enable */
<> 150:02e0a0aed4ec 645 #define _LEUART_ROUTE_TXPEN_SHIFT 1 /**< Shift value for LEUART_TXPEN */
<> 150:02e0a0aed4ec 646 #define _LEUART_ROUTE_TXPEN_MASK 0x2UL /**< Bit mask for LEUART_TXPEN */
<> 150:02e0a0aed4ec 647 #define _LEUART_ROUTE_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTE */
<> 150:02e0a0aed4ec 648 #define LEUART_ROUTE_TXPEN_DEFAULT (_LEUART_ROUTE_TXPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_ROUTE */
<> 150:02e0a0aed4ec 649 #define _LEUART_ROUTE_LOCATION_SHIFT 8 /**< Shift value for LEUART_LOCATION */
<> 150:02e0a0aed4ec 650 #define _LEUART_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for LEUART_LOCATION */
<> 150:02e0a0aed4ec 651 #define _LEUART_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for LEUART_ROUTE */
<> 150:02e0a0aed4ec 652 #define _LEUART_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTE */
<> 150:02e0a0aed4ec 653 #define _LEUART_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for LEUART_ROUTE */
<> 150:02e0a0aed4ec 654 #define _LEUART_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for LEUART_ROUTE */
<> 150:02e0a0aed4ec 655 #define _LEUART_ROUTE_LOCATION_LOC3 0x00000003UL /**< Mode LOC3 for LEUART_ROUTE */
<> 150:02e0a0aed4ec 656 #define _LEUART_ROUTE_LOCATION_LOC4 0x00000004UL /**< Mode LOC4 for LEUART_ROUTE */
<> 150:02e0a0aed4ec 657 #define LEUART_ROUTE_LOCATION_LOC0 (_LEUART_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for LEUART_ROUTE */
<> 150:02e0a0aed4ec 658 #define LEUART_ROUTE_LOCATION_DEFAULT (_LEUART_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_ROUTE */
<> 150:02e0a0aed4ec 659 #define LEUART_ROUTE_LOCATION_LOC1 (_LEUART_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for LEUART_ROUTE */
<> 150:02e0a0aed4ec 660 #define LEUART_ROUTE_LOCATION_LOC2 (_LEUART_ROUTE_LOCATION_LOC2 << 8) /**< Shifted mode LOC2 for LEUART_ROUTE */
<> 150:02e0a0aed4ec 661 #define LEUART_ROUTE_LOCATION_LOC3 (_LEUART_ROUTE_LOCATION_LOC3 << 8) /**< Shifted mode LOC3 for LEUART_ROUTE */
<> 150:02e0a0aed4ec 662 #define LEUART_ROUTE_LOCATION_LOC4 (_LEUART_ROUTE_LOCATION_LOC4 << 8) /**< Shifted mode LOC4 for LEUART_ROUTE */
<> 150:02e0a0aed4ec 663
<> 150:02e0a0aed4ec 664 /* Bit fields for LEUART INPUT */
<> 150:02e0a0aed4ec 665 #define _LEUART_INPUT_RESETVALUE 0x00000000UL /**< Default value for LEUART_INPUT */
<> 150:02e0a0aed4ec 666 #define _LEUART_INPUT_MASK 0x0000001FUL /**< Mask for LEUART_INPUT */
<> 150:02e0a0aed4ec 667 #define _LEUART_INPUT_RXPRSSEL_SHIFT 0 /**< Shift value for LEUART_RXPRSSEL */
<> 150:02e0a0aed4ec 668 #define _LEUART_INPUT_RXPRSSEL_MASK 0xFUL /**< Bit mask for LEUART_RXPRSSEL */
<> 150:02e0a0aed4ec 669 #define _LEUART_INPUT_RXPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_INPUT */
<> 150:02e0a0aed4ec 670 #define _LEUART_INPUT_RXPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LEUART_INPUT */
<> 150:02e0a0aed4ec 671 #define _LEUART_INPUT_RXPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LEUART_INPUT */
<> 150:02e0a0aed4ec 672 #define _LEUART_INPUT_RXPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LEUART_INPUT */
<> 150:02e0a0aed4ec 673 #define _LEUART_INPUT_RXPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LEUART_INPUT */
<> 150:02e0a0aed4ec 674 #define _LEUART_INPUT_RXPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LEUART_INPUT */
<> 150:02e0a0aed4ec 675 #define _LEUART_INPUT_RXPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LEUART_INPUT */
<> 150:02e0a0aed4ec 676 #define _LEUART_INPUT_RXPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LEUART_INPUT */
<> 150:02e0a0aed4ec 677 #define _LEUART_INPUT_RXPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LEUART_INPUT */
<> 150:02e0a0aed4ec 678 #define _LEUART_INPUT_RXPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LEUART_INPUT */
<> 150:02e0a0aed4ec 679 #define _LEUART_INPUT_RXPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LEUART_INPUT */
<> 150:02e0a0aed4ec 680 #define _LEUART_INPUT_RXPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LEUART_INPUT */
<> 150:02e0a0aed4ec 681 #define _LEUART_INPUT_RXPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LEUART_INPUT */
<> 150:02e0a0aed4ec 682 #define LEUART_INPUT_RXPRSSEL_DEFAULT (_LEUART_INPUT_RXPRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_INPUT */
<> 150:02e0a0aed4ec 683 #define LEUART_INPUT_RXPRSSEL_PRSCH0 (_LEUART_INPUT_RXPRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for LEUART_INPUT */
<> 150:02e0a0aed4ec 684 #define LEUART_INPUT_RXPRSSEL_PRSCH1 (_LEUART_INPUT_RXPRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for LEUART_INPUT */
<> 150:02e0a0aed4ec 685 #define LEUART_INPUT_RXPRSSEL_PRSCH2 (_LEUART_INPUT_RXPRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for LEUART_INPUT */
<> 150:02e0a0aed4ec 686 #define LEUART_INPUT_RXPRSSEL_PRSCH3 (_LEUART_INPUT_RXPRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for LEUART_INPUT */
<> 150:02e0a0aed4ec 687 #define LEUART_INPUT_RXPRSSEL_PRSCH4 (_LEUART_INPUT_RXPRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for LEUART_INPUT */
<> 150:02e0a0aed4ec 688 #define LEUART_INPUT_RXPRSSEL_PRSCH5 (_LEUART_INPUT_RXPRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for LEUART_INPUT */
<> 150:02e0a0aed4ec 689 #define LEUART_INPUT_RXPRSSEL_PRSCH6 (_LEUART_INPUT_RXPRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for LEUART_INPUT */
<> 150:02e0a0aed4ec 690 #define LEUART_INPUT_RXPRSSEL_PRSCH7 (_LEUART_INPUT_RXPRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for LEUART_INPUT */
<> 150:02e0a0aed4ec 691 #define LEUART_INPUT_RXPRSSEL_PRSCH8 (_LEUART_INPUT_RXPRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for LEUART_INPUT */
<> 150:02e0a0aed4ec 692 #define LEUART_INPUT_RXPRSSEL_PRSCH9 (_LEUART_INPUT_RXPRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for LEUART_INPUT */
<> 150:02e0a0aed4ec 693 #define LEUART_INPUT_RXPRSSEL_PRSCH10 (_LEUART_INPUT_RXPRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for LEUART_INPUT */
<> 150:02e0a0aed4ec 694 #define LEUART_INPUT_RXPRSSEL_PRSCH11 (_LEUART_INPUT_RXPRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for LEUART_INPUT */
<> 150:02e0a0aed4ec 695 #define LEUART_INPUT_RXPRS (0x1UL << 4) /**< PRS RX Enable */
<> 150:02e0a0aed4ec 696 #define _LEUART_INPUT_RXPRS_SHIFT 4 /**< Shift value for LEUART_RXPRS */
<> 150:02e0a0aed4ec 697 #define _LEUART_INPUT_RXPRS_MASK 0x10UL /**< Bit mask for LEUART_RXPRS */
<> 150:02e0a0aed4ec 698 #define _LEUART_INPUT_RXPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_INPUT */
<> 150:02e0a0aed4ec 699 #define LEUART_INPUT_RXPRS_DEFAULT (_LEUART_INPUT_RXPRS_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_INPUT */
<> 150:02e0a0aed4ec 700
<> 150:02e0a0aed4ec 701 /** @} End of group EFM32WG_LEUART */
<> 150:02e0a0aed4ec 702 /** @} End of group Parts */
<> 150:02e0a0aed4ec 703