Fawwaz Nadzmy / mbed-STM

mbed library sources. Supersedes mbed-src.

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targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_i2c.h@153:9398a535854b, 2016-12-22 (annotated)

Committer:
fwndz
Date:
Thu Dec 22 05:12:40 2016 +0000
Revision:
153:9398a535854b
Parent:
150:02e0a0aed4ec 
device target maximize

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 150:02e0a0aed4ec 1 /**************************************************************************//**
<> 150:02e0a0aed4ec 2 * @file efm32wg_i2c.h
<> 150:02e0a0aed4ec 3 * @brief EFM32WG_I2C register and bit field definitions
<> 150:02e0a0aed4ec 4 * @version 5.0.0
<> 150:02e0a0aed4ec 5 ******************************************************************************
<> 150:02e0a0aed4ec 6 * @section License
<> 150:02e0a0aed4ec 7 * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 150:02e0a0aed4ec 8 ******************************************************************************
<> 150:02e0a0aed4ec 9 *
<> 150:02e0a0aed4ec 10 * Permission is granted to anyone to use this software for any purpose,
<> 150:02e0a0aed4ec 11 * including commercial applications, and to alter it and redistribute it
<> 150:02e0a0aed4ec 12 * freely, subject to the following restrictions:
<> 150:02e0a0aed4ec 13 *
<> 150:02e0a0aed4ec 14 * 1. The origin of this software must not be misrepresented; you must not
<> 150:02e0a0aed4ec 15 * claim that you wrote the original software.@n
<> 150:02e0a0aed4ec 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 150:02e0a0aed4ec 17 * misrepresented as being the original software.@n
<> 150:02e0a0aed4ec 18 * 3. This notice may not be removed or altered from any source distribution.
<> 150:02e0a0aed4ec 19 *
<> 150:02e0a0aed4ec 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 150:02e0a0aed4ec 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 150:02e0a0aed4ec 22 * providing the Software "AS IS", with no express or implied warranties of any
<> 150:02e0a0aed4ec 23 * kind, including, but not limited to, any implied warranties of
<> 150:02e0a0aed4ec 24 * merchantability or fitness for any particular purpose or warranties against
<> 150:02e0a0aed4ec 25 * infringement of any proprietary rights of a third party.
<> 150:02e0a0aed4ec 26 *
<> 150:02e0a0aed4ec 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 150:02e0a0aed4ec 28 * incidental, or special damages, or any other relief, or for any claim by
<> 150:02e0a0aed4ec 29 * any third party, arising from your use of this Software.
<> 150:02e0a0aed4ec 30 *
<> 150:02e0a0aed4ec 31 *****************************************************************************/
<> 150:02e0a0aed4ec 32 /**************************************************************************//**
<> 150:02e0a0aed4ec 33 * @addtogroup Parts
<> 150:02e0a0aed4ec 34 * @{
<> 150:02e0a0aed4ec 35 ******************************************************************************/
<> 150:02e0a0aed4ec 36 /**************************************************************************//**
<> 150:02e0a0aed4ec 37 * @defgroup EFM32WG_I2C
<> 150:02e0a0aed4ec 38 * @{
<> 150:02e0a0aed4ec 39 * @brief EFM32WG_I2C Register Declaration
<> 150:02e0a0aed4ec 40 *****************************************************************************/
<> 150:02e0a0aed4ec 41 typedef struct
<> 150:02e0a0aed4ec 42 {
<> 150:02e0a0aed4ec 43 __IOM uint32_t CTRL; /**< Control Register */
<> 150:02e0a0aed4ec 44 __IOM uint32_t CMD; /**< Command Register */
<> 150:02e0a0aed4ec 45 __IM uint32_t STATE; /**< State Register */
<> 150:02e0a0aed4ec 46 __IM uint32_t STATUS; /**< Status Register */
<> 150:02e0a0aed4ec 47 __IOM uint32_t CLKDIV; /**< Clock Division Register */
<> 150:02e0a0aed4ec 48 __IOM uint32_t SADDR; /**< Slave Address Register */
<> 150:02e0a0aed4ec 49 __IOM uint32_t SADDRMASK; /**< Slave Address Mask Register */
<> 150:02e0a0aed4ec 50 __IM uint32_t RXDATA; /**< Receive Buffer Data Register */
<> 150:02e0a0aed4ec 51 __IM uint32_t RXDATAP; /**< Receive Buffer Data Peek Register */
<> 150:02e0a0aed4ec 52 __IOM uint32_t TXDATA; /**< Transmit Buffer Data Register */
<> 150:02e0a0aed4ec 53 __IM uint32_t IF; /**< Interrupt Flag Register */
<> 150:02e0a0aed4ec 54 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
<> 150:02e0a0aed4ec 55 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
<> 150:02e0a0aed4ec 56 __IOM uint32_t IEN; /**< Interrupt Enable Register */
<> 150:02e0a0aed4ec 57 __IOM uint32_t ROUTE; /**< I/O Routing Register */
<> 150:02e0a0aed4ec 58 } I2C_TypeDef; /** @} */
<> 150:02e0a0aed4ec 59
<> 150:02e0a0aed4ec 60 /**************************************************************************//**
<> 150:02e0a0aed4ec 61 * @defgroup EFM32WG_I2C_BitFields
<> 150:02e0a0aed4ec 62 * @{
<> 150:02e0a0aed4ec 63 *****************************************************************************/
<> 150:02e0a0aed4ec 64
<> 150:02e0a0aed4ec 65 /* Bit fields for I2C CTRL */
<> 150:02e0a0aed4ec 66 #define _I2C_CTRL_RESETVALUE 0x00000000UL /**< Default value for I2C_CTRL */
<> 150:02e0a0aed4ec 67 #define _I2C_CTRL_MASK 0x0007B37FUL /**< Mask for I2C_CTRL */
<> 150:02e0a0aed4ec 68 #define I2C_CTRL_EN (0x1UL << 0) /**< I2C Enable */
<> 150:02e0a0aed4ec 69 #define _I2C_CTRL_EN_SHIFT 0 /**< Shift value for I2C_EN */
<> 150:02e0a0aed4ec 70 #define _I2C_CTRL_EN_MASK 0x1UL /**< Bit mask for I2C_EN */
<> 150:02e0a0aed4ec 71 #define _I2C_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
<> 150:02e0a0aed4ec 72 #define I2C_CTRL_EN_DEFAULT (_I2C_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CTRL */
<> 150:02e0a0aed4ec 73 #define I2C_CTRL_SLAVE (0x1UL << 1) /**< Addressable as Slave */
<> 150:02e0a0aed4ec 74 #define _I2C_CTRL_SLAVE_SHIFT 1 /**< Shift value for I2C_SLAVE */
<> 150:02e0a0aed4ec 75 #define _I2C_CTRL_SLAVE_MASK 0x2UL /**< Bit mask for I2C_SLAVE */
<> 150:02e0a0aed4ec 76 #define _I2C_CTRL_SLAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
<> 150:02e0a0aed4ec 77 #define I2C_CTRL_SLAVE_DEFAULT (_I2C_CTRL_SLAVE_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CTRL */
<> 150:02e0a0aed4ec 78 #define I2C_CTRL_AUTOACK (0x1UL << 2) /**< Automatic Acknowledge */
<> 150:02e0a0aed4ec 79 #define _I2C_CTRL_AUTOACK_SHIFT 2 /**< Shift value for I2C_AUTOACK */
<> 150:02e0a0aed4ec 80 #define _I2C_CTRL_AUTOACK_MASK 0x4UL /**< Bit mask for I2C_AUTOACK */
<> 150:02e0a0aed4ec 81 #define _I2C_CTRL_AUTOACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
<> 150:02e0a0aed4ec 82 #define I2C_CTRL_AUTOACK_DEFAULT (_I2C_CTRL_AUTOACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CTRL */
<> 150:02e0a0aed4ec 83 #define I2C_CTRL_AUTOSE (0x1UL << 3) /**< Automatic STOP when Empty */
<> 150:02e0a0aed4ec 84 #define _I2C_CTRL_AUTOSE_SHIFT 3 /**< Shift value for I2C_AUTOSE */
<> 150:02e0a0aed4ec 85 #define _I2C_CTRL_AUTOSE_MASK 0x8UL /**< Bit mask for I2C_AUTOSE */
<> 150:02e0a0aed4ec 86 #define _I2C_CTRL_AUTOSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
<> 150:02e0a0aed4ec 87 #define I2C_CTRL_AUTOSE_DEFAULT (_I2C_CTRL_AUTOSE_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CTRL */
<> 150:02e0a0aed4ec 88 #define I2C_CTRL_AUTOSN (0x1UL << 4) /**< Automatic STOP on NACK */
<> 150:02e0a0aed4ec 89 #define _I2C_CTRL_AUTOSN_SHIFT 4 /**< Shift value for I2C_AUTOSN */
<> 150:02e0a0aed4ec 90 #define _I2C_CTRL_AUTOSN_MASK 0x10UL /**< Bit mask for I2C_AUTOSN */
<> 150:02e0a0aed4ec 91 #define _I2C_CTRL_AUTOSN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
<> 150:02e0a0aed4ec 92 #define I2C_CTRL_AUTOSN_DEFAULT (_I2C_CTRL_AUTOSN_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CTRL */
<> 150:02e0a0aed4ec 93 #define I2C_CTRL_ARBDIS (0x1UL << 5) /**< Arbitration Disable */
<> 150:02e0a0aed4ec 94 #define _I2C_CTRL_ARBDIS_SHIFT 5 /**< Shift value for I2C_ARBDIS */
<> 150:02e0a0aed4ec 95 #define _I2C_CTRL_ARBDIS_MASK 0x20UL /**< Bit mask for I2C_ARBDIS */
<> 150:02e0a0aed4ec 96 #define _I2C_CTRL_ARBDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
<> 150:02e0a0aed4ec 97 #define I2C_CTRL_ARBDIS_DEFAULT (_I2C_CTRL_ARBDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CTRL */
<> 150:02e0a0aed4ec 98 #define I2C_CTRL_GCAMEN (0x1UL << 6) /**< General Call Address Match Enable */
<> 150:02e0a0aed4ec 99 #define _I2C_CTRL_GCAMEN_SHIFT 6 /**< Shift value for I2C_GCAMEN */
<> 150:02e0a0aed4ec 100 #define _I2C_CTRL_GCAMEN_MASK 0x40UL /**< Bit mask for I2C_GCAMEN */
<> 150:02e0a0aed4ec 101 #define _I2C_CTRL_GCAMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
<> 150:02e0a0aed4ec 102 #define I2C_CTRL_GCAMEN_DEFAULT (_I2C_CTRL_GCAMEN_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CTRL */
<> 150:02e0a0aed4ec 103 #define _I2C_CTRL_CLHR_SHIFT 8 /**< Shift value for I2C_CLHR */
<> 150:02e0a0aed4ec 104 #define _I2C_CTRL_CLHR_MASK 0x300UL /**< Bit mask for I2C_CLHR */
<> 150:02e0a0aed4ec 105 #define _I2C_CTRL_CLHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
<> 150:02e0a0aed4ec 106 #define _I2C_CTRL_CLHR_STANDARD 0x00000000UL /**< Mode STANDARD for I2C_CTRL */
<> 150:02e0a0aed4ec 107 #define _I2C_CTRL_CLHR_ASYMMETRIC 0x00000001UL /**< Mode ASYMMETRIC for I2C_CTRL */
<> 150:02e0a0aed4ec 108 #define _I2C_CTRL_CLHR_FAST 0x00000002UL /**< Mode FAST for I2C_CTRL */
<> 150:02e0a0aed4ec 109 #define I2C_CTRL_CLHR_DEFAULT (_I2C_CTRL_CLHR_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_CTRL */
<> 150:02e0a0aed4ec 110 #define I2C_CTRL_CLHR_STANDARD (_I2C_CTRL_CLHR_STANDARD << 8) /**< Shifted mode STANDARD for I2C_CTRL */
<> 150:02e0a0aed4ec 111 #define I2C_CTRL_CLHR_ASYMMETRIC (_I2C_CTRL_CLHR_ASYMMETRIC << 8) /**< Shifted mode ASYMMETRIC for I2C_CTRL */
<> 150:02e0a0aed4ec 112 #define I2C_CTRL_CLHR_FAST (_I2C_CTRL_CLHR_FAST << 8) /**< Shifted mode FAST for I2C_CTRL */
<> 150:02e0a0aed4ec 113 #define _I2C_CTRL_BITO_SHIFT 12 /**< Shift value for I2C_BITO */
<> 150:02e0a0aed4ec 114 #define _I2C_CTRL_BITO_MASK 0x3000UL /**< Bit mask for I2C_BITO */
<> 150:02e0a0aed4ec 115 #define _I2C_CTRL_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
<> 150:02e0a0aed4ec 116 #define _I2C_CTRL_BITO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */
<> 150:02e0a0aed4ec 117 #define _I2C_CTRL_BITO_40PCC 0x00000001UL /**< Mode 40PCC for I2C_CTRL */
<> 150:02e0a0aed4ec 118 #define _I2C_CTRL_BITO_80PCC 0x00000002UL /**< Mode 80PCC for I2C_CTRL */
<> 150:02e0a0aed4ec 119 #define _I2C_CTRL_BITO_160PCC 0x00000003UL /**< Mode 160PCC for I2C_CTRL */
<> 150:02e0a0aed4ec 120 #define I2C_CTRL_BITO_DEFAULT (_I2C_CTRL_BITO_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_CTRL */
<> 150:02e0a0aed4ec 121 #define I2C_CTRL_BITO_OFF (_I2C_CTRL_BITO_OFF << 12) /**< Shifted mode OFF for I2C_CTRL */
<> 150:02e0a0aed4ec 122 #define I2C_CTRL_BITO_40PCC (_I2C_CTRL_BITO_40PCC << 12) /**< Shifted mode 40PCC for I2C_CTRL */
<> 150:02e0a0aed4ec 123 #define I2C_CTRL_BITO_80PCC (_I2C_CTRL_BITO_80PCC << 12) /**< Shifted mode 80PCC for I2C_CTRL */
<> 150:02e0a0aed4ec 124 #define I2C_CTRL_BITO_160PCC (_I2C_CTRL_BITO_160PCC << 12) /**< Shifted mode 160PCC for I2C_CTRL */
<> 150:02e0a0aed4ec 125 #define I2C_CTRL_GIBITO (0x1UL << 15) /**< Go Idle on Bus Idle Timeout */
<> 150:02e0a0aed4ec 126 #define _I2C_CTRL_GIBITO_SHIFT 15 /**< Shift value for I2C_GIBITO */
<> 150:02e0a0aed4ec 127 #define _I2C_CTRL_GIBITO_MASK 0x8000UL /**< Bit mask for I2C_GIBITO */
<> 150:02e0a0aed4ec 128 #define _I2C_CTRL_GIBITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
<> 150:02e0a0aed4ec 129 #define I2C_CTRL_GIBITO_DEFAULT (_I2C_CTRL_GIBITO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_CTRL */
<> 150:02e0a0aed4ec 130 #define _I2C_CTRL_CLTO_SHIFT 16 /**< Shift value for I2C_CLTO */
<> 150:02e0a0aed4ec 131 #define _I2C_CTRL_CLTO_MASK 0x70000UL /**< Bit mask for I2C_CLTO */
<> 150:02e0a0aed4ec 132 #define _I2C_CTRL_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
<> 150:02e0a0aed4ec 133 #define _I2C_CTRL_CLTO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */
<> 150:02e0a0aed4ec 134 #define _I2C_CTRL_CLTO_40PCC 0x00000001UL /**< Mode 40PCC for I2C_CTRL */
<> 150:02e0a0aed4ec 135 #define _I2C_CTRL_CLTO_80PCC 0x00000002UL /**< Mode 80PCC for I2C_CTRL */
<> 150:02e0a0aed4ec 136 #define _I2C_CTRL_CLTO_160PCC 0x00000003UL /**< Mode 160PCC for I2C_CTRL */
<> 150:02e0a0aed4ec 137 #define _I2C_CTRL_CLTO_320PPC 0x00000004UL /**< Mode 320PPC for I2C_CTRL */
<> 150:02e0a0aed4ec 138 #define _I2C_CTRL_CLTO_1024PPC 0x00000005UL /**< Mode 1024PPC for I2C_CTRL */
<> 150:02e0a0aed4ec 139 #define I2C_CTRL_CLTO_DEFAULT (_I2C_CTRL_CLTO_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_CTRL */
<> 150:02e0a0aed4ec 140 #define I2C_CTRL_CLTO_OFF (_I2C_CTRL_CLTO_OFF << 16) /**< Shifted mode OFF for I2C_CTRL */
<> 150:02e0a0aed4ec 141 #define I2C_CTRL_CLTO_40PCC (_I2C_CTRL_CLTO_40PCC << 16) /**< Shifted mode 40PCC for I2C_CTRL */
<> 150:02e0a0aed4ec 142 #define I2C_CTRL_CLTO_80PCC (_I2C_CTRL_CLTO_80PCC << 16) /**< Shifted mode 80PCC for I2C_CTRL */
<> 150:02e0a0aed4ec 143 #define I2C_CTRL_CLTO_160PCC (_I2C_CTRL_CLTO_160PCC << 16) /**< Shifted mode 160PCC for I2C_CTRL */
<> 150:02e0a0aed4ec 144 #define I2C_CTRL_CLTO_320PPC (_I2C_CTRL_CLTO_320PPC << 16) /**< Shifted mode 320PPC for I2C_CTRL */
<> 150:02e0a0aed4ec 145 #define I2C_CTRL_CLTO_1024PPC (_I2C_CTRL_CLTO_1024PPC << 16) /**< Shifted mode 1024PPC for I2C_CTRL */
<> 150:02e0a0aed4ec 146
<> 150:02e0a0aed4ec 147 /* Bit fields for I2C CMD */
<> 150:02e0a0aed4ec 148 #define _I2C_CMD_RESETVALUE 0x00000000UL /**< Default value for I2C_CMD */
<> 150:02e0a0aed4ec 149 #define _I2C_CMD_MASK 0x000000FFUL /**< Mask for I2C_CMD */
<> 150:02e0a0aed4ec 150 #define I2C_CMD_START (0x1UL << 0) /**< Send start condition */
<> 150:02e0a0aed4ec 151 #define _I2C_CMD_START_SHIFT 0 /**< Shift value for I2C_START */
<> 150:02e0a0aed4ec 152 #define _I2C_CMD_START_MASK 0x1UL /**< Bit mask for I2C_START */
<> 150:02e0a0aed4ec 153 #define _I2C_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
<> 150:02e0a0aed4ec 154 #define I2C_CMD_START_DEFAULT (_I2C_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CMD */
<> 150:02e0a0aed4ec 155 #define I2C_CMD_STOP (0x1UL << 1) /**< Send stop condition */
<> 150:02e0a0aed4ec 156 #define _I2C_CMD_STOP_SHIFT 1 /**< Shift value for I2C_STOP */
<> 150:02e0a0aed4ec 157 #define _I2C_CMD_STOP_MASK 0x2UL /**< Bit mask for I2C_STOP */
<> 150:02e0a0aed4ec 158 #define _I2C_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
<> 150:02e0a0aed4ec 159 #define I2C_CMD_STOP_DEFAULT (_I2C_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CMD */
<> 150:02e0a0aed4ec 160 #define I2C_CMD_ACK (0x1UL << 2) /**< Send ACK */
<> 150:02e0a0aed4ec 161 #define _I2C_CMD_ACK_SHIFT 2 /**< Shift value for I2C_ACK */
<> 150:02e0a0aed4ec 162 #define _I2C_CMD_ACK_MASK 0x4UL /**< Bit mask for I2C_ACK */
<> 150:02e0a0aed4ec 163 #define _I2C_CMD_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
<> 150:02e0a0aed4ec 164 #define I2C_CMD_ACK_DEFAULT (_I2C_CMD_ACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CMD */
<> 150:02e0a0aed4ec 165 #define I2C_CMD_NACK (0x1UL << 3) /**< Send NACK */
<> 150:02e0a0aed4ec 166 #define _I2C_CMD_NACK_SHIFT 3 /**< Shift value for I2C_NACK */
<> 150:02e0a0aed4ec 167 #define _I2C_CMD_NACK_MASK 0x8UL /**< Bit mask for I2C_NACK */
<> 150:02e0a0aed4ec 168 #define _I2C_CMD_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
<> 150:02e0a0aed4ec 169 #define I2C_CMD_NACK_DEFAULT (_I2C_CMD_NACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CMD */
<> 150:02e0a0aed4ec 170 #define I2C_CMD_CONT (0x1UL << 4) /**< Continue transmission */
<> 150:02e0a0aed4ec 171 #define _I2C_CMD_CONT_SHIFT 4 /**< Shift value for I2C_CONT */
<> 150:02e0a0aed4ec 172 #define _I2C_CMD_CONT_MASK 0x10UL /**< Bit mask for I2C_CONT */
<> 150:02e0a0aed4ec 173 #define _I2C_CMD_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
<> 150:02e0a0aed4ec 174 #define I2C_CMD_CONT_DEFAULT (_I2C_CMD_CONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CMD */
<> 150:02e0a0aed4ec 175 #define I2C_CMD_ABORT (0x1UL << 5) /**< Abort transmission */
<> 150:02e0a0aed4ec 176 #define _I2C_CMD_ABORT_SHIFT 5 /**< Shift value for I2C_ABORT */
<> 150:02e0a0aed4ec 177 #define _I2C_CMD_ABORT_MASK 0x20UL /**< Bit mask for I2C_ABORT */
<> 150:02e0a0aed4ec 178 #define _I2C_CMD_ABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
<> 150:02e0a0aed4ec 179 #define I2C_CMD_ABORT_DEFAULT (_I2C_CMD_ABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CMD */
<> 150:02e0a0aed4ec 180 #define I2C_CMD_CLEARTX (0x1UL << 6) /**< Clear TX */
<> 150:02e0a0aed4ec 181 #define _I2C_CMD_CLEARTX_SHIFT 6 /**< Shift value for I2C_CLEARTX */
<> 150:02e0a0aed4ec 182 #define _I2C_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for I2C_CLEARTX */
<> 150:02e0a0aed4ec 183 #define _I2C_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
<> 150:02e0a0aed4ec 184 #define I2C_CMD_CLEARTX_DEFAULT (_I2C_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CMD */
<> 150:02e0a0aed4ec 185 #define I2C_CMD_CLEARPC (0x1UL << 7) /**< Clear Pending Commands */
<> 150:02e0a0aed4ec 186 #define _I2C_CMD_CLEARPC_SHIFT 7 /**< Shift value for I2C_CLEARPC */
<> 150:02e0a0aed4ec 187 #define _I2C_CMD_CLEARPC_MASK 0x80UL /**< Bit mask for I2C_CLEARPC */
<> 150:02e0a0aed4ec 188 #define _I2C_CMD_CLEARPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
<> 150:02e0a0aed4ec 189 #define I2C_CMD_CLEARPC_DEFAULT (_I2C_CMD_CLEARPC_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CMD */
<> 150:02e0a0aed4ec 190
<> 150:02e0a0aed4ec 191 /* Bit fields for I2C STATE */
<> 150:02e0a0aed4ec 192 #define _I2C_STATE_RESETVALUE 0x00000001UL /**< Default value for I2C_STATE */
<> 150:02e0a0aed4ec 193 #define _I2C_STATE_MASK 0x000000FFUL /**< Mask for I2C_STATE */
<> 150:02e0a0aed4ec 194 #define I2C_STATE_BUSY (0x1UL << 0) /**< Bus Busy */
<> 150:02e0a0aed4ec 195 #define _I2C_STATE_BUSY_SHIFT 0 /**< Shift value for I2C_BUSY */
<> 150:02e0a0aed4ec 196 #define _I2C_STATE_BUSY_MASK 0x1UL /**< Bit mask for I2C_BUSY */
<> 150:02e0a0aed4ec 197 #define _I2C_STATE_BUSY_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATE */
<> 150:02e0a0aed4ec 198 #define I2C_STATE_BUSY_DEFAULT (_I2C_STATE_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATE */
<> 150:02e0a0aed4ec 199 #define I2C_STATE_MASTER (0x1UL << 1) /**< Master */
<> 150:02e0a0aed4ec 200 #define _I2C_STATE_MASTER_SHIFT 1 /**< Shift value for I2C_MASTER */
<> 150:02e0a0aed4ec 201 #define _I2C_STATE_MASTER_MASK 0x2UL /**< Bit mask for I2C_MASTER */
<> 150:02e0a0aed4ec 202 #define _I2C_STATE_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
<> 150:02e0a0aed4ec 203 #define I2C_STATE_MASTER_DEFAULT (_I2C_STATE_MASTER_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATE */
<> 150:02e0a0aed4ec 204 #define I2C_STATE_TRANSMITTER (0x1UL << 2) /**< Transmitter */
<> 150:02e0a0aed4ec 205 #define _I2C_STATE_TRANSMITTER_SHIFT 2 /**< Shift value for I2C_TRANSMITTER */
<> 150:02e0a0aed4ec 206 #define _I2C_STATE_TRANSMITTER_MASK 0x4UL /**< Bit mask for I2C_TRANSMITTER */
<> 150:02e0a0aed4ec 207 #define _I2C_STATE_TRANSMITTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
<> 150:02e0a0aed4ec 208 #define I2C_STATE_TRANSMITTER_DEFAULT (_I2C_STATE_TRANSMITTER_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATE */
<> 150:02e0a0aed4ec 209 #define I2C_STATE_NACKED (0x1UL << 3) /**< Nack Received */
<> 150:02e0a0aed4ec 210 #define _I2C_STATE_NACKED_SHIFT 3 /**< Shift value for I2C_NACKED */
<> 150:02e0a0aed4ec 211 #define _I2C_STATE_NACKED_MASK 0x8UL /**< Bit mask for I2C_NACKED */
<> 150:02e0a0aed4ec 212 #define _I2C_STATE_NACKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
<> 150:02e0a0aed4ec 213 #define I2C_STATE_NACKED_DEFAULT (_I2C_STATE_NACKED_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATE */
<> 150:02e0a0aed4ec 214 #define I2C_STATE_BUSHOLD (0x1UL << 4) /**< Bus Held */
<> 150:02e0a0aed4ec 215 #define _I2C_STATE_BUSHOLD_SHIFT 4 /**< Shift value for I2C_BUSHOLD */
<> 150:02e0a0aed4ec 216 #define _I2C_STATE_BUSHOLD_MASK 0x10UL /**< Bit mask for I2C_BUSHOLD */
<> 150:02e0a0aed4ec 217 #define _I2C_STATE_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
<> 150:02e0a0aed4ec 218 #define I2C_STATE_BUSHOLD_DEFAULT (_I2C_STATE_BUSHOLD_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATE */
<> 150:02e0a0aed4ec 219 #define _I2C_STATE_STATE_SHIFT 5 /**< Shift value for I2C_STATE */
<> 150:02e0a0aed4ec 220 #define _I2C_STATE_STATE_MASK 0xE0UL /**< Bit mask for I2C_STATE */
<> 150:02e0a0aed4ec 221 #define _I2C_STATE_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
<> 150:02e0a0aed4ec 222 #define _I2C_STATE_STATE_IDLE 0x00000000UL /**< Mode IDLE for I2C_STATE */
<> 150:02e0a0aed4ec 223 #define _I2C_STATE_STATE_WAIT 0x00000001UL /**< Mode WAIT for I2C_STATE */
<> 150:02e0a0aed4ec 224 #define _I2C_STATE_STATE_START 0x00000002UL /**< Mode START for I2C_STATE */
<> 150:02e0a0aed4ec 225 #define _I2C_STATE_STATE_ADDR 0x00000003UL /**< Mode ADDR for I2C_STATE */
<> 150:02e0a0aed4ec 226 #define _I2C_STATE_STATE_ADDRACK 0x00000004UL /**< Mode ADDRACK for I2C_STATE */
<> 150:02e0a0aed4ec 227 #define _I2C_STATE_STATE_DATA 0x00000005UL /**< Mode DATA for I2C_STATE */
<> 150:02e0a0aed4ec 228 #define _I2C_STATE_STATE_DATAACK 0x00000006UL /**< Mode DATAACK for I2C_STATE */
<> 150:02e0a0aed4ec 229 #define I2C_STATE_STATE_DEFAULT (_I2C_STATE_STATE_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATE */
<> 150:02e0a0aed4ec 230 #define I2C_STATE_STATE_IDLE (_I2C_STATE_STATE_IDLE << 5) /**< Shifted mode IDLE for I2C_STATE */
<> 150:02e0a0aed4ec 231 #define I2C_STATE_STATE_WAIT (_I2C_STATE_STATE_WAIT << 5) /**< Shifted mode WAIT for I2C_STATE */
<> 150:02e0a0aed4ec 232 #define I2C_STATE_STATE_START (_I2C_STATE_STATE_START << 5) /**< Shifted mode START for I2C_STATE */
<> 150:02e0a0aed4ec 233 #define I2C_STATE_STATE_ADDR (_I2C_STATE_STATE_ADDR << 5) /**< Shifted mode ADDR for I2C_STATE */
<> 150:02e0a0aed4ec 234 #define I2C_STATE_STATE_ADDRACK (_I2C_STATE_STATE_ADDRACK << 5) /**< Shifted mode ADDRACK for I2C_STATE */
<> 150:02e0a0aed4ec 235 #define I2C_STATE_STATE_DATA (_I2C_STATE_STATE_DATA << 5) /**< Shifted mode DATA for I2C_STATE */
<> 150:02e0a0aed4ec 236 #define I2C_STATE_STATE_DATAACK (_I2C_STATE_STATE_DATAACK << 5) /**< Shifted mode DATAACK for I2C_STATE */
<> 150:02e0a0aed4ec 237
<> 150:02e0a0aed4ec 238 /* Bit fields for I2C STATUS */
<> 150:02e0a0aed4ec 239 #define _I2C_STATUS_RESETVALUE 0x00000080UL /**< Default value for I2C_STATUS */
<> 150:02e0a0aed4ec 240 #define _I2C_STATUS_MASK 0x000001FFUL /**< Mask for I2C_STATUS */
<> 150:02e0a0aed4ec 241 #define I2C_STATUS_PSTART (0x1UL << 0) /**< Pending START */
<> 150:02e0a0aed4ec 242 #define _I2C_STATUS_PSTART_SHIFT 0 /**< Shift value for I2C_PSTART */
<> 150:02e0a0aed4ec 243 #define _I2C_STATUS_PSTART_MASK 0x1UL /**< Bit mask for I2C_PSTART */
<> 150:02e0a0aed4ec 244 #define _I2C_STATUS_PSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
<> 150:02e0a0aed4ec 245 #define I2C_STATUS_PSTART_DEFAULT (_I2C_STATUS_PSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATUS */
<> 150:02e0a0aed4ec 246 #define I2C_STATUS_PSTOP (0x1UL << 1) /**< Pending STOP */
<> 150:02e0a0aed4ec 247 #define _I2C_STATUS_PSTOP_SHIFT 1 /**< Shift value for I2C_PSTOP */
<> 150:02e0a0aed4ec 248 #define _I2C_STATUS_PSTOP_MASK 0x2UL /**< Bit mask for I2C_PSTOP */
<> 150:02e0a0aed4ec 249 #define _I2C_STATUS_PSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
<> 150:02e0a0aed4ec 250 #define I2C_STATUS_PSTOP_DEFAULT (_I2C_STATUS_PSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATUS */
<> 150:02e0a0aed4ec 251 #define I2C_STATUS_PACK (0x1UL << 2) /**< Pending ACK */
<> 150:02e0a0aed4ec 252 #define _I2C_STATUS_PACK_SHIFT 2 /**< Shift value for I2C_PACK */
<> 150:02e0a0aed4ec 253 #define _I2C_STATUS_PACK_MASK 0x4UL /**< Bit mask for I2C_PACK */
<> 150:02e0a0aed4ec 254 #define _I2C_STATUS_PACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
<> 150:02e0a0aed4ec 255 #define I2C_STATUS_PACK_DEFAULT (_I2C_STATUS_PACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATUS */
<> 150:02e0a0aed4ec 256 #define I2C_STATUS_PNACK (0x1UL << 3) /**< Pending NACK */
<> 150:02e0a0aed4ec 257 #define _I2C_STATUS_PNACK_SHIFT 3 /**< Shift value for I2C_PNACK */
<> 150:02e0a0aed4ec 258 #define _I2C_STATUS_PNACK_MASK 0x8UL /**< Bit mask for I2C_PNACK */
<> 150:02e0a0aed4ec 259 #define _I2C_STATUS_PNACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
<> 150:02e0a0aed4ec 260 #define I2C_STATUS_PNACK_DEFAULT (_I2C_STATUS_PNACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATUS */
<> 150:02e0a0aed4ec 261 #define I2C_STATUS_PCONT (0x1UL << 4) /**< Pending continue */
<> 150:02e0a0aed4ec 262 #define _I2C_STATUS_PCONT_SHIFT 4 /**< Shift value for I2C_PCONT */
<> 150:02e0a0aed4ec 263 #define _I2C_STATUS_PCONT_MASK 0x10UL /**< Bit mask for I2C_PCONT */
<> 150:02e0a0aed4ec 264 #define _I2C_STATUS_PCONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
<> 150:02e0a0aed4ec 265 #define I2C_STATUS_PCONT_DEFAULT (_I2C_STATUS_PCONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATUS */
<> 150:02e0a0aed4ec 266 #define I2C_STATUS_PABORT (0x1UL << 5) /**< Pending abort */
<> 150:02e0a0aed4ec 267 #define _I2C_STATUS_PABORT_SHIFT 5 /**< Shift value for I2C_PABORT */
<> 150:02e0a0aed4ec 268 #define _I2C_STATUS_PABORT_MASK 0x20UL /**< Bit mask for I2C_PABORT */
<> 150:02e0a0aed4ec 269 #define _I2C_STATUS_PABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
<> 150:02e0a0aed4ec 270 #define I2C_STATUS_PABORT_DEFAULT (_I2C_STATUS_PABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATUS */
<> 150:02e0a0aed4ec 271 #define I2C_STATUS_TXC (0x1UL << 6) /**< TX Complete */
<> 150:02e0a0aed4ec 272 #define _I2C_STATUS_TXC_SHIFT 6 /**< Shift value for I2C_TXC */
<> 150:02e0a0aed4ec 273 #define _I2C_STATUS_TXC_MASK 0x40UL /**< Bit mask for I2C_TXC */
<> 150:02e0a0aed4ec 274 #define _I2C_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
<> 150:02e0a0aed4ec 275 #define I2C_STATUS_TXC_DEFAULT (_I2C_STATUS_TXC_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_STATUS */
<> 150:02e0a0aed4ec 276 #define I2C_STATUS_TXBL (0x1UL << 7) /**< TX Buffer Level */
<> 150:02e0a0aed4ec 277 #define _I2C_STATUS_TXBL_SHIFT 7 /**< Shift value for I2C_TXBL */
<> 150:02e0a0aed4ec 278 #define _I2C_STATUS_TXBL_MASK 0x80UL /**< Bit mask for I2C_TXBL */
<> 150:02e0a0aed4ec 279 #define _I2C_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATUS */
<> 150:02e0a0aed4ec 280 #define I2C_STATUS_TXBL_DEFAULT (_I2C_STATUS_TXBL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_STATUS */
<> 150:02e0a0aed4ec 281 #define I2C_STATUS_RXDATAV (0x1UL << 8) /**< RX Data Valid */
<> 150:02e0a0aed4ec 282 #define _I2C_STATUS_RXDATAV_SHIFT 8 /**< Shift value for I2C_RXDATAV */
<> 150:02e0a0aed4ec 283 #define _I2C_STATUS_RXDATAV_MASK 0x100UL /**< Bit mask for I2C_RXDATAV */
<> 150:02e0a0aed4ec 284 #define _I2C_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
<> 150:02e0a0aed4ec 285 #define I2C_STATUS_RXDATAV_DEFAULT (_I2C_STATUS_RXDATAV_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_STATUS */
<> 150:02e0a0aed4ec 286
<> 150:02e0a0aed4ec 287 /* Bit fields for I2C CLKDIV */
<> 150:02e0a0aed4ec 288 #define _I2C_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for I2C_CLKDIV */
<> 150:02e0a0aed4ec 289 #define _I2C_CLKDIV_MASK 0x000001FFUL /**< Mask for I2C_CLKDIV */
<> 150:02e0a0aed4ec 290 #define _I2C_CLKDIV_DIV_SHIFT 0 /**< Shift value for I2C_DIV */
<> 150:02e0a0aed4ec 291 #define _I2C_CLKDIV_DIV_MASK 0x1FFUL /**< Bit mask for I2C_DIV */
<> 150:02e0a0aed4ec 292 #define _I2C_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CLKDIV */
<> 150:02e0a0aed4ec 293 #define I2C_CLKDIV_DIV_DEFAULT (_I2C_CLKDIV_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CLKDIV */
<> 150:02e0a0aed4ec 294
<> 150:02e0a0aed4ec 295 /* Bit fields for I2C SADDR */
<> 150:02e0a0aed4ec 296 #define _I2C_SADDR_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDR */
<> 150:02e0a0aed4ec 297 #define _I2C_SADDR_MASK 0x000000FEUL /**< Mask for I2C_SADDR */
<> 150:02e0a0aed4ec 298 #define _I2C_SADDR_ADDR_SHIFT 1 /**< Shift value for I2C_ADDR */
<> 150:02e0a0aed4ec 299 #define _I2C_SADDR_ADDR_MASK 0xFEUL /**< Bit mask for I2C_ADDR */
<> 150:02e0a0aed4ec 300 #define _I2C_SADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDR */
<> 150:02e0a0aed4ec 301 #define I2C_SADDR_ADDR_DEFAULT (_I2C_SADDR_ADDR_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDR */
<> 150:02e0a0aed4ec 302
<> 150:02e0a0aed4ec 303 /* Bit fields for I2C SADDRMASK */
<> 150:02e0a0aed4ec 304 #define _I2C_SADDRMASK_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDRMASK */
<> 150:02e0a0aed4ec 305 #define _I2C_SADDRMASK_MASK 0x000000FEUL /**< Mask for I2C_SADDRMASK */
<> 150:02e0a0aed4ec 306 #define _I2C_SADDRMASK_MASK_SHIFT 1 /**< Shift value for I2C_MASK */
<> 150:02e0a0aed4ec 307 #define _I2C_SADDRMASK_MASK_MASK 0xFEUL /**< Bit mask for I2C_MASK */
<> 150:02e0a0aed4ec 308 #define _I2C_SADDRMASK_MASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDRMASK */
<> 150:02e0a0aed4ec 309 #define I2C_SADDRMASK_MASK_DEFAULT (_I2C_SADDRMASK_MASK_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDRMASK */
<> 150:02e0a0aed4ec 310
<> 150:02e0a0aed4ec 311 /* Bit fields for I2C RXDATA */
<> 150:02e0a0aed4ec 312 #define _I2C_RXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATA */
<> 150:02e0a0aed4ec 313 #define _I2C_RXDATA_MASK 0x000000FFUL /**< Mask for I2C_RXDATA */
<> 150:02e0a0aed4ec 314 #define _I2C_RXDATA_RXDATA_SHIFT 0 /**< Shift value for I2C_RXDATA */
<> 150:02e0a0aed4ec 315 #define _I2C_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for I2C_RXDATA */
<> 150:02e0a0aed4ec 316 #define _I2C_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATA */
<> 150:02e0a0aed4ec 317 #define I2C_RXDATA_RXDATA_DEFAULT (_I2C_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATA */
<> 150:02e0a0aed4ec 318
<> 150:02e0a0aed4ec 319 /* Bit fields for I2C RXDATAP */
<> 150:02e0a0aed4ec 320 #define _I2C_RXDATAP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATAP */
<> 150:02e0a0aed4ec 321 #define _I2C_RXDATAP_MASK 0x000000FFUL /**< Mask for I2C_RXDATAP */
<> 150:02e0a0aed4ec 322 #define _I2C_RXDATAP_RXDATAP_SHIFT 0 /**< Shift value for I2C_RXDATAP */
<> 150:02e0a0aed4ec 323 #define _I2C_RXDATAP_RXDATAP_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP */
<> 150:02e0a0aed4ec 324 #define _I2C_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATAP */
<> 150:02e0a0aed4ec 325 #define I2C_RXDATAP_RXDATAP_DEFAULT (_I2C_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATAP */
<> 150:02e0a0aed4ec 326
<> 150:02e0a0aed4ec 327 /* Bit fields for I2C TXDATA */
<> 150:02e0a0aed4ec 328 #define _I2C_TXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDATA */
<> 150:02e0a0aed4ec 329 #define _I2C_TXDATA_MASK 0x000000FFUL /**< Mask for I2C_TXDATA */
<> 150:02e0a0aed4ec 330 #define _I2C_TXDATA_TXDATA_SHIFT 0 /**< Shift value for I2C_TXDATA */
<> 150:02e0a0aed4ec 331 #define _I2C_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for I2C_TXDATA */
<> 150:02e0a0aed4ec 332 #define _I2C_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDATA */
<> 150:02e0a0aed4ec 333 #define I2C_TXDATA_TXDATA_DEFAULT (_I2C_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDATA */
<> 150:02e0a0aed4ec 334
<> 150:02e0a0aed4ec 335 /* Bit fields for I2C IF */
<> 150:02e0a0aed4ec 336 #define _I2C_IF_RESETVALUE 0x00000010UL /**< Default value for I2C_IF */
<> 150:02e0a0aed4ec 337 #define _I2C_IF_MASK 0x0001FFFFUL /**< Mask for I2C_IF */
<> 150:02e0a0aed4ec 338 #define I2C_IF_START (0x1UL << 0) /**< START condition Interrupt Flag */
<> 150:02e0a0aed4ec 339 #define _I2C_IF_START_SHIFT 0 /**< Shift value for I2C_START */
<> 150:02e0a0aed4ec 340 #define _I2C_IF_START_MASK 0x1UL /**< Bit mask for I2C_START */
<> 150:02e0a0aed4ec 341 #define _I2C_IF_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
<> 150:02e0a0aed4ec 342 #define I2C_IF_START_DEFAULT (_I2C_IF_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IF */
<> 150:02e0a0aed4ec 343 #define I2C_IF_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Flag */
<> 150:02e0a0aed4ec 344 #define _I2C_IF_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
<> 150:02e0a0aed4ec 345 #define _I2C_IF_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
<> 150:02e0a0aed4ec 346 #define _I2C_IF_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
<> 150:02e0a0aed4ec 347 #define I2C_IF_RSTART_DEFAULT (_I2C_IF_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IF */
<> 150:02e0a0aed4ec 348 #define I2C_IF_ADDR (0x1UL << 2) /**< Address Interrupt Flag */
<> 150:02e0a0aed4ec 349 #define _I2C_IF_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */
<> 150:02e0a0aed4ec 350 #define _I2C_IF_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */
<> 150:02e0a0aed4ec 351 #define _I2C_IF_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
<> 150:02e0a0aed4ec 352 #define I2C_IF_ADDR_DEFAULT (_I2C_IF_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IF */
<> 150:02e0a0aed4ec 353 #define I2C_IF_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Flag */
<> 150:02e0a0aed4ec 354 #define _I2C_IF_TXC_SHIFT 3 /**< Shift value for I2C_TXC */
<> 150:02e0a0aed4ec 355 #define _I2C_IF_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */
<> 150:02e0a0aed4ec 356 #define _I2C_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
<> 150:02e0a0aed4ec 357 #define I2C_IF_TXC_DEFAULT (_I2C_IF_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IF */
<> 150:02e0a0aed4ec 358 #define I2C_IF_TXBL (0x1UL << 4) /**< Transmit Buffer Level Interrupt Flag */
<> 150:02e0a0aed4ec 359 #define _I2C_IF_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */
<> 150:02e0a0aed4ec 360 #define _I2C_IF_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */
<> 150:02e0a0aed4ec 361 #define _I2C_IF_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
<> 150:02e0a0aed4ec 362 #define I2C_IF_TXBL_DEFAULT (_I2C_IF_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IF */
<> 150:02e0a0aed4ec 363 #define I2C_IF_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Flag */
<> 150:02e0a0aed4ec 364 #define _I2C_IF_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */
<> 150:02e0a0aed4ec 365 #define _I2C_IF_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */
<> 150:02e0a0aed4ec 366 #define _I2C_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
<> 150:02e0a0aed4ec 367 #define I2C_IF_RXDATAV_DEFAULT (_I2C_IF_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IF */
<> 150:02e0a0aed4ec 368 #define I2C_IF_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Flag */
<> 150:02e0a0aed4ec 369 #define _I2C_IF_ACK_SHIFT 6 /**< Shift value for I2C_ACK */
<> 150:02e0a0aed4ec 370 #define _I2C_IF_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */
<> 150:02e0a0aed4ec 371 #define _I2C_IF_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
<> 150:02e0a0aed4ec 372 #define I2C_IF_ACK_DEFAULT (_I2C_IF_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IF */
<> 150:02e0a0aed4ec 373 #define I2C_IF_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Flag */
<> 150:02e0a0aed4ec 374 #define _I2C_IF_NACK_SHIFT 7 /**< Shift value for I2C_NACK */
<> 150:02e0a0aed4ec 375 #define _I2C_IF_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */
<> 150:02e0a0aed4ec 376 #define _I2C_IF_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
<> 150:02e0a0aed4ec 377 #define I2C_IF_NACK_DEFAULT (_I2C_IF_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IF */
<> 150:02e0a0aed4ec 378 #define I2C_IF_MSTOP (0x1UL << 8) /**< Master STOP Condition Interrupt Flag */
<> 150:02e0a0aed4ec 379 #define _I2C_IF_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */
<> 150:02e0a0aed4ec 380 #define _I2C_IF_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */
<> 150:02e0a0aed4ec 381 #define _I2C_IF_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
<> 150:02e0a0aed4ec 382 #define I2C_IF_MSTOP_DEFAULT (_I2C_IF_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IF */
<> 150:02e0a0aed4ec 383 #define I2C_IF_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Flag */
<> 150:02e0a0aed4ec 384 #define _I2C_IF_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */
<> 150:02e0a0aed4ec 385 #define _I2C_IF_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */
<> 150:02e0a0aed4ec 386 #define _I2C_IF_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
<> 150:02e0a0aed4ec 387 #define I2C_IF_ARBLOST_DEFAULT (_I2C_IF_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IF */
<> 150:02e0a0aed4ec 388 #define I2C_IF_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Flag */
<> 150:02e0a0aed4ec 389 #define _I2C_IF_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */
<> 150:02e0a0aed4ec 390 #define _I2C_IF_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */
<> 150:02e0a0aed4ec 391 #define _I2C_IF_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
<> 150:02e0a0aed4ec 392 #define I2C_IF_BUSERR_DEFAULT (_I2C_IF_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IF */
<> 150:02e0a0aed4ec 393 #define I2C_IF_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Flag */
<> 150:02e0a0aed4ec 394 #define _I2C_IF_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */
<> 150:02e0a0aed4ec 395 #define _I2C_IF_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */
<> 150:02e0a0aed4ec 396 #define _I2C_IF_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
<> 150:02e0a0aed4ec 397 #define I2C_IF_BUSHOLD_DEFAULT (_I2C_IF_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IF */
<> 150:02e0a0aed4ec 398 #define I2C_IF_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Flag */
<> 150:02e0a0aed4ec 399 #define _I2C_IF_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */
<> 150:02e0a0aed4ec 400 #define _I2C_IF_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */
<> 150:02e0a0aed4ec 401 #define _I2C_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
<> 150:02e0a0aed4ec 402 #define I2C_IF_TXOF_DEFAULT (_I2C_IF_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IF */
<> 150:02e0a0aed4ec 403 #define I2C_IF_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Flag */
<> 150:02e0a0aed4ec 404 #define _I2C_IF_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */
<> 150:02e0a0aed4ec 405 #define _I2C_IF_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */
<> 150:02e0a0aed4ec 406 #define _I2C_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
<> 150:02e0a0aed4ec 407 #define I2C_IF_RXUF_DEFAULT (_I2C_IF_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IF */
<> 150:02e0a0aed4ec 408 #define I2C_IF_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Flag */
<> 150:02e0a0aed4ec 409 #define _I2C_IF_BITO_SHIFT 14 /**< Shift value for I2C_BITO */
<> 150:02e0a0aed4ec 410 #define _I2C_IF_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */
<> 150:02e0a0aed4ec 411 #define _I2C_IF_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
<> 150:02e0a0aed4ec 412 #define I2C_IF_BITO_DEFAULT (_I2C_IF_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IF */
<> 150:02e0a0aed4ec 413 #define I2C_IF_CLTO (0x1UL << 15) /**< Clock Low Timeout Interrupt Flag */
<> 150:02e0a0aed4ec 414 #define _I2C_IF_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */
<> 150:02e0a0aed4ec 415 #define _I2C_IF_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
<> 150:02e0a0aed4ec 416 #define _I2C_IF_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
<> 150:02e0a0aed4ec 417 #define I2C_IF_CLTO_DEFAULT (_I2C_IF_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IF */
<> 150:02e0a0aed4ec 418 #define I2C_IF_SSTOP (0x1UL << 16) /**< Slave STOP condition Interrupt Flag */
<> 150:02e0a0aed4ec 419 #define _I2C_IF_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
<> 150:02e0a0aed4ec 420 #define _I2C_IF_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
<> 150:02e0a0aed4ec 421 #define _I2C_IF_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
<> 150:02e0a0aed4ec 422 #define I2C_IF_SSTOP_DEFAULT (_I2C_IF_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IF */
<> 150:02e0a0aed4ec 423
<> 150:02e0a0aed4ec 424 /* Bit fields for I2C IFS */
<> 150:02e0a0aed4ec 425 #define _I2C_IFS_RESETVALUE 0x00000000UL /**< Default value for I2C_IFS */
<> 150:02e0a0aed4ec 426 #define _I2C_IFS_MASK 0x0001FFCFUL /**< Mask for I2C_IFS */
<> 150:02e0a0aed4ec 427 #define I2C_IFS_START (0x1UL << 0) /**< Set START Interrupt Flag */
<> 150:02e0a0aed4ec 428 #define _I2C_IFS_START_SHIFT 0 /**< Shift value for I2C_START */
<> 150:02e0a0aed4ec 429 #define _I2C_IFS_START_MASK 0x1UL /**< Bit mask for I2C_START */
<> 150:02e0a0aed4ec 430 #define _I2C_IFS_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
<> 150:02e0a0aed4ec 431 #define I2C_IFS_START_DEFAULT (_I2C_IFS_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IFS */
<> 150:02e0a0aed4ec 432 #define I2C_IFS_RSTART (0x1UL << 1) /**< Set Repeated START Interrupt Flag */
<> 150:02e0a0aed4ec 433 #define _I2C_IFS_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
<> 150:02e0a0aed4ec 434 #define _I2C_IFS_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
<> 150:02e0a0aed4ec 435 #define _I2C_IFS_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
<> 150:02e0a0aed4ec 436 #define I2C_IFS_RSTART_DEFAULT (_I2C_IFS_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IFS */
<> 150:02e0a0aed4ec 437 #define I2C_IFS_ADDR (0x1UL << 2) /**< Set Address Interrupt Flag */
<> 150:02e0a0aed4ec 438 #define _I2C_IFS_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */
<> 150:02e0a0aed4ec 439 #define _I2C_IFS_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */
<> 150:02e0a0aed4ec 440 #define _I2C_IFS_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
<> 150:02e0a0aed4ec 441 #define I2C_IFS_ADDR_DEFAULT (_I2C_IFS_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IFS */
<> 150:02e0a0aed4ec 442 #define I2C_IFS_TXC (0x1UL << 3) /**< Set Transfer Completed Interrupt Flag */
<> 150:02e0a0aed4ec 443 #define _I2C_IFS_TXC_SHIFT 3 /**< Shift value for I2C_TXC */
<> 150:02e0a0aed4ec 444 #define _I2C_IFS_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */
<> 150:02e0a0aed4ec 445 #define _I2C_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
<> 150:02e0a0aed4ec 446 #define I2C_IFS_TXC_DEFAULT (_I2C_IFS_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IFS */
<> 150:02e0a0aed4ec 447 #define I2C_IFS_ACK (0x1UL << 6) /**< Set Acknowledge Received Interrupt Flag */
<> 150:02e0a0aed4ec 448 #define _I2C_IFS_ACK_SHIFT 6 /**< Shift value for I2C_ACK */
<> 150:02e0a0aed4ec 449 #define _I2C_IFS_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */
<> 150:02e0a0aed4ec 450 #define _I2C_IFS_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
<> 150:02e0a0aed4ec 451 #define I2C_IFS_ACK_DEFAULT (_I2C_IFS_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IFS */
<> 150:02e0a0aed4ec 452 #define I2C_IFS_NACK (0x1UL << 7) /**< Set Not Acknowledge Received Interrupt Flag */
<> 150:02e0a0aed4ec 453 #define _I2C_IFS_NACK_SHIFT 7 /**< Shift value for I2C_NACK */
<> 150:02e0a0aed4ec 454 #define _I2C_IFS_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */
<> 150:02e0a0aed4ec 455 #define _I2C_IFS_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
<> 150:02e0a0aed4ec 456 #define I2C_IFS_NACK_DEFAULT (_I2C_IFS_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IFS */
<> 150:02e0a0aed4ec 457 #define I2C_IFS_MSTOP (0x1UL << 8) /**< Set MSTOP Interrupt Flag */
<> 150:02e0a0aed4ec 458 #define _I2C_IFS_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */
<> 150:02e0a0aed4ec 459 #define _I2C_IFS_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */
<> 150:02e0a0aed4ec 460 #define _I2C_IFS_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
<> 150:02e0a0aed4ec 461 #define I2C_IFS_MSTOP_DEFAULT (_I2C_IFS_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IFS */
<> 150:02e0a0aed4ec 462 #define I2C_IFS_ARBLOST (0x1UL << 9) /**< Set Arbitration Lost Interrupt Flag */
<> 150:02e0a0aed4ec 463 #define _I2C_IFS_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */
<> 150:02e0a0aed4ec 464 #define _I2C_IFS_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */
<> 150:02e0a0aed4ec 465 #define _I2C_IFS_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
<> 150:02e0a0aed4ec 466 #define I2C_IFS_ARBLOST_DEFAULT (_I2C_IFS_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IFS */
<> 150:02e0a0aed4ec 467 #define I2C_IFS_BUSERR (0x1UL << 10) /**< Set Bus Error Interrupt Flag */
<> 150:02e0a0aed4ec 468 #define _I2C_IFS_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */
<> 150:02e0a0aed4ec 469 #define _I2C_IFS_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */
<> 150:02e0a0aed4ec 470 #define _I2C_IFS_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
<> 150:02e0a0aed4ec 471 #define I2C_IFS_BUSERR_DEFAULT (_I2C_IFS_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IFS */
<> 150:02e0a0aed4ec 472 #define I2C_IFS_BUSHOLD (0x1UL << 11) /**< Set Bus Held Interrupt Flag */
<> 150:02e0a0aed4ec 473 #define _I2C_IFS_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */
<> 150:02e0a0aed4ec 474 #define _I2C_IFS_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */
<> 150:02e0a0aed4ec 475 #define _I2C_IFS_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
<> 150:02e0a0aed4ec 476 #define I2C_IFS_BUSHOLD_DEFAULT (_I2C_IFS_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IFS */
<> 150:02e0a0aed4ec 477 #define I2C_IFS_TXOF (0x1UL << 12) /**< Set Transmit Buffer Overflow Interrupt Flag */
<> 150:02e0a0aed4ec 478 #define _I2C_IFS_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */
<> 150:02e0a0aed4ec 479 #define _I2C_IFS_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */
<> 150:02e0a0aed4ec 480 #define _I2C_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
<> 150:02e0a0aed4ec 481 #define I2C_IFS_TXOF_DEFAULT (_I2C_IFS_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IFS */
<> 150:02e0a0aed4ec 482 #define I2C_IFS_RXUF (0x1UL << 13) /**< Set Receive Buffer Underflow Interrupt Flag */
<> 150:02e0a0aed4ec 483 #define _I2C_IFS_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */
<> 150:02e0a0aed4ec 484 #define _I2C_IFS_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */
<> 150:02e0a0aed4ec 485 #define _I2C_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
<> 150:02e0a0aed4ec 486 #define I2C_IFS_RXUF_DEFAULT (_I2C_IFS_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IFS */
<> 150:02e0a0aed4ec 487 #define I2C_IFS_BITO (0x1UL << 14) /**< Set Bus Idle Timeout Interrupt Flag */
<> 150:02e0a0aed4ec 488 #define _I2C_IFS_BITO_SHIFT 14 /**< Shift value for I2C_BITO */
<> 150:02e0a0aed4ec 489 #define _I2C_IFS_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */
<> 150:02e0a0aed4ec 490 #define _I2C_IFS_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
<> 150:02e0a0aed4ec 491 #define I2C_IFS_BITO_DEFAULT (_I2C_IFS_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IFS */
<> 150:02e0a0aed4ec 492 #define I2C_IFS_CLTO (0x1UL << 15) /**< Set Clock Low Interrupt Flag */
<> 150:02e0a0aed4ec 493 #define _I2C_IFS_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */
<> 150:02e0a0aed4ec 494 #define _I2C_IFS_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
<> 150:02e0a0aed4ec 495 #define _I2C_IFS_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
<> 150:02e0a0aed4ec 496 #define I2C_IFS_CLTO_DEFAULT (_I2C_IFS_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IFS */
<> 150:02e0a0aed4ec 497 #define I2C_IFS_SSTOP (0x1UL << 16) /**< Set SSTOP Interrupt Flag */
<> 150:02e0a0aed4ec 498 #define _I2C_IFS_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
<> 150:02e0a0aed4ec 499 #define _I2C_IFS_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
<> 150:02e0a0aed4ec 500 #define _I2C_IFS_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
<> 150:02e0a0aed4ec 501 #define I2C_IFS_SSTOP_DEFAULT (_I2C_IFS_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IFS */
<> 150:02e0a0aed4ec 502
<> 150:02e0a0aed4ec 503 /* Bit fields for I2C IFC */
<> 150:02e0a0aed4ec 504 #define _I2C_IFC_RESETVALUE 0x00000000UL /**< Default value for I2C_IFC */
<> 150:02e0a0aed4ec 505 #define _I2C_IFC_MASK 0x0001FFCFUL /**< Mask for I2C_IFC */
<> 150:02e0a0aed4ec 506 #define I2C_IFC_START (0x1UL << 0) /**< Clear START Interrupt Flag */
<> 150:02e0a0aed4ec 507 #define _I2C_IFC_START_SHIFT 0 /**< Shift value for I2C_START */
<> 150:02e0a0aed4ec 508 #define _I2C_IFC_START_MASK 0x1UL /**< Bit mask for I2C_START */
<> 150:02e0a0aed4ec 509 #define _I2C_IFC_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
<> 150:02e0a0aed4ec 510 #define I2C_IFC_START_DEFAULT (_I2C_IFC_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IFC */
<> 150:02e0a0aed4ec 511 #define I2C_IFC_RSTART (0x1UL << 1) /**< Clear Repeated START Interrupt Flag */
<> 150:02e0a0aed4ec 512 #define _I2C_IFC_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
<> 150:02e0a0aed4ec 513 #define _I2C_IFC_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
<> 150:02e0a0aed4ec 514 #define _I2C_IFC_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
<> 150:02e0a0aed4ec 515 #define I2C_IFC_RSTART_DEFAULT (_I2C_IFC_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IFC */
<> 150:02e0a0aed4ec 516 #define I2C_IFC_ADDR (0x1UL << 2) /**< Clear Address Interrupt Flag */
<> 150:02e0a0aed4ec 517 #define _I2C_IFC_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */
<> 150:02e0a0aed4ec 518 #define _I2C_IFC_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */
<> 150:02e0a0aed4ec 519 #define _I2C_IFC_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
<> 150:02e0a0aed4ec 520 #define I2C_IFC_ADDR_DEFAULT (_I2C_IFC_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IFC */
<> 150:02e0a0aed4ec 521 #define I2C_IFC_TXC (0x1UL << 3) /**< Clear Transfer Completed Interrupt Flag */
<> 150:02e0a0aed4ec 522 #define _I2C_IFC_TXC_SHIFT 3 /**< Shift value for I2C_TXC */
<> 150:02e0a0aed4ec 523 #define _I2C_IFC_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */
<> 150:02e0a0aed4ec 524 #define _I2C_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
<> 150:02e0a0aed4ec 525 #define I2C_IFC_TXC_DEFAULT (_I2C_IFC_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IFC */
<> 150:02e0a0aed4ec 526 #define I2C_IFC_ACK (0x1UL << 6) /**< Clear Acknowledge Received Interrupt Flag */
<> 150:02e0a0aed4ec 527 #define _I2C_IFC_ACK_SHIFT 6 /**< Shift value for I2C_ACK */
<> 150:02e0a0aed4ec 528 #define _I2C_IFC_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */
<> 150:02e0a0aed4ec 529 #define _I2C_IFC_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
<> 150:02e0a0aed4ec 530 #define I2C_IFC_ACK_DEFAULT (_I2C_IFC_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IFC */
<> 150:02e0a0aed4ec 531 #define I2C_IFC_NACK (0x1UL << 7) /**< Clear Not Acknowledge Received Interrupt Flag */
<> 150:02e0a0aed4ec 532 #define _I2C_IFC_NACK_SHIFT 7 /**< Shift value for I2C_NACK */
<> 150:02e0a0aed4ec 533 #define _I2C_IFC_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */
<> 150:02e0a0aed4ec 534 #define _I2C_IFC_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
<> 150:02e0a0aed4ec 535 #define I2C_IFC_NACK_DEFAULT (_I2C_IFC_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IFC */
<> 150:02e0a0aed4ec 536 #define I2C_IFC_MSTOP (0x1UL << 8) /**< Clear MSTOP Interrupt Flag */
<> 150:02e0a0aed4ec 537 #define _I2C_IFC_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */
<> 150:02e0a0aed4ec 538 #define _I2C_IFC_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */
<> 150:02e0a0aed4ec 539 #define _I2C_IFC_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
<> 150:02e0a0aed4ec 540 #define I2C_IFC_MSTOP_DEFAULT (_I2C_IFC_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IFC */
<> 150:02e0a0aed4ec 541 #define I2C_IFC_ARBLOST (0x1UL << 9) /**< Clear Arbitration Lost Interrupt Flag */
<> 150:02e0a0aed4ec 542 #define _I2C_IFC_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */
<> 150:02e0a0aed4ec 543 #define _I2C_IFC_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */
<> 150:02e0a0aed4ec 544 #define _I2C_IFC_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
<> 150:02e0a0aed4ec 545 #define I2C_IFC_ARBLOST_DEFAULT (_I2C_IFC_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IFC */
<> 150:02e0a0aed4ec 546 #define I2C_IFC_BUSERR (0x1UL << 10) /**< Clear Bus Error Interrupt Flag */
<> 150:02e0a0aed4ec 547 #define _I2C_IFC_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */
<> 150:02e0a0aed4ec 548 #define _I2C_IFC_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */
<> 150:02e0a0aed4ec 549 #define _I2C_IFC_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
<> 150:02e0a0aed4ec 550 #define I2C_IFC_BUSERR_DEFAULT (_I2C_IFC_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IFC */
<> 150:02e0a0aed4ec 551 #define I2C_IFC_BUSHOLD (0x1UL << 11) /**< Clear Bus Held Interrupt Flag */
<> 150:02e0a0aed4ec 552 #define _I2C_IFC_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */
<> 150:02e0a0aed4ec 553 #define _I2C_IFC_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */
<> 150:02e0a0aed4ec 554 #define _I2C_IFC_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
<> 150:02e0a0aed4ec 555 #define I2C_IFC_BUSHOLD_DEFAULT (_I2C_IFC_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IFC */
<> 150:02e0a0aed4ec 556 #define I2C_IFC_TXOF (0x1UL << 12) /**< Clear Transmit Buffer Overflow Interrupt Flag */
<> 150:02e0a0aed4ec 557 #define _I2C_IFC_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */
<> 150:02e0a0aed4ec 558 #define _I2C_IFC_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */
<> 150:02e0a0aed4ec 559 #define _I2C_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
<> 150:02e0a0aed4ec 560 #define I2C_IFC_TXOF_DEFAULT (_I2C_IFC_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IFC */
<> 150:02e0a0aed4ec 561 #define I2C_IFC_RXUF (0x1UL << 13) /**< Clear Receive Buffer Underflow Interrupt Flag */
<> 150:02e0a0aed4ec 562 #define _I2C_IFC_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */
<> 150:02e0a0aed4ec 563 #define _I2C_IFC_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */
<> 150:02e0a0aed4ec 564 #define _I2C_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
<> 150:02e0a0aed4ec 565 #define I2C_IFC_RXUF_DEFAULT (_I2C_IFC_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IFC */
<> 150:02e0a0aed4ec 566 #define I2C_IFC_BITO (0x1UL << 14) /**< Clear Bus Idle Timeout Interrupt Flag */
<> 150:02e0a0aed4ec 567 #define _I2C_IFC_BITO_SHIFT 14 /**< Shift value for I2C_BITO */
<> 150:02e0a0aed4ec 568 #define _I2C_IFC_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */
<> 150:02e0a0aed4ec 569 #define _I2C_IFC_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
<> 150:02e0a0aed4ec 570 #define I2C_IFC_BITO_DEFAULT (_I2C_IFC_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IFC */
<> 150:02e0a0aed4ec 571 #define I2C_IFC_CLTO (0x1UL << 15) /**< Clear Clock Low Interrupt Flag */
<> 150:02e0a0aed4ec 572 #define _I2C_IFC_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */
<> 150:02e0a0aed4ec 573 #define _I2C_IFC_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
<> 150:02e0a0aed4ec 574 #define _I2C_IFC_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
<> 150:02e0a0aed4ec 575 #define I2C_IFC_CLTO_DEFAULT (_I2C_IFC_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IFC */
<> 150:02e0a0aed4ec 576 #define I2C_IFC_SSTOP (0x1UL << 16) /**< Clear SSTOP Interrupt Flag */
<> 150:02e0a0aed4ec 577 #define _I2C_IFC_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
<> 150:02e0a0aed4ec 578 #define _I2C_IFC_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
<> 150:02e0a0aed4ec 579 #define _I2C_IFC_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
<> 150:02e0a0aed4ec 580 #define I2C_IFC_SSTOP_DEFAULT (_I2C_IFC_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IFC */
<> 150:02e0a0aed4ec 581
<> 150:02e0a0aed4ec 582 /* Bit fields for I2C IEN */
<> 150:02e0a0aed4ec 583 #define _I2C_IEN_RESETVALUE 0x00000000UL /**< Default value for I2C_IEN */
<> 150:02e0a0aed4ec 584 #define _I2C_IEN_MASK 0x0001FFFFUL /**< Mask for I2C_IEN */
<> 150:02e0a0aed4ec 585 #define I2C_IEN_START (0x1UL << 0) /**< START Condition Interrupt Enable */
<> 150:02e0a0aed4ec 586 #define _I2C_IEN_START_SHIFT 0 /**< Shift value for I2C_START */
<> 150:02e0a0aed4ec 587 #define _I2C_IEN_START_MASK 0x1UL /**< Bit mask for I2C_START */
<> 150:02e0a0aed4ec 588 #define _I2C_IEN_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
<> 150:02e0a0aed4ec 589 #define I2C_IEN_START_DEFAULT (_I2C_IEN_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IEN */
<> 150:02e0a0aed4ec 590 #define I2C_IEN_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Enable */
<> 150:02e0a0aed4ec 591 #define _I2C_IEN_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
<> 150:02e0a0aed4ec 592 #define _I2C_IEN_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
<> 150:02e0a0aed4ec 593 #define _I2C_IEN_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
<> 150:02e0a0aed4ec 594 #define I2C_IEN_RSTART_DEFAULT (_I2C_IEN_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IEN */
<> 150:02e0a0aed4ec 595 #define I2C_IEN_ADDR (0x1UL << 2) /**< Address Interrupt Enable */
<> 150:02e0a0aed4ec 596 #define _I2C_IEN_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */
<> 150:02e0a0aed4ec 597 #define _I2C_IEN_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */
<> 150:02e0a0aed4ec 598 #define _I2C_IEN_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
<> 150:02e0a0aed4ec 599 #define I2C_IEN_ADDR_DEFAULT (_I2C_IEN_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IEN */
<> 150:02e0a0aed4ec 600 #define I2C_IEN_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Enable */
<> 150:02e0a0aed4ec 601 #define _I2C_IEN_TXC_SHIFT 3 /**< Shift value for I2C_TXC */
<> 150:02e0a0aed4ec 602 #define _I2C_IEN_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */
<> 150:02e0a0aed4ec 603 #define _I2C_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
<> 150:02e0a0aed4ec 604 #define I2C_IEN_TXC_DEFAULT (_I2C_IEN_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IEN */
<> 150:02e0a0aed4ec 605 #define I2C_IEN_TXBL (0x1UL << 4) /**< Transmit Buffer level Interrupt Enable */
<> 150:02e0a0aed4ec 606 #define _I2C_IEN_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */
<> 150:02e0a0aed4ec 607 #define _I2C_IEN_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */
<> 150:02e0a0aed4ec 608 #define _I2C_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
<> 150:02e0a0aed4ec 609 #define I2C_IEN_TXBL_DEFAULT (_I2C_IEN_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IEN */
<> 150:02e0a0aed4ec 610 #define I2C_IEN_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Enable */
<> 150:02e0a0aed4ec 611 #define _I2C_IEN_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */
<> 150:02e0a0aed4ec 612 #define _I2C_IEN_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */
<> 150:02e0a0aed4ec 613 #define _I2C_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
<> 150:02e0a0aed4ec 614 #define I2C_IEN_RXDATAV_DEFAULT (_I2C_IEN_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IEN */
<> 150:02e0a0aed4ec 615 #define I2C_IEN_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Enable */
<> 150:02e0a0aed4ec 616 #define _I2C_IEN_ACK_SHIFT 6 /**< Shift value for I2C_ACK */
<> 150:02e0a0aed4ec 617 #define _I2C_IEN_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */
<> 150:02e0a0aed4ec 618 #define _I2C_IEN_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
<> 150:02e0a0aed4ec 619 #define I2C_IEN_ACK_DEFAULT (_I2C_IEN_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IEN */
<> 150:02e0a0aed4ec 620 #define I2C_IEN_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Enable */
<> 150:02e0a0aed4ec 621 #define _I2C_IEN_NACK_SHIFT 7 /**< Shift value for I2C_NACK */
<> 150:02e0a0aed4ec 622 #define _I2C_IEN_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */
<> 150:02e0a0aed4ec 623 #define _I2C_IEN_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
<> 150:02e0a0aed4ec 624 #define I2C_IEN_NACK_DEFAULT (_I2C_IEN_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IEN */
<> 150:02e0a0aed4ec 625 #define I2C_IEN_MSTOP (0x1UL << 8) /**< MSTOP Interrupt Enable */
<> 150:02e0a0aed4ec 626 #define _I2C_IEN_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */
<> 150:02e0a0aed4ec 627 #define _I2C_IEN_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */
<> 150:02e0a0aed4ec 628 #define _I2C_IEN_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
<> 150:02e0a0aed4ec 629 #define I2C_IEN_MSTOP_DEFAULT (_I2C_IEN_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IEN */
<> 150:02e0a0aed4ec 630 #define I2C_IEN_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Enable */
<> 150:02e0a0aed4ec 631 #define _I2C_IEN_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */
<> 150:02e0a0aed4ec 632 #define _I2C_IEN_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */
<> 150:02e0a0aed4ec 633 #define _I2C_IEN_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
<> 150:02e0a0aed4ec 634 #define I2C_IEN_ARBLOST_DEFAULT (_I2C_IEN_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IEN */
<> 150:02e0a0aed4ec 635 #define I2C_IEN_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Enable */
<> 150:02e0a0aed4ec 636 #define _I2C_IEN_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */
<> 150:02e0a0aed4ec 637 #define _I2C_IEN_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */
<> 150:02e0a0aed4ec 638 #define _I2C_IEN_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
<> 150:02e0a0aed4ec 639 #define I2C_IEN_BUSERR_DEFAULT (_I2C_IEN_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IEN */
<> 150:02e0a0aed4ec 640 #define I2C_IEN_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Enable */
<> 150:02e0a0aed4ec 641 #define _I2C_IEN_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */
<> 150:02e0a0aed4ec 642 #define _I2C_IEN_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */
<> 150:02e0a0aed4ec 643 #define _I2C_IEN_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
<> 150:02e0a0aed4ec 644 #define I2C_IEN_BUSHOLD_DEFAULT (_I2C_IEN_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IEN */
<> 150:02e0a0aed4ec 645 #define I2C_IEN_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Enable */
<> 150:02e0a0aed4ec 646 #define _I2C_IEN_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */
<> 150:02e0a0aed4ec 647 #define _I2C_IEN_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */
<> 150:02e0a0aed4ec 648 #define _I2C_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
<> 150:02e0a0aed4ec 649 #define I2C_IEN_TXOF_DEFAULT (_I2C_IEN_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IEN */
<> 150:02e0a0aed4ec 650 #define I2C_IEN_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Enable */
<> 150:02e0a0aed4ec 651 #define _I2C_IEN_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */
<> 150:02e0a0aed4ec 652 #define _I2C_IEN_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */
<> 150:02e0a0aed4ec 653 #define _I2C_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
<> 150:02e0a0aed4ec 654 #define I2C_IEN_RXUF_DEFAULT (_I2C_IEN_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IEN */
<> 150:02e0a0aed4ec 655 #define I2C_IEN_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Enable */
<> 150:02e0a0aed4ec 656 #define _I2C_IEN_BITO_SHIFT 14 /**< Shift value for I2C_BITO */
<> 150:02e0a0aed4ec 657 #define _I2C_IEN_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */
<> 150:02e0a0aed4ec 658 #define _I2C_IEN_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
<> 150:02e0a0aed4ec 659 #define I2C_IEN_BITO_DEFAULT (_I2C_IEN_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IEN */
<> 150:02e0a0aed4ec 660 #define I2C_IEN_CLTO (0x1UL << 15) /**< Clock Low Interrupt Enable */
<> 150:02e0a0aed4ec 661 #define _I2C_IEN_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */
<> 150:02e0a0aed4ec 662 #define _I2C_IEN_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
<> 150:02e0a0aed4ec 663 #define _I2C_IEN_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
<> 150:02e0a0aed4ec 664 #define I2C_IEN_CLTO_DEFAULT (_I2C_IEN_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IEN */
<> 150:02e0a0aed4ec 665 #define I2C_IEN_SSTOP (0x1UL << 16) /**< SSTOP Interrupt Enable */
<> 150:02e0a0aed4ec 666 #define _I2C_IEN_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
<> 150:02e0a0aed4ec 667 #define _I2C_IEN_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
<> 150:02e0a0aed4ec 668 #define _I2C_IEN_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
<> 150:02e0a0aed4ec 669 #define I2C_IEN_SSTOP_DEFAULT (_I2C_IEN_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IEN */
<> 150:02e0a0aed4ec 670
<> 150:02e0a0aed4ec 671 /* Bit fields for I2C ROUTE */
<> 150:02e0a0aed4ec 672 #define _I2C_ROUTE_RESETVALUE 0x00000000UL /**< Default value for I2C_ROUTE */
<> 150:02e0a0aed4ec 673 #define _I2C_ROUTE_MASK 0x00000703UL /**< Mask for I2C_ROUTE */
<> 150:02e0a0aed4ec 674 #define I2C_ROUTE_SDAPEN (0x1UL << 0) /**< SDA Pin Enable */
<> 150:02e0a0aed4ec 675 #define _I2C_ROUTE_SDAPEN_SHIFT 0 /**< Shift value for I2C_SDAPEN */
<> 150:02e0a0aed4ec 676 #define _I2C_ROUTE_SDAPEN_MASK 0x1UL /**< Bit mask for I2C_SDAPEN */
<> 150:02e0a0aed4ec 677 #define _I2C_ROUTE_SDAPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTE */
<> 150:02e0a0aed4ec 678 #define I2C_ROUTE_SDAPEN_DEFAULT (_I2C_ROUTE_SDAPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_ROUTE */
<> 150:02e0a0aed4ec 679 #define I2C_ROUTE_SCLPEN (0x1UL << 1) /**< SCL Pin Enable */
<> 150:02e0a0aed4ec 680 #define _I2C_ROUTE_SCLPEN_SHIFT 1 /**< Shift value for I2C_SCLPEN */
<> 150:02e0a0aed4ec 681 #define _I2C_ROUTE_SCLPEN_MASK 0x2UL /**< Bit mask for I2C_SCLPEN */
<> 150:02e0a0aed4ec 682 #define _I2C_ROUTE_SCLPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTE */
<> 150:02e0a0aed4ec 683 #define I2C_ROUTE_SCLPEN_DEFAULT (_I2C_ROUTE_SCLPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_ROUTE */
<> 150:02e0a0aed4ec 684 #define _I2C_ROUTE_LOCATION_SHIFT 8 /**< Shift value for I2C_LOCATION */
<> 150:02e0a0aed4ec 685 #define _I2C_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for I2C_LOCATION */
<> 150:02e0a0aed4ec 686 #define _I2C_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for I2C_ROUTE */
<> 150:02e0a0aed4ec 687 #define _I2C_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTE */
<> 150:02e0a0aed4ec 688 #define _I2C_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for I2C_ROUTE */
<> 150:02e0a0aed4ec 689 #define _I2C_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for I2C_ROUTE */
<> 150:02e0a0aed4ec 690 #define _I2C_ROUTE_LOCATION_LOC3 0x00000003UL /**< Mode LOC3 for I2C_ROUTE */
<> 150:02e0a0aed4ec 691 #define _I2C_ROUTE_LOCATION_LOC4 0x00000004UL /**< Mode LOC4 for I2C_ROUTE */
<> 150:02e0a0aed4ec 692 #define _I2C_ROUTE_LOCATION_LOC5 0x00000005UL /**< Mode LOC5 for I2C_ROUTE */
<> 150:02e0a0aed4ec 693 #define _I2C_ROUTE_LOCATION_LOC6 0x00000006UL /**< Mode LOC6 for I2C_ROUTE */
<> 150:02e0a0aed4ec 694 #define I2C_ROUTE_LOCATION_LOC0 (_I2C_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for I2C_ROUTE */
<> 150:02e0a0aed4ec 695 #define I2C_ROUTE_LOCATION_DEFAULT (_I2C_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_ROUTE */
<> 150:02e0a0aed4ec 696 #define I2C_ROUTE_LOCATION_LOC1 (_I2C_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for I2C_ROUTE */
<> 150:02e0a0aed4ec 697 #define I2C_ROUTE_LOCATION_LOC2 (_I2C_ROUTE_LOCATION_LOC2 << 8) /**< Shifted mode LOC2 for I2C_ROUTE */
<> 150:02e0a0aed4ec 698 #define I2C_ROUTE_LOCATION_LOC3 (_I2C_ROUTE_LOCATION_LOC3 << 8) /**< Shifted mode LOC3 for I2C_ROUTE */
<> 150:02e0a0aed4ec 699 #define I2C_ROUTE_LOCATION_LOC4 (_I2C_ROUTE_LOCATION_LOC4 << 8) /**< Shifted mode LOC4 for I2C_ROUTE */
<> 150:02e0a0aed4ec 700 #define I2C_ROUTE_LOCATION_LOC5 (_I2C_ROUTE_LOCATION_LOC5 << 8) /**< Shifted mode LOC5 for I2C_ROUTE */
<> 150:02e0a0aed4ec 701 #define I2C_ROUTE_LOCATION_LOC6 (_I2C_ROUTE_LOCATION_LOC6 << 8) /**< Shifted mode LOC6 for I2C_ROUTE */
<> 150:02e0a0aed4ec 702
<> 150:02e0a0aed4ec 703 /** @} End of group EFM32WG_I2C */
<> 150:02e0a0aed4ec 704 /** @} End of group Parts */
<> 150:02e0a0aed4ec 705