Fawwaz Nadzmy
mbed library sources. Supersedes mbed-src.
Fork of
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by 
mbed official
targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_gpio.h@153:9398a535854b, 2016-12-22 (annotated)
- Committer:
- fwndz
- Date:
- Thu Dec 22 05:12:40 2016 +0000
- Revision:
- 153:9398a535854b
- Parent:
- 150:02e0a0aed4ec
device target maximize
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| <> | 150:02e0a0aed4ec | 1 | /**************************************************************************//** |
| <> | 150:02e0a0aed4ec | 2 | * @file efm32wg_gpio.h |
| <> | 150:02e0a0aed4ec | 3 | * @brief EFM32WG_GPIO register and bit field definitions |
| <> | 150:02e0a0aed4ec | 4 | * @version 5.0.0 |
| <> | 150:02e0a0aed4ec | 5 | ****************************************************************************** |
| <> | 150:02e0a0aed4ec | 6 | * @section License |
| <> | 150:02e0a0aed4ec | 7 | * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b> |
| <> | 150:02e0a0aed4ec | 8 | ****************************************************************************** |
| <> | 150:02e0a0aed4ec | 9 | * |
| <> | 150:02e0a0aed4ec | 10 | * Permission is granted to anyone to use this software for any purpose, |
| <> | 150:02e0a0aed4ec | 11 | * including commercial applications, and to alter it and redistribute it |
| <> | 150:02e0a0aed4ec | 12 | * freely, subject to the following restrictions: |
| <> | 150:02e0a0aed4ec | 13 | * |
| <> | 150:02e0a0aed4ec | 14 | * 1. The origin of this software must not be misrepresented; you must not |
| <> | 150:02e0a0aed4ec | 15 | * claim that you wrote the original software.@n |
| <> | 150:02e0a0aed4ec | 16 | * 2. Altered source versions must be plainly marked as such, and must not be |
| <> | 150:02e0a0aed4ec | 17 | * misrepresented as being the original software.@n |
| <> | 150:02e0a0aed4ec | 18 | * 3. This notice may not be removed or altered from any source distribution. |
| <> | 150:02e0a0aed4ec | 19 | * |
| <> | 150:02e0a0aed4ec | 20 | * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. |
| <> | 150:02e0a0aed4ec | 21 | * has no obligation to support this Software. Silicon Laboratories, Inc. is |
| <> | 150:02e0a0aed4ec | 22 | * providing the Software "AS IS", with no express or implied warranties of any |
| <> | 150:02e0a0aed4ec | 23 | * kind, including, but not limited to, any implied warranties of |
| <> | 150:02e0a0aed4ec | 24 | * merchantability or fitness for any particular purpose or warranties against |
| <> | 150:02e0a0aed4ec | 25 | * infringement of any proprietary rights of a third party. |
| <> | 150:02e0a0aed4ec | 26 | * |
| <> | 150:02e0a0aed4ec | 27 | * Silicon Laboratories, Inc. will not be liable for any consequential, |
| <> | 150:02e0a0aed4ec | 28 | * incidental, or special damages, or any other relief, or for any claim by |
| <> | 150:02e0a0aed4ec | 29 | * any third party, arising from your use of this Software. |
| <> | 150:02e0a0aed4ec | 30 | * |
| <> | 150:02e0a0aed4ec | 31 | *****************************************************************************/ |
| <> | 150:02e0a0aed4ec | 32 | /**************************************************************************//** |
| <> | 150:02e0a0aed4ec | 33 | * @addtogroup Parts |
| <> | 150:02e0a0aed4ec | 34 | * @{ |
| <> | 150:02e0a0aed4ec | 35 | ******************************************************************************/ |
| <> | 150:02e0a0aed4ec | 36 | /**************************************************************************//** |
| <> | 150:02e0a0aed4ec | 37 | * @defgroup EFM32WG_GPIO |
| <> | 150:02e0a0aed4ec | 38 | * @{ |
| <> | 150:02e0a0aed4ec | 39 | * @brief EFM32WG_GPIO Register Declaration |
| <> | 150:02e0a0aed4ec | 40 | *****************************************************************************/ |
| <> | 150:02e0a0aed4ec | 41 | typedef struct |
| <> | 150:02e0a0aed4ec | 42 | { |
| <> | 150:02e0a0aed4ec | 43 | GPIO_P_TypeDef P[6]; /**< Port configuration bits */ |
| <> | 150:02e0a0aed4ec | 44 | |
| <> | 150:02e0a0aed4ec | 45 | uint32_t RESERVED0[10]; /**< Reserved for future use **/ |
| <> | 150:02e0a0aed4ec | 46 | __IOM uint32_t EXTIPSELL; /**< External Interrupt Port Select Low Register */ |
| <> | 150:02e0a0aed4ec | 47 | __IOM uint32_t EXTIPSELH; /**< External Interrupt Port Select High Register */ |
| <> | 150:02e0a0aed4ec | 48 | __IOM uint32_t EXTIRISE; /**< External Interrupt Rising Edge Trigger Register */ |
| <> | 150:02e0a0aed4ec | 49 | __IOM uint32_t EXTIFALL; /**< External Interrupt Falling Edge Trigger Register */ |
| <> | 150:02e0a0aed4ec | 50 | __IOM uint32_t IEN; /**< Interrupt Enable Register */ |
| <> | 150:02e0a0aed4ec | 51 | __IM uint32_t IF; /**< Interrupt Flag Register */ |
| <> | 150:02e0a0aed4ec | 52 | __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ |
| <> | 150:02e0a0aed4ec | 53 | __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ |
| <> | 150:02e0a0aed4ec | 54 | |
| <> | 150:02e0a0aed4ec | 55 | __IOM uint32_t ROUTE; /**< I/O Routing Register */ |
| <> | 150:02e0a0aed4ec | 56 | __IOM uint32_t INSENSE; /**< Input Sense Register */ |
| <> | 150:02e0a0aed4ec | 57 | __IOM uint32_t LOCK; /**< Configuration Lock Register */ |
| <> | 150:02e0a0aed4ec | 58 | __IOM uint32_t CTRL; /**< GPIO Control Register */ |
| <> | 150:02e0a0aed4ec | 59 | __IOM uint32_t CMD; /**< GPIO Command Register */ |
| <> | 150:02e0a0aed4ec | 60 | __IOM uint32_t EM4WUEN; /**< EM4 Wake-up Enable Register */ |
| <> | 150:02e0a0aed4ec | 61 | __IOM uint32_t EM4WUPOL; /**< EM4 Wake-up Polarity Register */ |
| <> | 150:02e0a0aed4ec | 62 | __IM uint32_t EM4WUCAUSE; /**< EM4 Wake-up Cause Register */ |
| <> | 150:02e0a0aed4ec | 63 | } GPIO_TypeDef; /** @} */ |
| <> | 150:02e0a0aed4ec | 64 | |
| <> | 150:02e0a0aed4ec | 65 | /**************************************************************************//** |
| <> | 150:02e0a0aed4ec | 66 | * @defgroup EFM32WG_GPIO_BitFields |
| <> | 150:02e0a0aed4ec | 67 | * @{ |
| <> | 150:02e0a0aed4ec | 68 | *****************************************************************************/ |
| <> | 150:02e0a0aed4ec | 69 | |
| <> | 150:02e0a0aed4ec | 70 | /* Bit fields for GPIO P_CTRL */ |
| <> | 150:02e0a0aed4ec | 71 | #define _GPIO_P_CTRL_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_CTRL */ |
| <> | 150:02e0a0aed4ec | 72 | #define _GPIO_P_CTRL_MASK 0x00000003UL /**< Mask for GPIO_P_CTRL */ |
| <> | 150:02e0a0aed4ec | 73 | #define _GPIO_P_CTRL_DRIVEMODE_SHIFT 0 /**< Shift value for GPIO_DRIVEMODE */ |
| <> | 150:02e0a0aed4ec | 74 | #define _GPIO_P_CTRL_DRIVEMODE_MASK 0x3UL /**< Bit mask for GPIO_DRIVEMODE */ |
| <> | 150:02e0a0aed4ec | 75 | #define _GPIO_P_CTRL_DRIVEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */ |
| <> | 150:02e0a0aed4ec | 76 | #define _GPIO_P_CTRL_DRIVEMODE_STANDARD 0x00000000UL /**< Mode STANDARD for GPIO_P_CTRL */ |
| <> | 150:02e0a0aed4ec | 77 | #define _GPIO_P_CTRL_DRIVEMODE_LOWEST 0x00000001UL /**< Mode LOWEST for GPIO_P_CTRL */ |
| <> | 150:02e0a0aed4ec | 78 | #define _GPIO_P_CTRL_DRIVEMODE_HIGH 0x00000002UL /**< Mode HIGH for GPIO_P_CTRL */ |
| <> | 150:02e0a0aed4ec | 79 | #define _GPIO_P_CTRL_DRIVEMODE_LOW 0x00000003UL /**< Mode LOW for GPIO_P_CTRL */ |
| <> | 150:02e0a0aed4ec | 80 | #define GPIO_P_CTRL_DRIVEMODE_DEFAULT (_GPIO_P_CTRL_DRIVEMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ |
| <> | 150:02e0a0aed4ec | 81 | #define GPIO_P_CTRL_DRIVEMODE_STANDARD (_GPIO_P_CTRL_DRIVEMODE_STANDARD << 0) /**< Shifted mode STANDARD for GPIO_P_CTRL */ |
| <> | 150:02e0a0aed4ec | 82 | #define GPIO_P_CTRL_DRIVEMODE_LOWEST (_GPIO_P_CTRL_DRIVEMODE_LOWEST << 0) /**< Shifted mode LOWEST for GPIO_P_CTRL */ |
| <> | 150:02e0a0aed4ec | 83 | #define GPIO_P_CTRL_DRIVEMODE_HIGH (_GPIO_P_CTRL_DRIVEMODE_HIGH << 0) /**< Shifted mode HIGH for GPIO_P_CTRL */ |
| <> | 150:02e0a0aed4ec | 84 | #define GPIO_P_CTRL_DRIVEMODE_LOW (_GPIO_P_CTRL_DRIVEMODE_LOW << 0) /**< Shifted mode LOW for GPIO_P_CTRL */ |
| <> | 150:02e0a0aed4ec | 85 | |
| <> | 150:02e0a0aed4ec | 86 | /* Bit fields for GPIO P_MODEL */ |
| <> | 150:02e0a0aed4ec | 87 | #define _GPIO_P_MODEL_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 88 | #define _GPIO_P_MODEL_MASK 0xFFFFFFFFUL /**< Mask for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 89 | #define _GPIO_P_MODEL_MODE0_SHIFT 0 /**< Shift value for GPIO_MODE0 */ |
| <> | 150:02e0a0aed4ec | 90 | #define _GPIO_P_MODEL_MODE0_MASK 0xFUL /**< Bit mask for GPIO_MODE0 */ |
| <> | 150:02e0a0aed4ec | 91 | #define _GPIO_P_MODEL_MODE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 92 | #define _GPIO_P_MODEL_MODE0_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 93 | #define _GPIO_P_MODEL_MODE0_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 94 | #define _GPIO_P_MODEL_MODE0_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 95 | #define _GPIO_P_MODEL_MODE0_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 96 | #define _GPIO_P_MODEL_MODE0_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 97 | #define _GPIO_P_MODEL_MODE0_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 98 | #define _GPIO_P_MODEL_MODE0_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 99 | #define _GPIO_P_MODEL_MODE0_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 100 | #define _GPIO_P_MODEL_MODE0_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 101 | #define _GPIO_P_MODEL_MODE0_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 102 | #define _GPIO_P_MODEL_MODE0_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 103 | #define _GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 104 | #define _GPIO_P_MODEL_MODE0_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 105 | #define _GPIO_P_MODEL_MODE0_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 106 | #define _GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 107 | #define _GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 108 | #define GPIO_P_MODEL_MODE0_DEFAULT (_GPIO_P_MODEL_MODE0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 109 | #define GPIO_P_MODEL_MODE0_DISABLED (_GPIO_P_MODEL_MODE0_DISABLED << 0) /**< Shifted mode DISABLED for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 110 | #define GPIO_P_MODEL_MODE0_INPUT (_GPIO_P_MODEL_MODE0_INPUT << 0) /**< Shifted mode INPUT for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 111 | #define GPIO_P_MODEL_MODE0_INPUTPULL (_GPIO_P_MODEL_MODE0_INPUTPULL << 0) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 112 | #define GPIO_P_MODEL_MODE0_INPUTPULLFILTER (_GPIO_P_MODEL_MODE0_INPUTPULLFILTER << 0) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 113 | #define GPIO_P_MODEL_MODE0_PUSHPULL (_GPIO_P_MODEL_MODE0_PUSHPULL << 0) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 114 | #define GPIO_P_MODEL_MODE0_PUSHPULLDRIVE (_GPIO_P_MODEL_MODE0_PUSHPULLDRIVE << 0) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 115 | #define GPIO_P_MODEL_MODE0_WIREDOR (_GPIO_P_MODEL_MODE0_WIREDOR << 0) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 116 | #define GPIO_P_MODEL_MODE0_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE0_WIREDORPULLDOWN << 0) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 117 | #define GPIO_P_MODEL_MODE0_WIREDAND (_GPIO_P_MODEL_MODE0_WIREDAND << 0) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 118 | #define GPIO_P_MODEL_MODE0_WIREDANDFILTER (_GPIO_P_MODEL_MODE0_WIREDANDFILTER << 0) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 119 | #define GPIO_P_MODEL_MODE0_WIREDANDPULLUP (_GPIO_P_MODEL_MODE0_WIREDANDPULLUP << 0) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 120 | #define GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER << 0) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 121 | #define GPIO_P_MODEL_MODE0_WIREDANDDRIVE (_GPIO_P_MODEL_MODE0_WIREDANDDRIVE << 0) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 122 | #define GPIO_P_MODEL_MODE0_WIREDANDDRIVEFILTER (_GPIO_P_MODEL_MODE0_WIREDANDDRIVEFILTER << 0) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 123 | #define GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUP (_GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUP << 0) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 124 | #define GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUPFILTER << 0) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 125 | #define _GPIO_P_MODEL_MODE1_SHIFT 4 /**< Shift value for GPIO_MODE1 */ |
| <> | 150:02e0a0aed4ec | 126 | #define _GPIO_P_MODEL_MODE1_MASK 0xF0UL /**< Bit mask for GPIO_MODE1 */ |
| <> | 150:02e0a0aed4ec | 127 | #define _GPIO_P_MODEL_MODE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 128 | #define _GPIO_P_MODEL_MODE1_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 129 | #define _GPIO_P_MODEL_MODE1_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 130 | #define _GPIO_P_MODEL_MODE1_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 131 | #define _GPIO_P_MODEL_MODE1_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 132 | #define _GPIO_P_MODEL_MODE1_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 133 | #define _GPIO_P_MODEL_MODE1_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 134 | #define _GPIO_P_MODEL_MODE1_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 135 | #define _GPIO_P_MODEL_MODE1_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 136 | #define _GPIO_P_MODEL_MODE1_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 137 | #define _GPIO_P_MODEL_MODE1_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 138 | #define _GPIO_P_MODEL_MODE1_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 139 | #define _GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 140 | #define _GPIO_P_MODEL_MODE1_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 141 | #define _GPIO_P_MODEL_MODE1_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 142 | #define _GPIO_P_MODEL_MODE1_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 143 | #define _GPIO_P_MODEL_MODE1_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 144 | #define GPIO_P_MODEL_MODE1_DEFAULT (_GPIO_P_MODEL_MODE1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 145 | #define GPIO_P_MODEL_MODE1_DISABLED (_GPIO_P_MODEL_MODE1_DISABLED << 4) /**< Shifted mode DISABLED for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 146 | #define GPIO_P_MODEL_MODE1_INPUT (_GPIO_P_MODEL_MODE1_INPUT << 4) /**< Shifted mode INPUT for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 147 | #define GPIO_P_MODEL_MODE1_INPUTPULL (_GPIO_P_MODEL_MODE1_INPUTPULL << 4) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 148 | #define GPIO_P_MODEL_MODE1_INPUTPULLFILTER (_GPIO_P_MODEL_MODE1_INPUTPULLFILTER << 4) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 149 | #define GPIO_P_MODEL_MODE1_PUSHPULL (_GPIO_P_MODEL_MODE1_PUSHPULL << 4) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 150 | #define GPIO_P_MODEL_MODE1_PUSHPULLDRIVE (_GPIO_P_MODEL_MODE1_PUSHPULLDRIVE << 4) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 151 | #define GPIO_P_MODEL_MODE1_WIREDOR (_GPIO_P_MODEL_MODE1_WIREDOR << 4) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 152 | #define GPIO_P_MODEL_MODE1_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE1_WIREDORPULLDOWN << 4) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 153 | #define GPIO_P_MODEL_MODE1_WIREDAND (_GPIO_P_MODEL_MODE1_WIREDAND << 4) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 154 | #define GPIO_P_MODEL_MODE1_WIREDANDFILTER (_GPIO_P_MODEL_MODE1_WIREDANDFILTER << 4) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 155 | #define GPIO_P_MODEL_MODE1_WIREDANDPULLUP (_GPIO_P_MODEL_MODE1_WIREDANDPULLUP << 4) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 156 | #define GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER << 4) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 157 | #define GPIO_P_MODEL_MODE1_WIREDANDDRIVE (_GPIO_P_MODEL_MODE1_WIREDANDDRIVE << 4) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 158 | #define GPIO_P_MODEL_MODE1_WIREDANDDRIVEFILTER (_GPIO_P_MODEL_MODE1_WIREDANDDRIVEFILTER << 4) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 159 | #define GPIO_P_MODEL_MODE1_WIREDANDDRIVEPULLUP (_GPIO_P_MODEL_MODE1_WIREDANDDRIVEPULLUP << 4) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 160 | #define GPIO_P_MODEL_MODE1_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEL_MODE1_WIREDANDDRIVEPULLUPFILTER << 4) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 161 | #define _GPIO_P_MODEL_MODE2_SHIFT 8 /**< Shift value for GPIO_MODE2 */ |
| <> | 150:02e0a0aed4ec | 162 | #define _GPIO_P_MODEL_MODE2_MASK 0xF00UL /**< Bit mask for GPIO_MODE2 */ |
| <> | 150:02e0a0aed4ec | 163 | #define _GPIO_P_MODEL_MODE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 164 | #define _GPIO_P_MODEL_MODE2_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 165 | #define _GPIO_P_MODEL_MODE2_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 166 | #define _GPIO_P_MODEL_MODE2_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 167 | #define _GPIO_P_MODEL_MODE2_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 168 | #define _GPIO_P_MODEL_MODE2_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 169 | #define _GPIO_P_MODEL_MODE2_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 170 | #define _GPIO_P_MODEL_MODE2_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 171 | #define _GPIO_P_MODEL_MODE2_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 172 | #define _GPIO_P_MODEL_MODE2_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 173 | #define _GPIO_P_MODEL_MODE2_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 174 | #define _GPIO_P_MODEL_MODE2_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 175 | #define _GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 176 | #define _GPIO_P_MODEL_MODE2_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 177 | #define _GPIO_P_MODEL_MODE2_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 178 | #define _GPIO_P_MODEL_MODE2_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 179 | #define _GPIO_P_MODEL_MODE2_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 180 | #define GPIO_P_MODEL_MODE2_DEFAULT (_GPIO_P_MODEL_MODE2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 181 | #define GPIO_P_MODEL_MODE2_DISABLED (_GPIO_P_MODEL_MODE2_DISABLED << 8) /**< Shifted mode DISABLED for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 182 | #define GPIO_P_MODEL_MODE2_INPUT (_GPIO_P_MODEL_MODE2_INPUT << 8) /**< Shifted mode INPUT for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 183 | #define GPIO_P_MODEL_MODE2_INPUTPULL (_GPIO_P_MODEL_MODE2_INPUTPULL << 8) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 184 | #define GPIO_P_MODEL_MODE2_INPUTPULLFILTER (_GPIO_P_MODEL_MODE2_INPUTPULLFILTER << 8) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 185 | #define GPIO_P_MODEL_MODE2_PUSHPULL (_GPIO_P_MODEL_MODE2_PUSHPULL << 8) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 186 | #define GPIO_P_MODEL_MODE2_PUSHPULLDRIVE (_GPIO_P_MODEL_MODE2_PUSHPULLDRIVE << 8) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 187 | #define GPIO_P_MODEL_MODE2_WIREDOR (_GPIO_P_MODEL_MODE2_WIREDOR << 8) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 188 | #define GPIO_P_MODEL_MODE2_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE2_WIREDORPULLDOWN << 8) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 189 | #define GPIO_P_MODEL_MODE2_WIREDAND (_GPIO_P_MODEL_MODE2_WIREDAND << 8) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 190 | #define GPIO_P_MODEL_MODE2_WIREDANDFILTER (_GPIO_P_MODEL_MODE2_WIREDANDFILTER << 8) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 191 | #define GPIO_P_MODEL_MODE2_WIREDANDPULLUP (_GPIO_P_MODEL_MODE2_WIREDANDPULLUP << 8) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 192 | #define GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER << 8) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 193 | #define GPIO_P_MODEL_MODE2_WIREDANDDRIVE (_GPIO_P_MODEL_MODE2_WIREDANDDRIVE << 8) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 194 | #define GPIO_P_MODEL_MODE2_WIREDANDDRIVEFILTER (_GPIO_P_MODEL_MODE2_WIREDANDDRIVEFILTER << 8) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 195 | #define GPIO_P_MODEL_MODE2_WIREDANDDRIVEPULLUP (_GPIO_P_MODEL_MODE2_WIREDANDDRIVEPULLUP << 8) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 196 | #define GPIO_P_MODEL_MODE2_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEL_MODE2_WIREDANDDRIVEPULLUPFILTER << 8) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 197 | #define _GPIO_P_MODEL_MODE3_SHIFT 12 /**< Shift value for GPIO_MODE3 */ |
| <> | 150:02e0a0aed4ec | 198 | #define _GPIO_P_MODEL_MODE3_MASK 0xF000UL /**< Bit mask for GPIO_MODE3 */ |
| <> | 150:02e0a0aed4ec | 199 | #define _GPIO_P_MODEL_MODE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 200 | #define _GPIO_P_MODEL_MODE3_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 201 | #define _GPIO_P_MODEL_MODE3_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 202 | #define _GPIO_P_MODEL_MODE3_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 203 | #define _GPIO_P_MODEL_MODE3_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 204 | #define _GPIO_P_MODEL_MODE3_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 205 | #define _GPIO_P_MODEL_MODE3_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 206 | #define _GPIO_P_MODEL_MODE3_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 207 | #define _GPIO_P_MODEL_MODE3_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 208 | #define _GPIO_P_MODEL_MODE3_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 209 | #define _GPIO_P_MODEL_MODE3_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 210 | #define _GPIO_P_MODEL_MODE3_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 211 | #define _GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 212 | #define _GPIO_P_MODEL_MODE3_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 213 | #define _GPIO_P_MODEL_MODE3_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 214 | #define _GPIO_P_MODEL_MODE3_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 215 | #define _GPIO_P_MODEL_MODE3_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 216 | #define GPIO_P_MODEL_MODE3_DEFAULT (_GPIO_P_MODEL_MODE3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 217 | #define GPIO_P_MODEL_MODE3_DISABLED (_GPIO_P_MODEL_MODE3_DISABLED << 12) /**< Shifted mode DISABLED for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 218 | #define GPIO_P_MODEL_MODE3_INPUT (_GPIO_P_MODEL_MODE3_INPUT << 12) /**< Shifted mode INPUT for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 219 | #define GPIO_P_MODEL_MODE3_INPUTPULL (_GPIO_P_MODEL_MODE3_INPUTPULL << 12) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 220 | #define GPIO_P_MODEL_MODE3_INPUTPULLFILTER (_GPIO_P_MODEL_MODE3_INPUTPULLFILTER << 12) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 221 | #define GPIO_P_MODEL_MODE3_PUSHPULL (_GPIO_P_MODEL_MODE3_PUSHPULL << 12) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 222 | #define GPIO_P_MODEL_MODE3_PUSHPULLDRIVE (_GPIO_P_MODEL_MODE3_PUSHPULLDRIVE << 12) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 223 | #define GPIO_P_MODEL_MODE3_WIREDOR (_GPIO_P_MODEL_MODE3_WIREDOR << 12) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 224 | #define GPIO_P_MODEL_MODE3_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE3_WIREDORPULLDOWN << 12) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 225 | #define GPIO_P_MODEL_MODE3_WIREDAND (_GPIO_P_MODEL_MODE3_WIREDAND << 12) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 226 | #define GPIO_P_MODEL_MODE3_WIREDANDFILTER (_GPIO_P_MODEL_MODE3_WIREDANDFILTER << 12) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 227 | #define GPIO_P_MODEL_MODE3_WIREDANDPULLUP (_GPIO_P_MODEL_MODE3_WIREDANDPULLUP << 12) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 228 | #define GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER << 12) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 229 | #define GPIO_P_MODEL_MODE3_WIREDANDDRIVE (_GPIO_P_MODEL_MODE3_WIREDANDDRIVE << 12) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 230 | #define GPIO_P_MODEL_MODE3_WIREDANDDRIVEFILTER (_GPIO_P_MODEL_MODE3_WIREDANDDRIVEFILTER << 12) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 231 | #define GPIO_P_MODEL_MODE3_WIREDANDDRIVEPULLUP (_GPIO_P_MODEL_MODE3_WIREDANDDRIVEPULLUP << 12) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 232 | #define GPIO_P_MODEL_MODE3_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEL_MODE3_WIREDANDDRIVEPULLUPFILTER << 12) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 233 | #define _GPIO_P_MODEL_MODE4_SHIFT 16 /**< Shift value for GPIO_MODE4 */ |
| <> | 150:02e0a0aed4ec | 234 | #define _GPIO_P_MODEL_MODE4_MASK 0xF0000UL /**< Bit mask for GPIO_MODE4 */ |
| <> | 150:02e0a0aed4ec | 235 | #define _GPIO_P_MODEL_MODE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 236 | #define _GPIO_P_MODEL_MODE4_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 237 | #define _GPIO_P_MODEL_MODE4_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 238 | #define _GPIO_P_MODEL_MODE4_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 239 | #define _GPIO_P_MODEL_MODE4_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 240 | #define _GPIO_P_MODEL_MODE4_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 241 | #define _GPIO_P_MODEL_MODE4_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 242 | #define _GPIO_P_MODEL_MODE4_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 243 | #define _GPIO_P_MODEL_MODE4_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 244 | #define _GPIO_P_MODEL_MODE4_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 245 | #define _GPIO_P_MODEL_MODE4_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 246 | #define _GPIO_P_MODEL_MODE4_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 247 | #define _GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 248 | #define _GPIO_P_MODEL_MODE4_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 249 | #define _GPIO_P_MODEL_MODE4_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 250 | #define _GPIO_P_MODEL_MODE4_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 251 | #define _GPIO_P_MODEL_MODE4_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 252 | #define GPIO_P_MODEL_MODE4_DEFAULT (_GPIO_P_MODEL_MODE4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 253 | #define GPIO_P_MODEL_MODE4_DISABLED (_GPIO_P_MODEL_MODE4_DISABLED << 16) /**< Shifted mode DISABLED for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 254 | #define GPIO_P_MODEL_MODE4_INPUT (_GPIO_P_MODEL_MODE4_INPUT << 16) /**< Shifted mode INPUT for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 255 | #define GPIO_P_MODEL_MODE4_INPUTPULL (_GPIO_P_MODEL_MODE4_INPUTPULL << 16) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 256 | #define GPIO_P_MODEL_MODE4_INPUTPULLFILTER (_GPIO_P_MODEL_MODE4_INPUTPULLFILTER << 16) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 257 | #define GPIO_P_MODEL_MODE4_PUSHPULL (_GPIO_P_MODEL_MODE4_PUSHPULL << 16) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 258 | #define GPIO_P_MODEL_MODE4_PUSHPULLDRIVE (_GPIO_P_MODEL_MODE4_PUSHPULLDRIVE << 16) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 259 | #define GPIO_P_MODEL_MODE4_WIREDOR (_GPIO_P_MODEL_MODE4_WIREDOR << 16) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 260 | #define GPIO_P_MODEL_MODE4_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE4_WIREDORPULLDOWN << 16) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 261 | #define GPIO_P_MODEL_MODE4_WIREDAND (_GPIO_P_MODEL_MODE4_WIREDAND << 16) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 262 | #define GPIO_P_MODEL_MODE4_WIREDANDFILTER (_GPIO_P_MODEL_MODE4_WIREDANDFILTER << 16) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 263 | #define GPIO_P_MODEL_MODE4_WIREDANDPULLUP (_GPIO_P_MODEL_MODE4_WIREDANDPULLUP << 16) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 264 | #define GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER << 16) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 265 | #define GPIO_P_MODEL_MODE4_WIREDANDDRIVE (_GPIO_P_MODEL_MODE4_WIREDANDDRIVE << 16) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 266 | #define GPIO_P_MODEL_MODE4_WIREDANDDRIVEFILTER (_GPIO_P_MODEL_MODE4_WIREDANDDRIVEFILTER << 16) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 267 | #define GPIO_P_MODEL_MODE4_WIREDANDDRIVEPULLUP (_GPIO_P_MODEL_MODE4_WIREDANDDRIVEPULLUP << 16) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 268 | #define GPIO_P_MODEL_MODE4_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEL_MODE4_WIREDANDDRIVEPULLUPFILTER << 16) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 269 | #define _GPIO_P_MODEL_MODE5_SHIFT 20 /**< Shift value for GPIO_MODE5 */ |
| <> | 150:02e0a0aed4ec | 270 | #define _GPIO_P_MODEL_MODE5_MASK 0xF00000UL /**< Bit mask for GPIO_MODE5 */ |
| <> | 150:02e0a0aed4ec | 271 | #define _GPIO_P_MODEL_MODE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 272 | #define _GPIO_P_MODEL_MODE5_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 273 | #define _GPIO_P_MODEL_MODE5_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 274 | #define _GPIO_P_MODEL_MODE5_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 275 | #define _GPIO_P_MODEL_MODE5_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 276 | #define _GPIO_P_MODEL_MODE5_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 277 | #define _GPIO_P_MODEL_MODE5_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 278 | #define _GPIO_P_MODEL_MODE5_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 279 | #define _GPIO_P_MODEL_MODE5_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 280 | #define _GPIO_P_MODEL_MODE5_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 281 | #define _GPIO_P_MODEL_MODE5_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 282 | #define _GPIO_P_MODEL_MODE5_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 283 | #define _GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 284 | #define _GPIO_P_MODEL_MODE5_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 285 | #define _GPIO_P_MODEL_MODE5_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 286 | #define _GPIO_P_MODEL_MODE5_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 287 | #define _GPIO_P_MODEL_MODE5_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 288 | #define GPIO_P_MODEL_MODE5_DEFAULT (_GPIO_P_MODEL_MODE5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 289 | #define GPIO_P_MODEL_MODE5_DISABLED (_GPIO_P_MODEL_MODE5_DISABLED << 20) /**< Shifted mode DISABLED for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 290 | #define GPIO_P_MODEL_MODE5_INPUT (_GPIO_P_MODEL_MODE5_INPUT << 20) /**< Shifted mode INPUT for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 291 | #define GPIO_P_MODEL_MODE5_INPUTPULL (_GPIO_P_MODEL_MODE5_INPUTPULL << 20) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 292 | #define GPIO_P_MODEL_MODE5_INPUTPULLFILTER (_GPIO_P_MODEL_MODE5_INPUTPULLFILTER << 20) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 293 | #define GPIO_P_MODEL_MODE5_PUSHPULL (_GPIO_P_MODEL_MODE5_PUSHPULL << 20) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 294 | #define GPIO_P_MODEL_MODE5_PUSHPULLDRIVE (_GPIO_P_MODEL_MODE5_PUSHPULLDRIVE << 20) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 295 | #define GPIO_P_MODEL_MODE5_WIREDOR (_GPIO_P_MODEL_MODE5_WIREDOR << 20) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 296 | #define GPIO_P_MODEL_MODE5_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE5_WIREDORPULLDOWN << 20) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 297 | #define GPIO_P_MODEL_MODE5_WIREDAND (_GPIO_P_MODEL_MODE5_WIREDAND << 20) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 298 | #define GPIO_P_MODEL_MODE5_WIREDANDFILTER (_GPIO_P_MODEL_MODE5_WIREDANDFILTER << 20) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 299 | #define GPIO_P_MODEL_MODE5_WIREDANDPULLUP (_GPIO_P_MODEL_MODE5_WIREDANDPULLUP << 20) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 300 | #define GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER << 20) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 301 | #define GPIO_P_MODEL_MODE5_WIREDANDDRIVE (_GPIO_P_MODEL_MODE5_WIREDANDDRIVE << 20) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 302 | #define GPIO_P_MODEL_MODE5_WIREDANDDRIVEFILTER (_GPIO_P_MODEL_MODE5_WIREDANDDRIVEFILTER << 20) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 303 | #define GPIO_P_MODEL_MODE5_WIREDANDDRIVEPULLUP (_GPIO_P_MODEL_MODE5_WIREDANDDRIVEPULLUP << 20) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 304 | #define GPIO_P_MODEL_MODE5_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEL_MODE5_WIREDANDDRIVEPULLUPFILTER << 20) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 305 | #define _GPIO_P_MODEL_MODE6_SHIFT 24 /**< Shift value for GPIO_MODE6 */ |
| <> | 150:02e0a0aed4ec | 306 | #define _GPIO_P_MODEL_MODE6_MASK 0xF000000UL /**< Bit mask for GPIO_MODE6 */ |
| <> | 150:02e0a0aed4ec | 307 | #define _GPIO_P_MODEL_MODE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 308 | #define _GPIO_P_MODEL_MODE6_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 309 | #define _GPIO_P_MODEL_MODE6_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 310 | #define _GPIO_P_MODEL_MODE6_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 311 | #define _GPIO_P_MODEL_MODE6_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 312 | #define _GPIO_P_MODEL_MODE6_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 313 | #define _GPIO_P_MODEL_MODE6_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 314 | #define _GPIO_P_MODEL_MODE6_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 315 | #define _GPIO_P_MODEL_MODE6_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 316 | #define _GPIO_P_MODEL_MODE6_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 317 | #define _GPIO_P_MODEL_MODE6_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 318 | #define _GPIO_P_MODEL_MODE6_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 319 | #define _GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 320 | #define _GPIO_P_MODEL_MODE6_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 321 | #define _GPIO_P_MODEL_MODE6_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 322 | #define _GPIO_P_MODEL_MODE6_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 323 | #define _GPIO_P_MODEL_MODE6_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 324 | #define GPIO_P_MODEL_MODE6_DEFAULT (_GPIO_P_MODEL_MODE6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 325 | #define GPIO_P_MODEL_MODE6_DISABLED (_GPIO_P_MODEL_MODE6_DISABLED << 24) /**< Shifted mode DISABLED for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 326 | #define GPIO_P_MODEL_MODE6_INPUT (_GPIO_P_MODEL_MODE6_INPUT << 24) /**< Shifted mode INPUT for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 327 | #define GPIO_P_MODEL_MODE6_INPUTPULL (_GPIO_P_MODEL_MODE6_INPUTPULL << 24) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 328 | #define GPIO_P_MODEL_MODE6_INPUTPULLFILTER (_GPIO_P_MODEL_MODE6_INPUTPULLFILTER << 24) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 329 | #define GPIO_P_MODEL_MODE6_PUSHPULL (_GPIO_P_MODEL_MODE6_PUSHPULL << 24) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 330 | #define GPIO_P_MODEL_MODE6_PUSHPULLDRIVE (_GPIO_P_MODEL_MODE6_PUSHPULLDRIVE << 24) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 331 | #define GPIO_P_MODEL_MODE6_WIREDOR (_GPIO_P_MODEL_MODE6_WIREDOR << 24) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 332 | #define GPIO_P_MODEL_MODE6_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE6_WIREDORPULLDOWN << 24) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 333 | #define GPIO_P_MODEL_MODE6_WIREDAND (_GPIO_P_MODEL_MODE6_WIREDAND << 24) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 334 | #define GPIO_P_MODEL_MODE6_WIREDANDFILTER (_GPIO_P_MODEL_MODE6_WIREDANDFILTER << 24) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 335 | #define GPIO_P_MODEL_MODE6_WIREDANDPULLUP (_GPIO_P_MODEL_MODE6_WIREDANDPULLUP << 24) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 336 | #define GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER << 24) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 337 | #define GPIO_P_MODEL_MODE6_WIREDANDDRIVE (_GPIO_P_MODEL_MODE6_WIREDANDDRIVE << 24) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 338 | #define GPIO_P_MODEL_MODE6_WIREDANDDRIVEFILTER (_GPIO_P_MODEL_MODE6_WIREDANDDRIVEFILTER << 24) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 339 | #define GPIO_P_MODEL_MODE6_WIREDANDDRIVEPULLUP (_GPIO_P_MODEL_MODE6_WIREDANDDRIVEPULLUP << 24) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 340 | #define GPIO_P_MODEL_MODE6_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEL_MODE6_WIREDANDDRIVEPULLUPFILTER << 24) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 341 | #define _GPIO_P_MODEL_MODE7_SHIFT 28 /**< Shift value for GPIO_MODE7 */ |
| <> | 150:02e0a0aed4ec | 342 | #define _GPIO_P_MODEL_MODE7_MASK 0xF0000000UL /**< Bit mask for GPIO_MODE7 */ |
| <> | 150:02e0a0aed4ec | 343 | #define _GPIO_P_MODEL_MODE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 344 | #define _GPIO_P_MODEL_MODE7_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 345 | #define _GPIO_P_MODEL_MODE7_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 346 | #define _GPIO_P_MODEL_MODE7_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 347 | #define _GPIO_P_MODEL_MODE7_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 348 | #define _GPIO_P_MODEL_MODE7_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 349 | #define _GPIO_P_MODEL_MODE7_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 350 | #define _GPIO_P_MODEL_MODE7_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 351 | #define _GPIO_P_MODEL_MODE7_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 352 | #define _GPIO_P_MODEL_MODE7_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 353 | #define _GPIO_P_MODEL_MODE7_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 354 | #define _GPIO_P_MODEL_MODE7_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 355 | #define _GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 356 | #define _GPIO_P_MODEL_MODE7_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 357 | #define _GPIO_P_MODEL_MODE7_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 358 | #define _GPIO_P_MODEL_MODE7_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 359 | #define _GPIO_P_MODEL_MODE7_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 360 | #define GPIO_P_MODEL_MODE7_DEFAULT (_GPIO_P_MODEL_MODE7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 361 | #define GPIO_P_MODEL_MODE7_DISABLED (_GPIO_P_MODEL_MODE7_DISABLED << 28) /**< Shifted mode DISABLED for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 362 | #define GPIO_P_MODEL_MODE7_INPUT (_GPIO_P_MODEL_MODE7_INPUT << 28) /**< Shifted mode INPUT for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 363 | #define GPIO_P_MODEL_MODE7_INPUTPULL (_GPIO_P_MODEL_MODE7_INPUTPULL << 28) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 364 | #define GPIO_P_MODEL_MODE7_INPUTPULLFILTER (_GPIO_P_MODEL_MODE7_INPUTPULLFILTER << 28) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 365 | #define GPIO_P_MODEL_MODE7_PUSHPULL (_GPIO_P_MODEL_MODE7_PUSHPULL << 28) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 366 | #define GPIO_P_MODEL_MODE7_PUSHPULLDRIVE (_GPIO_P_MODEL_MODE7_PUSHPULLDRIVE << 28) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 367 | #define GPIO_P_MODEL_MODE7_WIREDOR (_GPIO_P_MODEL_MODE7_WIREDOR << 28) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 368 | #define GPIO_P_MODEL_MODE7_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE7_WIREDORPULLDOWN << 28) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 369 | #define GPIO_P_MODEL_MODE7_WIREDAND (_GPIO_P_MODEL_MODE7_WIREDAND << 28) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 370 | #define GPIO_P_MODEL_MODE7_WIREDANDFILTER (_GPIO_P_MODEL_MODE7_WIREDANDFILTER << 28) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 371 | #define GPIO_P_MODEL_MODE7_WIREDANDPULLUP (_GPIO_P_MODEL_MODE7_WIREDANDPULLUP << 28) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 372 | #define GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER << 28) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 373 | #define GPIO_P_MODEL_MODE7_WIREDANDDRIVE (_GPIO_P_MODEL_MODE7_WIREDANDDRIVE << 28) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 374 | #define GPIO_P_MODEL_MODE7_WIREDANDDRIVEFILTER (_GPIO_P_MODEL_MODE7_WIREDANDDRIVEFILTER << 28) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 375 | #define GPIO_P_MODEL_MODE7_WIREDANDDRIVEPULLUP (_GPIO_P_MODEL_MODE7_WIREDANDDRIVEPULLUP << 28) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 376 | #define GPIO_P_MODEL_MODE7_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEL_MODE7_WIREDANDDRIVEPULLUPFILTER << 28) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */ |
| <> | 150:02e0a0aed4ec | 377 | |
| <> | 150:02e0a0aed4ec | 378 | /* Bit fields for GPIO P_MODEH */ |
| <> | 150:02e0a0aed4ec | 379 | #define _GPIO_P_MODEH_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 380 | #define _GPIO_P_MODEH_MASK 0xFFFFFFFFUL /**< Mask for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 381 | #define _GPIO_P_MODEH_MODE8_SHIFT 0 /**< Shift value for GPIO_MODE8 */ |
| <> | 150:02e0a0aed4ec | 382 | #define _GPIO_P_MODEH_MODE8_MASK 0xFUL /**< Bit mask for GPIO_MODE8 */ |
| <> | 150:02e0a0aed4ec | 383 | #define _GPIO_P_MODEH_MODE8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 384 | #define _GPIO_P_MODEH_MODE8_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 385 | #define _GPIO_P_MODEH_MODE8_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 386 | #define _GPIO_P_MODEH_MODE8_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 387 | #define _GPIO_P_MODEH_MODE8_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 388 | #define _GPIO_P_MODEH_MODE8_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 389 | #define _GPIO_P_MODEH_MODE8_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 390 | #define _GPIO_P_MODEH_MODE8_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 391 | #define _GPIO_P_MODEH_MODE8_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 392 | #define _GPIO_P_MODEH_MODE8_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 393 | #define _GPIO_P_MODEH_MODE8_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 394 | #define _GPIO_P_MODEH_MODE8_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 395 | #define _GPIO_P_MODEH_MODE8_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 396 | #define _GPIO_P_MODEH_MODE8_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 397 | #define _GPIO_P_MODEH_MODE8_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 398 | #define _GPIO_P_MODEH_MODE8_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 399 | #define _GPIO_P_MODEH_MODE8_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 400 | #define GPIO_P_MODEH_MODE8_DEFAULT (_GPIO_P_MODEH_MODE8_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 401 | #define GPIO_P_MODEH_MODE8_DISABLED (_GPIO_P_MODEH_MODE8_DISABLED << 0) /**< Shifted mode DISABLED for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 402 | #define GPIO_P_MODEH_MODE8_INPUT (_GPIO_P_MODEH_MODE8_INPUT << 0) /**< Shifted mode INPUT for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 403 | #define GPIO_P_MODEH_MODE8_INPUTPULL (_GPIO_P_MODEH_MODE8_INPUTPULL << 0) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 404 | #define GPIO_P_MODEH_MODE8_INPUTPULLFILTER (_GPIO_P_MODEH_MODE8_INPUTPULLFILTER << 0) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 405 | #define GPIO_P_MODEH_MODE8_PUSHPULL (_GPIO_P_MODEH_MODE8_PUSHPULL << 0) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 406 | #define GPIO_P_MODEH_MODE8_PUSHPULLDRIVE (_GPIO_P_MODEH_MODE8_PUSHPULLDRIVE << 0) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 407 | #define GPIO_P_MODEH_MODE8_WIREDOR (_GPIO_P_MODEH_MODE8_WIREDOR << 0) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 408 | #define GPIO_P_MODEH_MODE8_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE8_WIREDORPULLDOWN << 0) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 409 | #define GPIO_P_MODEH_MODE8_WIREDAND (_GPIO_P_MODEH_MODE8_WIREDAND << 0) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 410 | #define GPIO_P_MODEH_MODE8_WIREDANDFILTER (_GPIO_P_MODEH_MODE8_WIREDANDFILTER << 0) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 411 | #define GPIO_P_MODEH_MODE8_WIREDANDPULLUP (_GPIO_P_MODEH_MODE8_WIREDANDPULLUP << 0) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 412 | #define GPIO_P_MODEH_MODE8_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE8_WIREDANDPULLUPFILTER << 0) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 413 | #define GPIO_P_MODEH_MODE8_WIREDANDDRIVE (_GPIO_P_MODEH_MODE8_WIREDANDDRIVE << 0) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 414 | #define GPIO_P_MODEH_MODE8_WIREDANDDRIVEFILTER (_GPIO_P_MODEH_MODE8_WIREDANDDRIVEFILTER << 0) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 415 | #define GPIO_P_MODEH_MODE8_WIREDANDDRIVEPULLUP (_GPIO_P_MODEH_MODE8_WIREDANDDRIVEPULLUP << 0) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 416 | #define GPIO_P_MODEH_MODE8_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEH_MODE8_WIREDANDDRIVEPULLUPFILTER << 0) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 417 | #define _GPIO_P_MODEH_MODE9_SHIFT 4 /**< Shift value for GPIO_MODE9 */ |
| <> | 150:02e0a0aed4ec | 418 | #define _GPIO_P_MODEH_MODE9_MASK 0xF0UL /**< Bit mask for GPIO_MODE9 */ |
| <> | 150:02e0a0aed4ec | 419 | #define _GPIO_P_MODEH_MODE9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 420 | #define _GPIO_P_MODEH_MODE9_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 421 | #define _GPIO_P_MODEH_MODE9_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 422 | #define _GPIO_P_MODEH_MODE9_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 423 | #define _GPIO_P_MODEH_MODE9_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 424 | #define _GPIO_P_MODEH_MODE9_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 425 | #define _GPIO_P_MODEH_MODE9_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 426 | #define _GPIO_P_MODEH_MODE9_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 427 | #define _GPIO_P_MODEH_MODE9_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 428 | #define _GPIO_P_MODEH_MODE9_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 429 | #define _GPIO_P_MODEH_MODE9_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 430 | #define _GPIO_P_MODEH_MODE9_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 431 | #define _GPIO_P_MODEH_MODE9_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 432 | #define _GPIO_P_MODEH_MODE9_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 433 | #define _GPIO_P_MODEH_MODE9_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 434 | #define _GPIO_P_MODEH_MODE9_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 435 | #define _GPIO_P_MODEH_MODE9_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 436 | #define GPIO_P_MODEH_MODE9_DEFAULT (_GPIO_P_MODEH_MODE9_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 437 | #define GPIO_P_MODEH_MODE9_DISABLED (_GPIO_P_MODEH_MODE9_DISABLED << 4) /**< Shifted mode DISABLED for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 438 | #define GPIO_P_MODEH_MODE9_INPUT (_GPIO_P_MODEH_MODE9_INPUT << 4) /**< Shifted mode INPUT for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 439 | #define GPIO_P_MODEH_MODE9_INPUTPULL (_GPIO_P_MODEH_MODE9_INPUTPULL << 4) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 440 | #define GPIO_P_MODEH_MODE9_INPUTPULLFILTER (_GPIO_P_MODEH_MODE9_INPUTPULLFILTER << 4) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 441 | #define GPIO_P_MODEH_MODE9_PUSHPULL (_GPIO_P_MODEH_MODE9_PUSHPULL << 4) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 442 | #define GPIO_P_MODEH_MODE9_PUSHPULLDRIVE (_GPIO_P_MODEH_MODE9_PUSHPULLDRIVE << 4) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 443 | #define GPIO_P_MODEH_MODE9_WIREDOR (_GPIO_P_MODEH_MODE9_WIREDOR << 4) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 444 | #define GPIO_P_MODEH_MODE9_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE9_WIREDORPULLDOWN << 4) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 445 | #define GPIO_P_MODEH_MODE9_WIREDAND (_GPIO_P_MODEH_MODE9_WIREDAND << 4) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 446 | #define GPIO_P_MODEH_MODE9_WIREDANDFILTER (_GPIO_P_MODEH_MODE9_WIREDANDFILTER << 4) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 447 | #define GPIO_P_MODEH_MODE9_WIREDANDPULLUP (_GPIO_P_MODEH_MODE9_WIREDANDPULLUP << 4) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 448 | #define GPIO_P_MODEH_MODE9_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE9_WIREDANDPULLUPFILTER << 4) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 449 | #define GPIO_P_MODEH_MODE9_WIREDANDDRIVE (_GPIO_P_MODEH_MODE9_WIREDANDDRIVE << 4) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 450 | #define GPIO_P_MODEH_MODE9_WIREDANDDRIVEFILTER (_GPIO_P_MODEH_MODE9_WIREDANDDRIVEFILTER << 4) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 451 | #define GPIO_P_MODEH_MODE9_WIREDANDDRIVEPULLUP (_GPIO_P_MODEH_MODE9_WIREDANDDRIVEPULLUP << 4) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 452 | #define GPIO_P_MODEH_MODE9_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEH_MODE9_WIREDANDDRIVEPULLUPFILTER << 4) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 453 | #define _GPIO_P_MODEH_MODE10_SHIFT 8 /**< Shift value for GPIO_MODE10 */ |
| <> | 150:02e0a0aed4ec | 454 | #define _GPIO_P_MODEH_MODE10_MASK 0xF00UL /**< Bit mask for GPIO_MODE10 */ |
| <> | 150:02e0a0aed4ec | 455 | #define _GPIO_P_MODEH_MODE10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 456 | #define _GPIO_P_MODEH_MODE10_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 457 | #define _GPIO_P_MODEH_MODE10_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 458 | #define _GPIO_P_MODEH_MODE10_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 459 | #define _GPIO_P_MODEH_MODE10_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 460 | #define _GPIO_P_MODEH_MODE10_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 461 | #define _GPIO_P_MODEH_MODE10_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 462 | #define _GPIO_P_MODEH_MODE10_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 463 | #define _GPIO_P_MODEH_MODE10_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 464 | #define _GPIO_P_MODEH_MODE10_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 465 | #define _GPIO_P_MODEH_MODE10_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 466 | #define _GPIO_P_MODEH_MODE10_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 467 | #define _GPIO_P_MODEH_MODE10_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 468 | #define _GPIO_P_MODEH_MODE10_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 469 | #define _GPIO_P_MODEH_MODE10_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 470 | #define _GPIO_P_MODEH_MODE10_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 471 | #define _GPIO_P_MODEH_MODE10_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 472 | #define GPIO_P_MODEH_MODE10_DEFAULT (_GPIO_P_MODEH_MODE10_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 473 | #define GPIO_P_MODEH_MODE10_DISABLED (_GPIO_P_MODEH_MODE10_DISABLED << 8) /**< Shifted mode DISABLED for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 474 | #define GPIO_P_MODEH_MODE10_INPUT (_GPIO_P_MODEH_MODE10_INPUT << 8) /**< Shifted mode INPUT for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 475 | #define GPIO_P_MODEH_MODE10_INPUTPULL (_GPIO_P_MODEH_MODE10_INPUTPULL << 8) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 476 | #define GPIO_P_MODEH_MODE10_INPUTPULLFILTER (_GPIO_P_MODEH_MODE10_INPUTPULLFILTER << 8) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 477 | #define GPIO_P_MODEH_MODE10_PUSHPULL (_GPIO_P_MODEH_MODE10_PUSHPULL << 8) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 478 | #define GPIO_P_MODEH_MODE10_PUSHPULLDRIVE (_GPIO_P_MODEH_MODE10_PUSHPULLDRIVE << 8) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 479 | #define GPIO_P_MODEH_MODE10_WIREDOR (_GPIO_P_MODEH_MODE10_WIREDOR << 8) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 480 | #define GPIO_P_MODEH_MODE10_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE10_WIREDORPULLDOWN << 8) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 481 | #define GPIO_P_MODEH_MODE10_WIREDAND (_GPIO_P_MODEH_MODE10_WIREDAND << 8) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 482 | #define GPIO_P_MODEH_MODE10_WIREDANDFILTER (_GPIO_P_MODEH_MODE10_WIREDANDFILTER << 8) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 483 | #define GPIO_P_MODEH_MODE10_WIREDANDPULLUP (_GPIO_P_MODEH_MODE10_WIREDANDPULLUP << 8) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 484 | #define GPIO_P_MODEH_MODE10_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE10_WIREDANDPULLUPFILTER << 8) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 485 | #define GPIO_P_MODEH_MODE10_WIREDANDDRIVE (_GPIO_P_MODEH_MODE10_WIREDANDDRIVE << 8) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 486 | #define GPIO_P_MODEH_MODE10_WIREDANDDRIVEFILTER (_GPIO_P_MODEH_MODE10_WIREDANDDRIVEFILTER << 8) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 487 | #define GPIO_P_MODEH_MODE10_WIREDANDDRIVEPULLUP (_GPIO_P_MODEH_MODE10_WIREDANDDRIVEPULLUP << 8) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 488 | #define GPIO_P_MODEH_MODE10_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEH_MODE10_WIREDANDDRIVEPULLUPFILTER << 8) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 489 | #define _GPIO_P_MODEH_MODE11_SHIFT 12 /**< Shift value for GPIO_MODE11 */ |
| <> | 150:02e0a0aed4ec | 490 | #define _GPIO_P_MODEH_MODE11_MASK 0xF000UL /**< Bit mask for GPIO_MODE11 */ |
| <> | 150:02e0a0aed4ec | 491 | #define _GPIO_P_MODEH_MODE11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 492 | #define _GPIO_P_MODEH_MODE11_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 493 | #define _GPIO_P_MODEH_MODE11_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 494 | #define _GPIO_P_MODEH_MODE11_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 495 | #define _GPIO_P_MODEH_MODE11_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 496 | #define _GPIO_P_MODEH_MODE11_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 497 | #define _GPIO_P_MODEH_MODE11_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 498 | #define _GPIO_P_MODEH_MODE11_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 499 | #define _GPIO_P_MODEH_MODE11_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 500 | #define _GPIO_P_MODEH_MODE11_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 501 | #define _GPIO_P_MODEH_MODE11_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 502 | #define _GPIO_P_MODEH_MODE11_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 503 | #define _GPIO_P_MODEH_MODE11_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 504 | #define _GPIO_P_MODEH_MODE11_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 505 | #define _GPIO_P_MODEH_MODE11_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 506 | #define _GPIO_P_MODEH_MODE11_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 507 | #define _GPIO_P_MODEH_MODE11_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 508 | #define GPIO_P_MODEH_MODE11_DEFAULT (_GPIO_P_MODEH_MODE11_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 509 | #define GPIO_P_MODEH_MODE11_DISABLED (_GPIO_P_MODEH_MODE11_DISABLED << 12) /**< Shifted mode DISABLED for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 510 | #define GPIO_P_MODEH_MODE11_INPUT (_GPIO_P_MODEH_MODE11_INPUT << 12) /**< Shifted mode INPUT for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 511 | #define GPIO_P_MODEH_MODE11_INPUTPULL (_GPIO_P_MODEH_MODE11_INPUTPULL << 12) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 512 | #define GPIO_P_MODEH_MODE11_INPUTPULLFILTER (_GPIO_P_MODEH_MODE11_INPUTPULLFILTER << 12) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 513 | #define GPIO_P_MODEH_MODE11_PUSHPULL (_GPIO_P_MODEH_MODE11_PUSHPULL << 12) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 514 | #define GPIO_P_MODEH_MODE11_PUSHPULLDRIVE (_GPIO_P_MODEH_MODE11_PUSHPULLDRIVE << 12) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 515 | #define GPIO_P_MODEH_MODE11_WIREDOR (_GPIO_P_MODEH_MODE11_WIREDOR << 12) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 516 | #define GPIO_P_MODEH_MODE11_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE11_WIREDORPULLDOWN << 12) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 517 | #define GPIO_P_MODEH_MODE11_WIREDAND (_GPIO_P_MODEH_MODE11_WIREDAND << 12) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 518 | #define GPIO_P_MODEH_MODE11_WIREDANDFILTER (_GPIO_P_MODEH_MODE11_WIREDANDFILTER << 12) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 519 | #define GPIO_P_MODEH_MODE11_WIREDANDPULLUP (_GPIO_P_MODEH_MODE11_WIREDANDPULLUP << 12) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 520 | #define GPIO_P_MODEH_MODE11_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE11_WIREDANDPULLUPFILTER << 12) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 521 | #define GPIO_P_MODEH_MODE11_WIREDANDDRIVE (_GPIO_P_MODEH_MODE11_WIREDANDDRIVE << 12) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 522 | #define GPIO_P_MODEH_MODE11_WIREDANDDRIVEFILTER (_GPIO_P_MODEH_MODE11_WIREDANDDRIVEFILTER << 12) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 523 | #define GPIO_P_MODEH_MODE11_WIREDANDDRIVEPULLUP (_GPIO_P_MODEH_MODE11_WIREDANDDRIVEPULLUP << 12) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 524 | #define GPIO_P_MODEH_MODE11_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEH_MODE11_WIREDANDDRIVEPULLUPFILTER << 12) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 525 | #define _GPIO_P_MODEH_MODE12_SHIFT 16 /**< Shift value for GPIO_MODE12 */ |
| <> | 150:02e0a0aed4ec | 526 | #define _GPIO_P_MODEH_MODE12_MASK 0xF0000UL /**< Bit mask for GPIO_MODE12 */ |
| <> | 150:02e0a0aed4ec | 527 | #define _GPIO_P_MODEH_MODE12_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 528 | #define _GPIO_P_MODEH_MODE12_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 529 | #define _GPIO_P_MODEH_MODE12_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 530 | #define _GPIO_P_MODEH_MODE12_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 531 | #define _GPIO_P_MODEH_MODE12_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 532 | #define _GPIO_P_MODEH_MODE12_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 533 | #define _GPIO_P_MODEH_MODE12_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 534 | #define _GPIO_P_MODEH_MODE12_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 535 | #define _GPIO_P_MODEH_MODE12_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 536 | #define _GPIO_P_MODEH_MODE12_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 537 | #define _GPIO_P_MODEH_MODE12_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 538 | #define _GPIO_P_MODEH_MODE12_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 539 | #define _GPIO_P_MODEH_MODE12_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 540 | #define _GPIO_P_MODEH_MODE12_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 541 | #define _GPIO_P_MODEH_MODE12_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 542 | #define _GPIO_P_MODEH_MODE12_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 543 | #define _GPIO_P_MODEH_MODE12_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 544 | #define GPIO_P_MODEH_MODE12_DEFAULT (_GPIO_P_MODEH_MODE12_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 545 | #define GPIO_P_MODEH_MODE12_DISABLED (_GPIO_P_MODEH_MODE12_DISABLED << 16) /**< Shifted mode DISABLED for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 546 | #define GPIO_P_MODEH_MODE12_INPUT (_GPIO_P_MODEH_MODE12_INPUT << 16) /**< Shifted mode INPUT for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 547 | #define GPIO_P_MODEH_MODE12_INPUTPULL (_GPIO_P_MODEH_MODE12_INPUTPULL << 16) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 548 | #define GPIO_P_MODEH_MODE12_INPUTPULLFILTER (_GPIO_P_MODEH_MODE12_INPUTPULLFILTER << 16) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 549 | #define GPIO_P_MODEH_MODE12_PUSHPULL (_GPIO_P_MODEH_MODE12_PUSHPULL << 16) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 550 | #define GPIO_P_MODEH_MODE12_PUSHPULLDRIVE (_GPIO_P_MODEH_MODE12_PUSHPULLDRIVE << 16) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 551 | #define GPIO_P_MODEH_MODE12_WIREDOR (_GPIO_P_MODEH_MODE12_WIREDOR << 16) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 552 | #define GPIO_P_MODEH_MODE12_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE12_WIREDORPULLDOWN << 16) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 553 | #define GPIO_P_MODEH_MODE12_WIREDAND (_GPIO_P_MODEH_MODE12_WIREDAND << 16) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 554 | #define GPIO_P_MODEH_MODE12_WIREDANDFILTER (_GPIO_P_MODEH_MODE12_WIREDANDFILTER << 16) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 555 | #define GPIO_P_MODEH_MODE12_WIREDANDPULLUP (_GPIO_P_MODEH_MODE12_WIREDANDPULLUP << 16) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 556 | #define GPIO_P_MODEH_MODE12_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE12_WIREDANDPULLUPFILTER << 16) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 557 | #define GPIO_P_MODEH_MODE12_WIREDANDDRIVE (_GPIO_P_MODEH_MODE12_WIREDANDDRIVE << 16) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 558 | #define GPIO_P_MODEH_MODE12_WIREDANDDRIVEFILTER (_GPIO_P_MODEH_MODE12_WIREDANDDRIVEFILTER << 16) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 559 | #define GPIO_P_MODEH_MODE12_WIREDANDDRIVEPULLUP (_GPIO_P_MODEH_MODE12_WIREDANDDRIVEPULLUP << 16) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 560 | #define GPIO_P_MODEH_MODE12_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEH_MODE12_WIREDANDDRIVEPULLUPFILTER << 16) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 561 | #define _GPIO_P_MODEH_MODE13_SHIFT 20 /**< Shift value for GPIO_MODE13 */ |
| <> | 150:02e0a0aed4ec | 562 | #define _GPIO_P_MODEH_MODE13_MASK 0xF00000UL /**< Bit mask for GPIO_MODE13 */ |
| <> | 150:02e0a0aed4ec | 563 | #define _GPIO_P_MODEH_MODE13_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 564 | #define _GPIO_P_MODEH_MODE13_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 565 | #define _GPIO_P_MODEH_MODE13_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 566 | #define _GPIO_P_MODEH_MODE13_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 567 | #define _GPIO_P_MODEH_MODE13_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 568 | #define _GPIO_P_MODEH_MODE13_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 569 | #define _GPIO_P_MODEH_MODE13_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 570 | #define _GPIO_P_MODEH_MODE13_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 571 | #define _GPIO_P_MODEH_MODE13_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 572 | #define _GPIO_P_MODEH_MODE13_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 573 | #define _GPIO_P_MODEH_MODE13_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 574 | #define _GPIO_P_MODEH_MODE13_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 575 | #define _GPIO_P_MODEH_MODE13_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 576 | #define _GPIO_P_MODEH_MODE13_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 577 | #define _GPIO_P_MODEH_MODE13_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 578 | #define _GPIO_P_MODEH_MODE13_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 579 | #define _GPIO_P_MODEH_MODE13_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 580 | #define GPIO_P_MODEH_MODE13_DEFAULT (_GPIO_P_MODEH_MODE13_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 581 | #define GPIO_P_MODEH_MODE13_DISABLED (_GPIO_P_MODEH_MODE13_DISABLED << 20) /**< Shifted mode DISABLED for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 582 | #define GPIO_P_MODEH_MODE13_INPUT (_GPIO_P_MODEH_MODE13_INPUT << 20) /**< Shifted mode INPUT for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 583 | #define GPIO_P_MODEH_MODE13_INPUTPULL (_GPIO_P_MODEH_MODE13_INPUTPULL << 20) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 584 | #define GPIO_P_MODEH_MODE13_INPUTPULLFILTER (_GPIO_P_MODEH_MODE13_INPUTPULLFILTER << 20) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 585 | #define GPIO_P_MODEH_MODE13_PUSHPULL (_GPIO_P_MODEH_MODE13_PUSHPULL << 20) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 586 | #define GPIO_P_MODEH_MODE13_PUSHPULLDRIVE (_GPIO_P_MODEH_MODE13_PUSHPULLDRIVE << 20) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 587 | #define GPIO_P_MODEH_MODE13_WIREDOR (_GPIO_P_MODEH_MODE13_WIREDOR << 20) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 588 | #define GPIO_P_MODEH_MODE13_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE13_WIREDORPULLDOWN << 20) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 589 | #define GPIO_P_MODEH_MODE13_WIREDAND (_GPIO_P_MODEH_MODE13_WIREDAND << 20) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 590 | #define GPIO_P_MODEH_MODE13_WIREDANDFILTER (_GPIO_P_MODEH_MODE13_WIREDANDFILTER << 20) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 591 | #define GPIO_P_MODEH_MODE13_WIREDANDPULLUP (_GPIO_P_MODEH_MODE13_WIREDANDPULLUP << 20) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 592 | #define GPIO_P_MODEH_MODE13_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE13_WIREDANDPULLUPFILTER << 20) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 593 | #define GPIO_P_MODEH_MODE13_WIREDANDDRIVE (_GPIO_P_MODEH_MODE13_WIREDANDDRIVE << 20) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 594 | #define GPIO_P_MODEH_MODE13_WIREDANDDRIVEFILTER (_GPIO_P_MODEH_MODE13_WIREDANDDRIVEFILTER << 20) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 595 | #define GPIO_P_MODEH_MODE13_WIREDANDDRIVEPULLUP (_GPIO_P_MODEH_MODE13_WIREDANDDRIVEPULLUP << 20) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 596 | #define GPIO_P_MODEH_MODE13_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEH_MODE13_WIREDANDDRIVEPULLUPFILTER << 20) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 597 | #define _GPIO_P_MODEH_MODE14_SHIFT 24 /**< Shift value for GPIO_MODE14 */ |
| <> | 150:02e0a0aed4ec | 598 | #define _GPIO_P_MODEH_MODE14_MASK 0xF000000UL /**< Bit mask for GPIO_MODE14 */ |
| <> | 150:02e0a0aed4ec | 599 | #define _GPIO_P_MODEH_MODE14_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 600 | #define _GPIO_P_MODEH_MODE14_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 601 | #define _GPIO_P_MODEH_MODE14_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 602 | #define _GPIO_P_MODEH_MODE14_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 603 | #define _GPIO_P_MODEH_MODE14_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 604 | #define _GPIO_P_MODEH_MODE14_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 605 | #define _GPIO_P_MODEH_MODE14_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 606 | #define _GPIO_P_MODEH_MODE14_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 607 | #define _GPIO_P_MODEH_MODE14_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 608 | #define _GPIO_P_MODEH_MODE14_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 609 | #define _GPIO_P_MODEH_MODE14_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 610 | #define _GPIO_P_MODEH_MODE14_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 611 | #define _GPIO_P_MODEH_MODE14_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 612 | #define _GPIO_P_MODEH_MODE14_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 613 | #define _GPIO_P_MODEH_MODE14_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 614 | #define _GPIO_P_MODEH_MODE14_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 615 | #define _GPIO_P_MODEH_MODE14_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 616 | #define GPIO_P_MODEH_MODE14_DEFAULT (_GPIO_P_MODEH_MODE14_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 617 | #define GPIO_P_MODEH_MODE14_DISABLED (_GPIO_P_MODEH_MODE14_DISABLED << 24) /**< Shifted mode DISABLED for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 618 | #define GPIO_P_MODEH_MODE14_INPUT (_GPIO_P_MODEH_MODE14_INPUT << 24) /**< Shifted mode INPUT for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 619 | #define GPIO_P_MODEH_MODE14_INPUTPULL (_GPIO_P_MODEH_MODE14_INPUTPULL << 24) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 620 | #define GPIO_P_MODEH_MODE14_INPUTPULLFILTER (_GPIO_P_MODEH_MODE14_INPUTPULLFILTER << 24) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 621 | #define GPIO_P_MODEH_MODE14_PUSHPULL (_GPIO_P_MODEH_MODE14_PUSHPULL << 24) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 622 | #define GPIO_P_MODEH_MODE14_PUSHPULLDRIVE (_GPIO_P_MODEH_MODE14_PUSHPULLDRIVE << 24) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 623 | #define GPIO_P_MODEH_MODE14_WIREDOR (_GPIO_P_MODEH_MODE14_WIREDOR << 24) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 624 | #define GPIO_P_MODEH_MODE14_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE14_WIREDORPULLDOWN << 24) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 625 | #define GPIO_P_MODEH_MODE14_WIREDAND (_GPIO_P_MODEH_MODE14_WIREDAND << 24) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 626 | #define GPIO_P_MODEH_MODE14_WIREDANDFILTER (_GPIO_P_MODEH_MODE14_WIREDANDFILTER << 24) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 627 | #define GPIO_P_MODEH_MODE14_WIREDANDPULLUP (_GPIO_P_MODEH_MODE14_WIREDANDPULLUP << 24) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 628 | #define GPIO_P_MODEH_MODE14_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE14_WIREDANDPULLUPFILTER << 24) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 629 | #define GPIO_P_MODEH_MODE14_WIREDANDDRIVE (_GPIO_P_MODEH_MODE14_WIREDANDDRIVE << 24) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 630 | #define GPIO_P_MODEH_MODE14_WIREDANDDRIVEFILTER (_GPIO_P_MODEH_MODE14_WIREDANDDRIVEFILTER << 24) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 631 | #define GPIO_P_MODEH_MODE14_WIREDANDDRIVEPULLUP (_GPIO_P_MODEH_MODE14_WIREDANDDRIVEPULLUP << 24) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 632 | #define GPIO_P_MODEH_MODE14_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEH_MODE14_WIREDANDDRIVEPULLUPFILTER << 24) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 633 | #define _GPIO_P_MODEH_MODE15_SHIFT 28 /**< Shift value for GPIO_MODE15 */ |
| <> | 150:02e0a0aed4ec | 634 | #define _GPIO_P_MODEH_MODE15_MASK 0xF0000000UL /**< Bit mask for GPIO_MODE15 */ |
| <> | 150:02e0a0aed4ec | 635 | #define _GPIO_P_MODEH_MODE15_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 636 | #define _GPIO_P_MODEH_MODE15_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 637 | #define _GPIO_P_MODEH_MODE15_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 638 | #define _GPIO_P_MODEH_MODE15_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 639 | #define _GPIO_P_MODEH_MODE15_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 640 | #define _GPIO_P_MODEH_MODE15_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 641 | #define _GPIO_P_MODEH_MODE15_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 642 | #define _GPIO_P_MODEH_MODE15_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 643 | #define _GPIO_P_MODEH_MODE15_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 644 | #define _GPIO_P_MODEH_MODE15_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 645 | #define _GPIO_P_MODEH_MODE15_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 646 | #define _GPIO_P_MODEH_MODE15_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 647 | #define _GPIO_P_MODEH_MODE15_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 648 | #define _GPIO_P_MODEH_MODE15_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 649 | #define _GPIO_P_MODEH_MODE15_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 650 | #define _GPIO_P_MODEH_MODE15_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 651 | #define _GPIO_P_MODEH_MODE15_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 652 | #define GPIO_P_MODEH_MODE15_DEFAULT (_GPIO_P_MODEH_MODE15_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 653 | #define GPIO_P_MODEH_MODE15_DISABLED (_GPIO_P_MODEH_MODE15_DISABLED << 28) /**< Shifted mode DISABLED for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 654 | #define GPIO_P_MODEH_MODE15_INPUT (_GPIO_P_MODEH_MODE15_INPUT << 28) /**< Shifted mode INPUT for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 655 | #define GPIO_P_MODEH_MODE15_INPUTPULL (_GPIO_P_MODEH_MODE15_INPUTPULL << 28) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 656 | #define GPIO_P_MODEH_MODE15_INPUTPULLFILTER (_GPIO_P_MODEH_MODE15_INPUTPULLFILTER << 28) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 657 | #define GPIO_P_MODEH_MODE15_PUSHPULL (_GPIO_P_MODEH_MODE15_PUSHPULL << 28) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 658 | #define GPIO_P_MODEH_MODE15_PUSHPULLDRIVE (_GPIO_P_MODEH_MODE15_PUSHPULLDRIVE << 28) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 659 | #define GPIO_P_MODEH_MODE15_WIREDOR (_GPIO_P_MODEH_MODE15_WIREDOR << 28) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 660 | #define GPIO_P_MODEH_MODE15_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE15_WIREDORPULLDOWN << 28) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 661 | #define GPIO_P_MODEH_MODE15_WIREDAND (_GPIO_P_MODEH_MODE15_WIREDAND << 28) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 662 | #define GPIO_P_MODEH_MODE15_WIREDANDFILTER (_GPIO_P_MODEH_MODE15_WIREDANDFILTER << 28) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 663 | #define GPIO_P_MODEH_MODE15_WIREDANDPULLUP (_GPIO_P_MODEH_MODE15_WIREDANDPULLUP << 28) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 664 | #define GPIO_P_MODEH_MODE15_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE15_WIREDANDPULLUPFILTER << 28) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 665 | #define GPIO_P_MODEH_MODE15_WIREDANDDRIVE (_GPIO_P_MODEH_MODE15_WIREDANDDRIVE << 28) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 666 | #define GPIO_P_MODEH_MODE15_WIREDANDDRIVEFILTER (_GPIO_P_MODEH_MODE15_WIREDANDDRIVEFILTER << 28) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 667 | #define GPIO_P_MODEH_MODE15_WIREDANDDRIVEPULLUP (_GPIO_P_MODEH_MODE15_WIREDANDDRIVEPULLUP << 28) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 668 | #define GPIO_P_MODEH_MODE15_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEH_MODE15_WIREDANDDRIVEPULLUPFILTER << 28) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */ |
| <> | 150:02e0a0aed4ec | 669 | |
| <> | 150:02e0a0aed4ec | 670 | /* Bit fields for GPIO P_DOUT */ |
| <> | 150:02e0a0aed4ec | 671 | #define _GPIO_P_DOUT_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DOUT */ |
| <> | 150:02e0a0aed4ec | 672 | #define _GPIO_P_DOUT_MASK 0x0000FFFFUL /**< Mask for GPIO_P_DOUT */ |
| <> | 150:02e0a0aed4ec | 673 | #define _GPIO_P_DOUT_DOUT_SHIFT 0 /**< Shift value for GPIO_DOUT */ |
| <> | 150:02e0a0aed4ec | 674 | #define _GPIO_P_DOUT_DOUT_MASK 0xFFFFUL /**< Bit mask for GPIO_DOUT */ |
| <> | 150:02e0a0aed4ec | 675 | #define _GPIO_P_DOUT_DOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DOUT */ |
| <> | 150:02e0a0aed4ec | 676 | #define GPIO_P_DOUT_DOUT_DEFAULT (_GPIO_P_DOUT_DOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DOUT */ |
| <> | 150:02e0a0aed4ec | 677 | |
| <> | 150:02e0a0aed4ec | 678 | /* Bit fields for GPIO P_DOUTSET */ |
| <> | 150:02e0a0aed4ec | 679 | #define _GPIO_P_DOUTSET_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DOUTSET */ |
| <> | 150:02e0a0aed4ec | 680 | #define _GPIO_P_DOUTSET_MASK 0x0000FFFFUL /**< Mask for GPIO_P_DOUTSET */ |
| <> | 150:02e0a0aed4ec | 681 | #define _GPIO_P_DOUTSET_DOUTSET_SHIFT 0 /**< Shift value for GPIO_DOUTSET */ |
| <> | 150:02e0a0aed4ec | 682 | #define _GPIO_P_DOUTSET_DOUTSET_MASK 0xFFFFUL /**< Bit mask for GPIO_DOUTSET */ |
| <> | 150:02e0a0aed4ec | 683 | #define _GPIO_P_DOUTSET_DOUTSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DOUTSET */ |
| <> | 150:02e0a0aed4ec | 684 | #define GPIO_P_DOUTSET_DOUTSET_DEFAULT (_GPIO_P_DOUTSET_DOUTSET_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DOUTSET */ |
| <> | 150:02e0a0aed4ec | 685 | |
| <> | 150:02e0a0aed4ec | 686 | /* Bit fields for GPIO P_DOUTCLR */ |
| <> | 150:02e0a0aed4ec | 687 | #define _GPIO_P_DOUTCLR_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DOUTCLR */ |
| <> | 150:02e0a0aed4ec | 688 | #define _GPIO_P_DOUTCLR_MASK 0x0000FFFFUL /**< Mask for GPIO_P_DOUTCLR */ |
| <> | 150:02e0a0aed4ec | 689 | #define _GPIO_P_DOUTCLR_DOUTCLR_SHIFT 0 /**< Shift value for GPIO_DOUTCLR */ |
| <> | 150:02e0a0aed4ec | 690 | #define _GPIO_P_DOUTCLR_DOUTCLR_MASK 0xFFFFUL /**< Bit mask for GPIO_DOUTCLR */ |
| <> | 150:02e0a0aed4ec | 691 | #define _GPIO_P_DOUTCLR_DOUTCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DOUTCLR */ |
| <> | 150:02e0a0aed4ec | 692 | #define GPIO_P_DOUTCLR_DOUTCLR_DEFAULT (_GPIO_P_DOUTCLR_DOUTCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DOUTCLR */ |
| <> | 150:02e0a0aed4ec | 693 | |
| <> | 150:02e0a0aed4ec | 694 | /* Bit fields for GPIO P_DOUTTGL */ |
| <> | 150:02e0a0aed4ec | 695 | #define _GPIO_P_DOUTTGL_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DOUTTGL */ |
| <> | 150:02e0a0aed4ec | 696 | #define _GPIO_P_DOUTTGL_MASK 0x0000FFFFUL /**< Mask for GPIO_P_DOUTTGL */ |
| <> | 150:02e0a0aed4ec | 697 | #define _GPIO_P_DOUTTGL_DOUTTGL_SHIFT 0 /**< Shift value for GPIO_DOUTTGL */ |
| <> | 150:02e0a0aed4ec | 698 | #define _GPIO_P_DOUTTGL_DOUTTGL_MASK 0xFFFFUL /**< Bit mask for GPIO_DOUTTGL */ |
| <> | 150:02e0a0aed4ec | 699 | #define _GPIO_P_DOUTTGL_DOUTTGL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DOUTTGL */ |
| <> | 150:02e0a0aed4ec | 700 | #define GPIO_P_DOUTTGL_DOUTTGL_DEFAULT (_GPIO_P_DOUTTGL_DOUTTGL_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DOUTTGL */ |
| <> | 150:02e0a0aed4ec | 701 | |
| <> | 150:02e0a0aed4ec | 702 | /* Bit fields for GPIO P_DIN */ |
| <> | 150:02e0a0aed4ec | 703 | #define _GPIO_P_DIN_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DIN */ |
| <> | 150:02e0a0aed4ec | 704 | #define _GPIO_P_DIN_MASK 0x0000FFFFUL /**< Mask for GPIO_P_DIN */ |
| <> | 150:02e0a0aed4ec | 705 | #define _GPIO_P_DIN_DIN_SHIFT 0 /**< Shift value for GPIO_DIN */ |
| <> | 150:02e0a0aed4ec | 706 | #define _GPIO_P_DIN_DIN_MASK 0xFFFFUL /**< Bit mask for GPIO_DIN */ |
| <> | 150:02e0a0aed4ec | 707 | #define _GPIO_P_DIN_DIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DIN */ |
| <> | 150:02e0a0aed4ec | 708 | #define GPIO_P_DIN_DIN_DEFAULT (_GPIO_P_DIN_DIN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DIN */ |
| <> | 150:02e0a0aed4ec | 709 | |
| <> | 150:02e0a0aed4ec | 710 | /* Bit fields for GPIO P_PINLOCKN */ |
| <> | 150:02e0a0aed4ec | 711 | #define _GPIO_P_PINLOCKN_RESETVALUE 0x0000FFFFUL /**< Default value for GPIO_P_PINLOCKN */ |
| <> | 150:02e0a0aed4ec | 712 | #define _GPIO_P_PINLOCKN_MASK 0x0000FFFFUL /**< Mask for GPIO_P_PINLOCKN */ |
| <> | 150:02e0a0aed4ec | 713 | #define _GPIO_P_PINLOCKN_PINLOCKN_SHIFT 0 /**< Shift value for GPIO_PINLOCKN */ |
| <> | 150:02e0a0aed4ec | 714 | #define _GPIO_P_PINLOCKN_PINLOCKN_MASK 0xFFFFUL /**< Bit mask for GPIO_PINLOCKN */ |
| <> | 150:02e0a0aed4ec | 715 | #define _GPIO_P_PINLOCKN_PINLOCKN_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for GPIO_P_PINLOCKN */ |
| <> | 150:02e0a0aed4ec | 716 | #define GPIO_P_PINLOCKN_PINLOCKN_DEFAULT (_GPIO_P_PINLOCKN_PINLOCKN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_PINLOCKN */ |
| <> | 150:02e0a0aed4ec | 717 | |
| <> | 150:02e0a0aed4ec | 718 | /* Bit fields for GPIO EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 719 | #define _GPIO_EXTIPSELL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 720 | #define _GPIO_EXTIPSELL_MASK 0x77777777UL /**< Mask for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 721 | #define _GPIO_EXTIPSELL_EXTIPSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPSEL0 */ |
| <> | 150:02e0a0aed4ec | 722 | #define _GPIO_EXTIPSELL_EXTIPSEL0_MASK 0x7UL /**< Bit mask for GPIO_EXTIPSEL0 */ |
| <> | 150:02e0a0aed4ec | 723 | #define _GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 724 | #define _GPIO_EXTIPSELL_EXTIPSEL0_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 725 | #define _GPIO_EXTIPSELL_EXTIPSEL0_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 726 | #define _GPIO_EXTIPSELL_EXTIPSEL0_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 727 | #define _GPIO_EXTIPSELL_EXTIPSEL0_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 728 | #define _GPIO_EXTIPSELL_EXTIPSEL0_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 729 | #define _GPIO_EXTIPSELL_EXTIPSEL0_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 730 | #define GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 731 | #define GPIO_EXTIPSELL_EXTIPSEL0_PORTA (_GPIO_EXTIPSELL_EXTIPSEL0_PORTA << 0) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 732 | #define GPIO_EXTIPSELL_EXTIPSEL0_PORTB (_GPIO_EXTIPSELL_EXTIPSEL0_PORTB << 0) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 733 | #define GPIO_EXTIPSELL_EXTIPSEL0_PORTC (_GPIO_EXTIPSELL_EXTIPSEL0_PORTC << 0) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 734 | #define GPIO_EXTIPSELL_EXTIPSEL0_PORTD (_GPIO_EXTIPSELL_EXTIPSEL0_PORTD << 0) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 735 | #define GPIO_EXTIPSELL_EXTIPSEL0_PORTE (_GPIO_EXTIPSELL_EXTIPSEL0_PORTE << 0) /**< Shifted mode PORTE for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 736 | #define GPIO_EXTIPSELL_EXTIPSEL0_PORTF (_GPIO_EXTIPSELL_EXTIPSEL0_PORTF << 0) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 737 | #define _GPIO_EXTIPSELL_EXTIPSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPSEL1 */ |
| <> | 150:02e0a0aed4ec | 738 | #define _GPIO_EXTIPSELL_EXTIPSEL1_MASK 0x70UL /**< Bit mask for GPIO_EXTIPSEL1 */ |
| <> | 150:02e0a0aed4ec | 739 | #define _GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 740 | #define _GPIO_EXTIPSELL_EXTIPSEL1_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 741 | #define _GPIO_EXTIPSELL_EXTIPSEL1_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 742 | #define _GPIO_EXTIPSELL_EXTIPSEL1_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 743 | #define _GPIO_EXTIPSELL_EXTIPSEL1_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 744 | #define _GPIO_EXTIPSELL_EXTIPSEL1_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 745 | #define _GPIO_EXTIPSELL_EXTIPSEL1_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 746 | #define GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 747 | #define GPIO_EXTIPSELL_EXTIPSEL1_PORTA (_GPIO_EXTIPSELL_EXTIPSEL1_PORTA << 4) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 748 | #define GPIO_EXTIPSELL_EXTIPSEL1_PORTB (_GPIO_EXTIPSELL_EXTIPSEL1_PORTB << 4) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 749 | #define GPIO_EXTIPSELL_EXTIPSEL1_PORTC (_GPIO_EXTIPSELL_EXTIPSEL1_PORTC << 4) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 750 | #define GPIO_EXTIPSELL_EXTIPSEL1_PORTD (_GPIO_EXTIPSELL_EXTIPSEL1_PORTD << 4) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 751 | #define GPIO_EXTIPSELL_EXTIPSEL1_PORTE (_GPIO_EXTIPSELL_EXTIPSEL1_PORTE << 4) /**< Shifted mode PORTE for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 752 | #define GPIO_EXTIPSELL_EXTIPSEL1_PORTF (_GPIO_EXTIPSELL_EXTIPSEL1_PORTF << 4) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 753 | #define _GPIO_EXTIPSELL_EXTIPSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPSEL2 */ |
| <> | 150:02e0a0aed4ec | 754 | #define _GPIO_EXTIPSELL_EXTIPSEL2_MASK 0x700UL /**< Bit mask for GPIO_EXTIPSEL2 */ |
| <> | 150:02e0a0aed4ec | 755 | #define _GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 756 | #define _GPIO_EXTIPSELL_EXTIPSEL2_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 757 | #define _GPIO_EXTIPSELL_EXTIPSEL2_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 758 | #define _GPIO_EXTIPSELL_EXTIPSEL2_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 759 | #define _GPIO_EXTIPSELL_EXTIPSEL2_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 760 | #define _GPIO_EXTIPSELL_EXTIPSEL2_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 761 | #define _GPIO_EXTIPSELL_EXTIPSEL2_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 762 | #define GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 763 | #define GPIO_EXTIPSELL_EXTIPSEL2_PORTA (_GPIO_EXTIPSELL_EXTIPSEL2_PORTA << 8) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 764 | #define GPIO_EXTIPSELL_EXTIPSEL2_PORTB (_GPIO_EXTIPSELL_EXTIPSEL2_PORTB << 8) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 765 | #define GPIO_EXTIPSELL_EXTIPSEL2_PORTC (_GPIO_EXTIPSELL_EXTIPSEL2_PORTC << 8) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 766 | #define GPIO_EXTIPSELL_EXTIPSEL2_PORTD (_GPIO_EXTIPSELL_EXTIPSEL2_PORTD << 8) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 767 | #define GPIO_EXTIPSELL_EXTIPSEL2_PORTE (_GPIO_EXTIPSELL_EXTIPSEL2_PORTE << 8) /**< Shifted mode PORTE for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 768 | #define GPIO_EXTIPSELL_EXTIPSEL2_PORTF (_GPIO_EXTIPSELL_EXTIPSEL2_PORTF << 8) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 769 | #define _GPIO_EXTIPSELL_EXTIPSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPSEL3 */ |
| <> | 150:02e0a0aed4ec | 770 | #define _GPIO_EXTIPSELL_EXTIPSEL3_MASK 0x7000UL /**< Bit mask for GPIO_EXTIPSEL3 */ |
| <> | 150:02e0a0aed4ec | 771 | #define _GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 772 | #define _GPIO_EXTIPSELL_EXTIPSEL3_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 773 | #define _GPIO_EXTIPSELL_EXTIPSEL3_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 774 | #define _GPIO_EXTIPSELL_EXTIPSEL3_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 775 | #define _GPIO_EXTIPSELL_EXTIPSEL3_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 776 | #define _GPIO_EXTIPSELL_EXTIPSEL3_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 777 | #define _GPIO_EXTIPSELL_EXTIPSEL3_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 778 | #define GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 779 | #define GPIO_EXTIPSELL_EXTIPSEL3_PORTA (_GPIO_EXTIPSELL_EXTIPSEL3_PORTA << 12) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 780 | #define GPIO_EXTIPSELL_EXTIPSEL3_PORTB (_GPIO_EXTIPSELL_EXTIPSEL3_PORTB << 12) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 781 | #define GPIO_EXTIPSELL_EXTIPSEL3_PORTC (_GPIO_EXTIPSELL_EXTIPSEL3_PORTC << 12) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 782 | #define GPIO_EXTIPSELL_EXTIPSEL3_PORTD (_GPIO_EXTIPSELL_EXTIPSEL3_PORTD << 12) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 783 | #define GPIO_EXTIPSELL_EXTIPSEL3_PORTE (_GPIO_EXTIPSELL_EXTIPSEL3_PORTE << 12) /**< Shifted mode PORTE for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 784 | #define GPIO_EXTIPSELL_EXTIPSEL3_PORTF (_GPIO_EXTIPSELL_EXTIPSEL3_PORTF << 12) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 785 | #define _GPIO_EXTIPSELL_EXTIPSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPSEL4 */ |
| <> | 150:02e0a0aed4ec | 786 | #define _GPIO_EXTIPSELL_EXTIPSEL4_MASK 0x70000UL /**< Bit mask for GPIO_EXTIPSEL4 */ |
| <> | 150:02e0a0aed4ec | 787 | #define _GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 788 | #define _GPIO_EXTIPSELL_EXTIPSEL4_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 789 | #define _GPIO_EXTIPSELL_EXTIPSEL4_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 790 | #define _GPIO_EXTIPSELL_EXTIPSEL4_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 791 | #define _GPIO_EXTIPSELL_EXTIPSEL4_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 792 | #define _GPIO_EXTIPSELL_EXTIPSEL4_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 793 | #define _GPIO_EXTIPSELL_EXTIPSEL4_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 794 | #define GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 795 | #define GPIO_EXTIPSELL_EXTIPSEL4_PORTA (_GPIO_EXTIPSELL_EXTIPSEL4_PORTA << 16) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 796 | #define GPIO_EXTIPSELL_EXTIPSEL4_PORTB (_GPIO_EXTIPSELL_EXTIPSEL4_PORTB << 16) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 797 | #define GPIO_EXTIPSELL_EXTIPSEL4_PORTC (_GPIO_EXTIPSELL_EXTIPSEL4_PORTC << 16) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 798 | #define GPIO_EXTIPSELL_EXTIPSEL4_PORTD (_GPIO_EXTIPSELL_EXTIPSEL4_PORTD << 16) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 799 | #define GPIO_EXTIPSELL_EXTIPSEL4_PORTE (_GPIO_EXTIPSELL_EXTIPSEL4_PORTE << 16) /**< Shifted mode PORTE for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 800 | #define GPIO_EXTIPSELL_EXTIPSEL4_PORTF (_GPIO_EXTIPSELL_EXTIPSEL4_PORTF << 16) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 801 | #define _GPIO_EXTIPSELL_EXTIPSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPSEL5 */ |
| <> | 150:02e0a0aed4ec | 802 | #define _GPIO_EXTIPSELL_EXTIPSEL5_MASK 0x700000UL /**< Bit mask for GPIO_EXTIPSEL5 */ |
| <> | 150:02e0a0aed4ec | 803 | #define _GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 804 | #define _GPIO_EXTIPSELL_EXTIPSEL5_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 805 | #define _GPIO_EXTIPSELL_EXTIPSEL5_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 806 | #define _GPIO_EXTIPSELL_EXTIPSEL5_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 807 | #define _GPIO_EXTIPSELL_EXTIPSEL5_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 808 | #define _GPIO_EXTIPSELL_EXTIPSEL5_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 809 | #define _GPIO_EXTIPSELL_EXTIPSEL5_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 810 | #define GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 811 | #define GPIO_EXTIPSELL_EXTIPSEL5_PORTA (_GPIO_EXTIPSELL_EXTIPSEL5_PORTA << 20) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 812 | #define GPIO_EXTIPSELL_EXTIPSEL5_PORTB (_GPIO_EXTIPSELL_EXTIPSEL5_PORTB << 20) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 813 | #define GPIO_EXTIPSELL_EXTIPSEL5_PORTC (_GPIO_EXTIPSELL_EXTIPSEL5_PORTC << 20) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 814 | #define GPIO_EXTIPSELL_EXTIPSEL5_PORTD (_GPIO_EXTIPSELL_EXTIPSEL5_PORTD << 20) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 815 | #define GPIO_EXTIPSELL_EXTIPSEL5_PORTE (_GPIO_EXTIPSELL_EXTIPSEL5_PORTE << 20) /**< Shifted mode PORTE for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 816 | #define GPIO_EXTIPSELL_EXTIPSEL5_PORTF (_GPIO_EXTIPSELL_EXTIPSEL5_PORTF << 20) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 817 | #define _GPIO_EXTIPSELL_EXTIPSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPSEL6 */ |
| <> | 150:02e0a0aed4ec | 818 | #define _GPIO_EXTIPSELL_EXTIPSEL6_MASK 0x7000000UL /**< Bit mask for GPIO_EXTIPSEL6 */ |
| <> | 150:02e0a0aed4ec | 819 | #define _GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 820 | #define _GPIO_EXTIPSELL_EXTIPSEL6_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 821 | #define _GPIO_EXTIPSELL_EXTIPSEL6_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 822 | #define _GPIO_EXTIPSELL_EXTIPSEL6_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 823 | #define _GPIO_EXTIPSELL_EXTIPSEL6_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 824 | #define _GPIO_EXTIPSELL_EXTIPSEL6_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 825 | #define _GPIO_EXTIPSELL_EXTIPSEL6_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 826 | #define GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 827 | #define GPIO_EXTIPSELL_EXTIPSEL6_PORTA (_GPIO_EXTIPSELL_EXTIPSEL6_PORTA << 24) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 828 | #define GPIO_EXTIPSELL_EXTIPSEL6_PORTB (_GPIO_EXTIPSELL_EXTIPSEL6_PORTB << 24) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 829 | #define GPIO_EXTIPSELL_EXTIPSEL6_PORTC (_GPIO_EXTIPSELL_EXTIPSEL6_PORTC << 24) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 830 | #define GPIO_EXTIPSELL_EXTIPSEL6_PORTD (_GPIO_EXTIPSELL_EXTIPSEL6_PORTD << 24) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 831 | #define GPIO_EXTIPSELL_EXTIPSEL6_PORTE (_GPIO_EXTIPSELL_EXTIPSEL6_PORTE << 24) /**< Shifted mode PORTE for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 832 | #define GPIO_EXTIPSELL_EXTIPSEL6_PORTF (_GPIO_EXTIPSELL_EXTIPSEL6_PORTF << 24) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 833 | #define _GPIO_EXTIPSELL_EXTIPSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPSEL7 */ |
| <> | 150:02e0a0aed4ec | 834 | #define _GPIO_EXTIPSELL_EXTIPSEL7_MASK 0x70000000UL /**< Bit mask for GPIO_EXTIPSEL7 */ |
| <> | 150:02e0a0aed4ec | 835 | #define _GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 836 | #define _GPIO_EXTIPSELL_EXTIPSEL7_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 837 | #define _GPIO_EXTIPSELL_EXTIPSEL7_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 838 | #define _GPIO_EXTIPSELL_EXTIPSEL7_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 839 | #define _GPIO_EXTIPSELL_EXTIPSEL7_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 840 | #define _GPIO_EXTIPSELL_EXTIPSEL7_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 841 | #define _GPIO_EXTIPSELL_EXTIPSEL7_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 842 | #define GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 843 | #define GPIO_EXTIPSELL_EXTIPSEL7_PORTA (_GPIO_EXTIPSELL_EXTIPSEL7_PORTA << 28) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 844 | #define GPIO_EXTIPSELL_EXTIPSEL7_PORTB (_GPIO_EXTIPSELL_EXTIPSEL7_PORTB << 28) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 845 | #define GPIO_EXTIPSELL_EXTIPSEL7_PORTC (_GPIO_EXTIPSELL_EXTIPSEL7_PORTC << 28) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 846 | #define GPIO_EXTIPSELL_EXTIPSEL7_PORTD (_GPIO_EXTIPSELL_EXTIPSEL7_PORTD << 28) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 847 | #define GPIO_EXTIPSELL_EXTIPSEL7_PORTE (_GPIO_EXTIPSELL_EXTIPSEL7_PORTE << 28) /**< Shifted mode PORTE for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 848 | #define GPIO_EXTIPSELL_EXTIPSEL7_PORTF (_GPIO_EXTIPSELL_EXTIPSEL7_PORTF << 28) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ |
| <> | 150:02e0a0aed4ec | 849 | |
| <> | 150:02e0a0aed4ec | 850 | /* Bit fields for GPIO EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 851 | #define _GPIO_EXTIPSELH_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 852 | #define _GPIO_EXTIPSELH_MASK 0x77777777UL /**< Mask for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 853 | #define _GPIO_EXTIPSELH_EXTIPSEL8_SHIFT 0 /**< Shift value for GPIO_EXTIPSEL8 */ |
| <> | 150:02e0a0aed4ec | 854 | #define _GPIO_EXTIPSELH_EXTIPSEL8_MASK 0x7UL /**< Bit mask for GPIO_EXTIPSEL8 */ |
| <> | 150:02e0a0aed4ec | 855 | #define _GPIO_EXTIPSELH_EXTIPSEL8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 856 | #define _GPIO_EXTIPSELH_EXTIPSEL8_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 857 | #define _GPIO_EXTIPSELH_EXTIPSEL8_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 858 | #define _GPIO_EXTIPSELH_EXTIPSEL8_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 859 | #define _GPIO_EXTIPSELH_EXTIPSEL8_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 860 | #define _GPIO_EXTIPSELH_EXTIPSEL8_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 861 | #define _GPIO_EXTIPSELH_EXTIPSEL8_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 862 | #define GPIO_EXTIPSELH_EXTIPSEL8_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL8_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 863 | #define GPIO_EXTIPSELH_EXTIPSEL8_PORTA (_GPIO_EXTIPSELH_EXTIPSEL8_PORTA << 0) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 864 | #define GPIO_EXTIPSELH_EXTIPSEL8_PORTB (_GPIO_EXTIPSELH_EXTIPSEL8_PORTB << 0) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 865 | #define GPIO_EXTIPSELH_EXTIPSEL8_PORTC (_GPIO_EXTIPSELH_EXTIPSEL8_PORTC << 0) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 866 | #define GPIO_EXTIPSELH_EXTIPSEL8_PORTD (_GPIO_EXTIPSELH_EXTIPSEL8_PORTD << 0) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 867 | #define GPIO_EXTIPSELH_EXTIPSEL8_PORTE (_GPIO_EXTIPSELH_EXTIPSEL8_PORTE << 0) /**< Shifted mode PORTE for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 868 | #define GPIO_EXTIPSELH_EXTIPSEL8_PORTF (_GPIO_EXTIPSELH_EXTIPSEL8_PORTF << 0) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 869 | #define _GPIO_EXTIPSELH_EXTIPSEL9_SHIFT 4 /**< Shift value for GPIO_EXTIPSEL9 */ |
| <> | 150:02e0a0aed4ec | 870 | #define _GPIO_EXTIPSELH_EXTIPSEL9_MASK 0x70UL /**< Bit mask for GPIO_EXTIPSEL9 */ |
| <> | 150:02e0a0aed4ec | 871 | #define _GPIO_EXTIPSELH_EXTIPSEL9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 872 | #define _GPIO_EXTIPSELH_EXTIPSEL9_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 873 | #define _GPIO_EXTIPSELH_EXTIPSEL9_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 874 | #define _GPIO_EXTIPSELH_EXTIPSEL9_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 875 | #define _GPIO_EXTIPSELH_EXTIPSEL9_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 876 | #define _GPIO_EXTIPSELH_EXTIPSEL9_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 877 | #define _GPIO_EXTIPSELH_EXTIPSEL9_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 878 | #define GPIO_EXTIPSELH_EXTIPSEL9_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL9_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 879 | #define GPIO_EXTIPSELH_EXTIPSEL9_PORTA (_GPIO_EXTIPSELH_EXTIPSEL9_PORTA << 4) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 880 | #define GPIO_EXTIPSELH_EXTIPSEL9_PORTB (_GPIO_EXTIPSELH_EXTIPSEL9_PORTB << 4) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 881 | #define GPIO_EXTIPSELH_EXTIPSEL9_PORTC (_GPIO_EXTIPSELH_EXTIPSEL9_PORTC << 4) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 882 | #define GPIO_EXTIPSELH_EXTIPSEL9_PORTD (_GPIO_EXTIPSELH_EXTIPSEL9_PORTD << 4) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 883 | #define GPIO_EXTIPSELH_EXTIPSEL9_PORTE (_GPIO_EXTIPSELH_EXTIPSEL9_PORTE << 4) /**< Shifted mode PORTE for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 884 | #define GPIO_EXTIPSELH_EXTIPSEL9_PORTF (_GPIO_EXTIPSELH_EXTIPSEL9_PORTF << 4) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 885 | #define _GPIO_EXTIPSELH_EXTIPSEL10_SHIFT 8 /**< Shift value for GPIO_EXTIPSEL10 */ |
| <> | 150:02e0a0aed4ec | 886 | #define _GPIO_EXTIPSELH_EXTIPSEL10_MASK 0x700UL /**< Bit mask for GPIO_EXTIPSEL10 */ |
| <> | 150:02e0a0aed4ec | 887 | #define _GPIO_EXTIPSELH_EXTIPSEL10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 888 | #define _GPIO_EXTIPSELH_EXTIPSEL10_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 889 | #define _GPIO_EXTIPSELH_EXTIPSEL10_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 890 | #define _GPIO_EXTIPSELH_EXTIPSEL10_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 891 | #define _GPIO_EXTIPSELH_EXTIPSEL10_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 892 | #define _GPIO_EXTIPSELH_EXTIPSEL10_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 893 | #define _GPIO_EXTIPSELH_EXTIPSEL10_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 894 | #define GPIO_EXTIPSELH_EXTIPSEL10_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL10_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 895 | #define GPIO_EXTIPSELH_EXTIPSEL10_PORTA (_GPIO_EXTIPSELH_EXTIPSEL10_PORTA << 8) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 896 | #define GPIO_EXTIPSELH_EXTIPSEL10_PORTB (_GPIO_EXTIPSELH_EXTIPSEL10_PORTB << 8) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 897 | #define GPIO_EXTIPSELH_EXTIPSEL10_PORTC (_GPIO_EXTIPSELH_EXTIPSEL10_PORTC << 8) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 898 | #define GPIO_EXTIPSELH_EXTIPSEL10_PORTD (_GPIO_EXTIPSELH_EXTIPSEL10_PORTD << 8) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 899 | #define GPIO_EXTIPSELH_EXTIPSEL10_PORTE (_GPIO_EXTIPSELH_EXTIPSEL10_PORTE << 8) /**< Shifted mode PORTE for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 900 | #define GPIO_EXTIPSELH_EXTIPSEL10_PORTF (_GPIO_EXTIPSELH_EXTIPSEL10_PORTF << 8) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 901 | #define _GPIO_EXTIPSELH_EXTIPSEL11_SHIFT 12 /**< Shift value for GPIO_EXTIPSEL11 */ |
| <> | 150:02e0a0aed4ec | 902 | #define _GPIO_EXTIPSELH_EXTIPSEL11_MASK 0x7000UL /**< Bit mask for GPIO_EXTIPSEL11 */ |
| <> | 150:02e0a0aed4ec | 903 | #define _GPIO_EXTIPSELH_EXTIPSEL11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 904 | #define _GPIO_EXTIPSELH_EXTIPSEL11_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 905 | #define _GPIO_EXTIPSELH_EXTIPSEL11_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 906 | #define _GPIO_EXTIPSELH_EXTIPSEL11_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 907 | #define _GPIO_EXTIPSELH_EXTIPSEL11_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 908 | #define _GPIO_EXTIPSELH_EXTIPSEL11_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 909 | #define _GPIO_EXTIPSELH_EXTIPSEL11_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 910 | #define GPIO_EXTIPSELH_EXTIPSEL11_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL11_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 911 | #define GPIO_EXTIPSELH_EXTIPSEL11_PORTA (_GPIO_EXTIPSELH_EXTIPSEL11_PORTA << 12) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 912 | #define GPIO_EXTIPSELH_EXTIPSEL11_PORTB (_GPIO_EXTIPSELH_EXTIPSEL11_PORTB << 12) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 913 | #define GPIO_EXTIPSELH_EXTIPSEL11_PORTC (_GPIO_EXTIPSELH_EXTIPSEL11_PORTC << 12) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 914 | #define GPIO_EXTIPSELH_EXTIPSEL11_PORTD (_GPIO_EXTIPSELH_EXTIPSEL11_PORTD << 12) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 915 | #define GPIO_EXTIPSELH_EXTIPSEL11_PORTE (_GPIO_EXTIPSELH_EXTIPSEL11_PORTE << 12) /**< Shifted mode PORTE for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 916 | #define GPIO_EXTIPSELH_EXTIPSEL11_PORTF (_GPIO_EXTIPSELH_EXTIPSEL11_PORTF << 12) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 917 | #define _GPIO_EXTIPSELH_EXTIPSEL12_SHIFT 16 /**< Shift value for GPIO_EXTIPSEL12 */ |
| <> | 150:02e0a0aed4ec | 918 | #define _GPIO_EXTIPSELH_EXTIPSEL12_MASK 0x70000UL /**< Bit mask for GPIO_EXTIPSEL12 */ |
| <> | 150:02e0a0aed4ec | 919 | #define _GPIO_EXTIPSELH_EXTIPSEL12_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 920 | #define _GPIO_EXTIPSELH_EXTIPSEL12_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 921 | #define _GPIO_EXTIPSELH_EXTIPSEL12_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 922 | #define _GPIO_EXTIPSELH_EXTIPSEL12_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 923 | #define _GPIO_EXTIPSELH_EXTIPSEL12_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 924 | #define _GPIO_EXTIPSELH_EXTIPSEL12_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 925 | #define _GPIO_EXTIPSELH_EXTIPSEL12_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 926 | #define GPIO_EXTIPSELH_EXTIPSEL12_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL12_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 927 | #define GPIO_EXTIPSELH_EXTIPSEL12_PORTA (_GPIO_EXTIPSELH_EXTIPSEL12_PORTA << 16) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 928 | #define GPIO_EXTIPSELH_EXTIPSEL12_PORTB (_GPIO_EXTIPSELH_EXTIPSEL12_PORTB << 16) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 929 | #define GPIO_EXTIPSELH_EXTIPSEL12_PORTC (_GPIO_EXTIPSELH_EXTIPSEL12_PORTC << 16) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 930 | #define GPIO_EXTIPSELH_EXTIPSEL12_PORTD (_GPIO_EXTIPSELH_EXTIPSEL12_PORTD << 16) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 931 | #define GPIO_EXTIPSELH_EXTIPSEL12_PORTE (_GPIO_EXTIPSELH_EXTIPSEL12_PORTE << 16) /**< Shifted mode PORTE for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 932 | #define GPIO_EXTIPSELH_EXTIPSEL12_PORTF (_GPIO_EXTIPSELH_EXTIPSEL12_PORTF << 16) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 933 | #define _GPIO_EXTIPSELH_EXTIPSEL13_SHIFT 20 /**< Shift value for GPIO_EXTIPSEL13 */ |
| <> | 150:02e0a0aed4ec | 934 | #define _GPIO_EXTIPSELH_EXTIPSEL13_MASK 0x700000UL /**< Bit mask for GPIO_EXTIPSEL13 */ |
| <> | 150:02e0a0aed4ec | 935 | #define _GPIO_EXTIPSELH_EXTIPSEL13_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 936 | #define _GPIO_EXTIPSELH_EXTIPSEL13_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 937 | #define _GPIO_EXTIPSELH_EXTIPSEL13_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 938 | #define _GPIO_EXTIPSELH_EXTIPSEL13_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 939 | #define _GPIO_EXTIPSELH_EXTIPSEL13_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 940 | #define _GPIO_EXTIPSELH_EXTIPSEL13_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 941 | #define _GPIO_EXTIPSELH_EXTIPSEL13_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 942 | #define GPIO_EXTIPSELH_EXTIPSEL13_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL13_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 943 | #define GPIO_EXTIPSELH_EXTIPSEL13_PORTA (_GPIO_EXTIPSELH_EXTIPSEL13_PORTA << 20) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 944 | #define GPIO_EXTIPSELH_EXTIPSEL13_PORTB (_GPIO_EXTIPSELH_EXTIPSEL13_PORTB << 20) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 945 | #define GPIO_EXTIPSELH_EXTIPSEL13_PORTC (_GPIO_EXTIPSELH_EXTIPSEL13_PORTC << 20) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 946 | #define GPIO_EXTIPSELH_EXTIPSEL13_PORTD (_GPIO_EXTIPSELH_EXTIPSEL13_PORTD << 20) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 947 | #define GPIO_EXTIPSELH_EXTIPSEL13_PORTE (_GPIO_EXTIPSELH_EXTIPSEL13_PORTE << 20) /**< Shifted mode PORTE for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 948 | #define GPIO_EXTIPSELH_EXTIPSEL13_PORTF (_GPIO_EXTIPSELH_EXTIPSEL13_PORTF << 20) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 949 | #define _GPIO_EXTIPSELH_EXTIPSEL14_SHIFT 24 /**< Shift value for GPIO_EXTIPSEL14 */ |
| <> | 150:02e0a0aed4ec | 950 | #define _GPIO_EXTIPSELH_EXTIPSEL14_MASK 0x7000000UL /**< Bit mask for GPIO_EXTIPSEL14 */ |
| <> | 150:02e0a0aed4ec | 951 | #define _GPIO_EXTIPSELH_EXTIPSEL14_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 952 | #define _GPIO_EXTIPSELH_EXTIPSEL14_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 953 | #define _GPIO_EXTIPSELH_EXTIPSEL14_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 954 | #define _GPIO_EXTIPSELH_EXTIPSEL14_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 955 | #define _GPIO_EXTIPSELH_EXTIPSEL14_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 956 | #define _GPIO_EXTIPSELH_EXTIPSEL14_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 957 | #define _GPIO_EXTIPSELH_EXTIPSEL14_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 958 | #define GPIO_EXTIPSELH_EXTIPSEL14_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL14_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 959 | #define GPIO_EXTIPSELH_EXTIPSEL14_PORTA (_GPIO_EXTIPSELH_EXTIPSEL14_PORTA << 24) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 960 | #define GPIO_EXTIPSELH_EXTIPSEL14_PORTB (_GPIO_EXTIPSELH_EXTIPSEL14_PORTB << 24) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 961 | #define GPIO_EXTIPSELH_EXTIPSEL14_PORTC (_GPIO_EXTIPSELH_EXTIPSEL14_PORTC << 24) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 962 | #define GPIO_EXTIPSELH_EXTIPSEL14_PORTD (_GPIO_EXTIPSELH_EXTIPSEL14_PORTD << 24) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 963 | #define GPIO_EXTIPSELH_EXTIPSEL14_PORTE (_GPIO_EXTIPSELH_EXTIPSEL14_PORTE << 24) /**< Shifted mode PORTE for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 964 | #define GPIO_EXTIPSELH_EXTIPSEL14_PORTF (_GPIO_EXTIPSELH_EXTIPSEL14_PORTF << 24) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 965 | #define _GPIO_EXTIPSELH_EXTIPSEL15_SHIFT 28 /**< Shift value for GPIO_EXTIPSEL15 */ |
| <> | 150:02e0a0aed4ec | 966 | #define _GPIO_EXTIPSELH_EXTIPSEL15_MASK 0x70000000UL /**< Bit mask for GPIO_EXTIPSEL15 */ |
| <> | 150:02e0a0aed4ec | 967 | #define _GPIO_EXTIPSELH_EXTIPSEL15_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 968 | #define _GPIO_EXTIPSELH_EXTIPSEL15_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 969 | #define _GPIO_EXTIPSELH_EXTIPSEL15_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 970 | #define _GPIO_EXTIPSELH_EXTIPSEL15_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 971 | #define _GPIO_EXTIPSELH_EXTIPSEL15_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 972 | #define _GPIO_EXTIPSELH_EXTIPSEL15_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 973 | #define _GPIO_EXTIPSELH_EXTIPSEL15_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 974 | #define GPIO_EXTIPSELH_EXTIPSEL15_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL15_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 975 | #define GPIO_EXTIPSELH_EXTIPSEL15_PORTA (_GPIO_EXTIPSELH_EXTIPSEL15_PORTA << 28) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 976 | #define GPIO_EXTIPSELH_EXTIPSEL15_PORTB (_GPIO_EXTIPSELH_EXTIPSEL15_PORTB << 28) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 977 | #define GPIO_EXTIPSELH_EXTIPSEL15_PORTC (_GPIO_EXTIPSELH_EXTIPSEL15_PORTC << 28) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 978 | #define GPIO_EXTIPSELH_EXTIPSEL15_PORTD (_GPIO_EXTIPSELH_EXTIPSEL15_PORTD << 28) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 979 | #define GPIO_EXTIPSELH_EXTIPSEL15_PORTE (_GPIO_EXTIPSELH_EXTIPSEL15_PORTE << 28) /**< Shifted mode PORTE for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 980 | #define GPIO_EXTIPSELH_EXTIPSEL15_PORTF (_GPIO_EXTIPSELH_EXTIPSEL15_PORTF << 28) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ |
| <> | 150:02e0a0aed4ec | 981 | |
| <> | 150:02e0a0aed4ec | 982 | /* Bit fields for GPIO EXTIRISE */ |
| <> | 150:02e0a0aed4ec | 983 | #define _GPIO_EXTIRISE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIRISE */ |
| <> | 150:02e0a0aed4ec | 984 | #define _GPIO_EXTIRISE_MASK 0x0000FFFFUL /**< Mask for GPIO_EXTIRISE */ |
| <> | 150:02e0a0aed4ec | 985 | #define _GPIO_EXTIRISE_EXTIRISE_SHIFT 0 /**< Shift value for GPIO_EXTIRISE */ |
| <> | 150:02e0a0aed4ec | 986 | #define _GPIO_EXTIRISE_EXTIRISE_MASK 0xFFFFUL /**< Bit mask for GPIO_EXTIRISE */ |
| <> | 150:02e0a0aed4ec | 987 | #define _GPIO_EXTIRISE_EXTIRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIRISE */ |
| <> | 150:02e0a0aed4ec | 988 | #define GPIO_EXTIRISE_EXTIRISE_DEFAULT (_GPIO_EXTIRISE_EXTIRISE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIRISE */ |
| <> | 150:02e0a0aed4ec | 989 | |
| <> | 150:02e0a0aed4ec | 990 | /* Bit fields for GPIO EXTIFALL */ |
| <> | 150:02e0a0aed4ec | 991 | #define _GPIO_EXTIFALL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIFALL */ |
| <> | 150:02e0a0aed4ec | 992 | #define _GPIO_EXTIFALL_MASK 0x0000FFFFUL /**< Mask for GPIO_EXTIFALL */ |
| <> | 150:02e0a0aed4ec | 993 | #define _GPIO_EXTIFALL_EXTIFALL_SHIFT 0 /**< Shift value for GPIO_EXTIFALL */ |
| <> | 150:02e0a0aed4ec | 994 | #define _GPIO_EXTIFALL_EXTIFALL_MASK 0xFFFFUL /**< Bit mask for GPIO_EXTIFALL */ |
| <> | 150:02e0a0aed4ec | 995 | #define _GPIO_EXTIFALL_EXTIFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIFALL */ |
| <> | 150:02e0a0aed4ec | 996 | #define GPIO_EXTIFALL_EXTIFALL_DEFAULT (_GPIO_EXTIFALL_EXTIFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIFALL */ |
| <> | 150:02e0a0aed4ec | 997 | |
| <> | 150:02e0a0aed4ec | 998 | /* Bit fields for GPIO IEN */ |
| <> | 150:02e0a0aed4ec | 999 | #define _GPIO_IEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_IEN */ |
| <> | 150:02e0a0aed4ec | 1000 | #define _GPIO_IEN_MASK 0x0000FFFFUL /**< Mask for GPIO_IEN */ |
| <> | 150:02e0a0aed4ec | 1001 | #define _GPIO_IEN_EXT_SHIFT 0 /**< Shift value for GPIO_EXT */ |
| <> | 150:02e0a0aed4ec | 1002 | #define _GPIO_IEN_EXT_MASK 0xFFFFUL /**< Bit mask for GPIO_EXT */ |
| <> | 150:02e0a0aed4ec | 1003 | #define _GPIO_IEN_EXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ |
| <> | 150:02e0a0aed4ec | 1004 | #define GPIO_IEN_EXT_DEFAULT (_GPIO_IEN_EXT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IEN */ |
| <> | 150:02e0a0aed4ec | 1005 | |
| <> | 150:02e0a0aed4ec | 1006 | /* Bit fields for GPIO IF */ |
| <> | 150:02e0a0aed4ec | 1007 | #define _GPIO_IF_RESETVALUE 0x00000000UL /**< Default value for GPIO_IF */ |
| <> | 150:02e0a0aed4ec | 1008 | #define _GPIO_IF_MASK 0x0000FFFFUL /**< Mask for GPIO_IF */ |
| <> | 150:02e0a0aed4ec | 1009 | #define _GPIO_IF_EXT_SHIFT 0 /**< Shift value for GPIO_EXT */ |
| <> | 150:02e0a0aed4ec | 1010 | #define _GPIO_IF_EXT_MASK 0xFFFFUL /**< Bit mask for GPIO_EXT */ |
| <> | 150:02e0a0aed4ec | 1011 | #define _GPIO_IF_EXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ |
| <> | 150:02e0a0aed4ec | 1012 | #define GPIO_IF_EXT_DEFAULT (_GPIO_IF_EXT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IF */ |
| <> | 150:02e0a0aed4ec | 1013 | |
| <> | 150:02e0a0aed4ec | 1014 | /* Bit fields for GPIO IFS */ |
| <> | 150:02e0a0aed4ec | 1015 | #define _GPIO_IFS_RESETVALUE 0x00000000UL /**< Default value for GPIO_IFS */ |
| <> | 150:02e0a0aed4ec | 1016 | #define _GPIO_IFS_MASK 0x0000FFFFUL /**< Mask for GPIO_IFS */ |
| <> | 150:02e0a0aed4ec | 1017 | #define _GPIO_IFS_EXT_SHIFT 0 /**< Shift value for GPIO_EXT */ |
| <> | 150:02e0a0aed4ec | 1018 | #define _GPIO_IFS_EXT_MASK 0xFFFFUL /**< Bit mask for GPIO_EXT */ |
| <> | 150:02e0a0aed4ec | 1019 | #define _GPIO_IFS_EXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IFS */ |
| <> | 150:02e0a0aed4ec | 1020 | #define GPIO_IFS_EXT_DEFAULT (_GPIO_IFS_EXT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IFS */ |
| <> | 150:02e0a0aed4ec | 1021 | |
| <> | 150:02e0a0aed4ec | 1022 | /* Bit fields for GPIO IFC */ |
| <> | 150:02e0a0aed4ec | 1023 | #define _GPIO_IFC_RESETVALUE 0x00000000UL /**< Default value for GPIO_IFC */ |
| <> | 150:02e0a0aed4ec | 1024 | #define _GPIO_IFC_MASK 0x0000FFFFUL /**< Mask for GPIO_IFC */ |
| <> | 150:02e0a0aed4ec | 1025 | #define _GPIO_IFC_EXT_SHIFT 0 /**< Shift value for GPIO_EXT */ |
| <> | 150:02e0a0aed4ec | 1026 | #define _GPIO_IFC_EXT_MASK 0xFFFFUL /**< Bit mask for GPIO_EXT */ |
| <> | 150:02e0a0aed4ec | 1027 | #define _GPIO_IFC_EXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IFC */ |
| <> | 150:02e0a0aed4ec | 1028 | #define GPIO_IFC_EXT_DEFAULT (_GPIO_IFC_EXT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IFC */ |
| <> | 150:02e0a0aed4ec | 1029 | |
| <> | 150:02e0a0aed4ec | 1030 | /* Bit fields for GPIO ROUTE */ |
| <> | 150:02e0a0aed4ec | 1031 | #define _GPIO_ROUTE_RESETVALUE 0x00000003UL /**< Default value for GPIO_ROUTE */ |
| <> | 150:02e0a0aed4ec | 1032 | #define _GPIO_ROUTE_MASK 0x0301F307UL /**< Mask for GPIO_ROUTE */ |
| <> | 150:02e0a0aed4ec | 1033 | #define GPIO_ROUTE_SWCLKPEN (0x1UL << 0) /**< Serial Wire Clock Pin Enable */ |
| <> | 150:02e0a0aed4ec | 1034 | #define _GPIO_ROUTE_SWCLKPEN_SHIFT 0 /**< Shift value for GPIO_SWCLKPEN */ |
| <> | 150:02e0a0aed4ec | 1035 | #define _GPIO_ROUTE_SWCLKPEN_MASK 0x1UL /**< Bit mask for GPIO_SWCLKPEN */ |
| <> | 150:02e0a0aed4ec | 1036 | #define _GPIO_ROUTE_SWCLKPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_ROUTE */ |
| <> | 150:02e0a0aed4ec | 1037 | #define GPIO_ROUTE_SWCLKPEN_DEFAULT (_GPIO_ROUTE_SWCLKPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ROUTE */ |
| <> | 150:02e0a0aed4ec | 1038 | #define GPIO_ROUTE_SWDIOPEN (0x1UL << 1) /**< Serial Wire Data Pin Enable */ |
| <> | 150:02e0a0aed4ec | 1039 | #define _GPIO_ROUTE_SWDIOPEN_SHIFT 1 /**< Shift value for GPIO_SWDIOPEN */ |
| <> | 150:02e0a0aed4ec | 1040 | #define _GPIO_ROUTE_SWDIOPEN_MASK 0x2UL /**< Bit mask for GPIO_SWDIOPEN */ |
| <> | 150:02e0a0aed4ec | 1041 | #define _GPIO_ROUTE_SWDIOPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_ROUTE */ |
| <> | 150:02e0a0aed4ec | 1042 | #define GPIO_ROUTE_SWDIOPEN_DEFAULT (_GPIO_ROUTE_SWDIOPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_ROUTE */ |
| <> | 150:02e0a0aed4ec | 1043 | #define GPIO_ROUTE_SWOPEN (0x1UL << 2) /**< Serial Wire Viewer Output Pin Enable */ |
| <> | 150:02e0a0aed4ec | 1044 | #define _GPIO_ROUTE_SWOPEN_SHIFT 2 /**< Shift value for GPIO_SWOPEN */ |
| <> | 150:02e0a0aed4ec | 1045 | #define _GPIO_ROUTE_SWOPEN_MASK 0x4UL /**< Bit mask for GPIO_SWOPEN */ |
| <> | 150:02e0a0aed4ec | 1046 | #define _GPIO_ROUTE_SWOPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTE */ |
| <> | 150:02e0a0aed4ec | 1047 | #define GPIO_ROUTE_SWOPEN_DEFAULT (_GPIO_ROUTE_SWOPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_ROUTE */ |
| <> | 150:02e0a0aed4ec | 1048 | #define _GPIO_ROUTE_SWLOCATION_SHIFT 8 /**< Shift value for GPIO_SWLOCATION */ |
| <> | 150:02e0a0aed4ec | 1049 | #define _GPIO_ROUTE_SWLOCATION_MASK 0x300UL /**< Bit mask for GPIO_SWLOCATION */ |
| <> | 150:02e0a0aed4ec | 1050 | #define _GPIO_ROUTE_SWLOCATION_LOC0 0x00000000UL /**< Mode LOC0 for GPIO_ROUTE */ |
| <> | 150:02e0a0aed4ec | 1051 | #define _GPIO_ROUTE_SWLOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTE */ |
| <> | 150:02e0a0aed4ec | 1052 | #define _GPIO_ROUTE_SWLOCATION_LOC1 0x00000001UL /**< Mode LOC1 for GPIO_ROUTE */ |
| <> | 150:02e0a0aed4ec | 1053 | #define _GPIO_ROUTE_SWLOCATION_LOC2 0x00000002UL /**< Mode LOC2 for GPIO_ROUTE */ |
| <> | 150:02e0a0aed4ec | 1054 | #define _GPIO_ROUTE_SWLOCATION_LOC3 0x00000003UL /**< Mode LOC3 for GPIO_ROUTE */ |
| <> | 150:02e0a0aed4ec | 1055 | #define GPIO_ROUTE_SWLOCATION_LOC0 (_GPIO_ROUTE_SWLOCATION_LOC0 << 8) /**< Shifted mode LOC0 for GPIO_ROUTE */ |
| <> | 150:02e0a0aed4ec | 1056 | #define GPIO_ROUTE_SWLOCATION_DEFAULT (_GPIO_ROUTE_SWLOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_ROUTE */ |
| <> | 150:02e0a0aed4ec | 1057 | #define GPIO_ROUTE_SWLOCATION_LOC1 (_GPIO_ROUTE_SWLOCATION_LOC1 << 8) /**< Shifted mode LOC1 for GPIO_ROUTE */ |
| <> | 150:02e0a0aed4ec | 1058 | #define GPIO_ROUTE_SWLOCATION_LOC2 (_GPIO_ROUTE_SWLOCATION_LOC2 << 8) /**< Shifted mode LOC2 for GPIO_ROUTE */ |
| <> | 150:02e0a0aed4ec | 1059 | #define GPIO_ROUTE_SWLOCATION_LOC3 (_GPIO_ROUTE_SWLOCATION_LOC3 << 8) /**< Shifted mode LOC3 for GPIO_ROUTE */ |
| <> | 150:02e0a0aed4ec | 1060 | #define GPIO_ROUTE_TCLKPEN (0x1UL << 12) /**< ETM Trace Clock Pin Enable */ |
| <> | 150:02e0a0aed4ec | 1061 | #define _GPIO_ROUTE_TCLKPEN_SHIFT 12 /**< Shift value for GPIO_TCLKPEN */ |
| <> | 150:02e0a0aed4ec | 1062 | #define _GPIO_ROUTE_TCLKPEN_MASK 0x1000UL /**< Bit mask for GPIO_TCLKPEN */ |
| <> | 150:02e0a0aed4ec | 1063 | #define _GPIO_ROUTE_TCLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTE */ |
| <> | 150:02e0a0aed4ec | 1064 | #define GPIO_ROUTE_TCLKPEN_DEFAULT (_GPIO_ROUTE_TCLKPEN_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_ROUTE */ |
| <> | 150:02e0a0aed4ec | 1065 | #define GPIO_ROUTE_TD0PEN (0x1UL << 13) /**< ETM Trace Data Pin Enable */ |
| <> | 150:02e0a0aed4ec | 1066 | #define _GPIO_ROUTE_TD0PEN_SHIFT 13 /**< Shift value for GPIO_TD0PEN */ |
| <> | 150:02e0a0aed4ec | 1067 | #define _GPIO_ROUTE_TD0PEN_MASK 0x2000UL /**< Bit mask for GPIO_TD0PEN */ |
| <> | 150:02e0a0aed4ec | 1068 | #define _GPIO_ROUTE_TD0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTE */ |
| <> | 150:02e0a0aed4ec | 1069 | #define GPIO_ROUTE_TD0PEN_DEFAULT (_GPIO_ROUTE_TD0PEN_DEFAULT << 13) /**< Shifted mode DEFAULT for GPIO_ROUTE */ |
| <> | 150:02e0a0aed4ec | 1070 | #define GPIO_ROUTE_TD1PEN (0x1UL << 14) /**< ETM Trace Data Pin Enable */ |
| <> | 150:02e0a0aed4ec | 1071 | #define _GPIO_ROUTE_TD1PEN_SHIFT 14 /**< Shift value for GPIO_TD1PEN */ |
| <> | 150:02e0a0aed4ec | 1072 | #define _GPIO_ROUTE_TD1PEN_MASK 0x4000UL /**< Bit mask for GPIO_TD1PEN */ |
| <> | 150:02e0a0aed4ec | 1073 | #define _GPIO_ROUTE_TD1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTE */ |
| <> | 150:02e0a0aed4ec | 1074 | #define GPIO_ROUTE_TD1PEN_DEFAULT (_GPIO_ROUTE_TD1PEN_DEFAULT << 14) /**< Shifted mode DEFAULT for GPIO_ROUTE */ |
| <> | 150:02e0a0aed4ec | 1075 | #define GPIO_ROUTE_TD2PEN (0x1UL << 15) /**< ETM Trace Data Pin Enable */ |
| <> | 150:02e0a0aed4ec | 1076 | #define _GPIO_ROUTE_TD2PEN_SHIFT 15 /**< Shift value for GPIO_TD2PEN */ |
| <> | 150:02e0a0aed4ec | 1077 | #define _GPIO_ROUTE_TD2PEN_MASK 0x8000UL /**< Bit mask for GPIO_TD2PEN */ |
| <> | 150:02e0a0aed4ec | 1078 | #define _GPIO_ROUTE_TD2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTE */ |
| <> | 150:02e0a0aed4ec | 1079 | #define GPIO_ROUTE_TD2PEN_DEFAULT (_GPIO_ROUTE_TD2PEN_DEFAULT << 15) /**< Shifted mode DEFAULT for GPIO_ROUTE */ |
| <> | 150:02e0a0aed4ec | 1080 | #define GPIO_ROUTE_TD3PEN (0x1UL << 16) /**< ETM Trace Data Pin Enable */ |
| <> | 150:02e0a0aed4ec | 1081 | #define _GPIO_ROUTE_TD3PEN_SHIFT 16 /**< Shift value for GPIO_TD3PEN */ |
| <> | 150:02e0a0aed4ec | 1082 | #define _GPIO_ROUTE_TD3PEN_MASK 0x10000UL /**< Bit mask for GPIO_TD3PEN */ |
| <> | 150:02e0a0aed4ec | 1083 | #define _GPIO_ROUTE_TD3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTE */ |
| <> | 150:02e0a0aed4ec | 1084 | #define GPIO_ROUTE_TD3PEN_DEFAULT (_GPIO_ROUTE_TD3PEN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_ROUTE */ |
| <> | 150:02e0a0aed4ec | 1085 | #define _GPIO_ROUTE_ETMLOCATION_SHIFT 24 /**< Shift value for GPIO_ETMLOCATION */ |
| <> | 150:02e0a0aed4ec | 1086 | #define _GPIO_ROUTE_ETMLOCATION_MASK 0x3000000UL /**< Bit mask for GPIO_ETMLOCATION */ |
| <> | 150:02e0a0aed4ec | 1087 | #define _GPIO_ROUTE_ETMLOCATION_LOC0 0x00000000UL /**< Mode LOC0 for GPIO_ROUTE */ |
| <> | 150:02e0a0aed4ec | 1088 | #define _GPIO_ROUTE_ETMLOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTE */ |
| <> | 150:02e0a0aed4ec | 1089 | #define _GPIO_ROUTE_ETMLOCATION_LOC1 0x00000001UL /**< Mode LOC1 for GPIO_ROUTE */ |
| <> | 150:02e0a0aed4ec | 1090 | #define _GPIO_ROUTE_ETMLOCATION_LOC2 0x00000002UL /**< Mode LOC2 for GPIO_ROUTE */ |
| <> | 150:02e0a0aed4ec | 1091 | #define _GPIO_ROUTE_ETMLOCATION_LOC3 0x00000003UL /**< Mode LOC3 for GPIO_ROUTE */ |
| <> | 150:02e0a0aed4ec | 1092 | #define GPIO_ROUTE_ETMLOCATION_LOC0 (_GPIO_ROUTE_ETMLOCATION_LOC0 << 24) /**< Shifted mode LOC0 for GPIO_ROUTE */ |
| <> | 150:02e0a0aed4ec | 1093 | #define GPIO_ROUTE_ETMLOCATION_DEFAULT (_GPIO_ROUTE_ETMLOCATION_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_ROUTE */ |
| <> | 150:02e0a0aed4ec | 1094 | #define GPIO_ROUTE_ETMLOCATION_LOC1 (_GPIO_ROUTE_ETMLOCATION_LOC1 << 24) /**< Shifted mode LOC1 for GPIO_ROUTE */ |
| <> | 150:02e0a0aed4ec | 1095 | #define GPIO_ROUTE_ETMLOCATION_LOC2 (_GPIO_ROUTE_ETMLOCATION_LOC2 << 24) /**< Shifted mode LOC2 for GPIO_ROUTE */ |
| <> | 150:02e0a0aed4ec | 1096 | #define GPIO_ROUTE_ETMLOCATION_LOC3 (_GPIO_ROUTE_ETMLOCATION_LOC3 << 24) /**< Shifted mode LOC3 for GPIO_ROUTE */ |
| <> | 150:02e0a0aed4ec | 1097 | |
| <> | 150:02e0a0aed4ec | 1098 | /* Bit fields for GPIO INSENSE */ |
| <> | 150:02e0a0aed4ec | 1099 | #define _GPIO_INSENSE_RESETVALUE 0x00000003UL /**< Default value for GPIO_INSENSE */ |
| <> | 150:02e0a0aed4ec | 1100 | #define _GPIO_INSENSE_MASK 0x00000003UL /**< Mask for GPIO_INSENSE */ |
| <> | 150:02e0a0aed4ec | 1101 | #define GPIO_INSENSE_INT (0x1UL << 0) /**< Interrupt Sense Enable */ |
| <> | 150:02e0a0aed4ec | 1102 | #define _GPIO_INSENSE_INT_SHIFT 0 /**< Shift value for GPIO_INT */ |
| <> | 150:02e0a0aed4ec | 1103 | #define _GPIO_INSENSE_INT_MASK 0x1UL /**< Bit mask for GPIO_INT */ |
| <> | 150:02e0a0aed4ec | 1104 | #define _GPIO_INSENSE_INT_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_INSENSE */ |
| <> | 150:02e0a0aed4ec | 1105 | #define GPIO_INSENSE_INT_DEFAULT (_GPIO_INSENSE_INT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_INSENSE */ |
| <> | 150:02e0a0aed4ec | 1106 | #define GPIO_INSENSE_PRS (0x1UL << 1) /**< PRS Sense Enable */ |
| <> | 150:02e0a0aed4ec | 1107 | #define _GPIO_INSENSE_PRS_SHIFT 1 /**< Shift value for GPIO_PRS */ |
| <> | 150:02e0a0aed4ec | 1108 | #define _GPIO_INSENSE_PRS_MASK 0x2UL /**< Bit mask for GPIO_PRS */ |
| <> | 150:02e0a0aed4ec | 1109 | #define _GPIO_INSENSE_PRS_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_INSENSE */ |
| <> | 150:02e0a0aed4ec | 1110 | #define GPIO_INSENSE_PRS_DEFAULT (_GPIO_INSENSE_PRS_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_INSENSE */ |
| <> | 150:02e0a0aed4ec | 1111 | |
| <> | 150:02e0a0aed4ec | 1112 | /* Bit fields for GPIO LOCK */ |
| <> | 150:02e0a0aed4ec | 1113 | #define _GPIO_LOCK_RESETVALUE 0x00000000UL /**< Default value for GPIO_LOCK */ |
| <> | 150:02e0a0aed4ec | 1114 | #define _GPIO_LOCK_MASK 0x0000FFFFUL /**< Mask for GPIO_LOCK */ |
| <> | 150:02e0a0aed4ec | 1115 | #define _GPIO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for GPIO_LOCKKEY */ |
| <> | 150:02e0a0aed4ec | 1116 | #define _GPIO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for GPIO_LOCKKEY */ |
| <> | 150:02e0a0aed4ec | 1117 | #define _GPIO_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LOCK */ |
| <> | 150:02e0a0aed4ec | 1118 | #define _GPIO_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for GPIO_LOCK */ |
| <> | 150:02e0a0aed4ec | 1119 | #define _GPIO_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for GPIO_LOCK */ |
| <> | 150:02e0a0aed4ec | 1120 | #define _GPIO_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for GPIO_LOCK */ |
| <> | 150:02e0a0aed4ec | 1121 | #define _GPIO_LOCK_LOCKKEY_UNLOCK 0x0000A534UL /**< Mode UNLOCK for GPIO_LOCK */ |
| <> | 150:02e0a0aed4ec | 1122 | #define GPIO_LOCK_LOCKKEY_DEFAULT (_GPIO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LOCK */ |
| <> | 150:02e0a0aed4ec | 1123 | #define GPIO_LOCK_LOCKKEY_LOCK (_GPIO_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for GPIO_LOCK */ |
| <> | 150:02e0a0aed4ec | 1124 | #define GPIO_LOCK_LOCKKEY_UNLOCKED (_GPIO_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for GPIO_LOCK */ |
| <> | 150:02e0a0aed4ec | 1125 | #define GPIO_LOCK_LOCKKEY_LOCKED (_GPIO_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for GPIO_LOCK */ |
| <> | 150:02e0a0aed4ec | 1126 | #define GPIO_LOCK_LOCKKEY_UNLOCK (_GPIO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for GPIO_LOCK */ |
| <> | 150:02e0a0aed4ec | 1127 | |
| <> | 150:02e0a0aed4ec | 1128 | /* Bit fields for GPIO CTRL */ |
| <> | 150:02e0a0aed4ec | 1129 | #define _GPIO_CTRL_RESETVALUE 0x00000000UL /**< Default value for GPIO_CTRL */ |
| <> | 150:02e0a0aed4ec | 1130 | #define _GPIO_CTRL_MASK 0x00000001UL /**< Mask for GPIO_CTRL */ |
| <> | 150:02e0a0aed4ec | 1131 | #define GPIO_CTRL_EM4RET (0x1UL << 0) /**< Enable EM4 retention */ |
| <> | 150:02e0a0aed4ec | 1132 | #define _GPIO_CTRL_EM4RET_SHIFT 0 /**< Shift value for GPIO_EM4RET */ |
| <> | 150:02e0a0aed4ec | 1133 | #define _GPIO_CTRL_EM4RET_MASK 0x1UL /**< Bit mask for GPIO_EM4RET */ |
| <> | 150:02e0a0aed4ec | 1134 | #define _GPIO_CTRL_EM4RET_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CTRL */ |
| <> | 150:02e0a0aed4ec | 1135 | #define GPIO_CTRL_EM4RET_DEFAULT (_GPIO_CTRL_EM4RET_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CTRL */ |
| <> | 150:02e0a0aed4ec | 1136 | |
| <> | 150:02e0a0aed4ec | 1137 | /* Bit fields for GPIO CMD */ |
| <> | 150:02e0a0aed4ec | 1138 | #define _GPIO_CMD_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMD */ |
| <> | 150:02e0a0aed4ec | 1139 | #define _GPIO_CMD_MASK 0x00000001UL /**< Mask for GPIO_CMD */ |
| <> | 150:02e0a0aed4ec | 1140 | #define GPIO_CMD_EM4WUCLR (0x1UL << 0) /**< EM4 Wake-up clear */ |
| <> | 150:02e0a0aed4ec | 1141 | #define _GPIO_CMD_EM4WUCLR_SHIFT 0 /**< Shift value for GPIO_EM4WUCLR */ |
| <> | 150:02e0a0aed4ec | 1142 | #define _GPIO_CMD_EM4WUCLR_MASK 0x1UL /**< Bit mask for GPIO_EM4WUCLR */ |
| <> | 150:02e0a0aed4ec | 1143 | #define _GPIO_CMD_EM4WUCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMD */ |
| <> | 150:02e0a0aed4ec | 1144 | #define GPIO_CMD_EM4WUCLR_DEFAULT (_GPIO_CMD_EM4WUCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMD */ |
| <> | 150:02e0a0aed4ec | 1145 | |
| <> | 150:02e0a0aed4ec | 1146 | /* Bit fields for GPIO EM4WUEN */ |
| <> | 150:02e0a0aed4ec | 1147 | #define _GPIO_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_EM4WUEN */ |
| <> | 150:02e0a0aed4ec | 1148 | #define _GPIO_EM4WUEN_MASK 0x0000003FUL /**< Mask for GPIO_EM4WUEN */ |
| <> | 150:02e0a0aed4ec | 1149 | #define _GPIO_EM4WUEN_EM4WUEN_SHIFT 0 /**< Shift value for GPIO_EM4WUEN */ |
| <> | 150:02e0a0aed4ec | 1150 | #define _GPIO_EM4WUEN_EM4WUEN_MASK 0x3FUL /**< Bit mask for GPIO_EM4WUEN */ |
| <> | 150:02e0a0aed4ec | 1151 | #define _GPIO_EM4WUEN_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EM4WUEN */ |
| <> | 150:02e0a0aed4ec | 1152 | #define _GPIO_EM4WUEN_EM4WUEN_A0 0x00000001UL /**< Mode A0 for GPIO_EM4WUEN */ |
| <> | 150:02e0a0aed4ec | 1153 | #define _GPIO_EM4WUEN_EM4WUEN_A6 0x00000002UL /**< Mode A6 for GPIO_EM4WUEN */ |
| <> | 150:02e0a0aed4ec | 1154 | #define _GPIO_EM4WUEN_EM4WUEN_C9 0x00000004UL /**< Mode C9 for GPIO_EM4WUEN */ |
| <> | 150:02e0a0aed4ec | 1155 | #define _GPIO_EM4WUEN_EM4WUEN_F1 0x00000008UL /**< Mode F1 for GPIO_EM4WUEN */ |
| <> | 150:02e0a0aed4ec | 1156 | #define _GPIO_EM4WUEN_EM4WUEN_F2 0x00000010UL /**< Mode F2 for GPIO_EM4WUEN */ |
| <> | 150:02e0a0aed4ec | 1157 | #define _GPIO_EM4WUEN_EM4WUEN_E13 0x00000020UL /**< Mode E13 for GPIO_EM4WUEN */ |
| <> | 150:02e0a0aed4ec | 1158 | #define GPIO_EM4WUEN_EM4WUEN_DEFAULT (_GPIO_EM4WUEN_EM4WUEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EM4WUEN */ |
| <> | 150:02e0a0aed4ec | 1159 | #define GPIO_EM4WUEN_EM4WUEN_A0 (_GPIO_EM4WUEN_EM4WUEN_A0 << 0) /**< Shifted mode A0 for GPIO_EM4WUEN */ |
| <> | 150:02e0a0aed4ec | 1160 | #define GPIO_EM4WUEN_EM4WUEN_A6 (_GPIO_EM4WUEN_EM4WUEN_A6 << 0) /**< Shifted mode A6 for GPIO_EM4WUEN */ |
| <> | 150:02e0a0aed4ec | 1161 | #define GPIO_EM4WUEN_EM4WUEN_C9 (_GPIO_EM4WUEN_EM4WUEN_C9 << 0) /**< Shifted mode C9 for GPIO_EM4WUEN */ |
| <> | 150:02e0a0aed4ec | 1162 | #define GPIO_EM4WUEN_EM4WUEN_F1 (_GPIO_EM4WUEN_EM4WUEN_F1 << 0) /**< Shifted mode F1 for GPIO_EM4WUEN */ |
| <> | 150:02e0a0aed4ec | 1163 | #define GPIO_EM4WUEN_EM4WUEN_F2 (_GPIO_EM4WUEN_EM4WUEN_F2 << 0) /**< Shifted mode F2 for GPIO_EM4WUEN */ |
| <> | 150:02e0a0aed4ec | 1164 | #define GPIO_EM4WUEN_EM4WUEN_E13 (_GPIO_EM4WUEN_EM4WUEN_E13 << 0) /**< Shifted mode E13 for GPIO_EM4WUEN */ |
| <> | 150:02e0a0aed4ec | 1165 | |
| <> | 150:02e0a0aed4ec | 1166 | /* Bit fields for GPIO EM4WUPOL */ |
| <> | 150:02e0a0aed4ec | 1167 | #define _GPIO_EM4WUPOL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EM4WUPOL */ |
| <> | 150:02e0a0aed4ec | 1168 | #define _GPIO_EM4WUPOL_MASK 0x0000003FUL /**< Mask for GPIO_EM4WUPOL */ |
| <> | 150:02e0a0aed4ec | 1169 | #define _GPIO_EM4WUPOL_EM4WUPOL_SHIFT 0 /**< Shift value for GPIO_EM4WUPOL */ |
| <> | 150:02e0a0aed4ec | 1170 | #define _GPIO_EM4WUPOL_EM4WUPOL_MASK 0x3FUL /**< Bit mask for GPIO_EM4WUPOL */ |
| <> | 150:02e0a0aed4ec | 1171 | #define _GPIO_EM4WUPOL_EM4WUPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EM4WUPOL */ |
| <> | 150:02e0a0aed4ec | 1172 | #define _GPIO_EM4WUPOL_EM4WUPOL_A0 0x00000001UL /**< Mode A0 for GPIO_EM4WUPOL */ |
| <> | 150:02e0a0aed4ec | 1173 | #define _GPIO_EM4WUPOL_EM4WUPOL_A6 0x00000002UL /**< Mode A6 for GPIO_EM4WUPOL */ |
| <> | 150:02e0a0aed4ec | 1174 | #define _GPIO_EM4WUPOL_EM4WUPOL_C9 0x00000004UL /**< Mode C9 for GPIO_EM4WUPOL */ |
| <> | 150:02e0a0aed4ec | 1175 | #define _GPIO_EM4WUPOL_EM4WUPOL_F1 0x00000008UL /**< Mode F1 for GPIO_EM4WUPOL */ |
| <> | 150:02e0a0aed4ec | 1176 | #define _GPIO_EM4WUPOL_EM4WUPOL_F2 0x00000010UL /**< Mode F2 for GPIO_EM4WUPOL */ |
| <> | 150:02e0a0aed4ec | 1177 | #define _GPIO_EM4WUPOL_EM4WUPOL_E13 0x00000020UL /**< Mode E13 for GPIO_EM4WUPOL */ |
| <> | 150:02e0a0aed4ec | 1178 | #define GPIO_EM4WUPOL_EM4WUPOL_DEFAULT (_GPIO_EM4WUPOL_EM4WUPOL_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EM4WUPOL */ |
| <> | 150:02e0a0aed4ec | 1179 | #define GPIO_EM4WUPOL_EM4WUPOL_A0 (_GPIO_EM4WUPOL_EM4WUPOL_A0 << 0) /**< Shifted mode A0 for GPIO_EM4WUPOL */ |
| <> | 150:02e0a0aed4ec | 1180 | #define GPIO_EM4WUPOL_EM4WUPOL_A6 (_GPIO_EM4WUPOL_EM4WUPOL_A6 << 0) /**< Shifted mode A6 for GPIO_EM4WUPOL */ |
| <> | 150:02e0a0aed4ec | 1181 | #define GPIO_EM4WUPOL_EM4WUPOL_C9 (_GPIO_EM4WUPOL_EM4WUPOL_C9 << 0) /**< Shifted mode C9 for GPIO_EM4WUPOL */ |
| <> | 150:02e0a0aed4ec | 1182 | #define GPIO_EM4WUPOL_EM4WUPOL_F1 (_GPIO_EM4WUPOL_EM4WUPOL_F1 << 0) /**< Shifted mode F1 for GPIO_EM4WUPOL */ |
| <> | 150:02e0a0aed4ec | 1183 | #define GPIO_EM4WUPOL_EM4WUPOL_F2 (_GPIO_EM4WUPOL_EM4WUPOL_F2 << 0) /**< Shifted mode F2 for GPIO_EM4WUPOL */ |
| <> | 150:02e0a0aed4ec | 1184 | #define GPIO_EM4WUPOL_EM4WUPOL_E13 (_GPIO_EM4WUPOL_EM4WUPOL_E13 << 0) /**< Shifted mode E13 for GPIO_EM4WUPOL */ |
| <> | 150:02e0a0aed4ec | 1185 | |
| <> | 150:02e0a0aed4ec | 1186 | /* Bit fields for GPIO EM4WUCAUSE */ |
| <> | 150:02e0a0aed4ec | 1187 | #define _GPIO_EM4WUCAUSE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EM4WUCAUSE */ |
| <> | 150:02e0a0aed4ec | 1188 | #define _GPIO_EM4WUCAUSE_MASK 0x0000003FUL /**< Mask for GPIO_EM4WUCAUSE */ |
| <> | 150:02e0a0aed4ec | 1189 | #define _GPIO_EM4WUCAUSE_EM4WUCAUSE_SHIFT 0 /**< Shift value for GPIO_EM4WUCAUSE */ |
| <> | 150:02e0a0aed4ec | 1190 | #define _GPIO_EM4WUCAUSE_EM4WUCAUSE_MASK 0x3FUL /**< Bit mask for GPIO_EM4WUCAUSE */ |
| <> | 150:02e0a0aed4ec | 1191 | #define _GPIO_EM4WUCAUSE_EM4WUCAUSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EM4WUCAUSE */ |
| <> | 150:02e0a0aed4ec | 1192 | #define _GPIO_EM4WUCAUSE_EM4WUCAUSE_A0 0x00000001UL /**< Mode A0 for GPIO_EM4WUCAUSE */ |
| <> | 150:02e0a0aed4ec | 1193 | #define _GPIO_EM4WUCAUSE_EM4WUCAUSE_A6 0x00000002UL /**< Mode A6 for GPIO_EM4WUCAUSE */ |
| <> | 150:02e0a0aed4ec | 1194 | #define _GPIO_EM4WUCAUSE_EM4WUCAUSE_C9 0x00000004UL /**< Mode C9 for GPIO_EM4WUCAUSE */ |
| <> | 150:02e0a0aed4ec | 1195 | #define _GPIO_EM4WUCAUSE_EM4WUCAUSE_F1 0x00000008UL /**< Mode F1 for GPIO_EM4WUCAUSE */ |
| <> | 150:02e0a0aed4ec | 1196 | #define _GPIO_EM4WUCAUSE_EM4WUCAUSE_F2 0x00000010UL /**< Mode F2 for GPIO_EM4WUCAUSE */ |
| <> | 150:02e0a0aed4ec | 1197 | #define _GPIO_EM4WUCAUSE_EM4WUCAUSE_E13 0x00000020UL /**< Mode E13 for GPIO_EM4WUCAUSE */ |
| <> | 150:02e0a0aed4ec | 1198 | #define GPIO_EM4WUCAUSE_EM4WUCAUSE_DEFAULT (_GPIO_EM4WUCAUSE_EM4WUCAUSE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EM4WUCAUSE */ |
| <> | 150:02e0a0aed4ec | 1199 | #define GPIO_EM4WUCAUSE_EM4WUCAUSE_A0 (_GPIO_EM4WUCAUSE_EM4WUCAUSE_A0 << 0) /**< Shifted mode A0 for GPIO_EM4WUCAUSE */ |
| <> | 150:02e0a0aed4ec | 1200 | #define GPIO_EM4WUCAUSE_EM4WUCAUSE_A6 (_GPIO_EM4WUCAUSE_EM4WUCAUSE_A6 << 0) /**< Shifted mode A6 for GPIO_EM4WUCAUSE */ |
| <> | 150:02e0a0aed4ec | 1201 | #define GPIO_EM4WUCAUSE_EM4WUCAUSE_C9 (_GPIO_EM4WUCAUSE_EM4WUCAUSE_C9 << 0) /**< Shifted mode C9 for GPIO_EM4WUCAUSE */ |
| <> | 150:02e0a0aed4ec | 1202 | #define GPIO_EM4WUCAUSE_EM4WUCAUSE_F1 (_GPIO_EM4WUCAUSE_EM4WUCAUSE_F1 << 0) /**< Shifted mode F1 for GPIO_EM4WUCAUSE */ |
| <> | 150:02e0a0aed4ec | 1203 | #define GPIO_EM4WUCAUSE_EM4WUCAUSE_F2 (_GPIO_EM4WUCAUSE_EM4WUCAUSE_F2 << 0) /**< Shifted mode F2 for GPIO_EM4WUCAUSE */ |
| <> | 150:02e0a0aed4ec | 1204 | #define GPIO_EM4WUCAUSE_EM4WUCAUSE_E13 (_GPIO_EM4WUCAUSE_EM4WUCAUSE_E13 << 0) /**< Shifted mode E13 for GPIO_EM4WUCAUSE */ |
| <> | 150:02e0a0aed4ec | 1205 | |
| <> | 150:02e0a0aed4ec | 1206 | /** @} End of group EFM32WG_GPIO */ |
| <> | 150:02e0a0aed4ec | 1207 | /** @} End of group Parts */ |
| <> | 150:02e0a0aed4ec | 1208 |