Fawwaz Nadzmy / mbed-STM

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_etm.h@153:9398a535854b, 2016-12-22 (annotated)

Committer:
fwndz
Date:
Thu Dec 22 05:12:40 2016 +0000
Revision:
153:9398a535854b
Parent:
150:02e0a0aed4ec 
device target maximize

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 150:02e0a0aed4ec 1 /**************************************************************************//**
<> 150:02e0a0aed4ec 2 * @file efm32wg_etm.h
<> 150:02e0a0aed4ec 3 * @brief EFM32WG_ETM register and bit field definitions
<> 150:02e0a0aed4ec 4 * @version 5.0.0
<> 150:02e0a0aed4ec 5 ******************************************************************************
<> 150:02e0a0aed4ec 6 * @section License
<> 150:02e0a0aed4ec 7 * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 150:02e0a0aed4ec 8 ******************************************************************************
<> 150:02e0a0aed4ec 9 *
<> 150:02e0a0aed4ec 10 * Permission is granted to anyone to use this software for any purpose,
<> 150:02e0a0aed4ec 11 * including commercial applications, and to alter it and redistribute it
<> 150:02e0a0aed4ec 12 * freely, subject to the following restrictions:
<> 150:02e0a0aed4ec 13 *
<> 150:02e0a0aed4ec 14 * 1. The origin of this software must not be misrepresented; you must not
<> 150:02e0a0aed4ec 15 * claim that you wrote the original software.@n
<> 150:02e0a0aed4ec 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 150:02e0a0aed4ec 17 * misrepresented as being the original software.@n
<> 150:02e0a0aed4ec 18 * 3. This notice may not be removed or altered from any source distribution.
<> 150:02e0a0aed4ec 19 *
<> 150:02e0a0aed4ec 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 150:02e0a0aed4ec 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 150:02e0a0aed4ec 22 * providing the Software "AS IS", with no express or implied warranties of any
<> 150:02e0a0aed4ec 23 * kind, including, but not limited to, any implied warranties of
<> 150:02e0a0aed4ec 24 * merchantability or fitness for any particular purpose or warranties against
<> 150:02e0a0aed4ec 25 * infringement of any proprietary rights of a third party.
<> 150:02e0a0aed4ec 26 *
<> 150:02e0a0aed4ec 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 150:02e0a0aed4ec 28 * incidental, or special damages, or any other relief, or for any claim by
<> 150:02e0a0aed4ec 29 * any third party, arising from your use of this Software.
<> 150:02e0a0aed4ec 30 *
<> 150:02e0a0aed4ec 31 *****************************************************************************/
<> 150:02e0a0aed4ec 32 /**************************************************************************//**
<> 150:02e0a0aed4ec 33 * @addtogroup Parts
<> 150:02e0a0aed4ec 34 * @{
<> 150:02e0a0aed4ec 35 ******************************************************************************/
<> 150:02e0a0aed4ec 36 /**************************************************************************//**
<> 150:02e0a0aed4ec 37 * @defgroup EFM32WG_ETM
<> 150:02e0a0aed4ec 38 * @{
<> 150:02e0a0aed4ec 39 * @brief EFM32WG_ETM Register Declaration
<> 150:02e0a0aed4ec 40 *****************************************************************************/
<> 150:02e0a0aed4ec 41 typedef struct
<> 150:02e0a0aed4ec 42 {
<> 150:02e0a0aed4ec 43 __IOM uint32_t ETMCR; /**< Main Control Register */
<> 150:02e0a0aed4ec 44 __IM uint32_t ETMCCR; /**< Configuration Code Register */
<> 150:02e0a0aed4ec 45 __IOM uint32_t ETMTRIGGER; /**< ETM Trigger Event Register */
<> 150:02e0a0aed4ec 46 uint32_t RESERVED0[1]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 47 __IOM uint32_t ETMSR; /**< ETM Status Register */
<> 150:02e0a0aed4ec 48 __IM uint32_t ETMSCR; /**< ETM System Configuration Register */
<> 150:02e0a0aed4ec 49 uint32_t RESERVED1[2]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 50 __IOM uint32_t ETMTEEVR; /**< ETM TraceEnable Event Register */
<> 150:02e0a0aed4ec 51 __IOM uint32_t ETMTECR1; /**< ETM Trace control Register */
<> 150:02e0a0aed4ec 52 uint32_t RESERVED2[1]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 53 __IOM uint32_t ETMFFLR; /**< ETM Fifo Full Level Register */
<> 150:02e0a0aed4ec 54 uint32_t RESERVED3[68]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 55 __IOM uint32_t ETMCNTRLDVR1; /**< Counter Reload Value */
<> 150:02e0a0aed4ec 56 uint32_t RESERVED4[39]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 57 __IOM uint32_t ETMSYNCFR; /**< Synchronisation Frequency Register */
<> 150:02e0a0aed4ec 58 __IM uint32_t ETMIDR; /**< ID Register */
<> 150:02e0a0aed4ec 59 __IM uint32_t ETMCCER; /**< Configuration Code Extension Register */
<> 150:02e0a0aed4ec 60 uint32_t RESERVED5[1]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 61 __IOM uint32_t ETMTESSEICR; /**< TraceEnable Start/Stop EmbeddedICE Control Register */
<> 150:02e0a0aed4ec 62 uint32_t RESERVED6[1]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 63 __IOM uint32_t ETMTSEVR; /**< Timestamp Event Register */
<> 150:02e0a0aed4ec 64 uint32_t RESERVED7[1]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 65 __IOM uint32_t ETMTRACEIDR; /**< CoreSight Trace ID Register */
<> 150:02e0a0aed4ec 66 uint32_t RESERVED8[1]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 67 __IM uint32_t ETMIDR2; /**< ETM ID Register 2 */
<> 150:02e0a0aed4ec 68 uint32_t RESERVED9[66]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 69 __IM uint32_t ETMPDSR; /**< Device Power-down Status Register */
<> 150:02e0a0aed4ec 70 uint32_t RESERVED10[754]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 71 __IOM uint32_t ETMISCIN; /**< Integration Test Miscellaneous Inputs Register */
<> 150:02e0a0aed4ec 72 uint32_t RESERVED11[1]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 73 __OM uint32_t ITTRIGOUT; /**< Integration Test Trigger Out Register */
<> 150:02e0a0aed4ec 74 uint32_t RESERVED12[1]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 75 __IM uint32_t ETMITATBCTR2; /**< ETM Integration Test ATB Control 2 Register */
<> 150:02e0a0aed4ec 76 uint32_t RESERVED13[1]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 77 __OM uint32_t ETMITATBCTR0; /**< ETM Integration Test ATB Control 0 Register */
<> 150:02e0a0aed4ec 78 uint32_t RESERVED14[1]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 79 __IOM uint32_t ETMITCTRL; /**< ETM Integration Control Register */
<> 150:02e0a0aed4ec 80 uint32_t RESERVED15[39]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 81 __IOM uint32_t ETMCLAIMSET; /**< ETM Claim Tag Set Register */
<> 150:02e0a0aed4ec 82 __IOM uint32_t ETMCLAIMCLR; /**< ETM Claim Tag Clear Register */
<> 150:02e0a0aed4ec 83 uint32_t RESERVED16[2]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 84 __IOM uint32_t ETMLAR; /**< ETM Lock Access Register */
<> 150:02e0a0aed4ec 85 __IM uint32_t ETMLSR; /**< Lock Status Register */
<> 150:02e0a0aed4ec 86 __IM uint32_t ETMAUTHSTATUS; /**< ETM Authentication Status Register */
<> 150:02e0a0aed4ec 87 uint32_t RESERVED17[4]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 88 __IM uint32_t ETMDEVTYPE; /**< CoreSight Device Type Register */
<> 150:02e0a0aed4ec 89 __IM uint32_t ETMPIDR4; /**< Peripheral ID4 Register */
<> 150:02e0a0aed4ec 90 __OM uint32_t ETMPIDR5; /**< Peripheral ID5 Register */
<> 150:02e0a0aed4ec 91 __OM uint32_t ETMPIDR6; /**< Peripheral ID6 Register */
<> 150:02e0a0aed4ec 92 __OM uint32_t ETMPIDR7; /**< Peripheral ID7 Register */
<> 150:02e0a0aed4ec 93 __IM uint32_t ETMPIDR0; /**< Peripheral ID0 Register */
<> 150:02e0a0aed4ec 94 __IM uint32_t ETMPIDR1; /**< Peripheral ID1 Register */
<> 150:02e0a0aed4ec 95 __IM uint32_t ETMPIDR2; /**< Peripheral ID2 Register */
<> 150:02e0a0aed4ec 96 __IM uint32_t ETMPIDR3; /**< Peripheral ID3 Register */
<> 150:02e0a0aed4ec 97 __IM uint32_t ETMCIDR0; /**< Component ID0 Register */
<> 150:02e0a0aed4ec 98 __IM uint32_t ETMCIDR1; /**< Component ID1 Register */
<> 150:02e0a0aed4ec 99 __IM uint32_t ETMCIDR2; /**< Component ID2 Register */
<> 150:02e0a0aed4ec 100 __IM uint32_t ETMCIDR3; /**< Component ID3 Register */
<> 150:02e0a0aed4ec 101 } ETM_TypeDef; /** @} */
<> 150:02e0a0aed4ec 102
<> 150:02e0a0aed4ec 103 /**************************************************************************//**
<> 150:02e0a0aed4ec 104 * @defgroup EFM32WG_ETM_BitFields
<> 150:02e0a0aed4ec 105 * @{
<> 150:02e0a0aed4ec 106 *****************************************************************************/
<> 150:02e0a0aed4ec 107
<> 150:02e0a0aed4ec 108 /* Bit fields for ETM ETMCR */
<> 150:02e0a0aed4ec 109 #define _ETM_ETMCR_RESETVALUE 0x00000411UL /**< Default value for ETM_ETMCR */
<> 150:02e0a0aed4ec 110 #define _ETM_ETMCR_MASK 0x10632FF1UL /**< Mask for ETM_ETMCR */
<> 150:02e0a0aed4ec 111 #define ETM_ETMCR_POWERDWN (0x1UL << 0) /**< ETM Control in low power mode */
<> 150:02e0a0aed4ec 112 #define _ETM_ETMCR_POWERDWN_SHIFT 0 /**< Shift value for ETM_POWERDWN */
<> 150:02e0a0aed4ec 113 #define _ETM_ETMCR_POWERDWN_MASK 0x1UL /**< Bit mask for ETM_POWERDWN */
<> 150:02e0a0aed4ec 114 #define _ETM_ETMCR_POWERDWN_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCR */
<> 150:02e0a0aed4ec 115 #define ETM_ETMCR_POWERDWN_DEFAULT (_ETM_ETMCR_POWERDWN_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCR */
<> 150:02e0a0aed4ec 116 #define _ETM_ETMCR_PORTSIZE_SHIFT 4 /**< Shift value for ETM_PORTSIZE */
<> 150:02e0a0aed4ec 117 #define _ETM_ETMCR_PORTSIZE_MASK 0x70UL /**< Bit mask for ETM_PORTSIZE */
<> 150:02e0a0aed4ec 118 #define _ETM_ETMCR_PORTSIZE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCR */
<> 150:02e0a0aed4ec 119 #define ETM_ETMCR_PORTSIZE_DEFAULT (_ETM_ETMCR_PORTSIZE_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMCR */
<> 150:02e0a0aed4ec 120 #define ETM_ETMCR_STALL (0x1UL << 7) /**< Stall Processor */
<> 150:02e0a0aed4ec 121 #define _ETM_ETMCR_STALL_SHIFT 7 /**< Shift value for ETM_STALL */
<> 150:02e0a0aed4ec 122 #define _ETM_ETMCR_STALL_MASK 0x80UL /**< Bit mask for ETM_STALL */
<> 150:02e0a0aed4ec 123 #define _ETM_ETMCR_STALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
<> 150:02e0a0aed4ec 124 #define ETM_ETMCR_STALL_DEFAULT (_ETM_ETMCR_STALL_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMCR */
<> 150:02e0a0aed4ec 125 #define ETM_ETMCR_BRANCHOUTPUT (0x1UL << 8) /**< Branch Output */
<> 150:02e0a0aed4ec 126 #define _ETM_ETMCR_BRANCHOUTPUT_SHIFT 8 /**< Shift value for ETM_BRANCHOUTPUT */
<> 150:02e0a0aed4ec 127 #define _ETM_ETMCR_BRANCHOUTPUT_MASK 0x100UL /**< Bit mask for ETM_BRANCHOUTPUT */
<> 150:02e0a0aed4ec 128 #define _ETM_ETMCR_BRANCHOUTPUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
<> 150:02e0a0aed4ec 129 #define ETM_ETMCR_BRANCHOUTPUT_DEFAULT (_ETM_ETMCR_BRANCHOUTPUT_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMCR */
<> 150:02e0a0aed4ec 130 #define ETM_ETMCR_DBGREQCTRL (0x1UL << 9) /**< Debug Request Control */
<> 150:02e0a0aed4ec 131 #define _ETM_ETMCR_DBGREQCTRL_SHIFT 9 /**< Shift value for ETM_DBGREQCTRL */
<> 150:02e0a0aed4ec 132 #define _ETM_ETMCR_DBGREQCTRL_MASK 0x200UL /**< Bit mask for ETM_DBGREQCTRL */
<> 150:02e0a0aed4ec 133 #define _ETM_ETMCR_DBGREQCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
<> 150:02e0a0aed4ec 134 #define ETM_ETMCR_DBGREQCTRL_DEFAULT (_ETM_ETMCR_DBGREQCTRL_DEFAULT << 9) /**< Shifted mode DEFAULT for ETM_ETMCR */
<> 150:02e0a0aed4ec 135 #define ETM_ETMCR_ETMPROG (0x1UL << 10) /**< ETM Programming */
<> 150:02e0a0aed4ec 136 #define _ETM_ETMCR_ETMPROG_SHIFT 10 /**< Shift value for ETM_ETMPROG */
<> 150:02e0a0aed4ec 137 #define _ETM_ETMCR_ETMPROG_MASK 0x400UL /**< Bit mask for ETM_ETMPROG */
<> 150:02e0a0aed4ec 138 #define _ETM_ETMCR_ETMPROG_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCR */
<> 150:02e0a0aed4ec 139 #define ETM_ETMCR_ETMPROG_DEFAULT (_ETM_ETMCR_ETMPROG_DEFAULT << 10) /**< Shifted mode DEFAULT for ETM_ETMCR */
<> 150:02e0a0aed4ec 140 #define ETM_ETMCR_ETMPORTSEL (0x1UL << 11) /**< ETM Port Selection */
<> 150:02e0a0aed4ec 141 #define _ETM_ETMCR_ETMPORTSEL_SHIFT 11 /**< Shift value for ETM_ETMPORTSEL */
<> 150:02e0a0aed4ec 142 #define _ETM_ETMCR_ETMPORTSEL_MASK 0x800UL /**< Bit mask for ETM_ETMPORTSEL */
<> 150:02e0a0aed4ec 143 #define _ETM_ETMCR_ETMPORTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
<> 150:02e0a0aed4ec 144 #define _ETM_ETMCR_ETMPORTSEL_ETMLOW 0x00000000UL /**< Mode ETMLOW for ETM_ETMCR */
<> 150:02e0a0aed4ec 145 #define _ETM_ETMCR_ETMPORTSEL_ETMHIGH 0x00000001UL /**< Mode ETMHIGH for ETM_ETMCR */
<> 150:02e0a0aed4ec 146 #define ETM_ETMCR_ETMPORTSEL_DEFAULT (_ETM_ETMCR_ETMPORTSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for ETM_ETMCR */
<> 150:02e0a0aed4ec 147 #define ETM_ETMCR_ETMPORTSEL_ETMLOW (_ETM_ETMCR_ETMPORTSEL_ETMLOW << 11) /**< Shifted mode ETMLOW for ETM_ETMCR */
<> 150:02e0a0aed4ec 148 #define ETM_ETMCR_ETMPORTSEL_ETMHIGH (_ETM_ETMCR_ETMPORTSEL_ETMHIGH << 11) /**< Shifted mode ETMHIGH for ETM_ETMCR */
<> 150:02e0a0aed4ec 149 #define ETM_ETMCR_PORTMODE2 (0x1UL << 13) /**< Port Mode[2] */
<> 150:02e0a0aed4ec 150 #define _ETM_ETMCR_PORTMODE2_SHIFT 13 /**< Shift value for ETM_PORTMODE2 */
<> 150:02e0a0aed4ec 151 #define _ETM_ETMCR_PORTMODE2_MASK 0x2000UL /**< Bit mask for ETM_PORTMODE2 */
<> 150:02e0a0aed4ec 152 #define _ETM_ETMCR_PORTMODE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
<> 150:02e0a0aed4ec 153 #define ETM_ETMCR_PORTMODE2_DEFAULT (_ETM_ETMCR_PORTMODE2_DEFAULT << 13) /**< Shifted mode DEFAULT for ETM_ETMCR */
<> 150:02e0a0aed4ec 154 #define _ETM_ETMCR_PORTMODE_SHIFT 16 /**< Shift value for ETM_PORTMODE */
<> 150:02e0a0aed4ec 155 #define _ETM_ETMCR_PORTMODE_MASK 0x30000UL /**< Bit mask for ETM_PORTMODE */
<> 150:02e0a0aed4ec 156 #define _ETM_ETMCR_PORTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
<> 150:02e0a0aed4ec 157 #define ETM_ETMCR_PORTMODE_DEFAULT (_ETM_ETMCR_PORTMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMCR */
<> 150:02e0a0aed4ec 158 #define _ETM_ETMCR_EPORTSIZE_SHIFT 21 /**< Shift value for ETM_EPORTSIZE */
<> 150:02e0a0aed4ec 159 #define _ETM_ETMCR_EPORTSIZE_MASK 0x600000UL /**< Bit mask for ETM_EPORTSIZE */
<> 150:02e0a0aed4ec 160 #define _ETM_ETMCR_EPORTSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
<> 150:02e0a0aed4ec 161 #define ETM_ETMCR_EPORTSIZE_DEFAULT (_ETM_ETMCR_EPORTSIZE_DEFAULT << 21) /**< Shifted mode DEFAULT for ETM_ETMCR */
<> 150:02e0a0aed4ec 162 #define ETM_ETMCR_TSTAMPEN (0x1UL << 28) /**< Time Stamp Enable */
<> 150:02e0a0aed4ec 163 #define _ETM_ETMCR_TSTAMPEN_SHIFT 28 /**< Shift value for ETM_TSTAMPEN */
<> 150:02e0a0aed4ec 164 #define _ETM_ETMCR_TSTAMPEN_MASK 0x10000000UL /**< Bit mask for ETM_TSTAMPEN */
<> 150:02e0a0aed4ec 165 #define _ETM_ETMCR_TSTAMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
<> 150:02e0a0aed4ec 166 #define ETM_ETMCR_TSTAMPEN_DEFAULT (_ETM_ETMCR_TSTAMPEN_DEFAULT << 28) /**< Shifted mode DEFAULT for ETM_ETMCR */
<> 150:02e0a0aed4ec 167
<> 150:02e0a0aed4ec 168 /* Bit fields for ETM ETMCCR */
<> 150:02e0a0aed4ec 169 #define _ETM_ETMCCR_RESETVALUE 0x8C802000UL /**< Default value for ETM_ETMCCR */
<> 150:02e0a0aed4ec 170 #define _ETM_ETMCCR_MASK 0x8FFFFFFFUL /**< Mask for ETM_ETMCCR */
<> 150:02e0a0aed4ec 171 #define _ETM_ETMCCR_ADRCMPPAIR_SHIFT 0 /**< Shift value for ETM_ADRCMPPAIR */
<> 150:02e0a0aed4ec 172 #define _ETM_ETMCCR_ADRCMPPAIR_MASK 0xFUL /**< Bit mask for ETM_ADRCMPPAIR */
<> 150:02e0a0aed4ec 173 #define _ETM_ETMCCR_ADRCMPPAIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
<> 150:02e0a0aed4ec 174 #define ETM_ETMCCR_ADRCMPPAIR_DEFAULT (_ETM_ETMCCR_ADRCMPPAIR_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCCR */
<> 150:02e0a0aed4ec 175 #define _ETM_ETMCCR_DATACMPNUM_SHIFT 4 /**< Shift value for ETM_DATACMPNUM */
<> 150:02e0a0aed4ec 176 #define _ETM_ETMCCR_DATACMPNUM_MASK 0xF0UL /**< Bit mask for ETM_DATACMPNUM */
<> 150:02e0a0aed4ec 177 #define _ETM_ETMCCR_DATACMPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
<> 150:02e0a0aed4ec 178 #define ETM_ETMCCR_DATACMPNUM_DEFAULT (_ETM_ETMCCR_DATACMPNUM_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMCCR */
<> 150:02e0a0aed4ec 179 #define _ETM_ETMCCR_MMDECCNT_SHIFT 8 /**< Shift value for ETM_MMDECCNT */
<> 150:02e0a0aed4ec 180 #define _ETM_ETMCCR_MMDECCNT_MASK 0x1F00UL /**< Bit mask for ETM_MMDECCNT */
<> 150:02e0a0aed4ec 181 #define _ETM_ETMCCR_MMDECCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
<> 150:02e0a0aed4ec 182 #define ETM_ETMCCR_MMDECCNT_DEFAULT (_ETM_ETMCCR_MMDECCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMCCR */
<> 150:02e0a0aed4ec 183 #define _ETM_ETMCCR_COUNTNUM_SHIFT 13 /**< Shift value for ETM_COUNTNUM */
<> 150:02e0a0aed4ec 184 #define _ETM_ETMCCR_COUNTNUM_MASK 0xE000UL /**< Bit mask for ETM_COUNTNUM */
<> 150:02e0a0aed4ec 185 #define _ETM_ETMCCR_COUNTNUM_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */
<> 150:02e0a0aed4ec 186 #define ETM_ETMCCR_COUNTNUM_DEFAULT (_ETM_ETMCCR_COUNTNUM_DEFAULT << 13) /**< Shifted mode DEFAULT for ETM_ETMCCR */
<> 150:02e0a0aed4ec 187 #define ETM_ETMCCR_SEQPRES (0x1UL << 16) /**< Sequencer Present */
<> 150:02e0a0aed4ec 188 #define _ETM_ETMCCR_SEQPRES_SHIFT 16 /**< Shift value for ETM_SEQPRES */
<> 150:02e0a0aed4ec 189 #define _ETM_ETMCCR_SEQPRES_MASK 0x10000UL /**< Bit mask for ETM_SEQPRES */
<> 150:02e0a0aed4ec 190 #define _ETM_ETMCCR_SEQPRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
<> 150:02e0a0aed4ec 191 #define ETM_ETMCCR_SEQPRES_DEFAULT (_ETM_ETMCCR_SEQPRES_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMCCR */
<> 150:02e0a0aed4ec 192 #define _ETM_ETMCCR_EXTINPNUM_SHIFT 17 /**< Shift value for ETM_EXTINPNUM */
<> 150:02e0a0aed4ec 193 #define _ETM_ETMCCR_EXTINPNUM_MASK 0xE0000UL /**< Bit mask for ETM_EXTINPNUM */
<> 150:02e0a0aed4ec 194 #define _ETM_ETMCCR_EXTINPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
<> 150:02e0a0aed4ec 195 #define _ETM_ETMCCR_EXTINPNUM_ZERO 0x00000000UL /**< Mode ZERO for ETM_ETMCCR */
<> 150:02e0a0aed4ec 196 #define _ETM_ETMCCR_EXTINPNUM_ONE 0x00000001UL /**< Mode ONE for ETM_ETMCCR */
<> 150:02e0a0aed4ec 197 #define _ETM_ETMCCR_EXTINPNUM_TWO 0x00000002UL /**< Mode TWO for ETM_ETMCCR */
<> 150:02e0a0aed4ec 198 #define ETM_ETMCCR_EXTINPNUM_DEFAULT (_ETM_ETMCCR_EXTINPNUM_DEFAULT << 17) /**< Shifted mode DEFAULT for ETM_ETMCCR */
<> 150:02e0a0aed4ec 199 #define ETM_ETMCCR_EXTINPNUM_ZERO (_ETM_ETMCCR_EXTINPNUM_ZERO << 17) /**< Shifted mode ZERO for ETM_ETMCCR */
<> 150:02e0a0aed4ec 200 #define ETM_ETMCCR_EXTINPNUM_ONE (_ETM_ETMCCR_EXTINPNUM_ONE << 17) /**< Shifted mode ONE for ETM_ETMCCR */
<> 150:02e0a0aed4ec 201 #define ETM_ETMCCR_EXTINPNUM_TWO (_ETM_ETMCCR_EXTINPNUM_TWO << 17) /**< Shifted mode TWO for ETM_ETMCCR */
<> 150:02e0a0aed4ec 202 #define _ETM_ETMCCR_EXTOUTNUM_SHIFT 20 /**< Shift value for ETM_EXTOUTNUM */
<> 150:02e0a0aed4ec 203 #define _ETM_ETMCCR_EXTOUTNUM_MASK 0x700000UL /**< Bit mask for ETM_EXTOUTNUM */
<> 150:02e0a0aed4ec 204 #define _ETM_ETMCCR_EXTOUTNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
<> 150:02e0a0aed4ec 205 #define ETM_ETMCCR_EXTOUTNUM_DEFAULT (_ETM_ETMCCR_EXTOUTNUM_DEFAULT << 20) /**< Shifted mode DEFAULT for ETM_ETMCCR */
<> 150:02e0a0aed4ec 206 #define ETM_ETMCCR_FIFOFULLPRES (0x1UL << 23) /**< FIFIO FULL present */
<> 150:02e0a0aed4ec 207 #define _ETM_ETMCCR_FIFOFULLPRES_SHIFT 23 /**< Shift value for ETM_FIFOFULLPRES */
<> 150:02e0a0aed4ec 208 #define _ETM_ETMCCR_FIFOFULLPRES_MASK 0x800000UL /**< Bit mask for ETM_FIFOFULLPRES */
<> 150:02e0a0aed4ec 209 #define _ETM_ETMCCR_FIFOFULLPRES_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */
<> 150:02e0a0aed4ec 210 #define ETM_ETMCCR_FIFOFULLPRES_DEFAULT (_ETM_ETMCCR_FIFOFULLPRES_DEFAULT << 23) /**< Shifted mode DEFAULT for ETM_ETMCCR */
<> 150:02e0a0aed4ec 211 #define _ETM_ETMCCR_IDCOMPNUM_SHIFT 24 /**< Shift value for ETM_IDCOMPNUM */
<> 150:02e0a0aed4ec 212 #define _ETM_ETMCCR_IDCOMPNUM_MASK 0x3000000UL /**< Bit mask for ETM_IDCOMPNUM */
<> 150:02e0a0aed4ec 213 #define _ETM_ETMCCR_IDCOMPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
<> 150:02e0a0aed4ec 214 #define ETM_ETMCCR_IDCOMPNUM_DEFAULT (_ETM_ETMCCR_IDCOMPNUM_DEFAULT << 24) /**< Shifted mode DEFAULT for ETM_ETMCCR */
<> 150:02e0a0aed4ec 215 #define ETM_ETMCCR_TRACESS (0x1UL << 26) /**< Trace Start/Stop Block Present */
<> 150:02e0a0aed4ec 216 #define _ETM_ETMCCR_TRACESS_SHIFT 26 /**< Shift value for ETM_TRACESS */
<> 150:02e0a0aed4ec 217 #define _ETM_ETMCCR_TRACESS_MASK 0x4000000UL /**< Bit mask for ETM_TRACESS */
<> 150:02e0a0aed4ec 218 #define _ETM_ETMCCR_TRACESS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */
<> 150:02e0a0aed4ec 219 #define ETM_ETMCCR_TRACESS_DEFAULT (_ETM_ETMCCR_TRACESS_DEFAULT << 26) /**< Shifted mode DEFAULT for ETM_ETMCCR */
<> 150:02e0a0aed4ec 220 #define ETM_ETMCCR_MMACCESS (0x1UL << 27) /**< Coprocessor and Memeory Access */
<> 150:02e0a0aed4ec 221 #define _ETM_ETMCCR_MMACCESS_SHIFT 27 /**< Shift value for ETM_MMACCESS */
<> 150:02e0a0aed4ec 222 #define _ETM_ETMCCR_MMACCESS_MASK 0x8000000UL /**< Bit mask for ETM_MMACCESS */
<> 150:02e0a0aed4ec 223 #define _ETM_ETMCCR_MMACCESS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */
<> 150:02e0a0aed4ec 224 #define ETM_ETMCCR_MMACCESS_DEFAULT (_ETM_ETMCCR_MMACCESS_DEFAULT << 27) /**< Shifted mode DEFAULT for ETM_ETMCCR */
<> 150:02e0a0aed4ec 225 #define ETM_ETMCCR_ETMID (0x1UL << 31) /**< ETM ID Register Present */
<> 150:02e0a0aed4ec 226 #define _ETM_ETMCCR_ETMID_SHIFT 31 /**< Shift value for ETM_ETMID */
<> 150:02e0a0aed4ec 227 #define _ETM_ETMCCR_ETMID_MASK 0x80000000UL /**< Bit mask for ETM_ETMID */
<> 150:02e0a0aed4ec 228 #define _ETM_ETMCCR_ETMID_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */
<> 150:02e0a0aed4ec 229 #define ETM_ETMCCR_ETMID_DEFAULT (_ETM_ETMCCR_ETMID_DEFAULT << 31) /**< Shifted mode DEFAULT for ETM_ETMCCR */
<> 150:02e0a0aed4ec 230
<> 150:02e0a0aed4ec 231 /* Bit fields for ETM ETMTRIGGER */
<> 150:02e0a0aed4ec 232 #define _ETM_ETMTRIGGER_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTRIGGER */
<> 150:02e0a0aed4ec 233 #define _ETM_ETMTRIGGER_MASK 0x0001FFFFUL /**< Mask for ETM_ETMTRIGGER */
<> 150:02e0a0aed4ec 234 #define _ETM_ETMTRIGGER_RESA_SHIFT 0 /**< Shift value for ETM_RESA */
<> 150:02e0a0aed4ec 235 #define _ETM_ETMTRIGGER_RESA_MASK 0x7FUL /**< Bit mask for ETM_RESA */
<> 150:02e0a0aed4ec 236 #define _ETM_ETMTRIGGER_RESA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRIGGER */
<> 150:02e0a0aed4ec 237 #define ETM_ETMTRIGGER_RESA_DEFAULT (_ETM_ETMTRIGGER_RESA_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTRIGGER */
<> 150:02e0a0aed4ec 238 #define _ETM_ETMTRIGGER_RESB_SHIFT 7 /**< Shift value for ETM_RESB */
<> 150:02e0a0aed4ec 239 #define _ETM_ETMTRIGGER_RESB_MASK 0x3F80UL /**< Bit mask for ETM_RESB */
<> 150:02e0a0aed4ec 240 #define _ETM_ETMTRIGGER_RESB_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRIGGER */
<> 150:02e0a0aed4ec 241 #define ETM_ETMTRIGGER_RESB_DEFAULT (_ETM_ETMTRIGGER_RESB_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMTRIGGER */
<> 150:02e0a0aed4ec 242 #define _ETM_ETMTRIGGER_ETMFCN_SHIFT 14 /**< Shift value for ETM_ETMFCN */
<> 150:02e0a0aed4ec 243 #define _ETM_ETMTRIGGER_ETMFCN_MASK 0x1C000UL /**< Bit mask for ETM_ETMFCN */
<> 150:02e0a0aed4ec 244 #define _ETM_ETMTRIGGER_ETMFCN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRIGGER */
<> 150:02e0a0aed4ec 245 #define ETM_ETMTRIGGER_ETMFCN_DEFAULT (_ETM_ETMTRIGGER_ETMFCN_DEFAULT << 14) /**< Shifted mode DEFAULT for ETM_ETMTRIGGER */
<> 150:02e0a0aed4ec 246
<> 150:02e0a0aed4ec 247 /* Bit fields for ETM ETMSR */
<> 150:02e0a0aed4ec 248 #define _ETM_ETMSR_RESETVALUE 0x00000002UL /**< Default value for ETM_ETMSR */
<> 150:02e0a0aed4ec 249 #define _ETM_ETMSR_MASK 0x0000000FUL /**< Mask for ETM_ETMSR */
<> 150:02e0a0aed4ec 250 #define ETM_ETMSR_ETHOF (0x1UL << 0) /**< ETM Overflow */
<> 150:02e0a0aed4ec 251 #define _ETM_ETMSR_ETHOF_SHIFT 0 /**< Shift value for ETM_ETHOF */
<> 150:02e0a0aed4ec 252 #define _ETM_ETMSR_ETHOF_MASK 0x1UL /**< Bit mask for ETM_ETHOF */
<> 150:02e0a0aed4ec 253 #define _ETM_ETMSR_ETHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSR */
<> 150:02e0a0aed4ec 254 #define ETM_ETMSR_ETHOF_DEFAULT (_ETM_ETMSR_ETHOF_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMSR */
<> 150:02e0a0aed4ec 255 #define ETM_ETMSR_ETMPROGBIT (0x1UL << 1) /**< ETM Programming Bit Status */
<> 150:02e0a0aed4ec 256 #define _ETM_ETMSR_ETMPROGBIT_SHIFT 1 /**< Shift value for ETM_ETMPROGBIT */
<> 150:02e0a0aed4ec 257 #define _ETM_ETMSR_ETMPROGBIT_MASK 0x2UL /**< Bit mask for ETM_ETMPROGBIT */
<> 150:02e0a0aed4ec 258 #define _ETM_ETMSR_ETMPROGBIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSR */
<> 150:02e0a0aed4ec 259 #define ETM_ETMSR_ETMPROGBIT_DEFAULT (_ETM_ETMSR_ETMPROGBIT_DEFAULT << 1) /**< Shifted mode DEFAULT for ETM_ETMSR */
<> 150:02e0a0aed4ec 260 #define ETM_ETMSR_TRACESTAT (0x1UL << 2) /**< Trace Start/Stop Status */
<> 150:02e0a0aed4ec 261 #define _ETM_ETMSR_TRACESTAT_SHIFT 2 /**< Shift value for ETM_TRACESTAT */
<> 150:02e0a0aed4ec 262 #define _ETM_ETMSR_TRACESTAT_MASK 0x4UL /**< Bit mask for ETM_TRACESTAT */
<> 150:02e0a0aed4ec 263 #define _ETM_ETMSR_TRACESTAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSR */
<> 150:02e0a0aed4ec 264 #define ETM_ETMSR_TRACESTAT_DEFAULT (_ETM_ETMSR_TRACESTAT_DEFAULT << 2) /**< Shifted mode DEFAULT for ETM_ETMSR */
<> 150:02e0a0aed4ec 265 #define ETM_ETMSR_TRIGBIT (0x1UL << 3) /**< Trigger Bit */
<> 150:02e0a0aed4ec 266 #define _ETM_ETMSR_TRIGBIT_SHIFT 3 /**< Shift value for ETM_TRIGBIT */
<> 150:02e0a0aed4ec 267 #define _ETM_ETMSR_TRIGBIT_MASK 0x8UL /**< Bit mask for ETM_TRIGBIT */
<> 150:02e0a0aed4ec 268 #define _ETM_ETMSR_TRIGBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSR */
<> 150:02e0a0aed4ec 269 #define ETM_ETMSR_TRIGBIT_DEFAULT (_ETM_ETMSR_TRIGBIT_DEFAULT << 3) /**< Shifted mode DEFAULT for ETM_ETMSR */
<> 150:02e0a0aed4ec 270
<> 150:02e0a0aed4ec 271 /* Bit fields for ETM ETMSCR */
<> 150:02e0a0aed4ec 272 #define _ETM_ETMSCR_RESETVALUE 0x00020D09UL /**< Default value for ETM_ETMSCR */
<> 150:02e0a0aed4ec 273 #define _ETM_ETMSCR_MASK 0x00027F0FUL /**< Mask for ETM_ETMSCR */
<> 150:02e0a0aed4ec 274 #define _ETM_ETMSCR_MAXPORTSIZE_SHIFT 0 /**< Shift value for ETM_MAXPORTSIZE */
<> 150:02e0a0aed4ec 275 #define _ETM_ETMSCR_MAXPORTSIZE_MASK 0x7UL /**< Bit mask for ETM_MAXPORTSIZE */
<> 150:02e0a0aed4ec 276 #define _ETM_ETMSCR_MAXPORTSIZE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */
<> 150:02e0a0aed4ec 277 #define ETM_ETMSCR_MAXPORTSIZE_DEFAULT (_ETM_ETMSCR_MAXPORTSIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMSCR */
<> 150:02e0a0aed4ec 278 #define ETM_ETMSCR_Reserved (0x1UL << 3) /**< Reserved */
<> 150:02e0a0aed4ec 279 #define _ETM_ETMSCR_Reserved_SHIFT 3 /**< Shift value for ETM_Reserved */
<> 150:02e0a0aed4ec 280 #define _ETM_ETMSCR_Reserved_MASK 0x8UL /**< Bit mask for ETM_Reserved */
<> 150:02e0a0aed4ec 281 #define _ETM_ETMSCR_Reserved_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */
<> 150:02e0a0aed4ec 282 #define ETM_ETMSCR_Reserved_DEFAULT (_ETM_ETMSCR_Reserved_DEFAULT << 3) /**< Shifted mode DEFAULT for ETM_ETMSCR */
<> 150:02e0a0aed4ec 283 #define ETM_ETMSCR_FIFOFULL (0x1UL << 8) /**< FIFO FULL Supported */
<> 150:02e0a0aed4ec 284 #define _ETM_ETMSCR_FIFOFULL_SHIFT 8 /**< Shift value for ETM_FIFOFULL */
<> 150:02e0a0aed4ec 285 #define _ETM_ETMSCR_FIFOFULL_MASK 0x100UL /**< Bit mask for ETM_FIFOFULL */
<> 150:02e0a0aed4ec 286 #define _ETM_ETMSCR_FIFOFULL_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */
<> 150:02e0a0aed4ec 287 #define ETM_ETMSCR_FIFOFULL_DEFAULT (_ETM_ETMSCR_FIFOFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMSCR */
<> 150:02e0a0aed4ec 288 #define ETM_ETMSCR_MAXPORTSIZE3 (0x1UL << 9) /**< Max Port Size[3] */
<> 150:02e0a0aed4ec 289 #define _ETM_ETMSCR_MAXPORTSIZE3_SHIFT 9 /**< Shift value for ETM_MAXPORTSIZE3 */
<> 150:02e0a0aed4ec 290 #define _ETM_ETMSCR_MAXPORTSIZE3_MASK 0x200UL /**< Bit mask for ETM_MAXPORTSIZE3 */
<> 150:02e0a0aed4ec 291 #define _ETM_ETMSCR_MAXPORTSIZE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSCR */
<> 150:02e0a0aed4ec 292 #define ETM_ETMSCR_MAXPORTSIZE3_DEFAULT (_ETM_ETMSCR_MAXPORTSIZE3_DEFAULT << 9) /**< Shifted mode DEFAULT for ETM_ETMSCR */
<> 150:02e0a0aed4ec 293 #define ETM_ETMSCR_PORTSIZE (0x1UL << 10) /**< Port Size Supported */
<> 150:02e0a0aed4ec 294 #define _ETM_ETMSCR_PORTSIZE_SHIFT 10 /**< Shift value for ETM_PORTSIZE */
<> 150:02e0a0aed4ec 295 #define _ETM_ETMSCR_PORTSIZE_MASK 0x400UL /**< Bit mask for ETM_PORTSIZE */
<> 150:02e0a0aed4ec 296 #define _ETM_ETMSCR_PORTSIZE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */
<> 150:02e0a0aed4ec 297 #define ETM_ETMSCR_PORTSIZE_DEFAULT (_ETM_ETMSCR_PORTSIZE_DEFAULT << 10) /**< Shifted mode DEFAULT for ETM_ETMSCR */
<> 150:02e0a0aed4ec 298 #define ETM_ETMSCR_PORTMODE (0x1UL << 11) /**< Port Mode Supported */
<> 150:02e0a0aed4ec 299 #define _ETM_ETMSCR_PORTMODE_SHIFT 11 /**< Shift value for ETM_PORTMODE */
<> 150:02e0a0aed4ec 300 #define _ETM_ETMSCR_PORTMODE_MASK 0x800UL /**< Bit mask for ETM_PORTMODE */
<> 150:02e0a0aed4ec 301 #define _ETM_ETMSCR_PORTMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */
<> 150:02e0a0aed4ec 302 #define ETM_ETMSCR_PORTMODE_DEFAULT (_ETM_ETMSCR_PORTMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for ETM_ETMSCR */
<> 150:02e0a0aed4ec 303 #define _ETM_ETMSCR_PROCNUM_SHIFT 12 /**< Shift value for ETM_PROCNUM */
<> 150:02e0a0aed4ec 304 #define _ETM_ETMSCR_PROCNUM_MASK 0x7000UL /**< Bit mask for ETM_PROCNUM */
<> 150:02e0a0aed4ec 305 #define _ETM_ETMSCR_PROCNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSCR */
<> 150:02e0a0aed4ec 306 #define ETM_ETMSCR_PROCNUM_DEFAULT (_ETM_ETMSCR_PROCNUM_DEFAULT << 12) /**< Shifted mode DEFAULT for ETM_ETMSCR */
<> 150:02e0a0aed4ec 307 #define ETM_ETMSCR_NOFETCHCOMP (0x1UL << 17) /**< No Fetch Comparison */
<> 150:02e0a0aed4ec 308 #define _ETM_ETMSCR_NOFETCHCOMP_SHIFT 17 /**< Shift value for ETM_NOFETCHCOMP */
<> 150:02e0a0aed4ec 309 #define _ETM_ETMSCR_NOFETCHCOMP_MASK 0x20000UL /**< Bit mask for ETM_NOFETCHCOMP */
<> 150:02e0a0aed4ec 310 #define _ETM_ETMSCR_NOFETCHCOMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */
<> 150:02e0a0aed4ec 311 #define ETM_ETMSCR_NOFETCHCOMP_DEFAULT (_ETM_ETMSCR_NOFETCHCOMP_DEFAULT << 17) /**< Shifted mode DEFAULT for ETM_ETMSCR */
<> 150:02e0a0aed4ec 312
<> 150:02e0a0aed4ec 313 /* Bit fields for ETM ETMTEEVR */
<> 150:02e0a0aed4ec 314 #define _ETM_ETMTEEVR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTEEVR */
<> 150:02e0a0aed4ec 315 #define _ETM_ETMTEEVR_MASK 0x0001FFFFUL /**< Mask for ETM_ETMTEEVR */
<> 150:02e0a0aed4ec 316 #define _ETM_ETMTEEVR_RESA_SHIFT 0 /**< Shift value for ETM_RESA */
<> 150:02e0a0aed4ec 317 #define _ETM_ETMTEEVR_RESA_MASK 0x7FUL /**< Bit mask for ETM_RESA */
<> 150:02e0a0aed4ec 318 #define _ETM_ETMTEEVR_RESA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTEEVR */
<> 150:02e0a0aed4ec 319 #define ETM_ETMTEEVR_RESA_DEFAULT (_ETM_ETMTEEVR_RESA_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTEEVR */
<> 150:02e0a0aed4ec 320 #define _ETM_ETMTEEVR_RESB_SHIFT 7 /**< Shift value for ETM_RESB */
<> 150:02e0a0aed4ec 321 #define _ETM_ETMTEEVR_RESB_MASK 0x3F80UL /**< Bit mask for ETM_RESB */
<> 150:02e0a0aed4ec 322 #define _ETM_ETMTEEVR_RESB_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTEEVR */
<> 150:02e0a0aed4ec 323 #define ETM_ETMTEEVR_RESB_DEFAULT (_ETM_ETMTEEVR_RESB_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMTEEVR */
<> 150:02e0a0aed4ec 324 #define _ETM_ETMTEEVR_ETMFCNEN_SHIFT 14 /**< Shift value for ETM_ETMFCNEN */
<> 150:02e0a0aed4ec 325 #define _ETM_ETMTEEVR_ETMFCNEN_MASK 0x1C000UL /**< Bit mask for ETM_ETMFCNEN */
<> 150:02e0a0aed4ec 326 #define _ETM_ETMTEEVR_ETMFCNEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTEEVR */
<> 150:02e0a0aed4ec 327 #define ETM_ETMTEEVR_ETMFCNEN_DEFAULT (_ETM_ETMTEEVR_ETMFCNEN_DEFAULT << 14) /**< Shifted mode DEFAULT for ETM_ETMTEEVR */
<> 150:02e0a0aed4ec 328
<> 150:02e0a0aed4ec 329 /* Bit fields for ETM ETMTECR1 */
<> 150:02e0a0aed4ec 330 #define _ETM_ETMTECR1_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTECR1 */
<> 150:02e0a0aed4ec 331 #define _ETM_ETMTECR1_MASK 0x03FFFFFFUL /**< Mask for ETM_ETMTECR1 */
<> 150:02e0a0aed4ec 332 #define _ETM_ETMTECR1_ADRCMP_SHIFT 0 /**< Shift value for ETM_ADRCMP */
<> 150:02e0a0aed4ec 333 #define _ETM_ETMTECR1_ADRCMP_MASK 0xFFUL /**< Bit mask for ETM_ADRCMP */
<> 150:02e0a0aed4ec 334 #define _ETM_ETMTECR1_ADRCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */
<> 150:02e0a0aed4ec 335 #define ETM_ETMTECR1_ADRCMP_DEFAULT (_ETM_ETMTECR1_ADRCMP_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */
<> 150:02e0a0aed4ec 336 #define _ETM_ETMTECR1_MEMMAP_SHIFT 8 /**< Shift value for ETM_MEMMAP */
<> 150:02e0a0aed4ec 337 #define _ETM_ETMTECR1_MEMMAP_MASK 0xFFFF00UL /**< Bit mask for ETM_MEMMAP */
<> 150:02e0a0aed4ec 338 #define _ETM_ETMTECR1_MEMMAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */
<> 150:02e0a0aed4ec 339 #define ETM_ETMTECR1_MEMMAP_DEFAULT (_ETM_ETMTECR1_MEMMAP_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */
<> 150:02e0a0aed4ec 340 #define ETM_ETMTECR1_INCEXCTL (0x1UL << 24) /**< Trace Include/Exclude Flag */
<> 150:02e0a0aed4ec 341 #define _ETM_ETMTECR1_INCEXCTL_SHIFT 24 /**< Shift value for ETM_INCEXCTL */
<> 150:02e0a0aed4ec 342 #define _ETM_ETMTECR1_INCEXCTL_MASK 0x1000000UL /**< Bit mask for ETM_INCEXCTL */
<> 150:02e0a0aed4ec 343 #define _ETM_ETMTECR1_INCEXCTL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */
<> 150:02e0a0aed4ec 344 #define _ETM_ETMTECR1_INCEXCTL_INC 0x00000000UL /**< Mode INC for ETM_ETMTECR1 */
<> 150:02e0a0aed4ec 345 #define _ETM_ETMTECR1_INCEXCTL_EXC 0x00000001UL /**< Mode EXC for ETM_ETMTECR1 */
<> 150:02e0a0aed4ec 346 #define ETM_ETMTECR1_INCEXCTL_DEFAULT (_ETM_ETMTECR1_INCEXCTL_DEFAULT << 24) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */
<> 150:02e0a0aed4ec 347 #define ETM_ETMTECR1_INCEXCTL_INC (_ETM_ETMTECR1_INCEXCTL_INC << 24) /**< Shifted mode INC for ETM_ETMTECR1 */
<> 150:02e0a0aed4ec 348 #define ETM_ETMTECR1_INCEXCTL_EXC (_ETM_ETMTECR1_INCEXCTL_EXC << 24) /**< Shifted mode EXC for ETM_ETMTECR1 */
<> 150:02e0a0aed4ec 349 #define ETM_ETMTECR1_TCE (0x1UL << 25) /**< Trace Control Enable */
<> 150:02e0a0aed4ec 350 #define _ETM_ETMTECR1_TCE_SHIFT 25 /**< Shift value for ETM_TCE */
<> 150:02e0a0aed4ec 351 #define _ETM_ETMTECR1_TCE_MASK 0x2000000UL /**< Bit mask for ETM_TCE */
<> 150:02e0a0aed4ec 352 #define _ETM_ETMTECR1_TCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */
<> 150:02e0a0aed4ec 353 #define _ETM_ETMTECR1_TCE_EN 0x00000000UL /**< Mode EN for ETM_ETMTECR1 */
<> 150:02e0a0aed4ec 354 #define _ETM_ETMTECR1_TCE_DIS 0x00000001UL /**< Mode DIS for ETM_ETMTECR1 */
<> 150:02e0a0aed4ec 355 #define ETM_ETMTECR1_TCE_DEFAULT (_ETM_ETMTECR1_TCE_DEFAULT << 25) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */
<> 150:02e0a0aed4ec 356 #define ETM_ETMTECR1_TCE_EN (_ETM_ETMTECR1_TCE_EN << 25) /**< Shifted mode EN for ETM_ETMTECR1 */
<> 150:02e0a0aed4ec 357 #define ETM_ETMTECR1_TCE_DIS (_ETM_ETMTECR1_TCE_DIS << 25) /**< Shifted mode DIS for ETM_ETMTECR1 */
<> 150:02e0a0aed4ec 358
<> 150:02e0a0aed4ec 359 /* Bit fields for ETM ETMFFLR */
<> 150:02e0a0aed4ec 360 #define _ETM_ETMFFLR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMFFLR */
<> 150:02e0a0aed4ec 361 #define _ETM_ETMFFLR_MASK 0x000000FFUL /**< Mask for ETM_ETMFFLR */
<> 150:02e0a0aed4ec 362 #define _ETM_ETMFFLR_BYTENUM_SHIFT 0 /**< Shift value for ETM_BYTENUM */
<> 150:02e0a0aed4ec 363 #define _ETM_ETMFFLR_BYTENUM_MASK 0xFFUL /**< Bit mask for ETM_BYTENUM */
<> 150:02e0a0aed4ec 364 #define _ETM_ETMFFLR_BYTENUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMFFLR */
<> 150:02e0a0aed4ec 365 #define ETM_ETMFFLR_BYTENUM_DEFAULT (_ETM_ETMFFLR_BYTENUM_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMFFLR */
<> 150:02e0a0aed4ec 366
<> 150:02e0a0aed4ec 367 /* Bit fields for ETM ETMCNTRLDVR1 */
<> 150:02e0a0aed4ec 368 #define _ETM_ETMCNTRLDVR1_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMCNTRLDVR1 */
<> 150:02e0a0aed4ec 369 #define _ETM_ETMCNTRLDVR1_MASK 0x0000FFFFUL /**< Mask for ETM_ETMCNTRLDVR1 */
<> 150:02e0a0aed4ec 370 #define _ETM_ETMCNTRLDVR1_COUNT_SHIFT 0 /**< Shift value for ETM_COUNT */
<> 150:02e0a0aed4ec 371 #define _ETM_ETMCNTRLDVR1_COUNT_MASK 0xFFFFUL /**< Bit mask for ETM_COUNT */
<> 150:02e0a0aed4ec 372 #define _ETM_ETMCNTRLDVR1_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCNTRLDVR1 */
<> 150:02e0a0aed4ec 373 #define ETM_ETMCNTRLDVR1_COUNT_DEFAULT (_ETM_ETMCNTRLDVR1_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCNTRLDVR1 */
<> 150:02e0a0aed4ec 374
<> 150:02e0a0aed4ec 375 /* Bit fields for ETM ETMSYNCFR */
<> 150:02e0a0aed4ec 376 #define _ETM_ETMSYNCFR_RESETVALUE 0x00000400UL /**< Default value for ETM_ETMSYNCFR */
<> 150:02e0a0aed4ec 377 #define _ETM_ETMSYNCFR_MASK 0x00000FFFUL /**< Mask for ETM_ETMSYNCFR */
<> 150:02e0a0aed4ec 378 #define _ETM_ETMSYNCFR_FREQ_SHIFT 0 /**< Shift value for ETM_FREQ */
<> 150:02e0a0aed4ec 379 #define _ETM_ETMSYNCFR_FREQ_MASK 0xFFFUL /**< Bit mask for ETM_FREQ */
<> 150:02e0a0aed4ec 380 #define _ETM_ETMSYNCFR_FREQ_DEFAULT 0x00000400UL /**< Mode DEFAULT for ETM_ETMSYNCFR */
<> 150:02e0a0aed4ec 381 #define ETM_ETMSYNCFR_FREQ_DEFAULT (_ETM_ETMSYNCFR_FREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMSYNCFR */
<> 150:02e0a0aed4ec 382
<> 150:02e0a0aed4ec 383 /* Bit fields for ETM ETMIDR */
<> 150:02e0a0aed4ec 384 #define _ETM_ETMIDR_RESETVALUE 0x4114F253UL /**< Default value for ETM_ETMIDR */
<> 150:02e0a0aed4ec 385 #define _ETM_ETMIDR_MASK 0xFF1DFFFFUL /**< Mask for ETM_ETMIDR */
<> 150:02e0a0aed4ec 386 #define _ETM_ETMIDR_IMPVER_SHIFT 0 /**< Shift value for ETM_IMPVER */
<> 150:02e0a0aed4ec 387 #define _ETM_ETMIDR_IMPVER_MASK 0xFUL /**< Bit mask for ETM_IMPVER */
<> 150:02e0a0aed4ec 388 #define _ETM_ETMIDR_IMPVER_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMIDR */
<> 150:02e0a0aed4ec 389 #define ETM_ETMIDR_IMPVER_DEFAULT (_ETM_ETMIDR_IMPVER_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMIDR */
<> 150:02e0a0aed4ec 390 #define _ETM_ETMIDR_ETMMINVER_SHIFT 4 /**< Shift value for ETM_ETMMINVER */
<> 150:02e0a0aed4ec 391 #define _ETM_ETMIDR_ETMMINVER_MASK 0xF0UL /**< Bit mask for ETM_ETMMINVER */
<> 150:02e0a0aed4ec 392 #define _ETM_ETMIDR_ETMMINVER_DEFAULT 0x00000005UL /**< Mode DEFAULT for ETM_ETMIDR */
<> 150:02e0a0aed4ec 393 #define ETM_ETMIDR_ETMMINVER_DEFAULT (_ETM_ETMIDR_ETMMINVER_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMIDR */
<> 150:02e0a0aed4ec 394 #define _ETM_ETMIDR_ETMMAJVER_SHIFT 8 /**< Shift value for ETM_ETMMAJVER */
<> 150:02e0a0aed4ec 395 #define _ETM_ETMIDR_ETMMAJVER_MASK 0xF00UL /**< Bit mask for ETM_ETMMAJVER */
<> 150:02e0a0aed4ec 396 #define _ETM_ETMIDR_ETMMAJVER_DEFAULT 0x00000002UL /**< Mode DEFAULT for ETM_ETMIDR */
<> 150:02e0a0aed4ec 397 #define ETM_ETMIDR_ETMMAJVER_DEFAULT (_ETM_ETMIDR_ETMMAJVER_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMIDR */
<> 150:02e0a0aed4ec 398 #define _ETM_ETMIDR_PROCFAM_SHIFT 12 /**< Shift value for ETM_PROCFAM */
<> 150:02e0a0aed4ec 399 #define _ETM_ETMIDR_PROCFAM_MASK 0xF000UL /**< Bit mask for ETM_PROCFAM */
<> 150:02e0a0aed4ec 400 #define _ETM_ETMIDR_PROCFAM_DEFAULT 0x0000000FUL /**< Mode DEFAULT for ETM_ETMIDR */
<> 150:02e0a0aed4ec 401 #define ETM_ETMIDR_PROCFAM_DEFAULT (_ETM_ETMIDR_PROCFAM_DEFAULT << 12) /**< Shifted mode DEFAULT for ETM_ETMIDR */
<> 150:02e0a0aed4ec 402 #define ETM_ETMIDR_LPCF (0x1UL << 16) /**< Load PC First */
<> 150:02e0a0aed4ec 403 #define _ETM_ETMIDR_LPCF_SHIFT 16 /**< Shift value for ETM_LPCF */
<> 150:02e0a0aed4ec 404 #define _ETM_ETMIDR_LPCF_MASK 0x10000UL /**< Bit mask for ETM_LPCF */
<> 150:02e0a0aed4ec 405 #define _ETM_ETMIDR_LPCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR */
<> 150:02e0a0aed4ec 406 #define ETM_ETMIDR_LPCF_DEFAULT (_ETM_ETMIDR_LPCF_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMIDR */
<> 150:02e0a0aed4ec 407 #define ETM_ETMIDR_THUMBT (0x1UL << 18) /**< 32-bit Thumb Instruction Tracing */
<> 150:02e0a0aed4ec 408 #define _ETM_ETMIDR_THUMBT_SHIFT 18 /**< Shift value for ETM_THUMBT */
<> 150:02e0a0aed4ec 409 #define _ETM_ETMIDR_THUMBT_MASK 0x40000UL /**< Bit mask for ETM_THUMBT */
<> 150:02e0a0aed4ec 410 #define _ETM_ETMIDR_THUMBT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMIDR */
<> 150:02e0a0aed4ec 411 #define ETM_ETMIDR_THUMBT_DEFAULT (_ETM_ETMIDR_THUMBT_DEFAULT << 18) /**< Shifted mode DEFAULT for ETM_ETMIDR */
<> 150:02e0a0aed4ec 412 #define ETM_ETMIDR_SECEXT (0x1UL << 19) /**< Security Extension Support */
<> 150:02e0a0aed4ec 413 #define _ETM_ETMIDR_SECEXT_SHIFT 19 /**< Shift value for ETM_SECEXT */
<> 150:02e0a0aed4ec 414 #define _ETM_ETMIDR_SECEXT_MASK 0x80000UL /**< Bit mask for ETM_SECEXT */
<> 150:02e0a0aed4ec 415 #define _ETM_ETMIDR_SECEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR */
<> 150:02e0a0aed4ec 416 #define ETM_ETMIDR_SECEXT_DEFAULT (_ETM_ETMIDR_SECEXT_DEFAULT << 19) /**< Shifted mode DEFAULT for ETM_ETMIDR */
<> 150:02e0a0aed4ec 417 #define ETM_ETMIDR_BPE (0x1UL << 20) /**< Branch Packet Encoding */
<> 150:02e0a0aed4ec 418 #define _ETM_ETMIDR_BPE_SHIFT 20 /**< Shift value for ETM_BPE */
<> 150:02e0a0aed4ec 419 #define _ETM_ETMIDR_BPE_MASK 0x100000UL /**< Bit mask for ETM_BPE */
<> 150:02e0a0aed4ec 420 #define _ETM_ETMIDR_BPE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMIDR */
<> 150:02e0a0aed4ec 421 #define ETM_ETMIDR_BPE_DEFAULT (_ETM_ETMIDR_BPE_DEFAULT << 20) /**< Shifted mode DEFAULT for ETM_ETMIDR */
<> 150:02e0a0aed4ec 422 #define _ETM_ETMIDR_IMPCODE_SHIFT 24 /**< Shift value for ETM_IMPCODE */
<> 150:02e0a0aed4ec 423 #define _ETM_ETMIDR_IMPCODE_MASK 0xFF000000UL /**< Bit mask for ETM_IMPCODE */
<> 150:02e0a0aed4ec 424 #define _ETM_ETMIDR_IMPCODE_DEFAULT 0x00000041UL /**< Mode DEFAULT for ETM_ETMIDR */
<> 150:02e0a0aed4ec 425 #define ETM_ETMIDR_IMPCODE_DEFAULT (_ETM_ETMIDR_IMPCODE_DEFAULT << 24) /**< Shifted mode DEFAULT for ETM_ETMIDR */
<> 150:02e0a0aed4ec 426
<> 150:02e0a0aed4ec 427 /* Bit fields for ETM ETMCCER */
<> 150:02e0a0aed4ec 428 #define _ETM_ETMCCER_RESETVALUE 0x18541800UL /**< Default value for ETM_ETMCCER */
<> 150:02e0a0aed4ec 429 #define _ETM_ETMCCER_MASK 0x387FFFFBUL /**< Mask for ETM_ETMCCER */
<> 150:02e0a0aed4ec 430 #define _ETM_ETMCCER_EXTINPSEL_SHIFT 0 /**< Shift value for ETM_EXTINPSEL */
<> 150:02e0a0aed4ec 431 #define _ETM_ETMCCER_EXTINPSEL_MASK 0x3UL /**< Bit mask for ETM_EXTINPSEL */
<> 150:02e0a0aed4ec 432 #define _ETM_ETMCCER_EXTINPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */
<> 150:02e0a0aed4ec 433 #define ETM_ETMCCER_EXTINPSEL_DEFAULT (_ETM_ETMCCER_EXTINPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCCER */
<> 150:02e0a0aed4ec 434 #define _ETM_ETMCCER_EXTINPBUS_SHIFT 3 /**< Shift value for ETM_EXTINPBUS */
<> 150:02e0a0aed4ec 435 #define _ETM_ETMCCER_EXTINPBUS_MASK 0x7F8UL /**< Bit mask for ETM_EXTINPBUS */
<> 150:02e0a0aed4ec 436 #define _ETM_ETMCCER_EXTINPBUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */
<> 150:02e0a0aed4ec 437 #define ETM_ETMCCER_EXTINPBUS_DEFAULT (_ETM_ETMCCER_EXTINPBUS_DEFAULT << 3) /**< Shifted mode DEFAULT for ETM_ETMCCER */
<> 150:02e0a0aed4ec 438 #define ETM_ETMCCER_READREGS (0x1UL << 11) /**< Readable Registers */
<> 150:02e0a0aed4ec 439 #define _ETM_ETMCCER_READREGS_SHIFT 11 /**< Shift value for ETM_READREGS */
<> 150:02e0a0aed4ec 440 #define _ETM_ETMCCER_READREGS_MASK 0x800UL /**< Bit mask for ETM_READREGS */
<> 150:02e0a0aed4ec 441 #define _ETM_ETMCCER_READREGS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */
<> 150:02e0a0aed4ec 442 #define ETM_ETMCCER_READREGS_DEFAULT (_ETM_ETMCCER_READREGS_DEFAULT << 11) /**< Shifted mode DEFAULT for ETM_ETMCCER */
<> 150:02e0a0aed4ec 443 #define ETM_ETMCCER_DADDRCMP (0x1UL << 12) /**< Data Address comparisons */
<> 150:02e0a0aed4ec 444 #define _ETM_ETMCCER_DADDRCMP_SHIFT 12 /**< Shift value for ETM_DADDRCMP */
<> 150:02e0a0aed4ec 445 #define _ETM_ETMCCER_DADDRCMP_MASK 0x1000UL /**< Bit mask for ETM_DADDRCMP */
<> 150:02e0a0aed4ec 446 #define _ETM_ETMCCER_DADDRCMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */
<> 150:02e0a0aed4ec 447 #define ETM_ETMCCER_DADDRCMP_DEFAULT (_ETM_ETMCCER_DADDRCMP_DEFAULT << 12) /**< Shifted mode DEFAULT for ETM_ETMCCER */
<> 150:02e0a0aed4ec 448 #define _ETM_ETMCCER_INSTRES_SHIFT 13 /**< Shift value for ETM_INSTRES */
<> 150:02e0a0aed4ec 449 #define _ETM_ETMCCER_INSTRES_MASK 0xE000UL /**< Bit mask for ETM_INSTRES */
<> 150:02e0a0aed4ec 450 #define _ETM_ETMCCER_INSTRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */
<> 150:02e0a0aed4ec 451 #define ETM_ETMCCER_INSTRES_DEFAULT (_ETM_ETMCCER_INSTRES_DEFAULT << 13) /**< Shifted mode DEFAULT for ETM_ETMCCER */
<> 150:02e0a0aed4ec 452 #define _ETM_ETMCCER_EICEWPNT_SHIFT 16 /**< Shift value for ETM_EICEWPNT */
<> 150:02e0a0aed4ec 453 #define _ETM_ETMCCER_EICEWPNT_MASK 0xF0000UL /**< Bit mask for ETM_EICEWPNT */
<> 150:02e0a0aed4ec 454 #define _ETM_ETMCCER_EICEWPNT_DEFAULT 0x00000004UL /**< Mode DEFAULT for ETM_ETMCCER */
<> 150:02e0a0aed4ec 455 #define ETM_ETMCCER_EICEWPNT_DEFAULT (_ETM_ETMCCER_EICEWPNT_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMCCER */
<> 150:02e0a0aed4ec 456 #define ETM_ETMCCER_TEICEWPNT (0x1UL << 20) /**< Trace Sart/Stop Block Uses EmbeddedICE watchpoint inputs */
<> 150:02e0a0aed4ec 457 #define _ETM_ETMCCER_TEICEWPNT_SHIFT 20 /**< Shift value for ETM_TEICEWPNT */
<> 150:02e0a0aed4ec 458 #define _ETM_ETMCCER_TEICEWPNT_MASK 0x100000UL /**< Bit mask for ETM_TEICEWPNT */
<> 150:02e0a0aed4ec 459 #define _ETM_ETMCCER_TEICEWPNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */
<> 150:02e0a0aed4ec 460 #define ETM_ETMCCER_TEICEWPNT_DEFAULT (_ETM_ETMCCER_TEICEWPNT_DEFAULT << 20) /**< Shifted mode DEFAULT for ETM_ETMCCER */
<> 150:02e0a0aed4ec 461 #define ETM_ETMCCER_EICEIMP (0x1UL << 21) /**< EmbeddedICE Behavior control Implemented */
<> 150:02e0a0aed4ec 462 #define _ETM_ETMCCER_EICEIMP_SHIFT 21 /**< Shift value for ETM_EICEIMP */
<> 150:02e0a0aed4ec 463 #define _ETM_ETMCCER_EICEIMP_MASK 0x200000UL /**< Bit mask for ETM_EICEIMP */
<> 150:02e0a0aed4ec 464 #define _ETM_ETMCCER_EICEIMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */
<> 150:02e0a0aed4ec 465 #define ETM_ETMCCER_EICEIMP_DEFAULT (_ETM_ETMCCER_EICEIMP_DEFAULT << 21) /**< Shifted mode DEFAULT for ETM_ETMCCER */
<> 150:02e0a0aed4ec 466 #define ETM_ETMCCER_TIMP (0x1UL << 22) /**< Timestamping Implemented */
<> 150:02e0a0aed4ec 467 #define _ETM_ETMCCER_TIMP_SHIFT 22 /**< Shift value for ETM_TIMP */
<> 150:02e0a0aed4ec 468 #define _ETM_ETMCCER_TIMP_MASK 0x400000UL /**< Bit mask for ETM_TIMP */
<> 150:02e0a0aed4ec 469 #define _ETM_ETMCCER_TIMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */
<> 150:02e0a0aed4ec 470 #define ETM_ETMCCER_TIMP_DEFAULT (_ETM_ETMCCER_TIMP_DEFAULT << 22) /**< Shifted mode DEFAULT for ETM_ETMCCER */
<> 150:02e0a0aed4ec 471 #define ETM_ETMCCER_RFCNT (0x1UL << 27) /**< Reduced Function Counter */
<> 150:02e0a0aed4ec 472 #define _ETM_ETMCCER_RFCNT_SHIFT 27 /**< Shift value for ETM_RFCNT */
<> 150:02e0a0aed4ec 473 #define _ETM_ETMCCER_RFCNT_MASK 0x8000000UL /**< Bit mask for ETM_RFCNT */
<> 150:02e0a0aed4ec 474 #define _ETM_ETMCCER_RFCNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */
<> 150:02e0a0aed4ec 475 #define ETM_ETMCCER_RFCNT_DEFAULT (_ETM_ETMCCER_RFCNT_DEFAULT << 27) /**< Shifted mode DEFAULT for ETM_ETMCCER */
<> 150:02e0a0aed4ec 476 #define ETM_ETMCCER_TENC (0x1UL << 28) /**< Timestamp Encoding */
<> 150:02e0a0aed4ec 477 #define _ETM_ETMCCER_TENC_SHIFT 28 /**< Shift value for ETM_TENC */
<> 150:02e0a0aed4ec 478 #define _ETM_ETMCCER_TENC_MASK 0x10000000UL /**< Bit mask for ETM_TENC */
<> 150:02e0a0aed4ec 479 #define _ETM_ETMCCER_TENC_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */
<> 150:02e0a0aed4ec 480 #define ETM_ETMCCER_TENC_DEFAULT (_ETM_ETMCCER_TENC_DEFAULT << 28) /**< Shifted mode DEFAULT for ETM_ETMCCER */
<> 150:02e0a0aed4ec 481 #define ETM_ETMCCER_TSIZE (0x1UL << 29) /**< Timestamp Size */
<> 150:02e0a0aed4ec 482 #define _ETM_ETMCCER_TSIZE_SHIFT 29 /**< Shift value for ETM_TSIZE */
<> 150:02e0a0aed4ec 483 #define _ETM_ETMCCER_TSIZE_MASK 0x20000000UL /**< Bit mask for ETM_TSIZE */
<> 150:02e0a0aed4ec 484 #define _ETM_ETMCCER_TSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */
<> 150:02e0a0aed4ec 485 #define ETM_ETMCCER_TSIZE_DEFAULT (_ETM_ETMCCER_TSIZE_DEFAULT << 29) /**< Shifted mode DEFAULT for ETM_ETMCCER */
<> 150:02e0a0aed4ec 486
<> 150:02e0a0aed4ec 487 /* Bit fields for ETM ETMTESSEICR */
<> 150:02e0a0aed4ec 488 #define _ETM_ETMTESSEICR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTESSEICR */
<> 150:02e0a0aed4ec 489 #define _ETM_ETMTESSEICR_MASK 0x000F000FUL /**< Mask for ETM_ETMTESSEICR */
<> 150:02e0a0aed4ec 490 #define _ETM_ETMTESSEICR_STARTRSEL_SHIFT 0 /**< Shift value for ETM_STARTRSEL */
<> 150:02e0a0aed4ec 491 #define _ETM_ETMTESSEICR_STARTRSEL_MASK 0xFUL /**< Bit mask for ETM_STARTRSEL */
<> 150:02e0a0aed4ec 492 #define _ETM_ETMTESSEICR_STARTRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTESSEICR */
<> 150:02e0a0aed4ec 493 #define ETM_ETMTESSEICR_STARTRSEL_DEFAULT (_ETM_ETMTESSEICR_STARTRSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTESSEICR */
<> 150:02e0a0aed4ec 494 #define _ETM_ETMTESSEICR_STOPRSEL_SHIFT 16 /**< Shift value for ETM_STOPRSEL */
<> 150:02e0a0aed4ec 495 #define _ETM_ETMTESSEICR_STOPRSEL_MASK 0xF0000UL /**< Bit mask for ETM_STOPRSEL */
<> 150:02e0a0aed4ec 496 #define _ETM_ETMTESSEICR_STOPRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTESSEICR */
<> 150:02e0a0aed4ec 497 #define ETM_ETMTESSEICR_STOPRSEL_DEFAULT (_ETM_ETMTESSEICR_STOPRSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMTESSEICR */
<> 150:02e0a0aed4ec 498
<> 150:02e0a0aed4ec 499 /* Bit fields for ETM ETMTSEVR */
<> 150:02e0a0aed4ec 500 #define _ETM_ETMTSEVR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTSEVR */
<> 150:02e0a0aed4ec 501 #define _ETM_ETMTSEVR_MASK 0x0001FFFFUL /**< Mask for ETM_ETMTSEVR */
<> 150:02e0a0aed4ec 502 #define _ETM_ETMTSEVR_RESAEVT_SHIFT 0 /**< Shift value for ETM_RESAEVT */
<> 150:02e0a0aed4ec 503 #define _ETM_ETMTSEVR_RESAEVT_MASK 0x7FUL /**< Bit mask for ETM_RESAEVT */
<> 150:02e0a0aed4ec 504 #define _ETM_ETMTSEVR_RESAEVT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTSEVR */
<> 150:02e0a0aed4ec 505 #define ETM_ETMTSEVR_RESAEVT_DEFAULT (_ETM_ETMTSEVR_RESAEVT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTSEVR */
<> 150:02e0a0aed4ec 506 #define _ETM_ETMTSEVR_RESBEVT_SHIFT 7 /**< Shift value for ETM_RESBEVT */
<> 150:02e0a0aed4ec 507 #define _ETM_ETMTSEVR_RESBEVT_MASK 0x3F80UL /**< Bit mask for ETM_RESBEVT */
<> 150:02e0a0aed4ec 508 #define _ETM_ETMTSEVR_RESBEVT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTSEVR */
<> 150:02e0a0aed4ec 509 #define ETM_ETMTSEVR_RESBEVT_DEFAULT (_ETM_ETMTSEVR_RESBEVT_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMTSEVR */
<> 150:02e0a0aed4ec 510 #define _ETM_ETMTSEVR_ETMFCNEVT_SHIFT 14 /**< Shift value for ETM_ETMFCNEVT */
<> 150:02e0a0aed4ec 511 #define _ETM_ETMTSEVR_ETMFCNEVT_MASK 0x1C000UL /**< Bit mask for ETM_ETMFCNEVT */
<> 150:02e0a0aed4ec 512 #define _ETM_ETMTSEVR_ETMFCNEVT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTSEVR */
<> 150:02e0a0aed4ec 513 #define ETM_ETMTSEVR_ETMFCNEVT_DEFAULT (_ETM_ETMTSEVR_ETMFCNEVT_DEFAULT << 14) /**< Shifted mode DEFAULT for ETM_ETMTSEVR */
<> 150:02e0a0aed4ec 514
<> 150:02e0a0aed4ec 515 /* Bit fields for ETM ETMTRACEIDR */
<> 150:02e0a0aed4ec 516 #define _ETM_ETMTRACEIDR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTRACEIDR */
<> 150:02e0a0aed4ec 517 #define _ETM_ETMTRACEIDR_MASK 0x0000007FUL /**< Mask for ETM_ETMTRACEIDR */
<> 150:02e0a0aed4ec 518 #define _ETM_ETMTRACEIDR_TRACEID_SHIFT 0 /**< Shift value for ETM_TRACEID */
<> 150:02e0a0aed4ec 519 #define _ETM_ETMTRACEIDR_TRACEID_MASK 0x7FUL /**< Bit mask for ETM_TRACEID */
<> 150:02e0a0aed4ec 520 #define _ETM_ETMTRACEIDR_TRACEID_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRACEIDR */
<> 150:02e0a0aed4ec 521 #define ETM_ETMTRACEIDR_TRACEID_DEFAULT (_ETM_ETMTRACEIDR_TRACEID_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTRACEIDR */
<> 150:02e0a0aed4ec 522
<> 150:02e0a0aed4ec 523 /* Bit fields for ETM ETMIDR2 */
<> 150:02e0a0aed4ec 524 #define _ETM_ETMIDR2_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMIDR2 */
<> 150:02e0a0aed4ec 525 #define _ETM_ETMIDR2_MASK 0x00000003UL /**< Mask for ETM_ETMIDR2 */
<> 150:02e0a0aed4ec 526 #define ETM_ETMIDR2_RFE (0x1UL << 0) /**< RFE Transfer Order */
<> 150:02e0a0aed4ec 527 #define _ETM_ETMIDR2_RFE_SHIFT 0 /**< Shift value for ETM_RFE */
<> 150:02e0a0aed4ec 528 #define _ETM_ETMIDR2_RFE_MASK 0x1UL /**< Bit mask for ETM_RFE */
<> 150:02e0a0aed4ec 529 #define _ETM_ETMIDR2_RFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR2 */
<> 150:02e0a0aed4ec 530 #define _ETM_ETMIDR2_RFE_PC 0x00000000UL /**< Mode PC for ETM_ETMIDR2 */
<> 150:02e0a0aed4ec 531 #define _ETM_ETMIDR2_RFE_CPSR 0x00000001UL /**< Mode CPSR for ETM_ETMIDR2 */
<> 150:02e0a0aed4ec 532 #define ETM_ETMIDR2_RFE_DEFAULT (_ETM_ETMIDR2_RFE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMIDR2 */
<> 150:02e0a0aed4ec 533 #define ETM_ETMIDR2_RFE_PC (_ETM_ETMIDR2_RFE_PC << 0) /**< Shifted mode PC for ETM_ETMIDR2 */
<> 150:02e0a0aed4ec 534 #define ETM_ETMIDR2_RFE_CPSR (_ETM_ETMIDR2_RFE_CPSR << 0) /**< Shifted mode CPSR for ETM_ETMIDR2 */
<> 150:02e0a0aed4ec 535 #define ETM_ETMIDR2_SWP (0x1UL << 1) /**< SWP Transfer Order */
<> 150:02e0a0aed4ec 536 #define _ETM_ETMIDR2_SWP_SHIFT 1 /**< Shift value for ETM_SWP */
<> 150:02e0a0aed4ec 537 #define _ETM_ETMIDR2_SWP_MASK 0x2UL /**< Bit mask for ETM_SWP */
<> 150:02e0a0aed4ec 538 #define _ETM_ETMIDR2_SWP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR2 */
<> 150:02e0a0aed4ec 539 #define _ETM_ETMIDR2_SWP_LOAD 0x00000000UL /**< Mode LOAD for ETM_ETMIDR2 */
<> 150:02e0a0aed4ec 540 #define _ETM_ETMIDR2_SWP_STORE 0x00000001UL /**< Mode STORE for ETM_ETMIDR2 */
<> 150:02e0a0aed4ec 541 #define ETM_ETMIDR2_SWP_DEFAULT (_ETM_ETMIDR2_SWP_DEFAULT << 1) /**< Shifted mode DEFAULT for ETM_ETMIDR2 */
<> 150:02e0a0aed4ec 542 #define ETM_ETMIDR2_SWP_LOAD (_ETM_ETMIDR2_SWP_LOAD << 1) /**< Shifted mode LOAD for ETM_ETMIDR2 */
<> 150:02e0a0aed4ec 543 #define ETM_ETMIDR2_SWP_STORE (_ETM_ETMIDR2_SWP_STORE << 1) /**< Shifted mode STORE for ETM_ETMIDR2 */
<> 150:02e0a0aed4ec 544
<> 150:02e0a0aed4ec 545 /* Bit fields for ETM ETMPDSR */
<> 150:02e0a0aed4ec 546 #define _ETM_ETMPDSR_RESETVALUE 0x00000001UL /**< Default value for ETM_ETMPDSR */
<> 150:02e0a0aed4ec 547 #define _ETM_ETMPDSR_MASK 0x00000001UL /**< Mask for ETM_ETMPDSR */
<> 150:02e0a0aed4ec 548 #define ETM_ETMPDSR_ETMUP (0x1UL << 0) /**< ETM Powered Up */
<> 150:02e0a0aed4ec 549 #define _ETM_ETMPDSR_ETMUP_SHIFT 0 /**< Shift value for ETM_ETMUP */
<> 150:02e0a0aed4ec 550 #define _ETM_ETMPDSR_ETMUP_MASK 0x1UL /**< Bit mask for ETM_ETMUP */
<> 150:02e0a0aed4ec 551 #define _ETM_ETMPDSR_ETMUP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMPDSR */
<> 150:02e0a0aed4ec 552 #define ETM_ETMPDSR_ETMUP_DEFAULT (_ETM_ETMPDSR_ETMUP_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPDSR */
<> 150:02e0a0aed4ec 553
<> 150:02e0a0aed4ec 554 /* Bit fields for ETM ETMISCIN */
<> 150:02e0a0aed4ec 555 #define _ETM_ETMISCIN_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMISCIN */
<> 150:02e0a0aed4ec 556 #define _ETM_ETMISCIN_MASK 0x00000013UL /**< Mask for ETM_ETMISCIN */
<> 150:02e0a0aed4ec 557 #define _ETM_ETMISCIN_EXTIN_SHIFT 0 /**< Shift value for ETM_EXTIN */
<> 150:02e0a0aed4ec 558 #define _ETM_ETMISCIN_EXTIN_MASK 0x3UL /**< Bit mask for ETM_EXTIN */
<> 150:02e0a0aed4ec 559 #define _ETM_ETMISCIN_EXTIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMISCIN */
<> 150:02e0a0aed4ec 560 #define ETM_ETMISCIN_EXTIN_DEFAULT (_ETM_ETMISCIN_EXTIN_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMISCIN */
<> 150:02e0a0aed4ec 561 #define ETM_ETMISCIN_COREHALT (0x1UL << 4) /**< Core Halt */
<> 150:02e0a0aed4ec 562 #define _ETM_ETMISCIN_COREHALT_SHIFT 4 /**< Shift value for ETM_COREHALT */
<> 150:02e0a0aed4ec 563 #define _ETM_ETMISCIN_COREHALT_MASK 0x10UL /**< Bit mask for ETM_COREHALT */
<> 150:02e0a0aed4ec 564 #define _ETM_ETMISCIN_COREHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMISCIN */
<> 150:02e0a0aed4ec 565 #define ETM_ETMISCIN_COREHALT_DEFAULT (_ETM_ETMISCIN_COREHALT_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMISCIN */
<> 150:02e0a0aed4ec 566
<> 150:02e0a0aed4ec 567 /* Bit fields for ETM ITTRIGOUT */
<> 150:02e0a0aed4ec 568 #define _ETM_ITTRIGOUT_RESETVALUE 0x00000000UL /**< Default value for ETM_ITTRIGOUT */
<> 150:02e0a0aed4ec 569 #define _ETM_ITTRIGOUT_MASK 0x00000001UL /**< Mask for ETM_ITTRIGOUT */
<> 150:02e0a0aed4ec 570 #define ETM_ITTRIGOUT_TRIGGEROUT (0x1UL << 0) /**< Trigger output value */
<> 150:02e0a0aed4ec 571 #define _ETM_ITTRIGOUT_TRIGGEROUT_SHIFT 0 /**< Shift value for ETM_TRIGGEROUT */
<> 150:02e0a0aed4ec 572 #define _ETM_ITTRIGOUT_TRIGGEROUT_MASK 0x1UL /**< Bit mask for ETM_TRIGGEROUT */
<> 150:02e0a0aed4ec 573 #define _ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ITTRIGOUT */
<> 150:02e0a0aed4ec 574 #define ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT (_ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ITTRIGOUT */
<> 150:02e0a0aed4ec 575
<> 150:02e0a0aed4ec 576 /* Bit fields for ETM ETMITATBCTR2 */
<> 150:02e0a0aed4ec 577 #define _ETM_ETMITATBCTR2_RESETVALUE 0x00000001UL /**< Default value for ETM_ETMITATBCTR2 */
<> 150:02e0a0aed4ec 578 #define _ETM_ETMITATBCTR2_MASK 0x00000001UL /**< Mask for ETM_ETMITATBCTR2 */
<> 150:02e0a0aed4ec 579 #define ETM_ETMITATBCTR2_ATREADY (0x1UL << 0) /**< ATREADY Input Value */
<> 150:02e0a0aed4ec 580 #define _ETM_ETMITATBCTR2_ATREADY_SHIFT 0 /**< Shift value for ETM_ATREADY */
<> 150:02e0a0aed4ec 581 #define _ETM_ETMITATBCTR2_ATREADY_MASK 0x1UL /**< Bit mask for ETM_ATREADY */
<> 150:02e0a0aed4ec 582 #define _ETM_ETMITATBCTR2_ATREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMITATBCTR2 */
<> 150:02e0a0aed4ec 583 #define ETM_ETMITATBCTR2_ATREADY_DEFAULT (_ETM_ETMITATBCTR2_ATREADY_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMITATBCTR2 */
<> 150:02e0a0aed4ec 584
<> 150:02e0a0aed4ec 585 /* Bit fields for ETM ETMITATBCTR0 */
<> 150:02e0a0aed4ec 586 #define _ETM_ETMITATBCTR0_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMITATBCTR0 */
<> 150:02e0a0aed4ec 587 #define _ETM_ETMITATBCTR0_MASK 0x00000001UL /**< Mask for ETM_ETMITATBCTR0 */
<> 150:02e0a0aed4ec 588 #define ETM_ETMITATBCTR0_ATVALID (0x1UL << 0) /**< ATVALID Output Value */
<> 150:02e0a0aed4ec 589 #define _ETM_ETMITATBCTR0_ATVALID_SHIFT 0 /**< Shift value for ETM_ATVALID */
<> 150:02e0a0aed4ec 590 #define _ETM_ETMITATBCTR0_ATVALID_MASK 0x1UL /**< Bit mask for ETM_ATVALID */
<> 150:02e0a0aed4ec 591 #define _ETM_ETMITATBCTR0_ATVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMITATBCTR0 */
<> 150:02e0a0aed4ec 592 #define ETM_ETMITATBCTR0_ATVALID_DEFAULT (_ETM_ETMITATBCTR0_ATVALID_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMITATBCTR0 */
<> 150:02e0a0aed4ec 593
<> 150:02e0a0aed4ec 594 /* Bit fields for ETM ETMITCTRL */
<> 150:02e0a0aed4ec 595 #define _ETM_ETMITCTRL_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMITCTRL */
<> 150:02e0a0aed4ec 596 #define _ETM_ETMITCTRL_MASK 0x00000001UL /**< Mask for ETM_ETMITCTRL */
<> 150:02e0a0aed4ec 597 #define ETM_ETMITCTRL_ITEN (0x1UL << 0) /**< Integration Mode Enable */
<> 150:02e0a0aed4ec 598 #define _ETM_ETMITCTRL_ITEN_SHIFT 0 /**< Shift value for ETM_ITEN */
<> 150:02e0a0aed4ec 599 #define _ETM_ETMITCTRL_ITEN_MASK 0x1UL /**< Bit mask for ETM_ITEN */
<> 150:02e0a0aed4ec 600 #define _ETM_ETMITCTRL_ITEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMITCTRL */
<> 150:02e0a0aed4ec 601 #define ETM_ETMITCTRL_ITEN_DEFAULT (_ETM_ETMITCTRL_ITEN_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMITCTRL */
<> 150:02e0a0aed4ec 602
<> 150:02e0a0aed4ec 603 /* Bit fields for ETM ETMCLAIMSET */
<> 150:02e0a0aed4ec 604 #define _ETM_ETMCLAIMSET_RESETVALUE 0x0000000FUL /**< Default value for ETM_ETMCLAIMSET */
<> 150:02e0a0aed4ec 605 #define _ETM_ETMCLAIMSET_MASK 0x000000FFUL /**< Mask for ETM_ETMCLAIMSET */
<> 150:02e0a0aed4ec 606 #define _ETM_ETMCLAIMSET_SETTAG_SHIFT 0 /**< Shift value for ETM_SETTAG */
<> 150:02e0a0aed4ec 607 #define _ETM_ETMCLAIMSET_SETTAG_MASK 0xFFUL /**< Bit mask for ETM_SETTAG */
<> 150:02e0a0aed4ec 608 #define _ETM_ETMCLAIMSET_SETTAG_DEFAULT 0x0000000FUL /**< Mode DEFAULT for ETM_ETMCLAIMSET */
<> 150:02e0a0aed4ec 609 #define ETM_ETMCLAIMSET_SETTAG_DEFAULT (_ETM_ETMCLAIMSET_SETTAG_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCLAIMSET */
<> 150:02e0a0aed4ec 610
<> 150:02e0a0aed4ec 611 /* Bit fields for ETM ETMCLAIMCLR */
<> 150:02e0a0aed4ec 612 #define _ETM_ETMCLAIMCLR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMCLAIMCLR */
<> 150:02e0a0aed4ec 613 #define _ETM_ETMCLAIMCLR_MASK 0x00000001UL /**< Mask for ETM_ETMCLAIMCLR */
<> 150:02e0a0aed4ec 614 #define ETM_ETMCLAIMCLR_CLRTAG (0x1UL << 0) /**< Tag Bits */
<> 150:02e0a0aed4ec 615 #define _ETM_ETMCLAIMCLR_CLRTAG_SHIFT 0 /**< Shift value for ETM_CLRTAG */
<> 150:02e0a0aed4ec 616 #define _ETM_ETMCLAIMCLR_CLRTAG_MASK 0x1UL /**< Bit mask for ETM_CLRTAG */
<> 150:02e0a0aed4ec 617 #define _ETM_ETMCLAIMCLR_CLRTAG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCLAIMCLR */
<> 150:02e0a0aed4ec 618 #define ETM_ETMCLAIMCLR_CLRTAG_DEFAULT (_ETM_ETMCLAIMCLR_CLRTAG_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCLAIMCLR */
<> 150:02e0a0aed4ec 619
<> 150:02e0a0aed4ec 620 /* Bit fields for ETM ETMLAR */
<> 150:02e0a0aed4ec 621 #define _ETM_ETMLAR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMLAR */
<> 150:02e0a0aed4ec 622 #define _ETM_ETMLAR_MASK 0x00000001UL /**< Mask for ETM_ETMLAR */
<> 150:02e0a0aed4ec 623 #define ETM_ETMLAR_KEY (0x1UL << 0) /**< Key Value */
<> 150:02e0a0aed4ec 624 #define _ETM_ETMLAR_KEY_SHIFT 0 /**< Shift value for ETM_KEY */
<> 150:02e0a0aed4ec 625 #define _ETM_ETMLAR_KEY_MASK 0x1UL /**< Bit mask for ETM_KEY */
<> 150:02e0a0aed4ec 626 #define _ETM_ETMLAR_KEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMLAR */
<> 150:02e0a0aed4ec 627 #define ETM_ETMLAR_KEY_DEFAULT (_ETM_ETMLAR_KEY_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMLAR */
<> 150:02e0a0aed4ec 628
<> 150:02e0a0aed4ec 629 /* Bit fields for ETM ETMLSR */
<> 150:02e0a0aed4ec 630 #define _ETM_ETMLSR_RESETVALUE 0x00000003UL /**< Default value for ETM_ETMLSR */
<> 150:02e0a0aed4ec 631 #define _ETM_ETMLSR_MASK 0x00000003UL /**< Mask for ETM_ETMLSR */
<> 150:02e0a0aed4ec 632 #define ETM_ETMLSR_LOCKIMP (0x1UL << 0) /**< ETM Locking Implemented */
<> 150:02e0a0aed4ec 633 #define _ETM_ETMLSR_LOCKIMP_SHIFT 0 /**< Shift value for ETM_LOCKIMP */
<> 150:02e0a0aed4ec 634 #define _ETM_ETMLSR_LOCKIMP_MASK 0x1UL /**< Bit mask for ETM_LOCKIMP */
<> 150:02e0a0aed4ec 635 #define _ETM_ETMLSR_LOCKIMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMLSR */
<> 150:02e0a0aed4ec 636 #define ETM_ETMLSR_LOCKIMP_DEFAULT (_ETM_ETMLSR_LOCKIMP_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMLSR */
<> 150:02e0a0aed4ec 637 #define ETM_ETMLSR_LOCKED (0x1UL << 1) /**< ETM locked */
<> 150:02e0a0aed4ec 638 #define _ETM_ETMLSR_LOCKED_SHIFT 1 /**< Shift value for ETM_LOCKED */
<> 150:02e0a0aed4ec 639 #define _ETM_ETMLSR_LOCKED_MASK 0x2UL /**< Bit mask for ETM_LOCKED */
<> 150:02e0a0aed4ec 640 #define _ETM_ETMLSR_LOCKED_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMLSR */
<> 150:02e0a0aed4ec 641 #define ETM_ETMLSR_LOCKED_DEFAULT (_ETM_ETMLSR_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for ETM_ETMLSR */
<> 150:02e0a0aed4ec 642
<> 150:02e0a0aed4ec 643 /* Bit fields for ETM ETMAUTHSTATUS */
<> 150:02e0a0aed4ec 644 #define _ETM_ETMAUTHSTATUS_RESETVALUE 0x000000C0UL /**< Default value for ETM_ETMAUTHSTATUS */
<> 150:02e0a0aed4ec 645 #define _ETM_ETMAUTHSTATUS_MASK 0x000000FFUL /**< Mask for ETM_ETMAUTHSTATUS */
<> 150:02e0a0aed4ec 646 #define _ETM_ETMAUTHSTATUS_NONSECINVDBG_SHIFT 0 /**< Shift value for ETM_NONSECINVDBG */
<> 150:02e0a0aed4ec 647 #define _ETM_ETMAUTHSTATUS_NONSECINVDBG_MASK 0x3UL /**< Bit mask for ETM_NONSECINVDBG */
<> 150:02e0a0aed4ec 648 #define _ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */
<> 150:02e0a0aed4ec 649 #define ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */
<> 150:02e0a0aed4ec 650 #define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_SHIFT 2 /**< Shift value for ETM_NONSECNONINVDBG */
<> 150:02e0a0aed4ec 651 #define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_MASK 0xCUL /**< Bit mask for ETM_NONSECNONINVDBG */
<> 150:02e0a0aed4ec 652 #define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */
<> 150:02e0a0aed4ec 653 #define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE 0x00000002UL /**< Mode DISABLE for ETM_ETMAUTHSTATUS */
<> 150:02e0a0aed4ec 654 #define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE 0x00000003UL /**< Mode ENABLE for ETM_ETMAUTHSTATUS */
<> 150:02e0a0aed4ec 655 #define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT << 2) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */
<> 150:02e0a0aed4ec 656 #define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE << 2) /**< Shifted mode DISABLE for ETM_ETMAUTHSTATUS */
<> 150:02e0a0aed4ec 657 #define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE << 2) /**< Shifted mode ENABLE for ETM_ETMAUTHSTATUS */
<> 150:02e0a0aed4ec 658 #define _ETM_ETMAUTHSTATUS_SECINVDBG_SHIFT 4 /**< Shift value for ETM_SECINVDBG */
<> 150:02e0a0aed4ec 659 #define _ETM_ETMAUTHSTATUS_SECINVDBG_MASK 0x30UL /**< Bit mask for ETM_SECINVDBG */
<> 150:02e0a0aed4ec 660 #define _ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */
<> 150:02e0a0aed4ec 661 #define ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */
<> 150:02e0a0aed4ec 662 #define _ETM_ETMAUTHSTATUS_SECNONINVDBG_SHIFT 6 /**< Shift value for ETM_SECNONINVDBG */
<> 150:02e0a0aed4ec 663 #define _ETM_ETMAUTHSTATUS_SECNONINVDBG_MASK 0xC0UL /**< Bit mask for ETM_SECNONINVDBG */
<> 150:02e0a0aed4ec 664 #define _ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */
<> 150:02e0a0aed4ec 665 #define ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT << 6) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */
<> 150:02e0a0aed4ec 666
<> 150:02e0a0aed4ec 667 /* Bit fields for ETM ETMDEVTYPE */
<> 150:02e0a0aed4ec 668 #define _ETM_ETMDEVTYPE_RESETVALUE 0x00000013UL /**< Default value for ETM_ETMDEVTYPE */
<> 150:02e0a0aed4ec 669 #define _ETM_ETMDEVTYPE_MASK 0x000000FFUL /**< Mask for ETM_ETMDEVTYPE */
<> 150:02e0a0aed4ec 670 #define _ETM_ETMDEVTYPE_TRACESRC_SHIFT 0 /**< Shift value for ETM_TRACESRC */
<> 150:02e0a0aed4ec 671 #define _ETM_ETMDEVTYPE_TRACESRC_MASK 0xFUL /**< Bit mask for ETM_TRACESRC */
<> 150:02e0a0aed4ec 672 #define _ETM_ETMDEVTYPE_TRACESRC_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMDEVTYPE */
<> 150:02e0a0aed4ec 673 #define ETM_ETMDEVTYPE_TRACESRC_DEFAULT (_ETM_ETMDEVTYPE_TRACESRC_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMDEVTYPE */
<> 150:02e0a0aed4ec 674 #define _ETM_ETMDEVTYPE_PROCTRACE_SHIFT 4 /**< Shift value for ETM_PROCTRACE */
<> 150:02e0a0aed4ec 675 #define _ETM_ETMDEVTYPE_PROCTRACE_MASK 0xF0UL /**< Bit mask for ETM_PROCTRACE */
<> 150:02e0a0aed4ec 676 #define _ETM_ETMDEVTYPE_PROCTRACE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMDEVTYPE */
<> 150:02e0a0aed4ec 677 #define ETM_ETMDEVTYPE_PROCTRACE_DEFAULT (_ETM_ETMDEVTYPE_PROCTRACE_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMDEVTYPE */
<> 150:02e0a0aed4ec 678
<> 150:02e0a0aed4ec 679 /* Bit fields for ETM ETMPIDR4 */
<> 150:02e0a0aed4ec 680 #define _ETM_ETMPIDR4_RESETVALUE 0x00000004UL /**< Default value for ETM_ETMPIDR4 */
<> 150:02e0a0aed4ec 681 #define _ETM_ETMPIDR4_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR4 */
<> 150:02e0a0aed4ec 682 #define _ETM_ETMPIDR4_CONTCODE_SHIFT 0 /**< Shift value for ETM_CONTCODE */
<> 150:02e0a0aed4ec 683 #define _ETM_ETMPIDR4_CONTCODE_MASK 0xFUL /**< Bit mask for ETM_CONTCODE */
<> 150:02e0a0aed4ec 684 #define _ETM_ETMPIDR4_CONTCODE_DEFAULT 0x00000004UL /**< Mode DEFAULT for ETM_ETMPIDR4 */
<> 150:02e0a0aed4ec 685 #define ETM_ETMPIDR4_CONTCODE_DEFAULT (_ETM_ETMPIDR4_CONTCODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR4 */
<> 150:02e0a0aed4ec 686 #define _ETM_ETMPIDR4_COUNT_SHIFT 4 /**< Shift value for ETM_COUNT */
<> 150:02e0a0aed4ec 687 #define _ETM_ETMPIDR4_COUNT_MASK 0xF0UL /**< Bit mask for ETM_COUNT */
<> 150:02e0a0aed4ec 688 #define _ETM_ETMPIDR4_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR4 */
<> 150:02e0a0aed4ec 689 #define ETM_ETMPIDR4_COUNT_DEFAULT (_ETM_ETMPIDR4_COUNT_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR4 */
<> 150:02e0a0aed4ec 690
<> 150:02e0a0aed4ec 691 /* Bit fields for ETM ETMPIDR5 */
<> 150:02e0a0aed4ec 692 #define _ETM_ETMPIDR5_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR5 */
<> 150:02e0a0aed4ec 693 #define _ETM_ETMPIDR5_MASK 0x00000000UL /**< Mask for ETM_ETMPIDR5 */
<> 150:02e0a0aed4ec 694
<> 150:02e0a0aed4ec 695 /* Bit fields for ETM ETMPIDR6 */
<> 150:02e0a0aed4ec 696 #define _ETM_ETMPIDR6_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR6 */
<> 150:02e0a0aed4ec 697 #define _ETM_ETMPIDR6_MASK 0x00000000UL /**< Mask for ETM_ETMPIDR6 */
<> 150:02e0a0aed4ec 698
<> 150:02e0a0aed4ec 699 /* Bit fields for ETM ETMPIDR7 */
<> 150:02e0a0aed4ec 700 #define _ETM_ETMPIDR7_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR7 */
<> 150:02e0a0aed4ec 701 #define _ETM_ETMPIDR7_MASK 0x00000000UL /**< Mask for ETM_ETMPIDR7 */
<> 150:02e0a0aed4ec 702
<> 150:02e0a0aed4ec 703 /* Bit fields for ETM ETMPIDR0 */
<> 150:02e0a0aed4ec 704 #define _ETM_ETMPIDR0_RESETVALUE 0x00000024UL /**< Default value for ETM_ETMPIDR0 */
<> 150:02e0a0aed4ec 705 #define _ETM_ETMPIDR0_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR0 */
<> 150:02e0a0aed4ec 706 #define _ETM_ETMPIDR0_PARTNUM_SHIFT 0 /**< Shift value for ETM_PARTNUM */
<> 150:02e0a0aed4ec 707 #define _ETM_ETMPIDR0_PARTNUM_MASK 0xFFUL /**< Bit mask for ETM_PARTNUM */
<> 150:02e0a0aed4ec 708 #define _ETM_ETMPIDR0_PARTNUM_DEFAULT 0x00000024UL /**< Mode DEFAULT for ETM_ETMPIDR0 */
<> 150:02e0a0aed4ec 709 #define ETM_ETMPIDR0_PARTNUM_DEFAULT (_ETM_ETMPIDR0_PARTNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR0 */
<> 150:02e0a0aed4ec 710
<> 150:02e0a0aed4ec 711 /* Bit fields for ETM ETMPIDR1 */
<> 150:02e0a0aed4ec 712 #define _ETM_ETMPIDR1_RESETVALUE 0x000000B9UL /**< Default value for ETM_ETMPIDR1 */
<> 150:02e0a0aed4ec 713 #define _ETM_ETMPIDR1_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR1 */
<> 150:02e0a0aed4ec 714 #define _ETM_ETMPIDR1_PARTNUM_SHIFT 0 /**< Shift value for ETM_PARTNUM */
<> 150:02e0a0aed4ec 715 #define _ETM_ETMPIDR1_PARTNUM_MASK 0xFUL /**< Bit mask for ETM_PARTNUM */
<> 150:02e0a0aed4ec 716 #define _ETM_ETMPIDR1_PARTNUM_DEFAULT 0x00000009UL /**< Mode DEFAULT for ETM_ETMPIDR1 */
<> 150:02e0a0aed4ec 717 #define ETM_ETMPIDR1_PARTNUM_DEFAULT (_ETM_ETMPIDR1_PARTNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR1 */
<> 150:02e0a0aed4ec 718 #define _ETM_ETMPIDR1_IDCODE_SHIFT 4 /**< Shift value for ETM_IDCODE */
<> 150:02e0a0aed4ec 719 #define _ETM_ETMPIDR1_IDCODE_MASK 0xF0UL /**< Bit mask for ETM_IDCODE */
<> 150:02e0a0aed4ec 720 #define _ETM_ETMPIDR1_IDCODE_DEFAULT 0x0000000BUL /**< Mode DEFAULT for ETM_ETMPIDR1 */
<> 150:02e0a0aed4ec 721 #define ETM_ETMPIDR1_IDCODE_DEFAULT (_ETM_ETMPIDR1_IDCODE_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR1 */
<> 150:02e0a0aed4ec 722
<> 150:02e0a0aed4ec 723 /* Bit fields for ETM ETMPIDR2 */
<> 150:02e0a0aed4ec 724 #define _ETM_ETMPIDR2_RESETVALUE 0x0000003BUL /**< Default value for ETM_ETMPIDR2 */
<> 150:02e0a0aed4ec 725 #define _ETM_ETMPIDR2_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR2 */
<> 150:02e0a0aed4ec 726 #define _ETM_ETMPIDR2_IDCODE_SHIFT 0 /**< Shift value for ETM_IDCODE */
<> 150:02e0a0aed4ec 727 #define _ETM_ETMPIDR2_IDCODE_MASK 0x7UL /**< Bit mask for ETM_IDCODE */
<> 150:02e0a0aed4ec 728 #define _ETM_ETMPIDR2_IDCODE_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMPIDR2 */
<> 150:02e0a0aed4ec 729 #define ETM_ETMPIDR2_IDCODE_DEFAULT (_ETM_ETMPIDR2_IDCODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR2 */
<> 150:02e0a0aed4ec 730 #define ETM_ETMPIDR2_ALWAYS1 (0x1UL << 3) /**< Always 1 */
<> 150:02e0a0aed4ec 731 #define _ETM_ETMPIDR2_ALWAYS1_SHIFT 3 /**< Shift value for ETM_ALWAYS1 */
<> 150:02e0a0aed4ec 732 #define _ETM_ETMPIDR2_ALWAYS1_MASK 0x8UL /**< Bit mask for ETM_ALWAYS1 */
<> 150:02e0a0aed4ec 733 #define _ETM_ETMPIDR2_ALWAYS1_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMPIDR2 */
<> 150:02e0a0aed4ec 734 #define ETM_ETMPIDR2_ALWAYS1_DEFAULT (_ETM_ETMPIDR2_ALWAYS1_DEFAULT << 3) /**< Shifted mode DEFAULT for ETM_ETMPIDR2 */
<> 150:02e0a0aed4ec 735 #define _ETM_ETMPIDR2_REV_SHIFT 4 /**< Shift value for ETM_REV */
<> 150:02e0a0aed4ec 736 #define _ETM_ETMPIDR2_REV_MASK 0xF0UL /**< Bit mask for ETM_REV */
<> 150:02e0a0aed4ec 737 #define _ETM_ETMPIDR2_REV_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMPIDR2 */
<> 150:02e0a0aed4ec 738 #define ETM_ETMPIDR2_REV_DEFAULT (_ETM_ETMPIDR2_REV_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR2 */
<> 150:02e0a0aed4ec 739
<> 150:02e0a0aed4ec 740 /* Bit fields for ETM ETMPIDR3 */
<> 150:02e0a0aed4ec 741 #define _ETM_ETMPIDR3_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR3 */
<> 150:02e0a0aed4ec 742 #define _ETM_ETMPIDR3_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR3 */
<> 150:02e0a0aed4ec 743 #define _ETM_ETMPIDR3_CUSTMOD_SHIFT 0 /**< Shift value for ETM_CUSTMOD */
<> 150:02e0a0aed4ec 744 #define _ETM_ETMPIDR3_CUSTMOD_MASK 0xFUL /**< Bit mask for ETM_CUSTMOD */
<> 150:02e0a0aed4ec 745 #define _ETM_ETMPIDR3_CUSTMOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR3 */
<> 150:02e0a0aed4ec 746 #define ETM_ETMPIDR3_CUSTMOD_DEFAULT (_ETM_ETMPIDR3_CUSTMOD_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR3 */
<> 150:02e0a0aed4ec 747 #define _ETM_ETMPIDR3_REVAND_SHIFT 4 /**< Shift value for ETM_REVAND */
<> 150:02e0a0aed4ec 748 #define _ETM_ETMPIDR3_REVAND_MASK 0xF0UL /**< Bit mask for ETM_REVAND */
<> 150:02e0a0aed4ec 749 #define _ETM_ETMPIDR3_REVAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR3 */
<> 150:02e0a0aed4ec 750 #define ETM_ETMPIDR3_REVAND_DEFAULT (_ETM_ETMPIDR3_REVAND_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR3 */
<> 150:02e0a0aed4ec 751
<> 150:02e0a0aed4ec 752 /* Bit fields for ETM ETMCIDR0 */
<> 150:02e0a0aed4ec 753 #define _ETM_ETMCIDR0_RESETVALUE 0x0000000DUL /**< Default value for ETM_ETMCIDR0 */
<> 150:02e0a0aed4ec 754 #define _ETM_ETMCIDR0_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR0 */
<> 150:02e0a0aed4ec 755 #define _ETM_ETMCIDR0_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */
<> 150:02e0a0aed4ec 756 #define _ETM_ETMCIDR0_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */
<> 150:02e0a0aed4ec 757 #define _ETM_ETMCIDR0_PREAMB_DEFAULT 0x0000000DUL /**< Mode DEFAULT for ETM_ETMCIDR0 */
<> 150:02e0a0aed4ec 758 #define ETM_ETMCIDR0_PREAMB_DEFAULT (_ETM_ETMCIDR0_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR0 */
<> 150:02e0a0aed4ec 759
<> 150:02e0a0aed4ec 760 /* Bit fields for ETM ETMCIDR1 */
<> 150:02e0a0aed4ec 761 #define _ETM_ETMCIDR1_RESETVALUE 0x00000090UL /**< Default value for ETM_ETMCIDR1 */
<> 150:02e0a0aed4ec 762 #define _ETM_ETMCIDR1_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR1 */
<> 150:02e0a0aed4ec 763 #define _ETM_ETMCIDR1_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */
<> 150:02e0a0aed4ec 764 #define _ETM_ETMCIDR1_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */
<> 150:02e0a0aed4ec 765 #define _ETM_ETMCIDR1_PREAMB_DEFAULT 0x00000090UL /**< Mode DEFAULT for ETM_ETMCIDR1 */
<> 150:02e0a0aed4ec 766 #define ETM_ETMCIDR1_PREAMB_DEFAULT (_ETM_ETMCIDR1_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR1 */
<> 150:02e0a0aed4ec 767
<> 150:02e0a0aed4ec 768 /* Bit fields for ETM ETMCIDR2 */
<> 150:02e0a0aed4ec 769 #define _ETM_ETMCIDR2_RESETVALUE 0x00000005UL /**< Default value for ETM_ETMCIDR2 */
<> 150:02e0a0aed4ec 770 #define _ETM_ETMCIDR2_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR2 */
<> 150:02e0a0aed4ec 771 #define _ETM_ETMCIDR2_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */
<> 150:02e0a0aed4ec 772 #define _ETM_ETMCIDR2_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */
<> 150:02e0a0aed4ec 773 #define _ETM_ETMCIDR2_PREAMB_DEFAULT 0x00000005UL /**< Mode DEFAULT for ETM_ETMCIDR2 */
<> 150:02e0a0aed4ec 774 #define ETM_ETMCIDR2_PREAMB_DEFAULT (_ETM_ETMCIDR2_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR2 */
<> 150:02e0a0aed4ec 775
<> 150:02e0a0aed4ec 776 /* Bit fields for ETM ETMCIDR3 */
<> 150:02e0a0aed4ec 777 #define _ETM_ETMCIDR3_RESETVALUE 0x000000B1UL /**< Default value for ETM_ETMCIDR3 */
<> 150:02e0a0aed4ec 778 #define _ETM_ETMCIDR3_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR3 */
<> 150:02e0a0aed4ec 779 #define _ETM_ETMCIDR3_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */
<> 150:02e0a0aed4ec 780 #define _ETM_ETMCIDR3_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */
<> 150:02e0a0aed4ec 781 #define _ETM_ETMCIDR3_PREAMB_DEFAULT 0x000000B1UL /**< Mode DEFAULT for ETM_ETMCIDR3 */
<> 150:02e0a0aed4ec 782 #define ETM_ETMCIDR3_PREAMB_DEFAULT (_ETM_ETMCIDR3_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR3 */
<> 150:02e0a0aed4ec 783
<> 150:02e0a0aed4ec 784 /** @} End of group EFM32WG_ETM */
<> 150:02e0a0aed4ec 785 /** @} End of group Parts */
<> 150:02e0a0aed4ec 786