Fawwaz Nadzmy / mbed-STM

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_dmareq.h@153:9398a535854b, 2016-12-22 (annotated)

Committer:
fwndz
Date:
Thu Dec 22 05:12:40 2016 +0000
Revision:
153:9398a535854b
Parent:
150:02e0a0aed4ec 
device target maximize

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 150:02e0a0aed4ec 1 /**************************************************************************//**
<> 150:02e0a0aed4ec 2 * @file efm32wg_dmareq.h
<> 150:02e0a0aed4ec 3 * @brief EFM32WG_DMAREQ register and bit field definitions
<> 150:02e0a0aed4ec 4 * @version 5.0.0
<> 150:02e0a0aed4ec 5 ******************************************************************************
<> 150:02e0a0aed4ec 6 * @section License
<> 150:02e0a0aed4ec 7 * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 150:02e0a0aed4ec 8 ******************************************************************************
<> 150:02e0a0aed4ec 9 *
<> 150:02e0a0aed4ec 10 * Permission is granted to anyone to use this software for any purpose,
<> 150:02e0a0aed4ec 11 * including commercial applications, and to alter it and redistribute it
<> 150:02e0a0aed4ec 12 * freely, subject to the following restrictions:
<> 150:02e0a0aed4ec 13 *
<> 150:02e0a0aed4ec 14 * 1. The origin of this software must not be misrepresented; you must not
<> 150:02e0a0aed4ec 15 * claim that you wrote the original software.@n
<> 150:02e0a0aed4ec 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 150:02e0a0aed4ec 17 * misrepresented as being the original software.@n
<> 150:02e0a0aed4ec 18 * 3. This notice may not be removed or altered from any source distribution.
<> 150:02e0a0aed4ec 19 *
<> 150:02e0a0aed4ec 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 150:02e0a0aed4ec 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 150:02e0a0aed4ec 22 * providing the Software "AS IS", with no express or implied warranties of any
<> 150:02e0a0aed4ec 23 * kind, including, but not limited to, any implied warranties of
<> 150:02e0a0aed4ec 24 * merchantability or fitness for any particular purpose or warranties against
<> 150:02e0a0aed4ec 25 * infringement of any proprietary rights of a third party.
<> 150:02e0a0aed4ec 26 *
<> 150:02e0a0aed4ec 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 150:02e0a0aed4ec 28 * incidental, or special damages, or any other relief, or for any claim by
<> 150:02e0a0aed4ec 29 * any third party, arising from your use of this Software.
<> 150:02e0a0aed4ec 30 *
<> 150:02e0a0aed4ec 31 *****************************************************************************/
<> 150:02e0a0aed4ec 32 /**************************************************************************//**
<> 150:02e0a0aed4ec 33 * @addtogroup Parts
<> 150:02e0a0aed4ec 34 * @{
<> 150:02e0a0aed4ec 35 ******************************************************************************/
<> 150:02e0a0aed4ec 36
<> 150:02e0a0aed4ec 37 /**************************************************************************//**
<> 150:02e0a0aed4ec 38 * @defgroup EFM32WG_DMAREQ_BitFields
<> 150:02e0a0aed4ec 39 * @{
<> 150:02e0a0aed4ec 40 *****************************************************************************/
<> 150:02e0a0aed4ec 41 #define DMAREQ_ADC0_SINGLE ((8 << 16) + 0) /**< DMA channel select for ADC0_SINGLE */
<> 150:02e0a0aed4ec 42 #define DMAREQ_ADC0_SCAN ((8 << 16) + 1) /**< DMA channel select for ADC0_SCAN */
<> 150:02e0a0aed4ec 43 #define DMAREQ_DAC0_CH0 ((10 << 16) + 0) /**< DMA channel select for DAC0_CH0 */
<> 150:02e0a0aed4ec 44 #define DMAREQ_DAC0_CH1 ((10 << 16) + 1) /**< DMA channel select for DAC0_CH1 */
<> 150:02e0a0aed4ec 45 #define DMAREQ_USART0_RXDATAV ((12 << 16) + 0) /**< DMA channel select for USART0_RXDATAV */
<> 150:02e0a0aed4ec 46 #define DMAREQ_USART0_TXBL ((12 << 16) + 1) /**< DMA channel select for USART0_TXBL */
<> 150:02e0a0aed4ec 47 #define DMAREQ_USART0_TXEMPTY ((12 << 16) + 2) /**< DMA channel select for USART0_TXEMPTY */
<> 150:02e0a0aed4ec 48 #define DMAREQ_USART1_RXDATAV ((13 << 16) + 0) /**< DMA channel select for USART1_RXDATAV */
<> 150:02e0a0aed4ec 49 #define DMAREQ_USART1_TXBL ((13 << 16) + 1) /**< DMA channel select for USART1_TXBL */
<> 150:02e0a0aed4ec 50 #define DMAREQ_USART1_TXEMPTY ((13 << 16) + 2) /**< DMA channel select for USART1_TXEMPTY */
<> 150:02e0a0aed4ec 51 #define DMAREQ_USART1_RXDATAVRIGHT ((13 << 16) + 3) /**< DMA channel select for USART1_RXDATAVRIGHT */
<> 150:02e0a0aed4ec 52 #define DMAREQ_USART1_TXBLRIGHT ((13 << 16) + 4) /**< DMA channel select for USART1_TXBLRIGHT */
<> 150:02e0a0aed4ec 53 #define DMAREQ_USART2_RXDATAV ((14 << 16) + 0) /**< DMA channel select for USART2_RXDATAV */
<> 150:02e0a0aed4ec 54 #define DMAREQ_USART2_TXBL ((14 << 16) + 1) /**< DMA channel select for USART2_TXBL */
<> 150:02e0a0aed4ec 55 #define DMAREQ_USART2_TXEMPTY ((14 << 16) + 2) /**< DMA channel select for USART2_TXEMPTY */
<> 150:02e0a0aed4ec 56 #define DMAREQ_USART2_RXDATAVRIGHT ((14 << 16) + 3) /**< DMA channel select for USART2_RXDATAVRIGHT */
<> 150:02e0a0aed4ec 57 #define DMAREQ_USART2_TXBLRIGHT ((14 << 16) + 4) /**< DMA channel select for USART2_TXBLRIGHT */
<> 150:02e0a0aed4ec 58 #define DMAREQ_LEUART0_RXDATAV ((16 << 16) + 0) /**< DMA channel select for LEUART0_RXDATAV */
<> 150:02e0a0aed4ec 59 #define DMAREQ_LEUART0_TXBL ((16 << 16) + 1) /**< DMA channel select for LEUART0_TXBL */
<> 150:02e0a0aed4ec 60 #define DMAREQ_LEUART0_TXEMPTY ((16 << 16) + 2) /**< DMA channel select for LEUART0_TXEMPTY */
<> 150:02e0a0aed4ec 61 #define DMAREQ_LEUART1_RXDATAV ((17 << 16) + 0) /**< DMA channel select for LEUART1_RXDATAV */
<> 150:02e0a0aed4ec 62 #define DMAREQ_LEUART1_TXBL ((17 << 16) + 1) /**< DMA channel select for LEUART1_TXBL */
<> 150:02e0a0aed4ec 63 #define DMAREQ_LEUART1_TXEMPTY ((17 << 16) + 2) /**< DMA channel select for LEUART1_TXEMPTY */
<> 150:02e0a0aed4ec 64 #define DMAREQ_I2C0_RXDATAV ((20 << 16) + 0) /**< DMA channel select for I2C0_RXDATAV */
<> 150:02e0a0aed4ec 65 #define DMAREQ_I2C0_TXBL ((20 << 16) + 1) /**< DMA channel select for I2C0_TXBL */
<> 150:02e0a0aed4ec 66 #define DMAREQ_I2C1_RXDATAV ((21 << 16) + 0) /**< DMA channel select for I2C1_RXDATAV */
<> 150:02e0a0aed4ec 67 #define DMAREQ_I2C1_TXBL ((21 << 16) + 1) /**< DMA channel select for I2C1_TXBL */
<> 150:02e0a0aed4ec 68 #define DMAREQ_TIMER0_UFOF ((24 << 16) + 0) /**< DMA channel select for TIMER0_UFOF */
<> 150:02e0a0aed4ec 69 #define DMAREQ_TIMER0_CC0 ((24 << 16) + 1) /**< DMA channel select for TIMER0_CC0 */
<> 150:02e0a0aed4ec 70 #define DMAREQ_TIMER0_CC1 ((24 << 16) + 2) /**< DMA channel select for TIMER0_CC1 */
<> 150:02e0a0aed4ec 71 #define DMAREQ_TIMER0_CC2 ((24 << 16) + 3) /**< DMA channel select for TIMER0_CC2 */
<> 150:02e0a0aed4ec 72 #define DMAREQ_TIMER1_UFOF ((25 << 16) + 0) /**< DMA channel select for TIMER1_UFOF */
<> 150:02e0a0aed4ec 73 #define DMAREQ_TIMER1_CC0 ((25 << 16) + 1) /**< DMA channel select for TIMER1_CC0 */
<> 150:02e0a0aed4ec 74 #define DMAREQ_TIMER1_CC1 ((25 << 16) + 2) /**< DMA channel select for TIMER1_CC1 */
<> 150:02e0a0aed4ec 75 #define DMAREQ_TIMER1_CC2 ((25 << 16) + 3) /**< DMA channel select for TIMER1_CC2 */
<> 150:02e0a0aed4ec 76 #define DMAREQ_TIMER2_UFOF ((26 << 16) + 0) /**< DMA channel select for TIMER2_UFOF */
<> 150:02e0a0aed4ec 77 #define DMAREQ_TIMER2_CC0 ((26 << 16) + 1) /**< DMA channel select for TIMER2_CC0 */
<> 150:02e0a0aed4ec 78 #define DMAREQ_TIMER2_CC1 ((26 << 16) + 2) /**< DMA channel select for TIMER2_CC1 */
<> 150:02e0a0aed4ec 79 #define DMAREQ_TIMER2_CC2 ((26 << 16) + 3) /**< DMA channel select for TIMER2_CC2 */
<> 150:02e0a0aed4ec 80 #define DMAREQ_TIMER3_UFOF ((27 << 16) + 0) /**< DMA channel select for TIMER3_UFOF */
<> 150:02e0a0aed4ec 81 #define DMAREQ_TIMER3_CC0 ((27 << 16) + 1) /**< DMA channel select for TIMER3_CC0 */
<> 150:02e0a0aed4ec 82 #define DMAREQ_TIMER3_CC1 ((27 << 16) + 2) /**< DMA channel select for TIMER3_CC1 */
<> 150:02e0a0aed4ec 83 #define DMAREQ_TIMER3_CC2 ((27 << 16) + 3) /**< DMA channel select for TIMER3_CC2 */
<> 150:02e0a0aed4ec 84 #define DMAREQ_UART0_RXDATAV ((44 << 16) + 0) /**< DMA channel select for UART0_RXDATAV */
<> 150:02e0a0aed4ec 85 #define DMAREQ_UART0_TXBL ((44 << 16) + 1) /**< DMA channel select for UART0_TXBL */
<> 150:02e0a0aed4ec 86 #define DMAREQ_UART0_TXEMPTY ((44 << 16) + 2) /**< DMA channel select for UART0_TXEMPTY */
<> 150:02e0a0aed4ec 87 #define DMAREQ_UART1_RXDATAV ((45 << 16) + 0) /**< DMA channel select for UART1_RXDATAV */
<> 150:02e0a0aed4ec 88 #define DMAREQ_UART1_TXBL ((45 << 16) + 1) /**< DMA channel select for UART1_TXBL */
<> 150:02e0a0aed4ec 89 #define DMAREQ_UART1_TXEMPTY ((45 << 16) + 2) /**< DMA channel select for UART1_TXEMPTY */
<> 150:02e0a0aed4ec 90 #define DMAREQ_MSC_WDATA ((48 << 16) + 0) /**< DMA channel select for MSC_WDATA */
<> 150:02e0a0aed4ec 91 #define DMAREQ_AES_DATAWR ((49 << 16) + 0) /**< DMA channel select for AES_DATAWR */
<> 150:02e0a0aed4ec 92 #define DMAREQ_AES_XORDATAWR ((49 << 16) + 1) /**< DMA channel select for AES_XORDATAWR */
<> 150:02e0a0aed4ec 93 #define DMAREQ_AES_DATARD ((49 << 16) + 2) /**< DMA channel select for AES_DATARD */
<> 150:02e0a0aed4ec 94 #define DMAREQ_AES_KEYWR ((49 << 16) + 3) /**< DMA channel select for AES_KEYWR */
<> 150:02e0a0aed4ec 95 #define DMAREQ_LESENSE_BUFDATAV ((50 << 16) + 0) /**< DMA channel select for LESENSE_BUFDATAV */
<> 150:02e0a0aed4ec 96 #define DMAREQ_EBI_PXL0EMPTY ((51 << 16) + 0) /**< DMA channel select for EBI_PXL0EMPTY */
<> 150:02e0a0aed4ec 97 #define DMAREQ_EBI_PXL1EMPTY ((51 << 16) + 1) /**< DMA channel select for EBI_PXL1EMPTY */
<> 150:02e0a0aed4ec 98 #define DMAREQ_EBI_PXLFULL ((51 << 16) + 2) /**< DMA channel select for EBI_PXLFULL */
<> 150:02e0a0aed4ec 99 #define DMAREQ_EBI_DDEMPTY ((51 << 16) + 3) /**< DMA channel select for EBI_DDEMPTY */
<> 150:02e0a0aed4ec 100
<> 150:02e0a0aed4ec 101 /** @} End of group EFM32WG_DMAREQ */
<> 150:02e0a0aed4ec 102 /** @} End of group Parts */
<> 150:02e0a0aed4ec 103