Fawwaz Nadzmy / mbed-STM

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_dmactrl.h@153:9398a535854b, 2016-12-22 (annotated)

Committer:
fwndz
Date:
Thu Dec 22 05:12:40 2016 +0000
Revision:
153:9398a535854b
Parent:
150:02e0a0aed4ec 
device target maximize

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 150:02e0a0aed4ec 1 /**************************************************************************//**
<> 150:02e0a0aed4ec 2 * @file efm32wg_dmactrl.h
<> 150:02e0a0aed4ec 3 * @brief EFM32WG_DMACTRL register and bit field definitions
<> 150:02e0a0aed4ec 4 * @version 5.0.0
<> 150:02e0a0aed4ec 5 ******************************************************************************
<> 150:02e0a0aed4ec 6 * @section License
<> 150:02e0a0aed4ec 7 * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 150:02e0a0aed4ec 8 ******************************************************************************
<> 150:02e0a0aed4ec 9 *
<> 150:02e0a0aed4ec 10 * Permission is granted to anyone to use this software for any purpose,
<> 150:02e0a0aed4ec 11 * including commercial applications, and to alter it and redistribute it
<> 150:02e0a0aed4ec 12 * freely, subject to the following restrictions:
<> 150:02e0a0aed4ec 13 *
<> 150:02e0a0aed4ec 14 * 1. The origin of this software must not be misrepresented; you must not
<> 150:02e0a0aed4ec 15 * claim that you wrote the original software.@n
<> 150:02e0a0aed4ec 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 150:02e0a0aed4ec 17 * misrepresented as being the original software.@n
<> 150:02e0a0aed4ec 18 * 3. This notice may not be removed or altered from any source distribution.
<> 150:02e0a0aed4ec 19 *
<> 150:02e0a0aed4ec 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 150:02e0a0aed4ec 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 150:02e0a0aed4ec 22 * providing the Software "AS IS", with no express or implied warranties of any
<> 150:02e0a0aed4ec 23 * kind, including, but not limited to, any implied warranties of
<> 150:02e0a0aed4ec 24 * merchantability or fitness for any particular purpose or warranties against
<> 150:02e0a0aed4ec 25 * infringement of any proprietary rights of a third party.
<> 150:02e0a0aed4ec 26 *
<> 150:02e0a0aed4ec 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 150:02e0a0aed4ec 28 * incidental, or special damages, or any other relief, or for any claim by
<> 150:02e0a0aed4ec 29 * any third party, arising from your use of this Software.
<> 150:02e0a0aed4ec 30 *
<> 150:02e0a0aed4ec 31 *****************************************************************************/
<> 150:02e0a0aed4ec 32 /**************************************************************************//**
<> 150:02e0a0aed4ec 33 * @addtogroup Parts
<> 150:02e0a0aed4ec 34 * @{
<> 150:02e0a0aed4ec 35 ******************************************************************************/
<> 150:02e0a0aed4ec 36
<> 150:02e0a0aed4ec 37 /**************************************************************************//**
<> 150:02e0a0aed4ec 38 * @defgroup EFM32WG_DMACTRL_BitFields
<> 150:02e0a0aed4ec 39 * @{
<> 150:02e0a0aed4ec 40 *****************************************************************************/
<> 150:02e0a0aed4ec 41 #define _DMA_CTRL_DST_INC_MASK 0xC0000000UL /**< Data increment for destination, bit mask */
<> 150:02e0a0aed4ec 42 #define _DMA_CTRL_DST_INC_SHIFT 30 /**< Data increment for destination, shift value */
<> 150:02e0a0aed4ec 43 #define _DMA_CTRL_DST_INC_BYTE 0x00 /**< Byte/8-bit increment */
<> 150:02e0a0aed4ec 44 #define _DMA_CTRL_DST_INC_HALFWORD 0x01 /**< Half word/16-bit increment */
<> 150:02e0a0aed4ec 45 #define _DMA_CTRL_DST_INC_WORD 0x02 /**< Word/32-bit increment */
<> 150:02e0a0aed4ec 46 #define _DMA_CTRL_DST_INC_NONE 0x03 /**< No increment */
<> 150:02e0a0aed4ec 47 #define DMA_CTRL_DST_INC_BYTE 0x00000000UL /**< Byte/8-bit increment */
<> 150:02e0a0aed4ec 48 #define DMA_CTRL_DST_INC_HALFWORD 0x40000000UL /**< Half word/16-bit increment */
<> 150:02e0a0aed4ec 49 #define DMA_CTRL_DST_INC_WORD 0x80000000UL /**< Word/32-bit increment */
<> 150:02e0a0aed4ec 50 #define DMA_CTRL_DST_INC_NONE 0xC0000000UL /**< No increment */
<> 150:02e0a0aed4ec 51 #define _DMA_CTRL_DST_SIZE_MASK 0x30000000UL /**< Data size for destination - MUST be the same as source, bit mask */
<> 150:02e0a0aed4ec 52 #define _DMA_CTRL_DST_SIZE_SHIFT 28 /**< Data size for destination - MUST be the same as source, shift value */
<> 150:02e0a0aed4ec 53 #define _DMA_CTRL_DST_SIZE_BYTE 0x00 /**< Byte/8-bit data size */
<> 150:02e0a0aed4ec 54 #define _DMA_CTRL_DST_SIZE_HALFWORD 0x01 /**< Half word/16-bit data size */
<> 150:02e0a0aed4ec 55 #define _DMA_CTRL_DST_SIZE_WORD 0x02 /**< Word/32-bit data size */
<> 150:02e0a0aed4ec 56 #define _DMA_CTRL_DST_SIZE_RSVD 0x03 /**< Reserved */
<> 150:02e0a0aed4ec 57 #define DMA_CTRL_DST_SIZE_BYTE 0x00000000UL /**< Byte/8-bit data size */
<> 150:02e0a0aed4ec 58 #define DMA_CTRL_DST_SIZE_HALFWORD 0x10000000UL /**< Half word/16-bit data size */
<> 150:02e0a0aed4ec 59 #define DMA_CTRL_DST_SIZE_WORD 0x20000000UL /**< Word/32-bit data size */
<> 150:02e0a0aed4ec 60 #define DMA_CTRL_DST_SIZE_RSVD 0x30000000UL /**< Reserved - do not use */
<> 150:02e0a0aed4ec 61 #define _DMA_CTRL_SRC_INC_MASK 0x0C000000UL /**< Data increment for source, bit mask */
<> 150:02e0a0aed4ec 62 #define _DMA_CTRL_SRC_INC_SHIFT 26 /**< Data increment for source, shift value */
<> 150:02e0a0aed4ec 63 #define _DMA_CTRL_SRC_INC_BYTE 0x00 /**< Byte/8-bit increment */
<> 150:02e0a0aed4ec 64 #define _DMA_CTRL_SRC_INC_HALFWORD 0x01 /**< Half word/16-bit increment */
<> 150:02e0a0aed4ec 65 #define _DMA_CTRL_SRC_INC_WORD 0x02 /**< Word/32-bit increment */
<> 150:02e0a0aed4ec 66 #define _DMA_CTRL_SRC_INC_NONE 0x03 /**< No increment */
<> 150:02e0a0aed4ec 67 #define DMA_CTRL_SRC_INC_BYTE 0x00000000UL /**< Byte/8-bit increment */
<> 150:02e0a0aed4ec 68 #define DMA_CTRL_SRC_INC_HALFWORD 0x04000000UL /**< Half word/16-bit increment */
<> 150:02e0a0aed4ec 69 #define DMA_CTRL_SRC_INC_WORD 0x08000000UL /**< Word/32-bit increment */
<> 150:02e0a0aed4ec 70 #define DMA_CTRL_SRC_INC_NONE 0x0C000000UL /**< No increment */
<> 150:02e0a0aed4ec 71 #define _DMA_CTRL_SRC_SIZE_MASK 0x03000000UL /**< Data size for source - MUST be the same as destination, bit mask */
<> 150:02e0a0aed4ec 72 #define _DMA_CTRL_SRC_SIZE_SHIFT 24 /**< Data size for source - MUST be the same as destination, shift value */
<> 150:02e0a0aed4ec 73 #define _DMA_CTRL_SRC_SIZE_BYTE 0x00 /**< Byte/8-bit data size */
<> 150:02e0a0aed4ec 74 #define _DMA_CTRL_SRC_SIZE_HALFWORD 0x01 /**< Half word/16-bit data size */
<> 150:02e0a0aed4ec 75 #define _DMA_CTRL_SRC_SIZE_WORD 0x02 /**< Word/32-bit data size */
<> 150:02e0a0aed4ec 76 #define _DMA_CTRL_SRC_SIZE_RSVD 0x03 /**< Reserved */
<> 150:02e0a0aed4ec 77 #define DMA_CTRL_SRC_SIZE_BYTE 0x00000000UL /**< Byte/8-bit data size */
<> 150:02e0a0aed4ec 78 #define DMA_CTRL_SRC_SIZE_HALFWORD 0x01000000UL /**< Half word/16-bit data size */
<> 150:02e0a0aed4ec 79 #define DMA_CTRL_SRC_SIZE_WORD 0x02000000UL /**< Word/32-bit data size */
<> 150:02e0a0aed4ec 80 #define DMA_CTRL_SRC_SIZE_RSVD 0x03000000UL /**< Reserved - do not use */
<> 150:02e0a0aed4ec 81 #define _DMA_CTRL_DST_PROT_CTRL_MASK 0x00E00000UL /**< Protection flag for destination, bit mask */
<> 150:02e0a0aed4ec 82 #define _DMA_CTRL_DST_PROT_CTRL_SHIFT 21 /**< Protection flag for destination, shift value */
<> 150:02e0a0aed4ec 83 #define DMA_CTRL_DST_PROT_PRIVILEGED 0x00200000UL /**< Privileged mode for destination */
<> 150:02e0a0aed4ec 84 #define DMA_CTRL_DST_PROT_NON_PRIVILEGED 0x00000000UL /**< Non-privileged mode for destination */
<> 150:02e0a0aed4ec 85 #define _DMA_CTRL_SRC_PROT_CTRL_MASK 0x001C0000UL /**< Protection flag for source, bit mask */
<> 150:02e0a0aed4ec 86 #define _DMA_CTRL_SRC_PROT_CTRL_SHIFT 18 /**< Protection flag for source, shift value */
<> 150:02e0a0aed4ec 87 #define DMA_CTRL_SRC_PROT_PRIVILEGED 0x00040000UL /**< Privileged mode for destination */
<> 150:02e0a0aed4ec 88 #define DMA_CTRL_SRC_PROT_NON_PRIVILEGED 0x00000000UL /**< Non-privileged mode for destination */
<> 150:02e0a0aed4ec 89 #define _DMA_CTRL_PROT_NON_PRIVILEGED 0x00 /**< Protection bits to indicate non-privileged access */
<> 150:02e0a0aed4ec 90 #define _DMA_CTRL_PROT_PRIVILEGED 0x01 /**< Protection bits to indicate privileged access */
<> 150:02e0a0aed4ec 91 #define _DMA_CTRL_R_POWER_MASK 0x0003C000UL /**< DMA arbitration mask */
<> 150:02e0a0aed4ec 92 #define _DMA_CTRL_R_POWER_SHIFT 14 /**< Number of DMA cycles before controller does new arbitration in 2^R */
<> 150:02e0a0aed4ec 93 #define _DMA_CTRL_R_POWER_1 0x00 /**< Arbitrate after each transfer */
<> 150:02e0a0aed4ec 94 #define _DMA_CTRL_R_POWER_2 0x01 /**< Arbitrate after every 2 transfers */
<> 150:02e0a0aed4ec 95 #define _DMA_CTRL_R_POWER_4 0x02 /**< Arbitrate after every 4 transfers */
<> 150:02e0a0aed4ec 96 #define _DMA_CTRL_R_POWER_8 0x03 /**< Arbitrate after every 8 transfers */
<> 150:02e0a0aed4ec 97 #define _DMA_CTRL_R_POWER_16 0x04 /**< Arbitrate after every 16 transfers */
<> 150:02e0a0aed4ec 98 #define _DMA_CTRL_R_POWER_32 0x05 /**< Arbitrate after every 32 transfers */
<> 150:02e0a0aed4ec 99 #define _DMA_CTRL_R_POWER_64 0x06 /**< Arbitrate after every 64 transfers */
<> 150:02e0a0aed4ec 100 #define _DMA_CTRL_R_POWER_128 0x07 /**< Arbitrate after every 128 transfers */
<> 150:02e0a0aed4ec 101 #define _DMA_CTRL_R_POWER_256 0x08 /**< Arbitrate after every 256 transfers */
<> 150:02e0a0aed4ec 102 #define _DMA_CTRL_R_POWER_512 0x09 /**< Arbitrate after every 512 transfers */
<> 150:02e0a0aed4ec 103 #define _DMA_CTRL_R_POWER_1024 0x0a /**< Arbitrate after every 1024 transfers */
<> 150:02e0a0aed4ec 104 #define DMA_CTRL_R_POWER_1 0x00000000UL /**< Arbitrate after each transfer */
<> 150:02e0a0aed4ec 105 #define DMA_CTRL_R_POWER_2 0x00004000UL /**< Arbitrate after every 2 transfers */
<> 150:02e0a0aed4ec 106 #define DMA_CTRL_R_POWER_4 0x00008000UL /**< Arbitrate after every 4 transfers */
<> 150:02e0a0aed4ec 107 #define DMA_CTRL_R_POWER_8 0x0000c000UL /**< Arbitrate after every 8 transfers */
<> 150:02e0a0aed4ec 108 #define DMA_CTRL_R_POWER_16 0x00010000UL /**< Arbitrate after every 16 transfers */
<> 150:02e0a0aed4ec 109 #define DMA_CTRL_R_POWER_32 0x00014000UL /**< Arbitrate after every 32 transfers */
<> 150:02e0a0aed4ec 110 #define DMA_CTRL_R_POWER_64 0x00018000UL /**< Arbitrate after every 64 transfers */
<> 150:02e0a0aed4ec 111 #define DMA_CTRL_R_POWER_128 0x0001c000UL /**< Arbitrate after every 128 transfers */
<> 150:02e0a0aed4ec 112 #define DMA_CTRL_R_POWER_256 0x00020000UL /**< Arbitrate after every 256 transfers */
<> 150:02e0a0aed4ec 113 #define DMA_CTRL_R_POWER_512 0x00024000UL /**< Arbitrate after every 512 transfers */
<> 150:02e0a0aed4ec 114 #define DMA_CTRL_R_POWER_1024 0x00028000UL /**< Arbitrate after every 1024 transfers */
<> 150:02e0a0aed4ec 115 #define _DMA_CTRL_N_MINUS_1_MASK 0x00003FF0UL /**< Number of DMA transfers minus 1, bit mask. See PL230 documentation */
<> 150:02e0a0aed4ec 116 #define _DMA_CTRL_N_MINUS_1_SHIFT 4 /**< Number of DMA transfers minus 1, shift mask. See PL230 documentation */
<> 150:02e0a0aed4ec 117 #define _DMA_CTRL_NEXT_USEBURST_MASK 0x00000008UL /**< DMA useburst_set[C] is 1 when using scatter-gather DMA and using alternate data */
<> 150:02e0a0aed4ec 118 #define _DMA_CTRL_NEXT_USEBURST_SHIFT 3 /**< DMA useburst shift */
<> 150:02e0a0aed4ec 119 #define _DMA_CTRL_CYCLE_CTRL_MASK 0x00000007UL /**< DMA Cycle control bit mask - basic/auto/ping-poing/scath-gath */
<> 150:02e0a0aed4ec 120 #define _DMA_CTRL_CYCLE_CTRL_SHIFT 0 /**< DMA Cycle control bit shift */
<> 150:02e0a0aed4ec 121 #define _DMA_CTRL_CYCLE_CTRL_INVALID 0x00 /**< Invalid cycle type */
<> 150:02e0a0aed4ec 122 #define _DMA_CTRL_CYCLE_CTRL_BASIC 0x01 /**< Basic cycle type */
<> 150:02e0a0aed4ec 123 #define _DMA_CTRL_CYCLE_CTRL_AUTO 0x02 /**< Auto cycle type */
<> 150:02e0a0aed4ec 124 #define _DMA_CTRL_CYCLE_CTRL_PINGPONG 0x03 /**< PingPong cycle type */
<> 150:02e0a0aed4ec 125 #define _DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER 0x04 /**< Memory scatter gather cycle type */
<> 150:02e0a0aed4ec 126 #define _DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER_ALT 0x05 /**< Memory scatter gather using alternate structure */
<> 150:02e0a0aed4ec 127 #define _DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER 0x06 /**< Peripheral scatter gather cycle type */
<> 150:02e0a0aed4ec 128 #define _DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER_ALT 0x07 /**< Peripheral scatter gather cycle type using alternate structure */
<> 150:02e0a0aed4ec 129 #define DMA_CTRL_CYCLE_CTRL_INVALID 0x00000000UL /**< Invalid cycle type */
<> 150:02e0a0aed4ec 130 #define DMA_CTRL_CYCLE_CTRL_BASIC 0x00000001UL /**< Basic cycle type */
<> 150:02e0a0aed4ec 131 #define DMA_CTRL_CYCLE_CTRL_AUTO 0x00000002UL /**< Auto cycle type */
<> 150:02e0a0aed4ec 132 #define DMA_CTRL_CYCLE_CTRL_PINGPONG 0x00000003UL /**< PingPong cycle type */
<> 150:02e0a0aed4ec 133 #define DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER 0x000000004UL /**< Memory scatter gather cycle type */
<> 150:02e0a0aed4ec 134 #define DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER_ALT 0x000000005UL /**< Memory scatter gather using alternate structure */
<> 150:02e0a0aed4ec 135 #define DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER 0x000000006UL /**< Peripheral scatter gather cycle type */
<> 150:02e0a0aed4ec 136 #define DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER_ALT 0x000000007UL /**< Peripheral scatter gather cycle type using alternate structure */
<> 150:02e0a0aed4ec 137
<> 150:02e0a0aed4ec 138 /** @} End of group EFM32WG_DMA */
<> 150:02e0a0aed4ec 139 /** @} End of group Parts */
<> 150:02e0a0aed4ec 140