Fawwaz Nadzmy / mbed-STM

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_dma.h@153:9398a535854b, 2016-12-22 (annotated)

Committer:
fwndz
Date:
Thu Dec 22 05:12:40 2016 +0000
Revision:
153:9398a535854b
Parent:
150:02e0a0aed4ec 
device target maximize

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 150:02e0a0aed4ec 1 /**************************************************************************//**
<> 150:02e0a0aed4ec 2 * @file efm32wg_dma.h
<> 150:02e0a0aed4ec 3 * @brief EFM32WG_DMA register and bit field definitions
<> 150:02e0a0aed4ec 4 * @version 5.0.0
<> 150:02e0a0aed4ec 5 ******************************************************************************
<> 150:02e0a0aed4ec 6 * @section License
<> 150:02e0a0aed4ec 7 * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 150:02e0a0aed4ec 8 ******************************************************************************
<> 150:02e0a0aed4ec 9 *
<> 150:02e0a0aed4ec 10 * Permission is granted to anyone to use this software for any purpose,
<> 150:02e0a0aed4ec 11 * including commercial applications, and to alter it and redistribute it
<> 150:02e0a0aed4ec 12 * freely, subject to the following restrictions:
<> 150:02e0a0aed4ec 13 *
<> 150:02e0a0aed4ec 14 * 1. The origin of this software must not be misrepresented; you must not
<> 150:02e0a0aed4ec 15 * claim that you wrote the original software.@n
<> 150:02e0a0aed4ec 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 150:02e0a0aed4ec 17 * misrepresented as being the original software.@n
<> 150:02e0a0aed4ec 18 * 3. This notice may not be removed or altered from any source distribution.
<> 150:02e0a0aed4ec 19 *
<> 150:02e0a0aed4ec 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 150:02e0a0aed4ec 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 150:02e0a0aed4ec 22 * providing the Software "AS IS", with no express or implied warranties of any
<> 150:02e0a0aed4ec 23 * kind, including, but not limited to, any implied warranties of
<> 150:02e0a0aed4ec 24 * merchantability or fitness for any particular purpose or warranties against
<> 150:02e0a0aed4ec 25 * infringement of any proprietary rights of a third party.
<> 150:02e0a0aed4ec 26 *
<> 150:02e0a0aed4ec 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 150:02e0a0aed4ec 28 * incidental, or special damages, or any other relief, or for any claim by
<> 150:02e0a0aed4ec 29 * any third party, arising from your use of this Software.
<> 150:02e0a0aed4ec 30 *
<> 150:02e0a0aed4ec 31 *****************************************************************************/
<> 150:02e0a0aed4ec 32 /**************************************************************************//**
<> 150:02e0a0aed4ec 33 * @addtogroup Parts
<> 150:02e0a0aed4ec 34 * @{
<> 150:02e0a0aed4ec 35 ******************************************************************************/
<> 150:02e0a0aed4ec 36 /**************************************************************************//**
<> 150:02e0a0aed4ec 37 * @defgroup EFM32WG_DMA
<> 150:02e0a0aed4ec 38 * @{
<> 150:02e0a0aed4ec 39 * @brief EFM32WG_DMA Register Declaration
<> 150:02e0a0aed4ec 40 *****************************************************************************/
<> 150:02e0a0aed4ec 41 typedef struct
<> 150:02e0a0aed4ec 42 {
<> 150:02e0a0aed4ec 43 __IM uint32_t STATUS; /**< DMA Status Registers */
<> 150:02e0a0aed4ec 44 __OM uint32_t CONFIG; /**< DMA Configuration Register */
<> 150:02e0a0aed4ec 45 __IOM uint32_t CTRLBASE; /**< Channel Control Data Base Pointer Register */
<> 150:02e0a0aed4ec 46 __IM uint32_t ALTCTRLBASE; /**< Channel Alternate Control Data Base Pointer Register */
<> 150:02e0a0aed4ec 47 __IM uint32_t CHWAITSTATUS; /**< Channel Wait on Request Status Register */
<> 150:02e0a0aed4ec 48 __OM uint32_t CHSWREQ; /**< Channel Software Request Register */
<> 150:02e0a0aed4ec 49 __IOM uint32_t CHUSEBURSTS; /**< Channel Useburst Set Register */
<> 150:02e0a0aed4ec 50 __OM uint32_t CHUSEBURSTC; /**< Channel Useburst Clear Register */
<> 150:02e0a0aed4ec 51 __IOM uint32_t CHREQMASKS; /**< Channel Request Mask Set Register */
<> 150:02e0a0aed4ec 52 __OM uint32_t CHREQMASKC; /**< Channel Request Mask Clear Register */
<> 150:02e0a0aed4ec 53 __IOM uint32_t CHENS; /**< Channel Enable Set Register */
<> 150:02e0a0aed4ec 54 __OM uint32_t CHENC; /**< Channel Enable Clear Register */
<> 150:02e0a0aed4ec 55 __IOM uint32_t CHALTS; /**< Channel Alternate Set Register */
<> 150:02e0a0aed4ec 56 __OM uint32_t CHALTC; /**< Channel Alternate Clear Register */
<> 150:02e0a0aed4ec 57 __IOM uint32_t CHPRIS; /**< Channel Priority Set Register */
<> 150:02e0a0aed4ec 58 __OM uint32_t CHPRIC; /**< Channel Priority Clear Register */
<> 150:02e0a0aed4ec 59 uint32_t RESERVED0[3]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 60 __IOM uint32_t ERRORC; /**< Bus Error Clear Register */
<> 150:02e0a0aed4ec 61
<> 150:02e0a0aed4ec 62 uint32_t RESERVED1[880]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 63 __IM uint32_t CHREQSTATUS; /**< Channel Request Status */
<> 150:02e0a0aed4ec 64 uint32_t RESERVED2[1]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 65 __IM uint32_t CHSREQSTATUS; /**< Channel Single Request Status */
<> 150:02e0a0aed4ec 66
<> 150:02e0a0aed4ec 67 uint32_t RESERVED3[121]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 68 __IM uint32_t IF; /**< Interrupt Flag Register */
<> 150:02e0a0aed4ec 69 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
<> 150:02e0a0aed4ec 70 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
<> 150:02e0a0aed4ec 71 __IOM uint32_t IEN; /**< Interrupt Enable register */
<> 150:02e0a0aed4ec 72 __IOM uint32_t CTRL; /**< DMA Control Register */
<> 150:02e0a0aed4ec 73 __IOM uint32_t RDS; /**< DMA Retain Descriptor State */
<> 150:02e0a0aed4ec 74
<> 150:02e0a0aed4ec 75 uint32_t RESERVED4[2]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 76 __IOM uint32_t LOOP0; /**< Channel 0 Loop Register */
<> 150:02e0a0aed4ec 77 __IOM uint32_t LOOP1; /**< Channel 1 Loop Register */
<> 150:02e0a0aed4ec 78 uint32_t RESERVED5[14]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 79 __IOM uint32_t RECT0; /**< Channel 0 Rectangle Register */
<> 150:02e0a0aed4ec 80
<> 150:02e0a0aed4ec 81 uint32_t RESERVED6[39]; /**< Reserved registers */
<> 150:02e0a0aed4ec 82 DMA_CH_TypeDef CH[12]; /**< Channel registers */
<> 150:02e0a0aed4ec 83 } DMA_TypeDef; /** @} */
<> 150:02e0a0aed4ec 84
<> 150:02e0a0aed4ec 85 /**************************************************************************//**
<> 150:02e0a0aed4ec 86 * @defgroup EFM32WG_DMA_BitFields
<> 150:02e0a0aed4ec 87 * @{
<> 150:02e0a0aed4ec 88 *****************************************************************************/
<> 150:02e0a0aed4ec 89
<> 150:02e0a0aed4ec 90 /* Bit fields for DMA STATUS */
<> 150:02e0a0aed4ec 91 #define _DMA_STATUS_RESETVALUE 0x100B0000UL /**< Default value for DMA_STATUS */
<> 150:02e0a0aed4ec 92 #define _DMA_STATUS_MASK 0x001F00F1UL /**< Mask for DMA_STATUS */
<> 150:02e0a0aed4ec 93 #define DMA_STATUS_EN (0x1UL << 0) /**< DMA Enable Status */
<> 150:02e0a0aed4ec 94 #define _DMA_STATUS_EN_SHIFT 0 /**< Shift value for DMA_EN */
<> 150:02e0a0aed4ec 95 #define _DMA_STATUS_EN_MASK 0x1UL /**< Bit mask for DMA_EN */
<> 150:02e0a0aed4ec 96 #define _DMA_STATUS_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_STATUS */
<> 150:02e0a0aed4ec 97 #define DMA_STATUS_EN_DEFAULT (_DMA_STATUS_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_STATUS */
<> 150:02e0a0aed4ec 98 #define _DMA_STATUS_STATE_SHIFT 4 /**< Shift value for DMA_STATE */
<> 150:02e0a0aed4ec 99 #define _DMA_STATUS_STATE_MASK 0xF0UL /**< Bit mask for DMA_STATE */
<> 150:02e0a0aed4ec 100 #define _DMA_STATUS_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_STATUS */
<> 150:02e0a0aed4ec 101 #define _DMA_STATUS_STATE_IDLE 0x00000000UL /**< Mode IDLE for DMA_STATUS */
<> 150:02e0a0aed4ec 102 #define _DMA_STATUS_STATE_RDCHCTRLDATA 0x00000001UL /**< Mode RDCHCTRLDATA for DMA_STATUS */
<> 150:02e0a0aed4ec 103 #define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL /**< Mode RDSRCENDPTR for DMA_STATUS */
<> 150:02e0a0aed4ec 104 #define _DMA_STATUS_STATE_RDDSTENDPTR 0x00000003UL /**< Mode RDDSTENDPTR for DMA_STATUS */
<> 150:02e0a0aed4ec 105 #define _DMA_STATUS_STATE_RDSRCDATA 0x00000004UL /**< Mode RDSRCDATA for DMA_STATUS */
<> 150:02e0a0aed4ec 106 #define _DMA_STATUS_STATE_WRDSTDATA 0x00000005UL /**< Mode WRDSTDATA for DMA_STATUS */
<> 150:02e0a0aed4ec 107 #define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL /**< Mode WAITREQCLR for DMA_STATUS */
<> 150:02e0a0aed4ec 108 #define _DMA_STATUS_STATE_WRCHCTRLDATA 0x00000007UL /**< Mode WRCHCTRLDATA for DMA_STATUS */
<> 150:02e0a0aed4ec 109 #define _DMA_STATUS_STATE_STALLED 0x00000008UL /**< Mode STALLED for DMA_STATUS */
<> 150:02e0a0aed4ec 110 #define _DMA_STATUS_STATE_DONE 0x00000009UL /**< Mode DONE for DMA_STATUS */
<> 150:02e0a0aed4ec 111 #define _DMA_STATUS_STATE_PERSCATTRANS 0x0000000AUL /**< Mode PERSCATTRANS for DMA_STATUS */
<> 150:02e0a0aed4ec 112 #define DMA_STATUS_STATE_DEFAULT (_DMA_STATUS_STATE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_STATUS */
<> 150:02e0a0aed4ec 113 #define DMA_STATUS_STATE_IDLE (_DMA_STATUS_STATE_IDLE << 4) /**< Shifted mode IDLE for DMA_STATUS */
<> 150:02e0a0aed4ec 114 #define DMA_STATUS_STATE_RDCHCTRLDATA (_DMA_STATUS_STATE_RDCHCTRLDATA << 4) /**< Shifted mode RDCHCTRLDATA for DMA_STATUS */
<> 150:02e0a0aed4ec 115 #define DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4) /**< Shifted mode RDSRCENDPTR for DMA_STATUS */
<> 150:02e0a0aed4ec 116 #define DMA_STATUS_STATE_RDDSTENDPTR (_DMA_STATUS_STATE_RDDSTENDPTR << 4) /**< Shifted mode RDDSTENDPTR for DMA_STATUS */
<> 150:02e0a0aed4ec 117 #define DMA_STATUS_STATE_RDSRCDATA (_DMA_STATUS_STATE_RDSRCDATA << 4) /**< Shifted mode RDSRCDATA for DMA_STATUS */
<> 150:02e0a0aed4ec 118 #define DMA_STATUS_STATE_WRDSTDATA (_DMA_STATUS_STATE_WRDSTDATA << 4) /**< Shifted mode WRDSTDATA for DMA_STATUS */
<> 150:02e0a0aed4ec 119 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< Shifted mode WAITREQCLR for DMA_STATUS */
<> 150:02e0a0aed4ec 120 #define DMA_STATUS_STATE_WRCHCTRLDATA (_DMA_STATUS_STATE_WRCHCTRLDATA << 4) /**< Shifted mode WRCHCTRLDATA for DMA_STATUS */
<> 150:02e0a0aed4ec 121 #define DMA_STATUS_STATE_STALLED (_DMA_STATUS_STATE_STALLED << 4) /**< Shifted mode STALLED for DMA_STATUS */
<> 150:02e0a0aed4ec 122 #define DMA_STATUS_STATE_DONE (_DMA_STATUS_STATE_DONE << 4) /**< Shifted mode DONE for DMA_STATUS */
<> 150:02e0a0aed4ec 123 #define DMA_STATUS_STATE_PERSCATTRANS (_DMA_STATUS_STATE_PERSCATTRANS << 4) /**< Shifted mode PERSCATTRANS for DMA_STATUS */
<> 150:02e0a0aed4ec 124 #define _DMA_STATUS_CHNUM_SHIFT 16 /**< Shift value for DMA_CHNUM */
<> 150:02e0a0aed4ec 125 #define _DMA_STATUS_CHNUM_MASK 0x1F0000UL /**< Bit mask for DMA_CHNUM */
<> 150:02e0a0aed4ec 126 #define _DMA_STATUS_CHNUM_DEFAULT 0x0000000BUL /**< Mode DEFAULT for DMA_STATUS */
<> 150:02e0a0aed4ec 127 #define DMA_STATUS_CHNUM_DEFAULT (_DMA_STATUS_CHNUM_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_STATUS */
<> 150:02e0a0aed4ec 128
<> 150:02e0a0aed4ec 129 /* Bit fields for DMA CONFIG */
<> 150:02e0a0aed4ec 130 #define _DMA_CONFIG_RESETVALUE 0x00000000UL /**< Default value for DMA_CONFIG */
<> 150:02e0a0aed4ec 131 #define _DMA_CONFIG_MASK 0x00000021UL /**< Mask for DMA_CONFIG */
<> 150:02e0a0aed4ec 132 #define DMA_CONFIG_EN (0x1UL << 0) /**< Enable DMA */
<> 150:02e0a0aed4ec 133 #define _DMA_CONFIG_EN_SHIFT 0 /**< Shift value for DMA_EN */
<> 150:02e0a0aed4ec 134 #define _DMA_CONFIG_EN_MASK 0x1UL /**< Bit mask for DMA_EN */
<> 150:02e0a0aed4ec 135 #define _DMA_CONFIG_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CONFIG */
<> 150:02e0a0aed4ec 136 #define DMA_CONFIG_EN_DEFAULT (_DMA_CONFIG_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CONFIG */
<> 150:02e0a0aed4ec 137 #define DMA_CONFIG_CHPROT (0x1UL << 5) /**< Channel Protection Control */
<> 150:02e0a0aed4ec 138 #define _DMA_CONFIG_CHPROT_SHIFT 5 /**< Shift value for DMA_CHPROT */
<> 150:02e0a0aed4ec 139 #define _DMA_CONFIG_CHPROT_MASK 0x20UL /**< Bit mask for DMA_CHPROT */
<> 150:02e0a0aed4ec 140 #define _DMA_CONFIG_CHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CONFIG */
<> 150:02e0a0aed4ec 141 #define DMA_CONFIG_CHPROT_DEFAULT (_DMA_CONFIG_CHPROT_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CONFIG */
<> 150:02e0a0aed4ec 142
<> 150:02e0a0aed4ec 143 /* Bit fields for DMA CTRLBASE */
<> 150:02e0a0aed4ec 144 #define _DMA_CTRLBASE_RESETVALUE 0x00000000UL /**< Default value for DMA_CTRLBASE */
<> 150:02e0a0aed4ec 145 #define _DMA_CTRLBASE_MASK 0xFFFFFFFFUL /**< Mask for DMA_CTRLBASE */
<> 150:02e0a0aed4ec 146 #define _DMA_CTRLBASE_CTRLBASE_SHIFT 0 /**< Shift value for DMA_CTRLBASE */
<> 150:02e0a0aed4ec 147 #define _DMA_CTRLBASE_CTRLBASE_MASK 0xFFFFFFFFUL /**< Bit mask for DMA_CTRLBASE */
<> 150:02e0a0aed4ec 148 #define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRLBASE */
<> 150:02e0a0aed4ec 149 #define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CTRLBASE */
<> 150:02e0a0aed4ec 150
<> 150:02e0a0aed4ec 151 /* Bit fields for DMA ALTCTRLBASE */
<> 150:02e0a0aed4ec 152 #define _DMA_ALTCTRLBASE_RESETVALUE 0x00000100UL /**< Default value for DMA_ALTCTRLBASE */
<> 150:02e0a0aed4ec 153 #define _DMA_ALTCTRLBASE_MASK 0xFFFFFFFFUL /**< Mask for DMA_ALTCTRLBASE */
<> 150:02e0a0aed4ec 154 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_SHIFT 0 /**< Shift value for DMA_ALTCTRLBASE */
<> 150:02e0a0aed4ec 155 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_MASK 0xFFFFFFFFUL /**< Bit mask for DMA_ALTCTRLBASE */
<> 150:02e0a0aed4ec 156 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT 0x00000100UL /**< Mode DEFAULT for DMA_ALTCTRLBASE */
<> 150:02e0a0aed4ec 157 #define DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT (_DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_ALTCTRLBASE */
<> 150:02e0a0aed4ec 158
<> 150:02e0a0aed4ec 159 /* Bit fields for DMA CHWAITSTATUS */
<> 150:02e0a0aed4ec 160 #define _DMA_CHWAITSTATUS_RESETVALUE 0x00000FFFUL /**< Default value for DMA_CHWAITSTATUS */
<> 150:02e0a0aed4ec 161 #define _DMA_CHWAITSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHWAITSTATUS */
<> 150:02e0a0aed4ec 162 #define DMA_CHWAITSTATUS_CH0WAITSTATUS (0x1UL << 0) /**< Channel 0 Wait on Request Status */
<> 150:02e0a0aed4ec 163 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_SHIFT 0 /**< Shift value for DMA_CH0WAITSTATUS */
<> 150:02e0a0aed4ec 164 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0WAITSTATUS */
<> 150:02e0a0aed4ec 165 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
<> 150:02e0a0aed4ec 166 #define DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
<> 150:02e0a0aed4ec 167 #define DMA_CHWAITSTATUS_CH1WAITSTATUS (0x1UL << 1) /**< Channel 1 Wait on Request Status */
<> 150:02e0a0aed4ec 168 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_SHIFT 1 /**< Shift value for DMA_CH1WAITSTATUS */
<> 150:02e0a0aed4ec 169 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1WAITSTATUS */
<> 150:02e0a0aed4ec 170 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
<> 150:02e0a0aed4ec 171 #define DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
<> 150:02e0a0aed4ec 172 #define DMA_CHWAITSTATUS_CH2WAITSTATUS (0x1UL << 2) /**< Channel 2 Wait on Request Status */
<> 150:02e0a0aed4ec 173 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_SHIFT 2 /**< Shift value for DMA_CH2WAITSTATUS */
<> 150:02e0a0aed4ec 174 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2WAITSTATUS */
<> 150:02e0a0aed4ec 175 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
<> 150:02e0a0aed4ec 176 #define DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
<> 150:02e0a0aed4ec 177 #define DMA_CHWAITSTATUS_CH3WAITSTATUS (0x1UL << 3) /**< Channel 3 Wait on Request Status */
<> 150:02e0a0aed4ec 178 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_SHIFT 3 /**< Shift value for DMA_CH3WAITSTATUS */
<> 150:02e0a0aed4ec 179 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3WAITSTATUS */
<> 150:02e0a0aed4ec 180 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
<> 150:02e0a0aed4ec 181 #define DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
<> 150:02e0a0aed4ec 182 #define DMA_CHWAITSTATUS_CH4WAITSTATUS (0x1UL << 4) /**< Channel 4 Wait on Request Status */
<> 150:02e0a0aed4ec 183 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_SHIFT 4 /**< Shift value for DMA_CH4WAITSTATUS */
<> 150:02e0a0aed4ec 184 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4WAITSTATUS */
<> 150:02e0a0aed4ec 185 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
<> 150:02e0a0aed4ec 186 #define DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
<> 150:02e0a0aed4ec 187 #define DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5) /**< Channel 5 Wait on Request Status */
<> 150:02e0a0aed4ec 188 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_SHIFT 5 /**< Shift value for DMA_CH5WAITSTATUS */
<> 150:02e0a0aed4ec 189 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5WAITSTATUS */
<> 150:02e0a0aed4ec 190 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
<> 150:02e0a0aed4ec 191 #define DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
<> 150:02e0a0aed4ec 192 #define DMA_CHWAITSTATUS_CH6WAITSTATUS (0x1UL << 6) /**< Channel 6 Wait on Request Status */
<> 150:02e0a0aed4ec 193 #define _DMA_CHWAITSTATUS_CH6WAITSTATUS_SHIFT 6 /**< Shift value for DMA_CH6WAITSTATUS */
<> 150:02e0a0aed4ec 194 #define _DMA_CHWAITSTATUS_CH6WAITSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6WAITSTATUS */
<> 150:02e0a0aed4ec 195 #define _DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
<> 150:02e0a0aed4ec 196 #define DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
<> 150:02e0a0aed4ec 197 #define DMA_CHWAITSTATUS_CH7WAITSTATUS (0x1UL << 7) /**< Channel 7 Wait on Request Status */
<> 150:02e0a0aed4ec 198 #define _DMA_CHWAITSTATUS_CH7WAITSTATUS_SHIFT 7 /**< Shift value for DMA_CH7WAITSTATUS */
<> 150:02e0a0aed4ec 199 #define _DMA_CHWAITSTATUS_CH7WAITSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7WAITSTATUS */
<> 150:02e0a0aed4ec 200 #define _DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
<> 150:02e0a0aed4ec 201 #define DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
<> 150:02e0a0aed4ec 202 #define DMA_CHWAITSTATUS_CH8WAITSTATUS (0x1UL << 8) /**< Channel 8 Wait on Request Status */
<> 150:02e0a0aed4ec 203 #define _DMA_CHWAITSTATUS_CH8WAITSTATUS_SHIFT 8 /**< Shift value for DMA_CH8WAITSTATUS */
<> 150:02e0a0aed4ec 204 #define _DMA_CHWAITSTATUS_CH8WAITSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8WAITSTATUS */
<> 150:02e0a0aed4ec 205 #define _DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
<> 150:02e0a0aed4ec 206 #define DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
<> 150:02e0a0aed4ec 207 #define DMA_CHWAITSTATUS_CH9WAITSTATUS (0x1UL << 9) /**< Channel 9 Wait on Request Status */
<> 150:02e0a0aed4ec 208 #define _DMA_CHWAITSTATUS_CH9WAITSTATUS_SHIFT 9 /**< Shift value for DMA_CH9WAITSTATUS */
<> 150:02e0a0aed4ec 209 #define _DMA_CHWAITSTATUS_CH9WAITSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9WAITSTATUS */
<> 150:02e0a0aed4ec 210 #define _DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
<> 150:02e0a0aed4ec 211 #define DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
<> 150:02e0a0aed4ec 212 #define DMA_CHWAITSTATUS_CH10WAITSTATUS (0x1UL << 10) /**< Channel 10 Wait on Request Status */
<> 150:02e0a0aed4ec 213 #define _DMA_CHWAITSTATUS_CH10WAITSTATUS_SHIFT 10 /**< Shift value for DMA_CH10WAITSTATUS */
<> 150:02e0a0aed4ec 214 #define _DMA_CHWAITSTATUS_CH10WAITSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10WAITSTATUS */
<> 150:02e0a0aed4ec 215 #define _DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
<> 150:02e0a0aed4ec 216 #define DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
<> 150:02e0a0aed4ec 217 #define DMA_CHWAITSTATUS_CH11WAITSTATUS (0x1UL << 11) /**< Channel 11 Wait on Request Status */
<> 150:02e0a0aed4ec 218 #define _DMA_CHWAITSTATUS_CH11WAITSTATUS_SHIFT 11 /**< Shift value for DMA_CH11WAITSTATUS */
<> 150:02e0a0aed4ec 219 #define _DMA_CHWAITSTATUS_CH11WAITSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11WAITSTATUS */
<> 150:02e0a0aed4ec 220 #define _DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
<> 150:02e0a0aed4ec 221 #define DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
<> 150:02e0a0aed4ec 222
<> 150:02e0a0aed4ec 223 /* Bit fields for DMA CHSWREQ */
<> 150:02e0a0aed4ec 224 #define _DMA_CHSWREQ_RESETVALUE 0x00000000UL /**< Default value for DMA_CHSWREQ */
<> 150:02e0a0aed4ec 225 #define _DMA_CHSWREQ_MASK 0x00000FFFUL /**< Mask for DMA_CHSWREQ */
<> 150:02e0a0aed4ec 226 #define DMA_CHSWREQ_CH0SWREQ (0x1UL << 0) /**< Channel 0 Software Request */
<> 150:02e0a0aed4ec 227 #define _DMA_CHSWREQ_CH0SWREQ_SHIFT 0 /**< Shift value for DMA_CH0SWREQ */
<> 150:02e0a0aed4ec 228 #define _DMA_CHSWREQ_CH0SWREQ_MASK 0x1UL /**< Bit mask for DMA_CH0SWREQ */
<> 150:02e0a0aed4ec 229 #define _DMA_CHSWREQ_CH0SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
<> 150:02e0a0aed4ec 230 #define DMA_CHSWREQ_CH0SWREQ_DEFAULT (_DMA_CHSWREQ_CH0SWREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
<> 150:02e0a0aed4ec 231 #define DMA_CHSWREQ_CH1SWREQ (0x1UL << 1) /**< Channel 1 Software Request */
<> 150:02e0a0aed4ec 232 #define _DMA_CHSWREQ_CH1SWREQ_SHIFT 1 /**< Shift value for DMA_CH1SWREQ */
<> 150:02e0a0aed4ec 233 #define _DMA_CHSWREQ_CH1SWREQ_MASK 0x2UL /**< Bit mask for DMA_CH1SWREQ */
<> 150:02e0a0aed4ec 234 #define _DMA_CHSWREQ_CH1SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
<> 150:02e0a0aed4ec 235 #define DMA_CHSWREQ_CH1SWREQ_DEFAULT (_DMA_CHSWREQ_CH1SWREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
<> 150:02e0a0aed4ec 236 #define DMA_CHSWREQ_CH2SWREQ (0x1UL << 2) /**< Channel 2 Software Request */
<> 150:02e0a0aed4ec 237 #define _DMA_CHSWREQ_CH2SWREQ_SHIFT 2 /**< Shift value for DMA_CH2SWREQ */
<> 150:02e0a0aed4ec 238 #define _DMA_CHSWREQ_CH2SWREQ_MASK 0x4UL /**< Bit mask for DMA_CH2SWREQ */
<> 150:02e0a0aed4ec 239 #define _DMA_CHSWREQ_CH2SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
<> 150:02e0a0aed4ec 240 #define DMA_CHSWREQ_CH2SWREQ_DEFAULT (_DMA_CHSWREQ_CH2SWREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
<> 150:02e0a0aed4ec 241 #define DMA_CHSWREQ_CH3SWREQ (0x1UL << 3) /**< Channel 3 Software Request */
<> 150:02e0a0aed4ec 242 #define _DMA_CHSWREQ_CH3SWREQ_SHIFT 3 /**< Shift value for DMA_CH3SWREQ */
<> 150:02e0a0aed4ec 243 #define _DMA_CHSWREQ_CH3SWREQ_MASK 0x8UL /**< Bit mask for DMA_CH3SWREQ */
<> 150:02e0a0aed4ec 244 #define _DMA_CHSWREQ_CH3SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
<> 150:02e0a0aed4ec 245 #define DMA_CHSWREQ_CH3SWREQ_DEFAULT (_DMA_CHSWREQ_CH3SWREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
<> 150:02e0a0aed4ec 246 #define DMA_CHSWREQ_CH4SWREQ (0x1UL << 4) /**< Channel 4 Software Request */
<> 150:02e0a0aed4ec 247 #define _DMA_CHSWREQ_CH4SWREQ_SHIFT 4 /**< Shift value for DMA_CH4SWREQ */
<> 150:02e0a0aed4ec 248 #define _DMA_CHSWREQ_CH4SWREQ_MASK 0x10UL /**< Bit mask for DMA_CH4SWREQ */
<> 150:02e0a0aed4ec 249 #define _DMA_CHSWREQ_CH4SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
<> 150:02e0a0aed4ec 250 #define DMA_CHSWREQ_CH4SWREQ_DEFAULT (_DMA_CHSWREQ_CH4SWREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
<> 150:02e0a0aed4ec 251 #define DMA_CHSWREQ_CH5SWREQ (0x1UL << 5) /**< Channel 5 Software Request */
<> 150:02e0a0aed4ec 252 #define _DMA_CHSWREQ_CH5SWREQ_SHIFT 5 /**< Shift value for DMA_CH5SWREQ */
<> 150:02e0a0aed4ec 253 #define _DMA_CHSWREQ_CH5SWREQ_MASK 0x20UL /**< Bit mask for DMA_CH5SWREQ */
<> 150:02e0a0aed4ec 254 #define _DMA_CHSWREQ_CH5SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
<> 150:02e0a0aed4ec 255 #define DMA_CHSWREQ_CH5SWREQ_DEFAULT (_DMA_CHSWREQ_CH5SWREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
<> 150:02e0a0aed4ec 256 #define DMA_CHSWREQ_CH6SWREQ (0x1UL << 6) /**< Channel 6 Software Request */
<> 150:02e0a0aed4ec 257 #define _DMA_CHSWREQ_CH6SWREQ_SHIFT 6 /**< Shift value for DMA_CH6SWREQ */
<> 150:02e0a0aed4ec 258 #define _DMA_CHSWREQ_CH6SWREQ_MASK 0x40UL /**< Bit mask for DMA_CH6SWREQ */
<> 150:02e0a0aed4ec 259 #define _DMA_CHSWREQ_CH6SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
<> 150:02e0a0aed4ec 260 #define DMA_CHSWREQ_CH6SWREQ_DEFAULT (_DMA_CHSWREQ_CH6SWREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
<> 150:02e0a0aed4ec 261 #define DMA_CHSWREQ_CH7SWREQ (0x1UL << 7) /**< Channel 7 Software Request */
<> 150:02e0a0aed4ec 262 #define _DMA_CHSWREQ_CH7SWREQ_SHIFT 7 /**< Shift value for DMA_CH7SWREQ */
<> 150:02e0a0aed4ec 263 #define _DMA_CHSWREQ_CH7SWREQ_MASK 0x80UL /**< Bit mask for DMA_CH7SWREQ */
<> 150:02e0a0aed4ec 264 #define _DMA_CHSWREQ_CH7SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
<> 150:02e0a0aed4ec 265 #define DMA_CHSWREQ_CH7SWREQ_DEFAULT (_DMA_CHSWREQ_CH7SWREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
<> 150:02e0a0aed4ec 266 #define DMA_CHSWREQ_CH8SWREQ (0x1UL << 8) /**< Channel 8 Software Request */
<> 150:02e0a0aed4ec 267 #define _DMA_CHSWREQ_CH8SWREQ_SHIFT 8 /**< Shift value for DMA_CH8SWREQ */
<> 150:02e0a0aed4ec 268 #define _DMA_CHSWREQ_CH8SWREQ_MASK 0x100UL /**< Bit mask for DMA_CH8SWREQ */
<> 150:02e0a0aed4ec 269 #define _DMA_CHSWREQ_CH8SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
<> 150:02e0a0aed4ec 270 #define DMA_CHSWREQ_CH8SWREQ_DEFAULT (_DMA_CHSWREQ_CH8SWREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
<> 150:02e0a0aed4ec 271 #define DMA_CHSWREQ_CH9SWREQ (0x1UL << 9) /**< Channel 9 Software Request */
<> 150:02e0a0aed4ec 272 #define _DMA_CHSWREQ_CH9SWREQ_SHIFT 9 /**< Shift value for DMA_CH9SWREQ */
<> 150:02e0a0aed4ec 273 #define _DMA_CHSWREQ_CH9SWREQ_MASK 0x200UL /**< Bit mask for DMA_CH9SWREQ */
<> 150:02e0a0aed4ec 274 #define _DMA_CHSWREQ_CH9SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
<> 150:02e0a0aed4ec 275 #define DMA_CHSWREQ_CH9SWREQ_DEFAULT (_DMA_CHSWREQ_CH9SWREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
<> 150:02e0a0aed4ec 276 #define DMA_CHSWREQ_CH10SWREQ (0x1UL << 10) /**< Channel 10 Software Request */
<> 150:02e0a0aed4ec 277 #define _DMA_CHSWREQ_CH10SWREQ_SHIFT 10 /**< Shift value for DMA_CH10SWREQ */
<> 150:02e0a0aed4ec 278 #define _DMA_CHSWREQ_CH10SWREQ_MASK 0x400UL /**< Bit mask for DMA_CH10SWREQ */
<> 150:02e0a0aed4ec 279 #define _DMA_CHSWREQ_CH10SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
<> 150:02e0a0aed4ec 280 #define DMA_CHSWREQ_CH10SWREQ_DEFAULT (_DMA_CHSWREQ_CH10SWREQ_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
<> 150:02e0a0aed4ec 281 #define DMA_CHSWREQ_CH11SWREQ (0x1UL << 11) /**< Channel 11 Software Request */
<> 150:02e0a0aed4ec 282 #define _DMA_CHSWREQ_CH11SWREQ_SHIFT 11 /**< Shift value for DMA_CH11SWREQ */
<> 150:02e0a0aed4ec 283 #define _DMA_CHSWREQ_CH11SWREQ_MASK 0x800UL /**< Bit mask for DMA_CH11SWREQ */
<> 150:02e0a0aed4ec 284 #define _DMA_CHSWREQ_CH11SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
<> 150:02e0a0aed4ec 285 #define DMA_CHSWREQ_CH11SWREQ_DEFAULT (_DMA_CHSWREQ_CH11SWREQ_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
<> 150:02e0a0aed4ec 286
<> 150:02e0a0aed4ec 287 /* Bit fields for DMA CHUSEBURSTS */
<> 150:02e0a0aed4ec 288 #define _DMA_CHUSEBURSTS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 289 #define _DMA_CHUSEBURSTS_MASK 0x00000FFFUL /**< Mask for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 290 #define DMA_CHUSEBURSTS_CH0USEBURSTS (0x1UL << 0) /**< Channel 0 Useburst Set */
<> 150:02e0a0aed4ec 291 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_SHIFT 0 /**< Shift value for DMA_CH0USEBURSTS */
<> 150:02e0a0aed4ec 292 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_MASK 0x1UL /**< Bit mask for DMA_CH0USEBURSTS */
<> 150:02e0a0aed4ec 293 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 294 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST 0x00000000UL /**< Mode SINGLEANDBURST for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 295 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY 0x00000001UL /**< Mode BURSTONLY for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 296 #define DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 297 #define DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST (_DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST << 0) /**< Shifted mode SINGLEANDBURST for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 298 #define DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY (_DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY << 0) /**< Shifted mode BURSTONLY for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 299 #define DMA_CHUSEBURSTS_CH1USEBURSTS (0x1UL << 1) /**< Channel 1 Useburst Set */
<> 150:02e0a0aed4ec 300 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_SHIFT 1 /**< Shift value for DMA_CH1USEBURSTS */
<> 150:02e0a0aed4ec 301 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_MASK 0x2UL /**< Bit mask for DMA_CH1USEBURSTS */
<> 150:02e0a0aed4ec 302 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 303 #define DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 304 #define DMA_CHUSEBURSTS_CH2USEBURSTS (0x1UL << 2) /**< Channel 2 Useburst Set */
<> 150:02e0a0aed4ec 305 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_SHIFT 2 /**< Shift value for DMA_CH2USEBURSTS */
<> 150:02e0a0aed4ec 306 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_MASK 0x4UL /**< Bit mask for DMA_CH2USEBURSTS */
<> 150:02e0a0aed4ec 307 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 308 #define DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 309 #define DMA_CHUSEBURSTS_CH3USEBURSTS (0x1UL << 3) /**< Channel 3 Useburst Set */
<> 150:02e0a0aed4ec 310 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_SHIFT 3 /**< Shift value for DMA_CH3USEBURSTS */
<> 150:02e0a0aed4ec 311 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_MASK 0x8UL /**< Bit mask for DMA_CH3USEBURSTS */
<> 150:02e0a0aed4ec 312 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 313 #define DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 314 #define DMA_CHUSEBURSTS_CH4USEBURSTS (0x1UL << 4) /**< Channel 4 Useburst Set */
<> 150:02e0a0aed4ec 315 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_SHIFT 4 /**< Shift value for DMA_CH4USEBURSTS */
<> 150:02e0a0aed4ec 316 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_MASK 0x10UL /**< Bit mask for DMA_CH4USEBURSTS */
<> 150:02e0a0aed4ec 317 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 318 #define DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 319 #define DMA_CHUSEBURSTS_CH5USEBURSTS (0x1UL << 5) /**< Channel 5 Useburst Set */
<> 150:02e0a0aed4ec 320 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_SHIFT 5 /**< Shift value for DMA_CH5USEBURSTS */
<> 150:02e0a0aed4ec 321 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_MASK 0x20UL /**< Bit mask for DMA_CH5USEBURSTS */
<> 150:02e0a0aed4ec 322 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 323 #define DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 324 #define DMA_CHUSEBURSTS_CH6USEBURSTS (0x1UL << 6) /**< Channel 6 Useburst Set */
<> 150:02e0a0aed4ec 325 #define _DMA_CHUSEBURSTS_CH6USEBURSTS_SHIFT 6 /**< Shift value for DMA_CH6USEBURSTS */
<> 150:02e0a0aed4ec 326 #define _DMA_CHUSEBURSTS_CH6USEBURSTS_MASK 0x40UL /**< Bit mask for DMA_CH6USEBURSTS */
<> 150:02e0a0aed4ec 327 #define _DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 328 #define DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 329 #define DMA_CHUSEBURSTS_CH7USEBURSTS (0x1UL << 7) /**< Channel 7 Useburst Set */
<> 150:02e0a0aed4ec 330 #define _DMA_CHUSEBURSTS_CH7USEBURSTS_SHIFT 7 /**< Shift value for DMA_CH7USEBURSTS */
<> 150:02e0a0aed4ec 331 #define _DMA_CHUSEBURSTS_CH7USEBURSTS_MASK 0x80UL /**< Bit mask for DMA_CH7USEBURSTS */
<> 150:02e0a0aed4ec 332 #define _DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 333 #define DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 334 #define DMA_CHUSEBURSTS_CH8USEBURSTS (0x1UL << 8) /**< Channel 8 Useburst Set */
<> 150:02e0a0aed4ec 335 #define _DMA_CHUSEBURSTS_CH8USEBURSTS_SHIFT 8 /**< Shift value for DMA_CH8USEBURSTS */
<> 150:02e0a0aed4ec 336 #define _DMA_CHUSEBURSTS_CH8USEBURSTS_MASK 0x100UL /**< Bit mask for DMA_CH8USEBURSTS */
<> 150:02e0a0aed4ec 337 #define _DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 338 #define DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 339 #define DMA_CHUSEBURSTS_CH9USEBURSTS (0x1UL << 9) /**< Channel 9 Useburst Set */
<> 150:02e0a0aed4ec 340 #define _DMA_CHUSEBURSTS_CH9USEBURSTS_SHIFT 9 /**< Shift value for DMA_CH9USEBURSTS */
<> 150:02e0a0aed4ec 341 #define _DMA_CHUSEBURSTS_CH9USEBURSTS_MASK 0x200UL /**< Bit mask for DMA_CH9USEBURSTS */
<> 150:02e0a0aed4ec 342 #define _DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 343 #define DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 344 #define DMA_CHUSEBURSTS_CH10USEBURSTS (0x1UL << 10) /**< Channel 10 Useburst Set */
<> 150:02e0a0aed4ec 345 #define _DMA_CHUSEBURSTS_CH10USEBURSTS_SHIFT 10 /**< Shift value for DMA_CH10USEBURSTS */
<> 150:02e0a0aed4ec 346 #define _DMA_CHUSEBURSTS_CH10USEBURSTS_MASK 0x400UL /**< Bit mask for DMA_CH10USEBURSTS */
<> 150:02e0a0aed4ec 347 #define _DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 348 #define DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 349 #define DMA_CHUSEBURSTS_CH11USEBURSTS (0x1UL << 11) /**< Channel 11 Useburst Set */
<> 150:02e0a0aed4ec 350 #define _DMA_CHUSEBURSTS_CH11USEBURSTS_SHIFT 11 /**< Shift value for DMA_CH11USEBURSTS */
<> 150:02e0a0aed4ec 351 #define _DMA_CHUSEBURSTS_CH11USEBURSTS_MASK 0x800UL /**< Bit mask for DMA_CH11USEBURSTS */
<> 150:02e0a0aed4ec 352 #define _DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 353 #define DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 354
<> 150:02e0a0aed4ec 355 /* Bit fields for DMA CHUSEBURSTC */
<> 150:02e0a0aed4ec 356 #define _DMA_CHUSEBURSTC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHUSEBURSTC */
<> 150:02e0a0aed4ec 357 #define _DMA_CHUSEBURSTC_MASK 0x00000FFFUL /**< Mask for DMA_CHUSEBURSTC */
<> 150:02e0a0aed4ec 358 #define DMA_CHUSEBURSTC_CH0USEBURSTC (0x1UL << 0) /**< Channel 0 Useburst Clear */
<> 150:02e0a0aed4ec 359 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_SHIFT 0 /**< Shift value for DMA_CH0USEBURSTC */
<> 150:02e0a0aed4ec 360 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_MASK 0x1UL /**< Bit mask for DMA_CH0USEBURSTC */
<> 150:02e0a0aed4ec 361 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
<> 150:02e0a0aed4ec 362 #define DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
<> 150:02e0a0aed4ec 363 #define DMA_CHUSEBURSTC_CH1USEBURSTC (0x1UL << 1) /**< Channel 1 Useburst Clear */
<> 150:02e0a0aed4ec 364 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_SHIFT 1 /**< Shift value for DMA_CH1USEBURSTC */
<> 150:02e0a0aed4ec 365 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_MASK 0x2UL /**< Bit mask for DMA_CH1USEBURSTC */
<> 150:02e0a0aed4ec 366 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
<> 150:02e0a0aed4ec 367 #define DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
<> 150:02e0a0aed4ec 368 #define DMA_CHUSEBURSTC_CH2USEBURSTC (0x1UL << 2) /**< Channel 2 Useburst Clear */
<> 150:02e0a0aed4ec 369 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_SHIFT 2 /**< Shift value for DMA_CH2USEBURSTC */
<> 150:02e0a0aed4ec 370 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_MASK 0x4UL /**< Bit mask for DMA_CH2USEBURSTC */
<> 150:02e0a0aed4ec 371 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
<> 150:02e0a0aed4ec 372 #define DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
<> 150:02e0a0aed4ec 373 #define DMA_CHUSEBURSTC_CH3USEBURSTC (0x1UL << 3) /**< Channel 3 Useburst Clear */
<> 150:02e0a0aed4ec 374 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_SHIFT 3 /**< Shift value for DMA_CH3USEBURSTC */
<> 150:02e0a0aed4ec 375 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_MASK 0x8UL /**< Bit mask for DMA_CH3USEBURSTC */
<> 150:02e0a0aed4ec 376 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
<> 150:02e0a0aed4ec 377 #define DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
<> 150:02e0a0aed4ec 378 #define DMA_CHUSEBURSTC_CH4USEBURSTC (0x1UL << 4) /**< Channel 4 Useburst Clear */
<> 150:02e0a0aed4ec 379 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_SHIFT 4 /**< Shift value for DMA_CH4USEBURSTC */
<> 150:02e0a0aed4ec 380 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_MASK 0x10UL /**< Bit mask for DMA_CH4USEBURSTC */
<> 150:02e0a0aed4ec 381 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
<> 150:02e0a0aed4ec 382 #define DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
<> 150:02e0a0aed4ec 383 #define DMA_CHUSEBURSTC_CH5USEBURSTC (0x1UL << 5) /**< Channel 5 Useburst Clear */
<> 150:02e0a0aed4ec 384 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_SHIFT 5 /**< Shift value for DMA_CH5USEBURSTC */
<> 150:02e0a0aed4ec 385 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_MASK 0x20UL /**< Bit mask for DMA_CH5USEBURSTC */
<> 150:02e0a0aed4ec 386 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
<> 150:02e0a0aed4ec 387 #define DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
<> 150:02e0a0aed4ec 388 #define DMA_CHUSEBURSTC_CH6USEBURSTC (0x1UL << 6) /**< Channel 6 Useburst Clear */
<> 150:02e0a0aed4ec 389 #define _DMA_CHUSEBURSTC_CH6USEBURSTC_SHIFT 6 /**< Shift value for DMA_CH6USEBURSTC */
<> 150:02e0a0aed4ec 390 #define _DMA_CHUSEBURSTC_CH6USEBURSTC_MASK 0x40UL /**< Bit mask for DMA_CH6USEBURSTC */
<> 150:02e0a0aed4ec 391 #define _DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
<> 150:02e0a0aed4ec 392 #define DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
<> 150:02e0a0aed4ec 393 #define DMA_CHUSEBURSTC_CH7USEBURSTC (0x1UL << 7) /**< Channel 7 Useburst Clear */
<> 150:02e0a0aed4ec 394 #define _DMA_CHUSEBURSTC_CH7USEBURSTC_SHIFT 7 /**< Shift value for DMA_CH7USEBURSTC */
<> 150:02e0a0aed4ec 395 #define _DMA_CHUSEBURSTC_CH7USEBURSTC_MASK 0x80UL /**< Bit mask for DMA_CH7USEBURSTC */
<> 150:02e0a0aed4ec 396 #define _DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
<> 150:02e0a0aed4ec 397 #define DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
<> 150:02e0a0aed4ec 398 #define DMA_CHUSEBURSTC_CH08USEBURSTC (0x1UL << 8) /**< Channel 8 Useburst Clear */
<> 150:02e0a0aed4ec 399 #define _DMA_CHUSEBURSTC_CH08USEBURSTC_SHIFT 8 /**< Shift value for DMA_CH08USEBURSTC */
<> 150:02e0a0aed4ec 400 #define _DMA_CHUSEBURSTC_CH08USEBURSTC_MASK 0x100UL /**< Bit mask for DMA_CH08USEBURSTC */
<> 150:02e0a0aed4ec 401 #define _DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
<> 150:02e0a0aed4ec 402 #define DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
<> 150:02e0a0aed4ec 403 #define DMA_CHUSEBURSTC_CH9USEBURSTC (0x1UL << 9) /**< Channel 9 Useburst Clear */
<> 150:02e0a0aed4ec 404 #define _DMA_CHUSEBURSTC_CH9USEBURSTC_SHIFT 9 /**< Shift value for DMA_CH9USEBURSTC */
<> 150:02e0a0aed4ec 405 #define _DMA_CHUSEBURSTC_CH9USEBURSTC_MASK 0x200UL /**< Bit mask for DMA_CH9USEBURSTC */
<> 150:02e0a0aed4ec 406 #define _DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
<> 150:02e0a0aed4ec 407 #define DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
<> 150:02e0a0aed4ec 408 #define DMA_CHUSEBURSTC_CH10USEBURSTC (0x1UL << 10) /**< Channel 10 Useburst Clear */
<> 150:02e0a0aed4ec 409 #define _DMA_CHUSEBURSTC_CH10USEBURSTC_SHIFT 10 /**< Shift value for DMA_CH10USEBURSTC */
<> 150:02e0a0aed4ec 410 #define _DMA_CHUSEBURSTC_CH10USEBURSTC_MASK 0x400UL /**< Bit mask for DMA_CH10USEBURSTC */
<> 150:02e0a0aed4ec 411 #define _DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
<> 150:02e0a0aed4ec 412 #define DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
<> 150:02e0a0aed4ec 413 #define DMA_CHUSEBURSTC_CH11USEBURSTC (0x1UL << 11) /**< Channel 11 Useburst Clear */
<> 150:02e0a0aed4ec 414 #define _DMA_CHUSEBURSTC_CH11USEBURSTC_SHIFT 11 /**< Shift value for DMA_CH11USEBURSTC */
<> 150:02e0a0aed4ec 415 #define _DMA_CHUSEBURSTC_CH11USEBURSTC_MASK 0x800UL /**< Bit mask for DMA_CH11USEBURSTC */
<> 150:02e0a0aed4ec 416 #define _DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
<> 150:02e0a0aed4ec 417 #define DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
<> 150:02e0a0aed4ec 418
<> 150:02e0a0aed4ec 419 /* Bit fields for DMA CHREQMASKS */
<> 150:02e0a0aed4ec 420 #define _DMA_CHREQMASKS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQMASKS */
<> 150:02e0a0aed4ec 421 #define _DMA_CHREQMASKS_MASK 0x00000FFFUL /**< Mask for DMA_CHREQMASKS */
<> 150:02e0a0aed4ec 422 #define DMA_CHREQMASKS_CH0REQMASKS (0x1UL << 0) /**< Channel 0 Request Mask Set */
<> 150:02e0a0aed4ec 423 #define _DMA_CHREQMASKS_CH0REQMASKS_SHIFT 0 /**< Shift value for DMA_CH0REQMASKS */
<> 150:02e0a0aed4ec 424 #define _DMA_CHREQMASKS_CH0REQMASKS_MASK 0x1UL /**< Bit mask for DMA_CH0REQMASKS */
<> 150:02e0a0aed4ec 425 #define _DMA_CHREQMASKS_CH0REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
<> 150:02e0a0aed4ec 426 #define DMA_CHREQMASKS_CH0REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH0REQMASKS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
<> 150:02e0a0aed4ec 427 #define DMA_CHREQMASKS_CH1REQMASKS (0x1UL << 1) /**< Channel 1 Request Mask Set */
<> 150:02e0a0aed4ec 428 #define _DMA_CHREQMASKS_CH1REQMASKS_SHIFT 1 /**< Shift value for DMA_CH1REQMASKS */
<> 150:02e0a0aed4ec 429 #define _DMA_CHREQMASKS_CH1REQMASKS_MASK 0x2UL /**< Bit mask for DMA_CH1REQMASKS */
<> 150:02e0a0aed4ec 430 #define _DMA_CHREQMASKS_CH1REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
<> 150:02e0a0aed4ec 431 #define DMA_CHREQMASKS_CH1REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH1REQMASKS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
<> 150:02e0a0aed4ec 432 #define DMA_CHREQMASKS_CH2REQMASKS (0x1UL << 2) /**< Channel 2 Request Mask Set */
<> 150:02e0a0aed4ec 433 #define _DMA_CHREQMASKS_CH2REQMASKS_SHIFT 2 /**< Shift value for DMA_CH2REQMASKS */
<> 150:02e0a0aed4ec 434 #define _DMA_CHREQMASKS_CH2REQMASKS_MASK 0x4UL /**< Bit mask for DMA_CH2REQMASKS */
<> 150:02e0a0aed4ec 435 #define _DMA_CHREQMASKS_CH2REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
<> 150:02e0a0aed4ec 436 #define DMA_CHREQMASKS_CH2REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH2REQMASKS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
<> 150:02e0a0aed4ec 437 #define DMA_CHREQMASKS_CH3REQMASKS (0x1UL << 3) /**< Channel 3 Request Mask Set */
<> 150:02e0a0aed4ec 438 #define _DMA_CHREQMASKS_CH3REQMASKS_SHIFT 3 /**< Shift value for DMA_CH3REQMASKS */
<> 150:02e0a0aed4ec 439 #define _DMA_CHREQMASKS_CH3REQMASKS_MASK 0x8UL /**< Bit mask for DMA_CH3REQMASKS */
<> 150:02e0a0aed4ec 440 #define _DMA_CHREQMASKS_CH3REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
<> 150:02e0a0aed4ec 441 #define DMA_CHREQMASKS_CH3REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH3REQMASKS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
<> 150:02e0a0aed4ec 442 #define DMA_CHREQMASKS_CH4REQMASKS (0x1UL << 4) /**< Channel 4 Request Mask Set */
<> 150:02e0a0aed4ec 443 #define _DMA_CHREQMASKS_CH4REQMASKS_SHIFT 4 /**< Shift value for DMA_CH4REQMASKS */
<> 150:02e0a0aed4ec 444 #define _DMA_CHREQMASKS_CH4REQMASKS_MASK 0x10UL /**< Bit mask for DMA_CH4REQMASKS */
<> 150:02e0a0aed4ec 445 #define _DMA_CHREQMASKS_CH4REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
<> 150:02e0a0aed4ec 446 #define DMA_CHREQMASKS_CH4REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH4REQMASKS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
<> 150:02e0a0aed4ec 447 #define DMA_CHREQMASKS_CH5REQMASKS (0x1UL << 5) /**< Channel 5 Request Mask Set */
<> 150:02e0a0aed4ec 448 #define _DMA_CHREQMASKS_CH5REQMASKS_SHIFT 5 /**< Shift value for DMA_CH5REQMASKS */
<> 150:02e0a0aed4ec 449 #define _DMA_CHREQMASKS_CH5REQMASKS_MASK 0x20UL /**< Bit mask for DMA_CH5REQMASKS */
<> 150:02e0a0aed4ec 450 #define _DMA_CHREQMASKS_CH5REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
<> 150:02e0a0aed4ec 451 #define DMA_CHREQMASKS_CH5REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH5REQMASKS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
<> 150:02e0a0aed4ec 452 #define DMA_CHREQMASKS_CH6REQMASKS (0x1UL << 6) /**< Channel 6 Request Mask Set */
<> 150:02e0a0aed4ec 453 #define _DMA_CHREQMASKS_CH6REQMASKS_SHIFT 6 /**< Shift value for DMA_CH6REQMASKS */
<> 150:02e0a0aed4ec 454 #define _DMA_CHREQMASKS_CH6REQMASKS_MASK 0x40UL /**< Bit mask for DMA_CH6REQMASKS */
<> 150:02e0a0aed4ec 455 #define _DMA_CHREQMASKS_CH6REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
<> 150:02e0a0aed4ec 456 #define DMA_CHREQMASKS_CH6REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH6REQMASKS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
<> 150:02e0a0aed4ec 457 #define DMA_CHREQMASKS_CH7REQMASKS (0x1UL << 7) /**< Channel 7 Request Mask Set */
<> 150:02e0a0aed4ec 458 #define _DMA_CHREQMASKS_CH7REQMASKS_SHIFT 7 /**< Shift value for DMA_CH7REQMASKS */
<> 150:02e0a0aed4ec 459 #define _DMA_CHREQMASKS_CH7REQMASKS_MASK 0x80UL /**< Bit mask for DMA_CH7REQMASKS */
<> 150:02e0a0aed4ec 460 #define _DMA_CHREQMASKS_CH7REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
<> 150:02e0a0aed4ec 461 #define DMA_CHREQMASKS_CH7REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH7REQMASKS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
<> 150:02e0a0aed4ec 462 #define DMA_CHREQMASKS_CH8REQMASKS (0x1UL << 8) /**< Channel 8 Request Mask Set */
<> 150:02e0a0aed4ec 463 #define _DMA_CHREQMASKS_CH8REQMASKS_SHIFT 8 /**< Shift value for DMA_CH8REQMASKS */
<> 150:02e0a0aed4ec 464 #define _DMA_CHREQMASKS_CH8REQMASKS_MASK 0x100UL /**< Bit mask for DMA_CH8REQMASKS */
<> 150:02e0a0aed4ec 465 #define _DMA_CHREQMASKS_CH8REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
<> 150:02e0a0aed4ec 466 #define DMA_CHREQMASKS_CH8REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH8REQMASKS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
<> 150:02e0a0aed4ec 467 #define DMA_CHREQMASKS_CH9REQMASKS (0x1UL << 9) /**< Channel 9 Request Mask Set */
<> 150:02e0a0aed4ec 468 #define _DMA_CHREQMASKS_CH9REQMASKS_SHIFT 9 /**< Shift value for DMA_CH9REQMASKS */
<> 150:02e0a0aed4ec 469 #define _DMA_CHREQMASKS_CH9REQMASKS_MASK 0x200UL /**< Bit mask for DMA_CH9REQMASKS */
<> 150:02e0a0aed4ec 470 #define _DMA_CHREQMASKS_CH9REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
<> 150:02e0a0aed4ec 471 #define DMA_CHREQMASKS_CH9REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH9REQMASKS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
<> 150:02e0a0aed4ec 472 #define DMA_CHREQMASKS_CH10REQMASKS (0x1UL << 10) /**< Channel 10 Request Mask Set */
<> 150:02e0a0aed4ec 473 #define _DMA_CHREQMASKS_CH10REQMASKS_SHIFT 10 /**< Shift value for DMA_CH10REQMASKS */
<> 150:02e0a0aed4ec 474 #define _DMA_CHREQMASKS_CH10REQMASKS_MASK 0x400UL /**< Bit mask for DMA_CH10REQMASKS */
<> 150:02e0a0aed4ec 475 #define _DMA_CHREQMASKS_CH10REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
<> 150:02e0a0aed4ec 476 #define DMA_CHREQMASKS_CH10REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH10REQMASKS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
<> 150:02e0a0aed4ec 477 #define DMA_CHREQMASKS_CH11REQMASKS (0x1UL << 11) /**< Channel 11 Request Mask Set */
<> 150:02e0a0aed4ec 478 #define _DMA_CHREQMASKS_CH11REQMASKS_SHIFT 11 /**< Shift value for DMA_CH11REQMASKS */
<> 150:02e0a0aed4ec 479 #define _DMA_CHREQMASKS_CH11REQMASKS_MASK 0x800UL /**< Bit mask for DMA_CH11REQMASKS */
<> 150:02e0a0aed4ec 480 #define _DMA_CHREQMASKS_CH11REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
<> 150:02e0a0aed4ec 481 #define DMA_CHREQMASKS_CH11REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH11REQMASKS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
<> 150:02e0a0aed4ec 482
<> 150:02e0a0aed4ec 483 /* Bit fields for DMA CHREQMASKC */
<> 150:02e0a0aed4ec 484 #define _DMA_CHREQMASKC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQMASKC */
<> 150:02e0a0aed4ec 485 #define _DMA_CHREQMASKC_MASK 0x00000FFFUL /**< Mask for DMA_CHREQMASKC */
<> 150:02e0a0aed4ec 486 #define DMA_CHREQMASKC_CH0REQMASKC (0x1UL << 0) /**< Channel 0 Request Mask Clear */
<> 150:02e0a0aed4ec 487 #define _DMA_CHREQMASKC_CH0REQMASKC_SHIFT 0 /**< Shift value for DMA_CH0REQMASKC */
<> 150:02e0a0aed4ec 488 #define _DMA_CHREQMASKC_CH0REQMASKC_MASK 0x1UL /**< Bit mask for DMA_CH0REQMASKC */
<> 150:02e0a0aed4ec 489 #define _DMA_CHREQMASKC_CH0REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
<> 150:02e0a0aed4ec 490 #define DMA_CHREQMASKC_CH0REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH0REQMASKC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
<> 150:02e0a0aed4ec 491 #define DMA_CHREQMASKC_CH1REQMASKC (0x1UL << 1) /**< Channel 1 Request Mask Clear */
<> 150:02e0a0aed4ec 492 #define _DMA_CHREQMASKC_CH1REQMASKC_SHIFT 1 /**< Shift value for DMA_CH1REQMASKC */
<> 150:02e0a0aed4ec 493 #define _DMA_CHREQMASKC_CH1REQMASKC_MASK 0x2UL /**< Bit mask for DMA_CH1REQMASKC */
<> 150:02e0a0aed4ec 494 #define _DMA_CHREQMASKC_CH1REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
<> 150:02e0a0aed4ec 495 #define DMA_CHREQMASKC_CH1REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH1REQMASKC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
<> 150:02e0a0aed4ec 496 #define DMA_CHREQMASKC_CH2REQMASKC (0x1UL << 2) /**< Channel 2 Request Mask Clear */
<> 150:02e0a0aed4ec 497 #define _DMA_CHREQMASKC_CH2REQMASKC_SHIFT 2 /**< Shift value for DMA_CH2REQMASKC */
<> 150:02e0a0aed4ec 498 #define _DMA_CHREQMASKC_CH2REQMASKC_MASK 0x4UL /**< Bit mask for DMA_CH2REQMASKC */
<> 150:02e0a0aed4ec 499 #define _DMA_CHREQMASKC_CH2REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
<> 150:02e0a0aed4ec 500 #define DMA_CHREQMASKC_CH2REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH2REQMASKC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
<> 150:02e0a0aed4ec 501 #define DMA_CHREQMASKC_CH3REQMASKC (0x1UL << 3) /**< Channel 3 Request Mask Clear */
<> 150:02e0a0aed4ec 502 #define _DMA_CHREQMASKC_CH3REQMASKC_SHIFT 3 /**< Shift value for DMA_CH3REQMASKC */
<> 150:02e0a0aed4ec 503 #define _DMA_CHREQMASKC_CH3REQMASKC_MASK 0x8UL /**< Bit mask for DMA_CH3REQMASKC */
<> 150:02e0a0aed4ec 504 #define _DMA_CHREQMASKC_CH3REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
<> 150:02e0a0aed4ec 505 #define DMA_CHREQMASKC_CH3REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH3REQMASKC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
<> 150:02e0a0aed4ec 506 #define DMA_CHREQMASKC_CH4REQMASKC (0x1UL << 4) /**< Channel 4 Request Mask Clear */
<> 150:02e0a0aed4ec 507 #define _DMA_CHREQMASKC_CH4REQMASKC_SHIFT 4 /**< Shift value for DMA_CH4REQMASKC */
<> 150:02e0a0aed4ec 508 #define _DMA_CHREQMASKC_CH4REQMASKC_MASK 0x10UL /**< Bit mask for DMA_CH4REQMASKC */
<> 150:02e0a0aed4ec 509 #define _DMA_CHREQMASKC_CH4REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
<> 150:02e0a0aed4ec 510 #define DMA_CHREQMASKC_CH4REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH4REQMASKC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
<> 150:02e0a0aed4ec 511 #define DMA_CHREQMASKC_CH5REQMASKC (0x1UL << 5) /**< Channel 5 Request Mask Clear */
<> 150:02e0a0aed4ec 512 #define _DMA_CHREQMASKC_CH5REQMASKC_SHIFT 5 /**< Shift value for DMA_CH5REQMASKC */
<> 150:02e0a0aed4ec 513 #define _DMA_CHREQMASKC_CH5REQMASKC_MASK 0x20UL /**< Bit mask for DMA_CH5REQMASKC */
<> 150:02e0a0aed4ec 514 #define _DMA_CHREQMASKC_CH5REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
<> 150:02e0a0aed4ec 515 #define DMA_CHREQMASKC_CH5REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH5REQMASKC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
<> 150:02e0a0aed4ec 516 #define DMA_CHREQMASKC_CH6REQMASKC (0x1UL << 6) /**< Channel 6 Request Mask Clear */
<> 150:02e0a0aed4ec 517 #define _DMA_CHREQMASKC_CH6REQMASKC_SHIFT 6 /**< Shift value for DMA_CH6REQMASKC */
<> 150:02e0a0aed4ec 518 #define _DMA_CHREQMASKC_CH6REQMASKC_MASK 0x40UL /**< Bit mask for DMA_CH6REQMASKC */
<> 150:02e0a0aed4ec 519 #define _DMA_CHREQMASKC_CH6REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
<> 150:02e0a0aed4ec 520 #define DMA_CHREQMASKC_CH6REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH6REQMASKC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
<> 150:02e0a0aed4ec 521 #define DMA_CHREQMASKC_CH7REQMASKC (0x1UL << 7) /**< Channel 7 Request Mask Clear */
<> 150:02e0a0aed4ec 522 #define _DMA_CHREQMASKC_CH7REQMASKC_SHIFT 7 /**< Shift value for DMA_CH7REQMASKC */
<> 150:02e0a0aed4ec 523 #define _DMA_CHREQMASKC_CH7REQMASKC_MASK 0x80UL /**< Bit mask for DMA_CH7REQMASKC */
<> 150:02e0a0aed4ec 524 #define _DMA_CHREQMASKC_CH7REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
<> 150:02e0a0aed4ec 525 #define DMA_CHREQMASKC_CH7REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH7REQMASKC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
<> 150:02e0a0aed4ec 526 #define DMA_CHREQMASKC_CH8REQMASKC (0x1UL << 8) /**< Channel 8 Request Mask Clear */
<> 150:02e0a0aed4ec 527 #define _DMA_CHREQMASKC_CH8REQMASKC_SHIFT 8 /**< Shift value for DMA_CH8REQMASKC */
<> 150:02e0a0aed4ec 528 #define _DMA_CHREQMASKC_CH8REQMASKC_MASK 0x100UL /**< Bit mask for DMA_CH8REQMASKC */
<> 150:02e0a0aed4ec 529 #define _DMA_CHREQMASKC_CH8REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
<> 150:02e0a0aed4ec 530 #define DMA_CHREQMASKC_CH8REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH8REQMASKC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
<> 150:02e0a0aed4ec 531 #define DMA_CHREQMASKC_CH9REQMASKC (0x1UL << 9) /**< Channel 9 Request Mask Clear */
<> 150:02e0a0aed4ec 532 #define _DMA_CHREQMASKC_CH9REQMASKC_SHIFT 9 /**< Shift value for DMA_CH9REQMASKC */
<> 150:02e0a0aed4ec 533 #define _DMA_CHREQMASKC_CH9REQMASKC_MASK 0x200UL /**< Bit mask for DMA_CH9REQMASKC */
<> 150:02e0a0aed4ec 534 #define _DMA_CHREQMASKC_CH9REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
<> 150:02e0a0aed4ec 535 #define DMA_CHREQMASKC_CH9REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH9REQMASKC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
<> 150:02e0a0aed4ec 536 #define DMA_CHREQMASKC_CH10REQMASKC (0x1UL << 10) /**< Channel 10 Request Mask Clear */
<> 150:02e0a0aed4ec 537 #define _DMA_CHREQMASKC_CH10REQMASKC_SHIFT 10 /**< Shift value for DMA_CH10REQMASKC */
<> 150:02e0a0aed4ec 538 #define _DMA_CHREQMASKC_CH10REQMASKC_MASK 0x400UL /**< Bit mask for DMA_CH10REQMASKC */
<> 150:02e0a0aed4ec 539 #define _DMA_CHREQMASKC_CH10REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
<> 150:02e0a0aed4ec 540 #define DMA_CHREQMASKC_CH10REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH10REQMASKC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
<> 150:02e0a0aed4ec 541 #define DMA_CHREQMASKC_CH11REQMASKC (0x1UL << 11) /**< Channel 11 Request Mask Clear */
<> 150:02e0a0aed4ec 542 #define _DMA_CHREQMASKC_CH11REQMASKC_SHIFT 11 /**< Shift value for DMA_CH11REQMASKC */
<> 150:02e0a0aed4ec 543 #define _DMA_CHREQMASKC_CH11REQMASKC_MASK 0x800UL /**< Bit mask for DMA_CH11REQMASKC */
<> 150:02e0a0aed4ec 544 #define _DMA_CHREQMASKC_CH11REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
<> 150:02e0a0aed4ec 545 #define DMA_CHREQMASKC_CH11REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH11REQMASKC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
<> 150:02e0a0aed4ec 546
<> 150:02e0a0aed4ec 547 /* Bit fields for DMA CHENS */
<> 150:02e0a0aed4ec 548 #define _DMA_CHENS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHENS */
<> 150:02e0a0aed4ec 549 #define _DMA_CHENS_MASK 0x00000FFFUL /**< Mask for DMA_CHENS */
<> 150:02e0a0aed4ec 550 #define DMA_CHENS_CH0ENS (0x1UL << 0) /**< Channel 0 Enable Set */
<> 150:02e0a0aed4ec 551 #define _DMA_CHENS_CH0ENS_SHIFT 0 /**< Shift value for DMA_CH0ENS */
<> 150:02e0a0aed4ec 552 #define _DMA_CHENS_CH0ENS_MASK 0x1UL /**< Bit mask for DMA_CH0ENS */
<> 150:02e0a0aed4ec 553 #define _DMA_CHENS_CH0ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
<> 150:02e0a0aed4ec 554 #define DMA_CHENS_CH0ENS_DEFAULT (_DMA_CHENS_CH0ENS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHENS */
<> 150:02e0a0aed4ec 555 #define DMA_CHENS_CH1ENS (0x1UL << 1) /**< Channel 1 Enable Set */
<> 150:02e0a0aed4ec 556 #define _DMA_CHENS_CH1ENS_SHIFT 1 /**< Shift value for DMA_CH1ENS */
<> 150:02e0a0aed4ec 557 #define _DMA_CHENS_CH1ENS_MASK 0x2UL /**< Bit mask for DMA_CH1ENS */
<> 150:02e0a0aed4ec 558 #define _DMA_CHENS_CH1ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
<> 150:02e0a0aed4ec 559 #define DMA_CHENS_CH1ENS_DEFAULT (_DMA_CHENS_CH1ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHENS */
<> 150:02e0a0aed4ec 560 #define DMA_CHENS_CH2ENS (0x1UL << 2) /**< Channel 2 Enable Set */
<> 150:02e0a0aed4ec 561 #define _DMA_CHENS_CH2ENS_SHIFT 2 /**< Shift value for DMA_CH2ENS */
<> 150:02e0a0aed4ec 562 #define _DMA_CHENS_CH2ENS_MASK 0x4UL /**< Bit mask for DMA_CH2ENS */
<> 150:02e0a0aed4ec 563 #define _DMA_CHENS_CH2ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
<> 150:02e0a0aed4ec 564 #define DMA_CHENS_CH2ENS_DEFAULT (_DMA_CHENS_CH2ENS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHENS */
<> 150:02e0a0aed4ec 565 #define DMA_CHENS_CH3ENS (0x1UL << 3) /**< Channel 3 Enable Set */
<> 150:02e0a0aed4ec 566 #define _DMA_CHENS_CH3ENS_SHIFT 3 /**< Shift value for DMA_CH3ENS */
<> 150:02e0a0aed4ec 567 #define _DMA_CHENS_CH3ENS_MASK 0x8UL /**< Bit mask for DMA_CH3ENS */
<> 150:02e0a0aed4ec 568 #define _DMA_CHENS_CH3ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
<> 150:02e0a0aed4ec 569 #define DMA_CHENS_CH3ENS_DEFAULT (_DMA_CHENS_CH3ENS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHENS */
<> 150:02e0a0aed4ec 570 #define DMA_CHENS_CH4ENS (0x1UL << 4) /**< Channel 4 Enable Set */
<> 150:02e0a0aed4ec 571 #define _DMA_CHENS_CH4ENS_SHIFT 4 /**< Shift value for DMA_CH4ENS */
<> 150:02e0a0aed4ec 572 #define _DMA_CHENS_CH4ENS_MASK 0x10UL /**< Bit mask for DMA_CH4ENS */
<> 150:02e0a0aed4ec 573 #define _DMA_CHENS_CH4ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
<> 150:02e0a0aed4ec 574 #define DMA_CHENS_CH4ENS_DEFAULT (_DMA_CHENS_CH4ENS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHENS */
<> 150:02e0a0aed4ec 575 #define DMA_CHENS_CH5ENS (0x1UL << 5) /**< Channel 5 Enable Set */
<> 150:02e0a0aed4ec 576 #define _DMA_CHENS_CH5ENS_SHIFT 5 /**< Shift value for DMA_CH5ENS */
<> 150:02e0a0aed4ec 577 #define _DMA_CHENS_CH5ENS_MASK 0x20UL /**< Bit mask for DMA_CH5ENS */
<> 150:02e0a0aed4ec 578 #define _DMA_CHENS_CH5ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
<> 150:02e0a0aed4ec 579 #define DMA_CHENS_CH5ENS_DEFAULT (_DMA_CHENS_CH5ENS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHENS */
<> 150:02e0a0aed4ec 580 #define DMA_CHENS_CH6ENS (0x1UL << 6) /**< Channel 6 Enable Set */
<> 150:02e0a0aed4ec 581 #define _DMA_CHENS_CH6ENS_SHIFT 6 /**< Shift value for DMA_CH6ENS */
<> 150:02e0a0aed4ec 582 #define _DMA_CHENS_CH6ENS_MASK 0x40UL /**< Bit mask for DMA_CH6ENS */
<> 150:02e0a0aed4ec 583 #define _DMA_CHENS_CH6ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
<> 150:02e0a0aed4ec 584 #define DMA_CHENS_CH6ENS_DEFAULT (_DMA_CHENS_CH6ENS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHENS */
<> 150:02e0a0aed4ec 585 #define DMA_CHENS_CH7ENS (0x1UL << 7) /**< Channel 7 Enable Set */
<> 150:02e0a0aed4ec 586 #define _DMA_CHENS_CH7ENS_SHIFT 7 /**< Shift value for DMA_CH7ENS */
<> 150:02e0a0aed4ec 587 #define _DMA_CHENS_CH7ENS_MASK 0x80UL /**< Bit mask for DMA_CH7ENS */
<> 150:02e0a0aed4ec 588 #define _DMA_CHENS_CH7ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
<> 150:02e0a0aed4ec 589 #define DMA_CHENS_CH7ENS_DEFAULT (_DMA_CHENS_CH7ENS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHENS */
<> 150:02e0a0aed4ec 590 #define DMA_CHENS_CH8ENS (0x1UL << 8) /**< Channel 8 Enable Set */
<> 150:02e0a0aed4ec 591 #define _DMA_CHENS_CH8ENS_SHIFT 8 /**< Shift value for DMA_CH8ENS */
<> 150:02e0a0aed4ec 592 #define _DMA_CHENS_CH8ENS_MASK 0x100UL /**< Bit mask for DMA_CH8ENS */
<> 150:02e0a0aed4ec 593 #define _DMA_CHENS_CH8ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
<> 150:02e0a0aed4ec 594 #define DMA_CHENS_CH8ENS_DEFAULT (_DMA_CHENS_CH8ENS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHENS */
<> 150:02e0a0aed4ec 595 #define DMA_CHENS_CH9ENS (0x1UL << 9) /**< Channel 9 Enable Set */
<> 150:02e0a0aed4ec 596 #define _DMA_CHENS_CH9ENS_SHIFT 9 /**< Shift value for DMA_CH9ENS */
<> 150:02e0a0aed4ec 597 #define _DMA_CHENS_CH9ENS_MASK 0x200UL /**< Bit mask for DMA_CH9ENS */
<> 150:02e0a0aed4ec 598 #define _DMA_CHENS_CH9ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
<> 150:02e0a0aed4ec 599 #define DMA_CHENS_CH9ENS_DEFAULT (_DMA_CHENS_CH9ENS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHENS */
<> 150:02e0a0aed4ec 600 #define DMA_CHENS_CH10ENS (0x1UL << 10) /**< Channel 10 Enable Set */
<> 150:02e0a0aed4ec 601 #define _DMA_CHENS_CH10ENS_SHIFT 10 /**< Shift value for DMA_CH10ENS */
<> 150:02e0a0aed4ec 602 #define _DMA_CHENS_CH10ENS_MASK 0x400UL /**< Bit mask for DMA_CH10ENS */
<> 150:02e0a0aed4ec 603 #define _DMA_CHENS_CH10ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
<> 150:02e0a0aed4ec 604 #define DMA_CHENS_CH10ENS_DEFAULT (_DMA_CHENS_CH10ENS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHENS */
<> 150:02e0a0aed4ec 605 #define DMA_CHENS_CH11ENS (0x1UL << 11) /**< Channel 11 Enable Set */
<> 150:02e0a0aed4ec 606 #define _DMA_CHENS_CH11ENS_SHIFT 11 /**< Shift value for DMA_CH11ENS */
<> 150:02e0a0aed4ec 607 #define _DMA_CHENS_CH11ENS_MASK 0x800UL /**< Bit mask for DMA_CH11ENS */
<> 150:02e0a0aed4ec 608 #define _DMA_CHENS_CH11ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
<> 150:02e0a0aed4ec 609 #define DMA_CHENS_CH11ENS_DEFAULT (_DMA_CHENS_CH11ENS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHENS */
<> 150:02e0a0aed4ec 610
<> 150:02e0a0aed4ec 611 /* Bit fields for DMA CHENC */
<> 150:02e0a0aed4ec 612 #define _DMA_CHENC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHENC */
<> 150:02e0a0aed4ec 613 #define _DMA_CHENC_MASK 0x00000FFFUL /**< Mask for DMA_CHENC */
<> 150:02e0a0aed4ec 614 #define DMA_CHENC_CH0ENC (0x1UL << 0) /**< Channel 0 Enable Clear */
<> 150:02e0a0aed4ec 615 #define _DMA_CHENC_CH0ENC_SHIFT 0 /**< Shift value for DMA_CH0ENC */
<> 150:02e0a0aed4ec 616 #define _DMA_CHENC_CH0ENC_MASK 0x1UL /**< Bit mask for DMA_CH0ENC */
<> 150:02e0a0aed4ec 617 #define _DMA_CHENC_CH0ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
<> 150:02e0a0aed4ec 618 #define DMA_CHENC_CH0ENC_DEFAULT (_DMA_CHENC_CH0ENC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHENC */
<> 150:02e0a0aed4ec 619 #define DMA_CHENC_CH1ENC (0x1UL << 1) /**< Channel 1 Enable Clear */
<> 150:02e0a0aed4ec 620 #define _DMA_CHENC_CH1ENC_SHIFT 1 /**< Shift value for DMA_CH1ENC */
<> 150:02e0a0aed4ec 621 #define _DMA_CHENC_CH1ENC_MASK 0x2UL /**< Bit mask for DMA_CH1ENC */
<> 150:02e0a0aed4ec 622 #define _DMA_CHENC_CH1ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
<> 150:02e0a0aed4ec 623 #define DMA_CHENC_CH1ENC_DEFAULT (_DMA_CHENC_CH1ENC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHENC */
<> 150:02e0a0aed4ec 624 #define DMA_CHENC_CH2ENC (0x1UL << 2) /**< Channel 2 Enable Clear */
<> 150:02e0a0aed4ec 625 #define _DMA_CHENC_CH2ENC_SHIFT 2 /**< Shift value for DMA_CH2ENC */
<> 150:02e0a0aed4ec 626 #define _DMA_CHENC_CH2ENC_MASK 0x4UL /**< Bit mask for DMA_CH2ENC */
<> 150:02e0a0aed4ec 627 #define _DMA_CHENC_CH2ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
<> 150:02e0a0aed4ec 628 #define DMA_CHENC_CH2ENC_DEFAULT (_DMA_CHENC_CH2ENC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHENC */
<> 150:02e0a0aed4ec 629 #define DMA_CHENC_CH3ENC (0x1UL << 3) /**< Channel 3 Enable Clear */
<> 150:02e0a0aed4ec 630 #define _DMA_CHENC_CH3ENC_SHIFT 3 /**< Shift value for DMA_CH3ENC */
<> 150:02e0a0aed4ec 631 #define _DMA_CHENC_CH3ENC_MASK 0x8UL /**< Bit mask for DMA_CH3ENC */
<> 150:02e0a0aed4ec 632 #define _DMA_CHENC_CH3ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
<> 150:02e0a0aed4ec 633 #define DMA_CHENC_CH3ENC_DEFAULT (_DMA_CHENC_CH3ENC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHENC */
<> 150:02e0a0aed4ec 634 #define DMA_CHENC_CH4ENC (0x1UL << 4) /**< Channel 4 Enable Clear */
<> 150:02e0a0aed4ec 635 #define _DMA_CHENC_CH4ENC_SHIFT 4 /**< Shift value for DMA_CH4ENC */
<> 150:02e0a0aed4ec 636 #define _DMA_CHENC_CH4ENC_MASK 0x10UL /**< Bit mask for DMA_CH4ENC */
<> 150:02e0a0aed4ec 637 #define _DMA_CHENC_CH4ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
<> 150:02e0a0aed4ec 638 #define DMA_CHENC_CH4ENC_DEFAULT (_DMA_CHENC_CH4ENC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHENC */
<> 150:02e0a0aed4ec 639 #define DMA_CHENC_CH5ENC (0x1UL << 5) /**< Channel 5 Enable Clear */
<> 150:02e0a0aed4ec 640 #define _DMA_CHENC_CH5ENC_SHIFT 5 /**< Shift value for DMA_CH5ENC */
<> 150:02e0a0aed4ec 641 #define _DMA_CHENC_CH5ENC_MASK 0x20UL /**< Bit mask for DMA_CH5ENC */
<> 150:02e0a0aed4ec 642 #define _DMA_CHENC_CH5ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
<> 150:02e0a0aed4ec 643 #define DMA_CHENC_CH5ENC_DEFAULT (_DMA_CHENC_CH5ENC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHENC */
<> 150:02e0a0aed4ec 644 #define DMA_CHENC_CH6ENC (0x1UL << 6) /**< Channel 6 Enable Clear */
<> 150:02e0a0aed4ec 645 #define _DMA_CHENC_CH6ENC_SHIFT 6 /**< Shift value for DMA_CH6ENC */
<> 150:02e0a0aed4ec 646 #define _DMA_CHENC_CH6ENC_MASK 0x40UL /**< Bit mask for DMA_CH6ENC */
<> 150:02e0a0aed4ec 647 #define _DMA_CHENC_CH6ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
<> 150:02e0a0aed4ec 648 #define DMA_CHENC_CH6ENC_DEFAULT (_DMA_CHENC_CH6ENC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHENC */
<> 150:02e0a0aed4ec 649 #define DMA_CHENC_CH7ENC (0x1UL << 7) /**< Channel 7 Enable Clear */
<> 150:02e0a0aed4ec 650 #define _DMA_CHENC_CH7ENC_SHIFT 7 /**< Shift value for DMA_CH7ENC */
<> 150:02e0a0aed4ec 651 #define _DMA_CHENC_CH7ENC_MASK 0x80UL /**< Bit mask for DMA_CH7ENC */
<> 150:02e0a0aed4ec 652 #define _DMA_CHENC_CH7ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
<> 150:02e0a0aed4ec 653 #define DMA_CHENC_CH7ENC_DEFAULT (_DMA_CHENC_CH7ENC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHENC */
<> 150:02e0a0aed4ec 654 #define DMA_CHENC_CH8ENC (0x1UL << 8) /**< Channel 8 Enable Clear */
<> 150:02e0a0aed4ec 655 #define _DMA_CHENC_CH8ENC_SHIFT 8 /**< Shift value for DMA_CH8ENC */
<> 150:02e0a0aed4ec 656 #define _DMA_CHENC_CH8ENC_MASK 0x100UL /**< Bit mask for DMA_CH8ENC */
<> 150:02e0a0aed4ec 657 #define _DMA_CHENC_CH8ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
<> 150:02e0a0aed4ec 658 #define DMA_CHENC_CH8ENC_DEFAULT (_DMA_CHENC_CH8ENC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHENC */
<> 150:02e0a0aed4ec 659 #define DMA_CHENC_CH9ENC (0x1UL << 9) /**< Channel 9 Enable Clear */
<> 150:02e0a0aed4ec 660 #define _DMA_CHENC_CH9ENC_SHIFT 9 /**< Shift value for DMA_CH9ENC */
<> 150:02e0a0aed4ec 661 #define _DMA_CHENC_CH9ENC_MASK 0x200UL /**< Bit mask for DMA_CH9ENC */
<> 150:02e0a0aed4ec 662 #define _DMA_CHENC_CH9ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
<> 150:02e0a0aed4ec 663 #define DMA_CHENC_CH9ENC_DEFAULT (_DMA_CHENC_CH9ENC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHENC */
<> 150:02e0a0aed4ec 664 #define DMA_CHENC_CH10ENC (0x1UL << 10) /**< Channel 10 Enable Clear */
<> 150:02e0a0aed4ec 665 #define _DMA_CHENC_CH10ENC_SHIFT 10 /**< Shift value for DMA_CH10ENC */
<> 150:02e0a0aed4ec 666 #define _DMA_CHENC_CH10ENC_MASK 0x400UL /**< Bit mask for DMA_CH10ENC */
<> 150:02e0a0aed4ec 667 #define _DMA_CHENC_CH10ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
<> 150:02e0a0aed4ec 668 #define DMA_CHENC_CH10ENC_DEFAULT (_DMA_CHENC_CH10ENC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHENC */
<> 150:02e0a0aed4ec 669 #define DMA_CHENC_CH11ENC (0x1UL << 11) /**< Channel 11 Enable Clear */
<> 150:02e0a0aed4ec 670 #define _DMA_CHENC_CH11ENC_SHIFT 11 /**< Shift value for DMA_CH11ENC */
<> 150:02e0a0aed4ec 671 #define _DMA_CHENC_CH11ENC_MASK 0x800UL /**< Bit mask for DMA_CH11ENC */
<> 150:02e0a0aed4ec 672 #define _DMA_CHENC_CH11ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
<> 150:02e0a0aed4ec 673 #define DMA_CHENC_CH11ENC_DEFAULT (_DMA_CHENC_CH11ENC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHENC */
<> 150:02e0a0aed4ec 674
<> 150:02e0a0aed4ec 675 /* Bit fields for DMA CHALTS */
<> 150:02e0a0aed4ec 676 #define _DMA_CHALTS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHALTS */
<> 150:02e0a0aed4ec 677 #define _DMA_CHALTS_MASK 0x00000FFFUL /**< Mask for DMA_CHALTS */
<> 150:02e0a0aed4ec 678 #define DMA_CHALTS_CH0ALTS (0x1UL << 0) /**< Channel 0 Alternate Structure Set */
<> 150:02e0a0aed4ec 679 #define _DMA_CHALTS_CH0ALTS_SHIFT 0 /**< Shift value for DMA_CH0ALTS */
<> 150:02e0a0aed4ec 680 #define _DMA_CHALTS_CH0ALTS_MASK 0x1UL /**< Bit mask for DMA_CH0ALTS */
<> 150:02e0a0aed4ec 681 #define _DMA_CHALTS_CH0ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
<> 150:02e0a0aed4ec 682 #define DMA_CHALTS_CH0ALTS_DEFAULT (_DMA_CHALTS_CH0ALTS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHALTS */
<> 150:02e0a0aed4ec 683 #define DMA_CHALTS_CH1ALTS (0x1UL << 1) /**< Channel 1 Alternate Structure Set */
<> 150:02e0a0aed4ec 684 #define _DMA_CHALTS_CH1ALTS_SHIFT 1 /**< Shift value for DMA_CH1ALTS */
<> 150:02e0a0aed4ec 685 #define _DMA_CHALTS_CH1ALTS_MASK 0x2UL /**< Bit mask for DMA_CH1ALTS */
<> 150:02e0a0aed4ec 686 #define _DMA_CHALTS_CH1ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
<> 150:02e0a0aed4ec 687 #define DMA_CHALTS_CH1ALTS_DEFAULT (_DMA_CHALTS_CH1ALTS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHALTS */
<> 150:02e0a0aed4ec 688 #define DMA_CHALTS_CH2ALTS (0x1UL << 2) /**< Channel 2 Alternate Structure Set */
<> 150:02e0a0aed4ec 689 #define _DMA_CHALTS_CH2ALTS_SHIFT 2 /**< Shift value for DMA_CH2ALTS */
<> 150:02e0a0aed4ec 690 #define _DMA_CHALTS_CH2ALTS_MASK 0x4UL /**< Bit mask for DMA_CH2ALTS */
<> 150:02e0a0aed4ec 691 #define _DMA_CHALTS_CH2ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
<> 150:02e0a0aed4ec 692 #define DMA_CHALTS_CH2ALTS_DEFAULT (_DMA_CHALTS_CH2ALTS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHALTS */
<> 150:02e0a0aed4ec 693 #define DMA_CHALTS_CH3ALTS (0x1UL << 3) /**< Channel 3 Alternate Structure Set */
<> 150:02e0a0aed4ec 694 #define _DMA_CHALTS_CH3ALTS_SHIFT 3 /**< Shift value for DMA_CH3ALTS */
<> 150:02e0a0aed4ec 695 #define _DMA_CHALTS_CH3ALTS_MASK 0x8UL /**< Bit mask for DMA_CH3ALTS */
<> 150:02e0a0aed4ec 696 #define _DMA_CHALTS_CH3ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
<> 150:02e0a0aed4ec 697 #define DMA_CHALTS_CH3ALTS_DEFAULT (_DMA_CHALTS_CH3ALTS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHALTS */
<> 150:02e0a0aed4ec 698 #define DMA_CHALTS_CH4ALTS (0x1UL << 4) /**< Channel 4 Alternate Structure Set */
<> 150:02e0a0aed4ec 699 #define _DMA_CHALTS_CH4ALTS_SHIFT 4 /**< Shift value for DMA_CH4ALTS */
<> 150:02e0a0aed4ec 700 #define _DMA_CHALTS_CH4ALTS_MASK 0x10UL /**< Bit mask for DMA_CH4ALTS */
<> 150:02e0a0aed4ec 701 #define _DMA_CHALTS_CH4ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
<> 150:02e0a0aed4ec 702 #define DMA_CHALTS_CH4ALTS_DEFAULT (_DMA_CHALTS_CH4ALTS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHALTS */
<> 150:02e0a0aed4ec 703 #define DMA_CHALTS_CH5ALTS (0x1UL << 5) /**< Channel 5 Alternate Structure Set */
<> 150:02e0a0aed4ec 704 #define _DMA_CHALTS_CH5ALTS_SHIFT 5 /**< Shift value for DMA_CH5ALTS */
<> 150:02e0a0aed4ec 705 #define _DMA_CHALTS_CH5ALTS_MASK 0x20UL /**< Bit mask for DMA_CH5ALTS */
<> 150:02e0a0aed4ec 706 #define _DMA_CHALTS_CH5ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
<> 150:02e0a0aed4ec 707 #define DMA_CHALTS_CH5ALTS_DEFAULT (_DMA_CHALTS_CH5ALTS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHALTS */
<> 150:02e0a0aed4ec 708 #define DMA_CHALTS_CH6ALTS (0x1UL << 6) /**< Channel 6 Alternate Structure Set */
<> 150:02e0a0aed4ec 709 #define _DMA_CHALTS_CH6ALTS_SHIFT 6 /**< Shift value for DMA_CH6ALTS */
<> 150:02e0a0aed4ec 710 #define _DMA_CHALTS_CH6ALTS_MASK 0x40UL /**< Bit mask for DMA_CH6ALTS */
<> 150:02e0a0aed4ec 711 #define _DMA_CHALTS_CH6ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
<> 150:02e0a0aed4ec 712 #define DMA_CHALTS_CH6ALTS_DEFAULT (_DMA_CHALTS_CH6ALTS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHALTS */
<> 150:02e0a0aed4ec 713 #define DMA_CHALTS_CH7ALTS (0x1UL << 7) /**< Channel 7 Alternate Structure Set */
<> 150:02e0a0aed4ec 714 #define _DMA_CHALTS_CH7ALTS_SHIFT 7 /**< Shift value for DMA_CH7ALTS */
<> 150:02e0a0aed4ec 715 #define _DMA_CHALTS_CH7ALTS_MASK 0x80UL /**< Bit mask for DMA_CH7ALTS */
<> 150:02e0a0aed4ec 716 #define _DMA_CHALTS_CH7ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
<> 150:02e0a0aed4ec 717 #define DMA_CHALTS_CH7ALTS_DEFAULT (_DMA_CHALTS_CH7ALTS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHALTS */
<> 150:02e0a0aed4ec 718 #define DMA_CHALTS_CH8ALTS (0x1UL << 8) /**< Channel 8 Alternate Structure Set */
<> 150:02e0a0aed4ec 719 #define _DMA_CHALTS_CH8ALTS_SHIFT 8 /**< Shift value for DMA_CH8ALTS */
<> 150:02e0a0aed4ec 720 #define _DMA_CHALTS_CH8ALTS_MASK 0x100UL /**< Bit mask for DMA_CH8ALTS */
<> 150:02e0a0aed4ec 721 #define _DMA_CHALTS_CH8ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
<> 150:02e0a0aed4ec 722 #define DMA_CHALTS_CH8ALTS_DEFAULT (_DMA_CHALTS_CH8ALTS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHALTS */
<> 150:02e0a0aed4ec 723 #define DMA_CHALTS_CH9ALTS (0x1UL << 9) /**< Channel 9 Alternate Structure Set */
<> 150:02e0a0aed4ec 724 #define _DMA_CHALTS_CH9ALTS_SHIFT 9 /**< Shift value for DMA_CH9ALTS */
<> 150:02e0a0aed4ec 725 #define _DMA_CHALTS_CH9ALTS_MASK 0x200UL /**< Bit mask for DMA_CH9ALTS */
<> 150:02e0a0aed4ec 726 #define _DMA_CHALTS_CH9ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
<> 150:02e0a0aed4ec 727 #define DMA_CHALTS_CH9ALTS_DEFAULT (_DMA_CHALTS_CH9ALTS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHALTS */
<> 150:02e0a0aed4ec 728 #define DMA_CHALTS_CH10ALTS (0x1UL << 10) /**< Channel 10 Alternate Structure Set */
<> 150:02e0a0aed4ec 729 #define _DMA_CHALTS_CH10ALTS_SHIFT 10 /**< Shift value for DMA_CH10ALTS */
<> 150:02e0a0aed4ec 730 #define _DMA_CHALTS_CH10ALTS_MASK 0x400UL /**< Bit mask for DMA_CH10ALTS */
<> 150:02e0a0aed4ec 731 #define _DMA_CHALTS_CH10ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
<> 150:02e0a0aed4ec 732 #define DMA_CHALTS_CH10ALTS_DEFAULT (_DMA_CHALTS_CH10ALTS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHALTS */
<> 150:02e0a0aed4ec 733 #define DMA_CHALTS_CH11ALTS (0x1UL << 11) /**< Channel 11 Alternate Structure Set */
<> 150:02e0a0aed4ec 734 #define _DMA_CHALTS_CH11ALTS_SHIFT 11 /**< Shift value for DMA_CH11ALTS */
<> 150:02e0a0aed4ec 735 #define _DMA_CHALTS_CH11ALTS_MASK 0x800UL /**< Bit mask for DMA_CH11ALTS */
<> 150:02e0a0aed4ec 736 #define _DMA_CHALTS_CH11ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
<> 150:02e0a0aed4ec 737 #define DMA_CHALTS_CH11ALTS_DEFAULT (_DMA_CHALTS_CH11ALTS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHALTS */
<> 150:02e0a0aed4ec 738
<> 150:02e0a0aed4ec 739 /* Bit fields for DMA CHALTC */
<> 150:02e0a0aed4ec 740 #define _DMA_CHALTC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHALTC */
<> 150:02e0a0aed4ec 741 #define _DMA_CHALTC_MASK 0x00000FFFUL /**< Mask for DMA_CHALTC */
<> 150:02e0a0aed4ec 742 #define DMA_CHALTC_CH0ALTC (0x1UL << 0) /**< Channel 0 Alternate Clear */
<> 150:02e0a0aed4ec 743 #define _DMA_CHALTC_CH0ALTC_SHIFT 0 /**< Shift value for DMA_CH0ALTC */
<> 150:02e0a0aed4ec 744 #define _DMA_CHALTC_CH0ALTC_MASK 0x1UL /**< Bit mask for DMA_CH0ALTC */
<> 150:02e0a0aed4ec 745 #define _DMA_CHALTC_CH0ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
<> 150:02e0a0aed4ec 746 #define DMA_CHALTC_CH0ALTC_DEFAULT (_DMA_CHALTC_CH0ALTC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHALTC */
<> 150:02e0a0aed4ec 747 #define DMA_CHALTC_CH1ALTC (0x1UL << 1) /**< Channel 1 Alternate Clear */
<> 150:02e0a0aed4ec 748 #define _DMA_CHALTC_CH1ALTC_SHIFT 1 /**< Shift value for DMA_CH1ALTC */
<> 150:02e0a0aed4ec 749 #define _DMA_CHALTC_CH1ALTC_MASK 0x2UL /**< Bit mask for DMA_CH1ALTC */
<> 150:02e0a0aed4ec 750 #define _DMA_CHALTC_CH1ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
<> 150:02e0a0aed4ec 751 #define DMA_CHALTC_CH1ALTC_DEFAULT (_DMA_CHALTC_CH1ALTC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHALTC */
<> 150:02e0a0aed4ec 752 #define DMA_CHALTC_CH2ALTC (0x1UL << 2) /**< Channel 2 Alternate Clear */
<> 150:02e0a0aed4ec 753 #define _DMA_CHALTC_CH2ALTC_SHIFT 2 /**< Shift value for DMA_CH2ALTC */
<> 150:02e0a0aed4ec 754 #define _DMA_CHALTC_CH2ALTC_MASK 0x4UL /**< Bit mask for DMA_CH2ALTC */
<> 150:02e0a0aed4ec 755 #define _DMA_CHALTC_CH2ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
<> 150:02e0a0aed4ec 756 #define DMA_CHALTC_CH2ALTC_DEFAULT (_DMA_CHALTC_CH2ALTC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHALTC */
<> 150:02e0a0aed4ec 757 #define DMA_CHALTC_CH3ALTC (0x1UL << 3) /**< Channel 3 Alternate Clear */
<> 150:02e0a0aed4ec 758 #define _DMA_CHALTC_CH3ALTC_SHIFT 3 /**< Shift value for DMA_CH3ALTC */
<> 150:02e0a0aed4ec 759 #define _DMA_CHALTC_CH3ALTC_MASK 0x8UL /**< Bit mask for DMA_CH3ALTC */
<> 150:02e0a0aed4ec 760 #define _DMA_CHALTC_CH3ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
<> 150:02e0a0aed4ec 761 #define DMA_CHALTC_CH3ALTC_DEFAULT (_DMA_CHALTC_CH3ALTC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHALTC */
<> 150:02e0a0aed4ec 762 #define DMA_CHALTC_CH4ALTC (0x1UL << 4) /**< Channel 4 Alternate Clear */
<> 150:02e0a0aed4ec 763 #define _DMA_CHALTC_CH4ALTC_SHIFT 4 /**< Shift value for DMA_CH4ALTC */
<> 150:02e0a0aed4ec 764 #define _DMA_CHALTC_CH4ALTC_MASK 0x10UL /**< Bit mask for DMA_CH4ALTC */
<> 150:02e0a0aed4ec 765 #define _DMA_CHALTC_CH4ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
<> 150:02e0a0aed4ec 766 #define DMA_CHALTC_CH4ALTC_DEFAULT (_DMA_CHALTC_CH4ALTC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHALTC */
<> 150:02e0a0aed4ec 767 #define DMA_CHALTC_CH5ALTC (0x1UL << 5) /**< Channel 5 Alternate Clear */
<> 150:02e0a0aed4ec 768 #define _DMA_CHALTC_CH5ALTC_SHIFT 5 /**< Shift value for DMA_CH5ALTC */
<> 150:02e0a0aed4ec 769 #define _DMA_CHALTC_CH5ALTC_MASK 0x20UL /**< Bit mask for DMA_CH5ALTC */
<> 150:02e0a0aed4ec 770 #define _DMA_CHALTC_CH5ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
<> 150:02e0a0aed4ec 771 #define DMA_CHALTC_CH5ALTC_DEFAULT (_DMA_CHALTC_CH5ALTC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHALTC */
<> 150:02e0a0aed4ec 772 #define DMA_CHALTC_CH6ALTC (0x1UL << 6) /**< Channel 6 Alternate Clear */
<> 150:02e0a0aed4ec 773 #define _DMA_CHALTC_CH6ALTC_SHIFT 6 /**< Shift value for DMA_CH6ALTC */
<> 150:02e0a0aed4ec 774 #define _DMA_CHALTC_CH6ALTC_MASK 0x40UL /**< Bit mask for DMA_CH6ALTC */
<> 150:02e0a0aed4ec 775 #define _DMA_CHALTC_CH6ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
<> 150:02e0a0aed4ec 776 #define DMA_CHALTC_CH6ALTC_DEFAULT (_DMA_CHALTC_CH6ALTC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHALTC */
<> 150:02e0a0aed4ec 777 #define DMA_CHALTC_CH7ALTC (0x1UL << 7) /**< Channel 7 Alternate Clear */
<> 150:02e0a0aed4ec 778 #define _DMA_CHALTC_CH7ALTC_SHIFT 7 /**< Shift value for DMA_CH7ALTC */
<> 150:02e0a0aed4ec 779 #define _DMA_CHALTC_CH7ALTC_MASK 0x80UL /**< Bit mask for DMA_CH7ALTC */
<> 150:02e0a0aed4ec 780 #define _DMA_CHALTC_CH7ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
<> 150:02e0a0aed4ec 781 #define DMA_CHALTC_CH7ALTC_DEFAULT (_DMA_CHALTC_CH7ALTC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHALTC */
<> 150:02e0a0aed4ec 782 #define DMA_CHALTC_CH8ALTC (0x1UL << 8) /**< Channel 8 Alternate Clear */
<> 150:02e0a0aed4ec 783 #define _DMA_CHALTC_CH8ALTC_SHIFT 8 /**< Shift value for DMA_CH8ALTC */
<> 150:02e0a0aed4ec 784 #define _DMA_CHALTC_CH8ALTC_MASK 0x100UL /**< Bit mask for DMA_CH8ALTC */
<> 150:02e0a0aed4ec 785 #define _DMA_CHALTC_CH8ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
<> 150:02e0a0aed4ec 786 #define DMA_CHALTC_CH8ALTC_DEFAULT (_DMA_CHALTC_CH8ALTC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHALTC */
<> 150:02e0a0aed4ec 787 #define DMA_CHALTC_CH9ALTC (0x1UL << 9) /**< Channel 9 Alternate Clear */
<> 150:02e0a0aed4ec 788 #define _DMA_CHALTC_CH9ALTC_SHIFT 9 /**< Shift value for DMA_CH9ALTC */
<> 150:02e0a0aed4ec 789 #define _DMA_CHALTC_CH9ALTC_MASK 0x200UL /**< Bit mask for DMA_CH9ALTC */
<> 150:02e0a0aed4ec 790 #define _DMA_CHALTC_CH9ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
<> 150:02e0a0aed4ec 791 #define DMA_CHALTC_CH9ALTC_DEFAULT (_DMA_CHALTC_CH9ALTC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHALTC */
<> 150:02e0a0aed4ec 792 #define DMA_CHALTC_CH10ALTC (0x1UL << 10) /**< Channel 10 Alternate Clear */
<> 150:02e0a0aed4ec 793 #define _DMA_CHALTC_CH10ALTC_SHIFT 10 /**< Shift value for DMA_CH10ALTC */
<> 150:02e0a0aed4ec 794 #define _DMA_CHALTC_CH10ALTC_MASK 0x400UL /**< Bit mask for DMA_CH10ALTC */
<> 150:02e0a0aed4ec 795 #define _DMA_CHALTC_CH10ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
<> 150:02e0a0aed4ec 796 #define DMA_CHALTC_CH10ALTC_DEFAULT (_DMA_CHALTC_CH10ALTC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHALTC */
<> 150:02e0a0aed4ec 797 #define DMA_CHALTC_CH11ALTC (0x1UL << 11) /**< Channel 11 Alternate Clear */
<> 150:02e0a0aed4ec 798 #define _DMA_CHALTC_CH11ALTC_SHIFT 11 /**< Shift value for DMA_CH11ALTC */
<> 150:02e0a0aed4ec 799 #define _DMA_CHALTC_CH11ALTC_MASK 0x800UL /**< Bit mask for DMA_CH11ALTC */
<> 150:02e0a0aed4ec 800 #define _DMA_CHALTC_CH11ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
<> 150:02e0a0aed4ec 801 #define DMA_CHALTC_CH11ALTC_DEFAULT (_DMA_CHALTC_CH11ALTC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHALTC */
<> 150:02e0a0aed4ec 802
<> 150:02e0a0aed4ec 803 /* Bit fields for DMA CHPRIS */
<> 150:02e0a0aed4ec 804 #define _DMA_CHPRIS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHPRIS */
<> 150:02e0a0aed4ec 805 #define _DMA_CHPRIS_MASK 0x00000FFFUL /**< Mask for DMA_CHPRIS */
<> 150:02e0a0aed4ec 806 #define DMA_CHPRIS_CH0PRIS (0x1UL << 0) /**< Channel 0 High Priority Set */
<> 150:02e0a0aed4ec 807 #define _DMA_CHPRIS_CH0PRIS_SHIFT 0 /**< Shift value for DMA_CH0PRIS */
<> 150:02e0a0aed4ec 808 #define _DMA_CHPRIS_CH0PRIS_MASK 0x1UL /**< Bit mask for DMA_CH0PRIS */
<> 150:02e0a0aed4ec 809 #define _DMA_CHPRIS_CH0PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
<> 150:02e0a0aed4ec 810 #define DMA_CHPRIS_CH0PRIS_DEFAULT (_DMA_CHPRIS_CH0PRIS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHPRIS */
<> 150:02e0a0aed4ec 811 #define DMA_CHPRIS_CH1PRIS (0x1UL << 1) /**< Channel 1 High Priority Set */
<> 150:02e0a0aed4ec 812 #define _DMA_CHPRIS_CH1PRIS_SHIFT 1 /**< Shift value for DMA_CH1PRIS */
<> 150:02e0a0aed4ec 813 #define _DMA_CHPRIS_CH1PRIS_MASK 0x2UL /**< Bit mask for DMA_CH1PRIS */
<> 150:02e0a0aed4ec 814 #define _DMA_CHPRIS_CH1PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
<> 150:02e0a0aed4ec 815 #define DMA_CHPRIS_CH1PRIS_DEFAULT (_DMA_CHPRIS_CH1PRIS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHPRIS */
<> 150:02e0a0aed4ec 816 #define DMA_CHPRIS_CH2PRIS (0x1UL << 2) /**< Channel 2 High Priority Set */
<> 150:02e0a0aed4ec 817 #define _DMA_CHPRIS_CH2PRIS_SHIFT 2 /**< Shift value for DMA_CH2PRIS */
<> 150:02e0a0aed4ec 818 #define _DMA_CHPRIS_CH2PRIS_MASK 0x4UL /**< Bit mask for DMA_CH2PRIS */
<> 150:02e0a0aed4ec 819 #define _DMA_CHPRIS_CH2PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
<> 150:02e0a0aed4ec 820 #define DMA_CHPRIS_CH2PRIS_DEFAULT (_DMA_CHPRIS_CH2PRIS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHPRIS */
<> 150:02e0a0aed4ec 821 #define DMA_CHPRIS_CH3PRIS (0x1UL << 3) /**< Channel 3 High Priority Set */
<> 150:02e0a0aed4ec 822 #define _DMA_CHPRIS_CH3PRIS_SHIFT 3 /**< Shift value for DMA_CH3PRIS */
<> 150:02e0a0aed4ec 823 #define _DMA_CHPRIS_CH3PRIS_MASK 0x8UL /**< Bit mask for DMA_CH3PRIS */
<> 150:02e0a0aed4ec 824 #define _DMA_CHPRIS_CH3PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
<> 150:02e0a0aed4ec 825 #define DMA_CHPRIS_CH3PRIS_DEFAULT (_DMA_CHPRIS_CH3PRIS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHPRIS */
<> 150:02e0a0aed4ec 826 #define DMA_CHPRIS_CH4PRIS (0x1UL << 4) /**< Channel 4 High Priority Set */
<> 150:02e0a0aed4ec 827 #define _DMA_CHPRIS_CH4PRIS_SHIFT 4 /**< Shift value for DMA_CH4PRIS */
<> 150:02e0a0aed4ec 828 #define _DMA_CHPRIS_CH4PRIS_MASK 0x10UL /**< Bit mask for DMA_CH4PRIS */
<> 150:02e0a0aed4ec 829 #define _DMA_CHPRIS_CH4PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
<> 150:02e0a0aed4ec 830 #define DMA_CHPRIS_CH4PRIS_DEFAULT (_DMA_CHPRIS_CH4PRIS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHPRIS */
<> 150:02e0a0aed4ec 831 #define DMA_CHPRIS_CH5PRIS (0x1UL << 5) /**< Channel 5 High Priority Set */
<> 150:02e0a0aed4ec 832 #define _DMA_CHPRIS_CH5PRIS_SHIFT 5 /**< Shift value for DMA_CH5PRIS */
<> 150:02e0a0aed4ec 833 #define _DMA_CHPRIS_CH5PRIS_MASK 0x20UL /**< Bit mask for DMA_CH5PRIS */
<> 150:02e0a0aed4ec 834 #define _DMA_CHPRIS_CH5PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
<> 150:02e0a0aed4ec 835 #define DMA_CHPRIS_CH5PRIS_DEFAULT (_DMA_CHPRIS_CH5PRIS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHPRIS */
<> 150:02e0a0aed4ec 836 #define DMA_CHPRIS_CH6PRIS (0x1UL << 6) /**< Channel 6 High Priority Set */
<> 150:02e0a0aed4ec 837 #define _DMA_CHPRIS_CH6PRIS_SHIFT 6 /**< Shift value for DMA_CH6PRIS */
<> 150:02e0a0aed4ec 838 #define _DMA_CHPRIS_CH6PRIS_MASK 0x40UL /**< Bit mask for DMA_CH6PRIS */
<> 150:02e0a0aed4ec 839 #define _DMA_CHPRIS_CH6PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
<> 150:02e0a0aed4ec 840 #define DMA_CHPRIS_CH6PRIS_DEFAULT (_DMA_CHPRIS_CH6PRIS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHPRIS */
<> 150:02e0a0aed4ec 841 #define DMA_CHPRIS_CH7PRIS (0x1UL << 7) /**< Channel 7 High Priority Set */
<> 150:02e0a0aed4ec 842 #define _DMA_CHPRIS_CH7PRIS_SHIFT 7 /**< Shift value for DMA_CH7PRIS */
<> 150:02e0a0aed4ec 843 #define _DMA_CHPRIS_CH7PRIS_MASK 0x80UL /**< Bit mask for DMA_CH7PRIS */
<> 150:02e0a0aed4ec 844 #define _DMA_CHPRIS_CH7PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
<> 150:02e0a0aed4ec 845 #define DMA_CHPRIS_CH7PRIS_DEFAULT (_DMA_CHPRIS_CH7PRIS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHPRIS */
<> 150:02e0a0aed4ec 846 #define DMA_CHPRIS_CH8PRIS (0x1UL << 8) /**< Channel 8 High Priority Set */
<> 150:02e0a0aed4ec 847 #define _DMA_CHPRIS_CH8PRIS_SHIFT 8 /**< Shift value for DMA_CH8PRIS */
<> 150:02e0a0aed4ec 848 #define _DMA_CHPRIS_CH8PRIS_MASK 0x100UL /**< Bit mask for DMA_CH8PRIS */
<> 150:02e0a0aed4ec 849 #define _DMA_CHPRIS_CH8PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
<> 150:02e0a0aed4ec 850 #define DMA_CHPRIS_CH8PRIS_DEFAULT (_DMA_CHPRIS_CH8PRIS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHPRIS */
<> 150:02e0a0aed4ec 851 #define DMA_CHPRIS_CH9PRIS (0x1UL << 9) /**< Channel 9 High Priority Set */
<> 150:02e0a0aed4ec 852 #define _DMA_CHPRIS_CH9PRIS_SHIFT 9 /**< Shift value for DMA_CH9PRIS */
<> 150:02e0a0aed4ec 853 #define _DMA_CHPRIS_CH9PRIS_MASK 0x200UL /**< Bit mask for DMA_CH9PRIS */
<> 150:02e0a0aed4ec 854 #define _DMA_CHPRIS_CH9PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
<> 150:02e0a0aed4ec 855 #define DMA_CHPRIS_CH9PRIS_DEFAULT (_DMA_CHPRIS_CH9PRIS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHPRIS */
<> 150:02e0a0aed4ec 856 #define DMA_CHPRIS_CH10PRIS (0x1UL << 10) /**< Channel 10 High Priority Set */
<> 150:02e0a0aed4ec 857 #define _DMA_CHPRIS_CH10PRIS_SHIFT 10 /**< Shift value for DMA_CH10PRIS */
<> 150:02e0a0aed4ec 858 #define _DMA_CHPRIS_CH10PRIS_MASK 0x400UL /**< Bit mask for DMA_CH10PRIS */
<> 150:02e0a0aed4ec 859 #define _DMA_CHPRIS_CH10PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
<> 150:02e0a0aed4ec 860 #define DMA_CHPRIS_CH10PRIS_DEFAULT (_DMA_CHPRIS_CH10PRIS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHPRIS */
<> 150:02e0a0aed4ec 861 #define DMA_CHPRIS_CH11PRIS (0x1UL << 11) /**< Channel 11 High Priority Set */
<> 150:02e0a0aed4ec 862 #define _DMA_CHPRIS_CH11PRIS_SHIFT 11 /**< Shift value for DMA_CH11PRIS */
<> 150:02e0a0aed4ec 863 #define _DMA_CHPRIS_CH11PRIS_MASK 0x800UL /**< Bit mask for DMA_CH11PRIS */
<> 150:02e0a0aed4ec 864 #define _DMA_CHPRIS_CH11PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
<> 150:02e0a0aed4ec 865 #define DMA_CHPRIS_CH11PRIS_DEFAULT (_DMA_CHPRIS_CH11PRIS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHPRIS */
<> 150:02e0a0aed4ec 866
<> 150:02e0a0aed4ec 867 /* Bit fields for DMA CHPRIC */
<> 150:02e0a0aed4ec 868 #define _DMA_CHPRIC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHPRIC */
<> 150:02e0a0aed4ec 869 #define _DMA_CHPRIC_MASK 0x00000FFFUL /**< Mask for DMA_CHPRIC */
<> 150:02e0a0aed4ec 870 #define DMA_CHPRIC_CH0PRIC (0x1UL << 0) /**< Channel 0 High Priority Clear */
<> 150:02e0a0aed4ec 871 #define _DMA_CHPRIC_CH0PRIC_SHIFT 0 /**< Shift value for DMA_CH0PRIC */
<> 150:02e0a0aed4ec 872 #define _DMA_CHPRIC_CH0PRIC_MASK 0x1UL /**< Bit mask for DMA_CH0PRIC */
<> 150:02e0a0aed4ec 873 #define _DMA_CHPRIC_CH0PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
<> 150:02e0a0aed4ec 874 #define DMA_CHPRIC_CH0PRIC_DEFAULT (_DMA_CHPRIC_CH0PRIC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHPRIC */
<> 150:02e0a0aed4ec 875 #define DMA_CHPRIC_CH1PRIC (0x1UL << 1) /**< Channel 1 High Priority Clear */
<> 150:02e0a0aed4ec 876 #define _DMA_CHPRIC_CH1PRIC_SHIFT 1 /**< Shift value for DMA_CH1PRIC */
<> 150:02e0a0aed4ec 877 #define _DMA_CHPRIC_CH1PRIC_MASK 0x2UL /**< Bit mask for DMA_CH1PRIC */
<> 150:02e0a0aed4ec 878 #define _DMA_CHPRIC_CH1PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
<> 150:02e0a0aed4ec 879 #define DMA_CHPRIC_CH1PRIC_DEFAULT (_DMA_CHPRIC_CH1PRIC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHPRIC */
<> 150:02e0a0aed4ec 880 #define DMA_CHPRIC_CH2PRIC (0x1UL << 2) /**< Channel 2 High Priority Clear */
<> 150:02e0a0aed4ec 881 #define _DMA_CHPRIC_CH2PRIC_SHIFT 2 /**< Shift value for DMA_CH2PRIC */
<> 150:02e0a0aed4ec 882 #define _DMA_CHPRIC_CH2PRIC_MASK 0x4UL /**< Bit mask for DMA_CH2PRIC */
<> 150:02e0a0aed4ec 883 #define _DMA_CHPRIC_CH2PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
<> 150:02e0a0aed4ec 884 #define DMA_CHPRIC_CH2PRIC_DEFAULT (_DMA_CHPRIC_CH2PRIC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHPRIC */
<> 150:02e0a0aed4ec 885 #define DMA_CHPRIC_CH3PRIC (0x1UL << 3) /**< Channel 3 High Priority Clear */
<> 150:02e0a0aed4ec 886 #define _DMA_CHPRIC_CH3PRIC_SHIFT 3 /**< Shift value for DMA_CH3PRIC */
<> 150:02e0a0aed4ec 887 #define _DMA_CHPRIC_CH3PRIC_MASK 0x8UL /**< Bit mask for DMA_CH3PRIC */
<> 150:02e0a0aed4ec 888 #define _DMA_CHPRIC_CH3PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
<> 150:02e0a0aed4ec 889 #define DMA_CHPRIC_CH3PRIC_DEFAULT (_DMA_CHPRIC_CH3PRIC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHPRIC */
<> 150:02e0a0aed4ec 890 #define DMA_CHPRIC_CH4PRIC (0x1UL << 4) /**< Channel 4 High Priority Clear */
<> 150:02e0a0aed4ec 891 #define _DMA_CHPRIC_CH4PRIC_SHIFT 4 /**< Shift value for DMA_CH4PRIC */
<> 150:02e0a0aed4ec 892 #define _DMA_CHPRIC_CH4PRIC_MASK 0x10UL /**< Bit mask for DMA_CH4PRIC */
<> 150:02e0a0aed4ec 893 #define _DMA_CHPRIC_CH4PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
<> 150:02e0a0aed4ec 894 #define DMA_CHPRIC_CH4PRIC_DEFAULT (_DMA_CHPRIC_CH4PRIC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHPRIC */
<> 150:02e0a0aed4ec 895 #define DMA_CHPRIC_CH5PRIC (0x1UL << 5) /**< Channel 5 High Priority Clear */
<> 150:02e0a0aed4ec 896 #define _DMA_CHPRIC_CH5PRIC_SHIFT 5 /**< Shift value for DMA_CH5PRIC */
<> 150:02e0a0aed4ec 897 #define _DMA_CHPRIC_CH5PRIC_MASK 0x20UL /**< Bit mask for DMA_CH5PRIC */
<> 150:02e0a0aed4ec 898 #define _DMA_CHPRIC_CH5PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
<> 150:02e0a0aed4ec 899 #define DMA_CHPRIC_CH5PRIC_DEFAULT (_DMA_CHPRIC_CH5PRIC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHPRIC */
<> 150:02e0a0aed4ec 900 #define DMA_CHPRIC_CH6PRIC (0x1UL << 6) /**< Channel 6 High Priority Clear */
<> 150:02e0a0aed4ec 901 #define _DMA_CHPRIC_CH6PRIC_SHIFT 6 /**< Shift value for DMA_CH6PRIC */
<> 150:02e0a0aed4ec 902 #define _DMA_CHPRIC_CH6PRIC_MASK 0x40UL /**< Bit mask for DMA_CH6PRIC */
<> 150:02e0a0aed4ec 903 #define _DMA_CHPRIC_CH6PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
<> 150:02e0a0aed4ec 904 #define DMA_CHPRIC_CH6PRIC_DEFAULT (_DMA_CHPRIC_CH6PRIC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHPRIC */
<> 150:02e0a0aed4ec 905 #define DMA_CHPRIC_CH7PRIC (0x1UL << 7) /**< Channel 7 High Priority Clear */
<> 150:02e0a0aed4ec 906 #define _DMA_CHPRIC_CH7PRIC_SHIFT 7 /**< Shift value for DMA_CH7PRIC */
<> 150:02e0a0aed4ec 907 #define _DMA_CHPRIC_CH7PRIC_MASK 0x80UL /**< Bit mask for DMA_CH7PRIC */
<> 150:02e0a0aed4ec 908 #define _DMA_CHPRIC_CH7PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
<> 150:02e0a0aed4ec 909 #define DMA_CHPRIC_CH7PRIC_DEFAULT (_DMA_CHPRIC_CH7PRIC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHPRIC */
<> 150:02e0a0aed4ec 910 #define DMA_CHPRIC_CH8PRIC (0x1UL << 8) /**< Channel 8 High Priority Clear */
<> 150:02e0a0aed4ec 911 #define _DMA_CHPRIC_CH8PRIC_SHIFT 8 /**< Shift value for DMA_CH8PRIC */
<> 150:02e0a0aed4ec 912 #define _DMA_CHPRIC_CH8PRIC_MASK 0x100UL /**< Bit mask for DMA_CH8PRIC */
<> 150:02e0a0aed4ec 913 #define _DMA_CHPRIC_CH8PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
<> 150:02e0a0aed4ec 914 #define DMA_CHPRIC_CH8PRIC_DEFAULT (_DMA_CHPRIC_CH8PRIC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHPRIC */
<> 150:02e0a0aed4ec 915 #define DMA_CHPRIC_CH9PRIC (0x1UL << 9) /**< Channel 9 High Priority Clear */
<> 150:02e0a0aed4ec 916 #define _DMA_CHPRIC_CH9PRIC_SHIFT 9 /**< Shift value for DMA_CH9PRIC */
<> 150:02e0a0aed4ec 917 #define _DMA_CHPRIC_CH9PRIC_MASK 0x200UL /**< Bit mask for DMA_CH9PRIC */
<> 150:02e0a0aed4ec 918 #define _DMA_CHPRIC_CH9PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
<> 150:02e0a0aed4ec 919 #define DMA_CHPRIC_CH9PRIC_DEFAULT (_DMA_CHPRIC_CH9PRIC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHPRIC */
<> 150:02e0a0aed4ec 920 #define DMA_CHPRIC_CH10PRIC (0x1UL << 10) /**< Channel 10 High Priority Clear */
<> 150:02e0a0aed4ec 921 #define _DMA_CHPRIC_CH10PRIC_SHIFT 10 /**< Shift value for DMA_CH10PRIC */
<> 150:02e0a0aed4ec 922 #define _DMA_CHPRIC_CH10PRIC_MASK 0x400UL /**< Bit mask for DMA_CH10PRIC */
<> 150:02e0a0aed4ec 923 #define _DMA_CHPRIC_CH10PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
<> 150:02e0a0aed4ec 924 #define DMA_CHPRIC_CH10PRIC_DEFAULT (_DMA_CHPRIC_CH10PRIC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHPRIC */
<> 150:02e0a0aed4ec 925 #define DMA_CHPRIC_CH11PRIC (0x1UL << 11) /**< Channel 11 High Priority Clear */
<> 150:02e0a0aed4ec 926 #define _DMA_CHPRIC_CH11PRIC_SHIFT 11 /**< Shift value for DMA_CH11PRIC */
<> 150:02e0a0aed4ec 927 #define _DMA_CHPRIC_CH11PRIC_MASK 0x800UL /**< Bit mask for DMA_CH11PRIC */
<> 150:02e0a0aed4ec 928 #define _DMA_CHPRIC_CH11PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
<> 150:02e0a0aed4ec 929 #define DMA_CHPRIC_CH11PRIC_DEFAULT (_DMA_CHPRIC_CH11PRIC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHPRIC */
<> 150:02e0a0aed4ec 930
<> 150:02e0a0aed4ec 931 /* Bit fields for DMA ERRORC */
<> 150:02e0a0aed4ec 932 #define _DMA_ERRORC_RESETVALUE 0x00000000UL /**< Default value for DMA_ERRORC */
<> 150:02e0a0aed4ec 933 #define _DMA_ERRORC_MASK 0x00000001UL /**< Mask for DMA_ERRORC */
<> 150:02e0a0aed4ec 934 #define DMA_ERRORC_ERRORC (0x1UL << 0) /**< Bus Error Clear */
<> 150:02e0a0aed4ec 935 #define _DMA_ERRORC_ERRORC_SHIFT 0 /**< Shift value for DMA_ERRORC */
<> 150:02e0a0aed4ec 936 #define _DMA_ERRORC_ERRORC_MASK 0x1UL /**< Bit mask for DMA_ERRORC */
<> 150:02e0a0aed4ec 937 #define _DMA_ERRORC_ERRORC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_ERRORC */
<> 150:02e0a0aed4ec 938 #define DMA_ERRORC_ERRORC_DEFAULT (_DMA_ERRORC_ERRORC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_ERRORC */
<> 150:02e0a0aed4ec 939
<> 150:02e0a0aed4ec 940 /* Bit fields for DMA CHREQSTATUS */
<> 150:02e0a0aed4ec 941 #define _DMA_CHREQSTATUS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQSTATUS */
<> 150:02e0a0aed4ec 942 #define _DMA_CHREQSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHREQSTATUS */
<> 150:02e0a0aed4ec 943 #define DMA_CHREQSTATUS_CH0REQSTATUS (0x1UL << 0) /**< Channel 0 Request Status */
<> 150:02e0a0aed4ec 944 #define _DMA_CHREQSTATUS_CH0REQSTATUS_SHIFT 0 /**< Shift value for DMA_CH0REQSTATUS */
<> 150:02e0a0aed4ec 945 #define _DMA_CHREQSTATUS_CH0REQSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0REQSTATUS */
<> 150:02e0a0aed4ec 946 #define _DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
<> 150:02e0a0aed4ec 947 #define DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
<> 150:02e0a0aed4ec 948 #define DMA_CHREQSTATUS_CH1REQSTATUS (0x1UL << 1) /**< Channel 1 Request Status */
<> 150:02e0a0aed4ec 949 #define _DMA_CHREQSTATUS_CH1REQSTATUS_SHIFT 1 /**< Shift value for DMA_CH1REQSTATUS */
<> 150:02e0a0aed4ec 950 #define _DMA_CHREQSTATUS_CH1REQSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1REQSTATUS */
<> 150:02e0a0aed4ec 951 #define _DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
<> 150:02e0a0aed4ec 952 #define DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
<> 150:02e0a0aed4ec 953 #define DMA_CHREQSTATUS_CH2REQSTATUS (0x1UL << 2) /**< Channel 2 Request Status */
<> 150:02e0a0aed4ec 954 #define _DMA_CHREQSTATUS_CH2REQSTATUS_SHIFT 2 /**< Shift value for DMA_CH2REQSTATUS */
<> 150:02e0a0aed4ec 955 #define _DMA_CHREQSTATUS_CH2REQSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2REQSTATUS */
<> 150:02e0a0aed4ec 956 #define _DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
<> 150:02e0a0aed4ec 957 #define DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
<> 150:02e0a0aed4ec 958 #define DMA_CHREQSTATUS_CH3REQSTATUS (0x1UL << 3) /**< Channel 3 Request Status */
<> 150:02e0a0aed4ec 959 #define _DMA_CHREQSTATUS_CH3REQSTATUS_SHIFT 3 /**< Shift value for DMA_CH3REQSTATUS */
<> 150:02e0a0aed4ec 960 #define _DMA_CHREQSTATUS_CH3REQSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3REQSTATUS */
<> 150:02e0a0aed4ec 961 #define _DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
<> 150:02e0a0aed4ec 962 #define DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
<> 150:02e0a0aed4ec 963 #define DMA_CHREQSTATUS_CH4REQSTATUS (0x1UL << 4) /**< Channel 4 Request Status */
<> 150:02e0a0aed4ec 964 #define _DMA_CHREQSTATUS_CH4REQSTATUS_SHIFT 4 /**< Shift value for DMA_CH4REQSTATUS */
<> 150:02e0a0aed4ec 965 #define _DMA_CHREQSTATUS_CH4REQSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4REQSTATUS */
<> 150:02e0a0aed4ec 966 #define _DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
<> 150:02e0a0aed4ec 967 #define DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
<> 150:02e0a0aed4ec 968 #define DMA_CHREQSTATUS_CH5REQSTATUS (0x1UL << 5) /**< Channel 5 Request Status */
<> 150:02e0a0aed4ec 969 #define _DMA_CHREQSTATUS_CH5REQSTATUS_SHIFT 5 /**< Shift value for DMA_CH5REQSTATUS */
<> 150:02e0a0aed4ec 970 #define _DMA_CHREQSTATUS_CH5REQSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5REQSTATUS */
<> 150:02e0a0aed4ec 971 #define _DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
<> 150:02e0a0aed4ec 972 #define DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
<> 150:02e0a0aed4ec 973 #define DMA_CHREQSTATUS_CH6REQSTATUS (0x1UL << 6) /**< Channel 6 Request Status */
<> 150:02e0a0aed4ec 974 #define _DMA_CHREQSTATUS_CH6REQSTATUS_SHIFT 6 /**< Shift value for DMA_CH6REQSTATUS */
<> 150:02e0a0aed4ec 975 #define _DMA_CHREQSTATUS_CH6REQSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6REQSTATUS */
<> 150:02e0a0aed4ec 976 #define _DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
<> 150:02e0a0aed4ec 977 #define DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
<> 150:02e0a0aed4ec 978 #define DMA_CHREQSTATUS_CH7REQSTATUS (0x1UL << 7) /**< Channel 7 Request Status */
<> 150:02e0a0aed4ec 979 #define _DMA_CHREQSTATUS_CH7REQSTATUS_SHIFT 7 /**< Shift value for DMA_CH7REQSTATUS */
<> 150:02e0a0aed4ec 980 #define _DMA_CHREQSTATUS_CH7REQSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7REQSTATUS */
<> 150:02e0a0aed4ec 981 #define _DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
<> 150:02e0a0aed4ec 982 #define DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
<> 150:02e0a0aed4ec 983 #define DMA_CHREQSTATUS_CH8REQSTATUS (0x1UL << 8) /**< Channel 8 Request Status */
<> 150:02e0a0aed4ec 984 #define _DMA_CHREQSTATUS_CH8REQSTATUS_SHIFT 8 /**< Shift value for DMA_CH8REQSTATUS */
<> 150:02e0a0aed4ec 985 #define _DMA_CHREQSTATUS_CH8REQSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8REQSTATUS */
<> 150:02e0a0aed4ec 986 #define _DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
<> 150:02e0a0aed4ec 987 #define DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
<> 150:02e0a0aed4ec 988 #define DMA_CHREQSTATUS_CH9REQSTATUS (0x1UL << 9) /**< Channel 9 Request Status */
<> 150:02e0a0aed4ec 989 #define _DMA_CHREQSTATUS_CH9REQSTATUS_SHIFT 9 /**< Shift value for DMA_CH9REQSTATUS */
<> 150:02e0a0aed4ec 990 #define _DMA_CHREQSTATUS_CH9REQSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9REQSTATUS */
<> 150:02e0a0aed4ec 991 #define _DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
<> 150:02e0a0aed4ec 992 #define DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
<> 150:02e0a0aed4ec 993 #define DMA_CHREQSTATUS_CH10REQSTATUS (0x1UL << 10) /**< Channel 10 Request Status */
<> 150:02e0a0aed4ec 994 #define _DMA_CHREQSTATUS_CH10REQSTATUS_SHIFT 10 /**< Shift value for DMA_CH10REQSTATUS */
<> 150:02e0a0aed4ec 995 #define _DMA_CHREQSTATUS_CH10REQSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10REQSTATUS */
<> 150:02e0a0aed4ec 996 #define _DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
<> 150:02e0a0aed4ec 997 #define DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
<> 150:02e0a0aed4ec 998 #define DMA_CHREQSTATUS_CH11REQSTATUS (0x1UL << 11) /**< Channel 11 Request Status */
<> 150:02e0a0aed4ec 999 #define _DMA_CHREQSTATUS_CH11REQSTATUS_SHIFT 11 /**< Shift value for DMA_CH11REQSTATUS */
<> 150:02e0a0aed4ec 1000 #define _DMA_CHREQSTATUS_CH11REQSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11REQSTATUS */
<> 150:02e0a0aed4ec 1001 #define _DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
<> 150:02e0a0aed4ec 1002 #define DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
<> 150:02e0a0aed4ec 1003
<> 150:02e0a0aed4ec 1004 /* Bit fields for DMA CHSREQSTATUS */
<> 150:02e0a0aed4ec 1005 #define _DMA_CHSREQSTATUS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHSREQSTATUS */
<> 150:02e0a0aed4ec 1006 #define _DMA_CHSREQSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHSREQSTATUS */
<> 150:02e0a0aed4ec 1007 #define DMA_CHSREQSTATUS_CH0SREQSTATUS (0x1UL << 0) /**< Channel 0 Single Request Status */
<> 150:02e0a0aed4ec 1008 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_SHIFT 0 /**< Shift value for DMA_CH0SREQSTATUS */
<> 150:02e0a0aed4ec 1009 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0SREQSTATUS */
<> 150:02e0a0aed4ec 1010 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
<> 150:02e0a0aed4ec 1011 #define DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
<> 150:02e0a0aed4ec 1012 #define DMA_CHSREQSTATUS_CH1SREQSTATUS (0x1UL << 1) /**< Channel 1 Single Request Status */
<> 150:02e0a0aed4ec 1013 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_SHIFT 1 /**< Shift value for DMA_CH1SREQSTATUS */
<> 150:02e0a0aed4ec 1014 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1SREQSTATUS */
<> 150:02e0a0aed4ec 1015 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
<> 150:02e0a0aed4ec 1016 #define DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
<> 150:02e0a0aed4ec 1017 #define DMA_CHSREQSTATUS_CH2SREQSTATUS (0x1UL << 2) /**< Channel 2 Single Request Status */
<> 150:02e0a0aed4ec 1018 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_SHIFT 2 /**< Shift value for DMA_CH2SREQSTATUS */
<> 150:02e0a0aed4ec 1019 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2SREQSTATUS */
<> 150:02e0a0aed4ec 1020 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
<> 150:02e0a0aed4ec 1021 #define DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
<> 150:02e0a0aed4ec 1022 #define DMA_CHSREQSTATUS_CH3SREQSTATUS (0x1UL << 3) /**< Channel 3 Single Request Status */
<> 150:02e0a0aed4ec 1023 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_SHIFT 3 /**< Shift value for DMA_CH3SREQSTATUS */
<> 150:02e0a0aed4ec 1024 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3SREQSTATUS */
<> 150:02e0a0aed4ec 1025 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
<> 150:02e0a0aed4ec 1026 #define DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
<> 150:02e0a0aed4ec 1027 #define DMA_CHSREQSTATUS_CH4SREQSTATUS (0x1UL << 4) /**< Channel 4 Single Request Status */
<> 150:02e0a0aed4ec 1028 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_SHIFT 4 /**< Shift value for DMA_CH4SREQSTATUS */
<> 150:02e0a0aed4ec 1029 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4SREQSTATUS */
<> 150:02e0a0aed4ec 1030 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
<> 150:02e0a0aed4ec 1031 #define DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
<> 150:02e0a0aed4ec 1032 #define DMA_CHSREQSTATUS_CH5SREQSTATUS (0x1UL << 5) /**< Channel 5 Single Request Status */
<> 150:02e0a0aed4ec 1033 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_SHIFT 5 /**< Shift value for DMA_CH5SREQSTATUS */
<> 150:02e0a0aed4ec 1034 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5SREQSTATUS */
<> 150:02e0a0aed4ec 1035 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
<> 150:02e0a0aed4ec 1036 #define DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
<> 150:02e0a0aed4ec 1037 #define DMA_CHSREQSTATUS_CH6SREQSTATUS (0x1UL << 6) /**< Channel 6 Single Request Status */
<> 150:02e0a0aed4ec 1038 #define _DMA_CHSREQSTATUS_CH6SREQSTATUS_SHIFT 6 /**< Shift value for DMA_CH6SREQSTATUS */
<> 150:02e0a0aed4ec 1039 #define _DMA_CHSREQSTATUS_CH6SREQSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6SREQSTATUS */
<> 150:02e0a0aed4ec 1040 #define _DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
<> 150:02e0a0aed4ec 1041 #define DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
<> 150:02e0a0aed4ec 1042 #define DMA_CHSREQSTATUS_CH7SREQSTATUS (0x1UL << 7) /**< Channel 7 Single Request Status */
<> 150:02e0a0aed4ec 1043 #define _DMA_CHSREQSTATUS_CH7SREQSTATUS_SHIFT 7 /**< Shift value for DMA_CH7SREQSTATUS */
<> 150:02e0a0aed4ec 1044 #define _DMA_CHSREQSTATUS_CH7SREQSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7SREQSTATUS */
<> 150:02e0a0aed4ec 1045 #define _DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
<> 150:02e0a0aed4ec 1046 #define DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
<> 150:02e0a0aed4ec 1047 #define DMA_CHSREQSTATUS_CH8SREQSTATUS (0x1UL << 8) /**< Channel 8 Single Request Status */
<> 150:02e0a0aed4ec 1048 #define _DMA_CHSREQSTATUS_CH8SREQSTATUS_SHIFT 8 /**< Shift value for DMA_CH8SREQSTATUS */
<> 150:02e0a0aed4ec 1049 #define _DMA_CHSREQSTATUS_CH8SREQSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8SREQSTATUS */
<> 150:02e0a0aed4ec 1050 #define _DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
<> 150:02e0a0aed4ec 1051 #define DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
<> 150:02e0a0aed4ec 1052 #define DMA_CHSREQSTATUS_CH9SREQSTATUS (0x1UL << 9) /**< Channel 9 Single Request Status */
<> 150:02e0a0aed4ec 1053 #define _DMA_CHSREQSTATUS_CH9SREQSTATUS_SHIFT 9 /**< Shift value for DMA_CH9SREQSTATUS */
<> 150:02e0a0aed4ec 1054 #define _DMA_CHSREQSTATUS_CH9SREQSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9SREQSTATUS */
<> 150:02e0a0aed4ec 1055 #define _DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
<> 150:02e0a0aed4ec 1056 #define DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
<> 150:02e0a0aed4ec 1057 #define DMA_CHSREQSTATUS_CH10SREQSTATUS (0x1UL << 10) /**< Channel 10 Single Request Status */
<> 150:02e0a0aed4ec 1058 #define _DMA_CHSREQSTATUS_CH10SREQSTATUS_SHIFT 10 /**< Shift value for DMA_CH10SREQSTATUS */
<> 150:02e0a0aed4ec 1059 #define _DMA_CHSREQSTATUS_CH10SREQSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10SREQSTATUS */
<> 150:02e0a0aed4ec 1060 #define _DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
<> 150:02e0a0aed4ec 1061 #define DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
<> 150:02e0a0aed4ec 1062 #define DMA_CHSREQSTATUS_CH11SREQSTATUS (0x1UL << 11) /**< Channel 11 Single Request Status */
<> 150:02e0a0aed4ec 1063 #define _DMA_CHSREQSTATUS_CH11SREQSTATUS_SHIFT 11 /**< Shift value for DMA_CH11SREQSTATUS */
<> 150:02e0a0aed4ec 1064 #define _DMA_CHSREQSTATUS_CH11SREQSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11SREQSTATUS */
<> 150:02e0a0aed4ec 1065 #define _DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
<> 150:02e0a0aed4ec 1066 #define DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
<> 150:02e0a0aed4ec 1067
<> 150:02e0a0aed4ec 1068 /* Bit fields for DMA IF */
<> 150:02e0a0aed4ec 1069 #define _DMA_IF_RESETVALUE 0x00000000UL /**< Default value for DMA_IF */
<> 150:02e0a0aed4ec 1070 #define _DMA_IF_MASK 0x80000FFFUL /**< Mask for DMA_IF */
<> 150:02e0a0aed4ec 1071 #define DMA_IF_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag */
<> 150:02e0a0aed4ec 1072 #define _DMA_IF_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */
<> 150:02e0a0aed4ec 1073 #define _DMA_IF_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */
<> 150:02e0a0aed4ec 1074 #define _DMA_IF_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
<> 150:02e0a0aed4ec 1075 #define DMA_IF_CH0DONE_DEFAULT (_DMA_IF_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IF */
<> 150:02e0a0aed4ec 1076 #define DMA_IF_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag */
<> 150:02e0a0aed4ec 1077 #define _DMA_IF_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */
<> 150:02e0a0aed4ec 1078 #define _DMA_IF_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */
<> 150:02e0a0aed4ec 1079 #define _DMA_IF_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
<> 150:02e0a0aed4ec 1080 #define DMA_IF_CH1DONE_DEFAULT (_DMA_IF_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IF */
<> 150:02e0a0aed4ec 1081 #define DMA_IF_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag */
<> 150:02e0a0aed4ec 1082 #define _DMA_IF_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */
<> 150:02e0a0aed4ec 1083 #define _DMA_IF_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */
<> 150:02e0a0aed4ec 1084 #define _DMA_IF_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
<> 150:02e0a0aed4ec 1085 #define DMA_IF_CH2DONE_DEFAULT (_DMA_IF_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IF */
<> 150:02e0a0aed4ec 1086 #define DMA_IF_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag */
<> 150:02e0a0aed4ec 1087 #define _DMA_IF_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */
<> 150:02e0a0aed4ec 1088 #define _DMA_IF_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */
<> 150:02e0a0aed4ec 1089 #define _DMA_IF_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
<> 150:02e0a0aed4ec 1090 #define DMA_IF_CH3DONE_DEFAULT (_DMA_IF_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IF */
<> 150:02e0a0aed4ec 1091 #define DMA_IF_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag */
<> 150:02e0a0aed4ec 1092 #define _DMA_IF_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */
<> 150:02e0a0aed4ec 1093 #define _DMA_IF_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */
<> 150:02e0a0aed4ec 1094 #define _DMA_IF_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
<> 150:02e0a0aed4ec 1095 #define DMA_IF_CH4DONE_DEFAULT (_DMA_IF_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IF */
<> 150:02e0a0aed4ec 1096 #define DMA_IF_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag */
<> 150:02e0a0aed4ec 1097 #define _DMA_IF_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */
<> 150:02e0a0aed4ec 1098 #define _DMA_IF_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */
<> 150:02e0a0aed4ec 1099 #define _DMA_IF_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
<> 150:02e0a0aed4ec 1100 #define DMA_IF_CH5DONE_DEFAULT (_DMA_IF_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IF */
<> 150:02e0a0aed4ec 1101 #define DMA_IF_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag */
<> 150:02e0a0aed4ec 1102 #define _DMA_IF_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */
<> 150:02e0a0aed4ec 1103 #define _DMA_IF_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */
<> 150:02e0a0aed4ec 1104 #define _DMA_IF_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
<> 150:02e0a0aed4ec 1105 #define DMA_IF_CH6DONE_DEFAULT (_DMA_IF_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IF */
<> 150:02e0a0aed4ec 1106 #define DMA_IF_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag */
<> 150:02e0a0aed4ec 1107 #define _DMA_IF_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */
<> 150:02e0a0aed4ec 1108 #define _DMA_IF_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */
<> 150:02e0a0aed4ec 1109 #define _DMA_IF_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
<> 150:02e0a0aed4ec 1110 #define DMA_IF_CH7DONE_DEFAULT (_DMA_IF_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IF */
<> 150:02e0a0aed4ec 1111 #define DMA_IF_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag */
<> 150:02e0a0aed4ec 1112 #define _DMA_IF_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */
<> 150:02e0a0aed4ec 1113 #define _DMA_IF_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */
<> 150:02e0a0aed4ec 1114 #define _DMA_IF_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
<> 150:02e0a0aed4ec 1115 #define DMA_IF_CH8DONE_DEFAULT (_DMA_IF_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IF */
<> 150:02e0a0aed4ec 1116 #define DMA_IF_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag */
<> 150:02e0a0aed4ec 1117 #define _DMA_IF_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */
<> 150:02e0a0aed4ec 1118 #define _DMA_IF_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */
<> 150:02e0a0aed4ec 1119 #define _DMA_IF_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
<> 150:02e0a0aed4ec 1120 #define DMA_IF_CH9DONE_DEFAULT (_DMA_IF_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IF */
<> 150:02e0a0aed4ec 1121 #define DMA_IF_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag */
<> 150:02e0a0aed4ec 1122 #define _DMA_IF_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */
<> 150:02e0a0aed4ec 1123 #define _DMA_IF_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */
<> 150:02e0a0aed4ec 1124 #define _DMA_IF_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
<> 150:02e0a0aed4ec 1125 #define DMA_IF_CH10DONE_DEFAULT (_DMA_IF_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IF */
<> 150:02e0a0aed4ec 1126 #define DMA_IF_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag */
<> 150:02e0a0aed4ec 1127 #define _DMA_IF_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */
<> 150:02e0a0aed4ec 1128 #define _DMA_IF_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */
<> 150:02e0a0aed4ec 1129 #define _DMA_IF_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
<> 150:02e0a0aed4ec 1130 #define DMA_IF_CH11DONE_DEFAULT (_DMA_IF_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IF */
<> 150:02e0a0aed4ec 1131 #define DMA_IF_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag */
<> 150:02e0a0aed4ec 1132 #define _DMA_IF_ERR_SHIFT 31 /**< Shift value for DMA_ERR */
<> 150:02e0a0aed4ec 1133 #define _DMA_IF_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */
<> 150:02e0a0aed4ec 1134 #define _DMA_IF_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
<> 150:02e0a0aed4ec 1135 #define DMA_IF_ERR_DEFAULT (_DMA_IF_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IF */
<> 150:02e0a0aed4ec 1136
<> 150:02e0a0aed4ec 1137 /* Bit fields for DMA IFS */
<> 150:02e0a0aed4ec 1138 #define _DMA_IFS_RESETVALUE 0x00000000UL /**< Default value for DMA_IFS */
<> 150:02e0a0aed4ec 1139 #define _DMA_IFS_MASK 0x80000FFFUL /**< Mask for DMA_IFS */
<> 150:02e0a0aed4ec 1140 #define DMA_IFS_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag Set */
<> 150:02e0a0aed4ec 1141 #define _DMA_IFS_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */
<> 150:02e0a0aed4ec 1142 #define _DMA_IFS_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */
<> 150:02e0a0aed4ec 1143 #define _DMA_IFS_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
<> 150:02e0a0aed4ec 1144 #define DMA_IFS_CH0DONE_DEFAULT (_DMA_IFS_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IFS */
<> 150:02e0a0aed4ec 1145 #define DMA_IFS_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag Set */
<> 150:02e0a0aed4ec 1146 #define _DMA_IFS_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */
<> 150:02e0a0aed4ec 1147 #define _DMA_IFS_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */
<> 150:02e0a0aed4ec 1148 #define _DMA_IFS_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
<> 150:02e0a0aed4ec 1149 #define DMA_IFS_CH1DONE_DEFAULT (_DMA_IFS_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IFS */
<> 150:02e0a0aed4ec 1150 #define DMA_IFS_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag Set */
<> 150:02e0a0aed4ec 1151 #define _DMA_IFS_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */
<> 150:02e0a0aed4ec 1152 #define _DMA_IFS_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */
<> 150:02e0a0aed4ec 1153 #define _DMA_IFS_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
<> 150:02e0a0aed4ec 1154 #define DMA_IFS_CH2DONE_DEFAULT (_DMA_IFS_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IFS */
<> 150:02e0a0aed4ec 1155 #define DMA_IFS_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag Set */
<> 150:02e0a0aed4ec 1156 #define _DMA_IFS_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */
<> 150:02e0a0aed4ec 1157 #define _DMA_IFS_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */
<> 150:02e0a0aed4ec 1158 #define _DMA_IFS_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
<> 150:02e0a0aed4ec 1159 #define DMA_IFS_CH3DONE_DEFAULT (_DMA_IFS_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IFS */
<> 150:02e0a0aed4ec 1160 #define DMA_IFS_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag Set */
<> 150:02e0a0aed4ec 1161 #define _DMA_IFS_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */
<> 150:02e0a0aed4ec 1162 #define _DMA_IFS_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */
<> 150:02e0a0aed4ec 1163 #define _DMA_IFS_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
<> 150:02e0a0aed4ec 1164 #define DMA_IFS_CH4DONE_DEFAULT (_DMA_IFS_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IFS */
<> 150:02e0a0aed4ec 1165 #define DMA_IFS_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag Set */
<> 150:02e0a0aed4ec 1166 #define _DMA_IFS_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */
<> 150:02e0a0aed4ec 1167 #define _DMA_IFS_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */
<> 150:02e0a0aed4ec 1168 #define _DMA_IFS_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
<> 150:02e0a0aed4ec 1169 #define DMA_IFS_CH5DONE_DEFAULT (_DMA_IFS_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IFS */
<> 150:02e0a0aed4ec 1170 #define DMA_IFS_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag Set */
<> 150:02e0a0aed4ec 1171 #define _DMA_IFS_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */
<> 150:02e0a0aed4ec 1172 #define _DMA_IFS_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */
<> 150:02e0a0aed4ec 1173 #define _DMA_IFS_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
<> 150:02e0a0aed4ec 1174 #define DMA_IFS_CH6DONE_DEFAULT (_DMA_IFS_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IFS */
<> 150:02e0a0aed4ec 1175 #define DMA_IFS_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag Set */
<> 150:02e0a0aed4ec 1176 #define _DMA_IFS_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */
<> 150:02e0a0aed4ec 1177 #define _DMA_IFS_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */
<> 150:02e0a0aed4ec 1178 #define _DMA_IFS_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
<> 150:02e0a0aed4ec 1179 #define DMA_IFS_CH7DONE_DEFAULT (_DMA_IFS_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IFS */
<> 150:02e0a0aed4ec 1180 #define DMA_IFS_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag Set */
<> 150:02e0a0aed4ec 1181 #define _DMA_IFS_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */
<> 150:02e0a0aed4ec 1182 #define _DMA_IFS_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */
<> 150:02e0a0aed4ec 1183 #define _DMA_IFS_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
<> 150:02e0a0aed4ec 1184 #define DMA_IFS_CH8DONE_DEFAULT (_DMA_IFS_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IFS */
<> 150:02e0a0aed4ec 1185 #define DMA_IFS_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag Set */
<> 150:02e0a0aed4ec 1186 #define _DMA_IFS_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */
<> 150:02e0a0aed4ec 1187 #define _DMA_IFS_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */
<> 150:02e0a0aed4ec 1188 #define _DMA_IFS_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
<> 150:02e0a0aed4ec 1189 #define DMA_IFS_CH9DONE_DEFAULT (_DMA_IFS_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IFS */
<> 150:02e0a0aed4ec 1190 #define DMA_IFS_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag Set */
<> 150:02e0a0aed4ec 1191 #define _DMA_IFS_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */
<> 150:02e0a0aed4ec 1192 #define _DMA_IFS_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */
<> 150:02e0a0aed4ec 1193 #define _DMA_IFS_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
<> 150:02e0a0aed4ec 1194 #define DMA_IFS_CH10DONE_DEFAULT (_DMA_IFS_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IFS */
<> 150:02e0a0aed4ec 1195 #define DMA_IFS_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag Set */
<> 150:02e0a0aed4ec 1196 #define _DMA_IFS_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */
<> 150:02e0a0aed4ec 1197 #define _DMA_IFS_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */
<> 150:02e0a0aed4ec 1198 #define _DMA_IFS_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
<> 150:02e0a0aed4ec 1199 #define DMA_IFS_CH11DONE_DEFAULT (_DMA_IFS_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IFS */
<> 150:02e0a0aed4ec 1200 #define DMA_IFS_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Set */
<> 150:02e0a0aed4ec 1201 #define _DMA_IFS_ERR_SHIFT 31 /**< Shift value for DMA_ERR */
<> 150:02e0a0aed4ec 1202 #define _DMA_IFS_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */
<> 150:02e0a0aed4ec 1203 #define _DMA_IFS_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
<> 150:02e0a0aed4ec 1204 #define DMA_IFS_ERR_DEFAULT (_DMA_IFS_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IFS */
<> 150:02e0a0aed4ec 1205
<> 150:02e0a0aed4ec 1206 /* Bit fields for DMA IFC */
<> 150:02e0a0aed4ec 1207 #define _DMA_IFC_RESETVALUE 0x00000000UL /**< Default value for DMA_IFC */
<> 150:02e0a0aed4ec 1208 #define _DMA_IFC_MASK 0x80000FFFUL /**< Mask for DMA_IFC */
<> 150:02e0a0aed4ec 1209 #define DMA_IFC_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag Clear */
<> 150:02e0a0aed4ec 1210 #define _DMA_IFC_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */
<> 150:02e0a0aed4ec 1211 #define _DMA_IFC_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */
<> 150:02e0a0aed4ec 1212 #define _DMA_IFC_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
<> 150:02e0a0aed4ec 1213 #define DMA_IFC_CH0DONE_DEFAULT (_DMA_IFC_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IFC */
<> 150:02e0a0aed4ec 1214 #define DMA_IFC_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag Clear */
<> 150:02e0a0aed4ec 1215 #define _DMA_IFC_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */
<> 150:02e0a0aed4ec 1216 #define _DMA_IFC_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */
<> 150:02e0a0aed4ec 1217 #define _DMA_IFC_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
<> 150:02e0a0aed4ec 1218 #define DMA_IFC_CH1DONE_DEFAULT (_DMA_IFC_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IFC */
<> 150:02e0a0aed4ec 1219 #define DMA_IFC_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag Clear */
<> 150:02e0a0aed4ec 1220 #define _DMA_IFC_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */
<> 150:02e0a0aed4ec 1221 #define _DMA_IFC_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */
<> 150:02e0a0aed4ec 1222 #define _DMA_IFC_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
<> 150:02e0a0aed4ec 1223 #define DMA_IFC_CH2DONE_DEFAULT (_DMA_IFC_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IFC */
<> 150:02e0a0aed4ec 1224 #define DMA_IFC_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag Clear */
<> 150:02e0a0aed4ec 1225 #define _DMA_IFC_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */
<> 150:02e0a0aed4ec 1226 #define _DMA_IFC_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */
<> 150:02e0a0aed4ec 1227 #define _DMA_IFC_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
<> 150:02e0a0aed4ec 1228 #define DMA_IFC_CH3DONE_DEFAULT (_DMA_IFC_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IFC */
<> 150:02e0a0aed4ec 1229 #define DMA_IFC_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag Clear */
<> 150:02e0a0aed4ec 1230 #define _DMA_IFC_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */
<> 150:02e0a0aed4ec 1231 #define _DMA_IFC_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */
<> 150:02e0a0aed4ec 1232 #define _DMA_IFC_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
<> 150:02e0a0aed4ec 1233 #define DMA_IFC_CH4DONE_DEFAULT (_DMA_IFC_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IFC */
<> 150:02e0a0aed4ec 1234 #define DMA_IFC_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag Clear */
<> 150:02e0a0aed4ec 1235 #define _DMA_IFC_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */
<> 150:02e0a0aed4ec 1236 #define _DMA_IFC_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */
<> 150:02e0a0aed4ec 1237 #define _DMA_IFC_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
<> 150:02e0a0aed4ec 1238 #define DMA_IFC_CH5DONE_DEFAULT (_DMA_IFC_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IFC */
<> 150:02e0a0aed4ec 1239 #define DMA_IFC_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag Clear */
<> 150:02e0a0aed4ec 1240 #define _DMA_IFC_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */
<> 150:02e0a0aed4ec 1241 #define _DMA_IFC_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */
<> 150:02e0a0aed4ec 1242 #define _DMA_IFC_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
<> 150:02e0a0aed4ec 1243 #define DMA_IFC_CH6DONE_DEFAULT (_DMA_IFC_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IFC */
<> 150:02e0a0aed4ec 1244 #define DMA_IFC_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag Clear */
<> 150:02e0a0aed4ec 1245 #define _DMA_IFC_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */
<> 150:02e0a0aed4ec 1246 #define _DMA_IFC_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */
<> 150:02e0a0aed4ec 1247 #define _DMA_IFC_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
<> 150:02e0a0aed4ec 1248 #define DMA_IFC_CH7DONE_DEFAULT (_DMA_IFC_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IFC */
<> 150:02e0a0aed4ec 1249 #define DMA_IFC_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag Clear */
<> 150:02e0a0aed4ec 1250 #define _DMA_IFC_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */
<> 150:02e0a0aed4ec 1251 #define _DMA_IFC_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */
<> 150:02e0a0aed4ec 1252 #define _DMA_IFC_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
<> 150:02e0a0aed4ec 1253 #define DMA_IFC_CH8DONE_DEFAULT (_DMA_IFC_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IFC */
<> 150:02e0a0aed4ec 1254 #define DMA_IFC_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag Clear */
<> 150:02e0a0aed4ec 1255 #define _DMA_IFC_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */
<> 150:02e0a0aed4ec 1256 #define _DMA_IFC_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */
<> 150:02e0a0aed4ec 1257 #define _DMA_IFC_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
<> 150:02e0a0aed4ec 1258 #define DMA_IFC_CH9DONE_DEFAULT (_DMA_IFC_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IFC */
<> 150:02e0a0aed4ec 1259 #define DMA_IFC_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag Clear */
<> 150:02e0a0aed4ec 1260 #define _DMA_IFC_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */
<> 150:02e0a0aed4ec 1261 #define _DMA_IFC_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */
<> 150:02e0a0aed4ec 1262 #define _DMA_IFC_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
<> 150:02e0a0aed4ec 1263 #define DMA_IFC_CH10DONE_DEFAULT (_DMA_IFC_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IFC */
<> 150:02e0a0aed4ec 1264 #define DMA_IFC_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag Clear */
<> 150:02e0a0aed4ec 1265 #define _DMA_IFC_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */
<> 150:02e0a0aed4ec 1266 #define _DMA_IFC_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */
<> 150:02e0a0aed4ec 1267 #define _DMA_IFC_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
<> 150:02e0a0aed4ec 1268 #define DMA_IFC_CH11DONE_DEFAULT (_DMA_IFC_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IFC */
<> 150:02e0a0aed4ec 1269 #define DMA_IFC_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Clear */
<> 150:02e0a0aed4ec 1270 #define _DMA_IFC_ERR_SHIFT 31 /**< Shift value for DMA_ERR */
<> 150:02e0a0aed4ec 1271 #define _DMA_IFC_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */
<> 150:02e0a0aed4ec 1272 #define _DMA_IFC_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
<> 150:02e0a0aed4ec 1273 #define DMA_IFC_ERR_DEFAULT (_DMA_IFC_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IFC */
<> 150:02e0a0aed4ec 1274
<> 150:02e0a0aed4ec 1275 /* Bit fields for DMA IEN */
<> 150:02e0a0aed4ec 1276 #define _DMA_IEN_RESETVALUE 0x00000000UL /**< Default value for DMA_IEN */
<> 150:02e0a0aed4ec 1277 #define _DMA_IEN_MASK 0x80000FFFUL /**< Mask for DMA_IEN */
<> 150:02e0a0aed4ec 1278 #define DMA_IEN_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Enable */
<> 150:02e0a0aed4ec 1279 #define _DMA_IEN_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */
<> 150:02e0a0aed4ec 1280 #define _DMA_IEN_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */
<> 150:02e0a0aed4ec 1281 #define _DMA_IEN_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
<> 150:02e0a0aed4ec 1282 #define DMA_IEN_CH0DONE_DEFAULT (_DMA_IEN_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IEN */
<> 150:02e0a0aed4ec 1283 #define DMA_IEN_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Enable */
<> 150:02e0a0aed4ec 1284 #define _DMA_IEN_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */
<> 150:02e0a0aed4ec 1285 #define _DMA_IEN_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */
<> 150:02e0a0aed4ec 1286 #define _DMA_IEN_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
<> 150:02e0a0aed4ec 1287 #define DMA_IEN_CH1DONE_DEFAULT (_DMA_IEN_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IEN */
<> 150:02e0a0aed4ec 1288 #define DMA_IEN_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Enable */
<> 150:02e0a0aed4ec 1289 #define _DMA_IEN_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */
<> 150:02e0a0aed4ec 1290 #define _DMA_IEN_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */
<> 150:02e0a0aed4ec 1291 #define _DMA_IEN_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
<> 150:02e0a0aed4ec 1292 #define DMA_IEN_CH2DONE_DEFAULT (_DMA_IEN_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IEN */
<> 150:02e0a0aed4ec 1293 #define DMA_IEN_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Enable */
<> 150:02e0a0aed4ec 1294 #define _DMA_IEN_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */
<> 150:02e0a0aed4ec 1295 #define _DMA_IEN_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */
<> 150:02e0a0aed4ec 1296 #define _DMA_IEN_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
<> 150:02e0a0aed4ec 1297 #define DMA_IEN_CH3DONE_DEFAULT (_DMA_IEN_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IEN */
<> 150:02e0a0aed4ec 1298 #define DMA_IEN_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Enable */
<> 150:02e0a0aed4ec 1299 #define _DMA_IEN_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */
<> 150:02e0a0aed4ec 1300 #define _DMA_IEN_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */
<> 150:02e0a0aed4ec 1301 #define _DMA_IEN_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
<> 150:02e0a0aed4ec 1302 #define DMA_IEN_CH4DONE_DEFAULT (_DMA_IEN_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IEN */
<> 150:02e0a0aed4ec 1303 #define DMA_IEN_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Enable */
<> 150:02e0a0aed4ec 1304 #define _DMA_IEN_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */
<> 150:02e0a0aed4ec 1305 #define _DMA_IEN_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */
<> 150:02e0a0aed4ec 1306 #define _DMA_IEN_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
<> 150:02e0a0aed4ec 1307 #define DMA_IEN_CH5DONE_DEFAULT (_DMA_IEN_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IEN */
<> 150:02e0a0aed4ec 1308 #define DMA_IEN_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Enable */
<> 150:02e0a0aed4ec 1309 #define _DMA_IEN_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */
<> 150:02e0a0aed4ec 1310 #define _DMA_IEN_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */
<> 150:02e0a0aed4ec 1311 #define _DMA_IEN_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
<> 150:02e0a0aed4ec 1312 #define DMA_IEN_CH6DONE_DEFAULT (_DMA_IEN_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IEN */
<> 150:02e0a0aed4ec 1313 #define DMA_IEN_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Enable */
<> 150:02e0a0aed4ec 1314 #define _DMA_IEN_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */
<> 150:02e0a0aed4ec 1315 #define _DMA_IEN_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */
<> 150:02e0a0aed4ec 1316 #define _DMA_IEN_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
<> 150:02e0a0aed4ec 1317 #define DMA_IEN_CH7DONE_DEFAULT (_DMA_IEN_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IEN */
<> 150:02e0a0aed4ec 1318 #define DMA_IEN_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Enable */
<> 150:02e0a0aed4ec 1319 #define _DMA_IEN_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */
<> 150:02e0a0aed4ec 1320 #define _DMA_IEN_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */
<> 150:02e0a0aed4ec 1321 #define _DMA_IEN_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
<> 150:02e0a0aed4ec 1322 #define DMA_IEN_CH8DONE_DEFAULT (_DMA_IEN_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IEN */
<> 150:02e0a0aed4ec 1323 #define DMA_IEN_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Enable */
<> 150:02e0a0aed4ec 1324 #define _DMA_IEN_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */
<> 150:02e0a0aed4ec 1325 #define _DMA_IEN_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */
<> 150:02e0a0aed4ec 1326 #define _DMA_IEN_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
<> 150:02e0a0aed4ec 1327 #define DMA_IEN_CH9DONE_DEFAULT (_DMA_IEN_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IEN */
<> 150:02e0a0aed4ec 1328 #define DMA_IEN_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Enable */
<> 150:02e0a0aed4ec 1329 #define _DMA_IEN_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */
<> 150:02e0a0aed4ec 1330 #define _DMA_IEN_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */
<> 150:02e0a0aed4ec 1331 #define _DMA_IEN_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
<> 150:02e0a0aed4ec 1332 #define DMA_IEN_CH10DONE_DEFAULT (_DMA_IEN_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IEN */
<> 150:02e0a0aed4ec 1333 #define DMA_IEN_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Enable */
<> 150:02e0a0aed4ec 1334 #define _DMA_IEN_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */
<> 150:02e0a0aed4ec 1335 #define _DMA_IEN_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */
<> 150:02e0a0aed4ec 1336 #define _DMA_IEN_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
<> 150:02e0a0aed4ec 1337 #define DMA_IEN_CH11DONE_DEFAULT (_DMA_IEN_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IEN */
<> 150:02e0a0aed4ec 1338 #define DMA_IEN_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Enable */
<> 150:02e0a0aed4ec 1339 #define _DMA_IEN_ERR_SHIFT 31 /**< Shift value for DMA_ERR */
<> 150:02e0a0aed4ec 1340 #define _DMA_IEN_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */
<> 150:02e0a0aed4ec 1341 #define _DMA_IEN_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
<> 150:02e0a0aed4ec 1342 #define DMA_IEN_ERR_DEFAULT (_DMA_IEN_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IEN */
<> 150:02e0a0aed4ec 1343
<> 150:02e0a0aed4ec 1344 /* Bit fields for DMA CTRL */
<> 150:02e0a0aed4ec 1345 #define _DMA_CTRL_RESETVALUE 0x00000000UL /**< Default value for DMA_CTRL */
<> 150:02e0a0aed4ec 1346 #define _DMA_CTRL_MASK 0x00000003UL /**< Mask for DMA_CTRL */
<> 150:02e0a0aed4ec 1347 #define DMA_CTRL_DESCRECT (0x1UL << 0) /**< Descriptor Specifies Rectangle */
<> 150:02e0a0aed4ec 1348 #define _DMA_CTRL_DESCRECT_SHIFT 0 /**< Shift value for DMA_DESCRECT */
<> 150:02e0a0aed4ec 1349 #define _DMA_CTRL_DESCRECT_MASK 0x1UL /**< Bit mask for DMA_DESCRECT */
<> 150:02e0a0aed4ec 1350 #define _DMA_CTRL_DESCRECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRL */
<> 150:02e0a0aed4ec 1351 #define DMA_CTRL_DESCRECT_DEFAULT (_DMA_CTRL_DESCRECT_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CTRL */
<> 150:02e0a0aed4ec 1352 #define DMA_CTRL_PRDU (0x1UL << 1) /**< Prevent Rect Descriptor Update */
<> 150:02e0a0aed4ec 1353 #define _DMA_CTRL_PRDU_SHIFT 1 /**< Shift value for DMA_PRDU */
<> 150:02e0a0aed4ec 1354 #define _DMA_CTRL_PRDU_MASK 0x2UL /**< Bit mask for DMA_PRDU */
<> 150:02e0a0aed4ec 1355 #define _DMA_CTRL_PRDU_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRL */
<> 150:02e0a0aed4ec 1356 #define DMA_CTRL_PRDU_DEFAULT (_DMA_CTRL_PRDU_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CTRL */
<> 150:02e0a0aed4ec 1357
<> 150:02e0a0aed4ec 1358 /* Bit fields for DMA RDS */
<> 150:02e0a0aed4ec 1359 #define _DMA_RDS_RESETVALUE 0x00000000UL /**< Default value for DMA_RDS */
<> 150:02e0a0aed4ec 1360 #define _DMA_RDS_MASK 0x00000FFFUL /**< Mask for DMA_RDS */
<> 150:02e0a0aed4ec 1361 #define DMA_RDS_RDSCH0 (0x1UL << 0) /**< Retain Descriptor State */
<> 150:02e0a0aed4ec 1362 #define _DMA_RDS_RDSCH0_SHIFT 0 /**< Shift value for DMA_RDSCH0 */
<> 150:02e0a0aed4ec 1363 #define _DMA_RDS_RDSCH0_MASK 0x1UL /**< Bit mask for DMA_RDSCH0 */
<> 150:02e0a0aed4ec 1364 #define _DMA_RDS_RDSCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
<> 150:02e0a0aed4ec 1365 #define DMA_RDS_RDSCH0_DEFAULT (_DMA_RDS_RDSCH0_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_RDS */
<> 150:02e0a0aed4ec 1366 #define DMA_RDS_RDSCH1 (0x1UL << 1) /**< Retain Descriptor State */
<> 150:02e0a0aed4ec 1367 #define _DMA_RDS_RDSCH1_SHIFT 1 /**< Shift value for DMA_RDSCH1 */
<> 150:02e0a0aed4ec 1368 #define _DMA_RDS_RDSCH1_MASK 0x2UL /**< Bit mask for DMA_RDSCH1 */
<> 150:02e0a0aed4ec 1369 #define _DMA_RDS_RDSCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
<> 150:02e0a0aed4ec 1370 #define DMA_RDS_RDSCH1_DEFAULT (_DMA_RDS_RDSCH1_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_RDS */
<> 150:02e0a0aed4ec 1371 #define DMA_RDS_RDSCH2 (0x1UL << 2) /**< Retain Descriptor State */
<> 150:02e0a0aed4ec 1372 #define _DMA_RDS_RDSCH2_SHIFT 2 /**< Shift value for DMA_RDSCH2 */
<> 150:02e0a0aed4ec 1373 #define _DMA_RDS_RDSCH2_MASK 0x4UL /**< Bit mask for DMA_RDSCH2 */
<> 150:02e0a0aed4ec 1374 #define _DMA_RDS_RDSCH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
<> 150:02e0a0aed4ec 1375 #define DMA_RDS_RDSCH2_DEFAULT (_DMA_RDS_RDSCH2_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_RDS */
<> 150:02e0a0aed4ec 1376 #define DMA_RDS_RDSCH3 (0x1UL << 3) /**< Retain Descriptor State */
<> 150:02e0a0aed4ec 1377 #define _DMA_RDS_RDSCH3_SHIFT 3 /**< Shift value for DMA_RDSCH3 */
<> 150:02e0a0aed4ec 1378 #define _DMA_RDS_RDSCH3_MASK 0x8UL /**< Bit mask for DMA_RDSCH3 */
<> 150:02e0a0aed4ec 1379 #define _DMA_RDS_RDSCH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
<> 150:02e0a0aed4ec 1380 #define DMA_RDS_RDSCH3_DEFAULT (_DMA_RDS_RDSCH3_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_RDS */
<> 150:02e0a0aed4ec 1381 #define DMA_RDS_RDSCH4 (0x1UL << 4) /**< Retain Descriptor State */
<> 150:02e0a0aed4ec 1382 #define _DMA_RDS_RDSCH4_SHIFT 4 /**< Shift value for DMA_RDSCH4 */
<> 150:02e0a0aed4ec 1383 #define _DMA_RDS_RDSCH4_MASK 0x10UL /**< Bit mask for DMA_RDSCH4 */
<> 150:02e0a0aed4ec 1384 #define _DMA_RDS_RDSCH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
<> 150:02e0a0aed4ec 1385 #define DMA_RDS_RDSCH4_DEFAULT (_DMA_RDS_RDSCH4_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_RDS */
<> 150:02e0a0aed4ec 1386 #define DMA_RDS_RDSCH5 (0x1UL << 5) /**< Retain Descriptor State */
<> 150:02e0a0aed4ec 1387 #define _DMA_RDS_RDSCH5_SHIFT 5 /**< Shift value for DMA_RDSCH5 */
<> 150:02e0a0aed4ec 1388 #define _DMA_RDS_RDSCH5_MASK 0x20UL /**< Bit mask for DMA_RDSCH5 */
<> 150:02e0a0aed4ec 1389 #define _DMA_RDS_RDSCH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
<> 150:02e0a0aed4ec 1390 #define DMA_RDS_RDSCH5_DEFAULT (_DMA_RDS_RDSCH5_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_RDS */
<> 150:02e0a0aed4ec 1391 #define DMA_RDS_RDSCH6 (0x1UL << 6) /**< Retain Descriptor State */
<> 150:02e0a0aed4ec 1392 #define _DMA_RDS_RDSCH6_SHIFT 6 /**< Shift value for DMA_RDSCH6 */
<> 150:02e0a0aed4ec 1393 #define _DMA_RDS_RDSCH6_MASK 0x40UL /**< Bit mask for DMA_RDSCH6 */
<> 150:02e0a0aed4ec 1394 #define _DMA_RDS_RDSCH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
<> 150:02e0a0aed4ec 1395 #define DMA_RDS_RDSCH6_DEFAULT (_DMA_RDS_RDSCH6_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_RDS */
<> 150:02e0a0aed4ec 1396 #define DMA_RDS_RDSCH7 (0x1UL << 7) /**< Retain Descriptor State */
<> 150:02e0a0aed4ec 1397 #define _DMA_RDS_RDSCH7_SHIFT 7 /**< Shift value for DMA_RDSCH7 */
<> 150:02e0a0aed4ec 1398 #define _DMA_RDS_RDSCH7_MASK 0x80UL /**< Bit mask for DMA_RDSCH7 */
<> 150:02e0a0aed4ec 1399 #define _DMA_RDS_RDSCH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
<> 150:02e0a0aed4ec 1400 #define DMA_RDS_RDSCH7_DEFAULT (_DMA_RDS_RDSCH7_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_RDS */
<> 150:02e0a0aed4ec 1401 #define DMA_RDS_RDSCH8 (0x1UL << 8) /**< Retain Descriptor State */
<> 150:02e0a0aed4ec 1402 #define _DMA_RDS_RDSCH8_SHIFT 8 /**< Shift value for DMA_RDSCH8 */
<> 150:02e0a0aed4ec 1403 #define _DMA_RDS_RDSCH8_MASK 0x100UL /**< Bit mask for DMA_RDSCH8 */
<> 150:02e0a0aed4ec 1404 #define _DMA_RDS_RDSCH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
<> 150:02e0a0aed4ec 1405 #define DMA_RDS_RDSCH8_DEFAULT (_DMA_RDS_RDSCH8_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_RDS */
<> 150:02e0a0aed4ec 1406 #define DMA_RDS_RDSCH9 (0x1UL << 9) /**< Retain Descriptor State */
<> 150:02e0a0aed4ec 1407 #define _DMA_RDS_RDSCH9_SHIFT 9 /**< Shift value for DMA_RDSCH9 */
<> 150:02e0a0aed4ec 1408 #define _DMA_RDS_RDSCH9_MASK 0x200UL /**< Bit mask for DMA_RDSCH9 */
<> 150:02e0a0aed4ec 1409 #define _DMA_RDS_RDSCH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
<> 150:02e0a0aed4ec 1410 #define DMA_RDS_RDSCH9_DEFAULT (_DMA_RDS_RDSCH9_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_RDS */
<> 150:02e0a0aed4ec 1411 #define DMA_RDS_RDSCH10 (0x1UL << 10) /**< Retain Descriptor State */
<> 150:02e0a0aed4ec 1412 #define _DMA_RDS_RDSCH10_SHIFT 10 /**< Shift value for DMA_RDSCH10 */
<> 150:02e0a0aed4ec 1413 #define _DMA_RDS_RDSCH10_MASK 0x400UL /**< Bit mask for DMA_RDSCH10 */
<> 150:02e0a0aed4ec 1414 #define _DMA_RDS_RDSCH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
<> 150:02e0a0aed4ec 1415 #define DMA_RDS_RDSCH10_DEFAULT (_DMA_RDS_RDSCH10_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_RDS */
<> 150:02e0a0aed4ec 1416 #define DMA_RDS_RDSCH11 (0x1UL << 11) /**< Retain Descriptor State */
<> 150:02e0a0aed4ec 1417 #define _DMA_RDS_RDSCH11_SHIFT 11 /**< Shift value for DMA_RDSCH11 */
<> 150:02e0a0aed4ec 1418 #define _DMA_RDS_RDSCH11_MASK 0x800UL /**< Bit mask for DMA_RDSCH11 */
<> 150:02e0a0aed4ec 1419 #define _DMA_RDS_RDSCH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
<> 150:02e0a0aed4ec 1420 #define DMA_RDS_RDSCH11_DEFAULT (_DMA_RDS_RDSCH11_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_RDS */
<> 150:02e0a0aed4ec 1421
<> 150:02e0a0aed4ec 1422 /* Bit fields for DMA LOOP0 */
<> 150:02e0a0aed4ec 1423 #define _DMA_LOOP0_RESETVALUE 0x00000000UL /**< Default value for DMA_LOOP0 */
<> 150:02e0a0aed4ec 1424 #define _DMA_LOOP0_MASK 0x000103FFUL /**< Mask for DMA_LOOP0 */
<> 150:02e0a0aed4ec 1425 #define _DMA_LOOP0_WIDTH_SHIFT 0 /**< Shift value for DMA_WIDTH */
<> 150:02e0a0aed4ec 1426 #define _DMA_LOOP0_WIDTH_MASK 0x3FFUL /**< Bit mask for DMA_WIDTH */
<> 150:02e0a0aed4ec 1427 #define _DMA_LOOP0_WIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP0 */
<> 150:02e0a0aed4ec 1428 #define DMA_LOOP0_WIDTH_DEFAULT (_DMA_LOOP0_WIDTH_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_LOOP0 */
<> 150:02e0a0aed4ec 1429 #define DMA_LOOP0_EN (0x1UL << 16) /**< DMA Channel 0 Loop Enable */
<> 150:02e0a0aed4ec 1430 #define _DMA_LOOP0_EN_SHIFT 16 /**< Shift value for DMA_EN */
<> 150:02e0a0aed4ec 1431 #define _DMA_LOOP0_EN_MASK 0x10000UL /**< Bit mask for DMA_EN */
<> 150:02e0a0aed4ec 1432 #define _DMA_LOOP0_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP0 */
<> 150:02e0a0aed4ec 1433 #define DMA_LOOP0_EN_DEFAULT (_DMA_LOOP0_EN_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_LOOP0 */
<> 150:02e0a0aed4ec 1434
<> 150:02e0a0aed4ec 1435 /* Bit fields for DMA LOOP1 */
<> 150:02e0a0aed4ec 1436 #define _DMA_LOOP1_RESETVALUE 0x00000000UL /**< Default value for DMA_LOOP1 */
<> 150:02e0a0aed4ec 1437 #define _DMA_LOOP1_MASK 0x000103FFUL /**< Mask for DMA_LOOP1 */
<> 150:02e0a0aed4ec 1438 #define _DMA_LOOP1_WIDTH_SHIFT 0 /**< Shift value for DMA_WIDTH */
<> 150:02e0a0aed4ec 1439 #define _DMA_LOOP1_WIDTH_MASK 0x3FFUL /**< Bit mask for DMA_WIDTH */
<> 150:02e0a0aed4ec 1440 #define _DMA_LOOP1_WIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP1 */
<> 150:02e0a0aed4ec 1441 #define DMA_LOOP1_WIDTH_DEFAULT (_DMA_LOOP1_WIDTH_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_LOOP1 */
<> 150:02e0a0aed4ec 1442 #define DMA_LOOP1_EN (0x1UL << 16) /**< DMA Channel 1 Loop Enable */
<> 150:02e0a0aed4ec 1443 #define _DMA_LOOP1_EN_SHIFT 16 /**< Shift value for DMA_EN */
<> 150:02e0a0aed4ec 1444 #define _DMA_LOOP1_EN_MASK 0x10000UL /**< Bit mask for DMA_EN */
<> 150:02e0a0aed4ec 1445 #define _DMA_LOOP1_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP1 */
<> 150:02e0a0aed4ec 1446 #define DMA_LOOP1_EN_DEFAULT (_DMA_LOOP1_EN_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_LOOP1 */
<> 150:02e0a0aed4ec 1447
<> 150:02e0a0aed4ec 1448 /* Bit fields for DMA RECT0 */
<> 150:02e0a0aed4ec 1449 #define _DMA_RECT0_RESETVALUE 0x00000000UL /**< Default value for DMA_RECT0 */
<> 150:02e0a0aed4ec 1450 #define _DMA_RECT0_MASK 0xFFFFFFFFUL /**< Mask for DMA_RECT0 */
<> 150:02e0a0aed4ec 1451 #define _DMA_RECT0_HEIGHT_SHIFT 0 /**< Shift value for DMA_HEIGHT */
<> 150:02e0a0aed4ec 1452 #define _DMA_RECT0_HEIGHT_MASK 0x3FFUL /**< Bit mask for DMA_HEIGHT */
<> 150:02e0a0aed4ec 1453 #define _DMA_RECT0_HEIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */
<> 150:02e0a0aed4ec 1454 #define DMA_RECT0_HEIGHT_DEFAULT (_DMA_RECT0_HEIGHT_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_RECT0 */
<> 150:02e0a0aed4ec 1455 #define _DMA_RECT0_SRCSTRIDE_SHIFT 10 /**< Shift value for DMA_SRCSTRIDE */
<> 150:02e0a0aed4ec 1456 #define _DMA_RECT0_SRCSTRIDE_MASK 0x1FFC00UL /**< Bit mask for DMA_SRCSTRIDE */
<> 150:02e0a0aed4ec 1457 #define _DMA_RECT0_SRCSTRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */
<> 150:02e0a0aed4ec 1458 #define DMA_RECT0_SRCSTRIDE_DEFAULT (_DMA_RECT0_SRCSTRIDE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_RECT0 */
<> 150:02e0a0aed4ec 1459 #define _DMA_RECT0_DSTSTRIDE_SHIFT 21 /**< Shift value for DMA_DSTSTRIDE */
<> 150:02e0a0aed4ec 1460 #define _DMA_RECT0_DSTSTRIDE_MASK 0xFFE00000UL /**< Bit mask for DMA_DSTSTRIDE */
<> 150:02e0a0aed4ec 1461 #define _DMA_RECT0_DSTSTRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */
<> 150:02e0a0aed4ec 1462 #define DMA_RECT0_DSTSTRIDE_DEFAULT (_DMA_RECT0_DSTSTRIDE_DEFAULT << 21) /**< Shifted mode DEFAULT for DMA_RECT0 */
<> 150:02e0a0aed4ec 1463
<> 150:02e0a0aed4ec 1464 /* Bit fields for DMA CH_CTRL */
<> 150:02e0a0aed4ec 1465 #define _DMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1466 #define _DMA_CH_CTRL_MASK 0x003F000FUL /**< Mask for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1467 #define _DMA_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for DMA_SIGSEL */
<> 150:02e0a0aed4ec 1468 #define _DMA_CH_CTRL_SIGSEL_MASK 0xFUL /**< Bit mask for DMA_SIGSEL */
<> 150:02e0a0aed4ec 1469 #define _DMA_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1470 #define _DMA_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1471 #define _DMA_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000000UL /**< Mode USART0RXDATAV for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1472 #define _DMA_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000000UL /**< Mode USART1RXDATAV for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1473 #define _DMA_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000000UL /**< Mode USART2RXDATAV for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1474 #define _DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV 0x00000000UL /**< Mode LEUART0RXDATAV for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1475 #define _DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV 0x00000000UL /**< Mode LEUART1RXDATAV for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1476 #define _DMA_CH_CTRL_SIGSEL_I2C0RXDATAV 0x00000000UL /**< Mode I2C0RXDATAV for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1477 #define _DMA_CH_CTRL_SIGSEL_I2C1RXDATAV 0x00000000UL /**< Mode I2C1RXDATAV for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1478 #define _DMA_CH_CTRL_SIGSEL_TIMER0UFOF 0x00000000UL /**< Mode TIMER0UFOF for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1479 #define _DMA_CH_CTRL_SIGSEL_TIMER1UFOF 0x00000000UL /**< Mode TIMER1UFOF for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1480 #define _DMA_CH_CTRL_SIGSEL_TIMER2UFOF 0x00000000UL /**< Mode TIMER2UFOF for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1481 #define _DMA_CH_CTRL_SIGSEL_TIMER3UFOF 0x00000000UL /**< Mode TIMER3UFOF for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1482 #define _DMA_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000000UL /**< Mode UART0RXDATAV for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1483 #define _DMA_CH_CTRL_SIGSEL_UART1RXDATAV 0x00000000UL /**< Mode UART1RXDATAV for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1484 #define _DMA_CH_CTRL_SIGSEL_MSCWDATA 0x00000000UL /**< Mode MSCWDATA for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1485 #define _DMA_CH_CTRL_SIGSEL_AESDATAWR 0x00000000UL /**< Mode AESDATAWR for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1486 #define _DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV 0x00000000UL /**< Mode LESENSEBUFDATAV for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1487 #define _DMA_CH_CTRL_SIGSEL_EBIPXL0EMPTY 0x00000000UL /**< Mode EBIPXL0EMPTY for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1488 #define _DMA_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1489 #define _DMA_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1490 #define _DMA_CH_CTRL_SIGSEL_USART0TXBL 0x00000001UL /**< Mode USART0TXBL for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1491 #define _DMA_CH_CTRL_SIGSEL_USART1TXBL 0x00000001UL /**< Mode USART1TXBL for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1492 #define _DMA_CH_CTRL_SIGSEL_USART2TXBL 0x00000001UL /**< Mode USART2TXBL for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1493 #define _DMA_CH_CTRL_SIGSEL_LEUART0TXBL 0x00000001UL /**< Mode LEUART0TXBL for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1494 #define _DMA_CH_CTRL_SIGSEL_LEUART1TXBL 0x00000001UL /**< Mode LEUART1TXBL for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1495 #define _DMA_CH_CTRL_SIGSEL_I2C0TXBL 0x00000001UL /**< Mode I2C0TXBL for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1496 #define _DMA_CH_CTRL_SIGSEL_I2C1TXBL 0x00000001UL /**< Mode I2C1TXBL for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1497 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC0 0x00000001UL /**< Mode TIMER0CC0 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1498 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC0 0x00000001UL /**< Mode TIMER1CC0 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1499 #define _DMA_CH_CTRL_SIGSEL_TIMER2CC0 0x00000001UL /**< Mode TIMER2CC0 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1500 #define _DMA_CH_CTRL_SIGSEL_TIMER3CC0 0x00000001UL /**< Mode TIMER3CC0 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1501 #define _DMA_CH_CTRL_SIGSEL_UART0TXBL 0x00000001UL /**< Mode UART0TXBL for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1502 #define _DMA_CH_CTRL_SIGSEL_UART1TXBL 0x00000001UL /**< Mode UART1TXBL for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1503 #define _DMA_CH_CTRL_SIGSEL_AESXORDATAWR 0x00000001UL /**< Mode AESXORDATAWR for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1504 #define _DMA_CH_CTRL_SIGSEL_EBIPXL1EMPTY 0x00000001UL /**< Mode EBIPXL1EMPTY for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1505 #define _DMA_CH_CTRL_SIGSEL_USART0TXEMPTY 0x00000002UL /**< Mode USART0TXEMPTY for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1506 #define _DMA_CH_CTRL_SIGSEL_USART1TXEMPTY 0x00000002UL /**< Mode USART1TXEMPTY for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1507 #define _DMA_CH_CTRL_SIGSEL_USART2TXEMPTY 0x00000002UL /**< Mode USART2TXEMPTY for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1508 #define _DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY 0x00000002UL /**< Mode LEUART0TXEMPTY for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1509 #define _DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY 0x00000002UL /**< Mode LEUART1TXEMPTY for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1510 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC1 0x00000002UL /**< Mode TIMER0CC1 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1511 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC1 0x00000002UL /**< Mode TIMER1CC1 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1512 #define _DMA_CH_CTRL_SIGSEL_TIMER2CC1 0x00000002UL /**< Mode TIMER2CC1 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1513 #define _DMA_CH_CTRL_SIGSEL_TIMER3CC1 0x00000002UL /**< Mode TIMER3CC1 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1514 #define _DMA_CH_CTRL_SIGSEL_UART0TXEMPTY 0x00000002UL /**< Mode UART0TXEMPTY for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1515 #define _DMA_CH_CTRL_SIGSEL_UART1TXEMPTY 0x00000002UL /**< Mode UART1TXEMPTY for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1516 #define _DMA_CH_CTRL_SIGSEL_AESDATARD 0x00000002UL /**< Mode AESDATARD for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1517 #define _DMA_CH_CTRL_SIGSEL_EBIPXLFULL 0x00000002UL /**< Mode EBIPXLFULL for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1518 #define _DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT 0x00000003UL /**< Mode USART1RXDATAVRIGHT for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1519 #define _DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT 0x00000003UL /**< Mode USART2RXDATAVRIGHT for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1520 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC2 0x00000003UL /**< Mode TIMER0CC2 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1521 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC2 0x00000003UL /**< Mode TIMER1CC2 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1522 #define _DMA_CH_CTRL_SIGSEL_TIMER2CC2 0x00000003UL /**< Mode TIMER2CC2 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1523 #define _DMA_CH_CTRL_SIGSEL_TIMER3CC2 0x00000003UL /**< Mode TIMER3CC2 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1524 #define _DMA_CH_CTRL_SIGSEL_AESKEYWR 0x00000003UL /**< Mode AESKEYWR for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1525 #define _DMA_CH_CTRL_SIGSEL_EBIDDEMPTY 0x00000003UL /**< Mode EBIDDEMPTY for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1526 #define _DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT 0x00000004UL /**< Mode USART1TXBLRIGHT for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1527 #define _DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT 0x00000004UL /**< Mode USART2TXBLRIGHT for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1528 #define DMA_CH_CTRL_SIGSEL_ADC0SINGLE (_DMA_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1529 #define DMA_CH_CTRL_SIGSEL_DAC0CH0 (_DMA_CH_CTRL_SIGSEL_DAC0CH0 << 0) /**< Shifted mode DAC0CH0 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1530 #define DMA_CH_CTRL_SIGSEL_USART0RXDATAV (_DMA_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1531 #define DMA_CH_CTRL_SIGSEL_USART1RXDATAV (_DMA_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1532 #define DMA_CH_CTRL_SIGSEL_USART2RXDATAV (_DMA_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1533 #define DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV << 0) /**< Shifted mode LEUART0RXDATAV for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1534 #define DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV << 0) /**< Shifted mode LEUART1RXDATAV for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1535 #define DMA_CH_CTRL_SIGSEL_I2C0RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV << 0) /**< Shifted mode I2C0RXDATAV for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1536 #define DMA_CH_CTRL_SIGSEL_I2C1RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C1RXDATAV << 0) /**< Shifted mode I2C1RXDATAV for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1537 #define DMA_CH_CTRL_SIGSEL_TIMER0UFOF (_DMA_CH_CTRL_SIGSEL_TIMER0UFOF << 0) /**< Shifted mode TIMER0UFOF for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1538 #define DMA_CH_CTRL_SIGSEL_TIMER1UFOF (_DMA_CH_CTRL_SIGSEL_TIMER1UFOF << 0) /**< Shifted mode TIMER1UFOF for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1539 #define DMA_CH_CTRL_SIGSEL_TIMER2UFOF (_DMA_CH_CTRL_SIGSEL_TIMER2UFOF << 0) /**< Shifted mode TIMER2UFOF for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1540 #define DMA_CH_CTRL_SIGSEL_TIMER3UFOF (_DMA_CH_CTRL_SIGSEL_TIMER3UFOF << 0) /**< Shifted mode TIMER3UFOF for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1541 #define DMA_CH_CTRL_SIGSEL_UART0RXDATAV (_DMA_CH_CTRL_SIGSEL_UART0RXDATAV << 0) /**< Shifted mode UART0RXDATAV for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1542 #define DMA_CH_CTRL_SIGSEL_UART1RXDATAV (_DMA_CH_CTRL_SIGSEL_UART1RXDATAV << 0) /**< Shifted mode UART1RXDATAV for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1543 #define DMA_CH_CTRL_SIGSEL_MSCWDATA (_DMA_CH_CTRL_SIGSEL_MSCWDATA << 0) /**< Shifted mode MSCWDATA for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1544 #define DMA_CH_CTRL_SIGSEL_AESDATAWR (_DMA_CH_CTRL_SIGSEL_AESDATAWR << 0) /**< Shifted mode AESDATAWR for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1545 #define DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV (_DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV << 0) /**< Shifted mode LESENSEBUFDATAV for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1546 #define DMA_CH_CTRL_SIGSEL_EBIPXL0EMPTY (_DMA_CH_CTRL_SIGSEL_EBIPXL0EMPTY << 0) /**< Shifted mode EBIPXL0EMPTY for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1547 #define DMA_CH_CTRL_SIGSEL_ADC0SCAN (_DMA_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1548 #define DMA_CH_CTRL_SIGSEL_DAC0CH1 (_DMA_CH_CTRL_SIGSEL_DAC0CH1 << 0) /**< Shifted mode DAC0CH1 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1549 #define DMA_CH_CTRL_SIGSEL_USART0TXBL (_DMA_CH_CTRL_SIGSEL_USART0TXBL << 0) /**< Shifted mode USART0TXBL for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1550 #define DMA_CH_CTRL_SIGSEL_USART1TXBL (_DMA_CH_CTRL_SIGSEL_USART1TXBL << 0) /**< Shifted mode USART1TXBL for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1551 #define DMA_CH_CTRL_SIGSEL_USART2TXBL (_DMA_CH_CTRL_SIGSEL_USART2TXBL << 0) /**< Shifted mode USART2TXBL for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1552 #define DMA_CH_CTRL_SIGSEL_LEUART0TXBL (_DMA_CH_CTRL_SIGSEL_LEUART0TXBL << 0) /**< Shifted mode LEUART0TXBL for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1553 #define DMA_CH_CTRL_SIGSEL_LEUART1TXBL (_DMA_CH_CTRL_SIGSEL_LEUART1TXBL << 0) /**< Shifted mode LEUART1TXBL for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1554 #define DMA_CH_CTRL_SIGSEL_I2C0TXBL (_DMA_CH_CTRL_SIGSEL_I2C0TXBL << 0) /**< Shifted mode I2C0TXBL for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1555 #define DMA_CH_CTRL_SIGSEL_I2C1TXBL (_DMA_CH_CTRL_SIGSEL_I2C1TXBL << 0) /**< Shifted mode I2C1TXBL for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1556 #define DMA_CH_CTRL_SIGSEL_TIMER0CC0 (_DMA_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1557 #define DMA_CH_CTRL_SIGSEL_TIMER1CC0 (_DMA_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1558 #define DMA_CH_CTRL_SIGSEL_TIMER2CC0 (_DMA_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1559 #define DMA_CH_CTRL_SIGSEL_TIMER3CC0 (_DMA_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1560 #define DMA_CH_CTRL_SIGSEL_UART0TXBL (_DMA_CH_CTRL_SIGSEL_UART0TXBL << 0) /**< Shifted mode UART0TXBL for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1561 #define DMA_CH_CTRL_SIGSEL_UART1TXBL (_DMA_CH_CTRL_SIGSEL_UART1TXBL << 0) /**< Shifted mode UART1TXBL for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1562 #define DMA_CH_CTRL_SIGSEL_AESXORDATAWR (_DMA_CH_CTRL_SIGSEL_AESXORDATAWR << 0) /**< Shifted mode AESXORDATAWR for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1563 #define DMA_CH_CTRL_SIGSEL_EBIPXL1EMPTY (_DMA_CH_CTRL_SIGSEL_EBIPXL1EMPTY << 0) /**< Shifted mode EBIPXL1EMPTY for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1564 #define DMA_CH_CTRL_SIGSEL_USART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART0TXEMPTY << 0) /**< Shifted mode USART0TXEMPTY for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1565 #define DMA_CH_CTRL_SIGSEL_USART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART1TXEMPTY << 0) /**< Shifted mode USART1TXEMPTY for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1566 #define DMA_CH_CTRL_SIGSEL_USART2TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART2TXEMPTY << 0) /**< Shifted mode USART2TXEMPTY for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1567 #define DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY << 0) /**< Shifted mode LEUART0TXEMPTY for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1568 #define DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY << 0) /**< Shifted mode LEUART1TXEMPTY for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1569 #define DMA_CH_CTRL_SIGSEL_TIMER0CC1 (_DMA_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1570 #define DMA_CH_CTRL_SIGSEL_TIMER1CC1 (_DMA_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1571 #define DMA_CH_CTRL_SIGSEL_TIMER2CC1 (_DMA_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1572 #define DMA_CH_CTRL_SIGSEL_TIMER3CC1 (_DMA_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1573 #define DMA_CH_CTRL_SIGSEL_UART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_UART0TXEMPTY << 0) /**< Shifted mode UART0TXEMPTY for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1574 #define DMA_CH_CTRL_SIGSEL_UART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_UART1TXEMPTY << 0) /**< Shifted mode UART1TXEMPTY for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1575 #define DMA_CH_CTRL_SIGSEL_AESDATARD (_DMA_CH_CTRL_SIGSEL_AESDATARD << 0) /**< Shifted mode AESDATARD for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1576 #define DMA_CH_CTRL_SIGSEL_EBIPXLFULL (_DMA_CH_CTRL_SIGSEL_EBIPXLFULL << 0) /**< Shifted mode EBIPXLFULL for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1577 #define DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT << 0) /**< Shifted mode USART1RXDATAVRIGHT for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1578 #define DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT << 0) /**< Shifted mode USART2RXDATAVRIGHT for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1579 #define DMA_CH_CTRL_SIGSEL_TIMER0CC2 (_DMA_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1580 #define DMA_CH_CTRL_SIGSEL_TIMER1CC2 (_DMA_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1581 #define DMA_CH_CTRL_SIGSEL_TIMER2CC2 (_DMA_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1582 #define DMA_CH_CTRL_SIGSEL_TIMER3CC2 (_DMA_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1583 #define DMA_CH_CTRL_SIGSEL_AESKEYWR (_DMA_CH_CTRL_SIGSEL_AESKEYWR << 0) /**< Shifted mode AESKEYWR for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1584 #define DMA_CH_CTRL_SIGSEL_EBIDDEMPTY (_DMA_CH_CTRL_SIGSEL_EBIDDEMPTY << 0) /**< Shifted mode EBIDDEMPTY for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1585 #define DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT << 0) /**< Shifted mode USART1TXBLRIGHT for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1586 #define DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT << 0) /**< Shifted mode USART2TXBLRIGHT for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1587 #define _DMA_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for DMA_SOURCESEL */
<> 150:02e0a0aed4ec 1588 #define _DMA_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for DMA_SOURCESEL */
<> 150:02e0a0aed4ec 1589 #define _DMA_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1590 #define _DMA_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1591 #define _DMA_CH_CTRL_SOURCESEL_DAC0 0x0000000AUL /**< Mode DAC0 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1592 #define _DMA_CH_CTRL_SOURCESEL_USART0 0x0000000CUL /**< Mode USART0 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1593 #define _DMA_CH_CTRL_SOURCESEL_USART1 0x0000000DUL /**< Mode USART1 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1594 #define _DMA_CH_CTRL_SOURCESEL_USART2 0x0000000EUL /**< Mode USART2 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1595 #define _DMA_CH_CTRL_SOURCESEL_LEUART0 0x00000010UL /**< Mode LEUART0 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1596 #define _DMA_CH_CTRL_SOURCESEL_LEUART1 0x00000011UL /**< Mode LEUART1 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1597 #define _DMA_CH_CTRL_SOURCESEL_I2C0 0x00000014UL /**< Mode I2C0 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1598 #define _DMA_CH_CTRL_SOURCESEL_I2C1 0x00000015UL /**< Mode I2C1 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1599 #define _DMA_CH_CTRL_SOURCESEL_TIMER0 0x00000018UL /**< Mode TIMER0 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1600 #define _DMA_CH_CTRL_SOURCESEL_TIMER1 0x00000019UL /**< Mode TIMER1 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1601 #define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL /**< Mode TIMER2 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1602 #define _DMA_CH_CTRL_SOURCESEL_TIMER3 0x0000001BUL /**< Mode TIMER3 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1603 #define _DMA_CH_CTRL_SOURCESEL_UART0 0x0000002CUL /**< Mode UART0 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1604 #define _DMA_CH_CTRL_SOURCESEL_UART1 0x0000002DUL /**< Mode UART1 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1605 #define _DMA_CH_CTRL_SOURCESEL_MSC 0x00000030UL /**< Mode MSC for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1606 #define _DMA_CH_CTRL_SOURCESEL_AES 0x00000031UL /**< Mode AES for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1607 #define _DMA_CH_CTRL_SOURCESEL_LESENSE 0x00000032UL /**< Mode LESENSE for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1608 #define _DMA_CH_CTRL_SOURCESEL_EBI 0x00000033UL /**< Mode EBI for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1609 #define DMA_CH_CTRL_SOURCESEL_NONE (_DMA_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1610 #define DMA_CH_CTRL_SOURCESEL_ADC0 (_DMA_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1611 #define DMA_CH_CTRL_SOURCESEL_DAC0 (_DMA_CH_CTRL_SOURCESEL_DAC0 << 16) /**< Shifted mode DAC0 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1612 #define DMA_CH_CTRL_SOURCESEL_USART0 (_DMA_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1613 #define DMA_CH_CTRL_SOURCESEL_USART1 (_DMA_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1614 #define DMA_CH_CTRL_SOURCESEL_USART2 (_DMA_CH_CTRL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1615 #define DMA_CH_CTRL_SOURCESEL_LEUART0 (_DMA_CH_CTRL_SOURCESEL_LEUART0 << 16) /**< Shifted mode LEUART0 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1616 #define DMA_CH_CTRL_SOURCESEL_LEUART1 (_DMA_CH_CTRL_SOURCESEL_LEUART1 << 16) /**< Shifted mode LEUART1 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1617 #define DMA_CH_CTRL_SOURCESEL_I2C0 (_DMA_CH_CTRL_SOURCESEL_I2C0 << 16) /**< Shifted mode I2C0 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1618 #define DMA_CH_CTRL_SOURCESEL_I2C1 (_DMA_CH_CTRL_SOURCESEL_I2C1 << 16) /**< Shifted mode I2C1 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1619 #define DMA_CH_CTRL_SOURCESEL_TIMER0 (_DMA_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1620 #define DMA_CH_CTRL_SOURCESEL_TIMER1 (_DMA_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1621 #define DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1622 #define DMA_CH_CTRL_SOURCESEL_TIMER3 (_DMA_CH_CTRL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1623 #define DMA_CH_CTRL_SOURCESEL_UART0 (_DMA_CH_CTRL_SOURCESEL_UART0 << 16) /**< Shifted mode UART0 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1624 #define DMA_CH_CTRL_SOURCESEL_UART1 (_DMA_CH_CTRL_SOURCESEL_UART1 << 16) /**< Shifted mode UART1 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1625 #define DMA_CH_CTRL_SOURCESEL_MSC (_DMA_CH_CTRL_SOURCESEL_MSC << 16) /**< Shifted mode MSC for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1626 #define DMA_CH_CTRL_SOURCESEL_AES (_DMA_CH_CTRL_SOURCESEL_AES << 16) /**< Shifted mode AES for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1627 #define DMA_CH_CTRL_SOURCESEL_LESENSE (_DMA_CH_CTRL_SOURCESEL_LESENSE << 16) /**< Shifted mode LESENSE for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1628 #define DMA_CH_CTRL_SOURCESEL_EBI (_DMA_CH_CTRL_SOURCESEL_EBI << 16) /**< Shifted mode EBI for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1629
<> 150:02e0a0aed4ec 1630 /** @} End of group EFM32WG_DMA */
<> 150:02e0a0aed4ec 1631 /** @} End of group Parts */
<> 150:02e0a0aed4ec 1632