Fawwaz Nadzmy / mbed-STM

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_devinfo.h@153:9398a535854b, 2016-12-22 (annotated)

Committer:
fwndz
Date:
Thu Dec 22 05:12:40 2016 +0000
Revision:
153:9398a535854b
Parent:
150:02e0a0aed4ec 
device target maximize

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 150:02e0a0aed4ec 1 /**************************************************************************//**
<> 150:02e0a0aed4ec 2 * @file efm32wg_devinfo.h
<> 150:02e0a0aed4ec 3 * @brief EFM32WG_DEVINFO register and bit field definitions
<> 150:02e0a0aed4ec 4 * @version 5.0.0
<> 150:02e0a0aed4ec 5 ******************************************************************************
<> 150:02e0a0aed4ec 6 * @section License
<> 150:02e0a0aed4ec 7 * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 150:02e0a0aed4ec 8 ******************************************************************************
<> 150:02e0a0aed4ec 9 *
<> 150:02e0a0aed4ec 10 * Permission is granted to anyone to use this software for any purpose,
<> 150:02e0a0aed4ec 11 * including commercial applications, and to alter it and redistribute it
<> 150:02e0a0aed4ec 12 * freely, subject to the following restrictions:
<> 150:02e0a0aed4ec 13 *
<> 150:02e0a0aed4ec 14 * 1. The origin of this software must not be misrepresented; you must not
<> 150:02e0a0aed4ec 15 * claim that you wrote the original software.@n
<> 150:02e0a0aed4ec 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 150:02e0a0aed4ec 17 * misrepresented as being the original software.@n
<> 150:02e0a0aed4ec 18 * 3. This notice may not be removed or altered from any source distribution.
<> 150:02e0a0aed4ec 19 *
<> 150:02e0a0aed4ec 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 150:02e0a0aed4ec 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 150:02e0a0aed4ec 22 * providing the Software "AS IS", with no express or implied warranties of any
<> 150:02e0a0aed4ec 23 * kind, including, but not limited to, any implied warranties of
<> 150:02e0a0aed4ec 24 * merchantability or fitness for any particular purpose or warranties against
<> 150:02e0a0aed4ec 25 * infringement of any proprietary rights of a third party.
<> 150:02e0a0aed4ec 26 *
<> 150:02e0a0aed4ec 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 150:02e0a0aed4ec 28 * incidental, or special damages, or any other relief, or for any claim by
<> 150:02e0a0aed4ec 29 * any third party, arising from your use of this Software.
<> 150:02e0a0aed4ec 30 *
<> 150:02e0a0aed4ec 31 *****************************************************************************/
<> 150:02e0a0aed4ec 32 /**************************************************************************//**
<> 150:02e0a0aed4ec 33 * @addtogroup Parts
<> 150:02e0a0aed4ec 34 * @{
<> 150:02e0a0aed4ec 35 ******************************************************************************/
<> 150:02e0a0aed4ec 36 /**************************************************************************//**
<> 150:02e0a0aed4ec 37 * @defgroup EFM32WG_DEVINFO
<> 150:02e0a0aed4ec 38 * @{
<> 150:02e0a0aed4ec 39 *****************************************************************************/
<> 150:02e0a0aed4ec 40 typedef struct
<> 150:02e0a0aed4ec 41 {
<> 150:02e0a0aed4ec 42 __IM uint32_t CAL; /**< Calibration temperature and checksum */
<> 150:02e0a0aed4ec 43 __IM uint32_t ADC0CAL0; /**< ADC0 Calibration register 0 */
<> 150:02e0a0aed4ec 44 __IM uint32_t ADC0CAL1; /**< ADC0 Calibration register 1 */
<> 150:02e0a0aed4ec 45 __IM uint32_t ADC0CAL2; /**< ADC0 Calibration register 2 */
<> 150:02e0a0aed4ec 46 uint32_t RESERVED0[2]; /**< Reserved */
<> 150:02e0a0aed4ec 47 __IM uint32_t DAC0CAL0; /**< DAC calibrartion register 0 */
<> 150:02e0a0aed4ec 48 __IM uint32_t DAC0CAL1; /**< DAC calibrartion register 1 */
<> 150:02e0a0aed4ec 49 __IM uint32_t DAC0CAL2; /**< DAC calibrartion register 2 */
<> 150:02e0a0aed4ec 50 __IM uint32_t AUXHFRCOCAL0; /**< AUXHFRCO calibration register 0 */
<> 150:02e0a0aed4ec 51 __IM uint32_t AUXHFRCOCAL1; /**< AUXHFRCO calibration register 1 */
<> 150:02e0a0aed4ec 52 __IM uint32_t HFRCOCAL0; /**< HFRCO calibration register 0 */
<> 150:02e0a0aed4ec 53 __IM uint32_t HFRCOCAL1; /**< HFRCO calibration register 1 */
<> 150:02e0a0aed4ec 54 __IM uint32_t MEMINFO; /**< Memory information */
<> 150:02e0a0aed4ec 55 uint32_t RESERVED2[2]; /**< Reserved */
<> 150:02e0a0aed4ec 56 __IM uint32_t UNIQUEL; /**< Low 32 bits of device unique number */
<> 150:02e0a0aed4ec 57 __IM uint32_t UNIQUEH; /**< High 32 bits of device unique number */
<> 150:02e0a0aed4ec 58 __IM uint32_t MSIZE; /**< Flash and SRAM Memory size in KiloBytes */
<> 150:02e0a0aed4ec 59 __IM uint32_t PART; /**< Part description */
<> 150:02e0a0aed4ec 60 } DEVINFO_TypeDef; /** @} */
<> 150:02e0a0aed4ec 61
<> 150:02e0a0aed4ec 62 /**************************************************************************//**
<> 150:02e0a0aed4ec 63 * @defgroup EFM32WG_DEVINFO_BitFields
<> 150:02e0a0aed4ec 64 * @{
<> 150:02e0a0aed4ec 65 *****************************************************************************/
<> 150:02e0a0aed4ec 66 /* Bit fields for EFM32WG_DEVINFO */
<> 150:02e0a0aed4ec 67 #define _DEVINFO_CAL_CRC_MASK 0x0000FFFFUL /**< Integrity CRC checksum mask */
<> 150:02e0a0aed4ec 68 #define _DEVINFO_CAL_CRC_SHIFT 0 /**< Integrity CRC checksum shift */
<> 150:02e0a0aed4ec 69 #define _DEVINFO_CAL_TEMP_MASK 0x00FF0000UL /**< Calibration temperature, DegC, mask */
<> 150:02e0a0aed4ec 70 #define _DEVINFO_CAL_TEMP_SHIFT 16 /**< Calibration temperature shift */
<> 150:02e0a0aed4ec 71 #define _DEVINFO_ADC0CAL0_1V25_GAIN_MASK 0x00007F00UL /**< Gain for 1V25 reference, mask */
<> 150:02e0a0aed4ec 72 #define _DEVINFO_ADC0CAL0_1V25_GAIN_SHIFT 8 /**< Gain for 1V25 reference, shift */
<> 150:02e0a0aed4ec 73 #define _DEVINFO_ADC0CAL0_1V25_OFFSET_MASK 0x0000007FUL /**< Offset for 1V25 reference, mask */
<> 150:02e0a0aed4ec 74 #define _DEVINFO_ADC0CAL0_1V25_OFFSET_SHIFT 0 /**< Offset for 1V25 reference, shift */
<> 150:02e0a0aed4ec 75 #define _DEVINFO_ADC0CAL0_2V5_GAIN_MASK 0x7F000000UL /**< Gain for 2V5 reference, mask */
<> 150:02e0a0aed4ec 76 #define _DEVINFO_ADC0CAL0_2V5_GAIN_SHIFT 24 /**< Gain for 2V5 reference, shift */
<> 150:02e0a0aed4ec 77 #define _DEVINFO_ADC0CAL0_2V5_OFFSET_MASK 0x007F0000UL /**< Offset for 2V5 reference, mask */
<> 150:02e0a0aed4ec 78 #define _DEVINFO_ADC0CAL0_2V5_OFFSET_SHIFT 16 /**< Offset for 2V5 reference, shift */
<> 150:02e0a0aed4ec 79 #define _DEVINFO_ADC0CAL1_VDD_GAIN_MASK 0x00007F00UL /**< Gain for VDD reference, mask */
<> 150:02e0a0aed4ec 80 #define _DEVINFO_ADC0CAL1_VDD_GAIN_SHIFT 8 /**< Gain for VDD reference, shift */
<> 150:02e0a0aed4ec 81 #define _DEVINFO_ADC0CAL1_VDD_OFFSET_MASK 0x0000007FUL /**< Offset for VDD reference, mask */
<> 150:02e0a0aed4ec 82 #define _DEVINFO_ADC0CAL1_VDD_OFFSET_SHIFT 0 /**< Offset for VDD reference, shift */
<> 150:02e0a0aed4ec 83 #define _DEVINFO_ADC0CAL1_5VDIFF_GAIN_MASK 0x7F000000UL /**< Gain 5VDIFF for 5VDIFF reference, mask */
<> 150:02e0a0aed4ec 84 #define _DEVINFO_ADC0CAL1_5VDIFF_GAIN_SHIFT 24 /**< Gain for 5VDIFF reference, mask */
<> 150:02e0a0aed4ec 85 #define _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_MASK 0x007F0000UL /**< Offset for 5VDIFF reference, mask */
<> 150:02e0a0aed4ec 86 #define _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_SHIFT 16 /**< Offset for 5VDIFF reference, shift */
<> 150:02e0a0aed4ec 87 #define _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_MASK 0x0000007FUL /**< Offset for 2XVDDVSS reference, mask */
<> 150:02e0a0aed4ec 88 #define _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_SHIFT 0 /**< Offset for 2XVDDVSS reference, shift */
<> 150:02e0a0aed4ec 89 #define _DEVINFO_ADC0CAL2_TEMP1V25_MASK 0xFFF00000UL /**< Temperature reading at 1V25 reference, mask */
<> 150:02e0a0aed4ec 90 #define _DEVINFO_ADC0CAL2_TEMP1V25_SHIFT 20 /**< Temperature reading at 1V25 reference, DegC */
<> 150:02e0a0aed4ec 91 #define _DEVINFO_DAC0CAL0_1V25_GAIN_MASK 0x007F0000UL /**< Gain for 1V25 reference, mask */
<> 150:02e0a0aed4ec 92 #define _DEVINFO_DAC0CAL0_1V25_GAIN_SHIFT 16 /**< Gain for 1V25 reference, shift */
<> 150:02e0a0aed4ec 93 #define _DEVINFO_DAC0CAL0_1V25_CH1_OFFSET_MASK 0x00003F00UL /**< Channel 1 offset for 1V25 reference, mask */
<> 150:02e0a0aed4ec 94 #define _DEVINFO_DAC0CAL0_1V25_CH1_OFFSET_SHIFT 8 /**< Channel 1 offset for 1V25 reference, shift */
<> 150:02e0a0aed4ec 95 #define _DEVINFO_DAC0CAL0_1V25_CH0_OFFSET_MASK 0x0000003FUL /**< Channel 0 offset for 1V25 reference, mask */
<> 150:02e0a0aed4ec 96 #define _DEVINFO_DAC0CAL0_1V25_CH0_OFFSET_SHIFT 0 /**< Channel 0 offset for 1V25 reference, shift */
<> 150:02e0a0aed4ec 97 #define _DEVINFO_DAC0CAL1_2V5_GAIN_MASK 0x007F0000UL /**< Gain for 2V5 reference, mask */
<> 150:02e0a0aed4ec 98 #define _DEVINFO_DAC0CAL1_2V5_GAIN_SHIFT 16 /**< Gain for 2V5 reference, shift */
<> 150:02e0a0aed4ec 99 #define _DEVINFO_DAC0CAL1_2V5_CH1_OFFSET_MASK 0x00003F00UL /**< Channel 1 offset for 2V5 reference, mask */
<> 150:02e0a0aed4ec 100 #define _DEVINFO_DAC0CAL1_2V5_CH1_OFFSET_SHIFT 8 /**< Channel 1 offset for 2V5 reference, shift */
<> 150:02e0a0aed4ec 101 #define _DEVINFO_DAC0CAL1_2V5_CH0_OFFSET_MASK 0x0000003FUL /**< Channel 0 offset for 2V5 reference, mask */
<> 150:02e0a0aed4ec 102 #define _DEVINFO_DAC0CAL1_2V5_CH0_OFFSET_SHIFT 0 /**< Channel 0 offset for 2V5 reference, shift */
<> 150:02e0a0aed4ec 103 #define _DEVINFO_DAC0CAL2_VDD_GAIN_MASK 0x007F0000UL /**< Gain for VDD reference, mask */
<> 150:02e0a0aed4ec 104 #define _DEVINFO_DAC0CAL2_VDD_GAIN_SHIFT 16 /**< Gain for VDD reference, shift */
<> 150:02e0a0aed4ec 105 #define _DEVINFO_DAC0CAL2_VDD_CH1_OFFSET_MASK 0x00003F00UL /**< Channel 1 offset for VDD reference, mask */
<> 150:02e0a0aed4ec 106 #define _DEVINFO_DAC0CAL2_VDD_CH1_OFFSET_SHIFT 8 /**< Channel 1 offset for VDD reference, shift */
<> 150:02e0a0aed4ec 107 #define _DEVINFO_DAC0CAL2_VDD_CH0_OFFSET_MASK 0x0000003FUL /**< Channel 0 offset for VDD reference, mask */
<> 150:02e0a0aed4ec 108 #define _DEVINFO_DAC0CAL2_VDD_CH0_OFFSET_SHIFT 0 /**< Channel 0 offset for VDD reference, shift*/
<> 150:02e0a0aed4ec 109 #define _DEVINFO_AUXHFRCOCAL0_BAND1_MASK 0x000000FFUL /**< 1MHz tuning value for AUXHFRCO, mask */
<> 150:02e0a0aed4ec 110 #define _DEVINFO_AUXHFRCOCAL0_BAND1_SHIFT 0 /**< 1MHz tuning value for AUXHFRCO, shift */
<> 150:02e0a0aed4ec 111 #define _DEVINFO_AUXHFRCOCAL0_BAND7_MASK 0x0000FF00UL /**< 7MHz tuning value for AUXHFRCO, mask */
<> 150:02e0a0aed4ec 112 #define _DEVINFO_AUXHFRCOCAL0_BAND7_SHIFT 8 /**< 7MHz tuning value for AUXHFRCO, shift */
<> 150:02e0a0aed4ec 113 #define _DEVINFO_AUXHFRCOCAL0_BAND11_MASK 0x00FF0000UL /**< 11MHz tuning value for AUXHFRCO, mask */
<> 150:02e0a0aed4ec 114 #define _DEVINFO_AUXHFRCOCAL0_BAND11_SHIFT 16 /**< 11MHz tuning value for AUXHFRCO, shift */
<> 150:02e0a0aed4ec 115 #define _DEVINFO_AUXHFRCOCAL0_BAND14_MASK 0xFF000000UL /**< 14MHz tuning value for AUXHFRCO, mask */
<> 150:02e0a0aed4ec 116 #define _DEVINFO_AUXHFRCOCAL0_BAND14_SHIFT 24 /**< 14MHz tuning value for AUXHFRCO, shift */
<> 150:02e0a0aed4ec 117 #define _DEVINFO_AUXHFRCOCAL1_BAND21_MASK 0x000000FFUL /**< 21MHz tuning value for AUXHFRCO, mask */
<> 150:02e0a0aed4ec 118 #define _DEVINFO_AUXHFRCOCAL1_BAND21_SHIFT 0 /**< 21MHz tuning value for AUXHFRCO, shift */
<> 150:02e0a0aed4ec 119 #define _DEVINFO_AUXHFRCOCAL1_BAND28_MASK 0x0000FF00UL /**< 28MHz tuning value for AUXHFRCO, shift */
<> 150:02e0a0aed4ec 120 #define _DEVINFO_AUXHFRCOCAL1_BAND28_SHIFT 8 /**< 28MHz tuning value for AUXHFRCO, mask */
<> 150:02e0a0aed4ec 121 #define _DEVINFO_HFRCOCAL0_BAND1_MASK 0x000000FFUL /**< 1MHz tuning value for HFRCO, mask */
<> 150:02e0a0aed4ec 122 #define _DEVINFO_HFRCOCAL0_BAND1_SHIFT 0 /**< 1MHz tuning value for HFRCO, shift */
<> 150:02e0a0aed4ec 123 #define _DEVINFO_HFRCOCAL0_BAND7_MASK 0x0000FF00UL /**< 7MHz tuning value for HFRCO, mask */
<> 150:02e0a0aed4ec 124 #define _DEVINFO_HFRCOCAL0_BAND7_SHIFT 8 /**< 7MHz tuning value for HFRCO, shift */
<> 150:02e0a0aed4ec 125 #define _DEVINFO_HFRCOCAL0_BAND11_MASK 0x00FF0000UL /**< 11MHz tuning value for HFRCO, mask */
<> 150:02e0a0aed4ec 126 #define _DEVINFO_HFRCOCAL0_BAND11_SHIFT 16 /**< 11MHz tuning value for HFRCO, shift */
<> 150:02e0a0aed4ec 127 #define _DEVINFO_HFRCOCAL0_BAND14_MASK 0xFF000000UL /**< 14MHz tuning value for HFRCO, mask */
<> 150:02e0a0aed4ec 128 #define _DEVINFO_HFRCOCAL0_BAND14_SHIFT 24 /**< 14MHz tuning value for HFRCO, shift */
<> 150:02e0a0aed4ec 129 #define _DEVINFO_HFRCOCAL1_BAND21_MASK 0x000000FFUL /**< 21MHz tuning value for HFRCO, mask */
<> 150:02e0a0aed4ec 130 #define _DEVINFO_HFRCOCAL1_BAND21_SHIFT 0 /**< 21MHz tuning value for HFRCO, shift */
<> 150:02e0a0aed4ec 131 #define _DEVINFO_HFRCOCAL1_BAND28_MASK 0x0000FF00UL /**< 28MHz tuning value for HFRCO, shift */
<> 150:02e0a0aed4ec 132 #define _DEVINFO_HFRCOCAL1_BAND28_SHIFT 8 /**< 28MHz tuning value for HFRCO, mask */
<> 150:02e0a0aed4ec 133 #define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK 0xFF000000UL /**< Flash page size (refer to ref.man for encoding) mask */
<> 150:02e0a0aed4ec 134 #define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT 24 /**< Flash page size shift */
<> 150:02e0a0aed4ec 135 #define _DEVINFO_UNIQUEL_MASK 0xFFFFFFFFUL /**< Lower part of 64-bit device unique number */
<> 150:02e0a0aed4ec 136 #define _DEVINFO_UNIQUEL_SHIFT 0 /**< Unique Low 32-bit shift */
<> 150:02e0a0aed4ec 137 #define _DEVINFO_UNIQUEH_MASK 0xFFFFFFFFUL /**< High part of 64-bit device unique number */
<> 150:02e0a0aed4ec 138 #define _DEVINFO_UNIQUEH_SHIFT 0 /**< Unique High 32-bit shift */
<> 150:02e0a0aed4ec 139 #define _DEVINFO_MSIZE_SRAM_MASK 0xFFFF0000UL /**< Flash size in kilobytes */
<> 150:02e0a0aed4ec 140 #define _DEVINFO_MSIZE_SRAM_SHIFT 16 /**< Bit position for flash size */
<> 150:02e0a0aed4ec 141 #define _DEVINFO_MSIZE_FLASH_MASK 0x0000FFFFUL /**< SRAM size in kilobytes */
<> 150:02e0a0aed4ec 142 #define _DEVINFO_MSIZE_FLASH_SHIFT 0 /**< Bit position for SRAM size */
<> 150:02e0a0aed4ec 143 #define _DEVINFO_PART_PROD_REV_MASK 0xFF000000UL /**< Production revision */
<> 150:02e0a0aed4ec 144 #define _DEVINFO_PART_PROD_REV_SHIFT 24 /**< Bit position for production revision */
<> 150:02e0a0aed4ec 145 #define _DEVINFO_PART_DEVICE_FAMILY_MASK 0x00FF0000UL /**< Device Family, 0x47 for Gecko */
<> 150:02e0a0aed4ec 146 #define _DEVINFO_PART_DEVICE_FAMILY_SHIFT 16 /**< Bit position for device family */
<> 150:02e0a0aed4ec 147 /* Legacy family #defines */
<> 150:02e0a0aed4ec 148 #define _DEVINFO_PART_DEVICE_FAMILY_G 71 /**< Gecko Device Family */
<> 150:02e0a0aed4ec 149 #define _DEVINFO_PART_DEVICE_FAMILY_GG 72 /**< Giant Gecko Device Family */
<> 150:02e0a0aed4ec 150 #define _DEVINFO_PART_DEVICE_FAMILY_TG 73 /**< Tiny Gecko Device Family */
<> 150:02e0a0aed4ec 151 #define _DEVINFO_PART_DEVICE_FAMILY_LG 74 /**< Leopard Gecko Device Family */
<> 150:02e0a0aed4ec 152 #define _DEVINFO_PART_DEVICE_FAMILY_WG 75 /**< Wonder Gecko Device Family */
<> 150:02e0a0aed4ec 153 #define _DEVINFO_PART_DEVICE_FAMILY_ZG 76 /**< Zero Gecko Device Family */
<> 150:02e0a0aed4ec 154 #define _DEVINFO_PART_DEVICE_FAMILY_HG 77 /**< Happy Gecko Device Family */
<> 150:02e0a0aed4ec 155 /* New style family #defines */
<> 150:02e0a0aed4ec 156 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32G 71 /**< Gecko Device Family */
<> 150:02e0a0aed4ec 157 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG 72 /**< Giant Gecko Device Family */
<> 150:02e0a0aed4ec 158 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG 73 /**< Tiny Gecko Device Family */
<> 150:02e0a0aed4ec 159 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32LG 74 /**< Leopard Gecko Device Family */
<> 150:02e0a0aed4ec 160 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32WG 75 /**< Wonder Gecko Device Family */
<> 150:02e0a0aed4ec 161 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG 76 /**< Zero Gecko Device Family */
<> 150:02e0a0aed4ec 162 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32HG 77 /**< Happy Gecko Device Family */
<> 150:02e0a0aed4ec 163 #define _DEVINFO_PART_DEVICE_FAMILY_EZR32WG 120 /**< EZR Wonder Gecko Device Family */
<> 150:02e0a0aed4ec 164 #define _DEVINFO_PART_DEVICE_FAMILY_EZR32LG 121 /**< EZR Leopard Gecko Device Family */
<> 150:02e0a0aed4ec 165 #define _DEVINFO_PART_DEVICE_FAMILY_EZR32HG 122 /**< EZR Happy Gecko Device Family */
<> 150:02e0a0aed4ec 166 #define _DEVINFO_PART_DEVICE_NUMBER_MASK 0x0000FFFFUL /**< Device number */
<> 150:02e0a0aed4ec 167 #define _DEVINFO_PART_DEVICE_NUMBER_SHIFT 0 /**< Bit position for device number */
<> 150:02e0a0aed4ec 168
<> 150:02e0a0aed4ec 169 /** @} End of group EFM32WG_DEVINFO */
<> 150:02e0a0aed4ec 170 /** @} End of group Parts */
<> 150:02e0a0aed4ec 171