Fawwaz Nadzmy / mbed-STM

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_dac.h@153:9398a535854b, 2016-12-22 (annotated)

Committer:
fwndz
Date:
Thu Dec 22 05:12:40 2016 +0000
Revision:
153:9398a535854b
Parent:
150:02e0a0aed4ec 
device target maximize

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 150:02e0a0aed4ec 1 /**************************************************************************//**
<> 150:02e0a0aed4ec 2 * @file efm32wg_dac.h
<> 150:02e0a0aed4ec 3 * @brief EFM32WG_DAC register and bit field definitions
<> 150:02e0a0aed4ec 4 * @version 5.0.0
<> 150:02e0a0aed4ec 5 ******************************************************************************
<> 150:02e0a0aed4ec 6 * @section License
<> 150:02e0a0aed4ec 7 * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 150:02e0a0aed4ec 8 ******************************************************************************
<> 150:02e0a0aed4ec 9 *
<> 150:02e0a0aed4ec 10 * Permission is granted to anyone to use this software for any purpose,
<> 150:02e0a0aed4ec 11 * including commercial applications, and to alter it and redistribute it
<> 150:02e0a0aed4ec 12 * freely, subject to the following restrictions:
<> 150:02e0a0aed4ec 13 *
<> 150:02e0a0aed4ec 14 * 1. The origin of this software must not be misrepresented; you must not
<> 150:02e0a0aed4ec 15 * claim that you wrote the original software.@n
<> 150:02e0a0aed4ec 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 150:02e0a0aed4ec 17 * misrepresented as being the original software.@n
<> 150:02e0a0aed4ec 18 * 3. This notice may not be removed or altered from any source distribution.
<> 150:02e0a0aed4ec 19 *
<> 150:02e0a0aed4ec 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 150:02e0a0aed4ec 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 150:02e0a0aed4ec 22 * providing the Software "AS IS", with no express or implied warranties of any
<> 150:02e0a0aed4ec 23 * kind, including, but not limited to, any implied warranties of
<> 150:02e0a0aed4ec 24 * merchantability or fitness for any particular purpose or warranties against
<> 150:02e0a0aed4ec 25 * infringement of any proprietary rights of a third party.
<> 150:02e0a0aed4ec 26 *
<> 150:02e0a0aed4ec 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 150:02e0a0aed4ec 28 * incidental, or special damages, or any other relief, or for any claim by
<> 150:02e0a0aed4ec 29 * any third party, arising from your use of this Software.
<> 150:02e0a0aed4ec 30 *
<> 150:02e0a0aed4ec 31 *****************************************************************************/
<> 150:02e0a0aed4ec 32 /**************************************************************************//**
<> 150:02e0a0aed4ec 33 * @addtogroup Parts
<> 150:02e0a0aed4ec 34 * @{
<> 150:02e0a0aed4ec 35 ******************************************************************************/
<> 150:02e0a0aed4ec 36 /**************************************************************************//**
<> 150:02e0a0aed4ec 37 * @defgroup EFM32WG_DAC
<> 150:02e0a0aed4ec 38 * @{
<> 150:02e0a0aed4ec 39 * @brief EFM32WG_DAC Register Declaration
<> 150:02e0a0aed4ec 40 *****************************************************************************/
<> 150:02e0a0aed4ec 41 typedef struct
<> 150:02e0a0aed4ec 42 {
<> 150:02e0a0aed4ec 43 __IOM uint32_t CTRL; /**< Control Register */
<> 150:02e0a0aed4ec 44 __IM uint32_t STATUS; /**< Status Register */
<> 150:02e0a0aed4ec 45 __IOM uint32_t CH0CTRL; /**< Channel 0 Control Register */
<> 150:02e0a0aed4ec 46 __IOM uint32_t CH1CTRL; /**< Channel 1 Control Register */
<> 150:02e0a0aed4ec 47 __IOM uint32_t IEN; /**< Interrupt Enable Register */
<> 150:02e0a0aed4ec 48 __IM uint32_t IF; /**< Interrupt Flag Register */
<> 150:02e0a0aed4ec 49 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
<> 150:02e0a0aed4ec 50 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
<> 150:02e0a0aed4ec 51 __IOM uint32_t CH0DATA; /**< Channel 0 Data Register */
<> 150:02e0a0aed4ec 52 __IOM uint32_t CH1DATA; /**< Channel 1 Data Register */
<> 150:02e0a0aed4ec 53 __IOM uint32_t COMBDATA; /**< Combined Data Register */
<> 150:02e0a0aed4ec 54 __IOM uint32_t CAL; /**< Calibration Register */
<> 150:02e0a0aed4ec 55 __IOM uint32_t BIASPROG; /**< Bias Programming Register */
<> 150:02e0a0aed4ec 56 uint32_t RESERVED0[8]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 57 __IOM uint32_t OPACTRL; /**< Operational Amplifier Control Register */
<> 150:02e0a0aed4ec 58 __IOM uint32_t OPAOFFSET; /**< Operational Amplifier Offset Register */
<> 150:02e0a0aed4ec 59 __IOM uint32_t OPA0MUX; /**< Operational Amplifier Mux Configuration Register */
<> 150:02e0a0aed4ec 60 __IOM uint32_t OPA1MUX; /**< Operational Amplifier Mux Configuration Register */
<> 150:02e0a0aed4ec 61 __IOM uint32_t OPA2MUX; /**< Operational Amplifier Mux Configuration Register */
<> 150:02e0a0aed4ec 62 } DAC_TypeDef; /** @} */
<> 150:02e0a0aed4ec 63
<> 150:02e0a0aed4ec 64 /**************************************************************************//**
<> 150:02e0a0aed4ec 65 * @defgroup EFM32WG_DAC_BitFields
<> 150:02e0a0aed4ec 66 * @{
<> 150:02e0a0aed4ec 67 *****************************************************************************/
<> 150:02e0a0aed4ec 68
<> 150:02e0a0aed4ec 69 /* Bit fields for DAC CTRL */
<> 150:02e0a0aed4ec 70 #define _DAC_CTRL_RESETVALUE 0x00000010UL /**< Default value for DAC_CTRL */
<> 150:02e0a0aed4ec 71 #define _DAC_CTRL_MASK 0x003703FFUL /**< Mask for DAC_CTRL */
<> 150:02e0a0aed4ec 72 #define DAC_CTRL_DIFF (0x1UL << 0) /**< Differential Mode */
<> 150:02e0a0aed4ec 73 #define _DAC_CTRL_DIFF_SHIFT 0 /**< Shift value for DAC_DIFF */
<> 150:02e0a0aed4ec 74 #define _DAC_CTRL_DIFF_MASK 0x1UL /**< Bit mask for DAC_DIFF */
<> 150:02e0a0aed4ec 75 #define _DAC_CTRL_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */
<> 150:02e0a0aed4ec 76 #define DAC_CTRL_DIFF_DEFAULT (_DAC_CTRL_DIFF_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_CTRL */
<> 150:02e0a0aed4ec 77 #define DAC_CTRL_SINEMODE (0x1UL << 1) /**< Sine Mode */
<> 150:02e0a0aed4ec 78 #define _DAC_CTRL_SINEMODE_SHIFT 1 /**< Shift value for DAC_SINEMODE */
<> 150:02e0a0aed4ec 79 #define _DAC_CTRL_SINEMODE_MASK 0x2UL /**< Bit mask for DAC_SINEMODE */
<> 150:02e0a0aed4ec 80 #define _DAC_CTRL_SINEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */
<> 150:02e0a0aed4ec 81 #define DAC_CTRL_SINEMODE_DEFAULT (_DAC_CTRL_SINEMODE_DEFAULT << 1) /**< Shifted mode DEFAULT for DAC_CTRL */
<> 150:02e0a0aed4ec 82 #define _DAC_CTRL_CONVMODE_SHIFT 2 /**< Shift value for DAC_CONVMODE */
<> 150:02e0a0aed4ec 83 #define _DAC_CTRL_CONVMODE_MASK 0xCUL /**< Bit mask for DAC_CONVMODE */
<> 150:02e0a0aed4ec 84 #define _DAC_CTRL_CONVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */
<> 150:02e0a0aed4ec 85 #define _DAC_CTRL_CONVMODE_CONTINUOUS 0x00000000UL /**< Mode CONTINUOUS for DAC_CTRL */
<> 150:02e0a0aed4ec 86 #define _DAC_CTRL_CONVMODE_SAMPLEHOLD 0x00000001UL /**< Mode SAMPLEHOLD for DAC_CTRL */
<> 150:02e0a0aed4ec 87 #define _DAC_CTRL_CONVMODE_SAMPLEOFF 0x00000002UL /**< Mode SAMPLEOFF for DAC_CTRL */
<> 150:02e0a0aed4ec 88 #define DAC_CTRL_CONVMODE_DEFAULT (_DAC_CTRL_CONVMODE_DEFAULT << 2) /**< Shifted mode DEFAULT for DAC_CTRL */
<> 150:02e0a0aed4ec 89 #define DAC_CTRL_CONVMODE_CONTINUOUS (_DAC_CTRL_CONVMODE_CONTINUOUS << 2) /**< Shifted mode CONTINUOUS for DAC_CTRL */
<> 150:02e0a0aed4ec 90 #define DAC_CTRL_CONVMODE_SAMPLEHOLD (_DAC_CTRL_CONVMODE_SAMPLEHOLD << 2) /**< Shifted mode SAMPLEHOLD for DAC_CTRL */
<> 150:02e0a0aed4ec 91 #define DAC_CTRL_CONVMODE_SAMPLEOFF (_DAC_CTRL_CONVMODE_SAMPLEOFF << 2) /**< Shifted mode SAMPLEOFF for DAC_CTRL */
<> 150:02e0a0aed4ec 92 #define _DAC_CTRL_OUTMODE_SHIFT 4 /**< Shift value for DAC_OUTMODE */
<> 150:02e0a0aed4ec 93 #define _DAC_CTRL_OUTMODE_MASK 0x30UL /**< Bit mask for DAC_OUTMODE */
<> 150:02e0a0aed4ec 94 #define _DAC_CTRL_OUTMODE_DISABLE 0x00000000UL /**< Mode DISABLE for DAC_CTRL */
<> 150:02e0a0aed4ec 95 #define _DAC_CTRL_OUTMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for DAC_CTRL */
<> 150:02e0a0aed4ec 96 #define _DAC_CTRL_OUTMODE_PIN 0x00000001UL /**< Mode PIN for DAC_CTRL */
<> 150:02e0a0aed4ec 97 #define _DAC_CTRL_OUTMODE_ADC 0x00000002UL /**< Mode ADC for DAC_CTRL */
<> 150:02e0a0aed4ec 98 #define _DAC_CTRL_OUTMODE_PINADC 0x00000003UL /**< Mode PINADC for DAC_CTRL */
<> 150:02e0a0aed4ec 99 #define DAC_CTRL_OUTMODE_DISABLE (_DAC_CTRL_OUTMODE_DISABLE << 4) /**< Shifted mode DISABLE for DAC_CTRL */
<> 150:02e0a0aed4ec 100 #define DAC_CTRL_OUTMODE_DEFAULT (_DAC_CTRL_OUTMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for DAC_CTRL */
<> 150:02e0a0aed4ec 101 #define DAC_CTRL_OUTMODE_PIN (_DAC_CTRL_OUTMODE_PIN << 4) /**< Shifted mode PIN for DAC_CTRL */
<> 150:02e0a0aed4ec 102 #define DAC_CTRL_OUTMODE_ADC (_DAC_CTRL_OUTMODE_ADC << 4) /**< Shifted mode ADC for DAC_CTRL */
<> 150:02e0a0aed4ec 103 #define DAC_CTRL_OUTMODE_PINADC (_DAC_CTRL_OUTMODE_PINADC << 4) /**< Shifted mode PINADC for DAC_CTRL */
<> 150:02e0a0aed4ec 104 #define DAC_CTRL_OUTENPRS (0x1UL << 6) /**< PRS Controlled Output Enable */
<> 150:02e0a0aed4ec 105 #define _DAC_CTRL_OUTENPRS_SHIFT 6 /**< Shift value for DAC_OUTENPRS */
<> 150:02e0a0aed4ec 106 #define _DAC_CTRL_OUTENPRS_MASK 0x40UL /**< Bit mask for DAC_OUTENPRS */
<> 150:02e0a0aed4ec 107 #define _DAC_CTRL_OUTENPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */
<> 150:02e0a0aed4ec 108 #define DAC_CTRL_OUTENPRS_DEFAULT (_DAC_CTRL_OUTENPRS_DEFAULT << 6) /**< Shifted mode DEFAULT for DAC_CTRL */
<> 150:02e0a0aed4ec 109 #define DAC_CTRL_CH0PRESCRST (0x1UL << 7) /**< Channel 0 Start Reset Prescaler */
<> 150:02e0a0aed4ec 110 #define _DAC_CTRL_CH0PRESCRST_SHIFT 7 /**< Shift value for DAC_CH0PRESCRST */
<> 150:02e0a0aed4ec 111 #define _DAC_CTRL_CH0PRESCRST_MASK 0x80UL /**< Bit mask for DAC_CH0PRESCRST */
<> 150:02e0a0aed4ec 112 #define _DAC_CTRL_CH0PRESCRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */
<> 150:02e0a0aed4ec 113 #define DAC_CTRL_CH0PRESCRST_DEFAULT (_DAC_CTRL_CH0PRESCRST_DEFAULT << 7) /**< Shifted mode DEFAULT for DAC_CTRL */
<> 150:02e0a0aed4ec 114 #define _DAC_CTRL_REFSEL_SHIFT 8 /**< Shift value for DAC_REFSEL */
<> 150:02e0a0aed4ec 115 #define _DAC_CTRL_REFSEL_MASK 0x300UL /**< Bit mask for DAC_REFSEL */
<> 150:02e0a0aed4ec 116 #define _DAC_CTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */
<> 150:02e0a0aed4ec 117 #define _DAC_CTRL_REFSEL_1V25 0x00000000UL /**< Mode 1V25 for DAC_CTRL */
<> 150:02e0a0aed4ec 118 #define _DAC_CTRL_REFSEL_2V5 0x00000001UL /**< Mode 2V5 for DAC_CTRL */
<> 150:02e0a0aed4ec 119 #define _DAC_CTRL_REFSEL_VDD 0x00000002UL /**< Mode VDD for DAC_CTRL */
<> 150:02e0a0aed4ec 120 #define DAC_CTRL_REFSEL_DEFAULT (_DAC_CTRL_REFSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for DAC_CTRL */
<> 150:02e0a0aed4ec 121 #define DAC_CTRL_REFSEL_1V25 (_DAC_CTRL_REFSEL_1V25 << 8) /**< Shifted mode 1V25 for DAC_CTRL */
<> 150:02e0a0aed4ec 122 #define DAC_CTRL_REFSEL_2V5 (_DAC_CTRL_REFSEL_2V5 << 8) /**< Shifted mode 2V5 for DAC_CTRL */
<> 150:02e0a0aed4ec 123 #define DAC_CTRL_REFSEL_VDD (_DAC_CTRL_REFSEL_VDD << 8) /**< Shifted mode VDD for DAC_CTRL */
<> 150:02e0a0aed4ec 124 #define _DAC_CTRL_PRESC_SHIFT 16 /**< Shift value for DAC_PRESC */
<> 150:02e0a0aed4ec 125 #define _DAC_CTRL_PRESC_MASK 0x70000UL /**< Bit mask for DAC_PRESC */
<> 150:02e0a0aed4ec 126 #define _DAC_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */
<> 150:02e0a0aed4ec 127 #define _DAC_CTRL_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for DAC_CTRL */
<> 150:02e0a0aed4ec 128 #define DAC_CTRL_PRESC_DEFAULT (_DAC_CTRL_PRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for DAC_CTRL */
<> 150:02e0a0aed4ec 129 #define DAC_CTRL_PRESC_NODIVISION (_DAC_CTRL_PRESC_NODIVISION << 16) /**< Shifted mode NODIVISION for DAC_CTRL */
<> 150:02e0a0aed4ec 130 #define _DAC_CTRL_REFRSEL_SHIFT 20 /**< Shift value for DAC_REFRSEL */
<> 150:02e0a0aed4ec 131 #define _DAC_CTRL_REFRSEL_MASK 0x300000UL /**< Bit mask for DAC_REFRSEL */
<> 150:02e0a0aed4ec 132 #define _DAC_CTRL_REFRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */
<> 150:02e0a0aed4ec 133 #define _DAC_CTRL_REFRSEL_8CYCLES 0x00000000UL /**< Mode 8CYCLES for DAC_CTRL */
<> 150:02e0a0aed4ec 134 #define _DAC_CTRL_REFRSEL_16CYCLES 0x00000001UL /**< Mode 16CYCLES for DAC_CTRL */
<> 150:02e0a0aed4ec 135 #define _DAC_CTRL_REFRSEL_32CYCLES 0x00000002UL /**< Mode 32CYCLES for DAC_CTRL */
<> 150:02e0a0aed4ec 136 #define _DAC_CTRL_REFRSEL_64CYCLES 0x00000003UL /**< Mode 64CYCLES for DAC_CTRL */
<> 150:02e0a0aed4ec 137 #define DAC_CTRL_REFRSEL_DEFAULT (_DAC_CTRL_REFRSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for DAC_CTRL */
<> 150:02e0a0aed4ec 138 #define DAC_CTRL_REFRSEL_8CYCLES (_DAC_CTRL_REFRSEL_8CYCLES << 20) /**< Shifted mode 8CYCLES for DAC_CTRL */
<> 150:02e0a0aed4ec 139 #define DAC_CTRL_REFRSEL_16CYCLES (_DAC_CTRL_REFRSEL_16CYCLES << 20) /**< Shifted mode 16CYCLES for DAC_CTRL */
<> 150:02e0a0aed4ec 140 #define DAC_CTRL_REFRSEL_32CYCLES (_DAC_CTRL_REFRSEL_32CYCLES << 20) /**< Shifted mode 32CYCLES for DAC_CTRL */
<> 150:02e0a0aed4ec 141 #define DAC_CTRL_REFRSEL_64CYCLES (_DAC_CTRL_REFRSEL_64CYCLES << 20) /**< Shifted mode 64CYCLES for DAC_CTRL */
<> 150:02e0a0aed4ec 142
<> 150:02e0a0aed4ec 143 /* Bit fields for DAC STATUS */
<> 150:02e0a0aed4ec 144 #define _DAC_STATUS_RESETVALUE 0x00000000UL /**< Default value for DAC_STATUS */
<> 150:02e0a0aed4ec 145 #define _DAC_STATUS_MASK 0x00000003UL /**< Mask for DAC_STATUS */
<> 150:02e0a0aed4ec 146 #define DAC_STATUS_CH0DV (0x1UL << 0) /**< Channel 0 Data Valid */
<> 150:02e0a0aed4ec 147 #define _DAC_STATUS_CH0DV_SHIFT 0 /**< Shift value for DAC_CH0DV */
<> 150:02e0a0aed4ec 148 #define _DAC_STATUS_CH0DV_MASK 0x1UL /**< Bit mask for DAC_CH0DV */
<> 150:02e0a0aed4ec 149 #define _DAC_STATUS_CH0DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_STATUS */
<> 150:02e0a0aed4ec 150 #define DAC_STATUS_CH0DV_DEFAULT (_DAC_STATUS_CH0DV_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_STATUS */
<> 150:02e0a0aed4ec 151 #define DAC_STATUS_CH1DV (0x1UL << 1) /**< Channel 1 Data Valid */
<> 150:02e0a0aed4ec 152 #define _DAC_STATUS_CH1DV_SHIFT 1 /**< Shift value for DAC_CH1DV */
<> 150:02e0a0aed4ec 153 #define _DAC_STATUS_CH1DV_MASK 0x2UL /**< Bit mask for DAC_CH1DV */
<> 150:02e0a0aed4ec 154 #define _DAC_STATUS_CH1DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_STATUS */
<> 150:02e0a0aed4ec 155 #define DAC_STATUS_CH1DV_DEFAULT (_DAC_STATUS_CH1DV_DEFAULT << 1) /**< Shifted mode DEFAULT for DAC_STATUS */
<> 150:02e0a0aed4ec 156
<> 150:02e0a0aed4ec 157 /* Bit fields for DAC CH0CTRL */
<> 150:02e0a0aed4ec 158 #define _DAC_CH0CTRL_RESETVALUE 0x00000000UL /**< Default value for DAC_CH0CTRL */
<> 150:02e0a0aed4ec 159 #define _DAC_CH0CTRL_MASK 0x000000F7UL /**< Mask for DAC_CH0CTRL */
<> 150:02e0a0aed4ec 160 #define DAC_CH0CTRL_EN (0x1UL << 0) /**< Channel 0 Enable */
<> 150:02e0a0aed4ec 161 #define _DAC_CH0CTRL_EN_SHIFT 0 /**< Shift value for DAC_EN */
<> 150:02e0a0aed4ec 162 #define _DAC_CH0CTRL_EN_MASK 0x1UL /**< Bit mask for DAC_EN */
<> 150:02e0a0aed4ec 163 #define _DAC_CH0CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH0CTRL */
<> 150:02e0a0aed4ec 164 #define DAC_CH0CTRL_EN_DEFAULT (_DAC_CH0CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_CH0CTRL */
<> 150:02e0a0aed4ec 165 #define DAC_CH0CTRL_REFREN (0x1UL << 1) /**< Channel 0 Automatic Refresh Enable */
<> 150:02e0a0aed4ec 166 #define _DAC_CH0CTRL_REFREN_SHIFT 1 /**< Shift value for DAC_REFREN */
<> 150:02e0a0aed4ec 167 #define _DAC_CH0CTRL_REFREN_MASK 0x2UL /**< Bit mask for DAC_REFREN */
<> 150:02e0a0aed4ec 168 #define _DAC_CH0CTRL_REFREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH0CTRL */
<> 150:02e0a0aed4ec 169 #define DAC_CH0CTRL_REFREN_DEFAULT (_DAC_CH0CTRL_REFREN_DEFAULT << 1) /**< Shifted mode DEFAULT for DAC_CH0CTRL */
<> 150:02e0a0aed4ec 170 #define DAC_CH0CTRL_PRSEN (0x1UL << 2) /**< Channel 0 PRS Trigger Enable */
<> 150:02e0a0aed4ec 171 #define _DAC_CH0CTRL_PRSEN_SHIFT 2 /**< Shift value for DAC_PRSEN */
<> 150:02e0a0aed4ec 172 #define _DAC_CH0CTRL_PRSEN_MASK 0x4UL /**< Bit mask for DAC_PRSEN */
<> 150:02e0a0aed4ec 173 #define _DAC_CH0CTRL_PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH0CTRL */
<> 150:02e0a0aed4ec 174 #define DAC_CH0CTRL_PRSEN_DEFAULT (_DAC_CH0CTRL_PRSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for DAC_CH0CTRL */
<> 150:02e0a0aed4ec 175 #define _DAC_CH0CTRL_PRSSEL_SHIFT 4 /**< Shift value for DAC_PRSSEL */
<> 150:02e0a0aed4ec 176 #define _DAC_CH0CTRL_PRSSEL_MASK 0xF0UL /**< Bit mask for DAC_PRSSEL */
<> 150:02e0a0aed4ec 177 #define _DAC_CH0CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH0CTRL */
<> 150:02e0a0aed4ec 178 #define _DAC_CH0CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for DAC_CH0CTRL */
<> 150:02e0a0aed4ec 179 #define _DAC_CH0CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for DAC_CH0CTRL */
<> 150:02e0a0aed4ec 180 #define _DAC_CH0CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for DAC_CH0CTRL */
<> 150:02e0a0aed4ec 181 #define _DAC_CH0CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for DAC_CH0CTRL */
<> 150:02e0a0aed4ec 182 #define _DAC_CH0CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for DAC_CH0CTRL */
<> 150:02e0a0aed4ec 183 #define _DAC_CH0CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for DAC_CH0CTRL */
<> 150:02e0a0aed4ec 184 #define _DAC_CH0CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for DAC_CH0CTRL */
<> 150:02e0a0aed4ec 185 #define _DAC_CH0CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for DAC_CH0CTRL */
<> 150:02e0a0aed4ec 186 #define _DAC_CH0CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for DAC_CH0CTRL */
<> 150:02e0a0aed4ec 187 #define _DAC_CH0CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for DAC_CH0CTRL */
<> 150:02e0a0aed4ec 188 #define _DAC_CH0CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for DAC_CH0CTRL */
<> 150:02e0a0aed4ec 189 #define _DAC_CH0CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for DAC_CH0CTRL */
<> 150:02e0a0aed4ec 190 #define DAC_CH0CTRL_PRSSEL_DEFAULT (_DAC_CH0CTRL_PRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for DAC_CH0CTRL */
<> 150:02e0a0aed4ec 191 #define DAC_CH0CTRL_PRSSEL_PRSCH0 (_DAC_CH0CTRL_PRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for DAC_CH0CTRL */
<> 150:02e0a0aed4ec 192 #define DAC_CH0CTRL_PRSSEL_PRSCH1 (_DAC_CH0CTRL_PRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for DAC_CH0CTRL */
<> 150:02e0a0aed4ec 193 #define DAC_CH0CTRL_PRSSEL_PRSCH2 (_DAC_CH0CTRL_PRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for DAC_CH0CTRL */
<> 150:02e0a0aed4ec 194 #define DAC_CH0CTRL_PRSSEL_PRSCH3 (_DAC_CH0CTRL_PRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for DAC_CH0CTRL */
<> 150:02e0a0aed4ec 195 #define DAC_CH0CTRL_PRSSEL_PRSCH4 (_DAC_CH0CTRL_PRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for DAC_CH0CTRL */
<> 150:02e0a0aed4ec 196 #define DAC_CH0CTRL_PRSSEL_PRSCH5 (_DAC_CH0CTRL_PRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for DAC_CH0CTRL */
<> 150:02e0a0aed4ec 197 #define DAC_CH0CTRL_PRSSEL_PRSCH6 (_DAC_CH0CTRL_PRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for DAC_CH0CTRL */
<> 150:02e0a0aed4ec 198 #define DAC_CH0CTRL_PRSSEL_PRSCH7 (_DAC_CH0CTRL_PRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for DAC_CH0CTRL */
<> 150:02e0a0aed4ec 199 #define DAC_CH0CTRL_PRSSEL_PRSCH8 (_DAC_CH0CTRL_PRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for DAC_CH0CTRL */
<> 150:02e0a0aed4ec 200 #define DAC_CH0CTRL_PRSSEL_PRSCH9 (_DAC_CH0CTRL_PRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for DAC_CH0CTRL */
<> 150:02e0a0aed4ec 201 #define DAC_CH0CTRL_PRSSEL_PRSCH10 (_DAC_CH0CTRL_PRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for DAC_CH0CTRL */
<> 150:02e0a0aed4ec 202 #define DAC_CH0CTRL_PRSSEL_PRSCH11 (_DAC_CH0CTRL_PRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for DAC_CH0CTRL */
<> 150:02e0a0aed4ec 203
<> 150:02e0a0aed4ec 204 /* Bit fields for DAC CH1CTRL */
<> 150:02e0a0aed4ec 205 #define _DAC_CH1CTRL_RESETVALUE 0x00000000UL /**< Default value for DAC_CH1CTRL */
<> 150:02e0a0aed4ec 206 #define _DAC_CH1CTRL_MASK 0x000000F7UL /**< Mask for DAC_CH1CTRL */
<> 150:02e0a0aed4ec 207 #define DAC_CH1CTRL_EN (0x1UL << 0) /**< Channel 1 Enable */
<> 150:02e0a0aed4ec 208 #define _DAC_CH1CTRL_EN_SHIFT 0 /**< Shift value for DAC_EN */
<> 150:02e0a0aed4ec 209 #define _DAC_CH1CTRL_EN_MASK 0x1UL /**< Bit mask for DAC_EN */
<> 150:02e0a0aed4ec 210 #define _DAC_CH1CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH1CTRL */
<> 150:02e0a0aed4ec 211 #define DAC_CH1CTRL_EN_DEFAULT (_DAC_CH1CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_CH1CTRL */
<> 150:02e0a0aed4ec 212 #define DAC_CH1CTRL_REFREN (0x1UL << 1) /**< Channel 1 Automatic Refresh Enable */
<> 150:02e0a0aed4ec 213 #define _DAC_CH1CTRL_REFREN_SHIFT 1 /**< Shift value for DAC_REFREN */
<> 150:02e0a0aed4ec 214 #define _DAC_CH1CTRL_REFREN_MASK 0x2UL /**< Bit mask for DAC_REFREN */
<> 150:02e0a0aed4ec 215 #define _DAC_CH1CTRL_REFREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH1CTRL */
<> 150:02e0a0aed4ec 216 #define DAC_CH1CTRL_REFREN_DEFAULT (_DAC_CH1CTRL_REFREN_DEFAULT << 1) /**< Shifted mode DEFAULT for DAC_CH1CTRL */
<> 150:02e0a0aed4ec 217 #define DAC_CH1CTRL_PRSEN (0x1UL << 2) /**< Channel 1 PRS Trigger Enable */
<> 150:02e0a0aed4ec 218 #define _DAC_CH1CTRL_PRSEN_SHIFT 2 /**< Shift value for DAC_PRSEN */
<> 150:02e0a0aed4ec 219 #define _DAC_CH1CTRL_PRSEN_MASK 0x4UL /**< Bit mask for DAC_PRSEN */
<> 150:02e0a0aed4ec 220 #define _DAC_CH1CTRL_PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH1CTRL */
<> 150:02e0a0aed4ec 221 #define DAC_CH1CTRL_PRSEN_DEFAULT (_DAC_CH1CTRL_PRSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for DAC_CH1CTRL */
<> 150:02e0a0aed4ec 222 #define _DAC_CH1CTRL_PRSSEL_SHIFT 4 /**< Shift value for DAC_PRSSEL */
<> 150:02e0a0aed4ec 223 #define _DAC_CH1CTRL_PRSSEL_MASK 0xF0UL /**< Bit mask for DAC_PRSSEL */
<> 150:02e0a0aed4ec 224 #define _DAC_CH1CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH1CTRL */
<> 150:02e0a0aed4ec 225 #define _DAC_CH1CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for DAC_CH1CTRL */
<> 150:02e0a0aed4ec 226 #define _DAC_CH1CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for DAC_CH1CTRL */
<> 150:02e0a0aed4ec 227 #define _DAC_CH1CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for DAC_CH1CTRL */
<> 150:02e0a0aed4ec 228 #define _DAC_CH1CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for DAC_CH1CTRL */
<> 150:02e0a0aed4ec 229 #define _DAC_CH1CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for DAC_CH1CTRL */
<> 150:02e0a0aed4ec 230 #define _DAC_CH1CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for DAC_CH1CTRL */
<> 150:02e0a0aed4ec 231 #define _DAC_CH1CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for DAC_CH1CTRL */
<> 150:02e0a0aed4ec 232 #define _DAC_CH1CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for DAC_CH1CTRL */
<> 150:02e0a0aed4ec 233 #define _DAC_CH1CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for DAC_CH1CTRL */
<> 150:02e0a0aed4ec 234 #define _DAC_CH1CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for DAC_CH1CTRL */
<> 150:02e0a0aed4ec 235 #define _DAC_CH1CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for DAC_CH1CTRL */
<> 150:02e0a0aed4ec 236 #define _DAC_CH1CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for DAC_CH1CTRL */
<> 150:02e0a0aed4ec 237 #define DAC_CH1CTRL_PRSSEL_DEFAULT (_DAC_CH1CTRL_PRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for DAC_CH1CTRL */
<> 150:02e0a0aed4ec 238 #define DAC_CH1CTRL_PRSSEL_PRSCH0 (_DAC_CH1CTRL_PRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for DAC_CH1CTRL */
<> 150:02e0a0aed4ec 239 #define DAC_CH1CTRL_PRSSEL_PRSCH1 (_DAC_CH1CTRL_PRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for DAC_CH1CTRL */
<> 150:02e0a0aed4ec 240 #define DAC_CH1CTRL_PRSSEL_PRSCH2 (_DAC_CH1CTRL_PRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for DAC_CH1CTRL */
<> 150:02e0a0aed4ec 241 #define DAC_CH1CTRL_PRSSEL_PRSCH3 (_DAC_CH1CTRL_PRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for DAC_CH1CTRL */
<> 150:02e0a0aed4ec 242 #define DAC_CH1CTRL_PRSSEL_PRSCH4 (_DAC_CH1CTRL_PRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for DAC_CH1CTRL */
<> 150:02e0a0aed4ec 243 #define DAC_CH1CTRL_PRSSEL_PRSCH5 (_DAC_CH1CTRL_PRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for DAC_CH1CTRL */
<> 150:02e0a0aed4ec 244 #define DAC_CH1CTRL_PRSSEL_PRSCH6 (_DAC_CH1CTRL_PRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for DAC_CH1CTRL */
<> 150:02e0a0aed4ec 245 #define DAC_CH1CTRL_PRSSEL_PRSCH7 (_DAC_CH1CTRL_PRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for DAC_CH1CTRL */
<> 150:02e0a0aed4ec 246 #define DAC_CH1CTRL_PRSSEL_PRSCH8 (_DAC_CH1CTRL_PRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for DAC_CH1CTRL */
<> 150:02e0a0aed4ec 247 #define DAC_CH1CTRL_PRSSEL_PRSCH9 (_DAC_CH1CTRL_PRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for DAC_CH1CTRL */
<> 150:02e0a0aed4ec 248 #define DAC_CH1CTRL_PRSSEL_PRSCH10 (_DAC_CH1CTRL_PRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for DAC_CH1CTRL */
<> 150:02e0a0aed4ec 249 #define DAC_CH1CTRL_PRSSEL_PRSCH11 (_DAC_CH1CTRL_PRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for DAC_CH1CTRL */
<> 150:02e0a0aed4ec 250
<> 150:02e0a0aed4ec 251 /* Bit fields for DAC IEN */
<> 150:02e0a0aed4ec 252 #define _DAC_IEN_RESETVALUE 0x00000000UL /**< Default value for DAC_IEN */
<> 150:02e0a0aed4ec 253 #define _DAC_IEN_MASK 0x00000033UL /**< Mask for DAC_IEN */
<> 150:02e0a0aed4ec 254 #define DAC_IEN_CH0 (0x1UL << 0) /**< Channel 0 Conversion Complete Interrupt Enable */
<> 150:02e0a0aed4ec 255 #define _DAC_IEN_CH0_SHIFT 0 /**< Shift value for DAC_CH0 */
<> 150:02e0a0aed4ec 256 #define _DAC_IEN_CH0_MASK 0x1UL /**< Bit mask for DAC_CH0 */
<> 150:02e0a0aed4ec 257 #define _DAC_IEN_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IEN */
<> 150:02e0a0aed4ec 258 #define DAC_IEN_CH0_DEFAULT (_DAC_IEN_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_IEN */
<> 150:02e0a0aed4ec 259 #define DAC_IEN_CH1 (0x1UL << 1) /**< Channel 1 Conversion Complete Interrupt Enable */
<> 150:02e0a0aed4ec 260 #define _DAC_IEN_CH1_SHIFT 1 /**< Shift value for DAC_CH1 */
<> 150:02e0a0aed4ec 261 #define _DAC_IEN_CH1_MASK 0x2UL /**< Bit mask for DAC_CH1 */
<> 150:02e0a0aed4ec 262 #define _DAC_IEN_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IEN */
<> 150:02e0a0aed4ec 263 #define DAC_IEN_CH1_DEFAULT (_DAC_IEN_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for DAC_IEN */
<> 150:02e0a0aed4ec 264 #define DAC_IEN_CH0UF (0x1UL << 4) /**< Channel 0 Conversion Data Underflow Interrupt Enable */
<> 150:02e0a0aed4ec 265 #define _DAC_IEN_CH0UF_SHIFT 4 /**< Shift value for DAC_CH0UF */
<> 150:02e0a0aed4ec 266 #define _DAC_IEN_CH0UF_MASK 0x10UL /**< Bit mask for DAC_CH0UF */
<> 150:02e0a0aed4ec 267 #define _DAC_IEN_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IEN */
<> 150:02e0a0aed4ec 268 #define DAC_IEN_CH0UF_DEFAULT (_DAC_IEN_CH0UF_DEFAULT << 4) /**< Shifted mode DEFAULT for DAC_IEN */
<> 150:02e0a0aed4ec 269 #define DAC_IEN_CH1UF (0x1UL << 5) /**< Channel 1 Conversion Data Underflow Interrupt Enable */
<> 150:02e0a0aed4ec 270 #define _DAC_IEN_CH1UF_SHIFT 5 /**< Shift value for DAC_CH1UF */
<> 150:02e0a0aed4ec 271 #define _DAC_IEN_CH1UF_MASK 0x20UL /**< Bit mask for DAC_CH1UF */
<> 150:02e0a0aed4ec 272 #define _DAC_IEN_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IEN */
<> 150:02e0a0aed4ec 273 #define DAC_IEN_CH1UF_DEFAULT (_DAC_IEN_CH1UF_DEFAULT << 5) /**< Shifted mode DEFAULT for DAC_IEN */
<> 150:02e0a0aed4ec 274
<> 150:02e0a0aed4ec 275 /* Bit fields for DAC IF */
<> 150:02e0a0aed4ec 276 #define _DAC_IF_RESETVALUE 0x00000000UL /**< Default value for DAC_IF */
<> 150:02e0a0aed4ec 277 #define _DAC_IF_MASK 0x00000033UL /**< Mask for DAC_IF */
<> 150:02e0a0aed4ec 278 #define DAC_IF_CH0 (0x1UL << 0) /**< Channel 0 Conversion Complete Interrupt Flag */
<> 150:02e0a0aed4ec 279 #define _DAC_IF_CH0_SHIFT 0 /**< Shift value for DAC_CH0 */
<> 150:02e0a0aed4ec 280 #define _DAC_IF_CH0_MASK 0x1UL /**< Bit mask for DAC_CH0 */
<> 150:02e0a0aed4ec 281 #define _DAC_IF_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IF */
<> 150:02e0a0aed4ec 282 #define DAC_IF_CH0_DEFAULT (_DAC_IF_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_IF */
<> 150:02e0a0aed4ec 283 #define DAC_IF_CH1 (0x1UL << 1) /**< Channel 1 Conversion Complete Interrupt Flag */
<> 150:02e0a0aed4ec 284 #define _DAC_IF_CH1_SHIFT 1 /**< Shift value for DAC_CH1 */
<> 150:02e0a0aed4ec 285 #define _DAC_IF_CH1_MASK 0x2UL /**< Bit mask for DAC_CH1 */
<> 150:02e0a0aed4ec 286 #define _DAC_IF_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IF */
<> 150:02e0a0aed4ec 287 #define DAC_IF_CH1_DEFAULT (_DAC_IF_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for DAC_IF */
<> 150:02e0a0aed4ec 288 #define DAC_IF_CH0UF (0x1UL << 4) /**< Channel 0 Data Underflow Interrupt Flag */
<> 150:02e0a0aed4ec 289 #define _DAC_IF_CH0UF_SHIFT 4 /**< Shift value for DAC_CH0UF */
<> 150:02e0a0aed4ec 290 #define _DAC_IF_CH0UF_MASK 0x10UL /**< Bit mask for DAC_CH0UF */
<> 150:02e0a0aed4ec 291 #define _DAC_IF_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IF */
<> 150:02e0a0aed4ec 292 #define DAC_IF_CH0UF_DEFAULT (_DAC_IF_CH0UF_DEFAULT << 4) /**< Shifted mode DEFAULT for DAC_IF */
<> 150:02e0a0aed4ec 293 #define DAC_IF_CH1UF (0x1UL << 5) /**< Channel 1 Data Underflow Interrupt Flag */
<> 150:02e0a0aed4ec 294 #define _DAC_IF_CH1UF_SHIFT 5 /**< Shift value for DAC_CH1UF */
<> 150:02e0a0aed4ec 295 #define _DAC_IF_CH1UF_MASK 0x20UL /**< Bit mask for DAC_CH1UF */
<> 150:02e0a0aed4ec 296 #define _DAC_IF_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IF */
<> 150:02e0a0aed4ec 297 #define DAC_IF_CH1UF_DEFAULT (_DAC_IF_CH1UF_DEFAULT << 5) /**< Shifted mode DEFAULT for DAC_IF */
<> 150:02e0a0aed4ec 298
<> 150:02e0a0aed4ec 299 /* Bit fields for DAC IFS */
<> 150:02e0a0aed4ec 300 #define _DAC_IFS_RESETVALUE 0x00000000UL /**< Default value for DAC_IFS */
<> 150:02e0a0aed4ec 301 #define _DAC_IFS_MASK 0x00000033UL /**< Mask for DAC_IFS */
<> 150:02e0a0aed4ec 302 #define DAC_IFS_CH0 (0x1UL << 0) /**< Channel 0 Conversion Complete Interrupt Flag Set */
<> 150:02e0a0aed4ec 303 #define _DAC_IFS_CH0_SHIFT 0 /**< Shift value for DAC_CH0 */
<> 150:02e0a0aed4ec 304 #define _DAC_IFS_CH0_MASK 0x1UL /**< Bit mask for DAC_CH0 */
<> 150:02e0a0aed4ec 305 #define _DAC_IFS_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IFS */
<> 150:02e0a0aed4ec 306 #define DAC_IFS_CH0_DEFAULT (_DAC_IFS_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_IFS */
<> 150:02e0a0aed4ec 307 #define DAC_IFS_CH1 (0x1UL << 1) /**< Channel 1 Conversion Complete Interrupt Flag Set */
<> 150:02e0a0aed4ec 308 #define _DAC_IFS_CH1_SHIFT 1 /**< Shift value for DAC_CH1 */
<> 150:02e0a0aed4ec 309 #define _DAC_IFS_CH1_MASK 0x2UL /**< Bit mask for DAC_CH1 */
<> 150:02e0a0aed4ec 310 #define _DAC_IFS_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IFS */
<> 150:02e0a0aed4ec 311 #define DAC_IFS_CH1_DEFAULT (_DAC_IFS_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for DAC_IFS */
<> 150:02e0a0aed4ec 312 #define DAC_IFS_CH0UF (0x1UL << 4) /**< Channel 0 Data Underflow Interrupt Flag Set */
<> 150:02e0a0aed4ec 313 #define _DAC_IFS_CH0UF_SHIFT 4 /**< Shift value for DAC_CH0UF */
<> 150:02e0a0aed4ec 314 #define _DAC_IFS_CH0UF_MASK 0x10UL /**< Bit mask for DAC_CH0UF */
<> 150:02e0a0aed4ec 315 #define _DAC_IFS_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IFS */
<> 150:02e0a0aed4ec 316 #define DAC_IFS_CH0UF_DEFAULT (_DAC_IFS_CH0UF_DEFAULT << 4) /**< Shifted mode DEFAULT for DAC_IFS */
<> 150:02e0a0aed4ec 317 #define DAC_IFS_CH1UF (0x1UL << 5) /**< Channel 1 Data Underflow Interrupt Flag Set */
<> 150:02e0a0aed4ec 318 #define _DAC_IFS_CH1UF_SHIFT 5 /**< Shift value for DAC_CH1UF */
<> 150:02e0a0aed4ec 319 #define _DAC_IFS_CH1UF_MASK 0x20UL /**< Bit mask for DAC_CH1UF */
<> 150:02e0a0aed4ec 320 #define _DAC_IFS_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IFS */
<> 150:02e0a0aed4ec 321 #define DAC_IFS_CH1UF_DEFAULT (_DAC_IFS_CH1UF_DEFAULT << 5) /**< Shifted mode DEFAULT for DAC_IFS */
<> 150:02e0a0aed4ec 322
<> 150:02e0a0aed4ec 323 /* Bit fields for DAC IFC */
<> 150:02e0a0aed4ec 324 #define _DAC_IFC_RESETVALUE 0x00000000UL /**< Default value for DAC_IFC */
<> 150:02e0a0aed4ec 325 #define _DAC_IFC_MASK 0x00000033UL /**< Mask for DAC_IFC */
<> 150:02e0a0aed4ec 326 #define DAC_IFC_CH0 (0x1UL << 0) /**< Channel 0 Conversion Complete Interrupt Flag Clear */
<> 150:02e0a0aed4ec 327 #define _DAC_IFC_CH0_SHIFT 0 /**< Shift value for DAC_CH0 */
<> 150:02e0a0aed4ec 328 #define _DAC_IFC_CH0_MASK 0x1UL /**< Bit mask for DAC_CH0 */
<> 150:02e0a0aed4ec 329 #define _DAC_IFC_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IFC */
<> 150:02e0a0aed4ec 330 #define DAC_IFC_CH0_DEFAULT (_DAC_IFC_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_IFC */
<> 150:02e0a0aed4ec 331 #define DAC_IFC_CH1 (0x1UL << 1) /**< Channel 1 Conversion Complete Interrupt Flag Clear */
<> 150:02e0a0aed4ec 332 #define _DAC_IFC_CH1_SHIFT 1 /**< Shift value for DAC_CH1 */
<> 150:02e0a0aed4ec 333 #define _DAC_IFC_CH1_MASK 0x2UL /**< Bit mask for DAC_CH1 */
<> 150:02e0a0aed4ec 334 #define _DAC_IFC_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IFC */
<> 150:02e0a0aed4ec 335 #define DAC_IFC_CH1_DEFAULT (_DAC_IFC_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for DAC_IFC */
<> 150:02e0a0aed4ec 336 #define DAC_IFC_CH0UF (0x1UL << 4) /**< Channel 0 Data Underflow Interrupt Flag Clear */
<> 150:02e0a0aed4ec 337 #define _DAC_IFC_CH0UF_SHIFT 4 /**< Shift value for DAC_CH0UF */
<> 150:02e0a0aed4ec 338 #define _DAC_IFC_CH0UF_MASK 0x10UL /**< Bit mask for DAC_CH0UF */
<> 150:02e0a0aed4ec 339 #define _DAC_IFC_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IFC */
<> 150:02e0a0aed4ec 340 #define DAC_IFC_CH0UF_DEFAULT (_DAC_IFC_CH0UF_DEFAULT << 4) /**< Shifted mode DEFAULT for DAC_IFC */
<> 150:02e0a0aed4ec 341 #define DAC_IFC_CH1UF (0x1UL << 5) /**< Channel 1 Data Underflow Interrupt Flag Clear */
<> 150:02e0a0aed4ec 342 #define _DAC_IFC_CH1UF_SHIFT 5 /**< Shift value for DAC_CH1UF */
<> 150:02e0a0aed4ec 343 #define _DAC_IFC_CH1UF_MASK 0x20UL /**< Bit mask for DAC_CH1UF */
<> 150:02e0a0aed4ec 344 #define _DAC_IFC_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IFC */
<> 150:02e0a0aed4ec 345 #define DAC_IFC_CH1UF_DEFAULT (_DAC_IFC_CH1UF_DEFAULT << 5) /**< Shifted mode DEFAULT for DAC_IFC */
<> 150:02e0a0aed4ec 346
<> 150:02e0a0aed4ec 347 /* Bit fields for DAC CH0DATA */
<> 150:02e0a0aed4ec 348 #define _DAC_CH0DATA_RESETVALUE 0x00000000UL /**< Default value for DAC_CH0DATA */
<> 150:02e0a0aed4ec 349 #define _DAC_CH0DATA_MASK 0x00000FFFUL /**< Mask for DAC_CH0DATA */
<> 150:02e0a0aed4ec 350 #define _DAC_CH0DATA_DATA_SHIFT 0 /**< Shift value for DAC_DATA */
<> 150:02e0a0aed4ec 351 #define _DAC_CH0DATA_DATA_MASK 0xFFFUL /**< Bit mask for DAC_DATA */
<> 150:02e0a0aed4ec 352 #define _DAC_CH0DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH0DATA */
<> 150:02e0a0aed4ec 353 #define DAC_CH0DATA_DATA_DEFAULT (_DAC_CH0DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_CH0DATA */
<> 150:02e0a0aed4ec 354
<> 150:02e0a0aed4ec 355 /* Bit fields for DAC CH1DATA */
<> 150:02e0a0aed4ec 356 #define _DAC_CH1DATA_RESETVALUE 0x00000000UL /**< Default value for DAC_CH1DATA */
<> 150:02e0a0aed4ec 357 #define _DAC_CH1DATA_MASK 0x00000FFFUL /**< Mask for DAC_CH1DATA */
<> 150:02e0a0aed4ec 358 #define _DAC_CH1DATA_DATA_SHIFT 0 /**< Shift value for DAC_DATA */
<> 150:02e0a0aed4ec 359 #define _DAC_CH1DATA_DATA_MASK 0xFFFUL /**< Bit mask for DAC_DATA */
<> 150:02e0a0aed4ec 360 #define _DAC_CH1DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH1DATA */
<> 150:02e0a0aed4ec 361 #define DAC_CH1DATA_DATA_DEFAULT (_DAC_CH1DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_CH1DATA */
<> 150:02e0a0aed4ec 362
<> 150:02e0a0aed4ec 363 /* Bit fields for DAC COMBDATA */
<> 150:02e0a0aed4ec 364 #define _DAC_COMBDATA_RESETVALUE 0x00000000UL /**< Default value for DAC_COMBDATA */
<> 150:02e0a0aed4ec 365 #define _DAC_COMBDATA_MASK 0x0FFF0FFFUL /**< Mask for DAC_COMBDATA */
<> 150:02e0a0aed4ec 366 #define _DAC_COMBDATA_CH0DATA_SHIFT 0 /**< Shift value for DAC_CH0DATA */
<> 150:02e0a0aed4ec 367 #define _DAC_COMBDATA_CH0DATA_MASK 0xFFFUL /**< Bit mask for DAC_CH0DATA */
<> 150:02e0a0aed4ec 368 #define _DAC_COMBDATA_CH0DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_COMBDATA */
<> 150:02e0a0aed4ec 369 #define DAC_COMBDATA_CH0DATA_DEFAULT (_DAC_COMBDATA_CH0DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_COMBDATA */
<> 150:02e0a0aed4ec 370 #define _DAC_COMBDATA_CH1DATA_SHIFT 16 /**< Shift value for DAC_CH1DATA */
<> 150:02e0a0aed4ec 371 #define _DAC_COMBDATA_CH1DATA_MASK 0xFFF0000UL /**< Bit mask for DAC_CH1DATA */
<> 150:02e0a0aed4ec 372 #define _DAC_COMBDATA_CH1DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_COMBDATA */
<> 150:02e0a0aed4ec 373 #define DAC_COMBDATA_CH1DATA_DEFAULT (_DAC_COMBDATA_CH1DATA_DEFAULT << 16) /**< Shifted mode DEFAULT for DAC_COMBDATA */
<> 150:02e0a0aed4ec 374
<> 150:02e0a0aed4ec 375 /* Bit fields for DAC CAL */
<> 150:02e0a0aed4ec 376 #define _DAC_CAL_RESETVALUE 0x00400000UL /**< Default value for DAC_CAL */
<> 150:02e0a0aed4ec 377 #define _DAC_CAL_MASK 0x007F3F3FUL /**< Mask for DAC_CAL */
<> 150:02e0a0aed4ec 378 #define _DAC_CAL_CH0OFFSET_SHIFT 0 /**< Shift value for DAC_CH0OFFSET */
<> 150:02e0a0aed4ec 379 #define _DAC_CAL_CH0OFFSET_MASK 0x3FUL /**< Bit mask for DAC_CH0OFFSET */
<> 150:02e0a0aed4ec 380 #define _DAC_CAL_CH0OFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CAL */
<> 150:02e0a0aed4ec 381 #define DAC_CAL_CH0OFFSET_DEFAULT (_DAC_CAL_CH0OFFSET_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_CAL */
<> 150:02e0a0aed4ec 382 #define _DAC_CAL_CH1OFFSET_SHIFT 8 /**< Shift value for DAC_CH1OFFSET */
<> 150:02e0a0aed4ec 383 #define _DAC_CAL_CH1OFFSET_MASK 0x3F00UL /**< Bit mask for DAC_CH1OFFSET */
<> 150:02e0a0aed4ec 384 #define _DAC_CAL_CH1OFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CAL */
<> 150:02e0a0aed4ec 385 #define DAC_CAL_CH1OFFSET_DEFAULT (_DAC_CAL_CH1OFFSET_DEFAULT << 8) /**< Shifted mode DEFAULT for DAC_CAL */
<> 150:02e0a0aed4ec 386 #define _DAC_CAL_GAIN_SHIFT 16 /**< Shift value for DAC_GAIN */
<> 150:02e0a0aed4ec 387 #define _DAC_CAL_GAIN_MASK 0x7F0000UL /**< Bit mask for DAC_GAIN */
<> 150:02e0a0aed4ec 388 #define _DAC_CAL_GAIN_DEFAULT 0x00000040UL /**< Mode DEFAULT for DAC_CAL */
<> 150:02e0a0aed4ec 389 #define DAC_CAL_GAIN_DEFAULT (_DAC_CAL_GAIN_DEFAULT << 16) /**< Shifted mode DEFAULT for DAC_CAL */
<> 150:02e0a0aed4ec 390
<> 150:02e0a0aed4ec 391 /* Bit fields for DAC BIASPROG */
<> 150:02e0a0aed4ec 392 #define _DAC_BIASPROG_RESETVALUE 0x00004747UL /**< Default value for DAC_BIASPROG */
<> 150:02e0a0aed4ec 393 #define _DAC_BIASPROG_MASK 0x00004F4FUL /**< Mask for DAC_BIASPROG */
<> 150:02e0a0aed4ec 394 #define _DAC_BIASPROG_BIASPROG_SHIFT 0 /**< Shift value for DAC_BIASPROG */
<> 150:02e0a0aed4ec 395 #define _DAC_BIASPROG_BIASPROG_MASK 0xFUL /**< Bit mask for DAC_BIASPROG */
<> 150:02e0a0aed4ec 396 #define _DAC_BIASPROG_BIASPROG_DEFAULT 0x00000007UL /**< Mode DEFAULT for DAC_BIASPROG */
<> 150:02e0a0aed4ec 397 #define DAC_BIASPROG_BIASPROG_DEFAULT (_DAC_BIASPROG_BIASPROG_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_BIASPROG */
<> 150:02e0a0aed4ec 398 #define DAC_BIASPROG_HALFBIAS (0x1UL << 6) /**< Half Bias Current */
<> 150:02e0a0aed4ec 399 #define _DAC_BIASPROG_HALFBIAS_SHIFT 6 /**< Shift value for DAC_HALFBIAS */
<> 150:02e0a0aed4ec 400 #define _DAC_BIASPROG_HALFBIAS_MASK 0x40UL /**< Bit mask for DAC_HALFBIAS */
<> 150:02e0a0aed4ec 401 #define _DAC_BIASPROG_HALFBIAS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DAC_BIASPROG */
<> 150:02e0a0aed4ec 402 #define DAC_BIASPROG_HALFBIAS_DEFAULT (_DAC_BIASPROG_HALFBIAS_DEFAULT << 6) /**< Shifted mode DEFAULT for DAC_BIASPROG */
<> 150:02e0a0aed4ec 403 #define _DAC_BIASPROG_OPA2BIASPROG_SHIFT 8 /**< Shift value for DAC_OPA2BIASPROG */
<> 150:02e0a0aed4ec 404 #define _DAC_BIASPROG_OPA2BIASPROG_MASK 0xF00UL /**< Bit mask for DAC_OPA2BIASPROG */
<> 150:02e0a0aed4ec 405 #define _DAC_BIASPROG_OPA2BIASPROG_DEFAULT 0x00000007UL /**< Mode DEFAULT for DAC_BIASPROG */
<> 150:02e0a0aed4ec 406 #define DAC_BIASPROG_OPA2BIASPROG_DEFAULT (_DAC_BIASPROG_OPA2BIASPROG_DEFAULT << 8) /**< Shifted mode DEFAULT for DAC_BIASPROG */
<> 150:02e0a0aed4ec 407 #define DAC_BIASPROG_OPA2HALFBIAS (0x1UL << 14) /**< Half Bias Current */
<> 150:02e0a0aed4ec 408 #define _DAC_BIASPROG_OPA2HALFBIAS_SHIFT 14 /**< Shift value for DAC_OPA2HALFBIAS */
<> 150:02e0a0aed4ec 409 #define _DAC_BIASPROG_OPA2HALFBIAS_MASK 0x4000UL /**< Bit mask for DAC_OPA2HALFBIAS */
<> 150:02e0a0aed4ec 410 #define _DAC_BIASPROG_OPA2HALFBIAS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DAC_BIASPROG */
<> 150:02e0a0aed4ec 411 #define DAC_BIASPROG_OPA2HALFBIAS_DEFAULT (_DAC_BIASPROG_OPA2HALFBIAS_DEFAULT << 14) /**< Shifted mode DEFAULT for DAC_BIASPROG */
<> 150:02e0a0aed4ec 412
<> 150:02e0a0aed4ec 413 /* Bit fields for DAC OPACTRL */
<> 150:02e0a0aed4ec 414 #define _DAC_OPACTRL_RESETVALUE 0x00000000UL /**< Default value for DAC_OPACTRL */
<> 150:02e0a0aed4ec 415 #define _DAC_OPACTRL_MASK 0x01C3F1C7UL /**< Mask for DAC_OPACTRL */
<> 150:02e0a0aed4ec 416 #define DAC_OPACTRL_OPA0EN (0x1UL << 0) /**< OPA0 Enable */
<> 150:02e0a0aed4ec 417 #define _DAC_OPACTRL_OPA0EN_SHIFT 0 /**< Shift value for DAC_OPA0EN */
<> 150:02e0a0aed4ec 418 #define _DAC_OPACTRL_OPA0EN_MASK 0x1UL /**< Bit mask for DAC_OPA0EN */
<> 150:02e0a0aed4ec 419 #define _DAC_OPACTRL_OPA0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPACTRL */
<> 150:02e0a0aed4ec 420 #define DAC_OPACTRL_OPA0EN_DEFAULT (_DAC_OPACTRL_OPA0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_OPACTRL */
<> 150:02e0a0aed4ec 421 #define DAC_OPACTRL_OPA1EN (0x1UL << 1) /**< OPA1 Enable */
<> 150:02e0a0aed4ec 422 #define _DAC_OPACTRL_OPA1EN_SHIFT 1 /**< Shift value for DAC_OPA1EN */
<> 150:02e0a0aed4ec 423 #define _DAC_OPACTRL_OPA1EN_MASK 0x2UL /**< Bit mask for DAC_OPA1EN */
<> 150:02e0a0aed4ec 424 #define _DAC_OPACTRL_OPA1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPACTRL */
<> 150:02e0a0aed4ec 425 #define DAC_OPACTRL_OPA1EN_DEFAULT (_DAC_OPACTRL_OPA1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for DAC_OPACTRL */
<> 150:02e0a0aed4ec 426 #define DAC_OPACTRL_OPA2EN (0x1UL << 2) /**< OPA2 Enable */
<> 150:02e0a0aed4ec 427 #define _DAC_OPACTRL_OPA2EN_SHIFT 2 /**< Shift value for DAC_OPA2EN */
<> 150:02e0a0aed4ec 428 #define _DAC_OPACTRL_OPA2EN_MASK 0x4UL /**< Bit mask for DAC_OPA2EN */
<> 150:02e0a0aed4ec 429 #define _DAC_OPACTRL_OPA2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPACTRL */
<> 150:02e0a0aed4ec 430 #define DAC_OPACTRL_OPA2EN_DEFAULT (_DAC_OPACTRL_OPA2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for DAC_OPACTRL */
<> 150:02e0a0aed4ec 431 #define DAC_OPACTRL_OPA0HCMDIS (0x1UL << 6) /**< High Common Mode Disable. */
<> 150:02e0a0aed4ec 432 #define _DAC_OPACTRL_OPA0HCMDIS_SHIFT 6 /**< Shift value for DAC_OPA0HCMDIS */
<> 150:02e0a0aed4ec 433 #define _DAC_OPACTRL_OPA0HCMDIS_MASK 0x40UL /**< Bit mask for DAC_OPA0HCMDIS */
<> 150:02e0a0aed4ec 434 #define _DAC_OPACTRL_OPA0HCMDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPACTRL */
<> 150:02e0a0aed4ec 435 #define DAC_OPACTRL_OPA0HCMDIS_DEFAULT (_DAC_OPACTRL_OPA0HCMDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for DAC_OPACTRL */
<> 150:02e0a0aed4ec 436 #define DAC_OPACTRL_OPA1HCMDIS (0x1UL << 7) /**< High Common Mode Disable. */
<> 150:02e0a0aed4ec 437 #define _DAC_OPACTRL_OPA1HCMDIS_SHIFT 7 /**< Shift value for DAC_OPA1HCMDIS */
<> 150:02e0a0aed4ec 438 #define _DAC_OPACTRL_OPA1HCMDIS_MASK 0x80UL /**< Bit mask for DAC_OPA1HCMDIS */
<> 150:02e0a0aed4ec 439 #define _DAC_OPACTRL_OPA1HCMDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPACTRL */
<> 150:02e0a0aed4ec 440 #define DAC_OPACTRL_OPA1HCMDIS_DEFAULT (_DAC_OPACTRL_OPA1HCMDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for DAC_OPACTRL */
<> 150:02e0a0aed4ec 441 #define DAC_OPACTRL_OPA2HCMDIS (0x1UL << 8) /**< High Common Mode Disable. */
<> 150:02e0a0aed4ec 442 #define _DAC_OPACTRL_OPA2HCMDIS_SHIFT 8 /**< Shift value for DAC_OPA2HCMDIS */
<> 150:02e0a0aed4ec 443 #define _DAC_OPACTRL_OPA2HCMDIS_MASK 0x100UL /**< Bit mask for DAC_OPA2HCMDIS */
<> 150:02e0a0aed4ec 444 #define _DAC_OPACTRL_OPA2HCMDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPACTRL */
<> 150:02e0a0aed4ec 445 #define DAC_OPACTRL_OPA2HCMDIS_DEFAULT (_DAC_OPACTRL_OPA2HCMDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for DAC_OPACTRL */
<> 150:02e0a0aed4ec 446 #define _DAC_OPACTRL_OPA0LPFDIS_SHIFT 12 /**< Shift value for DAC_OPA0LPFDIS */
<> 150:02e0a0aed4ec 447 #define _DAC_OPACTRL_OPA0LPFDIS_MASK 0x3000UL /**< Bit mask for DAC_OPA0LPFDIS */
<> 150:02e0a0aed4ec 448 #define _DAC_OPACTRL_OPA0LPFDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPACTRL */
<> 150:02e0a0aed4ec 449 #define _DAC_OPACTRL_OPA0LPFDIS_PLPFDIS 0x00000001UL /**< Mode PLPFDIS for DAC_OPACTRL */
<> 150:02e0a0aed4ec 450 #define _DAC_OPACTRL_OPA0LPFDIS_NLPFDIS 0x00000002UL /**< Mode NLPFDIS for DAC_OPACTRL */
<> 150:02e0a0aed4ec 451 #define DAC_OPACTRL_OPA0LPFDIS_DEFAULT (_DAC_OPACTRL_OPA0LPFDIS_DEFAULT << 12) /**< Shifted mode DEFAULT for DAC_OPACTRL */
<> 150:02e0a0aed4ec 452 #define DAC_OPACTRL_OPA0LPFDIS_PLPFDIS (_DAC_OPACTRL_OPA0LPFDIS_PLPFDIS << 12) /**< Shifted mode PLPFDIS for DAC_OPACTRL */
<> 150:02e0a0aed4ec 453 #define DAC_OPACTRL_OPA0LPFDIS_NLPFDIS (_DAC_OPACTRL_OPA0LPFDIS_NLPFDIS << 12) /**< Shifted mode NLPFDIS for DAC_OPACTRL */
<> 150:02e0a0aed4ec 454 #define _DAC_OPACTRL_OPA1LPFDIS_SHIFT 14 /**< Shift value for DAC_OPA1LPFDIS */
<> 150:02e0a0aed4ec 455 #define _DAC_OPACTRL_OPA1LPFDIS_MASK 0xC000UL /**< Bit mask for DAC_OPA1LPFDIS */
<> 150:02e0a0aed4ec 456 #define _DAC_OPACTRL_OPA1LPFDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPACTRL */
<> 150:02e0a0aed4ec 457 #define _DAC_OPACTRL_OPA1LPFDIS_PLPFDIS 0x00000001UL /**< Mode PLPFDIS for DAC_OPACTRL */
<> 150:02e0a0aed4ec 458 #define _DAC_OPACTRL_OPA1LPFDIS_NLPFDIS 0x00000002UL /**< Mode NLPFDIS for DAC_OPACTRL */
<> 150:02e0a0aed4ec 459 #define DAC_OPACTRL_OPA1LPFDIS_DEFAULT (_DAC_OPACTRL_OPA1LPFDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for DAC_OPACTRL */
<> 150:02e0a0aed4ec 460 #define DAC_OPACTRL_OPA1LPFDIS_PLPFDIS (_DAC_OPACTRL_OPA1LPFDIS_PLPFDIS << 14) /**< Shifted mode PLPFDIS for DAC_OPACTRL */
<> 150:02e0a0aed4ec 461 #define DAC_OPACTRL_OPA1LPFDIS_NLPFDIS (_DAC_OPACTRL_OPA1LPFDIS_NLPFDIS << 14) /**< Shifted mode NLPFDIS for DAC_OPACTRL */
<> 150:02e0a0aed4ec 462 #define _DAC_OPACTRL_OPA2LPFDIS_SHIFT 16 /**< Shift value for DAC_OPA2LPFDIS */
<> 150:02e0a0aed4ec 463 #define _DAC_OPACTRL_OPA2LPFDIS_MASK 0x30000UL /**< Bit mask for DAC_OPA2LPFDIS */
<> 150:02e0a0aed4ec 464 #define _DAC_OPACTRL_OPA2LPFDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPACTRL */
<> 150:02e0a0aed4ec 465 #define _DAC_OPACTRL_OPA2LPFDIS_PLPFDIS 0x00000001UL /**< Mode PLPFDIS for DAC_OPACTRL */
<> 150:02e0a0aed4ec 466 #define _DAC_OPACTRL_OPA2LPFDIS_NLPFDIS 0x00000002UL /**< Mode NLPFDIS for DAC_OPACTRL */
<> 150:02e0a0aed4ec 467 #define DAC_OPACTRL_OPA2LPFDIS_DEFAULT (_DAC_OPACTRL_OPA2LPFDIS_DEFAULT << 16) /**< Shifted mode DEFAULT for DAC_OPACTRL */
<> 150:02e0a0aed4ec 468 #define DAC_OPACTRL_OPA2LPFDIS_PLPFDIS (_DAC_OPACTRL_OPA2LPFDIS_PLPFDIS << 16) /**< Shifted mode PLPFDIS for DAC_OPACTRL */
<> 150:02e0a0aed4ec 469 #define DAC_OPACTRL_OPA2LPFDIS_NLPFDIS (_DAC_OPACTRL_OPA2LPFDIS_NLPFDIS << 16) /**< Shifted mode NLPFDIS for DAC_OPACTRL */
<> 150:02e0a0aed4ec 470 #define DAC_OPACTRL_OPA0SHORT (0x1UL << 22) /**< Short the non-inverting and inverting input. */
<> 150:02e0a0aed4ec 471 #define _DAC_OPACTRL_OPA0SHORT_SHIFT 22 /**< Shift value for DAC_OPA0SHORT */
<> 150:02e0a0aed4ec 472 #define _DAC_OPACTRL_OPA0SHORT_MASK 0x400000UL /**< Bit mask for DAC_OPA0SHORT */
<> 150:02e0a0aed4ec 473 #define _DAC_OPACTRL_OPA0SHORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPACTRL */
<> 150:02e0a0aed4ec 474 #define DAC_OPACTRL_OPA0SHORT_DEFAULT (_DAC_OPACTRL_OPA0SHORT_DEFAULT << 22) /**< Shifted mode DEFAULT for DAC_OPACTRL */
<> 150:02e0a0aed4ec 475 #define DAC_OPACTRL_OPA1SHORT (0x1UL << 23) /**< Short the non-inverting and inverting input. */
<> 150:02e0a0aed4ec 476 #define _DAC_OPACTRL_OPA1SHORT_SHIFT 23 /**< Shift value for DAC_OPA1SHORT */
<> 150:02e0a0aed4ec 477 #define _DAC_OPACTRL_OPA1SHORT_MASK 0x800000UL /**< Bit mask for DAC_OPA1SHORT */
<> 150:02e0a0aed4ec 478 #define _DAC_OPACTRL_OPA1SHORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPACTRL */
<> 150:02e0a0aed4ec 479 #define DAC_OPACTRL_OPA1SHORT_DEFAULT (_DAC_OPACTRL_OPA1SHORT_DEFAULT << 23) /**< Shifted mode DEFAULT for DAC_OPACTRL */
<> 150:02e0a0aed4ec 480 #define DAC_OPACTRL_OPA2SHORT (0x1UL << 24) /**< Short the non-inverting and inverting input. */
<> 150:02e0a0aed4ec 481 #define _DAC_OPACTRL_OPA2SHORT_SHIFT 24 /**< Shift value for DAC_OPA2SHORT */
<> 150:02e0a0aed4ec 482 #define _DAC_OPACTRL_OPA2SHORT_MASK 0x1000000UL /**< Bit mask for DAC_OPA2SHORT */
<> 150:02e0a0aed4ec 483 #define _DAC_OPACTRL_OPA2SHORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPACTRL */
<> 150:02e0a0aed4ec 484 #define DAC_OPACTRL_OPA2SHORT_DEFAULT (_DAC_OPACTRL_OPA2SHORT_DEFAULT << 24) /**< Shifted mode DEFAULT for DAC_OPACTRL */
<> 150:02e0a0aed4ec 485
<> 150:02e0a0aed4ec 486 /* Bit fields for DAC OPAOFFSET */
<> 150:02e0a0aed4ec 487 #define _DAC_OPAOFFSET_RESETVALUE 0x00000020UL /**< Default value for DAC_OPAOFFSET */
<> 150:02e0a0aed4ec 488 #define _DAC_OPAOFFSET_MASK 0x0000003FUL /**< Mask for DAC_OPAOFFSET */
<> 150:02e0a0aed4ec 489 #define _DAC_OPAOFFSET_OPA2OFFSET_SHIFT 0 /**< Shift value for DAC_OPA2OFFSET */
<> 150:02e0a0aed4ec 490 #define _DAC_OPAOFFSET_OPA2OFFSET_MASK 0x3FUL /**< Bit mask for DAC_OPA2OFFSET */
<> 150:02e0a0aed4ec 491 #define _DAC_OPAOFFSET_OPA2OFFSET_DEFAULT 0x00000020UL /**< Mode DEFAULT for DAC_OPAOFFSET */
<> 150:02e0a0aed4ec 492 #define DAC_OPAOFFSET_OPA2OFFSET_DEFAULT (_DAC_OPAOFFSET_OPA2OFFSET_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_OPAOFFSET */
<> 150:02e0a0aed4ec 493
<> 150:02e0a0aed4ec 494 /* Bit fields for DAC OPA0MUX */
<> 150:02e0a0aed4ec 495 #define _DAC_OPA0MUX_RESETVALUE 0x00400000UL /**< Default value for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 496 #define _DAC_OPA0MUX_MASK 0x74C7F737UL /**< Mask for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 497 #define _DAC_OPA0MUX_POSSEL_SHIFT 0 /**< Shift value for DAC_POSSEL */
<> 150:02e0a0aed4ec 498 #define _DAC_OPA0MUX_POSSEL_MASK 0x7UL /**< Bit mask for DAC_POSSEL */
<> 150:02e0a0aed4ec 499 #define _DAC_OPA0MUX_POSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 500 #define _DAC_OPA0MUX_POSSEL_DISABLE 0x00000000UL /**< Mode DISABLE for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 501 #define _DAC_OPA0MUX_POSSEL_DAC 0x00000001UL /**< Mode DAC for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 502 #define _DAC_OPA0MUX_POSSEL_POSPAD 0x00000002UL /**< Mode POSPAD for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 503 #define _DAC_OPA0MUX_POSSEL_OPA0INP 0x00000003UL /**< Mode OPA0INP for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 504 #define _DAC_OPA0MUX_POSSEL_OPATAP 0x00000004UL /**< Mode OPATAP for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 505 #define DAC_OPA0MUX_POSSEL_DEFAULT (_DAC_OPA0MUX_POSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 506 #define DAC_OPA0MUX_POSSEL_DISABLE (_DAC_OPA0MUX_POSSEL_DISABLE << 0) /**< Shifted mode DISABLE for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 507 #define DAC_OPA0MUX_POSSEL_DAC (_DAC_OPA0MUX_POSSEL_DAC << 0) /**< Shifted mode DAC for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 508 #define DAC_OPA0MUX_POSSEL_POSPAD (_DAC_OPA0MUX_POSSEL_POSPAD << 0) /**< Shifted mode POSPAD for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 509 #define DAC_OPA0MUX_POSSEL_OPA0INP (_DAC_OPA0MUX_POSSEL_OPA0INP << 0) /**< Shifted mode OPA0INP for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 510 #define DAC_OPA0MUX_POSSEL_OPATAP (_DAC_OPA0MUX_POSSEL_OPATAP << 0) /**< Shifted mode OPATAP for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 511 #define _DAC_OPA0MUX_NEGSEL_SHIFT 4 /**< Shift value for DAC_NEGSEL */
<> 150:02e0a0aed4ec 512 #define _DAC_OPA0MUX_NEGSEL_MASK 0x30UL /**< Bit mask for DAC_NEGSEL */
<> 150:02e0a0aed4ec 513 #define _DAC_OPA0MUX_NEGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 514 #define _DAC_OPA0MUX_NEGSEL_DISABLE 0x00000000UL /**< Mode DISABLE for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 515 #define _DAC_OPA0MUX_NEGSEL_UG 0x00000001UL /**< Mode UG for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 516 #define _DAC_OPA0MUX_NEGSEL_OPATAP 0x00000002UL /**< Mode OPATAP for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 517 #define _DAC_OPA0MUX_NEGSEL_NEGPAD 0x00000003UL /**< Mode NEGPAD for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 518 #define DAC_OPA0MUX_NEGSEL_DEFAULT (_DAC_OPA0MUX_NEGSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 519 #define DAC_OPA0MUX_NEGSEL_DISABLE (_DAC_OPA0MUX_NEGSEL_DISABLE << 4) /**< Shifted mode DISABLE for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 520 #define DAC_OPA0MUX_NEGSEL_UG (_DAC_OPA0MUX_NEGSEL_UG << 4) /**< Shifted mode UG for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 521 #define DAC_OPA0MUX_NEGSEL_OPATAP (_DAC_OPA0MUX_NEGSEL_OPATAP << 4) /**< Shifted mode OPATAP for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 522 #define DAC_OPA0MUX_NEGSEL_NEGPAD (_DAC_OPA0MUX_NEGSEL_NEGPAD << 4) /**< Shifted mode NEGPAD for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 523 #define _DAC_OPA0MUX_RESINMUX_SHIFT 8 /**< Shift value for DAC_RESINMUX */
<> 150:02e0a0aed4ec 524 #define _DAC_OPA0MUX_RESINMUX_MASK 0x700UL /**< Bit mask for DAC_RESINMUX */
<> 150:02e0a0aed4ec 525 #define _DAC_OPA0MUX_RESINMUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 526 #define _DAC_OPA0MUX_RESINMUX_DISABLE 0x00000000UL /**< Mode DISABLE for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 527 #define _DAC_OPA0MUX_RESINMUX_OPA0INP 0x00000001UL /**< Mode OPA0INP for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 528 #define _DAC_OPA0MUX_RESINMUX_NEGPAD 0x00000002UL /**< Mode NEGPAD for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 529 #define _DAC_OPA0MUX_RESINMUX_POSPAD 0x00000003UL /**< Mode POSPAD for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 530 #define _DAC_OPA0MUX_RESINMUX_VSS 0x00000004UL /**< Mode VSS for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 531 #define DAC_OPA0MUX_RESINMUX_DEFAULT (_DAC_OPA0MUX_RESINMUX_DEFAULT << 8) /**< Shifted mode DEFAULT for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 532 #define DAC_OPA0MUX_RESINMUX_DISABLE (_DAC_OPA0MUX_RESINMUX_DISABLE << 8) /**< Shifted mode DISABLE for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 533 #define DAC_OPA0MUX_RESINMUX_OPA0INP (_DAC_OPA0MUX_RESINMUX_OPA0INP << 8) /**< Shifted mode OPA0INP for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 534 #define DAC_OPA0MUX_RESINMUX_NEGPAD (_DAC_OPA0MUX_RESINMUX_NEGPAD << 8) /**< Shifted mode NEGPAD for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 535 #define DAC_OPA0MUX_RESINMUX_POSPAD (_DAC_OPA0MUX_RESINMUX_POSPAD << 8) /**< Shifted mode POSPAD for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 536 #define DAC_OPA0MUX_RESINMUX_VSS (_DAC_OPA0MUX_RESINMUX_VSS << 8) /**< Shifted mode VSS for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 537 #define DAC_OPA0MUX_PPEN (0x1UL << 12) /**< OPA0 Positive Pad Input Enable */
<> 150:02e0a0aed4ec 538 #define _DAC_OPA0MUX_PPEN_SHIFT 12 /**< Shift value for DAC_PPEN */
<> 150:02e0a0aed4ec 539 #define _DAC_OPA0MUX_PPEN_MASK 0x1000UL /**< Bit mask for DAC_PPEN */
<> 150:02e0a0aed4ec 540 #define _DAC_OPA0MUX_PPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 541 #define DAC_OPA0MUX_PPEN_DEFAULT (_DAC_OPA0MUX_PPEN_DEFAULT << 12) /**< Shifted mode DEFAULT for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 542 #define DAC_OPA0MUX_NPEN (0x1UL << 13) /**< OPA0 Negative Pad Input Enable */
<> 150:02e0a0aed4ec 543 #define _DAC_OPA0MUX_NPEN_SHIFT 13 /**< Shift value for DAC_NPEN */
<> 150:02e0a0aed4ec 544 #define _DAC_OPA0MUX_NPEN_MASK 0x2000UL /**< Bit mask for DAC_NPEN */
<> 150:02e0a0aed4ec 545 #define _DAC_OPA0MUX_NPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 546 #define DAC_OPA0MUX_NPEN_DEFAULT (_DAC_OPA0MUX_NPEN_DEFAULT << 13) /**< Shifted mode DEFAULT for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 547 #define _DAC_OPA0MUX_OUTPEN_SHIFT 14 /**< Shift value for DAC_OUTPEN */
<> 150:02e0a0aed4ec 548 #define _DAC_OPA0MUX_OUTPEN_MASK 0x7C000UL /**< Bit mask for DAC_OUTPEN */
<> 150:02e0a0aed4ec 549 #define _DAC_OPA0MUX_OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 550 #define _DAC_OPA0MUX_OUTPEN_OUT0 0x00000001UL /**< Mode OUT0 for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 551 #define _DAC_OPA0MUX_OUTPEN_OUT1 0x00000002UL /**< Mode OUT1 for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 552 #define _DAC_OPA0MUX_OUTPEN_OUT2 0x00000004UL /**< Mode OUT2 for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 553 #define _DAC_OPA0MUX_OUTPEN_OUT3 0x00000008UL /**< Mode OUT3 for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 554 #define _DAC_OPA0MUX_OUTPEN_OUT4 0x00000010UL /**< Mode OUT4 for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 555 #define DAC_OPA0MUX_OUTPEN_DEFAULT (_DAC_OPA0MUX_OUTPEN_DEFAULT << 14) /**< Shifted mode DEFAULT for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 556 #define DAC_OPA0MUX_OUTPEN_OUT0 (_DAC_OPA0MUX_OUTPEN_OUT0 << 14) /**< Shifted mode OUT0 for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 557 #define DAC_OPA0MUX_OUTPEN_OUT1 (_DAC_OPA0MUX_OUTPEN_OUT1 << 14) /**< Shifted mode OUT1 for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 558 #define DAC_OPA0MUX_OUTPEN_OUT2 (_DAC_OPA0MUX_OUTPEN_OUT2 << 14) /**< Shifted mode OUT2 for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 559 #define DAC_OPA0MUX_OUTPEN_OUT3 (_DAC_OPA0MUX_OUTPEN_OUT3 << 14) /**< Shifted mode OUT3 for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 560 #define DAC_OPA0MUX_OUTPEN_OUT4 (_DAC_OPA0MUX_OUTPEN_OUT4 << 14) /**< Shifted mode OUT4 for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 561 #define _DAC_OPA0MUX_OUTMODE_SHIFT 22 /**< Shift value for DAC_OUTMODE */
<> 150:02e0a0aed4ec 562 #define _DAC_OPA0MUX_OUTMODE_MASK 0xC00000UL /**< Bit mask for DAC_OUTMODE */
<> 150:02e0a0aed4ec 563 #define _DAC_OPA0MUX_OUTMODE_DISABLE 0x00000000UL /**< Mode DISABLE for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 564 #define _DAC_OPA0MUX_OUTMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 565 #define _DAC_OPA0MUX_OUTMODE_MAIN 0x00000001UL /**< Mode MAIN for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 566 #define _DAC_OPA0MUX_OUTMODE_ALT 0x00000002UL /**< Mode ALT for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 567 #define _DAC_OPA0MUX_OUTMODE_ALL 0x00000003UL /**< Mode ALL for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 568 #define DAC_OPA0MUX_OUTMODE_DISABLE (_DAC_OPA0MUX_OUTMODE_DISABLE << 22) /**< Shifted mode DISABLE for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 569 #define DAC_OPA0MUX_OUTMODE_DEFAULT (_DAC_OPA0MUX_OUTMODE_DEFAULT << 22) /**< Shifted mode DEFAULT for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 570 #define DAC_OPA0MUX_OUTMODE_MAIN (_DAC_OPA0MUX_OUTMODE_MAIN << 22) /**< Shifted mode MAIN for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 571 #define DAC_OPA0MUX_OUTMODE_ALT (_DAC_OPA0MUX_OUTMODE_ALT << 22) /**< Shifted mode ALT for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 572 #define DAC_OPA0MUX_OUTMODE_ALL (_DAC_OPA0MUX_OUTMODE_ALL << 22) /**< Shifted mode ALL for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 573 #define DAC_OPA0MUX_NEXTOUT (0x1UL << 26) /**< OPA0 Next Enable */
<> 150:02e0a0aed4ec 574 #define _DAC_OPA0MUX_NEXTOUT_SHIFT 26 /**< Shift value for DAC_NEXTOUT */
<> 150:02e0a0aed4ec 575 #define _DAC_OPA0MUX_NEXTOUT_MASK 0x4000000UL /**< Bit mask for DAC_NEXTOUT */
<> 150:02e0a0aed4ec 576 #define _DAC_OPA0MUX_NEXTOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 577 #define DAC_OPA0MUX_NEXTOUT_DEFAULT (_DAC_OPA0MUX_NEXTOUT_DEFAULT << 26) /**< Shifted mode DEFAULT for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 578 #define _DAC_OPA0MUX_RESSEL_SHIFT 28 /**< Shift value for DAC_RESSEL */
<> 150:02e0a0aed4ec 579 #define _DAC_OPA0MUX_RESSEL_MASK 0x70000000UL /**< Bit mask for DAC_RESSEL */
<> 150:02e0a0aed4ec 580 #define _DAC_OPA0MUX_RESSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 581 #define _DAC_OPA0MUX_RESSEL_RES0 0x00000000UL /**< Mode RES0 for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 582 #define _DAC_OPA0MUX_RESSEL_RES1 0x00000001UL /**< Mode RES1 for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 583 #define _DAC_OPA0MUX_RESSEL_RES2 0x00000002UL /**< Mode RES2 for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 584 #define _DAC_OPA0MUX_RESSEL_RES3 0x00000003UL /**< Mode RES3 for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 585 #define _DAC_OPA0MUX_RESSEL_RES4 0x00000004UL /**< Mode RES4 for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 586 #define _DAC_OPA0MUX_RESSEL_RES5 0x00000005UL /**< Mode RES5 for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 587 #define _DAC_OPA0MUX_RESSEL_RES6 0x00000006UL /**< Mode RES6 for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 588 #define _DAC_OPA0MUX_RESSEL_RES7 0x00000007UL /**< Mode RES7 for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 589 #define DAC_OPA0MUX_RESSEL_DEFAULT (_DAC_OPA0MUX_RESSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 590 #define DAC_OPA0MUX_RESSEL_RES0 (_DAC_OPA0MUX_RESSEL_RES0 << 28) /**< Shifted mode RES0 for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 591 #define DAC_OPA0MUX_RESSEL_RES1 (_DAC_OPA0MUX_RESSEL_RES1 << 28) /**< Shifted mode RES1 for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 592 #define DAC_OPA0MUX_RESSEL_RES2 (_DAC_OPA0MUX_RESSEL_RES2 << 28) /**< Shifted mode RES2 for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 593 #define DAC_OPA0MUX_RESSEL_RES3 (_DAC_OPA0MUX_RESSEL_RES3 << 28) /**< Shifted mode RES3 for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 594 #define DAC_OPA0MUX_RESSEL_RES4 (_DAC_OPA0MUX_RESSEL_RES4 << 28) /**< Shifted mode RES4 for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 595 #define DAC_OPA0MUX_RESSEL_RES5 (_DAC_OPA0MUX_RESSEL_RES5 << 28) /**< Shifted mode RES5 for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 596 #define DAC_OPA0MUX_RESSEL_RES6 (_DAC_OPA0MUX_RESSEL_RES6 << 28) /**< Shifted mode RES6 for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 597 #define DAC_OPA0MUX_RESSEL_RES7 (_DAC_OPA0MUX_RESSEL_RES7 << 28) /**< Shifted mode RES7 for DAC_OPA0MUX */
<> 150:02e0a0aed4ec 598
<> 150:02e0a0aed4ec 599 /* Bit fields for DAC OPA1MUX */
<> 150:02e0a0aed4ec 600 #define _DAC_OPA1MUX_RESETVALUE 0x00000000UL /**< Default value for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 601 #define _DAC_OPA1MUX_MASK 0x74C7F737UL /**< Mask for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 602 #define _DAC_OPA1MUX_POSSEL_SHIFT 0 /**< Shift value for DAC_POSSEL */
<> 150:02e0a0aed4ec 603 #define _DAC_OPA1MUX_POSSEL_MASK 0x7UL /**< Bit mask for DAC_POSSEL */
<> 150:02e0a0aed4ec 604 #define _DAC_OPA1MUX_POSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 605 #define _DAC_OPA1MUX_POSSEL_DISABLE 0x00000000UL /**< Mode DISABLE for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 606 #define _DAC_OPA1MUX_POSSEL_DAC 0x00000001UL /**< Mode DAC for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 607 #define _DAC_OPA1MUX_POSSEL_POSPAD 0x00000002UL /**< Mode POSPAD for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 608 #define _DAC_OPA1MUX_POSSEL_OPA0INP 0x00000003UL /**< Mode OPA0INP for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 609 #define _DAC_OPA1MUX_POSSEL_OPATAP 0x00000004UL /**< Mode OPATAP for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 610 #define DAC_OPA1MUX_POSSEL_DEFAULT (_DAC_OPA1MUX_POSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 611 #define DAC_OPA1MUX_POSSEL_DISABLE (_DAC_OPA1MUX_POSSEL_DISABLE << 0) /**< Shifted mode DISABLE for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 612 #define DAC_OPA1MUX_POSSEL_DAC (_DAC_OPA1MUX_POSSEL_DAC << 0) /**< Shifted mode DAC for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 613 #define DAC_OPA1MUX_POSSEL_POSPAD (_DAC_OPA1MUX_POSSEL_POSPAD << 0) /**< Shifted mode POSPAD for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 614 #define DAC_OPA1MUX_POSSEL_OPA0INP (_DAC_OPA1MUX_POSSEL_OPA0INP << 0) /**< Shifted mode OPA0INP for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 615 #define DAC_OPA1MUX_POSSEL_OPATAP (_DAC_OPA1MUX_POSSEL_OPATAP << 0) /**< Shifted mode OPATAP for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 616 #define _DAC_OPA1MUX_NEGSEL_SHIFT 4 /**< Shift value for DAC_NEGSEL */
<> 150:02e0a0aed4ec 617 #define _DAC_OPA1MUX_NEGSEL_MASK 0x30UL /**< Bit mask for DAC_NEGSEL */
<> 150:02e0a0aed4ec 618 #define _DAC_OPA1MUX_NEGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 619 #define _DAC_OPA1MUX_NEGSEL_DISABLE 0x00000000UL /**< Mode DISABLE for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 620 #define _DAC_OPA1MUX_NEGSEL_UG 0x00000001UL /**< Mode UG for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 621 #define _DAC_OPA1MUX_NEGSEL_OPATAP 0x00000002UL /**< Mode OPATAP for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 622 #define _DAC_OPA1MUX_NEGSEL_NEGPAD 0x00000003UL /**< Mode NEGPAD for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 623 #define DAC_OPA1MUX_NEGSEL_DEFAULT (_DAC_OPA1MUX_NEGSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 624 #define DAC_OPA1MUX_NEGSEL_DISABLE (_DAC_OPA1MUX_NEGSEL_DISABLE << 4) /**< Shifted mode DISABLE for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 625 #define DAC_OPA1MUX_NEGSEL_UG (_DAC_OPA1MUX_NEGSEL_UG << 4) /**< Shifted mode UG for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 626 #define DAC_OPA1MUX_NEGSEL_OPATAP (_DAC_OPA1MUX_NEGSEL_OPATAP << 4) /**< Shifted mode OPATAP for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 627 #define DAC_OPA1MUX_NEGSEL_NEGPAD (_DAC_OPA1MUX_NEGSEL_NEGPAD << 4) /**< Shifted mode NEGPAD for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 628 #define _DAC_OPA1MUX_RESINMUX_SHIFT 8 /**< Shift value for DAC_RESINMUX */
<> 150:02e0a0aed4ec 629 #define _DAC_OPA1MUX_RESINMUX_MASK 0x700UL /**< Bit mask for DAC_RESINMUX */
<> 150:02e0a0aed4ec 630 #define _DAC_OPA1MUX_RESINMUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 631 #define _DAC_OPA1MUX_RESINMUX_DISABLE 0x00000000UL /**< Mode DISABLE for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 632 #define _DAC_OPA1MUX_RESINMUX_OPA0INP 0x00000001UL /**< Mode OPA0INP for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 633 #define _DAC_OPA1MUX_RESINMUX_NEGPAD 0x00000002UL /**< Mode NEGPAD for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 634 #define _DAC_OPA1MUX_RESINMUX_POSPAD 0x00000003UL /**< Mode POSPAD for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 635 #define _DAC_OPA1MUX_RESINMUX_VSS 0x00000004UL /**< Mode VSS for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 636 #define DAC_OPA1MUX_RESINMUX_DEFAULT (_DAC_OPA1MUX_RESINMUX_DEFAULT << 8) /**< Shifted mode DEFAULT for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 637 #define DAC_OPA1MUX_RESINMUX_DISABLE (_DAC_OPA1MUX_RESINMUX_DISABLE << 8) /**< Shifted mode DISABLE for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 638 #define DAC_OPA1MUX_RESINMUX_OPA0INP (_DAC_OPA1MUX_RESINMUX_OPA0INP << 8) /**< Shifted mode OPA0INP for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 639 #define DAC_OPA1MUX_RESINMUX_NEGPAD (_DAC_OPA1MUX_RESINMUX_NEGPAD << 8) /**< Shifted mode NEGPAD for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 640 #define DAC_OPA1MUX_RESINMUX_POSPAD (_DAC_OPA1MUX_RESINMUX_POSPAD << 8) /**< Shifted mode POSPAD for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 641 #define DAC_OPA1MUX_RESINMUX_VSS (_DAC_OPA1MUX_RESINMUX_VSS << 8) /**< Shifted mode VSS for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 642 #define DAC_OPA1MUX_PPEN (0x1UL << 12) /**< OPA1 Positive Pad Input Enable */
<> 150:02e0a0aed4ec 643 #define _DAC_OPA1MUX_PPEN_SHIFT 12 /**< Shift value for DAC_PPEN */
<> 150:02e0a0aed4ec 644 #define _DAC_OPA1MUX_PPEN_MASK 0x1000UL /**< Bit mask for DAC_PPEN */
<> 150:02e0a0aed4ec 645 #define _DAC_OPA1MUX_PPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 646 #define DAC_OPA1MUX_PPEN_DEFAULT (_DAC_OPA1MUX_PPEN_DEFAULT << 12) /**< Shifted mode DEFAULT for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 647 #define DAC_OPA1MUX_NPEN (0x1UL << 13) /**< OPA1 Negative Pad Input Enable */
<> 150:02e0a0aed4ec 648 #define _DAC_OPA1MUX_NPEN_SHIFT 13 /**< Shift value for DAC_NPEN */
<> 150:02e0a0aed4ec 649 #define _DAC_OPA1MUX_NPEN_MASK 0x2000UL /**< Bit mask for DAC_NPEN */
<> 150:02e0a0aed4ec 650 #define _DAC_OPA1MUX_NPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 651 #define DAC_OPA1MUX_NPEN_DEFAULT (_DAC_OPA1MUX_NPEN_DEFAULT << 13) /**< Shifted mode DEFAULT for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 652 #define _DAC_OPA1MUX_OUTPEN_SHIFT 14 /**< Shift value for DAC_OUTPEN */
<> 150:02e0a0aed4ec 653 #define _DAC_OPA1MUX_OUTPEN_MASK 0x7C000UL /**< Bit mask for DAC_OUTPEN */
<> 150:02e0a0aed4ec 654 #define _DAC_OPA1MUX_OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 655 #define _DAC_OPA1MUX_OUTPEN_OUT0 0x00000001UL /**< Mode OUT0 for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 656 #define _DAC_OPA1MUX_OUTPEN_OUT1 0x00000002UL /**< Mode OUT1 for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 657 #define _DAC_OPA1MUX_OUTPEN_OUT2 0x00000004UL /**< Mode OUT2 for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 658 #define _DAC_OPA1MUX_OUTPEN_OUT3 0x00000008UL /**< Mode OUT3 for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 659 #define _DAC_OPA1MUX_OUTPEN_OUT4 0x00000010UL /**< Mode OUT4 for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 660 #define DAC_OPA1MUX_OUTPEN_DEFAULT (_DAC_OPA1MUX_OUTPEN_DEFAULT << 14) /**< Shifted mode DEFAULT for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 661 #define DAC_OPA1MUX_OUTPEN_OUT0 (_DAC_OPA1MUX_OUTPEN_OUT0 << 14) /**< Shifted mode OUT0 for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 662 #define DAC_OPA1MUX_OUTPEN_OUT1 (_DAC_OPA1MUX_OUTPEN_OUT1 << 14) /**< Shifted mode OUT1 for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 663 #define DAC_OPA1MUX_OUTPEN_OUT2 (_DAC_OPA1MUX_OUTPEN_OUT2 << 14) /**< Shifted mode OUT2 for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 664 #define DAC_OPA1MUX_OUTPEN_OUT3 (_DAC_OPA1MUX_OUTPEN_OUT3 << 14) /**< Shifted mode OUT3 for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 665 #define DAC_OPA1MUX_OUTPEN_OUT4 (_DAC_OPA1MUX_OUTPEN_OUT4 << 14) /**< Shifted mode OUT4 for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 666 #define _DAC_OPA1MUX_OUTMODE_SHIFT 22 /**< Shift value for DAC_OUTMODE */
<> 150:02e0a0aed4ec 667 #define _DAC_OPA1MUX_OUTMODE_MASK 0xC00000UL /**< Bit mask for DAC_OUTMODE */
<> 150:02e0a0aed4ec 668 #define _DAC_OPA1MUX_OUTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 669 #define _DAC_OPA1MUX_OUTMODE_DISABLE 0x00000000UL /**< Mode DISABLE for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 670 #define _DAC_OPA1MUX_OUTMODE_MAIN 0x00000001UL /**< Mode MAIN for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 671 #define _DAC_OPA1MUX_OUTMODE_ALT 0x00000002UL /**< Mode ALT for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 672 #define _DAC_OPA1MUX_OUTMODE_ALL 0x00000003UL /**< Mode ALL for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 673 #define DAC_OPA1MUX_OUTMODE_DEFAULT (_DAC_OPA1MUX_OUTMODE_DEFAULT << 22) /**< Shifted mode DEFAULT for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 674 #define DAC_OPA1MUX_OUTMODE_DISABLE (_DAC_OPA1MUX_OUTMODE_DISABLE << 22) /**< Shifted mode DISABLE for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 675 #define DAC_OPA1MUX_OUTMODE_MAIN (_DAC_OPA1MUX_OUTMODE_MAIN << 22) /**< Shifted mode MAIN for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 676 #define DAC_OPA1MUX_OUTMODE_ALT (_DAC_OPA1MUX_OUTMODE_ALT << 22) /**< Shifted mode ALT for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 677 #define DAC_OPA1MUX_OUTMODE_ALL (_DAC_OPA1MUX_OUTMODE_ALL << 22) /**< Shifted mode ALL for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 678 #define DAC_OPA1MUX_NEXTOUT (0x1UL << 26) /**< OPA1 Next Enable */
<> 150:02e0a0aed4ec 679 #define _DAC_OPA1MUX_NEXTOUT_SHIFT 26 /**< Shift value for DAC_NEXTOUT */
<> 150:02e0a0aed4ec 680 #define _DAC_OPA1MUX_NEXTOUT_MASK 0x4000000UL /**< Bit mask for DAC_NEXTOUT */
<> 150:02e0a0aed4ec 681 #define _DAC_OPA1MUX_NEXTOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 682 #define DAC_OPA1MUX_NEXTOUT_DEFAULT (_DAC_OPA1MUX_NEXTOUT_DEFAULT << 26) /**< Shifted mode DEFAULT for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 683 #define _DAC_OPA1MUX_RESSEL_SHIFT 28 /**< Shift value for DAC_RESSEL */
<> 150:02e0a0aed4ec 684 #define _DAC_OPA1MUX_RESSEL_MASK 0x70000000UL /**< Bit mask for DAC_RESSEL */
<> 150:02e0a0aed4ec 685 #define _DAC_OPA1MUX_RESSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 686 #define _DAC_OPA1MUX_RESSEL_RES0 0x00000000UL /**< Mode RES0 for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 687 #define _DAC_OPA1MUX_RESSEL_RES1 0x00000001UL /**< Mode RES1 for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 688 #define _DAC_OPA1MUX_RESSEL_RES2 0x00000002UL /**< Mode RES2 for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 689 #define _DAC_OPA1MUX_RESSEL_RES3 0x00000003UL /**< Mode RES3 for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 690 #define _DAC_OPA1MUX_RESSEL_RES4 0x00000004UL /**< Mode RES4 for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 691 #define _DAC_OPA1MUX_RESSEL_RES5 0x00000005UL /**< Mode RES5 for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 692 #define _DAC_OPA1MUX_RESSEL_RES6 0x00000006UL /**< Mode RES6 for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 693 #define _DAC_OPA1MUX_RESSEL_RES7 0x00000007UL /**< Mode RES7 for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 694 #define DAC_OPA1MUX_RESSEL_DEFAULT (_DAC_OPA1MUX_RESSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 695 #define DAC_OPA1MUX_RESSEL_RES0 (_DAC_OPA1MUX_RESSEL_RES0 << 28) /**< Shifted mode RES0 for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 696 #define DAC_OPA1MUX_RESSEL_RES1 (_DAC_OPA1MUX_RESSEL_RES1 << 28) /**< Shifted mode RES1 for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 697 #define DAC_OPA1MUX_RESSEL_RES2 (_DAC_OPA1MUX_RESSEL_RES2 << 28) /**< Shifted mode RES2 for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 698 #define DAC_OPA1MUX_RESSEL_RES3 (_DAC_OPA1MUX_RESSEL_RES3 << 28) /**< Shifted mode RES3 for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 699 #define DAC_OPA1MUX_RESSEL_RES4 (_DAC_OPA1MUX_RESSEL_RES4 << 28) /**< Shifted mode RES4 for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 700 #define DAC_OPA1MUX_RESSEL_RES5 (_DAC_OPA1MUX_RESSEL_RES5 << 28) /**< Shifted mode RES5 for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 701 #define DAC_OPA1MUX_RESSEL_RES6 (_DAC_OPA1MUX_RESSEL_RES6 << 28) /**< Shifted mode RES6 for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 702 #define DAC_OPA1MUX_RESSEL_RES7 (_DAC_OPA1MUX_RESSEL_RES7 << 28) /**< Shifted mode RES7 for DAC_OPA1MUX */
<> 150:02e0a0aed4ec 703
<> 150:02e0a0aed4ec 704 /* Bit fields for DAC OPA2MUX */
<> 150:02e0a0aed4ec 705 #define _DAC_OPA2MUX_RESETVALUE 0x00000000UL /**< Default value for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 706 #define _DAC_OPA2MUX_MASK 0x7440F737UL /**< Mask for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 707 #define _DAC_OPA2MUX_POSSEL_SHIFT 0 /**< Shift value for DAC_POSSEL */
<> 150:02e0a0aed4ec 708 #define _DAC_OPA2MUX_POSSEL_MASK 0x7UL /**< Bit mask for DAC_POSSEL */
<> 150:02e0a0aed4ec 709 #define _DAC_OPA2MUX_POSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 710 #define _DAC_OPA2MUX_POSSEL_DISABLE 0x00000000UL /**< Mode DISABLE for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 711 #define _DAC_OPA2MUX_POSSEL_POSPAD 0x00000002UL /**< Mode POSPAD for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 712 #define _DAC_OPA2MUX_POSSEL_OPA1INP 0x00000003UL /**< Mode OPA1INP for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 713 #define _DAC_OPA2MUX_POSSEL_OPATAP 0x00000004UL /**< Mode OPATAP for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 714 #define DAC_OPA2MUX_POSSEL_DEFAULT (_DAC_OPA2MUX_POSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 715 #define DAC_OPA2MUX_POSSEL_DISABLE (_DAC_OPA2MUX_POSSEL_DISABLE << 0) /**< Shifted mode DISABLE for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 716 #define DAC_OPA2MUX_POSSEL_POSPAD (_DAC_OPA2MUX_POSSEL_POSPAD << 0) /**< Shifted mode POSPAD for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 717 #define DAC_OPA2MUX_POSSEL_OPA1INP (_DAC_OPA2MUX_POSSEL_OPA1INP << 0) /**< Shifted mode OPA1INP for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 718 #define DAC_OPA2MUX_POSSEL_OPATAP (_DAC_OPA2MUX_POSSEL_OPATAP << 0) /**< Shifted mode OPATAP for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 719 #define _DAC_OPA2MUX_NEGSEL_SHIFT 4 /**< Shift value for DAC_NEGSEL */
<> 150:02e0a0aed4ec 720 #define _DAC_OPA2MUX_NEGSEL_MASK 0x30UL /**< Bit mask for DAC_NEGSEL */
<> 150:02e0a0aed4ec 721 #define _DAC_OPA2MUX_NEGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 722 #define _DAC_OPA2MUX_NEGSEL_DISABLE 0x00000000UL /**< Mode DISABLE for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 723 #define _DAC_OPA2MUX_NEGSEL_UG 0x00000001UL /**< Mode UG for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 724 #define _DAC_OPA2MUX_NEGSEL_OPATAP 0x00000002UL /**< Mode OPATAP for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 725 #define _DAC_OPA2MUX_NEGSEL_NEGPAD 0x00000003UL /**< Mode NEGPAD for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 726 #define DAC_OPA2MUX_NEGSEL_DEFAULT (_DAC_OPA2MUX_NEGSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 727 #define DAC_OPA2MUX_NEGSEL_DISABLE (_DAC_OPA2MUX_NEGSEL_DISABLE << 4) /**< Shifted mode DISABLE for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 728 #define DAC_OPA2MUX_NEGSEL_UG (_DAC_OPA2MUX_NEGSEL_UG << 4) /**< Shifted mode UG for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 729 #define DAC_OPA2MUX_NEGSEL_OPATAP (_DAC_OPA2MUX_NEGSEL_OPATAP << 4) /**< Shifted mode OPATAP for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 730 #define DAC_OPA2MUX_NEGSEL_NEGPAD (_DAC_OPA2MUX_NEGSEL_NEGPAD << 4) /**< Shifted mode NEGPAD for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 731 #define _DAC_OPA2MUX_RESINMUX_SHIFT 8 /**< Shift value for DAC_RESINMUX */
<> 150:02e0a0aed4ec 732 #define _DAC_OPA2MUX_RESINMUX_MASK 0x700UL /**< Bit mask for DAC_RESINMUX */
<> 150:02e0a0aed4ec 733 #define _DAC_OPA2MUX_RESINMUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 734 #define _DAC_OPA2MUX_RESINMUX_DISABLE 0x00000000UL /**< Mode DISABLE for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 735 #define _DAC_OPA2MUX_RESINMUX_OPA1INP 0x00000001UL /**< Mode OPA1INP for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 736 #define _DAC_OPA2MUX_RESINMUX_NEGPAD 0x00000002UL /**< Mode NEGPAD for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 737 #define _DAC_OPA2MUX_RESINMUX_POSPAD 0x00000003UL /**< Mode POSPAD for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 738 #define _DAC_OPA2MUX_RESINMUX_VSS 0x00000004UL /**< Mode VSS for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 739 #define DAC_OPA2MUX_RESINMUX_DEFAULT (_DAC_OPA2MUX_RESINMUX_DEFAULT << 8) /**< Shifted mode DEFAULT for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 740 #define DAC_OPA2MUX_RESINMUX_DISABLE (_DAC_OPA2MUX_RESINMUX_DISABLE << 8) /**< Shifted mode DISABLE for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 741 #define DAC_OPA2MUX_RESINMUX_OPA1INP (_DAC_OPA2MUX_RESINMUX_OPA1INP << 8) /**< Shifted mode OPA1INP for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 742 #define DAC_OPA2MUX_RESINMUX_NEGPAD (_DAC_OPA2MUX_RESINMUX_NEGPAD << 8) /**< Shifted mode NEGPAD for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 743 #define DAC_OPA2MUX_RESINMUX_POSPAD (_DAC_OPA2MUX_RESINMUX_POSPAD << 8) /**< Shifted mode POSPAD for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 744 #define DAC_OPA2MUX_RESINMUX_VSS (_DAC_OPA2MUX_RESINMUX_VSS << 8) /**< Shifted mode VSS for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 745 #define DAC_OPA2MUX_PPEN (0x1UL << 12) /**< OPA2 Positive Pad Input Enable */
<> 150:02e0a0aed4ec 746 #define _DAC_OPA2MUX_PPEN_SHIFT 12 /**< Shift value for DAC_PPEN */
<> 150:02e0a0aed4ec 747 #define _DAC_OPA2MUX_PPEN_MASK 0x1000UL /**< Bit mask for DAC_PPEN */
<> 150:02e0a0aed4ec 748 #define _DAC_OPA2MUX_PPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 749 #define DAC_OPA2MUX_PPEN_DEFAULT (_DAC_OPA2MUX_PPEN_DEFAULT << 12) /**< Shifted mode DEFAULT for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 750 #define DAC_OPA2MUX_NPEN (0x1UL << 13) /**< OPA2 Negative Pad Input Enable */
<> 150:02e0a0aed4ec 751 #define _DAC_OPA2MUX_NPEN_SHIFT 13 /**< Shift value for DAC_NPEN */
<> 150:02e0a0aed4ec 752 #define _DAC_OPA2MUX_NPEN_MASK 0x2000UL /**< Bit mask for DAC_NPEN */
<> 150:02e0a0aed4ec 753 #define _DAC_OPA2MUX_NPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 754 #define DAC_OPA2MUX_NPEN_DEFAULT (_DAC_OPA2MUX_NPEN_DEFAULT << 13) /**< Shifted mode DEFAULT for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 755 #define _DAC_OPA2MUX_OUTPEN_SHIFT 14 /**< Shift value for DAC_OUTPEN */
<> 150:02e0a0aed4ec 756 #define _DAC_OPA2MUX_OUTPEN_MASK 0xC000UL /**< Bit mask for DAC_OUTPEN */
<> 150:02e0a0aed4ec 757 #define _DAC_OPA2MUX_OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 758 #define _DAC_OPA2MUX_OUTPEN_OUT0 0x00000001UL /**< Mode OUT0 for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 759 #define _DAC_OPA2MUX_OUTPEN_OUT1 0x00000002UL /**< Mode OUT1 for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 760 #define DAC_OPA2MUX_OUTPEN_DEFAULT (_DAC_OPA2MUX_OUTPEN_DEFAULT << 14) /**< Shifted mode DEFAULT for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 761 #define DAC_OPA2MUX_OUTPEN_OUT0 (_DAC_OPA2MUX_OUTPEN_OUT0 << 14) /**< Shifted mode OUT0 for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 762 #define DAC_OPA2MUX_OUTPEN_OUT1 (_DAC_OPA2MUX_OUTPEN_OUT1 << 14) /**< Shifted mode OUT1 for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 763 #define DAC_OPA2MUX_OUTMODE (0x1UL << 22) /**< Output Select */
<> 150:02e0a0aed4ec 764 #define _DAC_OPA2MUX_OUTMODE_SHIFT 22 /**< Shift value for DAC_OUTMODE */
<> 150:02e0a0aed4ec 765 #define _DAC_OPA2MUX_OUTMODE_MASK 0x400000UL /**< Bit mask for DAC_OUTMODE */
<> 150:02e0a0aed4ec 766 #define _DAC_OPA2MUX_OUTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 767 #define DAC_OPA2MUX_OUTMODE_DEFAULT (_DAC_OPA2MUX_OUTMODE_DEFAULT << 22) /**< Shifted mode DEFAULT for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 768 #define DAC_OPA2MUX_NEXTOUT (0x1UL << 26) /**< OPA2 Next Enable */
<> 150:02e0a0aed4ec 769 #define _DAC_OPA2MUX_NEXTOUT_SHIFT 26 /**< Shift value for DAC_NEXTOUT */
<> 150:02e0a0aed4ec 770 #define _DAC_OPA2MUX_NEXTOUT_MASK 0x4000000UL /**< Bit mask for DAC_NEXTOUT */
<> 150:02e0a0aed4ec 771 #define _DAC_OPA2MUX_NEXTOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 772 #define DAC_OPA2MUX_NEXTOUT_DEFAULT (_DAC_OPA2MUX_NEXTOUT_DEFAULT << 26) /**< Shifted mode DEFAULT for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 773 #define _DAC_OPA2MUX_RESSEL_SHIFT 28 /**< Shift value for DAC_RESSEL */
<> 150:02e0a0aed4ec 774 #define _DAC_OPA2MUX_RESSEL_MASK 0x70000000UL /**< Bit mask for DAC_RESSEL */
<> 150:02e0a0aed4ec 775 #define _DAC_OPA2MUX_RESSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 776 #define _DAC_OPA2MUX_RESSEL_RES0 0x00000000UL /**< Mode RES0 for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 777 #define _DAC_OPA2MUX_RESSEL_RES1 0x00000001UL /**< Mode RES1 for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 778 #define _DAC_OPA2MUX_RESSEL_RES2 0x00000002UL /**< Mode RES2 for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 779 #define _DAC_OPA2MUX_RESSEL_RES3 0x00000003UL /**< Mode RES3 for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 780 #define _DAC_OPA2MUX_RESSEL_RES4 0x00000004UL /**< Mode RES4 for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 781 #define _DAC_OPA2MUX_RESSEL_RES5 0x00000005UL /**< Mode RES5 for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 782 #define _DAC_OPA2MUX_RESSEL_RES6 0x00000006UL /**< Mode RES6 for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 783 #define _DAC_OPA2MUX_RESSEL_RES7 0x00000007UL /**< Mode RES7 for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 784 #define DAC_OPA2MUX_RESSEL_DEFAULT (_DAC_OPA2MUX_RESSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 785 #define DAC_OPA2MUX_RESSEL_RES0 (_DAC_OPA2MUX_RESSEL_RES0 << 28) /**< Shifted mode RES0 for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 786 #define DAC_OPA2MUX_RESSEL_RES1 (_DAC_OPA2MUX_RESSEL_RES1 << 28) /**< Shifted mode RES1 for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 787 #define DAC_OPA2MUX_RESSEL_RES2 (_DAC_OPA2MUX_RESSEL_RES2 << 28) /**< Shifted mode RES2 for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 788 #define DAC_OPA2MUX_RESSEL_RES3 (_DAC_OPA2MUX_RESSEL_RES3 << 28) /**< Shifted mode RES3 for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 789 #define DAC_OPA2MUX_RESSEL_RES4 (_DAC_OPA2MUX_RESSEL_RES4 << 28) /**< Shifted mode RES4 for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 790 #define DAC_OPA2MUX_RESSEL_RES5 (_DAC_OPA2MUX_RESSEL_RES5 << 28) /**< Shifted mode RES5 for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 791 #define DAC_OPA2MUX_RESSEL_RES6 (_DAC_OPA2MUX_RESSEL_RES6 << 28) /**< Shifted mode RES6 for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 792 #define DAC_OPA2MUX_RESSEL_RES7 (_DAC_OPA2MUX_RESSEL_RES7 << 28) /**< Shifted mode RES7 for DAC_OPA2MUX */
<> 150:02e0a0aed4ec 793
<> 150:02e0a0aed4ec 794 /** @} End of group EFM32WG_DAC */
<> 150:02e0a0aed4ec 795 /** @} End of group Parts */
<> 150:02e0a0aed4ec 796