Fawwaz Nadzmy / mbed-STM

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_cmu.h@153:9398a535854b, 2016-12-22 (annotated)

Committer:
fwndz
Date:
Thu Dec 22 05:12:40 2016 +0000
Revision:
153:9398a535854b
Parent:
150:02e0a0aed4ec 
device target maximize

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 150:02e0a0aed4ec 1 /**************************************************************************//**
<> 150:02e0a0aed4ec 2 * @file efm32wg_cmu.h
<> 150:02e0a0aed4ec 3 * @brief EFM32WG_CMU register and bit field definitions
<> 150:02e0a0aed4ec 4 * @version 5.0.0
<> 150:02e0a0aed4ec 5 ******************************************************************************
<> 150:02e0a0aed4ec 6 * @section License
<> 150:02e0a0aed4ec 7 * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 150:02e0a0aed4ec 8 ******************************************************************************
<> 150:02e0a0aed4ec 9 *
<> 150:02e0a0aed4ec 10 * Permission is granted to anyone to use this software for any purpose,
<> 150:02e0a0aed4ec 11 * including commercial applications, and to alter it and redistribute it
<> 150:02e0a0aed4ec 12 * freely, subject to the following restrictions:
<> 150:02e0a0aed4ec 13 *
<> 150:02e0a0aed4ec 14 * 1. The origin of this software must not be misrepresented; you must not
<> 150:02e0a0aed4ec 15 * claim that you wrote the original software.@n
<> 150:02e0a0aed4ec 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 150:02e0a0aed4ec 17 * misrepresented as being the original software.@n
<> 150:02e0a0aed4ec 18 * 3. This notice may not be removed or altered from any source distribution.
<> 150:02e0a0aed4ec 19 *
<> 150:02e0a0aed4ec 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 150:02e0a0aed4ec 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 150:02e0a0aed4ec 22 * providing the Software "AS IS", with no express or implied warranties of any
<> 150:02e0a0aed4ec 23 * kind, including, but not limited to, any implied warranties of
<> 150:02e0a0aed4ec 24 * merchantability or fitness for any particular purpose or warranties against
<> 150:02e0a0aed4ec 25 * infringement of any proprietary rights of a third party.
<> 150:02e0a0aed4ec 26 *
<> 150:02e0a0aed4ec 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 150:02e0a0aed4ec 28 * incidental, or special damages, or any other relief, or for any claim by
<> 150:02e0a0aed4ec 29 * any third party, arising from your use of this Software.
<> 150:02e0a0aed4ec 30 *
<> 150:02e0a0aed4ec 31 *****************************************************************************/
<> 150:02e0a0aed4ec 32 /**************************************************************************//**
<> 150:02e0a0aed4ec 33 * @addtogroup Parts
<> 150:02e0a0aed4ec 34 * @{
<> 150:02e0a0aed4ec 35 ******************************************************************************/
<> 150:02e0a0aed4ec 36 /**************************************************************************//**
<> 150:02e0a0aed4ec 37 * @defgroup EFM32WG_CMU
<> 150:02e0a0aed4ec 38 * @{
<> 150:02e0a0aed4ec 39 * @brief EFM32WG_CMU Register Declaration
<> 150:02e0a0aed4ec 40 *****************************************************************************/
<> 150:02e0a0aed4ec 41 typedef struct
<> 150:02e0a0aed4ec 42 {
<> 150:02e0a0aed4ec 43 __IOM uint32_t CTRL; /**< CMU Control Register */
<> 150:02e0a0aed4ec 44 __IOM uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register */
<> 150:02e0a0aed4ec 45 __IOM uint32_t HFPERCLKDIV; /**< High Frequency Peripheral Clock Division Register */
<> 150:02e0a0aed4ec 46 __IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */
<> 150:02e0a0aed4ec 47 __IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */
<> 150:02e0a0aed4ec 48 __IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */
<> 150:02e0a0aed4ec 49 __IOM uint32_t CALCTRL; /**< Calibration Control Register */
<> 150:02e0a0aed4ec 50 __IOM uint32_t CALCNT; /**< Calibration Counter Register */
<> 150:02e0a0aed4ec 51 __IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */
<> 150:02e0a0aed4ec 52 __IOM uint32_t CMD; /**< Command Register */
<> 150:02e0a0aed4ec 53 __IOM uint32_t LFCLKSEL; /**< Low Frequency Clock Select Register */
<> 150:02e0a0aed4ec 54 __IM uint32_t STATUS; /**< Status Register */
<> 150:02e0a0aed4ec 55 __IM uint32_t IF; /**< Interrupt Flag Register */
<> 150:02e0a0aed4ec 56 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
<> 150:02e0a0aed4ec 57 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
<> 150:02e0a0aed4ec 58 __IOM uint32_t IEN; /**< Interrupt Enable Register */
<> 150:02e0a0aed4ec 59 __IOM uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0 */
<> 150:02e0a0aed4ec 60 __IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */
<> 150:02e0a0aed4ec 61 uint32_t RESERVED0[2]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 62 __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
<> 150:02e0a0aed4ec 63 __IOM uint32_t FREEZE; /**< Freeze Register */
<> 150:02e0a0aed4ec 64 __IOM uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */
<> 150:02e0a0aed4ec 65 uint32_t RESERVED1[1]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 66 __IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */
<> 150:02e0a0aed4ec 67
<> 150:02e0a0aed4ec 68 uint32_t RESERVED2[1]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 69 __IOM uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */
<> 150:02e0a0aed4ec 70 uint32_t RESERVED3[1]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 71 __IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */
<> 150:02e0a0aed4ec 72 uint32_t RESERVED4[1]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 73 __IOM uint32_t PCNTCTRL; /**< PCNT Control Register */
<> 150:02e0a0aed4ec 74 __IOM uint32_t LCDCTRL; /**< LCD Control Register */
<> 150:02e0a0aed4ec 75 __IOM uint32_t ROUTE; /**< I/O Routing Register */
<> 150:02e0a0aed4ec 76 __IOM uint32_t LOCK; /**< Configuration Lock Register */
<> 150:02e0a0aed4ec 77 } CMU_TypeDef; /** @} */
<> 150:02e0a0aed4ec 78
<> 150:02e0a0aed4ec 79 /**************************************************************************//**
<> 150:02e0a0aed4ec 80 * @defgroup EFM32WG_CMU_BitFields
<> 150:02e0a0aed4ec 81 * @{
<> 150:02e0a0aed4ec 82 *****************************************************************************/
<> 150:02e0a0aed4ec 83
<> 150:02e0a0aed4ec 84 /* Bit fields for CMU CTRL */
<> 150:02e0a0aed4ec 85 #define _CMU_CTRL_RESETVALUE 0x000C262CUL /**< Default value for CMU_CTRL */
<> 150:02e0a0aed4ec 86 #define _CMU_CTRL_MASK 0x57FFFEEFUL /**< Mask for CMU_CTRL */
<> 150:02e0a0aed4ec 87 #define _CMU_CTRL_HFXOMODE_SHIFT 0 /**< Shift value for CMU_HFXOMODE */
<> 150:02e0a0aed4ec 88 #define _CMU_CTRL_HFXOMODE_MASK 0x3UL /**< Bit mask for CMU_HFXOMODE */
<> 150:02e0a0aed4ec 89 #define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 90 #define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */
<> 150:02e0a0aed4ec 91 #define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */
<> 150:02e0a0aed4ec 92 #define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */
<> 150:02e0a0aed4ec 93 #define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 94 #define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0) /**< Shifted mode XTAL for CMU_CTRL */
<> 150:02e0a0aed4ec 95 #define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0) /**< Shifted mode BUFEXTCLK for CMU_CTRL */
<> 150:02e0a0aed4ec 96 #define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_CTRL */
<> 150:02e0a0aed4ec 97 #define _CMU_CTRL_HFXOBOOST_SHIFT 2 /**< Shift value for CMU_HFXOBOOST */
<> 150:02e0a0aed4ec 98 #define _CMU_CTRL_HFXOBOOST_MASK 0xCUL /**< Bit mask for CMU_HFXOBOOST */
<> 150:02e0a0aed4ec 99 #define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL /**< Mode 50PCENT for CMU_CTRL */
<> 150:02e0a0aed4ec 100 #define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL /**< Mode 70PCENT for CMU_CTRL */
<> 150:02e0a0aed4ec 101 #define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL /**< Mode 80PCENT for CMU_CTRL */
<> 150:02e0a0aed4ec 102 #define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 103 #define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL /**< Mode 100PCENT for CMU_CTRL */
<> 150:02e0a0aed4ec 104 #define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2) /**< Shifted mode 50PCENT for CMU_CTRL */
<> 150:02e0a0aed4ec 105 #define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2) /**< Shifted mode 70PCENT for CMU_CTRL */
<> 150:02e0a0aed4ec 106 #define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2) /**< Shifted mode 80PCENT for CMU_CTRL */
<> 150:02e0a0aed4ec 107 #define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 108 #define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2) /**< Shifted mode 100PCENT for CMU_CTRL */
<> 150:02e0a0aed4ec 109 #define _CMU_CTRL_HFXOBUFCUR_SHIFT 5 /**< Shift value for CMU_HFXOBUFCUR */
<> 150:02e0a0aed4ec 110 #define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL /**< Bit mask for CMU_HFXOBUFCUR */
<> 150:02e0a0aed4ec 111 #define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 112 #define _CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ 0x00000001UL /**< Mode BOOSTUPTO32MHZ for CMU_CTRL */
<> 150:02e0a0aed4ec 113 #define _CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ 0x00000003UL /**< Mode BOOSTABOVE32MHZ for CMU_CTRL */
<> 150:02e0a0aed4ec 114 #define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 115 #define CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ << 5) /**< Shifted mode BOOSTUPTO32MHZ for CMU_CTRL */
<> 150:02e0a0aed4ec 116 #define CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ << 5) /**< Shifted mode BOOSTABOVE32MHZ for CMU_CTRL */
<> 150:02e0a0aed4ec 117 #define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7) /**< HFXO Glitch Detector Enable */
<> 150:02e0a0aed4ec 118 #define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7 /**< Shift value for CMU_HFXOGLITCHDETEN */
<> 150:02e0a0aed4ec 119 #define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL /**< Bit mask for CMU_HFXOGLITCHDETEN */
<> 150:02e0a0aed4ec 120 #define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 121 #define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 122 #define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9 /**< Shift value for CMU_HFXOTIMEOUT */
<> 150:02e0a0aed4ec 123 #define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL /**< Bit mask for CMU_HFXOTIMEOUT */
<> 150:02e0a0aed4ec 124 #define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */
<> 150:02e0a0aed4ec 125 #define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_CTRL */
<> 150:02e0a0aed4ec 126 #define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_CTRL */
<> 150:02e0a0aed4ec 127 #define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 128 #define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL /**< Mode 16KCYCLES for CMU_CTRL */
<> 150:02e0a0aed4ec 129 #define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9) /**< Shifted mode 8CYCLES for CMU_CTRL */
<> 150:02e0a0aed4ec 130 #define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9) /**< Shifted mode 256CYCLES for CMU_CTRL */
<> 150:02e0a0aed4ec 131 #define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9) /**< Shifted mode 1KCYCLES for CMU_CTRL */
<> 150:02e0a0aed4ec 132 #define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 133 #define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9) /**< Shifted mode 16KCYCLES for CMU_CTRL */
<> 150:02e0a0aed4ec 134 #define _CMU_CTRL_LFXOMODE_SHIFT 11 /**< Shift value for CMU_LFXOMODE */
<> 150:02e0a0aed4ec 135 #define _CMU_CTRL_LFXOMODE_MASK 0x1800UL /**< Bit mask for CMU_LFXOMODE */
<> 150:02e0a0aed4ec 136 #define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 137 #define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */
<> 150:02e0a0aed4ec 138 #define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */
<> 150:02e0a0aed4ec 139 #define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */
<> 150:02e0a0aed4ec 140 #define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 141 #define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11) /**< Shifted mode XTAL for CMU_CTRL */
<> 150:02e0a0aed4ec 142 #define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11) /**< Shifted mode BUFEXTCLK for CMU_CTRL */
<> 150:02e0a0aed4ec 143 #define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11) /**< Shifted mode DIGEXTCLK for CMU_CTRL */
<> 150:02e0a0aed4ec 144 #define CMU_CTRL_LFXOBOOST (0x1UL << 13) /**< LFXO Start-up Boost Current */
<> 150:02e0a0aed4ec 145 #define _CMU_CTRL_LFXOBOOST_SHIFT 13 /**< Shift value for CMU_LFXOBOOST */
<> 150:02e0a0aed4ec 146 #define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL /**< Bit mask for CMU_LFXOBOOST */
<> 150:02e0a0aed4ec 147 #define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL /**< Mode 70PCENT for CMU_CTRL */
<> 150:02e0a0aed4ec 148 #define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 149 #define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL /**< Mode 100PCENT for CMU_CTRL */
<> 150:02e0a0aed4ec 150 #define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13) /**< Shifted mode 70PCENT for CMU_CTRL */
<> 150:02e0a0aed4ec 151 #define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 152 #define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13) /**< Shifted mode 100PCENT for CMU_CTRL */
<> 150:02e0a0aed4ec 153 #define _CMU_CTRL_HFCLKDIV_SHIFT 14 /**< Shift value for CMU_HFCLKDIV */
<> 150:02e0a0aed4ec 154 #define _CMU_CTRL_HFCLKDIV_MASK 0x1C000UL /**< Bit mask for CMU_HFCLKDIV */
<> 150:02e0a0aed4ec 155 #define _CMU_CTRL_HFCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 156 #define CMU_CTRL_HFCLKDIV_DEFAULT (_CMU_CTRL_HFCLKDIV_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 157 #define CMU_CTRL_LFXOBUFCUR (0x1UL << 17) /**< LFXO Boost Buffer Current */
<> 150:02e0a0aed4ec 158 #define _CMU_CTRL_LFXOBUFCUR_SHIFT 17 /**< Shift value for CMU_LFXOBUFCUR */
<> 150:02e0a0aed4ec 159 #define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL /**< Bit mask for CMU_LFXOBUFCUR */
<> 150:02e0a0aed4ec 160 #define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 161 #define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 162 #define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18 /**< Shift value for CMU_LFXOTIMEOUT */
<> 150:02e0a0aed4ec 163 #define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL /**< Bit mask for CMU_LFXOTIMEOUT */
<> 150:02e0a0aed4ec 164 #define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */
<> 150:02e0a0aed4ec 165 #define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL /**< Mode 1KCYCLES for CMU_CTRL */
<> 150:02e0a0aed4ec 166 #define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL /**< Mode 16KCYCLES for CMU_CTRL */
<> 150:02e0a0aed4ec 167 #define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 168 #define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL /**< Mode 32KCYCLES for CMU_CTRL */
<> 150:02e0a0aed4ec 169 #define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18) /**< Shifted mode 8CYCLES for CMU_CTRL */
<> 150:02e0a0aed4ec 170 #define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18) /**< Shifted mode 1KCYCLES for CMU_CTRL */
<> 150:02e0a0aed4ec 171 #define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18) /**< Shifted mode 16KCYCLES for CMU_CTRL */
<> 150:02e0a0aed4ec 172 #define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 173 #define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18) /**< Shifted mode 32KCYCLES for CMU_CTRL */
<> 150:02e0a0aed4ec 174 #define _CMU_CTRL_CLKOUTSEL0_SHIFT 20 /**< Shift value for CMU_CLKOUTSEL0 */
<> 150:02e0a0aed4ec 175 #define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL /**< Bit mask for CMU_CLKOUTSEL0 */
<> 150:02e0a0aed4ec 176 #define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 177 #define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL /**< Mode HFRCO for CMU_CTRL */
<> 150:02e0a0aed4ec 178 #define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL /**< Mode HFXO for CMU_CTRL */
<> 150:02e0a0aed4ec 179 #define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL /**< Mode HFCLK2 for CMU_CTRL */
<> 150:02e0a0aed4ec 180 #define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL /**< Mode HFCLK4 for CMU_CTRL */
<> 150:02e0a0aed4ec 181 #define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL /**< Mode HFCLK8 for CMU_CTRL */
<> 150:02e0a0aed4ec 182 #define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL /**< Mode HFCLK16 for CMU_CTRL */
<> 150:02e0a0aed4ec 183 #define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL /**< Mode ULFRCO for CMU_CTRL */
<> 150:02e0a0aed4ec 184 #define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL /**< Mode AUXHFRCO for CMU_CTRL */
<> 150:02e0a0aed4ec 185 #define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 186 #define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20) /**< Shifted mode HFRCO for CMU_CTRL */
<> 150:02e0a0aed4ec 187 #define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20) /**< Shifted mode HFXO for CMU_CTRL */
<> 150:02e0a0aed4ec 188 #define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20) /**< Shifted mode HFCLK2 for CMU_CTRL */
<> 150:02e0a0aed4ec 189 #define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20) /**< Shifted mode HFCLK4 for CMU_CTRL */
<> 150:02e0a0aed4ec 190 #define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20) /**< Shifted mode HFCLK8 for CMU_CTRL */
<> 150:02e0a0aed4ec 191 #define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20) /**< Shifted mode HFCLK16 for CMU_CTRL */
<> 150:02e0a0aed4ec 192 #define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_CTRL */
<> 150:02e0a0aed4ec 193 #define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_CTRL */
<> 150:02e0a0aed4ec 194 #define _CMU_CTRL_CLKOUTSEL1_SHIFT 23 /**< Shift value for CMU_CLKOUTSEL1 */
<> 150:02e0a0aed4ec 195 #define _CMU_CTRL_CLKOUTSEL1_MASK 0x7800000UL /**< Bit mask for CMU_CLKOUTSEL1 */
<> 150:02e0a0aed4ec 196 #define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 197 #define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL /**< Mode LFRCO for CMU_CTRL */
<> 150:02e0a0aed4ec 198 #define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL /**< Mode LFXO for CMU_CTRL */
<> 150:02e0a0aed4ec 199 #define _CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL /**< Mode HFCLK for CMU_CTRL */
<> 150:02e0a0aed4ec 200 #define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL /**< Mode LFXOQ for CMU_CTRL */
<> 150:02e0a0aed4ec 201 #define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL /**< Mode HFXOQ for CMU_CTRL */
<> 150:02e0a0aed4ec 202 #define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL /**< Mode LFRCOQ for CMU_CTRL */
<> 150:02e0a0aed4ec 203 #define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL /**< Mode HFRCOQ for CMU_CTRL */
<> 150:02e0a0aed4ec 204 #define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL /**< Mode AUXHFRCOQ for CMU_CTRL */
<> 150:02e0a0aed4ec 205 #define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 206 #define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23) /**< Shifted mode LFRCO for CMU_CTRL */
<> 150:02e0a0aed4ec 207 #define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23) /**< Shifted mode LFXO for CMU_CTRL */
<> 150:02e0a0aed4ec 208 #define CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23) /**< Shifted mode HFCLK for CMU_CTRL */
<> 150:02e0a0aed4ec 209 #define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23) /**< Shifted mode LFXOQ for CMU_CTRL */
<> 150:02e0a0aed4ec 210 #define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23) /**< Shifted mode HFXOQ for CMU_CTRL */
<> 150:02e0a0aed4ec 211 #define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23) /**< Shifted mode LFRCOQ for CMU_CTRL */
<> 150:02e0a0aed4ec 212 #define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23) /**< Shifted mode HFRCOQ for CMU_CTRL */
<> 150:02e0a0aed4ec 213 #define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */
<> 150:02e0a0aed4ec 214 #define CMU_CTRL_DBGCLK (0x1UL << 28) /**< Debug Clock */
<> 150:02e0a0aed4ec 215 #define _CMU_CTRL_DBGCLK_SHIFT 28 /**< Shift value for CMU_DBGCLK */
<> 150:02e0a0aed4ec 216 #define _CMU_CTRL_DBGCLK_MASK 0x10000000UL /**< Bit mask for CMU_DBGCLK */
<> 150:02e0a0aed4ec 217 #define _CMU_CTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 218 #define _CMU_CTRL_DBGCLK_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_CTRL */
<> 150:02e0a0aed4ec 219 #define _CMU_CTRL_DBGCLK_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_CTRL */
<> 150:02e0a0aed4ec 220 #define CMU_CTRL_DBGCLK_DEFAULT (_CMU_CTRL_DBGCLK_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 221 #define CMU_CTRL_DBGCLK_AUXHFRCO (_CMU_CTRL_DBGCLK_AUXHFRCO << 28) /**< Shifted mode AUXHFRCO for CMU_CTRL */
<> 150:02e0a0aed4ec 222 #define CMU_CTRL_DBGCLK_HFCLK (_CMU_CTRL_DBGCLK_HFCLK << 28) /**< Shifted mode HFCLK for CMU_CTRL */
<> 150:02e0a0aed4ec 223 #define CMU_CTRL_HFLE (0x1UL << 30) /**< High-Frequency LE Interface */
<> 150:02e0a0aed4ec 224 #define _CMU_CTRL_HFLE_SHIFT 30 /**< Shift value for CMU_HFLE */
<> 150:02e0a0aed4ec 225 #define _CMU_CTRL_HFLE_MASK 0x40000000UL /**< Bit mask for CMU_HFLE */
<> 150:02e0a0aed4ec 226 #define _CMU_CTRL_HFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 227 #define CMU_CTRL_HFLE_DEFAULT (_CMU_CTRL_HFLE_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 228
<> 150:02e0a0aed4ec 229 /* Bit fields for CMU HFCORECLKDIV */
<> 150:02e0a0aed4ec 230 #define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 231 #define _CMU_HFCORECLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 232 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0 /**< Shift value for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 233 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 234 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 235 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 236 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 237 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 238 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 239 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 240 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 241 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 242 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 243 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 244 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 245 #define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 246 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 247 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 248 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 249 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 250 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 251 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 252 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 253 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 254 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 255 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 256 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV (0x1UL << 8) /**< Additional Division Factor For HFCORECLKLE */
<> 150:02e0a0aed4ec 257 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT 8 /**< Shift value for CMU_HFCORECLKLEDIV */
<> 150:02e0a0aed4ec 258 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK 0x100UL /**< Bit mask for CMU_HFCORECLKLEDIV */
<> 150:02e0a0aed4ec 259 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 260 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 261 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 262 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 263 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8) /**< Shifted mode DIV2 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 264 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8) /**< Shifted mode DIV4 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 265
<> 150:02e0a0aed4ec 266 /* Bit fields for CMU HFPERCLKDIV */
<> 150:02e0a0aed4ec 267 #define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL /**< Default value for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 268 #define _CMU_HFPERCLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 269 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0 /**< Shift value for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 270 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 271 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 272 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 273 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 274 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 275 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 276 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 277 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 278 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 279 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 280 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 281 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 282 #define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 283 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 284 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 285 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 286 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 287 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 288 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 289 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 290 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 291 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 292 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 293 #define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8) /**< HFPERCLK Enable */
<> 150:02e0a0aed4ec 294 #define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8 /**< Shift value for CMU_HFPERCLKEN */
<> 150:02e0a0aed4ec 295 #define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL /**< Bit mask for CMU_HFPERCLKEN */
<> 150:02e0a0aed4ec 296 #define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 297 #define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 298
<> 150:02e0a0aed4ec 299 /* Bit fields for CMU HFRCOCTRL */
<> 150:02e0a0aed4ec 300 #define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL /**< Default value for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 301 #define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL /**< Mask for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 302 #define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */
<> 150:02e0a0aed4ec 303 #define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */
<> 150:02e0a0aed4ec 304 #define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 305 #define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 306 #define _CMU_HFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */
<> 150:02e0a0aed4ec 307 #define _CMU_HFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */
<> 150:02e0a0aed4ec 308 #define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL /**< Mode 1MHZ for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 309 #define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL /**< Mode 7MHZ for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 310 #define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL /**< Mode 11MHZ for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 311 #define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 312 #define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL /**< Mode 14MHZ for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 313 #define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL /**< Mode 21MHZ for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 314 #define _CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL /**< Mode 28MHZ for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 315 #define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 316 #define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 317 #define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 318 #define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 319 #define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 320 #define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 321 #define CMU_HFRCOCTRL_BAND_28MHZ (_CMU_HFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 322 #define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12 /**< Shift value for CMU_SUDELAY */
<> 150:02e0a0aed4ec 323 #define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL /**< Bit mask for CMU_SUDELAY */
<> 150:02e0a0aed4ec 324 #define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 325 #define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 326
<> 150:02e0a0aed4ec 327 /* Bit fields for CMU LFRCOCTRL */
<> 150:02e0a0aed4ec 328 #define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL /**< Default value for CMU_LFRCOCTRL */
<> 150:02e0a0aed4ec 329 #define _CMU_LFRCOCTRL_MASK 0x0000007FUL /**< Mask for CMU_LFRCOCTRL */
<> 150:02e0a0aed4ec 330 #define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */
<> 150:02e0a0aed4ec 331 #define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */
<> 150:02e0a0aed4ec 332 #define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL /**< Mode DEFAULT for CMU_LFRCOCTRL */
<> 150:02e0a0aed4ec 333 #define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */
<> 150:02e0a0aed4ec 334
<> 150:02e0a0aed4ec 335 /* Bit fields for CMU AUXHFRCOCTRL */
<> 150:02e0a0aed4ec 336 #define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL /**< Default value for CMU_AUXHFRCOCTRL */
<> 150:02e0a0aed4ec 337 #define _CMU_AUXHFRCOCTRL_MASK 0x000007FFUL /**< Mask for CMU_AUXHFRCOCTRL */
<> 150:02e0a0aed4ec 338 #define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */
<> 150:02e0a0aed4ec 339 #define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */
<> 150:02e0a0aed4ec 340 #define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
<> 150:02e0a0aed4ec 341 #define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
<> 150:02e0a0aed4ec 342 #define _CMU_AUXHFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */
<> 150:02e0a0aed4ec 343 #define _CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */
<> 150:02e0a0aed4ec 344 #define _CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
<> 150:02e0a0aed4ec 345 #define _CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL /**< Mode 14MHZ for CMU_AUXHFRCOCTRL */
<> 150:02e0a0aed4ec 346 #define _CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL /**< Mode 11MHZ for CMU_AUXHFRCOCTRL */
<> 150:02e0a0aed4ec 347 #define _CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL /**< Mode 7MHZ for CMU_AUXHFRCOCTRL */
<> 150:02e0a0aed4ec 348 #define _CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL /**< Mode 1MHZ for CMU_AUXHFRCOCTRL */
<> 150:02e0a0aed4ec 349 #define _CMU_AUXHFRCOCTRL_BAND_28MHZ 0x00000006UL /**< Mode 28MHZ for CMU_AUXHFRCOCTRL */
<> 150:02e0a0aed4ec 350 #define _CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL /**< Mode 21MHZ for CMU_AUXHFRCOCTRL */
<> 150:02e0a0aed4ec 351 #define CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
<> 150:02e0a0aed4ec 352 #define CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_AUXHFRCOCTRL */
<> 150:02e0a0aed4ec 353 #define CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_AUXHFRCOCTRL */
<> 150:02e0a0aed4ec 354 #define CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_AUXHFRCOCTRL */
<> 150:02e0a0aed4ec 355 #define CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_AUXHFRCOCTRL */
<> 150:02e0a0aed4ec 356 #define CMU_AUXHFRCOCTRL_BAND_28MHZ (_CMU_AUXHFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_AUXHFRCOCTRL */
<> 150:02e0a0aed4ec 357 #define CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_AUXHFRCOCTRL */
<> 150:02e0a0aed4ec 358
<> 150:02e0a0aed4ec 359 /* Bit fields for CMU CALCTRL */
<> 150:02e0a0aed4ec 360 #define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */
<> 150:02e0a0aed4ec 361 #define _CMU_CALCTRL_MASK 0x0000007FUL /**< Mask for CMU_CALCTRL */
<> 150:02e0a0aed4ec 362 #define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */
<> 150:02e0a0aed4ec 363 #define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */
<> 150:02e0a0aed4ec 364 #define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */
<> 150:02e0a0aed4ec 365 #define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 366 #define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 367 #define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 368 #define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 369 #define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 370 #define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */
<> 150:02e0a0aed4ec 371 #define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 372 #define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 373 #define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 374 #define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 375 #define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 376 #define _CMU_CALCTRL_DOWNSEL_SHIFT 3 /**< Shift value for CMU_DOWNSEL */
<> 150:02e0a0aed4ec 377 #define _CMU_CALCTRL_DOWNSEL_MASK 0x38UL /**< Bit mask for CMU_DOWNSEL */
<> 150:02e0a0aed4ec 378 #define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */
<> 150:02e0a0aed4ec 379 #define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */
<> 150:02e0a0aed4ec 380 #define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 381 #define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 382 #define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 383 #define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 384 #define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 385 #define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CALCTRL */
<> 150:02e0a0aed4ec 386 #define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3) /**< Shifted mode HFCLK for CMU_CALCTRL */
<> 150:02e0a0aed4ec 387 #define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 388 #define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 389 #define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3) /**< Shifted mode HFRCO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 390 #define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3) /**< Shifted mode LFRCO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 391 #define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 392 #define CMU_CALCTRL_CONT (0x1UL << 6) /**< Continuous Calibration */
<> 150:02e0a0aed4ec 393 #define _CMU_CALCTRL_CONT_SHIFT 6 /**< Shift value for CMU_CONT */
<> 150:02e0a0aed4ec 394 #define _CMU_CALCTRL_CONT_MASK 0x40UL /**< Bit mask for CMU_CONT */
<> 150:02e0a0aed4ec 395 #define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */
<> 150:02e0a0aed4ec 396 #define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CALCTRL */
<> 150:02e0a0aed4ec 397
<> 150:02e0a0aed4ec 398 /* Bit fields for CMU CALCNT */
<> 150:02e0a0aed4ec 399 #define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */
<> 150:02e0a0aed4ec 400 #define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */
<> 150:02e0a0aed4ec 401 #define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */
<> 150:02e0a0aed4ec 402 #define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */
<> 150:02e0a0aed4ec 403 #define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */
<> 150:02e0a0aed4ec 404 #define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */
<> 150:02e0a0aed4ec 405
<> 150:02e0a0aed4ec 406 /* Bit fields for CMU OSCENCMD */
<> 150:02e0a0aed4ec 407 #define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 408 #define _CMU_OSCENCMD_MASK 0x000003FFUL /**< Mask for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 409 #define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */
<> 150:02e0a0aed4ec 410 #define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */
<> 150:02e0a0aed4ec 411 #define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */
<> 150:02e0a0aed4ec 412 #define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 413 #define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 414 #define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */
<> 150:02e0a0aed4ec 415 #define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */
<> 150:02e0a0aed4ec 416 #define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */
<> 150:02e0a0aed4ec 417 #define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 418 #define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 419 #define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */
<> 150:02e0a0aed4ec 420 #define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */
<> 150:02e0a0aed4ec 421 #define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */
<> 150:02e0a0aed4ec 422 #define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 423 #define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 424 #define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */
<> 150:02e0a0aed4ec 425 #define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */
<> 150:02e0a0aed4ec 426 #define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */
<> 150:02e0a0aed4ec 427 #define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 428 #define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 429 #define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */
<> 150:02e0a0aed4ec 430 #define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */
<> 150:02e0a0aed4ec 431 #define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */
<> 150:02e0a0aed4ec 432 #define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 433 #define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 434 #define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */
<> 150:02e0a0aed4ec 435 #define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */
<> 150:02e0a0aed4ec 436 #define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */
<> 150:02e0a0aed4ec 437 #define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 438 #define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 439 #define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */
<> 150:02e0a0aed4ec 440 #define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */
<> 150:02e0a0aed4ec 441 #define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */
<> 150:02e0a0aed4ec 442 #define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 443 #define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 444 #define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */
<> 150:02e0a0aed4ec 445 #define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */
<> 150:02e0a0aed4ec 446 #define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */
<> 150:02e0a0aed4ec 447 #define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 448 #define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 449 #define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */
<> 150:02e0a0aed4ec 450 #define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */
<> 150:02e0a0aed4ec 451 #define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */
<> 150:02e0a0aed4ec 452 #define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 453 #define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 454 #define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */
<> 150:02e0a0aed4ec 455 #define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */
<> 150:02e0a0aed4ec 456 #define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */
<> 150:02e0a0aed4ec 457 #define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 458 #define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 459
<> 150:02e0a0aed4ec 460 /* Bit fields for CMU CMD */
<> 150:02e0a0aed4ec 461 #define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */
<> 150:02e0a0aed4ec 462 #define _CMU_CMD_MASK 0x000000FFUL /**< Mask for CMU_CMD */
<> 150:02e0a0aed4ec 463 #define _CMU_CMD_HFCLKSEL_SHIFT 0 /**< Shift value for CMU_HFCLKSEL */
<> 150:02e0a0aed4ec 464 #define _CMU_CMD_HFCLKSEL_MASK 0x7UL /**< Bit mask for CMU_HFCLKSEL */
<> 150:02e0a0aed4ec 465 #define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */
<> 150:02e0a0aed4ec 466 #define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_CMD */
<> 150:02e0a0aed4ec 467 #define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CMD */
<> 150:02e0a0aed4ec 468 #define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */
<> 150:02e0a0aed4ec 469 #define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CMD */
<> 150:02e0a0aed4ec 470 #define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */
<> 150:02e0a0aed4ec 471 #define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CMD */
<> 150:02e0a0aed4ec 472 #define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CMD */
<> 150:02e0a0aed4ec 473 #define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CMD */
<> 150:02e0a0aed4ec 474 #define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CMD */
<> 150:02e0a0aed4ec 475 #define CMU_CMD_CALSTART (0x1UL << 3) /**< Calibration Start */
<> 150:02e0a0aed4ec 476 #define _CMU_CMD_CALSTART_SHIFT 3 /**< Shift value for CMU_CALSTART */
<> 150:02e0a0aed4ec 477 #define _CMU_CMD_CALSTART_MASK 0x8UL /**< Bit mask for CMU_CALSTART */
<> 150:02e0a0aed4ec 478 #define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */
<> 150:02e0a0aed4ec 479 #define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CMD */
<> 150:02e0a0aed4ec 480 #define CMU_CMD_CALSTOP (0x1UL << 4) /**< Calibration Stop */
<> 150:02e0a0aed4ec 481 #define _CMU_CMD_CALSTOP_SHIFT 4 /**< Shift value for CMU_CALSTOP */
<> 150:02e0a0aed4ec 482 #define _CMU_CMD_CALSTOP_MASK 0x10UL /**< Bit mask for CMU_CALSTOP */
<> 150:02e0a0aed4ec 483 #define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */
<> 150:02e0a0aed4ec 484 #define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */
<> 150:02e0a0aed4ec 485 #define _CMU_CMD_USBCCLKSEL_SHIFT 5 /**< Shift value for CMU_USBCCLKSEL */
<> 150:02e0a0aed4ec 486 #define _CMU_CMD_USBCCLKSEL_MASK 0xE0UL /**< Bit mask for CMU_USBCCLKSEL */
<> 150:02e0a0aed4ec 487 #define _CMU_CMD_USBCCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */
<> 150:02e0a0aed4ec 488 #define _CMU_CMD_USBCCLKSEL_HFCLKNODIV 0x00000001UL /**< Mode HFCLKNODIV for CMU_CMD */
<> 150:02e0a0aed4ec 489 #define _CMU_CMD_USBCCLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CMD */
<> 150:02e0a0aed4ec 490 #define _CMU_CMD_USBCCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */
<> 150:02e0a0aed4ec 491 #define CMU_CMD_USBCCLKSEL_DEFAULT (_CMU_CMD_USBCCLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CMD */
<> 150:02e0a0aed4ec 492 #define CMU_CMD_USBCCLKSEL_HFCLKNODIV (_CMU_CMD_USBCCLKSEL_HFCLKNODIV << 5) /**< Shifted mode HFCLKNODIV for CMU_CMD */
<> 150:02e0a0aed4ec 493 #define CMU_CMD_USBCCLKSEL_LFXO (_CMU_CMD_USBCCLKSEL_LFXO << 5) /**< Shifted mode LFXO for CMU_CMD */
<> 150:02e0a0aed4ec 494 #define CMU_CMD_USBCCLKSEL_LFRCO (_CMU_CMD_USBCCLKSEL_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CMD */
<> 150:02e0a0aed4ec 495
<> 150:02e0a0aed4ec 496 /* Bit fields for CMU LFCLKSEL */
<> 150:02e0a0aed4ec 497 #define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL /**< Default value for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 498 #define _CMU_LFCLKSEL_MASK 0x0011000FUL /**< Mask for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 499 #define _CMU_LFCLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */
<> 150:02e0a0aed4ec 500 #define _CMU_LFCLKSEL_LFA_MASK 0x3UL /**< Bit mask for CMU_LFA */
<> 150:02e0a0aed4ec 501 #define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 502 #define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 503 #define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 504 #define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 505 #define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 506 #define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 507 #define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 508 #define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 509 #define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 510 #define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 511 #define _CMU_LFCLKSEL_LFB_SHIFT 2 /**< Shift value for CMU_LFB */
<> 150:02e0a0aed4ec 512 #define _CMU_LFCLKSEL_LFB_MASK 0xCUL /**< Bit mask for CMU_LFB */
<> 150:02e0a0aed4ec 513 #define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 514 #define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 515 #define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 516 #define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 517 #define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 518 #define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2) /**< Shifted mode DISABLED for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 519 #define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 520 #define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2) /**< Shifted mode LFRCO for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 521 #define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2) /**< Shifted mode LFXO for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 522 #define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 523 #define CMU_LFCLKSEL_LFAE (0x1UL << 16) /**< Clock Select for LFA Extended */
<> 150:02e0a0aed4ec 524 #define _CMU_LFCLKSEL_LFAE_SHIFT 16 /**< Shift value for CMU_LFAE */
<> 150:02e0a0aed4ec 525 #define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL /**< Bit mask for CMU_LFAE */
<> 150:02e0a0aed4ec 526 #define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 527 #define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 528 #define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 529 #define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 530 #define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16) /**< Shifted mode DISABLED for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 531 #define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 532 #define CMU_LFCLKSEL_LFBE (0x1UL << 20) /**< Clock Select for LFB Extended */
<> 150:02e0a0aed4ec 533 #define _CMU_LFCLKSEL_LFBE_SHIFT 20 /**< Shift value for CMU_LFBE */
<> 150:02e0a0aed4ec 534 #define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL /**< Bit mask for CMU_LFBE */
<> 150:02e0a0aed4ec 535 #define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 536 #define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 537 #define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 538 #define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 539 #define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20) /**< Shifted mode DISABLED for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 540 #define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 541
<> 150:02e0a0aed4ec 542 /* Bit fields for CMU STATUS */
<> 150:02e0a0aed4ec 543 #define _CMU_STATUS_RESETVALUE 0x00000403UL /**< Default value for CMU_STATUS */
<> 150:02e0a0aed4ec 544 #define _CMU_STATUS_MASK 0x0003FFFFUL /**< Mask for CMU_STATUS */
<> 150:02e0a0aed4ec 545 #define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */
<> 150:02e0a0aed4ec 546 #define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */
<> 150:02e0a0aed4ec 547 #define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */
<> 150:02e0a0aed4ec 548 #define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 549 #define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 550 #define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */
<> 150:02e0a0aed4ec 551 #define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */
<> 150:02e0a0aed4ec 552 #define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */
<> 150:02e0a0aed4ec 553 #define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 554 #define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 555 #define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */
<> 150:02e0a0aed4ec 556 #define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */
<> 150:02e0a0aed4ec 557 #define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */
<> 150:02e0a0aed4ec 558 #define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 559 #define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 560 #define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */
<> 150:02e0a0aed4ec 561 #define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */
<> 150:02e0a0aed4ec 562 #define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */
<> 150:02e0a0aed4ec 563 #define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 564 #define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 565 #define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */
<> 150:02e0a0aed4ec 566 #define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */
<> 150:02e0a0aed4ec 567 #define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */
<> 150:02e0a0aed4ec 568 #define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 569 #define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 570 #define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */
<> 150:02e0a0aed4ec 571 #define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */
<> 150:02e0a0aed4ec 572 #define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */
<> 150:02e0a0aed4ec 573 #define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 574 #define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 575 #define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */
<> 150:02e0a0aed4ec 576 #define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */
<> 150:02e0a0aed4ec 577 #define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */
<> 150:02e0a0aed4ec 578 #define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 579 #define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 580 #define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */
<> 150:02e0a0aed4ec 581 #define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */
<> 150:02e0a0aed4ec 582 #define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */
<> 150:02e0a0aed4ec 583 #define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 584 #define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 585 #define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */
<> 150:02e0a0aed4ec 586 #define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */
<> 150:02e0a0aed4ec 587 #define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */
<> 150:02e0a0aed4ec 588 #define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 589 #define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 590 #define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */
<> 150:02e0a0aed4ec 591 #define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */
<> 150:02e0a0aed4ec 592 #define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */
<> 150:02e0a0aed4ec 593 #define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 594 #define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 595 #define CMU_STATUS_HFRCOSEL (0x1UL << 10) /**< HFRCO Selected */
<> 150:02e0a0aed4ec 596 #define _CMU_STATUS_HFRCOSEL_SHIFT 10 /**< Shift value for CMU_HFRCOSEL */
<> 150:02e0a0aed4ec 597 #define _CMU_STATUS_HFRCOSEL_MASK 0x400UL /**< Bit mask for CMU_HFRCOSEL */
<> 150:02e0a0aed4ec 598 #define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 599 #define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 600 #define CMU_STATUS_HFXOSEL (0x1UL << 11) /**< HFXO Selected */
<> 150:02e0a0aed4ec 601 #define _CMU_STATUS_HFXOSEL_SHIFT 11 /**< Shift value for CMU_HFXOSEL */
<> 150:02e0a0aed4ec 602 #define _CMU_STATUS_HFXOSEL_MASK 0x800UL /**< Bit mask for CMU_HFXOSEL */
<> 150:02e0a0aed4ec 603 #define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 604 #define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 605 #define CMU_STATUS_LFRCOSEL (0x1UL << 12) /**< LFRCO Selected */
<> 150:02e0a0aed4ec 606 #define _CMU_STATUS_LFRCOSEL_SHIFT 12 /**< Shift value for CMU_LFRCOSEL */
<> 150:02e0a0aed4ec 607 #define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL /**< Bit mask for CMU_LFRCOSEL */
<> 150:02e0a0aed4ec 608 #define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 609 #define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 610 #define CMU_STATUS_LFXOSEL (0x1UL << 13) /**< LFXO Selected */
<> 150:02e0a0aed4ec 611 #define _CMU_STATUS_LFXOSEL_SHIFT 13 /**< Shift value for CMU_LFXOSEL */
<> 150:02e0a0aed4ec 612 #define _CMU_STATUS_LFXOSEL_MASK 0x2000UL /**< Bit mask for CMU_LFXOSEL */
<> 150:02e0a0aed4ec 613 #define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 614 #define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 615 #define CMU_STATUS_CALBSY (0x1UL << 14) /**< Calibration Busy */
<> 150:02e0a0aed4ec 616 #define _CMU_STATUS_CALBSY_SHIFT 14 /**< Shift value for CMU_CALBSY */
<> 150:02e0a0aed4ec 617 #define _CMU_STATUS_CALBSY_MASK 0x4000UL /**< Bit mask for CMU_CALBSY */
<> 150:02e0a0aed4ec 618 #define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 619 #define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 620 #define CMU_STATUS_USBCHFCLKSEL (0x1UL << 15) /**< USBC HFCLK Selected */
<> 150:02e0a0aed4ec 621 #define _CMU_STATUS_USBCHFCLKSEL_SHIFT 15 /**< Shift value for CMU_USBCHFCLKSEL */
<> 150:02e0a0aed4ec 622 #define _CMU_STATUS_USBCHFCLKSEL_MASK 0x8000UL /**< Bit mask for CMU_USBCHFCLKSEL */
<> 150:02e0a0aed4ec 623 #define _CMU_STATUS_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 624 #define CMU_STATUS_USBCHFCLKSEL_DEFAULT (_CMU_STATUS_USBCHFCLKSEL_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 625 #define CMU_STATUS_USBCLFXOSEL (0x1UL << 16) /**< USBC LFXO Selected */
<> 150:02e0a0aed4ec 626 #define _CMU_STATUS_USBCLFXOSEL_SHIFT 16 /**< Shift value for CMU_USBCLFXOSEL */
<> 150:02e0a0aed4ec 627 #define _CMU_STATUS_USBCLFXOSEL_MASK 0x10000UL /**< Bit mask for CMU_USBCLFXOSEL */
<> 150:02e0a0aed4ec 628 #define _CMU_STATUS_USBCLFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 629 #define CMU_STATUS_USBCLFXOSEL_DEFAULT (_CMU_STATUS_USBCLFXOSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 630 #define CMU_STATUS_USBCLFRCOSEL (0x1UL << 17) /**< USBC LFRCO Selected */
<> 150:02e0a0aed4ec 631 #define _CMU_STATUS_USBCLFRCOSEL_SHIFT 17 /**< Shift value for CMU_USBCLFRCOSEL */
<> 150:02e0a0aed4ec 632 #define _CMU_STATUS_USBCLFRCOSEL_MASK 0x20000UL /**< Bit mask for CMU_USBCLFRCOSEL */
<> 150:02e0a0aed4ec 633 #define _CMU_STATUS_USBCLFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 634 #define CMU_STATUS_USBCLFRCOSEL_DEFAULT (_CMU_STATUS_USBCLFRCOSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 635
<> 150:02e0a0aed4ec 636 /* Bit fields for CMU IF */
<> 150:02e0a0aed4ec 637 #define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */
<> 150:02e0a0aed4ec 638 #define _CMU_IF_MASK 0x000000FFUL /**< Mask for CMU_IF */
<> 150:02e0a0aed4ec 639 #define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */
<> 150:02e0a0aed4ec 640 #define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */
<> 150:02e0a0aed4ec 641 #define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */
<> 150:02e0a0aed4ec 642 #define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */
<> 150:02e0a0aed4ec 643 #define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */
<> 150:02e0a0aed4ec 644 #define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */
<> 150:02e0a0aed4ec 645 #define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */
<> 150:02e0a0aed4ec 646 #define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */
<> 150:02e0a0aed4ec 647 #define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
<> 150:02e0a0aed4ec 648 #define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */
<> 150:02e0a0aed4ec 649 #define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */
<> 150:02e0a0aed4ec 650 #define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */
<> 150:02e0a0aed4ec 651 #define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */
<> 150:02e0a0aed4ec 652 #define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
<> 150:02e0a0aed4ec 653 #define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */
<> 150:02e0a0aed4ec 654 #define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */
<> 150:02e0a0aed4ec 655 #define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */
<> 150:02e0a0aed4ec 656 #define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */
<> 150:02e0a0aed4ec 657 #define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
<> 150:02e0a0aed4ec 658 #define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */
<> 150:02e0a0aed4ec 659 #define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */
<> 150:02e0a0aed4ec 660 #define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */
<> 150:02e0a0aed4ec 661 #define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */
<> 150:02e0a0aed4ec 662 #define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
<> 150:02e0a0aed4ec 663 #define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */
<> 150:02e0a0aed4ec 664 #define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */
<> 150:02e0a0aed4ec 665 #define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */
<> 150:02e0a0aed4ec 666 #define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */
<> 150:02e0a0aed4ec 667 #define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
<> 150:02e0a0aed4ec 668 #define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */
<> 150:02e0a0aed4ec 669 #define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */
<> 150:02e0a0aed4ec 670 #define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */
<> 150:02e0a0aed4ec 671 #define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */
<> 150:02e0a0aed4ec 672 #define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
<> 150:02e0a0aed4ec 673 #define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */
<> 150:02e0a0aed4ec 674 #define CMU_IF_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Flag */
<> 150:02e0a0aed4ec 675 #define _CMU_IF_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */
<> 150:02e0a0aed4ec 676 #define _CMU_IF_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */
<> 150:02e0a0aed4ec 677 #define _CMU_IF_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
<> 150:02e0a0aed4ec 678 #define CMU_IF_USBCHFCLKSEL_DEFAULT (_CMU_IF_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IF */
<> 150:02e0a0aed4ec 679
<> 150:02e0a0aed4ec 680 /* Bit fields for CMU IFS */
<> 150:02e0a0aed4ec 681 #define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */
<> 150:02e0a0aed4ec 682 #define _CMU_IFS_MASK 0x000000FFUL /**< Mask for CMU_IFS */
<> 150:02e0a0aed4ec 683 #define CMU_IFS_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Set */
<> 150:02e0a0aed4ec 684 #define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */
<> 150:02e0a0aed4ec 685 #define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */
<> 150:02e0a0aed4ec 686 #define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
<> 150:02e0a0aed4ec 687 #define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */
<> 150:02e0a0aed4ec 688 #define CMU_IFS_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Set */
<> 150:02e0a0aed4ec 689 #define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */
<> 150:02e0a0aed4ec 690 #define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */
<> 150:02e0a0aed4ec 691 #define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
<> 150:02e0a0aed4ec 692 #define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */
<> 150:02e0a0aed4ec 693 #define CMU_IFS_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Set */
<> 150:02e0a0aed4ec 694 #define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */
<> 150:02e0a0aed4ec 695 #define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */
<> 150:02e0a0aed4ec 696 #define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
<> 150:02e0a0aed4ec 697 #define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */
<> 150:02e0a0aed4ec 698 #define CMU_IFS_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Set */
<> 150:02e0a0aed4ec 699 #define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */
<> 150:02e0a0aed4ec 700 #define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */
<> 150:02e0a0aed4ec 701 #define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
<> 150:02e0a0aed4ec 702 #define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */
<> 150:02e0a0aed4ec 703 #define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Set */
<> 150:02e0a0aed4ec 704 #define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */
<> 150:02e0a0aed4ec 705 #define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */
<> 150:02e0a0aed4ec 706 #define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
<> 150:02e0a0aed4ec 707 #define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */
<> 150:02e0a0aed4ec 708 #define CMU_IFS_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Set */
<> 150:02e0a0aed4ec 709 #define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */
<> 150:02e0a0aed4ec 710 #define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */
<> 150:02e0a0aed4ec 711 #define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
<> 150:02e0a0aed4ec 712 #define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */
<> 150:02e0a0aed4ec 713 #define CMU_IFS_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Set */
<> 150:02e0a0aed4ec 714 #define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */
<> 150:02e0a0aed4ec 715 #define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */
<> 150:02e0a0aed4ec 716 #define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
<> 150:02e0a0aed4ec 717 #define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */
<> 150:02e0a0aed4ec 718 #define CMU_IFS_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Flag Set */
<> 150:02e0a0aed4ec 719 #define _CMU_IFS_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */
<> 150:02e0a0aed4ec 720 #define _CMU_IFS_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */
<> 150:02e0a0aed4ec 721 #define _CMU_IFS_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
<> 150:02e0a0aed4ec 722 #define CMU_IFS_USBCHFCLKSEL_DEFAULT (_CMU_IFS_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFS */
<> 150:02e0a0aed4ec 723
<> 150:02e0a0aed4ec 724 /* Bit fields for CMU IFC */
<> 150:02e0a0aed4ec 725 #define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */
<> 150:02e0a0aed4ec 726 #define _CMU_IFC_MASK 0x000000FFUL /**< Mask for CMU_IFC */
<> 150:02e0a0aed4ec 727 #define CMU_IFC_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Clear */
<> 150:02e0a0aed4ec 728 #define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */
<> 150:02e0a0aed4ec 729 #define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */
<> 150:02e0a0aed4ec 730 #define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
<> 150:02e0a0aed4ec 731 #define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */
<> 150:02e0a0aed4ec 732 #define CMU_IFC_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Clear */
<> 150:02e0a0aed4ec 733 #define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */
<> 150:02e0a0aed4ec 734 #define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */
<> 150:02e0a0aed4ec 735 #define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
<> 150:02e0a0aed4ec 736 #define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */
<> 150:02e0a0aed4ec 737 #define CMU_IFC_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Clear */
<> 150:02e0a0aed4ec 738 #define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */
<> 150:02e0a0aed4ec 739 #define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */
<> 150:02e0a0aed4ec 740 #define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
<> 150:02e0a0aed4ec 741 #define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */
<> 150:02e0a0aed4ec 742 #define CMU_IFC_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Clear */
<> 150:02e0a0aed4ec 743 #define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */
<> 150:02e0a0aed4ec 744 #define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */
<> 150:02e0a0aed4ec 745 #define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
<> 150:02e0a0aed4ec 746 #define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */
<> 150:02e0a0aed4ec 747 #define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Clear */
<> 150:02e0a0aed4ec 748 #define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */
<> 150:02e0a0aed4ec 749 #define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */
<> 150:02e0a0aed4ec 750 #define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
<> 150:02e0a0aed4ec 751 #define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */
<> 150:02e0a0aed4ec 752 #define CMU_IFC_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Clear */
<> 150:02e0a0aed4ec 753 #define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */
<> 150:02e0a0aed4ec 754 #define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */
<> 150:02e0a0aed4ec 755 #define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
<> 150:02e0a0aed4ec 756 #define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */
<> 150:02e0a0aed4ec 757 #define CMU_IFC_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Clear */
<> 150:02e0a0aed4ec 758 #define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */
<> 150:02e0a0aed4ec 759 #define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */
<> 150:02e0a0aed4ec 760 #define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
<> 150:02e0a0aed4ec 761 #define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */
<> 150:02e0a0aed4ec 762 #define CMU_IFC_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Flag Clear */
<> 150:02e0a0aed4ec 763 #define _CMU_IFC_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */
<> 150:02e0a0aed4ec 764 #define _CMU_IFC_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */
<> 150:02e0a0aed4ec 765 #define _CMU_IFC_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
<> 150:02e0a0aed4ec 766 #define CMU_IFC_USBCHFCLKSEL_DEFAULT (_CMU_IFC_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFC */
<> 150:02e0a0aed4ec 767
<> 150:02e0a0aed4ec 768 /* Bit fields for CMU IEN */
<> 150:02e0a0aed4ec 769 #define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */
<> 150:02e0a0aed4ec 770 #define _CMU_IEN_MASK 0x000000FFUL /**< Mask for CMU_IEN */
<> 150:02e0a0aed4ec 771 #define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Enable */
<> 150:02e0a0aed4ec 772 #define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */
<> 150:02e0a0aed4ec 773 #define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */
<> 150:02e0a0aed4ec 774 #define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
<> 150:02e0a0aed4ec 775 #define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */
<> 150:02e0a0aed4ec 776 #define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Enable */
<> 150:02e0a0aed4ec 777 #define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */
<> 150:02e0a0aed4ec 778 #define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */
<> 150:02e0a0aed4ec 779 #define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
<> 150:02e0a0aed4ec 780 #define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */
<> 150:02e0a0aed4ec 781 #define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Enable */
<> 150:02e0a0aed4ec 782 #define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */
<> 150:02e0a0aed4ec 783 #define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */
<> 150:02e0a0aed4ec 784 #define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
<> 150:02e0a0aed4ec 785 #define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */
<> 150:02e0a0aed4ec 786 #define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Enable */
<> 150:02e0a0aed4ec 787 #define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */
<> 150:02e0a0aed4ec 788 #define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */
<> 150:02e0a0aed4ec 789 #define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
<> 150:02e0a0aed4ec 790 #define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */
<> 150:02e0a0aed4ec 791 #define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Enable */
<> 150:02e0a0aed4ec 792 #define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */
<> 150:02e0a0aed4ec 793 #define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */
<> 150:02e0a0aed4ec 794 #define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
<> 150:02e0a0aed4ec 795 #define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */
<> 150:02e0a0aed4ec 796 #define CMU_IEN_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Enable */
<> 150:02e0a0aed4ec 797 #define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */
<> 150:02e0a0aed4ec 798 #define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */
<> 150:02e0a0aed4ec 799 #define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
<> 150:02e0a0aed4ec 800 #define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */
<> 150:02e0a0aed4ec 801 #define CMU_IEN_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Enable */
<> 150:02e0a0aed4ec 802 #define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */
<> 150:02e0a0aed4ec 803 #define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */
<> 150:02e0a0aed4ec 804 #define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
<> 150:02e0a0aed4ec 805 #define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */
<> 150:02e0a0aed4ec 806 #define CMU_IEN_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Enable */
<> 150:02e0a0aed4ec 807 #define _CMU_IEN_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */
<> 150:02e0a0aed4ec 808 #define _CMU_IEN_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */
<> 150:02e0a0aed4ec 809 #define _CMU_IEN_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
<> 150:02e0a0aed4ec 810 #define CMU_IEN_USBCHFCLKSEL_DEFAULT (_CMU_IEN_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IEN */
<> 150:02e0a0aed4ec 811
<> 150:02e0a0aed4ec 812 /* Bit fields for CMU HFCORECLKEN0 */
<> 150:02e0a0aed4ec 813 #define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKEN0 */
<> 150:02e0a0aed4ec 814 #define _CMU_HFCORECLKEN0_MASK 0x0000003FUL /**< Mask for CMU_HFCORECLKEN0 */
<> 150:02e0a0aed4ec 815 #define CMU_HFCORECLKEN0_DMA (0x1UL << 0) /**< Direct Memory Access Controller Clock Enable */
<> 150:02e0a0aed4ec 816 #define _CMU_HFCORECLKEN0_DMA_SHIFT 0 /**< Shift value for CMU_DMA */
<> 150:02e0a0aed4ec 817 #define _CMU_HFCORECLKEN0_DMA_MASK 0x1UL /**< Bit mask for CMU_DMA */
<> 150:02e0a0aed4ec 818 #define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */
<> 150:02e0a0aed4ec 819 #define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */
<> 150:02e0a0aed4ec 820 #define CMU_HFCORECLKEN0_AES (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */
<> 150:02e0a0aed4ec 821 #define _CMU_HFCORECLKEN0_AES_SHIFT 1 /**< Shift value for CMU_AES */
<> 150:02e0a0aed4ec 822 #define _CMU_HFCORECLKEN0_AES_MASK 0x2UL /**< Bit mask for CMU_AES */
<> 150:02e0a0aed4ec 823 #define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */
<> 150:02e0a0aed4ec 824 #define CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */
<> 150:02e0a0aed4ec 825 #define CMU_HFCORECLKEN0_USBC (0x1UL << 2) /**< Universal Serial Bus Interface Core Clock Enable */
<> 150:02e0a0aed4ec 826 #define _CMU_HFCORECLKEN0_USBC_SHIFT 2 /**< Shift value for CMU_USBC */
<> 150:02e0a0aed4ec 827 #define _CMU_HFCORECLKEN0_USBC_MASK 0x4UL /**< Bit mask for CMU_USBC */
<> 150:02e0a0aed4ec 828 #define _CMU_HFCORECLKEN0_USBC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */
<> 150:02e0a0aed4ec 829 #define CMU_HFCORECLKEN0_USBC_DEFAULT (_CMU_HFCORECLKEN0_USBC_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */
<> 150:02e0a0aed4ec 830 #define CMU_HFCORECLKEN0_USB (0x1UL << 3) /**< Universal Serial Bus Interface Clock Enable */
<> 150:02e0a0aed4ec 831 #define _CMU_HFCORECLKEN0_USB_SHIFT 3 /**< Shift value for CMU_USB */
<> 150:02e0a0aed4ec 832 #define _CMU_HFCORECLKEN0_USB_MASK 0x8UL /**< Bit mask for CMU_USB */
<> 150:02e0a0aed4ec 833 #define _CMU_HFCORECLKEN0_USB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */
<> 150:02e0a0aed4ec 834 #define CMU_HFCORECLKEN0_USB_DEFAULT (_CMU_HFCORECLKEN0_USB_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */
<> 150:02e0a0aed4ec 835 #define CMU_HFCORECLKEN0_LE (0x1UL << 4) /**< Low Energy Peripheral Interface Clock Enable */
<> 150:02e0a0aed4ec 836 #define _CMU_HFCORECLKEN0_LE_SHIFT 4 /**< Shift value for CMU_LE */
<> 150:02e0a0aed4ec 837 #define _CMU_HFCORECLKEN0_LE_MASK 0x10UL /**< Bit mask for CMU_LE */
<> 150:02e0a0aed4ec 838 #define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */
<> 150:02e0a0aed4ec 839 #define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */
<> 150:02e0a0aed4ec 840 #define CMU_HFCORECLKEN0_EBI (0x1UL << 5) /**< External Bus Interface Clock Enable */
<> 150:02e0a0aed4ec 841 #define _CMU_HFCORECLKEN0_EBI_SHIFT 5 /**< Shift value for CMU_EBI */
<> 150:02e0a0aed4ec 842 #define _CMU_HFCORECLKEN0_EBI_MASK 0x20UL /**< Bit mask for CMU_EBI */
<> 150:02e0a0aed4ec 843 #define _CMU_HFCORECLKEN0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */
<> 150:02e0a0aed4ec 844 #define CMU_HFCORECLKEN0_EBI_DEFAULT (_CMU_HFCORECLKEN0_EBI_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */
<> 150:02e0a0aed4ec 845
<> 150:02e0a0aed4ec 846 /* Bit fields for CMU HFPERCLKEN0 */
<> 150:02e0a0aed4ec 847 #define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 848 #define _CMU_HFPERCLKEN0_MASK 0x0003FFFFUL /**< Mask for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 849 #define CMU_HFPERCLKEN0_USART0 (0x1UL << 0) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */
<> 150:02e0a0aed4ec 850 #define _CMU_HFPERCLKEN0_USART0_SHIFT 0 /**< Shift value for CMU_USART0 */
<> 150:02e0a0aed4ec 851 #define _CMU_HFPERCLKEN0_USART0_MASK 0x1UL /**< Bit mask for CMU_USART0 */
<> 150:02e0a0aed4ec 852 #define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 853 #define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 854 #define CMU_HFPERCLKEN0_USART1 (0x1UL << 1) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */
<> 150:02e0a0aed4ec 855 #define _CMU_HFPERCLKEN0_USART1_SHIFT 1 /**< Shift value for CMU_USART1 */
<> 150:02e0a0aed4ec 856 #define _CMU_HFPERCLKEN0_USART1_MASK 0x2UL /**< Bit mask for CMU_USART1 */
<> 150:02e0a0aed4ec 857 #define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 858 #define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 859 #define CMU_HFPERCLKEN0_USART2 (0x1UL << 2) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */
<> 150:02e0a0aed4ec 860 #define _CMU_HFPERCLKEN0_USART2_SHIFT 2 /**< Shift value for CMU_USART2 */
<> 150:02e0a0aed4ec 861 #define _CMU_HFPERCLKEN0_USART2_MASK 0x4UL /**< Bit mask for CMU_USART2 */
<> 150:02e0a0aed4ec 862 #define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 863 #define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 864 #define CMU_HFPERCLKEN0_UART0 (0x1UL << 3) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */
<> 150:02e0a0aed4ec 865 #define _CMU_HFPERCLKEN0_UART0_SHIFT 3 /**< Shift value for CMU_UART0 */
<> 150:02e0a0aed4ec 866 #define _CMU_HFPERCLKEN0_UART0_MASK 0x8UL /**< Bit mask for CMU_UART0 */
<> 150:02e0a0aed4ec 867 #define _CMU_HFPERCLKEN0_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 868 #define CMU_HFPERCLKEN0_UART0_DEFAULT (_CMU_HFPERCLKEN0_UART0_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 869 #define CMU_HFPERCLKEN0_UART1 (0x1UL << 4) /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */
<> 150:02e0a0aed4ec 870 #define _CMU_HFPERCLKEN0_UART1_SHIFT 4 /**< Shift value for CMU_UART1 */
<> 150:02e0a0aed4ec 871 #define _CMU_HFPERCLKEN0_UART1_MASK 0x10UL /**< Bit mask for CMU_UART1 */
<> 150:02e0a0aed4ec 872 #define _CMU_HFPERCLKEN0_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 873 #define CMU_HFPERCLKEN0_UART1_DEFAULT (_CMU_HFPERCLKEN0_UART1_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 874 #define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 5) /**< Timer 0 Clock Enable */
<> 150:02e0a0aed4ec 875 #define _CMU_HFPERCLKEN0_TIMER0_SHIFT 5 /**< Shift value for CMU_TIMER0 */
<> 150:02e0a0aed4ec 876 #define _CMU_HFPERCLKEN0_TIMER0_MASK 0x20UL /**< Bit mask for CMU_TIMER0 */
<> 150:02e0a0aed4ec 877 #define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 878 #define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 879 #define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 6) /**< Timer 1 Clock Enable */
<> 150:02e0a0aed4ec 880 #define _CMU_HFPERCLKEN0_TIMER1_SHIFT 6 /**< Shift value for CMU_TIMER1 */
<> 150:02e0a0aed4ec 881 #define _CMU_HFPERCLKEN0_TIMER1_MASK 0x40UL /**< Bit mask for CMU_TIMER1 */
<> 150:02e0a0aed4ec 882 #define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 883 #define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 884 #define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 7) /**< Timer 2 Clock Enable */
<> 150:02e0a0aed4ec 885 #define _CMU_HFPERCLKEN0_TIMER2_SHIFT 7 /**< Shift value for CMU_TIMER2 */
<> 150:02e0a0aed4ec 886 #define _CMU_HFPERCLKEN0_TIMER2_MASK 0x80UL /**< Bit mask for CMU_TIMER2 */
<> 150:02e0a0aed4ec 887 #define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 888 #define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 889 #define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 8) /**< Timer 3 Clock Enable */
<> 150:02e0a0aed4ec 890 #define _CMU_HFPERCLKEN0_TIMER3_SHIFT 8 /**< Shift value for CMU_TIMER3 */
<> 150:02e0a0aed4ec 891 #define _CMU_HFPERCLKEN0_TIMER3_MASK 0x100UL /**< Bit mask for CMU_TIMER3 */
<> 150:02e0a0aed4ec 892 #define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 893 #define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 894 #define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 9) /**< Analog Comparator 0 Clock Enable */
<> 150:02e0a0aed4ec 895 #define _CMU_HFPERCLKEN0_ACMP0_SHIFT 9 /**< Shift value for CMU_ACMP0 */
<> 150:02e0a0aed4ec 896 #define _CMU_HFPERCLKEN0_ACMP0_MASK 0x200UL /**< Bit mask for CMU_ACMP0 */
<> 150:02e0a0aed4ec 897 #define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 898 #define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 899 #define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 10) /**< Analog Comparator 1 Clock Enable */
<> 150:02e0a0aed4ec 900 #define _CMU_HFPERCLKEN0_ACMP1_SHIFT 10 /**< Shift value for CMU_ACMP1 */
<> 150:02e0a0aed4ec 901 #define _CMU_HFPERCLKEN0_ACMP1_MASK 0x400UL /**< Bit mask for CMU_ACMP1 */
<> 150:02e0a0aed4ec 902 #define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 903 #define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 904 #define CMU_HFPERCLKEN0_I2C0 (0x1UL << 11) /**< I2C 0 Clock Enable */
<> 150:02e0a0aed4ec 905 #define _CMU_HFPERCLKEN0_I2C0_SHIFT 11 /**< Shift value for CMU_I2C0 */
<> 150:02e0a0aed4ec 906 #define _CMU_HFPERCLKEN0_I2C0_MASK 0x800UL /**< Bit mask for CMU_I2C0 */
<> 150:02e0a0aed4ec 907 #define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 908 #define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 909 #define CMU_HFPERCLKEN0_I2C1 (0x1UL << 12) /**< I2C 1 Clock Enable */
<> 150:02e0a0aed4ec 910 #define _CMU_HFPERCLKEN0_I2C1_SHIFT 12 /**< Shift value for CMU_I2C1 */
<> 150:02e0a0aed4ec 911 #define _CMU_HFPERCLKEN0_I2C1_MASK 0x1000UL /**< Bit mask for CMU_I2C1 */
<> 150:02e0a0aed4ec 912 #define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 913 #define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 914 #define CMU_HFPERCLKEN0_GPIO (0x1UL << 13) /**< General purpose Input/Output Clock Enable */
<> 150:02e0a0aed4ec 915 #define _CMU_HFPERCLKEN0_GPIO_SHIFT 13 /**< Shift value for CMU_GPIO */
<> 150:02e0a0aed4ec 916 #define _CMU_HFPERCLKEN0_GPIO_MASK 0x2000UL /**< Bit mask for CMU_GPIO */
<> 150:02e0a0aed4ec 917 #define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 918 #define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 919 #define CMU_HFPERCLKEN0_VCMP (0x1UL << 14) /**< Voltage Comparator Clock Enable */
<> 150:02e0a0aed4ec 920 #define _CMU_HFPERCLKEN0_VCMP_SHIFT 14 /**< Shift value for CMU_VCMP */
<> 150:02e0a0aed4ec 921 #define _CMU_HFPERCLKEN0_VCMP_MASK 0x4000UL /**< Bit mask for CMU_VCMP */
<> 150:02e0a0aed4ec 922 #define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 923 #define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 924 #define CMU_HFPERCLKEN0_PRS (0x1UL << 15) /**< Peripheral Reflex System Clock Enable */
<> 150:02e0a0aed4ec 925 #define _CMU_HFPERCLKEN0_PRS_SHIFT 15 /**< Shift value for CMU_PRS */
<> 150:02e0a0aed4ec 926 #define _CMU_HFPERCLKEN0_PRS_MASK 0x8000UL /**< Bit mask for CMU_PRS */
<> 150:02e0a0aed4ec 927 #define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 928 #define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 929 #define CMU_HFPERCLKEN0_ADC0 (0x1UL << 16) /**< Analog to Digital Converter 0 Clock Enable */
<> 150:02e0a0aed4ec 930 #define _CMU_HFPERCLKEN0_ADC0_SHIFT 16 /**< Shift value for CMU_ADC0 */
<> 150:02e0a0aed4ec 931 #define _CMU_HFPERCLKEN0_ADC0_MASK 0x10000UL /**< Bit mask for CMU_ADC0 */
<> 150:02e0a0aed4ec 932 #define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 933 #define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 934 #define CMU_HFPERCLKEN0_DAC0 (0x1UL << 17) /**< Digital to Analog Converter 0 Clock Enable */
<> 150:02e0a0aed4ec 935 #define _CMU_HFPERCLKEN0_DAC0_SHIFT 17 /**< Shift value for CMU_DAC0 */
<> 150:02e0a0aed4ec 936 #define _CMU_HFPERCLKEN0_DAC0_MASK 0x20000UL /**< Bit mask for CMU_DAC0 */
<> 150:02e0a0aed4ec 937 #define _CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 938 #define CMU_HFPERCLKEN0_DAC0_DEFAULT (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 939
<> 150:02e0a0aed4ec 940 /* Bit fields for CMU SYNCBUSY */
<> 150:02e0a0aed4ec 941 #define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */
<> 150:02e0a0aed4ec 942 #define _CMU_SYNCBUSY_MASK 0x00000055UL /**< Mask for CMU_SYNCBUSY */
<> 150:02e0a0aed4ec 943 #define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */
<> 150:02e0a0aed4ec 944 #define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */
<> 150:02e0a0aed4ec 945 #define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */
<> 150:02e0a0aed4ec 946 #define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
<> 150:02e0a0aed4ec 947 #define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
<> 150:02e0a0aed4ec 948 #define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */
<> 150:02e0a0aed4ec 949 #define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 950 #define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 951 #define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
<> 150:02e0a0aed4ec 952 #define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
<> 150:02e0a0aed4ec 953 #define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */
<> 150:02e0a0aed4ec 954 #define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */
<> 150:02e0a0aed4ec 955 #define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */
<> 150:02e0a0aed4ec 956 #define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
<> 150:02e0a0aed4ec 957 #define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
<> 150:02e0a0aed4ec 958 #define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */
<> 150:02e0a0aed4ec 959 #define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 960 #define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 961 #define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
<> 150:02e0a0aed4ec 962 #define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
<> 150:02e0a0aed4ec 963
<> 150:02e0a0aed4ec 964 /* Bit fields for CMU FREEZE */
<> 150:02e0a0aed4ec 965 #define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */
<> 150:02e0a0aed4ec 966 #define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */
<> 150:02e0a0aed4ec 967 #define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */
<> 150:02e0a0aed4ec 968 #define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */
<> 150:02e0a0aed4ec 969 #define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */
<> 150:02e0a0aed4ec 970 #define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */
<> 150:02e0a0aed4ec 971 #define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */
<> 150:02e0a0aed4ec 972 #define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */
<> 150:02e0a0aed4ec 973 #define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */
<> 150:02e0a0aed4ec 974 #define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */
<> 150:02e0a0aed4ec 975 #define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */
<> 150:02e0a0aed4ec 976
<> 150:02e0a0aed4ec 977 /* Bit fields for CMU LFACLKEN0 */
<> 150:02e0a0aed4ec 978 #define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */
<> 150:02e0a0aed4ec 979 #define _CMU_LFACLKEN0_MASK 0x0000000FUL /**< Mask for CMU_LFACLKEN0 */
<> 150:02e0a0aed4ec 980 #define CMU_LFACLKEN0_LESENSE (0x1UL << 0) /**< Low Energy Sensor Interface Clock Enable */
<> 150:02e0a0aed4ec 981 #define _CMU_LFACLKEN0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */
<> 150:02e0a0aed4ec 982 #define _CMU_LFACLKEN0_LESENSE_MASK 0x1UL /**< Bit mask for CMU_LESENSE */
<> 150:02e0a0aed4ec 983 #define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */
<> 150:02e0a0aed4ec 984 #define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */
<> 150:02e0a0aed4ec 985 #define CMU_LFACLKEN0_RTC (0x1UL << 1) /**< Real-Time Counter Clock Enable */
<> 150:02e0a0aed4ec 986 #define _CMU_LFACLKEN0_RTC_SHIFT 1 /**< Shift value for CMU_RTC */
<> 150:02e0a0aed4ec 987 #define _CMU_LFACLKEN0_RTC_MASK 0x2UL /**< Bit mask for CMU_RTC */
<> 150:02e0a0aed4ec 988 #define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */
<> 150:02e0a0aed4ec 989 #define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */
<> 150:02e0a0aed4ec 990 #define CMU_LFACLKEN0_LETIMER0 (0x1UL << 2) /**< Low Energy Timer 0 Clock Enable */
<> 150:02e0a0aed4ec 991 #define _CMU_LFACLKEN0_LETIMER0_SHIFT 2 /**< Shift value for CMU_LETIMER0 */
<> 150:02e0a0aed4ec 992 #define _CMU_LFACLKEN0_LETIMER0_MASK 0x4UL /**< Bit mask for CMU_LETIMER0 */
<> 150:02e0a0aed4ec 993 #define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */
<> 150:02e0a0aed4ec 994 #define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */
<> 150:02e0a0aed4ec 995 #define CMU_LFACLKEN0_LCD (0x1UL << 3) /**< Liquid Crystal Display Controller Clock Enable */
<> 150:02e0a0aed4ec 996 #define _CMU_LFACLKEN0_LCD_SHIFT 3 /**< Shift value for CMU_LCD */
<> 150:02e0a0aed4ec 997 #define _CMU_LFACLKEN0_LCD_MASK 0x8UL /**< Bit mask for CMU_LCD */
<> 150:02e0a0aed4ec 998 #define _CMU_LFACLKEN0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */
<> 150:02e0a0aed4ec 999 #define CMU_LFACLKEN0_LCD_DEFAULT (_CMU_LFACLKEN0_LCD_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */
<> 150:02e0a0aed4ec 1000
<> 150:02e0a0aed4ec 1001 /* Bit fields for CMU LFBCLKEN0 */
<> 150:02e0a0aed4ec 1002 #define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */
<> 150:02e0a0aed4ec 1003 #define _CMU_LFBCLKEN0_MASK 0x00000003UL /**< Mask for CMU_LFBCLKEN0 */
<> 150:02e0a0aed4ec 1004 #define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */
<> 150:02e0a0aed4ec 1005 #define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */
<> 150:02e0a0aed4ec 1006 #define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */
<> 150:02e0a0aed4ec 1007 #define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */
<> 150:02e0a0aed4ec 1008 #define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */
<> 150:02e0a0aed4ec 1009 #define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */
<> 150:02e0a0aed4ec 1010 #define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */
<> 150:02e0a0aed4ec 1011 #define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */
<> 150:02e0a0aed4ec 1012 #define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */
<> 150:02e0a0aed4ec 1013 #define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */
<> 150:02e0a0aed4ec 1014
<> 150:02e0a0aed4ec 1015 /* Bit fields for CMU LFAPRESC0 */
<> 150:02e0a0aed4ec 1016 #define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1017 #define _CMU_LFAPRESC0_MASK 0x00003FF3UL /**< Mask for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1018 #define _CMU_LFAPRESC0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */
<> 150:02e0a0aed4ec 1019 #define _CMU_LFAPRESC0_LESENSE_MASK 0x3UL /**< Bit mask for CMU_LESENSE */
<> 150:02e0a0aed4ec 1020 #define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1021 #define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1022 #define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1023 #define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1024 #define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1025 #define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1026 #define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1027 #define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1028 #define _CMU_LFAPRESC0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */
<> 150:02e0a0aed4ec 1029 #define _CMU_LFAPRESC0_RTC_MASK 0xF0UL /**< Bit mask for CMU_RTC */
<> 150:02e0a0aed4ec 1030 #define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1031 #define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1032 #define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1033 #define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1034 #define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1035 #define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1036 #define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1037 #define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1038 #define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1039 #define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1040 #define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1041 #define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1042 #define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1043 #define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1044 #define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1045 #define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1046 #define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1047 #define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1048 #define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1049 #define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1050 #define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1051 #define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1052 #define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1053 #define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1054 #define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1055 #define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1056 #define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1057 #define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1058 #define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1059 #define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1060 #define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1061 #define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1062 #define _CMU_LFAPRESC0_LETIMER0_SHIFT 8 /**< Shift value for CMU_LETIMER0 */
<> 150:02e0a0aed4ec 1063 #define _CMU_LFAPRESC0_LETIMER0_MASK 0xF00UL /**< Bit mask for CMU_LETIMER0 */
<> 150:02e0a0aed4ec 1064 #define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1065 #define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1066 #define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1067 #define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1068 #define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1069 #define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1070 #define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1071 #define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1072 #define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1073 #define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1074 #define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1075 #define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1076 #define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1077 #define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1078 #define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1079 #define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1080 #define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1081 #define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1082 #define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1083 #define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1084 #define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 8) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1085 #define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 8) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1086 #define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 8) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1087 #define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 8) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1088 #define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 8) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1089 #define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 8) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1090 #define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 8) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1091 #define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 8) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1092 #define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 8) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1093 #define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 8) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1094 #define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 8) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1095 #define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 8) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1096 #define _CMU_LFAPRESC0_LCD_SHIFT 12 /**< Shift value for CMU_LCD */
<> 150:02e0a0aed4ec 1097 #define _CMU_LFAPRESC0_LCD_MASK 0x3000UL /**< Bit mask for CMU_LCD */
<> 150:02e0a0aed4ec 1098 #define _CMU_LFAPRESC0_LCD_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1099 #define _CMU_LFAPRESC0_LCD_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1100 #define _CMU_LFAPRESC0_LCD_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1101 #define _CMU_LFAPRESC0_LCD_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1102 #define CMU_LFAPRESC0_LCD_DIV16 (_CMU_LFAPRESC0_LCD_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1103 #define CMU_LFAPRESC0_LCD_DIV32 (_CMU_LFAPRESC0_LCD_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1104 #define CMU_LFAPRESC0_LCD_DIV64 (_CMU_LFAPRESC0_LCD_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1105 #define CMU_LFAPRESC0_LCD_DIV128 (_CMU_LFAPRESC0_LCD_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1106
<> 150:02e0a0aed4ec 1107 /* Bit fields for CMU LFBPRESC0 */
<> 150:02e0a0aed4ec 1108 #define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 1109 #define _CMU_LFBPRESC0_MASK 0x00000033UL /**< Mask for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 1110 #define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */
<> 150:02e0a0aed4ec 1111 #define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */
<> 150:02e0a0aed4ec 1112 #define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 1113 #define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 1114 #define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 1115 #define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 1116 #define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 1117 #define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 1118 #define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 1119 #define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 1120 #define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */
<> 150:02e0a0aed4ec 1121 #define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */
<> 150:02e0a0aed4ec 1122 #define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 1123 #define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 1124 #define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 1125 #define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 1126 #define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 1127 #define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 1128 #define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 1129 #define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 1130
<> 150:02e0a0aed4ec 1131 /* Bit fields for CMU PCNTCTRL */
<> 150:02e0a0aed4ec 1132 #define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 1133 #define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 1134 #define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */
<> 150:02e0a0aed4ec 1135 #define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */
<> 150:02e0a0aed4ec 1136 #define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */
<> 150:02e0a0aed4ec 1137 #define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 1138 #define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 1139 #define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */
<> 150:02e0a0aed4ec 1140 #define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */
<> 150:02e0a0aed4ec 1141 #define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */
<> 150:02e0a0aed4ec 1142 #define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 1143 #define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 1144 #define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 1145 #define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 1146 #define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 1147 #define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 1148 #define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */
<> 150:02e0a0aed4ec 1149 #define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */
<> 150:02e0a0aed4ec 1150 #define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */
<> 150:02e0a0aed4ec 1151 #define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 1152 #define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 1153 #define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */
<> 150:02e0a0aed4ec 1154 #define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */
<> 150:02e0a0aed4ec 1155 #define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */
<> 150:02e0a0aed4ec 1156 #define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 1157 #define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 1158 #define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 1159 #define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 1160 #define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 1161 #define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 1162 #define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */
<> 150:02e0a0aed4ec 1163 #define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */
<> 150:02e0a0aed4ec 1164 #define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */
<> 150:02e0a0aed4ec 1165 #define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 1166 #define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 1167 #define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */
<> 150:02e0a0aed4ec 1168 #define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */
<> 150:02e0a0aed4ec 1169 #define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */
<> 150:02e0a0aed4ec 1170 #define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 1171 #define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 1172 #define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 1173 #define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 1174 #define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 1175 #define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 1176
<> 150:02e0a0aed4ec 1177 /* Bit fields for CMU LCDCTRL */
<> 150:02e0a0aed4ec 1178 #define _CMU_LCDCTRL_RESETVALUE 0x00000020UL /**< Default value for CMU_LCDCTRL */
<> 150:02e0a0aed4ec 1179 #define _CMU_LCDCTRL_MASK 0x0000007FUL /**< Mask for CMU_LCDCTRL */
<> 150:02e0a0aed4ec 1180 #define _CMU_LCDCTRL_FDIV_SHIFT 0 /**< Shift value for CMU_FDIV */
<> 150:02e0a0aed4ec 1181 #define _CMU_LCDCTRL_FDIV_MASK 0x7UL /**< Bit mask for CMU_FDIV */
<> 150:02e0a0aed4ec 1182 #define _CMU_LCDCTRL_FDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LCDCTRL */
<> 150:02e0a0aed4ec 1183 #define CMU_LCDCTRL_FDIV_DEFAULT (_CMU_LCDCTRL_FDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LCDCTRL */
<> 150:02e0a0aed4ec 1184 #define CMU_LCDCTRL_VBOOSTEN (0x1UL << 3) /**< Voltage Boost Enable */
<> 150:02e0a0aed4ec 1185 #define _CMU_LCDCTRL_VBOOSTEN_SHIFT 3 /**< Shift value for CMU_VBOOSTEN */
<> 150:02e0a0aed4ec 1186 #define _CMU_LCDCTRL_VBOOSTEN_MASK 0x8UL /**< Bit mask for CMU_VBOOSTEN */
<> 150:02e0a0aed4ec 1187 #define _CMU_LCDCTRL_VBOOSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LCDCTRL */
<> 150:02e0a0aed4ec 1188 #define CMU_LCDCTRL_VBOOSTEN_DEFAULT (_CMU_LCDCTRL_VBOOSTEN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LCDCTRL */
<> 150:02e0a0aed4ec 1189 #define _CMU_LCDCTRL_VBFDIV_SHIFT 4 /**< Shift value for CMU_VBFDIV */
<> 150:02e0a0aed4ec 1190 #define _CMU_LCDCTRL_VBFDIV_MASK 0x70UL /**< Bit mask for CMU_VBFDIV */
<> 150:02e0a0aed4ec 1191 #define _CMU_LCDCTRL_VBFDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LCDCTRL */
<> 150:02e0a0aed4ec 1192 #define _CMU_LCDCTRL_VBFDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LCDCTRL */
<> 150:02e0a0aed4ec 1193 #define _CMU_LCDCTRL_VBFDIV_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LCDCTRL */
<> 150:02e0a0aed4ec 1194 #define _CMU_LCDCTRL_VBFDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LCDCTRL */
<> 150:02e0a0aed4ec 1195 #define _CMU_LCDCTRL_VBFDIV_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LCDCTRL */
<> 150:02e0a0aed4ec 1196 #define _CMU_LCDCTRL_VBFDIV_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LCDCTRL */
<> 150:02e0a0aed4ec 1197 #define _CMU_LCDCTRL_VBFDIV_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LCDCTRL */
<> 150:02e0a0aed4ec 1198 #define _CMU_LCDCTRL_VBFDIV_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LCDCTRL */
<> 150:02e0a0aed4ec 1199 #define _CMU_LCDCTRL_VBFDIV_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LCDCTRL */
<> 150:02e0a0aed4ec 1200 #define CMU_LCDCTRL_VBFDIV_DIV1 (_CMU_LCDCTRL_VBFDIV_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LCDCTRL */
<> 150:02e0a0aed4ec 1201 #define CMU_LCDCTRL_VBFDIV_DIV2 (_CMU_LCDCTRL_VBFDIV_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LCDCTRL */
<> 150:02e0a0aed4ec 1202 #define CMU_LCDCTRL_VBFDIV_DEFAULT (_CMU_LCDCTRL_VBFDIV_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_LCDCTRL */
<> 150:02e0a0aed4ec 1203 #define CMU_LCDCTRL_VBFDIV_DIV4 (_CMU_LCDCTRL_VBFDIV_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LCDCTRL */
<> 150:02e0a0aed4ec 1204 #define CMU_LCDCTRL_VBFDIV_DIV8 (_CMU_LCDCTRL_VBFDIV_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LCDCTRL */
<> 150:02e0a0aed4ec 1205 #define CMU_LCDCTRL_VBFDIV_DIV16 (_CMU_LCDCTRL_VBFDIV_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LCDCTRL */
<> 150:02e0a0aed4ec 1206 #define CMU_LCDCTRL_VBFDIV_DIV32 (_CMU_LCDCTRL_VBFDIV_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LCDCTRL */
<> 150:02e0a0aed4ec 1207 #define CMU_LCDCTRL_VBFDIV_DIV64 (_CMU_LCDCTRL_VBFDIV_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LCDCTRL */
<> 150:02e0a0aed4ec 1208 #define CMU_LCDCTRL_VBFDIV_DIV128 (_CMU_LCDCTRL_VBFDIV_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LCDCTRL */
<> 150:02e0a0aed4ec 1209
<> 150:02e0a0aed4ec 1210 /* Bit fields for CMU ROUTE */
<> 150:02e0a0aed4ec 1211 #define _CMU_ROUTE_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTE */
<> 150:02e0a0aed4ec 1212 #define _CMU_ROUTE_MASK 0x0000001FUL /**< Mask for CMU_ROUTE */
<> 150:02e0a0aed4ec 1213 #define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */
<> 150:02e0a0aed4ec 1214 #define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */
<> 150:02e0a0aed4ec 1215 #define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */
<> 150:02e0a0aed4ec 1216 #define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */
<> 150:02e0a0aed4ec 1217 #define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTE */
<> 150:02e0a0aed4ec 1218 #define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */
<> 150:02e0a0aed4ec 1219 #define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */
<> 150:02e0a0aed4ec 1220 #define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */
<> 150:02e0a0aed4ec 1221 #define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */
<> 150:02e0a0aed4ec 1222 #define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTE */
<> 150:02e0a0aed4ec 1223 #define _CMU_ROUTE_LOCATION_SHIFT 2 /**< Shift value for CMU_LOCATION */
<> 150:02e0a0aed4ec 1224 #define _CMU_ROUTE_LOCATION_MASK 0x1CUL /**< Bit mask for CMU_LOCATION */
<> 150:02e0a0aed4ec 1225 #define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTE */
<> 150:02e0a0aed4ec 1226 #define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */
<> 150:02e0a0aed4ec 1227 #define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTE */
<> 150:02e0a0aed4ec 1228 #define _CMU_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTE */
<> 150:02e0a0aed4ec 1229 #define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2) /**< Shifted mode LOC0 for CMU_ROUTE */
<> 150:02e0a0aed4ec 1230 #define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTE */
<> 150:02e0a0aed4ec 1231 #define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2) /**< Shifted mode LOC1 for CMU_ROUTE */
<> 150:02e0a0aed4ec 1232 #define CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2) /**< Shifted mode LOC2 for CMU_ROUTE */
<> 150:02e0a0aed4ec 1233
<> 150:02e0a0aed4ec 1234 /* Bit fields for CMU LOCK */
<> 150:02e0a0aed4ec 1235 #define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */
<> 150:02e0a0aed4ec 1236 #define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */
<> 150:02e0a0aed4ec 1237 #define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */
<> 150:02e0a0aed4ec 1238 #define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */
<> 150:02e0a0aed4ec 1239 #define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */
<> 150:02e0a0aed4ec 1240 #define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */
<> 150:02e0a0aed4ec 1241 #define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */
<> 150:02e0a0aed4ec 1242 #define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */
<> 150:02e0a0aed4ec 1243 #define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */
<> 150:02e0a0aed4ec 1244 #define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */
<> 150:02e0a0aed4ec 1245 #define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */
<> 150:02e0a0aed4ec 1246 #define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */
<> 150:02e0a0aed4ec 1247 #define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */
<> 150:02e0a0aed4ec 1248 #define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */
<> 150:02e0a0aed4ec 1249
<> 150:02e0a0aed4ec 1250 /** @} End of group EFM32WG_CMU */
<> 150:02e0a0aed4ec 1251 /** @} End of group Parts */
<> 150:02e0a0aed4ec 1252