Fawwaz Nadzmy / mbed-STM

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_burtc.h@153:9398a535854b, 2016-12-22 (annotated)

Committer:
fwndz
Date:
Thu Dec 22 05:12:40 2016 +0000
Revision:
153:9398a535854b
Parent:
150:02e0a0aed4ec 
device target maximize

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 150:02e0a0aed4ec 1 /**************************************************************************//**
<> 150:02e0a0aed4ec 2 * @file efm32wg_burtc.h
<> 150:02e0a0aed4ec 3 * @brief EFM32WG_BURTC register and bit field definitions
<> 150:02e0a0aed4ec 4 * @version 5.0.0
<> 150:02e0a0aed4ec 5 ******************************************************************************
<> 150:02e0a0aed4ec 6 * @section License
<> 150:02e0a0aed4ec 7 * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 150:02e0a0aed4ec 8 ******************************************************************************
<> 150:02e0a0aed4ec 9 *
<> 150:02e0a0aed4ec 10 * Permission is granted to anyone to use this software for any purpose,
<> 150:02e0a0aed4ec 11 * including commercial applications, and to alter it and redistribute it
<> 150:02e0a0aed4ec 12 * freely, subject to the following restrictions:
<> 150:02e0a0aed4ec 13 *
<> 150:02e0a0aed4ec 14 * 1. The origin of this software must not be misrepresented; you must not
<> 150:02e0a0aed4ec 15 * claim that you wrote the original software.@n
<> 150:02e0a0aed4ec 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 150:02e0a0aed4ec 17 * misrepresented as being the original software.@n
<> 150:02e0a0aed4ec 18 * 3. This notice may not be removed or altered from any source distribution.
<> 150:02e0a0aed4ec 19 *
<> 150:02e0a0aed4ec 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 150:02e0a0aed4ec 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 150:02e0a0aed4ec 22 * providing the Software "AS IS", with no express or implied warranties of any
<> 150:02e0a0aed4ec 23 * kind, including, but not limited to, any implied warranties of
<> 150:02e0a0aed4ec 24 * merchantability or fitness for any particular purpose or warranties against
<> 150:02e0a0aed4ec 25 * infringement of any proprietary rights of a third party.
<> 150:02e0a0aed4ec 26 *
<> 150:02e0a0aed4ec 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 150:02e0a0aed4ec 28 * incidental, or special damages, or any other relief, or for any claim by
<> 150:02e0a0aed4ec 29 * any third party, arising from your use of this Software.
<> 150:02e0a0aed4ec 30 *
<> 150:02e0a0aed4ec 31 *****************************************************************************/
<> 150:02e0a0aed4ec 32 /**************************************************************************//**
<> 150:02e0a0aed4ec 33 * @addtogroup Parts
<> 150:02e0a0aed4ec 34 * @{
<> 150:02e0a0aed4ec 35 ******************************************************************************/
<> 150:02e0a0aed4ec 36 /**************************************************************************//**
<> 150:02e0a0aed4ec 37 * @defgroup EFM32WG_BURTC
<> 150:02e0a0aed4ec 38 * @{
<> 150:02e0a0aed4ec 39 * @brief EFM32WG_BURTC Register Declaration
<> 150:02e0a0aed4ec 40 *****************************************************************************/
<> 150:02e0a0aed4ec 41 typedef struct
<> 150:02e0a0aed4ec 42 {
<> 150:02e0a0aed4ec 43 __IOM uint32_t CTRL; /**< Control Register */
<> 150:02e0a0aed4ec 44 __IOM uint32_t LPMODE; /**< Low power mode configuration */
<> 150:02e0a0aed4ec 45 __IM uint32_t CNT; /**< Counter Value Register */
<> 150:02e0a0aed4ec 46 __IOM uint32_t COMP0; /**< Counter Compare Value */
<> 150:02e0a0aed4ec 47 __IM uint32_t TIMESTAMP; /**< Backup mode timestamp */
<> 150:02e0a0aed4ec 48 __IOM uint32_t LFXOFDET; /**< LFXO */
<> 150:02e0a0aed4ec 49 __IM uint32_t STATUS; /**< Status Register */
<> 150:02e0a0aed4ec 50 __IOM uint32_t CMD; /**< Command Register */
<> 150:02e0a0aed4ec 51 __IOM uint32_t POWERDOWN; /**< Retention RAM power-down Register */
<> 150:02e0a0aed4ec 52 __IOM uint32_t LOCK; /**< Configuration Lock Register */
<> 150:02e0a0aed4ec 53 __IM uint32_t IF; /**< Interrupt Flag Register */
<> 150:02e0a0aed4ec 54 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
<> 150:02e0a0aed4ec 55 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
<> 150:02e0a0aed4ec 56 __IOM uint32_t IEN; /**< Interrupt Enable Register */
<> 150:02e0a0aed4ec 57
<> 150:02e0a0aed4ec 58 __IOM uint32_t FREEZE; /**< Freeze Register */
<> 150:02e0a0aed4ec 59 __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
<> 150:02e0a0aed4ec 60
<> 150:02e0a0aed4ec 61 uint32_t RESERVED0[48]; /**< Reserved registers */
<> 150:02e0a0aed4ec 62 BURTC_RET_TypeDef RET[128]; /**< RetentionReg */
<> 150:02e0a0aed4ec 63 } BURTC_TypeDef; /** @} */
<> 150:02e0a0aed4ec 64
<> 150:02e0a0aed4ec 65 /**************************************************************************//**
<> 150:02e0a0aed4ec 66 * @defgroup EFM32WG_BURTC_BitFields
<> 150:02e0a0aed4ec 67 * @{
<> 150:02e0a0aed4ec 68 *****************************************************************************/
<> 150:02e0a0aed4ec 69
<> 150:02e0a0aed4ec 70 /* Bit fields for BURTC CTRL */
<> 150:02e0a0aed4ec 71 #define _BURTC_CTRL_RESETVALUE 0x00000008UL /**< Default value for BURTC_CTRL */
<> 150:02e0a0aed4ec 72 #define _BURTC_CTRL_MASK 0x000077FFUL /**< Mask for BURTC_CTRL */
<> 150:02e0a0aed4ec 73 #define _BURTC_CTRL_MODE_SHIFT 0 /**< Shift value for BURTC_MODE */
<> 150:02e0a0aed4ec 74 #define _BURTC_CTRL_MODE_MASK 0x3UL /**< Bit mask for BURTC_MODE */
<> 150:02e0a0aed4ec 75 #define _BURTC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CTRL */
<> 150:02e0a0aed4ec 76 #define _BURTC_CTRL_MODE_DISABLE 0x00000000UL /**< Mode DISABLE for BURTC_CTRL */
<> 150:02e0a0aed4ec 77 #define _BURTC_CTRL_MODE_EM2EN 0x00000001UL /**< Mode EM2EN for BURTC_CTRL */
<> 150:02e0a0aed4ec 78 #define _BURTC_CTRL_MODE_EM3EN 0x00000002UL /**< Mode EM3EN for BURTC_CTRL */
<> 150:02e0a0aed4ec 79 #define _BURTC_CTRL_MODE_EM4EN 0x00000003UL /**< Mode EM4EN for BURTC_CTRL */
<> 150:02e0a0aed4ec 80 #define BURTC_CTRL_MODE_DEFAULT (_BURTC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CTRL */
<> 150:02e0a0aed4ec 81 #define BURTC_CTRL_MODE_DISABLE (_BURTC_CTRL_MODE_DISABLE << 0) /**< Shifted mode DISABLE for BURTC_CTRL */
<> 150:02e0a0aed4ec 82 #define BURTC_CTRL_MODE_EM2EN (_BURTC_CTRL_MODE_EM2EN << 0) /**< Shifted mode EM2EN for BURTC_CTRL */
<> 150:02e0a0aed4ec 83 #define BURTC_CTRL_MODE_EM3EN (_BURTC_CTRL_MODE_EM3EN << 0) /**< Shifted mode EM3EN for BURTC_CTRL */
<> 150:02e0a0aed4ec 84 #define BURTC_CTRL_MODE_EM4EN (_BURTC_CTRL_MODE_EM4EN << 0) /**< Shifted mode EM4EN for BURTC_CTRL */
<> 150:02e0a0aed4ec 85 #define BURTC_CTRL_DEBUGRUN (0x1UL << 2) /**< Debug Mode Run Enable */
<> 150:02e0a0aed4ec 86 #define _BURTC_CTRL_DEBUGRUN_SHIFT 2 /**< Shift value for BURTC_DEBUGRUN */
<> 150:02e0a0aed4ec 87 #define _BURTC_CTRL_DEBUGRUN_MASK 0x4UL /**< Bit mask for BURTC_DEBUGRUN */
<> 150:02e0a0aed4ec 88 #define _BURTC_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CTRL */
<> 150:02e0a0aed4ec 89 #define BURTC_CTRL_DEBUGRUN_DEFAULT (_BURTC_CTRL_DEBUGRUN_DEFAULT << 2) /**< Shifted mode DEFAULT for BURTC_CTRL */
<> 150:02e0a0aed4ec 90 #define BURTC_CTRL_RSTEN (0x1UL << 3) /**< Enable BURTC reset */
<> 150:02e0a0aed4ec 91 #define _BURTC_CTRL_RSTEN_SHIFT 3 /**< Shift value for BURTC_RSTEN */
<> 150:02e0a0aed4ec 92 #define _BURTC_CTRL_RSTEN_MASK 0x8UL /**< Bit mask for BURTC_RSTEN */
<> 150:02e0a0aed4ec 93 #define _BURTC_CTRL_RSTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for BURTC_CTRL */
<> 150:02e0a0aed4ec 94 #define BURTC_CTRL_RSTEN_DEFAULT (_BURTC_CTRL_RSTEN_DEFAULT << 3) /**< Shifted mode DEFAULT for BURTC_CTRL */
<> 150:02e0a0aed4ec 95 #define BURTC_CTRL_COMP0TOP (0x1UL << 4) /**< Compare clear enable */
<> 150:02e0a0aed4ec 96 #define _BURTC_CTRL_COMP0TOP_SHIFT 4 /**< Shift value for BURTC_COMP0TOP */
<> 150:02e0a0aed4ec 97 #define _BURTC_CTRL_COMP0TOP_MASK 0x10UL /**< Bit mask for BURTC_COMP0TOP */
<> 150:02e0a0aed4ec 98 #define _BURTC_CTRL_COMP0TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CTRL */
<> 150:02e0a0aed4ec 99 #define BURTC_CTRL_COMP0TOP_DEFAULT (_BURTC_CTRL_COMP0TOP_DEFAULT << 4) /**< Shifted mode DEFAULT for BURTC_CTRL */
<> 150:02e0a0aed4ec 100 #define _BURTC_CTRL_LPCOMP_SHIFT 5 /**< Shift value for BURTC_LPCOMP */
<> 150:02e0a0aed4ec 101 #define _BURTC_CTRL_LPCOMP_MASK 0xE0UL /**< Bit mask for BURTC_LPCOMP */
<> 150:02e0a0aed4ec 102 #define _BURTC_CTRL_LPCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CTRL */
<> 150:02e0a0aed4ec 103 #define _BURTC_CTRL_LPCOMP_IGN0LSB 0x00000000UL /**< Mode IGN0LSB for BURTC_CTRL */
<> 150:02e0a0aed4ec 104 #define _BURTC_CTRL_LPCOMP_IGN1LSB 0x00000001UL /**< Mode IGN1LSB for BURTC_CTRL */
<> 150:02e0a0aed4ec 105 #define _BURTC_CTRL_LPCOMP_IGN2LSB 0x00000002UL /**< Mode IGN2LSB for BURTC_CTRL */
<> 150:02e0a0aed4ec 106 #define _BURTC_CTRL_LPCOMP_IGN3LSB 0x00000003UL /**< Mode IGN3LSB for BURTC_CTRL */
<> 150:02e0a0aed4ec 107 #define _BURTC_CTRL_LPCOMP_IGN4LSB 0x00000004UL /**< Mode IGN4LSB for BURTC_CTRL */
<> 150:02e0a0aed4ec 108 #define _BURTC_CTRL_LPCOMP_IGN5LSB 0x00000005UL /**< Mode IGN5LSB for BURTC_CTRL */
<> 150:02e0a0aed4ec 109 #define _BURTC_CTRL_LPCOMP_IGN6LSB 0x00000006UL /**< Mode IGN6LSB for BURTC_CTRL */
<> 150:02e0a0aed4ec 110 #define _BURTC_CTRL_LPCOMP_IGN7LSB 0x00000007UL /**< Mode IGN7LSB for BURTC_CTRL */
<> 150:02e0a0aed4ec 111 #define BURTC_CTRL_LPCOMP_DEFAULT (_BURTC_CTRL_LPCOMP_DEFAULT << 5) /**< Shifted mode DEFAULT for BURTC_CTRL */
<> 150:02e0a0aed4ec 112 #define BURTC_CTRL_LPCOMP_IGN0LSB (_BURTC_CTRL_LPCOMP_IGN0LSB << 5) /**< Shifted mode IGN0LSB for BURTC_CTRL */
<> 150:02e0a0aed4ec 113 #define BURTC_CTRL_LPCOMP_IGN1LSB (_BURTC_CTRL_LPCOMP_IGN1LSB << 5) /**< Shifted mode IGN1LSB for BURTC_CTRL */
<> 150:02e0a0aed4ec 114 #define BURTC_CTRL_LPCOMP_IGN2LSB (_BURTC_CTRL_LPCOMP_IGN2LSB << 5) /**< Shifted mode IGN2LSB for BURTC_CTRL */
<> 150:02e0a0aed4ec 115 #define BURTC_CTRL_LPCOMP_IGN3LSB (_BURTC_CTRL_LPCOMP_IGN3LSB << 5) /**< Shifted mode IGN3LSB for BURTC_CTRL */
<> 150:02e0a0aed4ec 116 #define BURTC_CTRL_LPCOMP_IGN4LSB (_BURTC_CTRL_LPCOMP_IGN4LSB << 5) /**< Shifted mode IGN4LSB for BURTC_CTRL */
<> 150:02e0a0aed4ec 117 #define BURTC_CTRL_LPCOMP_IGN5LSB (_BURTC_CTRL_LPCOMP_IGN5LSB << 5) /**< Shifted mode IGN5LSB for BURTC_CTRL */
<> 150:02e0a0aed4ec 118 #define BURTC_CTRL_LPCOMP_IGN6LSB (_BURTC_CTRL_LPCOMP_IGN6LSB << 5) /**< Shifted mode IGN6LSB for BURTC_CTRL */
<> 150:02e0a0aed4ec 119 #define BURTC_CTRL_LPCOMP_IGN7LSB (_BURTC_CTRL_LPCOMP_IGN7LSB << 5) /**< Shifted mode IGN7LSB for BURTC_CTRL */
<> 150:02e0a0aed4ec 120 #define _BURTC_CTRL_PRESC_SHIFT 8 /**< Shift value for BURTC_PRESC */
<> 150:02e0a0aed4ec 121 #define _BURTC_CTRL_PRESC_MASK 0x700UL /**< Bit mask for BURTC_PRESC */
<> 150:02e0a0aed4ec 122 #define _BURTC_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CTRL */
<> 150:02e0a0aed4ec 123 #define _BURTC_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for BURTC_CTRL */
<> 150:02e0a0aed4ec 124 #define _BURTC_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for BURTC_CTRL */
<> 150:02e0a0aed4ec 125 #define _BURTC_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for BURTC_CTRL */
<> 150:02e0a0aed4ec 126 #define _BURTC_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for BURTC_CTRL */
<> 150:02e0a0aed4ec 127 #define _BURTC_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for BURTC_CTRL */
<> 150:02e0a0aed4ec 128 #define _BURTC_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for BURTC_CTRL */
<> 150:02e0a0aed4ec 129 #define _BURTC_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for BURTC_CTRL */
<> 150:02e0a0aed4ec 130 #define _BURTC_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for BURTC_CTRL */
<> 150:02e0a0aed4ec 131 #define BURTC_CTRL_PRESC_DEFAULT (_BURTC_CTRL_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for BURTC_CTRL */
<> 150:02e0a0aed4ec 132 #define BURTC_CTRL_PRESC_DIV1 (_BURTC_CTRL_PRESC_DIV1 << 8) /**< Shifted mode DIV1 for BURTC_CTRL */
<> 150:02e0a0aed4ec 133 #define BURTC_CTRL_PRESC_DIV2 (_BURTC_CTRL_PRESC_DIV2 << 8) /**< Shifted mode DIV2 for BURTC_CTRL */
<> 150:02e0a0aed4ec 134 #define BURTC_CTRL_PRESC_DIV4 (_BURTC_CTRL_PRESC_DIV4 << 8) /**< Shifted mode DIV4 for BURTC_CTRL */
<> 150:02e0a0aed4ec 135 #define BURTC_CTRL_PRESC_DIV8 (_BURTC_CTRL_PRESC_DIV8 << 8) /**< Shifted mode DIV8 for BURTC_CTRL */
<> 150:02e0a0aed4ec 136 #define BURTC_CTRL_PRESC_DIV16 (_BURTC_CTRL_PRESC_DIV16 << 8) /**< Shifted mode DIV16 for BURTC_CTRL */
<> 150:02e0a0aed4ec 137 #define BURTC_CTRL_PRESC_DIV32 (_BURTC_CTRL_PRESC_DIV32 << 8) /**< Shifted mode DIV32 for BURTC_CTRL */
<> 150:02e0a0aed4ec 138 #define BURTC_CTRL_PRESC_DIV64 (_BURTC_CTRL_PRESC_DIV64 << 8) /**< Shifted mode DIV64 for BURTC_CTRL */
<> 150:02e0a0aed4ec 139 #define BURTC_CTRL_PRESC_DIV128 (_BURTC_CTRL_PRESC_DIV128 << 8) /**< Shifted mode DIV128 for BURTC_CTRL */
<> 150:02e0a0aed4ec 140 #define _BURTC_CTRL_CLKSEL_SHIFT 12 /**< Shift value for BURTC_CLKSEL */
<> 150:02e0a0aed4ec 141 #define _BURTC_CTRL_CLKSEL_MASK 0x3000UL /**< Bit mask for BURTC_CLKSEL */
<> 150:02e0a0aed4ec 142 #define _BURTC_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CTRL */
<> 150:02e0a0aed4ec 143 #define _BURTC_CTRL_CLKSEL_NONE 0x00000000UL /**< Mode NONE for BURTC_CTRL */
<> 150:02e0a0aed4ec 144 #define _BURTC_CTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for BURTC_CTRL */
<> 150:02e0a0aed4ec 145 #define _BURTC_CTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for BURTC_CTRL */
<> 150:02e0a0aed4ec 146 #define _BURTC_CTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for BURTC_CTRL */
<> 150:02e0a0aed4ec 147 #define BURTC_CTRL_CLKSEL_DEFAULT (_BURTC_CTRL_CLKSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for BURTC_CTRL */
<> 150:02e0a0aed4ec 148 #define BURTC_CTRL_CLKSEL_NONE (_BURTC_CTRL_CLKSEL_NONE << 12) /**< Shifted mode NONE for BURTC_CTRL */
<> 150:02e0a0aed4ec 149 #define BURTC_CTRL_CLKSEL_LFRCO (_BURTC_CTRL_CLKSEL_LFRCO << 12) /**< Shifted mode LFRCO for BURTC_CTRL */
<> 150:02e0a0aed4ec 150 #define BURTC_CTRL_CLKSEL_LFXO (_BURTC_CTRL_CLKSEL_LFXO << 12) /**< Shifted mode LFXO for BURTC_CTRL */
<> 150:02e0a0aed4ec 151 #define BURTC_CTRL_CLKSEL_ULFRCO (_BURTC_CTRL_CLKSEL_ULFRCO << 12) /**< Shifted mode ULFRCO for BURTC_CTRL */
<> 150:02e0a0aed4ec 152 #define BURTC_CTRL_BUMODETSEN (0x1UL << 14) /**< Backup mode timestamp enable */
<> 150:02e0a0aed4ec 153 #define _BURTC_CTRL_BUMODETSEN_SHIFT 14 /**< Shift value for BURTC_BUMODETSEN */
<> 150:02e0a0aed4ec 154 #define _BURTC_CTRL_BUMODETSEN_MASK 0x4000UL /**< Bit mask for BURTC_BUMODETSEN */
<> 150:02e0a0aed4ec 155 #define _BURTC_CTRL_BUMODETSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CTRL */
<> 150:02e0a0aed4ec 156 #define BURTC_CTRL_BUMODETSEN_DEFAULT (_BURTC_CTRL_BUMODETSEN_DEFAULT << 14) /**< Shifted mode DEFAULT for BURTC_CTRL */
<> 150:02e0a0aed4ec 157
<> 150:02e0a0aed4ec 158 /* Bit fields for BURTC LPMODE */
<> 150:02e0a0aed4ec 159 #define _BURTC_LPMODE_RESETVALUE 0x00000000UL /**< Default value for BURTC_LPMODE */
<> 150:02e0a0aed4ec 160 #define _BURTC_LPMODE_MASK 0x00000003UL /**< Mask for BURTC_LPMODE */
<> 150:02e0a0aed4ec 161 #define _BURTC_LPMODE_LPMODE_SHIFT 0 /**< Shift value for BURTC_LPMODE */
<> 150:02e0a0aed4ec 162 #define _BURTC_LPMODE_LPMODE_MASK 0x3UL /**< Bit mask for BURTC_LPMODE */
<> 150:02e0a0aed4ec 163 #define _BURTC_LPMODE_LPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_LPMODE */
<> 150:02e0a0aed4ec 164 #define _BURTC_LPMODE_LPMODE_DISABLE 0x00000000UL /**< Mode DISABLE for BURTC_LPMODE */
<> 150:02e0a0aed4ec 165 #define _BURTC_LPMODE_LPMODE_ENABLE 0x00000001UL /**< Mode ENABLE for BURTC_LPMODE */
<> 150:02e0a0aed4ec 166 #define _BURTC_LPMODE_LPMODE_BUEN 0x00000002UL /**< Mode BUEN for BURTC_LPMODE */
<> 150:02e0a0aed4ec 167 #define BURTC_LPMODE_LPMODE_DEFAULT (_BURTC_LPMODE_LPMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_LPMODE */
<> 150:02e0a0aed4ec 168 #define BURTC_LPMODE_LPMODE_DISABLE (_BURTC_LPMODE_LPMODE_DISABLE << 0) /**< Shifted mode DISABLE for BURTC_LPMODE */
<> 150:02e0a0aed4ec 169 #define BURTC_LPMODE_LPMODE_ENABLE (_BURTC_LPMODE_LPMODE_ENABLE << 0) /**< Shifted mode ENABLE for BURTC_LPMODE */
<> 150:02e0a0aed4ec 170 #define BURTC_LPMODE_LPMODE_BUEN (_BURTC_LPMODE_LPMODE_BUEN << 0) /**< Shifted mode BUEN for BURTC_LPMODE */
<> 150:02e0a0aed4ec 171
<> 150:02e0a0aed4ec 172 /* Bit fields for BURTC CNT */
<> 150:02e0a0aed4ec 173 #define _BURTC_CNT_RESETVALUE 0x00000000UL /**< Default value for BURTC_CNT */
<> 150:02e0a0aed4ec 174 #define _BURTC_CNT_MASK 0xFFFFFFFFUL /**< Mask for BURTC_CNT */
<> 150:02e0a0aed4ec 175 #define _BURTC_CNT_CNT_SHIFT 0 /**< Shift value for BURTC_CNT */
<> 150:02e0a0aed4ec 176 #define _BURTC_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_CNT */
<> 150:02e0a0aed4ec 177 #define _BURTC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CNT */
<> 150:02e0a0aed4ec 178 #define BURTC_CNT_CNT_DEFAULT (_BURTC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CNT */
<> 150:02e0a0aed4ec 179
<> 150:02e0a0aed4ec 180 /* Bit fields for BURTC COMP0 */
<> 150:02e0a0aed4ec 181 #define _BURTC_COMP0_RESETVALUE 0x00000000UL /**< Default value for BURTC_COMP0 */
<> 150:02e0a0aed4ec 182 #define _BURTC_COMP0_MASK 0xFFFFFFFFUL /**< Mask for BURTC_COMP0 */
<> 150:02e0a0aed4ec 183 #define _BURTC_COMP0_COMP0_SHIFT 0 /**< Shift value for BURTC_COMP0 */
<> 150:02e0a0aed4ec 184 #define _BURTC_COMP0_COMP0_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_COMP0 */
<> 150:02e0a0aed4ec 185 #define _BURTC_COMP0_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_COMP0 */
<> 150:02e0a0aed4ec 186 #define BURTC_COMP0_COMP0_DEFAULT (_BURTC_COMP0_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_COMP0 */
<> 150:02e0a0aed4ec 187
<> 150:02e0a0aed4ec 188 /* Bit fields for BURTC TIMESTAMP */
<> 150:02e0a0aed4ec 189 #define _BURTC_TIMESTAMP_RESETVALUE 0x00000000UL /**< Default value for BURTC_TIMESTAMP */
<> 150:02e0a0aed4ec 190 #define _BURTC_TIMESTAMP_MASK 0xFFFFFFFFUL /**< Mask for BURTC_TIMESTAMP */
<> 150:02e0a0aed4ec 191 #define _BURTC_TIMESTAMP_TIMESTAMP_SHIFT 0 /**< Shift value for BURTC_TIMESTAMP */
<> 150:02e0a0aed4ec 192 #define _BURTC_TIMESTAMP_TIMESTAMP_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_TIMESTAMP */
<> 150:02e0a0aed4ec 193 #define _BURTC_TIMESTAMP_TIMESTAMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_TIMESTAMP */
<> 150:02e0a0aed4ec 194 #define BURTC_TIMESTAMP_TIMESTAMP_DEFAULT (_BURTC_TIMESTAMP_TIMESTAMP_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_TIMESTAMP */
<> 150:02e0a0aed4ec 195
<> 150:02e0a0aed4ec 196 /* Bit fields for BURTC LFXOFDET */
<> 150:02e0a0aed4ec 197 #define _BURTC_LFXOFDET_RESETVALUE 0x00000000UL /**< Default value for BURTC_LFXOFDET */
<> 150:02e0a0aed4ec 198 #define _BURTC_LFXOFDET_MASK 0x000001F3UL /**< Mask for BURTC_LFXOFDET */
<> 150:02e0a0aed4ec 199 #define _BURTC_LFXOFDET_OSC_SHIFT 0 /**< Shift value for BURTC_OSC */
<> 150:02e0a0aed4ec 200 #define _BURTC_LFXOFDET_OSC_MASK 0x3UL /**< Bit mask for BURTC_OSC */
<> 150:02e0a0aed4ec 201 #define _BURTC_LFXOFDET_OSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_LFXOFDET */
<> 150:02e0a0aed4ec 202 #define _BURTC_LFXOFDET_OSC_DISABLE 0x00000000UL /**< Mode DISABLE for BURTC_LFXOFDET */
<> 150:02e0a0aed4ec 203 #define _BURTC_LFXOFDET_OSC_LFRCO 0x00000001UL /**< Mode LFRCO for BURTC_LFXOFDET */
<> 150:02e0a0aed4ec 204 #define _BURTC_LFXOFDET_OSC_ULFRCO 0x00000002UL /**< Mode ULFRCO for BURTC_LFXOFDET */
<> 150:02e0a0aed4ec 205 #define BURTC_LFXOFDET_OSC_DEFAULT (_BURTC_LFXOFDET_OSC_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_LFXOFDET */
<> 150:02e0a0aed4ec 206 #define BURTC_LFXOFDET_OSC_DISABLE (_BURTC_LFXOFDET_OSC_DISABLE << 0) /**< Shifted mode DISABLE for BURTC_LFXOFDET */
<> 150:02e0a0aed4ec 207 #define BURTC_LFXOFDET_OSC_LFRCO (_BURTC_LFXOFDET_OSC_LFRCO << 0) /**< Shifted mode LFRCO for BURTC_LFXOFDET */
<> 150:02e0a0aed4ec 208 #define BURTC_LFXOFDET_OSC_ULFRCO (_BURTC_LFXOFDET_OSC_ULFRCO << 0) /**< Shifted mode ULFRCO for BURTC_LFXOFDET */
<> 150:02e0a0aed4ec 209 #define _BURTC_LFXOFDET_TOP_SHIFT 4 /**< Shift value for BURTC_TOP */
<> 150:02e0a0aed4ec 210 #define _BURTC_LFXOFDET_TOP_MASK 0x1F0UL /**< Bit mask for BURTC_TOP */
<> 150:02e0a0aed4ec 211 #define _BURTC_LFXOFDET_TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_LFXOFDET */
<> 150:02e0a0aed4ec 212 #define BURTC_LFXOFDET_TOP_DEFAULT (_BURTC_LFXOFDET_TOP_DEFAULT << 4) /**< Shifted mode DEFAULT for BURTC_LFXOFDET */
<> 150:02e0a0aed4ec 213
<> 150:02e0a0aed4ec 214 /* Bit fields for BURTC STATUS */
<> 150:02e0a0aed4ec 215 #define _BURTC_STATUS_RESETVALUE 0x00000000UL /**< Default value for BURTC_STATUS */
<> 150:02e0a0aed4ec 216 #define _BURTC_STATUS_MASK 0x00000007UL /**< Mask for BURTC_STATUS */
<> 150:02e0a0aed4ec 217 #define BURTC_STATUS_LPMODEACT (0x1UL << 0) /**< Low power mode active */
<> 150:02e0a0aed4ec 218 #define _BURTC_STATUS_LPMODEACT_SHIFT 0 /**< Shift value for BURTC_LPMODEACT */
<> 150:02e0a0aed4ec 219 #define _BURTC_STATUS_LPMODEACT_MASK 0x1UL /**< Bit mask for BURTC_LPMODEACT */
<> 150:02e0a0aed4ec 220 #define _BURTC_STATUS_LPMODEACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_STATUS */
<> 150:02e0a0aed4ec 221 #define BURTC_STATUS_LPMODEACT_DEFAULT (_BURTC_STATUS_LPMODEACT_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_STATUS */
<> 150:02e0a0aed4ec 222 #define BURTC_STATUS_BUMODETS (0x1UL << 1) /**< Timestamp for backup mode entry stored. */
<> 150:02e0a0aed4ec 223 #define _BURTC_STATUS_BUMODETS_SHIFT 1 /**< Shift value for BURTC_BUMODETS */
<> 150:02e0a0aed4ec 224 #define _BURTC_STATUS_BUMODETS_MASK 0x2UL /**< Bit mask for BURTC_BUMODETS */
<> 150:02e0a0aed4ec 225 #define _BURTC_STATUS_BUMODETS_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_STATUS */
<> 150:02e0a0aed4ec 226 #define BURTC_STATUS_BUMODETS_DEFAULT (_BURTC_STATUS_BUMODETS_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_STATUS */
<> 150:02e0a0aed4ec 227 #define BURTC_STATUS_RAMWERR (0x1UL << 2) /**< RAM write error. */
<> 150:02e0a0aed4ec 228 #define _BURTC_STATUS_RAMWERR_SHIFT 2 /**< Shift value for BURTC_RAMWERR */
<> 150:02e0a0aed4ec 229 #define _BURTC_STATUS_RAMWERR_MASK 0x4UL /**< Bit mask for BURTC_RAMWERR */
<> 150:02e0a0aed4ec 230 #define _BURTC_STATUS_RAMWERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_STATUS */
<> 150:02e0a0aed4ec 231 #define BURTC_STATUS_RAMWERR_DEFAULT (_BURTC_STATUS_RAMWERR_DEFAULT << 2) /**< Shifted mode DEFAULT for BURTC_STATUS */
<> 150:02e0a0aed4ec 232
<> 150:02e0a0aed4ec 233 /* Bit fields for BURTC CMD */
<> 150:02e0a0aed4ec 234 #define _BURTC_CMD_RESETVALUE 0x00000000UL /**< Default value for BURTC_CMD */
<> 150:02e0a0aed4ec 235 #define _BURTC_CMD_MASK 0x00000001UL /**< Mask for BURTC_CMD */
<> 150:02e0a0aed4ec 236 #define BURTC_CMD_CLRSTATUS (0x1UL << 0) /**< Clear BURTC_STATUS register. */
<> 150:02e0a0aed4ec 237 #define _BURTC_CMD_CLRSTATUS_SHIFT 0 /**< Shift value for BURTC_CLRSTATUS */
<> 150:02e0a0aed4ec 238 #define _BURTC_CMD_CLRSTATUS_MASK 0x1UL /**< Bit mask for BURTC_CLRSTATUS */
<> 150:02e0a0aed4ec 239 #define _BURTC_CMD_CLRSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CMD */
<> 150:02e0a0aed4ec 240 #define BURTC_CMD_CLRSTATUS_DEFAULT (_BURTC_CMD_CLRSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CMD */
<> 150:02e0a0aed4ec 241
<> 150:02e0a0aed4ec 242 /* Bit fields for BURTC POWERDOWN */
<> 150:02e0a0aed4ec 243 #define _BURTC_POWERDOWN_RESETVALUE 0x00000000UL /**< Default value for BURTC_POWERDOWN */
<> 150:02e0a0aed4ec 244 #define _BURTC_POWERDOWN_MASK 0x00000001UL /**< Mask for BURTC_POWERDOWN */
<> 150:02e0a0aed4ec 245 #define BURTC_POWERDOWN_RAM (0x1UL << 0) /**< Retention RAM power-down */
<> 150:02e0a0aed4ec 246 #define _BURTC_POWERDOWN_RAM_SHIFT 0 /**< Shift value for BURTC_RAM */
<> 150:02e0a0aed4ec 247 #define _BURTC_POWERDOWN_RAM_MASK 0x1UL /**< Bit mask for BURTC_RAM */
<> 150:02e0a0aed4ec 248 #define _BURTC_POWERDOWN_RAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_POWERDOWN */
<> 150:02e0a0aed4ec 249 #define BURTC_POWERDOWN_RAM_DEFAULT (_BURTC_POWERDOWN_RAM_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_POWERDOWN */
<> 150:02e0a0aed4ec 250
<> 150:02e0a0aed4ec 251 /* Bit fields for BURTC LOCK */
<> 150:02e0a0aed4ec 252 #define _BURTC_LOCK_RESETVALUE 0x00000000UL /**< Default value for BURTC_LOCK */
<> 150:02e0a0aed4ec 253 #define _BURTC_LOCK_MASK 0x0000FFFFUL /**< Mask for BURTC_LOCK */
<> 150:02e0a0aed4ec 254 #define _BURTC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for BURTC_LOCKKEY */
<> 150:02e0a0aed4ec 255 #define _BURTC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for BURTC_LOCKKEY */
<> 150:02e0a0aed4ec 256 #define _BURTC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_LOCK */
<> 150:02e0a0aed4ec 257 #define _BURTC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for BURTC_LOCK */
<> 150:02e0a0aed4ec 258 #define _BURTC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for BURTC_LOCK */
<> 150:02e0a0aed4ec 259 #define _BURTC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for BURTC_LOCK */
<> 150:02e0a0aed4ec 260 #define _BURTC_LOCK_LOCKKEY_UNLOCK 0x0000AEE8UL /**< Mode UNLOCK for BURTC_LOCK */
<> 150:02e0a0aed4ec 261 #define BURTC_LOCK_LOCKKEY_DEFAULT (_BURTC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_LOCK */
<> 150:02e0a0aed4ec 262 #define BURTC_LOCK_LOCKKEY_LOCK (_BURTC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for BURTC_LOCK */
<> 150:02e0a0aed4ec 263 #define BURTC_LOCK_LOCKKEY_UNLOCKED (_BURTC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for BURTC_LOCK */
<> 150:02e0a0aed4ec 264 #define BURTC_LOCK_LOCKKEY_LOCKED (_BURTC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for BURTC_LOCK */
<> 150:02e0a0aed4ec 265 #define BURTC_LOCK_LOCKKEY_UNLOCK (_BURTC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for BURTC_LOCK */
<> 150:02e0a0aed4ec 266
<> 150:02e0a0aed4ec 267 /* Bit fields for BURTC IF */
<> 150:02e0a0aed4ec 268 #define _BURTC_IF_RESETVALUE 0x00000000UL /**< Default value for BURTC_IF */
<> 150:02e0a0aed4ec 269 #define _BURTC_IF_MASK 0x00000007UL /**< Mask for BURTC_IF */
<> 150:02e0a0aed4ec 270 #define BURTC_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */
<> 150:02e0a0aed4ec 271 #define _BURTC_IF_OF_SHIFT 0 /**< Shift value for BURTC_OF */
<> 150:02e0a0aed4ec 272 #define _BURTC_IF_OF_MASK 0x1UL /**< Bit mask for BURTC_OF */
<> 150:02e0a0aed4ec 273 #define _BURTC_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IF */
<> 150:02e0a0aed4ec 274 #define BURTC_IF_OF_DEFAULT (_BURTC_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IF */
<> 150:02e0a0aed4ec 275 #define BURTC_IF_COMP0 (0x1UL << 1) /**< Compare match Interrupt Flag */
<> 150:02e0a0aed4ec 276 #define _BURTC_IF_COMP0_SHIFT 1 /**< Shift value for BURTC_COMP0 */
<> 150:02e0a0aed4ec 277 #define _BURTC_IF_COMP0_MASK 0x2UL /**< Bit mask for BURTC_COMP0 */
<> 150:02e0a0aed4ec 278 #define _BURTC_IF_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IF */
<> 150:02e0a0aed4ec 279 #define BURTC_IF_COMP0_DEFAULT (_BURTC_IF_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_IF */
<> 150:02e0a0aed4ec 280 #define BURTC_IF_LFXOFAIL (0x1UL << 2) /**< LFXO failure Interrupt Flag */
<> 150:02e0a0aed4ec 281 #define _BURTC_IF_LFXOFAIL_SHIFT 2 /**< Shift value for BURTC_LFXOFAIL */
<> 150:02e0a0aed4ec 282 #define _BURTC_IF_LFXOFAIL_MASK 0x4UL /**< Bit mask for BURTC_LFXOFAIL */
<> 150:02e0a0aed4ec 283 #define _BURTC_IF_LFXOFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IF */
<> 150:02e0a0aed4ec 284 #define BURTC_IF_LFXOFAIL_DEFAULT (_BURTC_IF_LFXOFAIL_DEFAULT << 2) /**< Shifted mode DEFAULT for BURTC_IF */
<> 150:02e0a0aed4ec 285
<> 150:02e0a0aed4ec 286 /* Bit fields for BURTC IFS */
<> 150:02e0a0aed4ec 287 #define _BURTC_IFS_RESETVALUE 0x00000000UL /**< Default value for BURTC_IFS */
<> 150:02e0a0aed4ec 288 #define _BURTC_IFS_MASK 0x00000007UL /**< Mask for BURTC_IFS */
<> 150:02e0a0aed4ec 289 #define BURTC_IFS_OF (0x1UL << 0) /**< Set Overflow Interrupt Flag */
<> 150:02e0a0aed4ec 290 #define _BURTC_IFS_OF_SHIFT 0 /**< Shift value for BURTC_OF */
<> 150:02e0a0aed4ec 291 #define _BURTC_IFS_OF_MASK 0x1UL /**< Bit mask for BURTC_OF */
<> 150:02e0a0aed4ec 292 #define _BURTC_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IFS */
<> 150:02e0a0aed4ec 293 #define BURTC_IFS_OF_DEFAULT (_BURTC_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IFS */
<> 150:02e0a0aed4ec 294 #define BURTC_IFS_COMP0 (0x1UL << 1) /**< Set compare match Interrupt Flag */
<> 150:02e0a0aed4ec 295 #define _BURTC_IFS_COMP0_SHIFT 1 /**< Shift value for BURTC_COMP0 */
<> 150:02e0a0aed4ec 296 #define _BURTC_IFS_COMP0_MASK 0x2UL /**< Bit mask for BURTC_COMP0 */
<> 150:02e0a0aed4ec 297 #define _BURTC_IFS_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IFS */
<> 150:02e0a0aed4ec 298 #define BURTC_IFS_COMP0_DEFAULT (_BURTC_IFS_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_IFS */
<> 150:02e0a0aed4ec 299 #define BURTC_IFS_LFXOFAIL (0x1UL << 2) /**< Set LFXO fail Interrupt Flag */
<> 150:02e0a0aed4ec 300 #define _BURTC_IFS_LFXOFAIL_SHIFT 2 /**< Shift value for BURTC_LFXOFAIL */
<> 150:02e0a0aed4ec 301 #define _BURTC_IFS_LFXOFAIL_MASK 0x4UL /**< Bit mask for BURTC_LFXOFAIL */
<> 150:02e0a0aed4ec 302 #define _BURTC_IFS_LFXOFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IFS */
<> 150:02e0a0aed4ec 303 #define BURTC_IFS_LFXOFAIL_DEFAULT (_BURTC_IFS_LFXOFAIL_DEFAULT << 2) /**< Shifted mode DEFAULT for BURTC_IFS */
<> 150:02e0a0aed4ec 304
<> 150:02e0a0aed4ec 305 /* Bit fields for BURTC IFC */
<> 150:02e0a0aed4ec 306 #define _BURTC_IFC_RESETVALUE 0x00000000UL /**< Default value for BURTC_IFC */
<> 150:02e0a0aed4ec 307 #define _BURTC_IFC_MASK 0x00000007UL /**< Mask for BURTC_IFC */
<> 150:02e0a0aed4ec 308 #define BURTC_IFC_OF (0x1UL << 0) /**< Clear Overflow Interrupt Flag */
<> 150:02e0a0aed4ec 309 #define _BURTC_IFC_OF_SHIFT 0 /**< Shift value for BURTC_OF */
<> 150:02e0a0aed4ec 310 #define _BURTC_IFC_OF_MASK 0x1UL /**< Bit mask for BURTC_OF */
<> 150:02e0a0aed4ec 311 #define _BURTC_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IFC */
<> 150:02e0a0aed4ec 312 #define BURTC_IFC_OF_DEFAULT (_BURTC_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IFC */
<> 150:02e0a0aed4ec 313 #define BURTC_IFC_COMP0 (0x1UL << 1) /**< Clear compare match Interrupt Flag */
<> 150:02e0a0aed4ec 314 #define _BURTC_IFC_COMP0_SHIFT 1 /**< Shift value for BURTC_COMP0 */
<> 150:02e0a0aed4ec 315 #define _BURTC_IFC_COMP0_MASK 0x2UL /**< Bit mask for BURTC_COMP0 */
<> 150:02e0a0aed4ec 316 #define _BURTC_IFC_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IFC */
<> 150:02e0a0aed4ec 317 #define BURTC_IFC_COMP0_DEFAULT (_BURTC_IFC_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_IFC */
<> 150:02e0a0aed4ec 318 #define BURTC_IFC_LFXOFAIL (0x1UL << 2) /**< Clear LFXO failure Interrupt Flag */
<> 150:02e0a0aed4ec 319 #define _BURTC_IFC_LFXOFAIL_SHIFT 2 /**< Shift value for BURTC_LFXOFAIL */
<> 150:02e0a0aed4ec 320 #define _BURTC_IFC_LFXOFAIL_MASK 0x4UL /**< Bit mask for BURTC_LFXOFAIL */
<> 150:02e0a0aed4ec 321 #define _BURTC_IFC_LFXOFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IFC */
<> 150:02e0a0aed4ec 322 #define BURTC_IFC_LFXOFAIL_DEFAULT (_BURTC_IFC_LFXOFAIL_DEFAULT << 2) /**< Shifted mode DEFAULT for BURTC_IFC */
<> 150:02e0a0aed4ec 323
<> 150:02e0a0aed4ec 324 /* Bit fields for BURTC IEN */
<> 150:02e0a0aed4ec 325 #define _BURTC_IEN_RESETVALUE 0x00000000UL /**< Default value for BURTC_IEN */
<> 150:02e0a0aed4ec 326 #define _BURTC_IEN_MASK 0x00000007UL /**< Mask for BURTC_IEN */
<> 150:02e0a0aed4ec 327 #define BURTC_IEN_OF (0x1UL << 0) /**< Overflow Interrupt Enable */
<> 150:02e0a0aed4ec 328 #define _BURTC_IEN_OF_SHIFT 0 /**< Shift value for BURTC_OF */
<> 150:02e0a0aed4ec 329 #define _BURTC_IEN_OF_MASK 0x1UL /**< Bit mask for BURTC_OF */
<> 150:02e0a0aed4ec 330 #define _BURTC_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IEN */
<> 150:02e0a0aed4ec 331 #define BURTC_IEN_OF_DEFAULT (_BURTC_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IEN */
<> 150:02e0a0aed4ec 332 #define BURTC_IEN_COMP0 (0x1UL << 1) /**< Compare match Interrupt Enable */
<> 150:02e0a0aed4ec 333 #define _BURTC_IEN_COMP0_SHIFT 1 /**< Shift value for BURTC_COMP0 */
<> 150:02e0a0aed4ec 334 #define _BURTC_IEN_COMP0_MASK 0x2UL /**< Bit mask for BURTC_COMP0 */
<> 150:02e0a0aed4ec 335 #define _BURTC_IEN_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IEN */
<> 150:02e0a0aed4ec 336 #define BURTC_IEN_COMP0_DEFAULT (_BURTC_IEN_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_IEN */
<> 150:02e0a0aed4ec 337 #define BURTC_IEN_LFXOFAIL (0x1UL << 2) /**< LFXO failure Interrupt Enable */
<> 150:02e0a0aed4ec 338 #define _BURTC_IEN_LFXOFAIL_SHIFT 2 /**< Shift value for BURTC_LFXOFAIL */
<> 150:02e0a0aed4ec 339 #define _BURTC_IEN_LFXOFAIL_MASK 0x4UL /**< Bit mask for BURTC_LFXOFAIL */
<> 150:02e0a0aed4ec 340 #define _BURTC_IEN_LFXOFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IEN */
<> 150:02e0a0aed4ec 341 #define BURTC_IEN_LFXOFAIL_DEFAULT (_BURTC_IEN_LFXOFAIL_DEFAULT << 2) /**< Shifted mode DEFAULT for BURTC_IEN */
<> 150:02e0a0aed4ec 342
<> 150:02e0a0aed4ec 343 /* Bit fields for BURTC FREEZE */
<> 150:02e0a0aed4ec 344 #define _BURTC_FREEZE_RESETVALUE 0x00000000UL /**< Default value for BURTC_FREEZE */
<> 150:02e0a0aed4ec 345 #define _BURTC_FREEZE_MASK 0x00000001UL /**< Mask for BURTC_FREEZE */
<> 150:02e0a0aed4ec 346 #define BURTC_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */
<> 150:02e0a0aed4ec 347 #define _BURTC_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for BURTC_REGFREEZE */
<> 150:02e0a0aed4ec 348 #define _BURTC_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for BURTC_REGFREEZE */
<> 150:02e0a0aed4ec 349 #define _BURTC_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_FREEZE */
<> 150:02e0a0aed4ec 350 #define _BURTC_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for BURTC_FREEZE */
<> 150:02e0a0aed4ec 351 #define _BURTC_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for BURTC_FREEZE */
<> 150:02e0a0aed4ec 352 #define BURTC_FREEZE_REGFREEZE_DEFAULT (_BURTC_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_FREEZE */
<> 150:02e0a0aed4ec 353 #define BURTC_FREEZE_REGFREEZE_UPDATE (_BURTC_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for BURTC_FREEZE */
<> 150:02e0a0aed4ec 354 #define BURTC_FREEZE_REGFREEZE_FREEZE (_BURTC_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for BURTC_FREEZE */
<> 150:02e0a0aed4ec 355
<> 150:02e0a0aed4ec 356 /* Bit fields for BURTC SYNCBUSY */
<> 150:02e0a0aed4ec 357 #define _BURTC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for BURTC_SYNCBUSY */
<> 150:02e0a0aed4ec 358 #define _BURTC_SYNCBUSY_MASK 0x00000003UL /**< Mask for BURTC_SYNCBUSY */
<> 150:02e0a0aed4ec 359 #define BURTC_SYNCBUSY_LPMODE (0x1UL << 0) /**< LPMODE Register Busy */
<> 150:02e0a0aed4ec 360 #define _BURTC_SYNCBUSY_LPMODE_SHIFT 0 /**< Shift value for BURTC_LPMODE */
<> 150:02e0a0aed4ec 361 #define _BURTC_SYNCBUSY_LPMODE_MASK 0x1UL /**< Bit mask for BURTC_LPMODE */
<> 150:02e0a0aed4ec 362 #define _BURTC_SYNCBUSY_LPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */
<> 150:02e0a0aed4ec 363 #define BURTC_SYNCBUSY_LPMODE_DEFAULT (_BURTC_SYNCBUSY_LPMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */
<> 150:02e0a0aed4ec 364 #define BURTC_SYNCBUSY_COMP0 (0x1UL << 1) /**< COMP0 Register Busy */
<> 150:02e0a0aed4ec 365 #define _BURTC_SYNCBUSY_COMP0_SHIFT 1 /**< Shift value for BURTC_COMP0 */
<> 150:02e0a0aed4ec 366 #define _BURTC_SYNCBUSY_COMP0_MASK 0x2UL /**< Bit mask for BURTC_COMP0 */
<> 150:02e0a0aed4ec 367 #define _BURTC_SYNCBUSY_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */
<> 150:02e0a0aed4ec 368 #define BURTC_SYNCBUSY_COMP0_DEFAULT (_BURTC_SYNCBUSY_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */
<> 150:02e0a0aed4ec 369
<> 150:02e0a0aed4ec 370 /* Bit fields for BURTC RET_REG */
<> 150:02e0a0aed4ec 371 #define _BURTC_RET_REG_RESETVALUE 0x00000000UL /**< Default value for BURTC_RET_REG */
<> 150:02e0a0aed4ec 372 #define _BURTC_RET_REG_MASK 0xFFFFFFFFUL /**< Mask for BURTC_RET_REG */
<> 150:02e0a0aed4ec 373 #define _BURTC_RET_REG_REG_SHIFT 0 /**< Shift value for REG */
<> 150:02e0a0aed4ec 374 #define _BURTC_RET_REG_REG_MASK 0xFFFFFFFFUL /**< Bit mask for REG */
<> 150:02e0a0aed4ec 375 #define _BURTC_RET_REG_REG_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_RET_REG */
<> 150:02e0a0aed4ec 376 #define BURTC_RET_REG_REG_DEFAULT (_BURTC_RET_REG_REG_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_RET_REG */
<> 150:02e0a0aed4ec 377
<> 150:02e0a0aed4ec 378 /** @} End of group EFM32WG_BURTC */
<> 150:02e0a0aed4ec 379 /** @} End of group Parts */
<> 150:02e0a0aed4ec 380