Fawwaz Nadzmy / mbed-STM

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_aes.h@153:9398a535854b, 2016-12-22 (annotated)

Committer:
fwndz
Date:
Thu Dec 22 05:12:40 2016 +0000
Revision:
153:9398a535854b
Parent:
150:02e0a0aed4ec 
device target maximize

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 150:02e0a0aed4ec 1 /**************************************************************************//**
<> 150:02e0a0aed4ec 2 * @file efm32wg_aes.h
<> 150:02e0a0aed4ec 3 * @brief EFM32WG_AES register and bit field definitions
<> 150:02e0a0aed4ec 4 * @version 5.0.0
<> 150:02e0a0aed4ec 5 ******************************************************************************
<> 150:02e0a0aed4ec 6 * @section License
<> 150:02e0a0aed4ec 7 * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 150:02e0a0aed4ec 8 ******************************************************************************
<> 150:02e0a0aed4ec 9 *
<> 150:02e0a0aed4ec 10 * Permission is granted to anyone to use this software for any purpose,
<> 150:02e0a0aed4ec 11 * including commercial applications, and to alter it and redistribute it
<> 150:02e0a0aed4ec 12 * freely, subject to the following restrictions:
<> 150:02e0a0aed4ec 13 *
<> 150:02e0a0aed4ec 14 * 1. The origin of this software must not be misrepresented; you must not
<> 150:02e0a0aed4ec 15 * claim that you wrote the original software.@n
<> 150:02e0a0aed4ec 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 150:02e0a0aed4ec 17 * misrepresented as being the original software.@n
<> 150:02e0a0aed4ec 18 * 3. This notice may not be removed or altered from any source distribution.
<> 150:02e0a0aed4ec 19 *
<> 150:02e0a0aed4ec 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 150:02e0a0aed4ec 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 150:02e0a0aed4ec 22 * providing the Software "AS IS", with no express or implied warranties of any
<> 150:02e0a0aed4ec 23 * kind, including, but not limited to, any implied warranties of
<> 150:02e0a0aed4ec 24 * merchantability or fitness for any particular purpose or warranties against
<> 150:02e0a0aed4ec 25 * infringement of any proprietary rights of a third party.
<> 150:02e0a0aed4ec 26 *
<> 150:02e0a0aed4ec 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 150:02e0a0aed4ec 28 * incidental, or special damages, or any other relief, or for any claim by
<> 150:02e0a0aed4ec 29 * any third party, arising from your use of this Software.
<> 150:02e0a0aed4ec 30 *
<> 150:02e0a0aed4ec 31 *****************************************************************************/
<> 150:02e0a0aed4ec 32 /**************************************************************************//**
<> 150:02e0a0aed4ec 33 * @addtogroup Parts
<> 150:02e0a0aed4ec 34 * @{
<> 150:02e0a0aed4ec 35 ******************************************************************************/
<> 150:02e0a0aed4ec 36 /**************************************************************************//**
<> 150:02e0a0aed4ec 37 * @defgroup EFM32WG_AES
<> 150:02e0a0aed4ec 38 * @{
<> 150:02e0a0aed4ec 39 * @brief EFM32WG_AES Register Declaration
<> 150:02e0a0aed4ec 40 *****************************************************************************/
<> 150:02e0a0aed4ec 41 typedef struct
<> 150:02e0a0aed4ec 42 {
<> 150:02e0a0aed4ec 43 __IOM uint32_t CTRL; /**< Control Register */
<> 150:02e0a0aed4ec 44 __IOM uint32_t CMD; /**< Command Register */
<> 150:02e0a0aed4ec 45 __IM uint32_t STATUS; /**< Status Register */
<> 150:02e0a0aed4ec 46 __IOM uint32_t IEN; /**< Interrupt Enable Register */
<> 150:02e0a0aed4ec 47 __IM uint32_t IF; /**< Interrupt Flag Register */
<> 150:02e0a0aed4ec 48 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
<> 150:02e0a0aed4ec 49 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
<> 150:02e0a0aed4ec 50 __IOM uint32_t DATA; /**< DATA Register */
<> 150:02e0a0aed4ec 51 __IOM uint32_t XORDATA; /**< XORDATA Register */
<> 150:02e0a0aed4ec 52 uint32_t RESERVED0[3]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 53 __IOM uint32_t KEYLA; /**< KEY Low Register */
<> 150:02e0a0aed4ec 54 __IOM uint32_t KEYLB; /**< KEY Low Register */
<> 150:02e0a0aed4ec 55 __IOM uint32_t KEYLC; /**< KEY Low Register */
<> 150:02e0a0aed4ec 56 __IOM uint32_t KEYLD; /**< KEY Low Register */
<> 150:02e0a0aed4ec 57 __IOM uint32_t KEYHA; /**< KEY High Register */
<> 150:02e0a0aed4ec 58 __IOM uint32_t KEYHB; /**< KEY High Register */
<> 150:02e0a0aed4ec 59 __IOM uint32_t KEYHC; /**< KEY High Register */
<> 150:02e0a0aed4ec 60 __IOM uint32_t KEYHD; /**< KEY High Register */
<> 150:02e0a0aed4ec 61 } AES_TypeDef; /** @} */
<> 150:02e0a0aed4ec 62
<> 150:02e0a0aed4ec 63 /**************************************************************************//**
<> 150:02e0a0aed4ec 64 * @defgroup EFM32WG_AES_BitFields
<> 150:02e0a0aed4ec 65 * @{
<> 150:02e0a0aed4ec 66 *****************************************************************************/
<> 150:02e0a0aed4ec 67
<> 150:02e0a0aed4ec 68 /* Bit fields for AES CTRL */
<> 150:02e0a0aed4ec 69 #define _AES_CTRL_RESETVALUE 0x00000000UL /**< Default value for AES_CTRL */
<> 150:02e0a0aed4ec 70 #define _AES_CTRL_MASK 0x00000077UL /**< Mask for AES_CTRL */
<> 150:02e0a0aed4ec 71 #define AES_CTRL_DECRYPT (0x1UL << 0) /**< Decryption/Encryption Mode */
<> 150:02e0a0aed4ec 72 #define _AES_CTRL_DECRYPT_SHIFT 0 /**< Shift value for AES_DECRYPT */
<> 150:02e0a0aed4ec 73 #define _AES_CTRL_DECRYPT_MASK 0x1UL /**< Bit mask for AES_DECRYPT */
<> 150:02e0a0aed4ec 74 #define _AES_CTRL_DECRYPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */
<> 150:02e0a0aed4ec 75 #define AES_CTRL_DECRYPT_DEFAULT (_AES_CTRL_DECRYPT_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_CTRL */
<> 150:02e0a0aed4ec 76 #define AES_CTRL_AES256 (0x1UL << 1) /**< AES-256 Mode */
<> 150:02e0a0aed4ec 77 #define _AES_CTRL_AES256_SHIFT 1 /**< Shift value for AES_AES256 */
<> 150:02e0a0aed4ec 78 #define _AES_CTRL_AES256_MASK 0x2UL /**< Bit mask for AES_AES256 */
<> 150:02e0a0aed4ec 79 #define _AES_CTRL_AES256_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */
<> 150:02e0a0aed4ec 80 #define AES_CTRL_AES256_DEFAULT (_AES_CTRL_AES256_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_CTRL */
<> 150:02e0a0aed4ec 81 #define AES_CTRL_KEYBUFEN (0x1UL << 2) /**< Key Buffer Enable */
<> 150:02e0a0aed4ec 82 #define _AES_CTRL_KEYBUFEN_SHIFT 2 /**< Shift value for AES_KEYBUFEN */
<> 150:02e0a0aed4ec 83 #define _AES_CTRL_KEYBUFEN_MASK 0x4UL /**< Bit mask for AES_KEYBUFEN */
<> 150:02e0a0aed4ec 84 #define _AES_CTRL_KEYBUFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */
<> 150:02e0a0aed4ec 85 #define AES_CTRL_KEYBUFEN_DEFAULT (_AES_CTRL_KEYBUFEN_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_CTRL */
<> 150:02e0a0aed4ec 86 #define AES_CTRL_DATASTART (0x1UL << 4) /**< AES_DATA Write Start */
<> 150:02e0a0aed4ec 87 #define _AES_CTRL_DATASTART_SHIFT 4 /**< Shift value for AES_DATASTART */
<> 150:02e0a0aed4ec 88 #define _AES_CTRL_DATASTART_MASK 0x10UL /**< Bit mask for AES_DATASTART */
<> 150:02e0a0aed4ec 89 #define _AES_CTRL_DATASTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */
<> 150:02e0a0aed4ec 90 #define AES_CTRL_DATASTART_DEFAULT (_AES_CTRL_DATASTART_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_CTRL */
<> 150:02e0a0aed4ec 91 #define AES_CTRL_XORSTART (0x1UL << 5) /**< AES_XORDATA Write Start */
<> 150:02e0a0aed4ec 92 #define _AES_CTRL_XORSTART_SHIFT 5 /**< Shift value for AES_XORSTART */
<> 150:02e0a0aed4ec 93 #define _AES_CTRL_XORSTART_MASK 0x20UL /**< Bit mask for AES_XORSTART */
<> 150:02e0a0aed4ec 94 #define _AES_CTRL_XORSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */
<> 150:02e0a0aed4ec 95 #define AES_CTRL_XORSTART_DEFAULT (_AES_CTRL_XORSTART_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_CTRL */
<> 150:02e0a0aed4ec 96 #define AES_CTRL_BYTEORDER (0x1UL << 6) /**< Configure byte order in data and key registers */
<> 150:02e0a0aed4ec 97 #define _AES_CTRL_BYTEORDER_SHIFT 6 /**< Shift value for AES_BYTEORDER */
<> 150:02e0a0aed4ec 98 #define _AES_CTRL_BYTEORDER_MASK 0x40UL /**< Bit mask for AES_BYTEORDER */
<> 150:02e0a0aed4ec 99 #define _AES_CTRL_BYTEORDER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */
<> 150:02e0a0aed4ec 100 #define AES_CTRL_BYTEORDER_DEFAULT (_AES_CTRL_BYTEORDER_DEFAULT << 6) /**< Shifted mode DEFAULT for AES_CTRL */
<> 150:02e0a0aed4ec 101
<> 150:02e0a0aed4ec 102 /* Bit fields for AES CMD */
<> 150:02e0a0aed4ec 103 #define _AES_CMD_RESETVALUE 0x00000000UL /**< Default value for AES_CMD */
<> 150:02e0a0aed4ec 104 #define _AES_CMD_MASK 0x00000003UL /**< Mask for AES_CMD */
<> 150:02e0a0aed4ec 105 #define AES_CMD_START (0x1UL << 0) /**< Encryption/Decryption Start */
<> 150:02e0a0aed4ec 106 #define _AES_CMD_START_SHIFT 0 /**< Shift value for AES_START */
<> 150:02e0a0aed4ec 107 #define _AES_CMD_START_MASK 0x1UL /**< Bit mask for AES_START */
<> 150:02e0a0aed4ec 108 #define _AES_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CMD */
<> 150:02e0a0aed4ec 109 #define AES_CMD_START_DEFAULT (_AES_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_CMD */
<> 150:02e0a0aed4ec 110 #define AES_CMD_STOP (0x1UL << 1) /**< Encryption/Decryption Stop */
<> 150:02e0a0aed4ec 111 #define _AES_CMD_STOP_SHIFT 1 /**< Shift value for AES_STOP */
<> 150:02e0a0aed4ec 112 #define _AES_CMD_STOP_MASK 0x2UL /**< Bit mask for AES_STOP */
<> 150:02e0a0aed4ec 113 #define _AES_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CMD */
<> 150:02e0a0aed4ec 114 #define AES_CMD_STOP_DEFAULT (_AES_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_CMD */
<> 150:02e0a0aed4ec 115
<> 150:02e0a0aed4ec 116 /* Bit fields for AES STATUS */
<> 150:02e0a0aed4ec 117 #define _AES_STATUS_RESETVALUE 0x00000000UL /**< Default value for AES_STATUS */
<> 150:02e0a0aed4ec 118 #define _AES_STATUS_MASK 0x00000001UL /**< Mask for AES_STATUS */
<> 150:02e0a0aed4ec 119 #define AES_STATUS_RUNNING (0x1UL << 0) /**< AES Running */
<> 150:02e0a0aed4ec 120 #define _AES_STATUS_RUNNING_SHIFT 0 /**< Shift value for AES_RUNNING */
<> 150:02e0a0aed4ec 121 #define _AES_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for AES_RUNNING */
<> 150:02e0a0aed4ec 122 #define _AES_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */
<> 150:02e0a0aed4ec 123 #define AES_STATUS_RUNNING_DEFAULT (_AES_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_STATUS */
<> 150:02e0a0aed4ec 124
<> 150:02e0a0aed4ec 125 /* Bit fields for AES IEN */
<> 150:02e0a0aed4ec 126 #define _AES_IEN_RESETVALUE 0x00000000UL /**< Default value for AES_IEN */
<> 150:02e0a0aed4ec 127 #define _AES_IEN_MASK 0x00000001UL /**< Mask for AES_IEN */
<> 150:02e0a0aed4ec 128 #define AES_IEN_DONE (0x1UL << 0) /**< Encryption/Decryption Done Interrupt Enable */
<> 150:02e0a0aed4ec 129 #define _AES_IEN_DONE_SHIFT 0 /**< Shift value for AES_DONE */
<> 150:02e0a0aed4ec 130 #define _AES_IEN_DONE_MASK 0x1UL /**< Bit mask for AES_DONE */
<> 150:02e0a0aed4ec 131 #define _AES_IEN_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */
<> 150:02e0a0aed4ec 132 #define AES_IEN_DONE_DEFAULT (_AES_IEN_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IEN */
<> 150:02e0a0aed4ec 133
<> 150:02e0a0aed4ec 134 /* Bit fields for AES IF */
<> 150:02e0a0aed4ec 135 #define _AES_IF_RESETVALUE 0x00000000UL /**< Default value for AES_IF */
<> 150:02e0a0aed4ec 136 #define _AES_IF_MASK 0x00000001UL /**< Mask for AES_IF */
<> 150:02e0a0aed4ec 137 #define AES_IF_DONE (0x1UL << 0) /**< Encryption/Decryption Done Interrupt Flag */
<> 150:02e0a0aed4ec 138 #define _AES_IF_DONE_SHIFT 0 /**< Shift value for AES_DONE */
<> 150:02e0a0aed4ec 139 #define _AES_IF_DONE_MASK 0x1UL /**< Bit mask for AES_DONE */
<> 150:02e0a0aed4ec 140 #define _AES_IF_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */
<> 150:02e0a0aed4ec 141 #define AES_IF_DONE_DEFAULT (_AES_IF_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IF */
<> 150:02e0a0aed4ec 142
<> 150:02e0a0aed4ec 143 /* Bit fields for AES IFS */
<> 150:02e0a0aed4ec 144 #define _AES_IFS_RESETVALUE 0x00000000UL /**< Default value for AES_IFS */
<> 150:02e0a0aed4ec 145 #define _AES_IFS_MASK 0x00000001UL /**< Mask for AES_IFS */
<> 150:02e0a0aed4ec 146 #define AES_IFS_DONE (0x1UL << 0) /**< Encryption/Decryption Done Interrupt Flag Set */
<> 150:02e0a0aed4ec 147 #define _AES_IFS_DONE_SHIFT 0 /**< Shift value for AES_DONE */
<> 150:02e0a0aed4ec 148 #define _AES_IFS_DONE_MASK 0x1UL /**< Bit mask for AES_DONE */
<> 150:02e0a0aed4ec 149 #define _AES_IFS_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IFS */
<> 150:02e0a0aed4ec 150 #define AES_IFS_DONE_DEFAULT (_AES_IFS_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IFS */
<> 150:02e0a0aed4ec 151
<> 150:02e0a0aed4ec 152 /* Bit fields for AES IFC */
<> 150:02e0a0aed4ec 153 #define _AES_IFC_RESETVALUE 0x00000000UL /**< Default value for AES_IFC */
<> 150:02e0a0aed4ec 154 #define _AES_IFC_MASK 0x00000001UL /**< Mask for AES_IFC */
<> 150:02e0a0aed4ec 155 #define AES_IFC_DONE (0x1UL << 0) /**< Encryption/Decryption Done Interrupt Flag Clear */
<> 150:02e0a0aed4ec 156 #define _AES_IFC_DONE_SHIFT 0 /**< Shift value for AES_DONE */
<> 150:02e0a0aed4ec 157 #define _AES_IFC_DONE_MASK 0x1UL /**< Bit mask for AES_DONE */
<> 150:02e0a0aed4ec 158 #define _AES_IFC_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IFC */
<> 150:02e0a0aed4ec 159 #define AES_IFC_DONE_DEFAULT (_AES_IFC_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IFC */
<> 150:02e0a0aed4ec 160
<> 150:02e0a0aed4ec 161 /* Bit fields for AES DATA */
<> 150:02e0a0aed4ec 162 #define _AES_DATA_RESETVALUE 0x00000000UL /**< Default value for AES_DATA */
<> 150:02e0a0aed4ec 163 #define _AES_DATA_MASK 0xFFFFFFFFUL /**< Mask for AES_DATA */
<> 150:02e0a0aed4ec 164 #define _AES_DATA_DATA_SHIFT 0 /**< Shift value for AES_DATA */
<> 150:02e0a0aed4ec 165 #define _AES_DATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for AES_DATA */
<> 150:02e0a0aed4ec 166 #define _AES_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_DATA */
<> 150:02e0a0aed4ec 167 #define AES_DATA_DATA_DEFAULT (_AES_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_DATA */
<> 150:02e0a0aed4ec 168
<> 150:02e0a0aed4ec 169 /* Bit fields for AES XORDATA */
<> 150:02e0a0aed4ec 170 #define _AES_XORDATA_RESETVALUE 0x00000000UL /**< Default value for AES_XORDATA */
<> 150:02e0a0aed4ec 171 #define _AES_XORDATA_MASK 0xFFFFFFFFUL /**< Mask for AES_XORDATA */
<> 150:02e0a0aed4ec 172 #define _AES_XORDATA_XORDATA_SHIFT 0 /**< Shift value for AES_XORDATA */
<> 150:02e0a0aed4ec 173 #define _AES_XORDATA_XORDATA_MASK 0xFFFFFFFFUL /**< Bit mask for AES_XORDATA */
<> 150:02e0a0aed4ec 174 #define _AES_XORDATA_XORDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_XORDATA */
<> 150:02e0a0aed4ec 175 #define AES_XORDATA_XORDATA_DEFAULT (_AES_XORDATA_XORDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_XORDATA */
<> 150:02e0a0aed4ec 176
<> 150:02e0a0aed4ec 177 /* Bit fields for AES KEYLA */
<> 150:02e0a0aed4ec 178 #define _AES_KEYLA_RESETVALUE 0x00000000UL /**< Default value for AES_KEYLA */
<> 150:02e0a0aed4ec 179 #define _AES_KEYLA_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYLA */
<> 150:02e0a0aed4ec 180 #define _AES_KEYLA_KEYLA_SHIFT 0 /**< Shift value for AES_KEYLA */
<> 150:02e0a0aed4ec 181 #define _AES_KEYLA_KEYLA_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYLA */
<> 150:02e0a0aed4ec 182 #define _AES_KEYLA_KEYLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYLA */
<> 150:02e0a0aed4ec 183 #define AES_KEYLA_KEYLA_DEFAULT (_AES_KEYLA_KEYLA_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYLA */
<> 150:02e0a0aed4ec 184
<> 150:02e0a0aed4ec 185 /* Bit fields for AES KEYLB */
<> 150:02e0a0aed4ec 186 #define _AES_KEYLB_RESETVALUE 0x00000000UL /**< Default value for AES_KEYLB */
<> 150:02e0a0aed4ec 187 #define _AES_KEYLB_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYLB */
<> 150:02e0a0aed4ec 188 #define _AES_KEYLB_KEYLB_SHIFT 0 /**< Shift value for AES_KEYLB */
<> 150:02e0a0aed4ec 189 #define _AES_KEYLB_KEYLB_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYLB */
<> 150:02e0a0aed4ec 190 #define _AES_KEYLB_KEYLB_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYLB */
<> 150:02e0a0aed4ec 191 #define AES_KEYLB_KEYLB_DEFAULT (_AES_KEYLB_KEYLB_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYLB */
<> 150:02e0a0aed4ec 192
<> 150:02e0a0aed4ec 193 /* Bit fields for AES KEYLC */
<> 150:02e0a0aed4ec 194 #define _AES_KEYLC_RESETVALUE 0x00000000UL /**< Default value for AES_KEYLC */
<> 150:02e0a0aed4ec 195 #define _AES_KEYLC_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYLC */
<> 150:02e0a0aed4ec 196 #define _AES_KEYLC_KEYLC_SHIFT 0 /**< Shift value for AES_KEYLC */
<> 150:02e0a0aed4ec 197 #define _AES_KEYLC_KEYLC_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYLC */
<> 150:02e0a0aed4ec 198 #define _AES_KEYLC_KEYLC_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYLC */
<> 150:02e0a0aed4ec 199 #define AES_KEYLC_KEYLC_DEFAULT (_AES_KEYLC_KEYLC_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYLC */
<> 150:02e0a0aed4ec 200
<> 150:02e0a0aed4ec 201 /* Bit fields for AES KEYLD */
<> 150:02e0a0aed4ec 202 #define _AES_KEYLD_RESETVALUE 0x00000000UL /**< Default value for AES_KEYLD */
<> 150:02e0a0aed4ec 203 #define _AES_KEYLD_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYLD */
<> 150:02e0a0aed4ec 204 #define _AES_KEYLD_KEYLD_SHIFT 0 /**< Shift value for AES_KEYLD */
<> 150:02e0a0aed4ec 205 #define _AES_KEYLD_KEYLD_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYLD */
<> 150:02e0a0aed4ec 206 #define _AES_KEYLD_KEYLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYLD */
<> 150:02e0a0aed4ec 207 #define AES_KEYLD_KEYLD_DEFAULT (_AES_KEYLD_KEYLD_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYLD */
<> 150:02e0a0aed4ec 208
<> 150:02e0a0aed4ec 209 /* Bit fields for AES KEYHA */
<> 150:02e0a0aed4ec 210 #define _AES_KEYHA_RESETVALUE 0x00000000UL /**< Default value for AES_KEYHA */
<> 150:02e0a0aed4ec 211 #define _AES_KEYHA_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYHA */
<> 150:02e0a0aed4ec 212 #define _AES_KEYHA_KEYHA_SHIFT 0 /**< Shift value for AES_KEYHA */
<> 150:02e0a0aed4ec 213 #define _AES_KEYHA_KEYHA_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYHA */
<> 150:02e0a0aed4ec 214 #define _AES_KEYHA_KEYHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYHA */
<> 150:02e0a0aed4ec 215 #define AES_KEYHA_KEYHA_DEFAULT (_AES_KEYHA_KEYHA_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYHA */
<> 150:02e0a0aed4ec 216
<> 150:02e0a0aed4ec 217 /* Bit fields for AES KEYHB */
<> 150:02e0a0aed4ec 218 #define _AES_KEYHB_RESETVALUE 0x00000000UL /**< Default value for AES_KEYHB */
<> 150:02e0a0aed4ec 219 #define _AES_KEYHB_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYHB */
<> 150:02e0a0aed4ec 220 #define _AES_KEYHB_KEYHB_SHIFT 0 /**< Shift value for AES_KEYHB */
<> 150:02e0a0aed4ec 221 #define _AES_KEYHB_KEYHB_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYHB */
<> 150:02e0a0aed4ec 222 #define _AES_KEYHB_KEYHB_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYHB */
<> 150:02e0a0aed4ec 223 #define AES_KEYHB_KEYHB_DEFAULT (_AES_KEYHB_KEYHB_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYHB */
<> 150:02e0a0aed4ec 224
<> 150:02e0a0aed4ec 225 /* Bit fields for AES KEYHC */
<> 150:02e0a0aed4ec 226 #define _AES_KEYHC_RESETVALUE 0x00000000UL /**< Default value for AES_KEYHC */
<> 150:02e0a0aed4ec 227 #define _AES_KEYHC_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYHC */
<> 150:02e0a0aed4ec 228 #define _AES_KEYHC_KEYHC_SHIFT 0 /**< Shift value for AES_KEYHC */
<> 150:02e0a0aed4ec 229 #define _AES_KEYHC_KEYHC_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYHC */
<> 150:02e0a0aed4ec 230 #define _AES_KEYHC_KEYHC_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYHC */
<> 150:02e0a0aed4ec 231 #define AES_KEYHC_KEYHC_DEFAULT (_AES_KEYHC_KEYHC_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYHC */
<> 150:02e0a0aed4ec 232
<> 150:02e0a0aed4ec 233 /* Bit fields for AES KEYHD */
<> 150:02e0a0aed4ec 234 #define _AES_KEYHD_RESETVALUE 0x00000000UL /**< Default value for AES_KEYHD */
<> 150:02e0a0aed4ec 235 #define _AES_KEYHD_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYHD */
<> 150:02e0a0aed4ec 236 #define _AES_KEYHD_KEYHD_SHIFT 0 /**< Shift value for AES_KEYHD */
<> 150:02e0a0aed4ec 237 #define _AES_KEYHD_KEYHD_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYHD */
<> 150:02e0a0aed4ec 238 #define _AES_KEYHD_KEYHD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYHD */
<> 150:02e0a0aed4ec 239 #define AES_KEYHD_KEYHD_DEFAULT (_AES_KEYHD_KEYHD_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYHD */
<> 150:02e0a0aed4ec 240
<> 150:02e0a0aed4ec 241 /** @} End of group EFM32WG_AES */
<> 150:02e0a0aed4ec 242 /** @} End of group Parts */
<> 150:02e0a0aed4ec 243