Fawwaz Nadzmy / mbed-STM

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_acmp.h@153:9398a535854b, 2016-12-22 (annotated)

Committer:
fwndz
Date:
Thu Dec 22 05:12:40 2016 +0000
Revision:
153:9398a535854b
Parent:
150:02e0a0aed4ec 
device target maximize

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 150:02e0a0aed4ec 1 /**************************************************************************//**
<> 150:02e0a0aed4ec 2 * @file efm32wg_acmp.h
<> 150:02e0a0aed4ec 3 * @brief EFM32WG_ACMP register and bit field definitions
<> 150:02e0a0aed4ec 4 * @version 5.0.0
<> 150:02e0a0aed4ec 5 ******************************************************************************
<> 150:02e0a0aed4ec 6 * @section License
<> 150:02e0a0aed4ec 7 * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 150:02e0a0aed4ec 8 ******************************************************************************
<> 150:02e0a0aed4ec 9 *
<> 150:02e0a0aed4ec 10 * Permission is granted to anyone to use this software for any purpose,
<> 150:02e0a0aed4ec 11 * including commercial applications, and to alter it and redistribute it
<> 150:02e0a0aed4ec 12 * freely, subject to the following restrictions:
<> 150:02e0a0aed4ec 13 *
<> 150:02e0a0aed4ec 14 * 1. The origin of this software must not be misrepresented; you must not
<> 150:02e0a0aed4ec 15 * claim that you wrote the original software.@n
<> 150:02e0a0aed4ec 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 150:02e0a0aed4ec 17 * misrepresented as being the original software.@n
<> 150:02e0a0aed4ec 18 * 3. This notice may not be removed or altered from any source distribution.
<> 150:02e0a0aed4ec 19 *
<> 150:02e0a0aed4ec 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 150:02e0a0aed4ec 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 150:02e0a0aed4ec 22 * providing the Software "AS IS", with no express or implied warranties of any
<> 150:02e0a0aed4ec 23 * kind, including, but not limited to, any implied warranties of
<> 150:02e0a0aed4ec 24 * merchantability or fitness for any particular purpose or warranties against
<> 150:02e0a0aed4ec 25 * infringement of any proprietary rights of a third party.
<> 150:02e0a0aed4ec 26 *
<> 150:02e0a0aed4ec 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 150:02e0a0aed4ec 28 * incidental, or special damages, or any other relief, or for any claim by
<> 150:02e0a0aed4ec 29 * any third party, arising from your use of this Software.
<> 150:02e0a0aed4ec 30 *
<> 150:02e0a0aed4ec 31 *****************************************************************************/
<> 150:02e0a0aed4ec 32 /**************************************************************************//**
<> 150:02e0a0aed4ec 33 * @addtogroup Parts
<> 150:02e0a0aed4ec 34 * @{
<> 150:02e0a0aed4ec 35 ******************************************************************************/
<> 150:02e0a0aed4ec 36 /**************************************************************************//**
<> 150:02e0a0aed4ec 37 * @defgroup EFM32WG_ACMP
<> 150:02e0a0aed4ec 38 * @{
<> 150:02e0a0aed4ec 39 * @brief EFM32WG_ACMP Register Declaration
<> 150:02e0a0aed4ec 40 *****************************************************************************/
<> 150:02e0a0aed4ec 41 typedef struct
<> 150:02e0a0aed4ec 42 {
<> 150:02e0a0aed4ec 43 __IOM uint32_t CTRL; /**< Control Register */
<> 150:02e0a0aed4ec 44 __IOM uint32_t INPUTSEL; /**< Input Selection Register */
<> 150:02e0a0aed4ec 45 __IM uint32_t STATUS; /**< Status Register */
<> 150:02e0a0aed4ec 46 __IOM uint32_t IEN; /**< Interrupt Enable Register */
<> 150:02e0a0aed4ec 47 __IM uint32_t IF; /**< Interrupt Flag Register */
<> 150:02e0a0aed4ec 48 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
<> 150:02e0a0aed4ec 49 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
<> 150:02e0a0aed4ec 50 __IOM uint32_t ROUTE; /**< I/O Routing Register */
<> 150:02e0a0aed4ec 51 } ACMP_TypeDef; /** @} */
<> 150:02e0a0aed4ec 52
<> 150:02e0a0aed4ec 53 /**************************************************************************//**
<> 150:02e0a0aed4ec 54 * @defgroup EFM32WG_ACMP_BitFields
<> 150:02e0a0aed4ec 55 * @{
<> 150:02e0a0aed4ec 56 *****************************************************************************/
<> 150:02e0a0aed4ec 57
<> 150:02e0a0aed4ec 58 /* Bit fields for ACMP CTRL */
<> 150:02e0a0aed4ec 59 #define _ACMP_CTRL_RESETVALUE 0x47000000UL /**< Default value for ACMP_CTRL */
<> 150:02e0a0aed4ec 60 #define _ACMP_CTRL_MASK 0xCF03077FUL /**< Mask for ACMP_CTRL */
<> 150:02e0a0aed4ec 61 #define ACMP_CTRL_EN (0x1UL << 0) /**< Analog Comparator Enable */
<> 150:02e0a0aed4ec 62 #define _ACMP_CTRL_EN_SHIFT 0 /**< Shift value for ACMP_EN */
<> 150:02e0a0aed4ec 63 #define _ACMP_CTRL_EN_MASK 0x1UL /**< Bit mask for ACMP_EN */
<> 150:02e0a0aed4ec 64 #define _ACMP_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
<> 150:02e0a0aed4ec 65 #define ACMP_CTRL_EN_DEFAULT (_ACMP_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_CTRL */
<> 150:02e0a0aed4ec 66 #define ACMP_CTRL_MUXEN (0x1UL << 1) /**< Input Mux Enable */
<> 150:02e0a0aed4ec 67 #define _ACMP_CTRL_MUXEN_SHIFT 1 /**< Shift value for ACMP_MUXEN */
<> 150:02e0a0aed4ec 68 #define _ACMP_CTRL_MUXEN_MASK 0x2UL /**< Bit mask for ACMP_MUXEN */
<> 150:02e0a0aed4ec 69 #define _ACMP_CTRL_MUXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
<> 150:02e0a0aed4ec 70 #define ACMP_CTRL_MUXEN_DEFAULT (_ACMP_CTRL_MUXEN_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_CTRL */
<> 150:02e0a0aed4ec 71 #define ACMP_CTRL_INACTVAL (0x1UL << 2) /**< Inactive Value */
<> 150:02e0a0aed4ec 72 #define _ACMP_CTRL_INACTVAL_SHIFT 2 /**< Shift value for ACMP_INACTVAL */
<> 150:02e0a0aed4ec 73 #define _ACMP_CTRL_INACTVAL_MASK 0x4UL /**< Bit mask for ACMP_INACTVAL */
<> 150:02e0a0aed4ec 74 #define _ACMP_CTRL_INACTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
<> 150:02e0a0aed4ec 75 #define _ACMP_CTRL_INACTVAL_LOW 0x00000000UL /**< Mode LOW for ACMP_CTRL */
<> 150:02e0a0aed4ec 76 #define _ACMP_CTRL_INACTVAL_HIGH 0x00000001UL /**< Mode HIGH for ACMP_CTRL */
<> 150:02e0a0aed4ec 77 #define ACMP_CTRL_INACTVAL_DEFAULT (_ACMP_CTRL_INACTVAL_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_CTRL */
<> 150:02e0a0aed4ec 78 #define ACMP_CTRL_INACTVAL_LOW (_ACMP_CTRL_INACTVAL_LOW << 2) /**< Shifted mode LOW for ACMP_CTRL */
<> 150:02e0a0aed4ec 79 #define ACMP_CTRL_INACTVAL_HIGH (_ACMP_CTRL_INACTVAL_HIGH << 2) /**< Shifted mode HIGH for ACMP_CTRL */
<> 150:02e0a0aed4ec 80 #define ACMP_CTRL_GPIOINV (0x1UL << 3) /**< Comparator GPIO Output Invert */
<> 150:02e0a0aed4ec 81 #define _ACMP_CTRL_GPIOINV_SHIFT 3 /**< Shift value for ACMP_GPIOINV */
<> 150:02e0a0aed4ec 82 #define _ACMP_CTRL_GPIOINV_MASK 0x8UL /**< Bit mask for ACMP_GPIOINV */
<> 150:02e0a0aed4ec 83 #define _ACMP_CTRL_GPIOINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
<> 150:02e0a0aed4ec 84 #define _ACMP_CTRL_GPIOINV_NOTINV 0x00000000UL /**< Mode NOTINV for ACMP_CTRL */
<> 150:02e0a0aed4ec 85 #define _ACMP_CTRL_GPIOINV_INV 0x00000001UL /**< Mode INV for ACMP_CTRL */
<> 150:02e0a0aed4ec 86 #define ACMP_CTRL_GPIOINV_DEFAULT (_ACMP_CTRL_GPIOINV_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_CTRL */
<> 150:02e0a0aed4ec 87 #define ACMP_CTRL_GPIOINV_NOTINV (_ACMP_CTRL_GPIOINV_NOTINV << 3) /**< Shifted mode NOTINV for ACMP_CTRL */
<> 150:02e0a0aed4ec 88 #define ACMP_CTRL_GPIOINV_INV (_ACMP_CTRL_GPIOINV_INV << 3) /**< Shifted mode INV for ACMP_CTRL */
<> 150:02e0a0aed4ec 89 #define _ACMP_CTRL_HYSTSEL_SHIFT 4 /**< Shift value for ACMP_HYSTSEL */
<> 150:02e0a0aed4ec 90 #define _ACMP_CTRL_HYSTSEL_MASK 0x70UL /**< Bit mask for ACMP_HYSTSEL */
<> 150:02e0a0aed4ec 91 #define _ACMP_CTRL_HYSTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
<> 150:02e0a0aed4ec 92 #define _ACMP_CTRL_HYSTSEL_HYST0 0x00000000UL /**< Mode HYST0 for ACMP_CTRL */
<> 150:02e0a0aed4ec 93 #define _ACMP_CTRL_HYSTSEL_HYST1 0x00000001UL /**< Mode HYST1 for ACMP_CTRL */
<> 150:02e0a0aed4ec 94 #define _ACMP_CTRL_HYSTSEL_HYST2 0x00000002UL /**< Mode HYST2 for ACMP_CTRL */
<> 150:02e0a0aed4ec 95 #define _ACMP_CTRL_HYSTSEL_HYST3 0x00000003UL /**< Mode HYST3 for ACMP_CTRL */
<> 150:02e0a0aed4ec 96 #define _ACMP_CTRL_HYSTSEL_HYST4 0x00000004UL /**< Mode HYST4 for ACMP_CTRL */
<> 150:02e0a0aed4ec 97 #define _ACMP_CTRL_HYSTSEL_HYST5 0x00000005UL /**< Mode HYST5 for ACMP_CTRL */
<> 150:02e0a0aed4ec 98 #define _ACMP_CTRL_HYSTSEL_HYST6 0x00000006UL /**< Mode HYST6 for ACMP_CTRL */
<> 150:02e0a0aed4ec 99 #define _ACMP_CTRL_HYSTSEL_HYST7 0x00000007UL /**< Mode HYST7 for ACMP_CTRL */
<> 150:02e0a0aed4ec 100 #define ACMP_CTRL_HYSTSEL_DEFAULT (_ACMP_CTRL_HYSTSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_CTRL */
<> 150:02e0a0aed4ec 101 #define ACMP_CTRL_HYSTSEL_HYST0 (_ACMP_CTRL_HYSTSEL_HYST0 << 4) /**< Shifted mode HYST0 for ACMP_CTRL */
<> 150:02e0a0aed4ec 102 #define ACMP_CTRL_HYSTSEL_HYST1 (_ACMP_CTRL_HYSTSEL_HYST1 << 4) /**< Shifted mode HYST1 for ACMP_CTRL */
<> 150:02e0a0aed4ec 103 #define ACMP_CTRL_HYSTSEL_HYST2 (_ACMP_CTRL_HYSTSEL_HYST2 << 4) /**< Shifted mode HYST2 for ACMP_CTRL */
<> 150:02e0a0aed4ec 104 #define ACMP_CTRL_HYSTSEL_HYST3 (_ACMP_CTRL_HYSTSEL_HYST3 << 4) /**< Shifted mode HYST3 for ACMP_CTRL */
<> 150:02e0a0aed4ec 105 #define ACMP_CTRL_HYSTSEL_HYST4 (_ACMP_CTRL_HYSTSEL_HYST4 << 4) /**< Shifted mode HYST4 for ACMP_CTRL */
<> 150:02e0a0aed4ec 106 #define ACMP_CTRL_HYSTSEL_HYST5 (_ACMP_CTRL_HYSTSEL_HYST5 << 4) /**< Shifted mode HYST5 for ACMP_CTRL */
<> 150:02e0a0aed4ec 107 #define ACMP_CTRL_HYSTSEL_HYST6 (_ACMP_CTRL_HYSTSEL_HYST6 << 4) /**< Shifted mode HYST6 for ACMP_CTRL */
<> 150:02e0a0aed4ec 108 #define ACMP_CTRL_HYSTSEL_HYST7 (_ACMP_CTRL_HYSTSEL_HYST7 << 4) /**< Shifted mode HYST7 for ACMP_CTRL */
<> 150:02e0a0aed4ec 109 #define _ACMP_CTRL_WARMTIME_SHIFT 8 /**< Shift value for ACMP_WARMTIME */
<> 150:02e0a0aed4ec 110 #define _ACMP_CTRL_WARMTIME_MASK 0x700UL /**< Bit mask for ACMP_WARMTIME */
<> 150:02e0a0aed4ec 111 #define _ACMP_CTRL_WARMTIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
<> 150:02e0a0aed4ec 112 #define _ACMP_CTRL_WARMTIME_4CYCLES 0x00000000UL /**< Mode 4CYCLES for ACMP_CTRL */
<> 150:02e0a0aed4ec 113 #define _ACMP_CTRL_WARMTIME_8CYCLES 0x00000001UL /**< Mode 8CYCLES for ACMP_CTRL */
<> 150:02e0a0aed4ec 114 #define _ACMP_CTRL_WARMTIME_16CYCLES 0x00000002UL /**< Mode 16CYCLES for ACMP_CTRL */
<> 150:02e0a0aed4ec 115 #define _ACMP_CTRL_WARMTIME_32CYCLES 0x00000003UL /**< Mode 32CYCLES for ACMP_CTRL */
<> 150:02e0a0aed4ec 116 #define _ACMP_CTRL_WARMTIME_64CYCLES 0x00000004UL /**< Mode 64CYCLES for ACMP_CTRL */
<> 150:02e0a0aed4ec 117 #define _ACMP_CTRL_WARMTIME_128CYCLES 0x00000005UL /**< Mode 128CYCLES for ACMP_CTRL */
<> 150:02e0a0aed4ec 118 #define _ACMP_CTRL_WARMTIME_256CYCLES 0x00000006UL /**< Mode 256CYCLES for ACMP_CTRL */
<> 150:02e0a0aed4ec 119 #define _ACMP_CTRL_WARMTIME_512CYCLES 0x00000007UL /**< Mode 512CYCLES for ACMP_CTRL */
<> 150:02e0a0aed4ec 120 #define ACMP_CTRL_WARMTIME_DEFAULT (_ACMP_CTRL_WARMTIME_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_CTRL */
<> 150:02e0a0aed4ec 121 #define ACMP_CTRL_WARMTIME_4CYCLES (_ACMP_CTRL_WARMTIME_4CYCLES << 8) /**< Shifted mode 4CYCLES for ACMP_CTRL */
<> 150:02e0a0aed4ec 122 #define ACMP_CTRL_WARMTIME_8CYCLES (_ACMP_CTRL_WARMTIME_8CYCLES << 8) /**< Shifted mode 8CYCLES for ACMP_CTRL */
<> 150:02e0a0aed4ec 123 #define ACMP_CTRL_WARMTIME_16CYCLES (_ACMP_CTRL_WARMTIME_16CYCLES << 8) /**< Shifted mode 16CYCLES for ACMP_CTRL */
<> 150:02e0a0aed4ec 124 #define ACMP_CTRL_WARMTIME_32CYCLES (_ACMP_CTRL_WARMTIME_32CYCLES << 8) /**< Shifted mode 32CYCLES for ACMP_CTRL */
<> 150:02e0a0aed4ec 125 #define ACMP_CTRL_WARMTIME_64CYCLES (_ACMP_CTRL_WARMTIME_64CYCLES << 8) /**< Shifted mode 64CYCLES for ACMP_CTRL */
<> 150:02e0a0aed4ec 126 #define ACMP_CTRL_WARMTIME_128CYCLES (_ACMP_CTRL_WARMTIME_128CYCLES << 8) /**< Shifted mode 128CYCLES for ACMP_CTRL */
<> 150:02e0a0aed4ec 127 #define ACMP_CTRL_WARMTIME_256CYCLES (_ACMP_CTRL_WARMTIME_256CYCLES << 8) /**< Shifted mode 256CYCLES for ACMP_CTRL */
<> 150:02e0a0aed4ec 128 #define ACMP_CTRL_WARMTIME_512CYCLES (_ACMP_CTRL_WARMTIME_512CYCLES << 8) /**< Shifted mode 512CYCLES for ACMP_CTRL */
<> 150:02e0a0aed4ec 129 #define ACMP_CTRL_IRISE (0x1UL << 16) /**< Rising Edge Interrupt Sense */
<> 150:02e0a0aed4ec 130 #define _ACMP_CTRL_IRISE_SHIFT 16 /**< Shift value for ACMP_IRISE */
<> 150:02e0a0aed4ec 131 #define _ACMP_CTRL_IRISE_MASK 0x10000UL /**< Bit mask for ACMP_IRISE */
<> 150:02e0a0aed4ec 132 #define _ACMP_CTRL_IRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
<> 150:02e0a0aed4ec 133 #define _ACMP_CTRL_IRISE_DISABLED 0x00000000UL /**< Mode DISABLED for ACMP_CTRL */
<> 150:02e0a0aed4ec 134 #define _ACMP_CTRL_IRISE_ENABLED 0x00000001UL /**< Mode ENABLED for ACMP_CTRL */
<> 150:02e0a0aed4ec 135 #define ACMP_CTRL_IRISE_DEFAULT (_ACMP_CTRL_IRISE_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_CTRL */
<> 150:02e0a0aed4ec 136 #define ACMP_CTRL_IRISE_DISABLED (_ACMP_CTRL_IRISE_DISABLED << 16) /**< Shifted mode DISABLED for ACMP_CTRL */
<> 150:02e0a0aed4ec 137 #define ACMP_CTRL_IRISE_ENABLED (_ACMP_CTRL_IRISE_ENABLED << 16) /**< Shifted mode ENABLED for ACMP_CTRL */
<> 150:02e0a0aed4ec 138 #define ACMP_CTRL_IFALL (0x1UL << 17) /**< Falling Edge Interrupt Sense */
<> 150:02e0a0aed4ec 139 #define _ACMP_CTRL_IFALL_SHIFT 17 /**< Shift value for ACMP_IFALL */
<> 150:02e0a0aed4ec 140 #define _ACMP_CTRL_IFALL_MASK 0x20000UL /**< Bit mask for ACMP_IFALL */
<> 150:02e0a0aed4ec 141 #define _ACMP_CTRL_IFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
<> 150:02e0a0aed4ec 142 #define _ACMP_CTRL_IFALL_DISABLED 0x00000000UL /**< Mode DISABLED for ACMP_CTRL */
<> 150:02e0a0aed4ec 143 #define _ACMP_CTRL_IFALL_ENABLED 0x00000001UL /**< Mode ENABLED for ACMP_CTRL */
<> 150:02e0a0aed4ec 144 #define ACMP_CTRL_IFALL_DEFAULT (_ACMP_CTRL_IFALL_DEFAULT << 17) /**< Shifted mode DEFAULT for ACMP_CTRL */
<> 150:02e0a0aed4ec 145 #define ACMP_CTRL_IFALL_DISABLED (_ACMP_CTRL_IFALL_DISABLED << 17) /**< Shifted mode DISABLED for ACMP_CTRL */
<> 150:02e0a0aed4ec 146 #define ACMP_CTRL_IFALL_ENABLED (_ACMP_CTRL_IFALL_ENABLED << 17) /**< Shifted mode ENABLED for ACMP_CTRL */
<> 150:02e0a0aed4ec 147 #define _ACMP_CTRL_BIASPROG_SHIFT 24 /**< Shift value for ACMP_BIASPROG */
<> 150:02e0a0aed4ec 148 #define _ACMP_CTRL_BIASPROG_MASK 0xF000000UL /**< Bit mask for ACMP_BIASPROG */
<> 150:02e0a0aed4ec 149 #define _ACMP_CTRL_BIASPROG_DEFAULT 0x00000007UL /**< Mode DEFAULT for ACMP_CTRL */
<> 150:02e0a0aed4ec 150 #define ACMP_CTRL_BIASPROG_DEFAULT (_ACMP_CTRL_BIASPROG_DEFAULT << 24) /**< Shifted mode DEFAULT for ACMP_CTRL */
<> 150:02e0a0aed4ec 151 #define ACMP_CTRL_HALFBIAS (0x1UL << 30) /**< Half Bias Current */
<> 150:02e0a0aed4ec 152 #define _ACMP_CTRL_HALFBIAS_SHIFT 30 /**< Shift value for ACMP_HALFBIAS */
<> 150:02e0a0aed4ec 153 #define _ACMP_CTRL_HALFBIAS_MASK 0x40000000UL /**< Bit mask for ACMP_HALFBIAS */
<> 150:02e0a0aed4ec 154 #define _ACMP_CTRL_HALFBIAS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ACMP_CTRL */
<> 150:02e0a0aed4ec 155 #define ACMP_CTRL_HALFBIAS_DEFAULT (_ACMP_CTRL_HALFBIAS_DEFAULT << 30) /**< Shifted mode DEFAULT for ACMP_CTRL */
<> 150:02e0a0aed4ec 156 #define ACMP_CTRL_FULLBIAS (0x1UL << 31) /**< Full Bias Current */
<> 150:02e0a0aed4ec 157 #define _ACMP_CTRL_FULLBIAS_SHIFT 31 /**< Shift value for ACMP_FULLBIAS */
<> 150:02e0a0aed4ec 158 #define _ACMP_CTRL_FULLBIAS_MASK 0x80000000UL /**< Bit mask for ACMP_FULLBIAS */
<> 150:02e0a0aed4ec 159 #define _ACMP_CTRL_FULLBIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
<> 150:02e0a0aed4ec 160 #define ACMP_CTRL_FULLBIAS_DEFAULT (_ACMP_CTRL_FULLBIAS_DEFAULT << 31) /**< Shifted mode DEFAULT for ACMP_CTRL */
<> 150:02e0a0aed4ec 161
<> 150:02e0a0aed4ec 162 /* Bit fields for ACMP INPUTSEL */
<> 150:02e0a0aed4ec 163 #define _ACMP_INPUTSEL_RESETVALUE 0x00010080UL /**< Default value for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 164 #define _ACMP_INPUTSEL_MASK 0x31013FF7UL /**< Mask for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 165 #define _ACMP_INPUTSEL_POSSEL_SHIFT 0 /**< Shift value for ACMP_POSSEL */
<> 150:02e0a0aed4ec 166 #define _ACMP_INPUTSEL_POSSEL_MASK 0x7UL /**< Bit mask for ACMP_POSSEL */
<> 150:02e0a0aed4ec 167 #define _ACMP_INPUTSEL_POSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 168 #define _ACMP_INPUTSEL_POSSEL_CH0 0x00000000UL /**< Mode CH0 for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 169 #define _ACMP_INPUTSEL_POSSEL_CH1 0x00000001UL /**< Mode CH1 for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 170 #define _ACMP_INPUTSEL_POSSEL_CH2 0x00000002UL /**< Mode CH2 for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 171 #define _ACMP_INPUTSEL_POSSEL_CH3 0x00000003UL /**< Mode CH3 for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 172 #define _ACMP_INPUTSEL_POSSEL_CH4 0x00000004UL /**< Mode CH4 for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 173 #define _ACMP_INPUTSEL_POSSEL_CH5 0x00000005UL /**< Mode CH5 for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 174 #define _ACMP_INPUTSEL_POSSEL_CH6 0x00000006UL /**< Mode CH6 for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 175 #define _ACMP_INPUTSEL_POSSEL_CH7 0x00000007UL /**< Mode CH7 for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 176 #define ACMP_INPUTSEL_POSSEL_DEFAULT (_ACMP_INPUTSEL_POSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 177 #define ACMP_INPUTSEL_POSSEL_CH0 (_ACMP_INPUTSEL_POSSEL_CH0 << 0) /**< Shifted mode CH0 for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 178 #define ACMP_INPUTSEL_POSSEL_CH1 (_ACMP_INPUTSEL_POSSEL_CH1 << 0) /**< Shifted mode CH1 for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 179 #define ACMP_INPUTSEL_POSSEL_CH2 (_ACMP_INPUTSEL_POSSEL_CH2 << 0) /**< Shifted mode CH2 for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 180 #define ACMP_INPUTSEL_POSSEL_CH3 (_ACMP_INPUTSEL_POSSEL_CH3 << 0) /**< Shifted mode CH3 for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 181 #define ACMP_INPUTSEL_POSSEL_CH4 (_ACMP_INPUTSEL_POSSEL_CH4 << 0) /**< Shifted mode CH4 for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 182 #define ACMP_INPUTSEL_POSSEL_CH5 (_ACMP_INPUTSEL_POSSEL_CH5 << 0) /**< Shifted mode CH5 for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 183 #define ACMP_INPUTSEL_POSSEL_CH6 (_ACMP_INPUTSEL_POSSEL_CH6 << 0) /**< Shifted mode CH6 for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 184 #define ACMP_INPUTSEL_POSSEL_CH7 (_ACMP_INPUTSEL_POSSEL_CH7 << 0) /**< Shifted mode CH7 for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 185 #define _ACMP_INPUTSEL_NEGSEL_SHIFT 4 /**< Shift value for ACMP_NEGSEL */
<> 150:02e0a0aed4ec 186 #define _ACMP_INPUTSEL_NEGSEL_MASK 0xF0UL /**< Bit mask for ACMP_NEGSEL */
<> 150:02e0a0aed4ec 187 #define _ACMP_INPUTSEL_NEGSEL_CH0 0x00000000UL /**< Mode CH0 for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 188 #define _ACMP_INPUTSEL_NEGSEL_CH1 0x00000001UL /**< Mode CH1 for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 189 #define _ACMP_INPUTSEL_NEGSEL_CH2 0x00000002UL /**< Mode CH2 for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 190 #define _ACMP_INPUTSEL_NEGSEL_CH3 0x00000003UL /**< Mode CH3 for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 191 #define _ACMP_INPUTSEL_NEGSEL_CH4 0x00000004UL /**< Mode CH4 for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 192 #define _ACMP_INPUTSEL_NEGSEL_CH5 0x00000005UL /**< Mode CH5 for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 193 #define _ACMP_INPUTSEL_NEGSEL_CH6 0x00000006UL /**< Mode CH6 for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 194 #define _ACMP_INPUTSEL_NEGSEL_CH7 0x00000007UL /**< Mode CH7 for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 195 #define _ACMP_INPUTSEL_NEGSEL_DEFAULT 0x00000008UL /**< Mode DEFAULT for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 196 #define _ACMP_INPUTSEL_NEGSEL_1V25 0x00000008UL /**< Mode 1V25 for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 197 #define _ACMP_INPUTSEL_NEGSEL_2V5 0x00000009UL /**< Mode 2V5 for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 198 #define _ACMP_INPUTSEL_NEGSEL_VDD 0x0000000AUL /**< Mode VDD for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 199 #define _ACMP_INPUTSEL_NEGSEL_CAPSENSE 0x0000000BUL /**< Mode CAPSENSE for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 200 #define _ACMP_INPUTSEL_NEGSEL_DAC0CH0 0x0000000CUL /**< Mode DAC0CH0 for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 201 #define _ACMP_INPUTSEL_NEGSEL_DAC0CH1 0x0000000DUL /**< Mode DAC0CH1 for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 202 #define ACMP_INPUTSEL_NEGSEL_CH0 (_ACMP_INPUTSEL_NEGSEL_CH0 << 4) /**< Shifted mode CH0 for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 203 #define ACMP_INPUTSEL_NEGSEL_CH1 (_ACMP_INPUTSEL_NEGSEL_CH1 << 4) /**< Shifted mode CH1 for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 204 #define ACMP_INPUTSEL_NEGSEL_CH2 (_ACMP_INPUTSEL_NEGSEL_CH2 << 4) /**< Shifted mode CH2 for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 205 #define ACMP_INPUTSEL_NEGSEL_CH3 (_ACMP_INPUTSEL_NEGSEL_CH3 << 4) /**< Shifted mode CH3 for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 206 #define ACMP_INPUTSEL_NEGSEL_CH4 (_ACMP_INPUTSEL_NEGSEL_CH4 << 4) /**< Shifted mode CH4 for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 207 #define ACMP_INPUTSEL_NEGSEL_CH5 (_ACMP_INPUTSEL_NEGSEL_CH5 << 4) /**< Shifted mode CH5 for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 208 #define ACMP_INPUTSEL_NEGSEL_CH6 (_ACMP_INPUTSEL_NEGSEL_CH6 << 4) /**< Shifted mode CH6 for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 209 #define ACMP_INPUTSEL_NEGSEL_CH7 (_ACMP_INPUTSEL_NEGSEL_CH7 << 4) /**< Shifted mode CH7 for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 210 #define ACMP_INPUTSEL_NEGSEL_DEFAULT (_ACMP_INPUTSEL_NEGSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 211 #define ACMP_INPUTSEL_NEGSEL_1V25 (_ACMP_INPUTSEL_NEGSEL_1V25 << 4) /**< Shifted mode 1V25 for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 212 #define ACMP_INPUTSEL_NEGSEL_2V5 (_ACMP_INPUTSEL_NEGSEL_2V5 << 4) /**< Shifted mode 2V5 for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 213 #define ACMP_INPUTSEL_NEGSEL_VDD (_ACMP_INPUTSEL_NEGSEL_VDD << 4) /**< Shifted mode VDD for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 214 #define ACMP_INPUTSEL_NEGSEL_CAPSENSE (_ACMP_INPUTSEL_NEGSEL_CAPSENSE << 4) /**< Shifted mode CAPSENSE for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 215 #define ACMP_INPUTSEL_NEGSEL_DAC0CH0 (_ACMP_INPUTSEL_NEGSEL_DAC0CH0 << 4) /**< Shifted mode DAC0CH0 for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 216 #define ACMP_INPUTSEL_NEGSEL_DAC0CH1 (_ACMP_INPUTSEL_NEGSEL_DAC0CH1 << 4) /**< Shifted mode DAC0CH1 for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 217 #define _ACMP_INPUTSEL_VDDLEVEL_SHIFT 8 /**< Shift value for ACMP_VDDLEVEL */
<> 150:02e0a0aed4ec 218 #define _ACMP_INPUTSEL_VDDLEVEL_MASK 0x3F00UL /**< Bit mask for ACMP_VDDLEVEL */
<> 150:02e0a0aed4ec 219 #define _ACMP_INPUTSEL_VDDLEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 220 #define ACMP_INPUTSEL_VDDLEVEL_DEFAULT (_ACMP_INPUTSEL_VDDLEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 221 #define ACMP_INPUTSEL_LPREF (0x1UL << 16) /**< Low Power Reference Mode */
<> 150:02e0a0aed4ec 222 #define _ACMP_INPUTSEL_LPREF_SHIFT 16 /**< Shift value for ACMP_LPREF */
<> 150:02e0a0aed4ec 223 #define _ACMP_INPUTSEL_LPREF_MASK 0x10000UL /**< Bit mask for ACMP_LPREF */
<> 150:02e0a0aed4ec 224 #define _ACMP_INPUTSEL_LPREF_DEFAULT 0x00000001UL /**< Mode DEFAULT for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 225 #define ACMP_INPUTSEL_LPREF_DEFAULT (_ACMP_INPUTSEL_LPREF_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 226 #define ACMP_INPUTSEL_CSRESEN (0x1UL << 24) /**< Capacitive Sense Mode Internal Resistor Enable */
<> 150:02e0a0aed4ec 227 #define _ACMP_INPUTSEL_CSRESEN_SHIFT 24 /**< Shift value for ACMP_CSRESEN */
<> 150:02e0a0aed4ec 228 #define _ACMP_INPUTSEL_CSRESEN_MASK 0x1000000UL /**< Bit mask for ACMP_CSRESEN */
<> 150:02e0a0aed4ec 229 #define _ACMP_INPUTSEL_CSRESEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 230 #define ACMP_INPUTSEL_CSRESEN_DEFAULT (_ACMP_INPUTSEL_CSRESEN_DEFAULT << 24) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 231 #define _ACMP_INPUTSEL_CSRESSEL_SHIFT 28 /**< Shift value for ACMP_CSRESSEL */
<> 150:02e0a0aed4ec 232 #define _ACMP_INPUTSEL_CSRESSEL_MASK 0x30000000UL /**< Bit mask for ACMP_CSRESSEL */
<> 150:02e0a0aed4ec 233 #define _ACMP_INPUTSEL_CSRESSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 234 #define _ACMP_INPUTSEL_CSRESSEL_RES0 0x00000000UL /**< Mode RES0 for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 235 #define _ACMP_INPUTSEL_CSRESSEL_RES1 0x00000001UL /**< Mode RES1 for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 236 #define _ACMP_INPUTSEL_CSRESSEL_RES2 0x00000002UL /**< Mode RES2 for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 237 #define _ACMP_INPUTSEL_CSRESSEL_RES3 0x00000003UL /**< Mode RES3 for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 238 #define ACMP_INPUTSEL_CSRESSEL_DEFAULT (_ACMP_INPUTSEL_CSRESSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 239 #define ACMP_INPUTSEL_CSRESSEL_RES0 (_ACMP_INPUTSEL_CSRESSEL_RES0 << 28) /**< Shifted mode RES0 for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 240 #define ACMP_INPUTSEL_CSRESSEL_RES1 (_ACMP_INPUTSEL_CSRESSEL_RES1 << 28) /**< Shifted mode RES1 for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 241 #define ACMP_INPUTSEL_CSRESSEL_RES2 (_ACMP_INPUTSEL_CSRESSEL_RES2 << 28) /**< Shifted mode RES2 for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 242 #define ACMP_INPUTSEL_CSRESSEL_RES3 (_ACMP_INPUTSEL_CSRESSEL_RES3 << 28) /**< Shifted mode RES3 for ACMP_INPUTSEL */
<> 150:02e0a0aed4ec 243
<> 150:02e0a0aed4ec 244 /* Bit fields for ACMP STATUS */
<> 150:02e0a0aed4ec 245 #define _ACMP_STATUS_RESETVALUE 0x00000000UL /**< Default value for ACMP_STATUS */
<> 150:02e0a0aed4ec 246 #define _ACMP_STATUS_MASK 0x00000003UL /**< Mask for ACMP_STATUS */
<> 150:02e0a0aed4ec 247 #define ACMP_STATUS_ACMPACT (0x1UL << 0) /**< Analog Comparator Active */
<> 150:02e0a0aed4ec 248 #define _ACMP_STATUS_ACMPACT_SHIFT 0 /**< Shift value for ACMP_ACMPACT */
<> 150:02e0a0aed4ec 249 #define _ACMP_STATUS_ACMPACT_MASK 0x1UL /**< Bit mask for ACMP_ACMPACT */
<> 150:02e0a0aed4ec 250 #define _ACMP_STATUS_ACMPACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */
<> 150:02e0a0aed4ec 251 #define ACMP_STATUS_ACMPACT_DEFAULT (_ACMP_STATUS_ACMPACT_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_STATUS */
<> 150:02e0a0aed4ec 252 #define ACMP_STATUS_ACMPOUT (0x1UL << 1) /**< Analog Comparator Output */
<> 150:02e0a0aed4ec 253 #define _ACMP_STATUS_ACMPOUT_SHIFT 1 /**< Shift value for ACMP_ACMPOUT */
<> 150:02e0a0aed4ec 254 #define _ACMP_STATUS_ACMPOUT_MASK 0x2UL /**< Bit mask for ACMP_ACMPOUT */
<> 150:02e0a0aed4ec 255 #define _ACMP_STATUS_ACMPOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */
<> 150:02e0a0aed4ec 256 #define ACMP_STATUS_ACMPOUT_DEFAULT (_ACMP_STATUS_ACMPOUT_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_STATUS */
<> 150:02e0a0aed4ec 257
<> 150:02e0a0aed4ec 258 /* Bit fields for ACMP IEN */
<> 150:02e0a0aed4ec 259 #define _ACMP_IEN_RESETVALUE 0x00000000UL /**< Default value for ACMP_IEN */
<> 150:02e0a0aed4ec 260 #define _ACMP_IEN_MASK 0x00000003UL /**< Mask for ACMP_IEN */
<> 150:02e0a0aed4ec 261 #define ACMP_IEN_EDGE (0x1UL << 0) /**< Edge Trigger Interrupt Enable */
<> 150:02e0a0aed4ec 262 #define _ACMP_IEN_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */
<> 150:02e0a0aed4ec 263 #define _ACMP_IEN_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */
<> 150:02e0a0aed4ec 264 #define _ACMP_IEN_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */
<> 150:02e0a0aed4ec 265 #define ACMP_IEN_EDGE_DEFAULT (_ACMP_IEN_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IEN */
<> 150:02e0a0aed4ec 266 #define ACMP_IEN_WARMUP (0x1UL << 1) /**< Warm-up Interrupt Enable */
<> 150:02e0a0aed4ec 267 #define _ACMP_IEN_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */
<> 150:02e0a0aed4ec 268 #define _ACMP_IEN_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */
<> 150:02e0a0aed4ec 269 #define _ACMP_IEN_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */
<> 150:02e0a0aed4ec 270 #define ACMP_IEN_WARMUP_DEFAULT (_ACMP_IEN_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IEN */
<> 150:02e0a0aed4ec 271
<> 150:02e0a0aed4ec 272 /* Bit fields for ACMP IF */
<> 150:02e0a0aed4ec 273 #define _ACMP_IF_RESETVALUE 0x00000000UL /**< Default value for ACMP_IF */
<> 150:02e0a0aed4ec 274 #define _ACMP_IF_MASK 0x00000003UL /**< Mask for ACMP_IF */
<> 150:02e0a0aed4ec 275 #define ACMP_IF_EDGE (0x1UL << 0) /**< Edge Triggered Interrupt Flag */
<> 150:02e0a0aed4ec 276 #define _ACMP_IF_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */
<> 150:02e0a0aed4ec 277 #define _ACMP_IF_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */
<> 150:02e0a0aed4ec 278 #define _ACMP_IF_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */
<> 150:02e0a0aed4ec 279 #define ACMP_IF_EDGE_DEFAULT (_ACMP_IF_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IF */
<> 150:02e0a0aed4ec 280 #define ACMP_IF_WARMUP (0x1UL << 1) /**< Warm-up Interrupt Flag */
<> 150:02e0a0aed4ec 281 #define _ACMP_IF_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */
<> 150:02e0a0aed4ec 282 #define _ACMP_IF_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */
<> 150:02e0a0aed4ec 283 #define _ACMP_IF_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */
<> 150:02e0a0aed4ec 284 #define ACMP_IF_WARMUP_DEFAULT (_ACMP_IF_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IF */
<> 150:02e0a0aed4ec 285
<> 150:02e0a0aed4ec 286 /* Bit fields for ACMP IFS */
<> 150:02e0a0aed4ec 287 #define _ACMP_IFS_RESETVALUE 0x00000000UL /**< Default value for ACMP_IFS */
<> 150:02e0a0aed4ec 288 #define _ACMP_IFS_MASK 0x00000003UL /**< Mask for ACMP_IFS */
<> 150:02e0a0aed4ec 289 #define ACMP_IFS_EDGE (0x1UL << 0) /**< Edge Triggered Interrupt Flag Set */
<> 150:02e0a0aed4ec 290 #define _ACMP_IFS_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */
<> 150:02e0a0aed4ec 291 #define _ACMP_IFS_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */
<> 150:02e0a0aed4ec 292 #define _ACMP_IFS_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFS */
<> 150:02e0a0aed4ec 293 #define ACMP_IFS_EDGE_DEFAULT (_ACMP_IFS_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IFS */
<> 150:02e0a0aed4ec 294 #define ACMP_IFS_WARMUP (0x1UL << 1) /**< Warm-up Interrupt Flag Set */
<> 150:02e0a0aed4ec 295 #define _ACMP_IFS_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */
<> 150:02e0a0aed4ec 296 #define _ACMP_IFS_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */
<> 150:02e0a0aed4ec 297 #define _ACMP_IFS_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFS */
<> 150:02e0a0aed4ec 298 #define ACMP_IFS_WARMUP_DEFAULT (_ACMP_IFS_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IFS */
<> 150:02e0a0aed4ec 299
<> 150:02e0a0aed4ec 300 /* Bit fields for ACMP IFC */
<> 150:02e0a0aed4ec 301 #define _ACMP_IFC_RESETVALUE 0x00000000UL /**< Default value for ACMP_IFC */
<> 150:02e0a0aed4ec 302 #define _ACMP_IFC_MASK 0x00000003UL /**< Mask for ACMP_IFC */
<> 150:02e0a0aed4ec 303 #define ACMP_IFC_EDGE (0x1UL << 0) /**< Edge Triggered Interrupt Flag Clear */
<> 150:02e0a0aed4ec 304 #define _ACMP_IFC_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */
<> 150:02e0a0aed4ec 305 #define _ACMP_IFC_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */
<> 150:02e0a0aed4ec 306 #define _ACMP_IFC_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFC */
<> 150:02e0a0aed4ec 307 #define ACMP_IFC_EDGE_DEFAULT (_ACMP_IFC_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IFC */
<> 150:02e0a0aed4ec 308 #define ACMP_IFC_WARMUP (0x1UL << 1) /**< Warm-up Interrupt Flag Clear */
<> 150:02e0a0aed4ec 309 #define _ACMP_IFC_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */
<> 150:02e0a0aed4ec 310 #define _ACMP_IFC_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */
<> 150:02e0a0aed4ec 311 #define _ACMP_IFC_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFC */
<> 150:02e0a0aed4ec 312 #define ACMP_IFC_WARMUP_DEFAULT (_ACMP_IFC_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IFC */
<> 150:02e0a0aed4ec 313
<> 150:02e0a0aed4ec 314 /* Bit fields for ACMP ROUTE */
<> 150:02e0a0aed4ec 315 #define _ACMP_ROUTE_RESETVALUE 0x00000000UL /**< Default value for ACMP_ROUTE */
<> 150:02e0a0aed4ec 316 #define _ACMP_ROUTE_MASK 0x00000701UL /**< Mask for ACMP_ROUTE */
<> 150:02e0a0aed4ec 317 #define ACMP_ROUTE_ACMPPEN (0x1UL << 0) /**< ACMP Output Pin Enable */
<> 150:02e0a0aed4ec 318 #define _ACMP_ROUTE_ACMPPEN_SHIFT 0 /**< Shift value for ACMP_ACMPPEN */
<> 150:02e0a0aed4ec 319 #define _ACMP_ROUTE_ACMPPEN_MASK 0x1UL /**< Bit mask for ACMP_ACMPPEN */
<> 150:02e0a0aed4ec 320 #define _ACMP_ROUTE_ACMPPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_ROUTE */
<> 150:02e0a0aed4ec 321 #define ACMP_ROUTE_ACMPPEN_DEFAULT (_ACMP_ROUTE_ACMPPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_ROUTE */
<> 150:02e0a0aed4ec 322 #define _ACMP_ROUTE_LOCATION_SHIFT 8 /**< Shift value for ACMP_LOCATION */
<> 150:02e0a0aed4ec 323 #define _ACMP_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for ACMP_LOCATION */
<> 150:02e0a0aed4ec 324 #define _ACMP_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for ACMP_ROUTE */
<> 150:02e0a0aed4ec 325 #define _ACMP_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_ROUTE */
<> 150:02e0a0aed4ec 326 #define _ACMP_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for ACMP_ROUTE */
<> 150:02e0a0aed4ec 327 #define _ACMP_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for ACMP_ROUTE */
<> 150:02e0a0aed4ec 328 #define ACMP_ROUTE_LOCATION_LOC0 (_ACMP_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for ACMP_ROUTE */
<> 150:02e0a0aed4ec 329 #define ACMP_ROUTE_LOCATION_DEFAULT (_ACMP_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_ROUTE */
<> 150:02e0a0aed4ec 330 #define ACMP_ROUTE_LOCATION_LOC1 (_ACMP_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for ACMP_ROUTE */
<> 150:02e0a0aed4ec 331 #define ACMP_ROUTE_LOCATION_LOC2 (_ACMP_ROUTE_LOCATION_LOC2 << 8) /**< Shifted mode LOC2 for ACMP_ROUTE */
<> 150:02e0a0aed4ec 332
<> 150:02e0a0aed4ec 333 /** @} End of group EFM32WG_ACMP */
<> 150:02e0a0aed4ec 334 /** @} End of group Parts */
<> 150:02e0a0aed4ec 335