Fawwaz Nadzmy / mbed-STM

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targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg995f256.h@153:9398a535854b, 2016-12-22 (annotated)

Committer:
fwndz
Date:
Thu Dec 22 05:12:40 2016 +0000
Revision:
153:9398a535854b
Parent:
150:02e0a0aed4ec 
device target maximize

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 150:02e0a0aed4ec 1 /**************************************************************************//**
<> 150:02e0a0aed4ec 2 * @file efm32wg995f256.h
<> 150:02e0a0aed4ec 3 * @brief CMSIS Cortex-M Peripheral Access Layer Header File
<> 150:02e0a0aed4ec 4 * for EFM32WG995F256
<> 150:02e0a0aed4ec 5 * @version 5.0.0
<> 150:02e0a0aed4ec 6 ******************************************************************************
<> 150:02e0a0aed4ec 7 * @section License
<> 150:02e0a0aed4ec 8 * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 150:02e0a0aed4ec 9 ******************************************************************************
<> 150:02e0a0aed4ec 10 *
<> 150:02e0a0aed4ec 11 * Permission is granted to anyone to use this software for any purpose,
<> 150:02e0a0aed4ec 12 * including commercial applications, and to alter it and redistribute it
<> 150:02e0a0aed4ec 13 * freely, subject to the following restrictions:
<> 150:02e0a0aed4ec 14 *
<> 150:02e0a0aed4ec 15 * 1. The origin of this software must not be misrepresented; you must not
<> 150:02e0a0aed4ec 16 * claim that you wrote the original software.@n
<> 150:02e0a0aed4ec 17 * 2. Altered source versions must be plainly marked as such, and must not be
<> 150:02e0a0aed4ec 18 * misrepresented as being the original software.@n
<> 150:02e0a0aed4ec 19 * 3. This notice may not be removed or altered from any source distribution.
<> 150:02e0a0aed4ec 20 *
<> 150:02e0a0aed4ec 21 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 150:02e0a0aed4ec 22 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 150:02e0a0aed4ec 23 * providing the Software "AS IS", with no express or implied warranties of any
<> 150:02e0a0aed4ec 24 * kind, including, but not limited to, any implied warranties of
<> 150:02e0a0aed4ec 25 * merchantability or fitness for any particular purpose or warranties against
<> 150:02e0a0aed4ec 26 * infringement of any proprietary rights of a third party.
<> 150:02e0a0aed4ec 27 *
<> 150:02e0a0aed4ec 28 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 150:02e0a0aed4ec 29 * incidental, or special damages, or any other relief, or for any claim by
<> 150:02e0a0aed4ec 30 * any third party, arising from your use of this Software.
<> 150:02e0a0aed4ec 31 *
<> 150:02e0a0aed4ec 32 *****************************************************************************/
<> 150:02e0a0aed4ec 33
<> 150:02e0a0aed4ec 34 #ifndef EFM32WG995F256_H
<> 150:02e0a0aed4ec 35 #define EFM32WG995F256_H
<> 150:02e0a0aed4ec 36
<> 150:02e0a0aed4ec 37 #ifdef __cplusplus
<> 150:02e0a0aed4ec 38 extern "C" {
<> 150:02e0a0aed4ec 39 #endif
<> 150:02e0a0aed4ec 40
<> 150:02e0a0aed4ec 41 /**************************************************************************//**
<> 150:02e0a0aed4ec 42 * @addtogroup Parts
<> 150:02e0a0aed4ec 43 * @{
<> 150:02e0a0aed4ec 44 *****************************************************************************/
<> 150:02e0a0aed4ec 45
<> 150:02e0a0aed4ec 46 /**************************************************************************//**
<> 150:02e0a0aed4ec 47 * @defgroup EFM32WG995F256 EFM32WG995F256
<> 150:02e0a0aed4ec 48 * @{
<> 150:02e0a0aed4ec 49 *****************************************************************************/
<> 150:02e0a0aed4ec 50
<> 150:02e0a0aed4ec 51 /** Interrupt Number Definition */
<> 150:02e0a0aed4ec 52 typedef enum IRQn
<> 150:02e0a0aed4ec 53 {
<> 150:02e0a0aed4ec 54 /****** Cortex-M4 Processor Exceptions Numbers ********************************************/
<> 150:02e0a0aed4ec 55 NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */
<> 150:02e0a0aed4ec 56 HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */
<> 150:02e0a0aed4ec 57 MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */
<> 150:02e0a0aed4ec 58 BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */
<> 150:02e0a0aed4ec 59 UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */
<> 150:02e0a0aed4ec 60 SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */
<> 150:02e0a0aed4ec 61 DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */
<> 150:02e0a0aed4ec 62 PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */
<> 150:02e0a0aed4ec 63 SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */
<> 150:02e0a0aed4ec 64
<> 150:02e0a0aed4ec 65 /****** EFM32WG Peripheral Interrupt Numbers **********************************************/
<> 150:02e0a0aed4ec 66 DMA_IRQn = 0, /*!< 0 EFM32 DMA Interrupt */
<> 150:02e0a0aed4ec 67 GPIO_EVEN_IRQn = 1, /*!< 1 EFM32 GPIO_EVEN Interrupt */
<> 150:02e0a0aed4ec 68 TIMER0_IRQn = 2, /*!< 2 EFM32 TIMER0 Interrupt */
<> 150:02e0a0aed4ec 69 USART0_RX_IRQn = 3, /*!< 3 EFM32 USART0_RX Interrupt */
<> 150:02e0a0aed4ec 70 USART0_TX_IRQn = 4, /*!< 4 EFM32 USART0_TX Interrupt */
<> 150:02e0a0aed4ec 71 USB_IRQn = 5, /*!< 5 EFM32 USB Interrupt */
<> 150:02e0a0aed4ec 72 ACMP0_IRQn = 6, /*!< 6 EFM32 ACMP0 Interrupt */
<> 150:02e0a0aed4ec 73 ADC0_IRQn = 7, /*!< 7 EFM32 ADC0 Interrupt */
<> 150:02e0a0aed4ec 74 DAC0_IRQn = 8, /*!< 8 EFM32 DAC0 Interrupt */
<> 150:02e0a0aed4ec 75 I2C0_IRQn = 9, /*!< 9 EFM32 I2C0 Interrupt */
<> 150:02e0a0aed4ec 76 I2C1_IRQn = 10, /*!< 10 EFM32 I2C1 Interrupt */
<> 150:02e0a0aed4ec 77 GPIO_ODD_IRQn = 11, /*!< 11 EFM32 GPIO_ODD Interrupt */
<> 150:02e0a0aed4ec 78 TIMER1_IRQn = 12, /*!< 12 EFM32 TIMER1 Interrupt */
<> 150:02e0a0aed4ec 79 TIMER2_IRQn = 13, /*!< 13 EFM32 TIMER2 Interrupt */
<> 150:02e0a0aed4ec 80 TIMER3_IRQn = 14, /*!< 14 EFM32 TIMER3 Interrupt */
<> 150:02e0a0aed4ec 81 USART1_RX_IRQn = 15, /*!< 15 EFM32 USART1_RX Interrupt */
<> 150:02e0a0aed4ec 82 USART1_TX_IRQn = 16, /*!< 16 EFM32 USART1_TX Interrupt */
<> 150:02e0a0aed4ec 83 LESENSE_IRQn = 17, /*!< 17 EFM32 LESENSE Interrupt */
<> 150:02e0a0aed4ec 84 USART2_RX_IRQn = 18, /*!< 18 EFM32 USART2_RX Interrupt */
<> 150:02e0a0aed4ec 85 USART2_TX_IRQn = 19, /*!< 19 EFM32 USART2_TX Interrupt */
<> 150:02e0a0aed4ec 86 UART0_RX_IRQn = 20, /*!< 20 EFM32 UART0_RX Interrupt */
<> 150:02e0a0aed4ec 87 UART0_TX_IRQn = 21, /*!< 21 EFM32 UART0_TX Interrupt */
<> 150:02e0a0aed4ec 88 UART1_RX_IRQn = 22, /*!< 22 EFM32 UART1_RX Interrupt */
<> 150:02e0a0aed4ec 89 UART1_TX_IRQn = 23, /*!< 23 EFM32 UART1_TX Interrupt */
<> 150:02e0a0aed4ec 90 LEUART0_IRQn = 24, /*!< 24 EFM32 LEUART0 Interrupt */
<> 150:02e0a0aed4ec 91 LEUART1_IRQn = 25, /*!< 25 EFM32 LEUART1 Interrupt */
<> 150:02e0a0aed4ec 92 LETIMER0_IRQn = 26, /*!< 26 EFM32 LETIMER0 Interrupt */
<> 150:02e0a0aed4ec 93 PCNT0_IRQn = 27, /*!< 27 EFM32 PCNT0 Interrupt */
<> 150:02e0a0aed4ec 94 PCNT1_IRQn = 28, /*!< 28 EFM32 PCNT1 Interrupt */
<> 150:02e0a0aed4ec 95 PCNT2_IRQn = 29, /*!< 29 EFM32 PCNT2 Interrupt */
<> 150:02e0a0aed4ec 96 RTC_IRQn = 30, /*!< 30 EFM32 RTC Interrupt */
<> 150:02e0a0aed4ec 97 BURTC_IRQn = 31, /*!< 31 EFM32 BURTC Interrupt */
<> 150:02e0a0aed4ec 98 CMU_IRQn = 32, /*!< 32 EFM32 CMU Interrupt */
<> 150:02e0a0aed4ec 99 VCMP_IRQn = 33, /*!< 33 EFM32 VCMP Interrupt */
<> 150:02e0a0aed4ec 100 LCD_IRQn = 34, /*!< 34 EFM32 LCD Interrupt */
<> 150:02e0a0aed4ec 101 MSC_IRQn = 35, /*!< 35 EFM32 MSC Interrupt */
<> 150:02e0a0aed4ec 102 AES_IRQn = 36, /*!< 36 EFM32 AES Interrupt */
<> 150:02e0a0aed4ec 103 EBI_IRQn = 37, /*!< 37 EFM32 EBI Interrupt */
<> 150:02e0a0aed4ec 104 EMU_IRQn = 38, /*!< 38 EFM32 EMU Interrupt */
<> 150:02e0a0aed4ec 105 FPUEH_IRQn = 39, /*!< 39 EFM32 FPUEH Interrupt */
<> 150:02e0a0aed4ec 106 } IRQn_Type;
<> 150:02e0a0aed4ec 107
<> 150:02e0a0aed4ec 108 /**************************************************************************//**
<> 150:02e0a0aed4ec 109 * @defgroup EFM32WG995F256_Core EFM32WG995F256 Core
<> 150:02e0a0aed4ec 110 * @{
<> 150:02e0a0aed4ec 111 * @brief Processor and Core Peripheral Section
<> 150:02e0a0aed4ec 112 *****************************************************************************/
<> 150:02e0a0aed4ec 113 #define __MPU_PRESENT 1 /**< Presence of MPU */
<> 150:02e0a0aed4ec 114 #define __FPU_PRESENT 1 /**< Presence of FPU */
<> 150:02e0a0aed4ec 115 #define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
<> 150:02e0a0aed4ec 116 #define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
<> 150:02e0a0aed4ec 117 #define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
<> 150:02e0a0aed4ec 118
<> 150:02e0a0aed4ec 119 /** @} End of group EFM32WG995F256_Core */
<> 150:02e0a0aed4ec 120
<> 150:02e0a0aed4ec 121 /**************************************************************************//**
<> 150:02e0a0aed4ec 122 * @defgroup EFM32WG995F256_Part EFM32WG995F256 Part
<> 150:02e0a0aed4ec 123 * @{
<> 150:02e0a0aed4ec 124 ******************************************************************************/
<> 150:02e0a0aed4ec 125
<> 150:02e0a0aed4ec 126 /** Part family */
<> 150:02e0a0aed4ec 127 #define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */
<> 150:02e0a0aed4ec 128 #define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */
<> 150:02e0a0aed4ec 129 #define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */
<> 150:02e0a0aed4ec 130 #define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */
<> 150:02e0a0aed4ec 131 #define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */
<> 150:02e0a0aed4ec 132 #define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */
<> 150:02e0a0aed4ec 133
<> 150:02e0a0aed4ec 134 /* If part number is not defined as compiler option, define it */
<> 150:02e0a0aed4ec 135 #if !defined(EFM32WG995F256)
<> 150:02e0a0aed4ec 136 #define EFM32WG995F256 1 /**< Wonder Gecko Part */
<> 150:02e0a0aed4ec 137 #endif
<> 150:02e0a0aed4ec 138
<> 150:02e0a0aed4ec 139 /** Configure part number */
<> 150:02e0a0aed4ec 140 #define PART_NUMBER "EFM32WG995F256" /**< Part Number */
<> 150:02e0a0aed4ec 141
<> 150:02e0a0aed4ec 142 /** Memory Base addresses and limits */
<> 150:02e0a0aed4ec 143 #define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
<> 150:02e0a0aed4ec 144 #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
<> 150:02e0a0aed4ec 145 #define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
<> 150:02e0a0aed4ec 146 #define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
<> 150:02e0a0aed4ec 147 #define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
<> 150:02e0a0aed4ec 148 #define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
<> 150:02e0a0aed4ec 149 #define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
<> 150:02e0a0aed4ec 150 #define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
<> 150:02e0a0aed4ec 151 #define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */
<> 150:02e0a0aed4ec 152 #define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */
<> 150:02e0a0aed4ec 153 #define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */
<> 150:02e0a0aed4ec 154 #define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */
<> 150:02e0a0aed4ec 155 #define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */
<> 150:02e0a0aed4ec 156 #define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */
<> 150:02e0a0aed4ec 157 #define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */
<> 150:02e0a0aed4ec 158 #define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */
<> 150:02e0a0aed4ec 159 #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
<> 150:02e0a0aed4ec 160 #define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
<> 150:02e0a0aed4ec 161 #define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
<> 150:02e0a0aed4ec 162 #define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
<> 150:02e0a0aed4ec 163 #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
<> 150:02e0a0aed4ec 164 #define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */
<> 150:02e0a0aed4ec 165 #define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */
<> 150:02e0a0aed4ec 166 #define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */
<> 150:02e0a0aed4ec 167 #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
<> 150:02e0a0aed4ec 168 #define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */
<> 150:02e0a0aed4ec 169 #define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */
<> 150:02e0a0aed4ec 170 #define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */
<> 150:02e0a0aed4ec 171 #define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
<> 150:02e0a0aed4ec 172 #define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */
<> 150:02e0a0aed4ec 173 #define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */
<> 150:02e0a0aed4ec 174 #define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */
<> 150:02e0a0aed4ec 175
<> 150:02e0a0aed4ec 176 /** Bit banding area */
<> 150:02e0a0aed4ec 177 #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
<> 150:02e0a0aed4ec 178 #define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
<> 150:02e0a0aed4ec 179
<> 150:02e0a0aed4ec 180 /** Flash and SRAM limits for EFM32WG995F256 */
<> 150:02e0a0aed4ec 181 #define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
<> 150:02e0a0aed4ec 182 #define FLASH_SIZE (0x00040000UL) /**< Available Flash Memory */
<> 150:02e0a0aed4ec 183 #define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size */
<> 150:02e0a0aed4ec 184 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
<> 150:02e0a0aed4ec 185 #define SRAM_SIZE (0x00008000UL) /**< Available SRAM Memory */
<> 150:02e0a0aed4ec 186 #define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */
<> 150:02e0a0aed4ec 187 #define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
<> 150:02e0a0aed4ec 188 #define DMA_CHAN_COUNT 12 /**< Number of DMA channels */
<> 150:02e0a0aed4ec 189 #define EXT_IRQ_COUNT 40 /**< Number of External (NVIC) interrupts */
<> 150:02e0a0aed4ec 190
<> 150:02e0a0aed4ec 191 /** AF channels connect the different on-chip peripherals with the af-mux */
<> 150:02e0a0aed4ec 192 #define AFCHAN_MAX 163
<> 150:02e0a0aed4ec 193 #define AFCHANLOC_MAX 7
<> 150:02e0a0aed4ec 194 /** Analog AF channels */
<> 150:02e0a0aed4ec 195 #define AFACHAN_MAX 53
<> 150:02e0a0aed4ec 196
<> 150:02e0a0aed4ec 197 /* Part number capabilities */
<> 150:02e0a0aed4ec 198
<> 150:02e0a0aed4ec 199 #define USART_PRESENT /**< USART is available in this part */
<> 150:02e0a0aed4ec 200 #define USART_COUNT 3 /**< 3 USARTs available */
<> 150:02e0a0aed4ec 201 #define UART_PRESENT /**< UART is available in this part */
<> 150:02e0a0aed4ec 202 #define UART_COUNT 2 /**< 2 UARTs available */
<> 150:02e0a0aed4ec 203 #define TIMER_PRESENT /**< TIMER is available in this part */
<> 150:02e0a0aed4ec 204 #define TIMER_COUNT 4 /**< 4 TIMERs available */
<> 150:02e0a0aed4ec 205 #define ACMP_PRESENT /**< ACMP is available in this part */
<> 150:02e0a0aed4ec 206 #define ACMP_COUNT 2 /**< 2 ACMPs available */
<> 150:02e0a0aed4ec 207 #define LEUART_PRESENT /**< LEUART is available in this part */
<> 150:02e0a0aed4ec 208 #define LEUART_COUNT 2 /**< 2 LEUARTs available */
<> 150:02e0a0aed4ec 209 #define LETIMER_PRESENT /**< LETIMER is available in this part */
<> 150:02e0a0aed4ec 210 #define LETIMER_COUNT 1 /**< 1 LETIMERs available */
<> 150:02e0a0aed4ec 211 #define PCNT_PRESENT /**< PCNT is available in this part */
<> 150:02e0a0aed4ec 212 #define PCNT_COUNT 3 /**< 3 PCNTs available */
<> 150:02e0a0aed4ec 213 #define I2C_PRESENT /**< I2C is available in this part */
<> 150:02e0a0aed4ec 214 #define I2C_COUNT 2 /**< 2 I2Cs available */
<> 150:02e0a0aed4ec 215 #define ADC_PRESENT /**< ADC is available in this part */
<> 150:02e0a0aed4ec 216 #define ADC_COUNT 1 /**< 1 ADCs available */
<> 150:02e0a0aed4ec 217 #define DAC_PRESENT /**< DAC is available in this part */
<> 150:02e0a0aed4ec 218 #define DAC_COUNT 1 /**< 1 DACs available */
<> 150:02e0a0aed4ec 219 #define DMA_PRESENT
<> 150:02e0a0aed4ec 220 #define DMA_COUNT 1
<> 150:02e0a0aed4ec 221 #define AES_PRESENT
<> 150:02e0a0aed4ec 222 #define AES_COUNT 1
<> 150:02e0a0aed4ec 223 #define USBC_PRESENT
<> 150:02e0a0aed4ec 224 #define USBC_COUNT 1
<> 150:02e0a0aed4ec 225 #define USB_PRESENT
<> 150:02e0a0aed4ec 226 #define USB_COUNT 1
<> 150:02e0a0aed4ec 227 #define LE_PRESENT
<> 150:02e0a0aed4ec 228 #define LE_COUNT 1
<> 150:02e0a0aed4ec 229 #define MSC_PRESENT
<> 150:02e0a0aed4ec 230 #define MSC_COUNT 1
<> 150:02e0a0aed4ec 231 #define EMU_PRESENT
<> 150:02e0a0aed4ec 232 #define EMU_COUNT 1
<> 150:02e0a0aed4ec 233 #define RMU_PRESENT
<> 150:02e0a0aed4ec 234 #define RMU_COUNT 1
<> 150:02e0a0aed4ec 235 #define CMU_PRESENT
<> 150:02e0a0aed4ec 236 #define CMU_COUNT 1
<> 150:02e0a0aed4ec 237 #define LESENSE_PRESENT
<> 150:02e0a0aed4ec 238 #define LESENSE_COUNT 1
<> 150:02e0a0aed4ec 239 #define EBI_PRESENT
<> 150:02e0a0aed4ec 240 #define EBI_COUNT 1
<> 150:02e0a0aed4ec 241 #define FPUEH_PRESENT
<> 150:02e0a0aed4ec 242 #define FPUEH_COUNT 1
<> 150:02e0a0aed4ec 243 #define RTC_PRESENT
<> 150:02e0a0aed4ec 244 #define RTC_COUNT 1
<> 150:02e0a0aed4ec 245 #define GPIO_PRESENT
<> 150:02e0a0aed4ec 246 #define GPIO_COUNT 1
<> 150:02e0a0aed4ec 247 #define VCMP_PRESENT
<> 150:02e0a0aed4ec 248 #define VCMP_COUNT 1
<> 150:02e0a0aed4ec 249 #define PRS_PRESENT
<> 150:02e0a0aed4ec 250 #define PRS_COUNT 1
<> 150:02e0a0aed4ec 251 #define OPAMP_PRESENT
<> 150:02e0a0aed4ec 252 #define OPAMP_COUNT 1
<> 150:02e0a0aed4ec 253 #define BU_PRESENT
<> 150:02e0a0aed4ec 254 #define BU_COUNT 1
<> 150:02e0a0aed4ec 255 #define LCD_PRESENT
<> 150:02e0a0aed4ec 256 #define LCD_COUNT 1
<> 150:02e0a0aed4ec 257 #define BURTC_PRESENT
<> 150:02e0a0aed4ec 258 #define BURTC_COUNT 1
<> 150:02e0a0aed4ec 259 #define HFXTAL_PRESENT
<> 150:02e0a0aed4ec 260 #define HFXTAL_COUNT 1
<> 150:02e0a0aed4ec 261 #define LFXTAL_PRESENT
<> 150:02e0a0aed4ec 262 #define LFXTAL_COUNT 1
<> 150:02e0a0aed4ec 263 #define WDOG_PRESENT
<> 150:02e0a0aed4ec 264 #define WDOG_COUNT 1
<> 150:02e0a0aed4ec 265 #define DBG_PRESENT
<> 150:02e0a0aed4ec 266 #define DBG_COUNT 1
<> 150:02e0a0aed4ec 267 #define ETM_PRESENT
<> 150:02e0a0aed4ec 268 #define ETM_COUNT 1
<> 150:02e0a0aed4ec 269 #define BOOTLOADER_PRESENT
<> 150:02e0a0aed4ec 270 #define BOOTLOADER_COUNT 1
<> 150:02e0a0aed4ec 271 #define ANALOG_PRESENT
<> 150:02e0a0aed4ec 272 #define ANALOG_COUNT 1
<> 150:02e0a0aed4ec 273
<> 150:02e0a0aed4ec 274 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
<> 150:02e0a0aed4ec 275 #include "system_efm32wg.h" /* System Header */
<> 150:02e0a0aed4ec 276
<> 150:02e0a0aed4ec 277 /** @} End of group EFM32WG995F256_Part */
<> 150:02e0a0aed4ec 278
<> 150:02e0a0aed4ec 279 /**************************************************************************//**
<> 150:02e0a0aed4ec 280 * @defgroup EFM32WG995F256_Peripheral_TypeDefs EFM32WG995F256 Peripheral TypeDefs
<> 150:02e0a0aed4ec 281 * @{
<> 150:02e0a0aed4ec 282 * @brief Device Specific Peripheral Register Structures
<> 150:02e0a0aed4ec 283 *****************************************************************************/
<> 150:02e0a0aed4ec 284
<> 150:02e0a0aed4ec 285 #include "efm32wg_dma_ch.h"
<> 150:02e0a0aed4ec 286 #include "efm32wg_dma.h"
<> 150:02e0a0aed4ec 287 #include "efm32wg_aes.h"
<> 150:02e0a0aed4ec 288 #include "efm32wg_usb_hc.h"
<> 150:02e0a0aed4ec 289 #include "efm32wg_usb_diep.h"
<> 150:02e0a0aed4ec 290 #include "efm32wg_usb_doep.h"
<> 150:02e0a0aed4ec 291 #include "efm32wg_usb.h"
<> 150:02e0a0aed4ec 292 #include "efm32wg_msc.h"
<> 150:02e0a0aed4ec 293 #include "efm32wg_emu.h"
<> 150:02e0a0aed4ec 294 #include "efm32wg_rmu.h"
<> 150:02e0a0aed4ec 295 #include "efm32wg_cmu.h"
<> 150:02e0a0aed4ec 296 #include "efm32wg_lesense_st.h"
<> 150:02e0a0aed4ec 297 #include "efm32wg_lesense_buf.h"
<> 150:02e0a0aed4ec 298 #include "efm32wg_lesense_ch.h"
<> 150:02e0a0aed4ec 299 #include "efm32wg_lesense.h"
<> 150:02e0a0aed4ec 300 #include "efm32wg_ebi.h"
<> 150:02e0a0aed4ec 301 #include "efm32wg_fpueh.h"
<> 150:02e0a0aed4ec 302 #include "efm32wg_usart.h"
<> 150:02e0a0aed4ec 303 #include "efm32wg_timer_cc.h"
<> 150:02e0a0aed4ec 304 #include "efm32wg_timer.h"
<> 150:02e0a0aed4ec 305 #include "efm32wg_acmp.h"
<> 150:02e0a0aed4ec 306 #include "efm32wg_leuart.h"
<> 150:02e0a0aed4ec 307 #include "efm32wg_rtc.h"
<> 150:02e0a0aed4ec 308 #include "efm32wg_letimer.h"
<> 150:02e0a0aed4ec 309 #include "efm32wg_pcnt.h"
<> 150:02e0a0aed4ec 310 #include "efm32wg_i2c.h"
<> 150:02e0a0aed4ec 311 #include "efm32wg_gpio_p.h"
<> 150:02e0a0aed4ec 312 #include "efm32wg_gpio.h"
<> 150:02e0a0aed4ec 313 #include "efm32wg_vcmp.h"
<> 150:02e0a0aed4ec 314 #include "efm32wg_prs_ch.h"
<> 150:02e0a0aed4ec 315 #include "efm32wg_prs.h"
<> 150:02e0a0aed4ec 316 #include "efm32wg_adc.h"
<> 150:02e0a0aed4ec 317 #include "efm32wg_dac.h"
<> 150:02e0a0aed4ec 318 #include "efm32wg_lcd.h"
<> 150:02e0a0aed4ec 319 #include "efm32wg_burtc_ret.h"
<> 150:02e0a0aed4ec 320 #include "efm32wg_burtc.h"
<> 150:02e0a0aed4ec 321 #include "efm32wg_wdog.h"
<> 150:02e0a0aed4ec 322 #include "efm32wg_etm.h"
<> 150:02e0a0aed4ec 323 #include "efm32wg_dma_descriptor.h"
<> 150:02e0a0aed4ec 324 #include "efm32wg_devinfo.h"
<> 150:02e0a0aed4ec 325 #include "efm32wg_romtable.h"
<> 150:02e0a0aed4ec 326 #include "efm32wg_calibrate.h"
<> 150:02e0a0aed4ec 327
<> 150:02e0a0aed4ec 328 /** @} End of group EFM32WG995F256_Peripheral_TypeDefs */
<> 150:02e0a0aed4ec 329
<> 150:02e0a0aed4ec 330 /**************************************************************************//**
<> 150:02e0a0aed4ec 331 * @defgroup EFM32WG995F256_Peripheral_Base EFM32WG995F256 Peripheral Memory Map
<> 150:02e0a0aed4ec 332 * @{
<> 150:02e0a0aed4ec 333 *****************************************************************************/
<> 150:02e0a0aed4ec 334
<> 150:02e0a0aed4ec 335 #define DMA_BASE (0x400C2000UL) /**< DMA base address */
<> 150:02e0a0aed4ec 336 #define AES_BASE (0x400E0000UL) /**< AES base address */
<> 150:02e0a0aed4ec 337 #define USB_BASE (0x400C4000UL) /**< USB base address */
<> 150:02e0a0aed4ec 338 #define MSC_BASE (0x400C0000UL) /**< MSC base address */
<> 150:02e0a0aed4ec 339 #define EMU_BASE (0x400C6000UL) /**< EMU base address */
<> 150:02e0a0aed4ec 340 #define RMU_BASE (0x400CA000UL) /**< RMU base address */
<> 150:02e0a0aed4ec 341 #define CMU_BASE (0x400C8000UL) /**< CMU base address */
<> 150:02e0a0aed4ec 342 #define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */
<> 150:02e0a0aed4ec 343 #define EBI_BASE (0x40008000UL) /**< EBI base address */
<> 150:02e0a0aed4ec 344 #define FPUEH_BASE (0x400C1C00UL) /**< FPUEH base address */
<> 150:02e0a0aed4ec 345 #define USART0_BASE (0x4000C000UL) /**< USART0 base address */
<> 150:02e0a0aed4ec 346 #define USART1_BASE (0x4000C400UL) /**< USART1 base address */
<> 150:02e0a0aed4ec 347 #define USART2_BASE (0x4000C800UL) /**< USART2 base address */
<> 150:02e0a0aed4ec 348 #define UART0_BASE (0x4000E000UL) /**< UART0 base address */
<> 150:02e0a0aed4ec 349 #define UART1_BASE (0x4000E400UL) /**< UART1 base address */
<> 150:02e0a0aed4ec 350 #define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */
<> 150:02e0a0aed4ec 351 #define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */
<> 150:02e0a0aed4ec 352 #define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */
<> 150:02e0a0aed4ec 353 #define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */
<> 150:02e0a0aed4ec 354 #define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */
<> 150:02e0a0aed4ec 355 #define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */
<> 150:02e0a0aed4ec 356 #define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */
<> 150:02e0a0aed4ec 357 #define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */
<> 150:02e0a0aed4ec 358 #define RTC_BASE (0x40080000UL) /**< RTC base address */
<> 150:02e0a0aed4ec 359 #define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */
<> 150:02e0a0aed4ec 360 #define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */
<> 150:02e0a0aed4ec 361 #define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */
<> 150:02e0a0aed4ec 362 #define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */
<> 150:02e0a0aed4ec 363 #define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */
<> 150:02e0a0aed4ec 364 #define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */
<> 150:02e0a0aed4ec 365 #define GPIO_BASE (0x40006000UL) /**< GPIO base address */
<> 150:02e0a0aed4ec 366 #define VCMP_BASE (0x40000000UL) /**< VCMP base address */
<> 150:02e0a0aed4ec 367 #define PRS_BASE (0x400CC000UL) /**< PRS base address */
<> 150:02e0a0aed4ec 368 #define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
<> 150:02e0a0aed4ec 369 #define DAC0_BASE (0x40004000UL) /**< DAC0 base address */
<> 150:02e0a0aed4ec 370 #define LCD_BASE (0x4008A000UL) /**< LCD base address */
<> 150:02e0a0aed4ec 371 #define BURTC_BASE (0x40081000UL) /**< BURTC base address */
<> 150:02e0a0aed4ec 372 #define WDOG_BASE (0x40088000UL) /**< WDOG base address */
<> 150:02e0a0aed4ec 373 #define ETM_BASE (0xE0041000UL) /**< ETM base address */
<> 150:02e0a0aed4ec 374 #define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */
<> 150:02e0a0aed4ec 375 #define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
<> 150:02e0a0aed4ec 376 #define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
<> 150:02e0a0aed4ec 377 #define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
<> 150:02e0a0aed4ec 378 #define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
<> 150:02e0a0aed4ec 379
<> 150:02e0a0aed4ec 380 /** @} End of group EFM32WG995F256_Peripheral_Base */
<> 150:02e0a0aed4ec 381
<> 150:02e0a0aed4ec 382 /**************************************************************************//**
<> 150:02e0a0aed4ec 383 * @defgroup EFM32WG995F256_Peripheral_Declaration EFM32WG995F256 Peripheral Declarations
<> 150:02e0a0aed4ec 384 * @{
<> 150:02e0a0aed4ec 385 *****************************************************************************/
<> 150:02e0a0aed4ec 386
<> 150:02e0a0aed4ec 387 #define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
<> 150:02e0a0aed4ec 388 #define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
<> 150:02e0a0aed4ec 389 #define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */
<> 150:02e0a0aed4ec 390 #define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
<> 150:02e0a0aed4ec 391 #define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
<> 150:02e0a0aed4ec 392 #define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
<> 150:02e0a0aed4ec 393 #define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
<> 150:02e0a0aed4ec 394 #define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */
<> 150:02e0a0aed4ec 395 #define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */
<> 150:02e0a0aed4ec 396 #define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */
<> 150:02e0a0aed4ec 397 #define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
<> 150:02e0a0aed4ec 398 #define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
<> 150:02e0a0aed4ec 399 #define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
<> 150:02e0a0aed4ec 400 #define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */
<> 150:02e0a0aed4ec 401 #define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */
<> 150:02e0a0aed4ec 402 #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
<> 150:02e0a0aed4ec 403 #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
<> 150:02e0a0aed4ec 404 #define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
<> 150:02e0a0aed4ec 405 #define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */
<> 150:02e0a0aed4ec 406 #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
<> 150:02e0a0aed4ec 407 #define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
<> 150:02e0a0aed4ec 408 #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
<> 150:02e0a0aed4ec 409 #define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
<> 150:02e0a0aed4ec 410 #define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
<> 150:02e0a0aed4ec 411 #define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
<> 150:02e0a0aed4ec 412 #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
<> 150:02e0a0aed4ec 413 #define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
<> 150:02e0a0aed4ec 414 #define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
<> 150:02e0a0aed4ec 415 #define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
<> 150:02e0a0aed4ec 416 #define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */
<> 150:02e0a0aed4ec 417 #define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
<> 150:02e0a0aed4ec 418 #define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
<> 150:02e0a0aed4ec 419 #define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
<> 150:02e0a0aed4ec 420 #define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
<> 150:02e0a0aed4ec 421 #define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
<> 150:02e0a0aed4ec 422 #define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */
<> 150:02e0a0aed4ec 423 #define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */
<> 150:02e0a0aed4ec 424 #define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
<> 150:02e0a0aed4ec 425 #define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */
<> 150:02e0a0aed4ec 426 #define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
<> 150:02e0a0aed4ec 427 #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
<> 150:02e0a0aed4ec 428 #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
<> 150:02e0a0aed4ec 429
<> 150:02e0a0aed4ec 430 /** @} End of group EFM32WG995F256_Peripheral_Declaration */
<> 150:02e0a0aed4ec 431
<> 150:02e0a0aed4ec 432 /**************************************************************************//**
<> 150:02e0a0aed4ec 433 * @defgroup EFM32WG995F256_BitFields EFM32WG995F256 Bit Fields
<> 150:02e0a0aed4ec 434 * @{
<> 150:02e0a0aed4ec 435 *****************************************************************************/
<> 150:02e0a0aed4ec 436
<> 150:02e0a0aed4ec 437 #include "efm32wg_prs_signals.h"
<> 150:02e0a0aed4ec 438 #include "efm32wg_dmareq.h"
<> 150:02e0a0aed4ec 439 #include "efm32wg_dmactrl.h"
<> 150:02e0a0aed4ec 440 #include "efm32wg_uart.h"
<> 150:02e0a0aed4ec 441
<> 150:02e0a0aed4ec 442 /**************************************************************************//**
<> 150:02e0a0aed4ec 443 * @defgroup EFM32WG995F256_UNLOCK EFM32WG995F256 Unlock Codes
<> 150:02e0a0aed4ec 444 * @{
<> 150:02e0a0aed4ec 445 *****************************************************************************/
<> 150:02e0a0aed4ec 446 #define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
<> 150:02e0a0aed4ec 447 #define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
<> 150:02e0a0aed4ec 448 #define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
<> 150:02e0a0aed4ec 449 #define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
<> 150:02e0a0aed4ec 450 #define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
<> 150:02e0a0aed4ec 451 #define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */
<> 150:02e0a0aed4ec 452
<> 150:02e0a0aed4ec 453 /** @} End of group EFM32WG995F256_UNLOCK */
<> 150:02e0a0aed4ec 454
<> 150:02e0a0aed4ec 455 /** @} End of group EFM32WG995F256_BitFields */
<> 150:02e0a0aed4ec 456
<> 150:02e0a0aed4ec 457 /**************************************************************************//**
<> 150:02e0a0aed4ec 458 * @defgroup EFM32WG995F256_Alternate_Function EFM32WG995F256 Alternate Function
<> 150:02e0a0aed4ec 459 * @{
<> 150:02e0a0aed4ec 460 *****************************************************************************/
<> 150:02e0a0aed4ec 461
<> 150:02e0a0aed4ec 462 #include "efm32wg_af_ports.h"
<> 150:02e0a0aed4ec 463 #include "efm32wg_af_pins.h"
<> 150:02e0a0aed4ec 464
<> 150:02e0a0aed4ec 465 /** @} End of group EFM32WG995F256_Alternate_Function */
<> 150:02e0a0aed4ec 466
<> 150:02e0a0aed4ec 467 /**************************************************************************//**
<> 150:02e0a0aed4ec 468 * @brief Set the value of a bit field within a register.
<> 150:02e0a0aed4ec 469 *
<> 150:02e0a0aed4ec 470 * @param REG
<> 150:02e0a0aed4ec 471 * The register to update
<> 150:02e0a0aed4ec 472 * @param MASK
<> 150:02e0a0aed4ec 473 * The mask for the bit field to update
<> 150:02e0a0aed4ec 474 * @param VALUE
<> 150:02e0a0aed4ec 475 * The value to write to the bit field
<> 150:02e0a0aed4ec 476 * @param OFFSET
<> 150:02e0a0aed4ec 477 * The number of bits that the field is offset within the register.
<> 150:02e0a0aed4ec 478 * 0 (zero) means LSB.
<> 150:02e0a0aed4ec 479 *****************************************************************************/
<> 150:02e0a0aed4ec 480 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
<> 150:02e0a0aed4ec 481 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
<> 150:02e0a0aed4ec 482
<> 150:02e0a0aed4ec 483 /** @} End of group EFM32WG995F256 */
<> 150:02e0a0aed4ec 484
<> 150:02e0a0aed4ec 485 /** @} End of group Parts */
<> 150:02e0a0aed4ec 486
<> 150:02e0a0aed4ec 487 #ifdef __cplusplus
<> 150:02e0a0aed4ec 488 }
<> 150:02e0a0aed4ec 489 #endif
<> 150:02e0a0aed4ec 490 #endif /* EFM32WG995F256_H */