Fawwaz Nadzmy / mbed-STM

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg895f128.h@153:9398a535854b, 2016-12-22 (annotated)

Committer:
fwndz
Date:
Thu Dec 22 05:12:40 2016 +0000
Revision:
153:9398a535854b
Parent:
150:02e0a0aed4ec 
device target maximize

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 150:02e0a0aed4ec 1 /**************************************************************************//**
<> 150:02e0a0aed4ec 2 * @file efm32wg895f128.h
<> 150:02e0a0aed4ec 3 * @brief CMSIS Cortex-M Peripheral Access Layer Header File
<> 150:02e0a0aed4ec 4 * for EFM32WG895F128
<> 150:02e0a0aed4ec 5 * @version 5.0.0
<> 150:02e0a0aed4ec 6 ******************************************************************************
<> 150:02e0a0aed4ec 7 * @section License
<> 150:02e0a0aed4ec 8 * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 150:02e0a0aed4ec 9 ******************************************************************************
<> 150:02e0a0aed4ec 10 *
<> 150:02e0a0aed4ec 11 * Permission is granted to anyone to use this software for any purpose,
<> 150:02e0a0aed4ec 12 * including commercial applications, and to alter it and redistribute it
<> 150:02e0a0aed4ec 13 * freely, subject to the following restrictions:
<> 150:02e0a0aed4ec 14 *
<> 150:02e0a0aed4ec 15 * 1. The origin of this software must not be misrepresented; you must not
<> 150:02e0a0aed4ec 16 * claim that you wrote the original software.@n
<> 150:02e0a0aed4ec 17 * 2. Altered source versions must be plainly marked as such, and must not be
<> 150:02e0a0aed4ec 18 * misrepresented as being the original software.@n
<> 150:02e0a0aed4ec 19 * 3. This notice may not be removed or altered from any source distribution.
<> 150:02e0a0aed4ec 20 *
<> 150:02e0a0aed4ec 21 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 150:02e0a0aed4ec 22 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 150:02e0a0aed4ec 23 * providing the Software "AS IS", with no express or implied warranties of any
<> 150:02e0a0aed4ec 24 * kind, including, but not limited to, any implied warranties of
<> 150:02e0a0aed4ec 25 * merchantability or fitness for any particular purpose or warranties against
<> 150:02e0a0aed4ec 26 * infringement of any proprietary rights of a third party.
<> 150:02e0a0aed4ec 27 *
<> 150:02e0a0aed4ec 28 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 150:02e0a0aed4ec 29 * incidental, or special damages, or any other relief, or for any claim by
<> 150:02e0a0aed4ec 30 * any third party, arising from your use of this Software.
<> 150:02e0a0aed4ec 31 *
<> 150:02e0a0aed4ec 32 *****************************************************************************/
<> 150:02e0a0aed4ec 33
<> 150:02e0a0aed4ec 34 #ifndef EFM32WG895F128_H
<> 150:02e0a0aed4ec 35 #define EFM32WG895F128_H
<> 150:02e0a0aed4ec 36
<> 150:02e0a0aed4ec 37 #ifdef __cplusplus
<> 150:02e0a0aed4ec 38 extern "C" {
<> 150:02e0a0aed4ec 39 #endif
<> 150:02e0a0aed4ec 40
<> 150:02e0a0aed4ec 41 /**************************************************************************//**
<> 150:02e0a0aed4ec 42 * @addtogroup Parts
<> 150:02e0a0aed4ec 43 * @{
<> 150:02e0a0aed4ec 44 *****************************************************************************/
<> 150:02e0a0aed4ec 45
<> 150:02e0a0aed4ec 46 /**************************************************************************//**
<> 150:02e0a0aed4ec 47 * @defgroup EFM32WG895F128 EFM32WG895F128
<> 150:02e0a0aed4ec 48 * @{
<> 150:02e0a0aed4ec 49 *****************************************************************************/
<> 150:02e0a0aed4ec 50
<> 150:02e0a0aed4ec 51 /** Interrupt Number Definition */
<> 150:02e0a0aed4ec 52 typedef enum IRQn
<> 150:02e0a0aed4ec 53 {
<> 150:02e0a0aed4ec 54 /****** Cortex-M4 Processor Exceptions Numbers ********************************************/
<> 150:02e0a0aed4ec 55 NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */
<> 150:02e0a0aed4ec 56 HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */
<> 150:02e0a0aed4ec 57 MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */
<> 150:02e0a0aed4ec 58 BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */
<> 150:02e0a0aed4ec 59 UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */
<> 150:02e0a0aed4ec 60 SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */
<> 150:02e0a0aed4ec 61 DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */
<> 150:02e0a0aed4ec 62 PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */
<> 150:02e0a0aed4ec 63 SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */
<> 150:02e0a0aed4ec 64
<> 150:02e0a0aed4ec 65 /****** EFM32WG Peripheral Interrupt Numbers **********************************************/
<> 150:02e0a0aed4ec 66 DMA_IRQn = 0, /*!< 0 EFM32 DMA Interrupt */
<> 150:02e0a0aed4ec 67 GPIO_EVEN_IRQn = 1, /*!< 1 EFM32 GPIO_EVEN Interrupt */
<> 150:02e0a0aed4ec 68 TIMER0_IRQn = 2, /*!< 2 EFM32 TIMER0 Interrupt */
<> 150:02e0a0aed4ec 69 USART0_RX_IRQn = 3, /*!< 3 EFM32 USART0_RX Interrupt */
<> 150:02e0a0aed4ec 70 USART0_TX_IRQn = 4, /*!< 4 EFM32 USART0_TX Interrupt */
<> 150:02e0a0aed4ec 71 ACMP0_IRQn = 6, /*!< 6 EFM32 ACMP0 Interrupt */
<> 150:02e0a0aed4ec 72 ADC0_IRQn = 7, /*!< 7 EFM32 ADC0 Interrupt */
<> 150:02e0a0aed4ec 73 DAC0_IRQn = 8, /*!< 8 EFM32 DAC0 Interrupt */
<> 150:02e0a0aed4ec 74 I2C0_IRQn = 9, /*!< 9 EFM32 I2C0 Interrupt */
<> 150:02e0a0aed4ec 75 I2C1_IRQn = 10, /*!< 10 EFM32 I2C1 Interrupt */
<> 150:02e0a0aed4ec 76 GPIO_ODD_IRQn = 11, /*!< 11 EFM32 GPIO_ODD Interrupt */
<> 150:02e0a0aed4ec 77 TIMER1_IRQn = 12, /*!< 12 EFM32 TIMER1 Interrupt */
<> 150:02e0a0aed4ec 78 TIMER2_IRQn = 13, /*!< 13 EFM32 TIMER2 Interrupt */
<> 150:02e0a0aed4ec 79 TIMER3_IRQn = 14, /*!< 14 EFM32 TIMER3 Interrupt */
<> 150:02e0a0aed4ec 80 USART1_RX_IRQn = 15, /*!< 15 EFM32 USART1_RX Interrupt */
<> 150:02e0a0aed4ec 81 USART1_TX_IRQn = 16, /*!< 16 EFM32 USART1_TX Interrupt */
<> 150:02e0a0aed4ec 82 LESENSE_IRQn = 17, /*!< 17 EFM32 LESENSE Interrupt */
<> 150:02e0a0aed4ec 83 USART2_RX_IRQn = 18, /*!< 18 EFM32 USART2_RX Interrupt */
<> 150:02e0a0aed4ec 84 USART2_TX_IRQn = 19, /*!< 19 EFM32 USART2_TX Interrupt */
<> 150:02e0a0aed4ec 85 UART0_RX_IRQn = 20, /*!< 20 EFM32 UART0_RX Interrupt */
<> 150:02e0a0aed4ec 86 UART0_TX_IRQn = 21, /*!< 21 EFM32 UART0_TX Interrupt */
<> 150:02e0a0aed4ec 87 UART1_RX_IRQn = 22, /*!< 22 EFM32 UART1_RX Interrupt */
<> 150:02e0a0aed4ec 88 UART1_TX_IRQn = 23, /*!< 23 EFM32 UART1_TX Interrupt */
<> 150:02e0a0aed4ec 89 LEUART0_IRQn = 24, /*!< 24 EFM32 LEUART0 Interrupt */
<> 150:02e0a0aed4ec 90 LEUART1_IRQn = 25, /*!< 25 EFM32 LEUART1 Interrupt */
<> 150:02e0a0aed4ec 91 LETIMER0_IRQn = 26, /*!< 26 EFM32 LETIMER0 Interrupt */
<> 150:02e0a0aed4ec 92 PCNT0_IRQn = 27, /*!< 27 EFM32 PCNT0 Interrupt */
<> 150:02e0a0aed4ec 93 PCNT1_IRQn = 28, /*!< 28 EFM32 PCNT1 Interrupt */
<> 150:02e0a0aed4ec 94 PCNT2_IRQn = 29, /*!< 29 EFM32 PCNT2 Interrupt */
<> 150:02e0a0aed4ec 95 RTC_IRQn = 30, /*!< 30 EFM32 RTC Interrupt */
<> 150:02e0a0aed4ec 96 BURTC_IRQn = 31, /*!< 31 EFM32 BURTC Interrupt */
<> 150:02e0a0aed4ec 97 CMU_IRQn = 32, /*!< 32 EFM32 CMU Interrupt */
<> 150:02e0a0aed4ec 98 VCMP_IRQn = 33, /*!< 33 EFM32 VCMP Interrupt */
<> 150:02e0a0aed4ec 99 LCD_IRQn = 34, /*!< 34 EFM32 LCD Interrupt */
<> 150:02e0a0aed4ec 100 MSC_IRQn = 35, /*!< 35 EFM32 MSC Interrupt */
<> 150:02e0a0aed4ec 101 AES_IRQn = 36, /*!< 36 EFM32 AES Interrupt */
<> 150:02e0a0aed4ec 102 EBI_IRQn = 37, /*!< 37 EFM32 EBI Interrupt */
<> 150:02e0a0aed4ec 103 EMU_IRQn = 38, /*!< 38 EFM32 EMU Interrupt */
<> 150:02e0a0aed4ec 104 FPUEH_IRQn = 39, /*!< 39 EFM32 FPUEH Interrupt */
<> 150:02e0a0aed4ec 105 } IRQn_Type;
<> 150:02e0a0aed4ec 106
<> 150:02e0a0aed4ec 107 /**************************************************************************//**
<> 150:02e0a0aed4ec 108 * @defgroup EFM32WG895F128_Core EFM32WG895F128 Core
<> 150:02e0a0aed4ec 109 * @{
<> 150:02e0a0aed4ec 110 * @brief Processor and Core Peripheral Section
<> 150:02e0a0aed4ec 111 *****************************************************************************/
<> 150:02e0a0aed4ec 112 #define __MPU_PRESENT 1 /**< Presence of MPU */
<> 150:02e0a0aed4ec 113 #define __FPU_PRESENT 1 /**< Presence of FPU */
<> 150:02e0a0aed4ec 114 #define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
<> 150:02e0a0aed4ec 115 #define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
<> 150:02e0a0aed4ec 116 #define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
<> 150:02e0a0aed4ec 117
<> 150:02e0a0aed4ec 118 /** @} End of group EFM32WG895F128_Core */
<> 150:02e0a0aed4ec 119
<> 150:02e0a0aed4ec 120 /**************************************************************************//**
<> 150:02e0a0aed4ec 121 * @defgroup EFM32WG895F128_Part EFM32WG895F128 Part
<> 150:02e0a0aed4ec 122 * @{
<> 150:02e0a0aed4ec 123 ******************************************************************************/
<> 150:02e0a0aed4ec 124
<> 150:02e0a0aed4ec 125 /** Part family */
<> 150:02e0a0aed4ec 126 #define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */
<> 150:02e0a0aed4ec 127 #define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */
<> 150:02e0a0aed4ec 128 #define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */
<> 150:02e0a0aed4ec 129 #define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */
<> 150:02e0a0aed4ec 130 #define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */
<> 150:02e0a0aed4ec 131 #define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */
<> 150:02e0a0aed4ec 132
<> 150:02e0a0aed4ec 133 /* If part number is not defined as compiler option, define it */
<> 150:02e0a0aed4ec 134 #if !defined(EFM32WG895F128)
<> 150:02e0a0aed4ec 135 #define EFM32WG895F128 1 /**< Wonder Gecko Part */
<> 150:02e0a0aed4ec 136 #endif
<> 150:02e0a0aed4ec 137
<> 150:02e0a0aed4ec 138 /** Configure part number */
<> 150:02e0a0aed4ec 139 #define PART_NUMBER "EFM32WG895F128" /**< Part Number */
<> 150:02e0a0aed4ec 140
<> 150:02e0a0aed4ec 141 /** Memory Base addresses and limits */
<> 150:02e0a0aed4ec 142 #define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
<> 150:02e0a0aed4ec 143 #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
<> 150:02e0a0aed4ec 144 #define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
<> 150:02e0a0aed4ec 145 #define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
<> 150:02e0a0aed4ec 146 #define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
<> 150:02e0a0aed4ec 147 #define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
<> 150:02e0a0aed4ec 148 #define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
<> 150:02e0a0aed4ec 149 #define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
<> 150:02e0a0aed4ec 150 #define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */
<> 150:02e0a0aed4ec 151 #define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */
<> 150:02e0a0aed4ec 152 #define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */
<> 150:02e0a0aed4ec 153 #define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */
<> 150:02e0a0aed4ec 154 #define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */
<> 150:02e0a0aed4ec 155 #define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */
<> 150:02e0a0aed4ec 156 #define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */
<> 150:02e0a0aed4ec 157 #define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */
<> 150:02e0a0aed4ec 158 #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
<> 150:02e0a0aed4ec 159 #define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
<> 150:02e0a0aed4ec 160 #define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
<> 150:02e0a0aed4ec 161 #define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
<> 150:02e0a0aed4ec 162 #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
<> 150:02e0a0aed4ec 163 #define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */
<> 150:02e0a0aed4ec 164 #define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */
<> 150:02e0a0aed4ec 165 #define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */
<> 150:02e0a0aed4ec 166 #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
<> 150:02e0a0aed4ec 167 #define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */
<> 150:02e0a0aed4ec 168 #define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */
<> 150:02e0a0aed4ec 169 #define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */
<> 150:02e0a0aed4ec 170 #define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
<> 150:02e0a0aed4ec 171 #define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */
<> 150:02e0a0aed4ec 172 #define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */
<> 150:02e0a0aed4ec 173 #define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */
<> 150:02e0a0aed4ec 174
<> 150:02e0a0aed4ec 175 /** Bit banding area */
<> 150:02e0a0aed4ec 176 #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
<> 150:02e0a0aed4ec 177 #define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
<> 150:02e0a0aed4ec 178
<> 150:02e0a0aed4ec 179 /** Flash and SRAM limits for EFM32WG895F128 */
<> 150:02e0a0aed4ec 180 #define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
<> 150:02e0a0aed4ec 181 #define FLASH_SIZE (0x00020000UL) /**< Available Flash Memory */
<> 150:02e0a0aed4ec 182 #define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size */
<> 150:02e0a0aed4ec 183 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
<> 150:02e0a0aed4ec 184 #define SRAM_SIZE (0x00008000UL) /**< Available SRAM Memory */
<> 150:02e0a0aed4ec 185 #define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */
<> 150:02e0a0aed4ec 186 #define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
<> 150:02e0a0aed4ec 187 #define DMA_CHAN_COUNT 12 /**< Number of DMA channels */
<> 150:02e0a0aed4ec 188 #define EXT_IRQ_COUNT 40 /**< Number of External (NVIC) interrupts */
<> 150:02e0a0aed4ec 189
<> 150:02e0a0aed4ec 190 /** AF channels connect the different on-chip peripherals with the af-mux */
<> 150:02e0a0aed4ec 191 #define AFCHAN_MAX 163
<> 150:02e0a0aed4ec 192 #define AFCHANLOC_MAX 7
<> 150:02e0a0aed4ec 193 /** Analog AF channels */
<> 150:02e0a0aed4ec 194 #define AFACHAN_MAX 53
<> 150:02e0a0aed4ec 195
<> 150:02e0a0aed4ec 196 /* Part number capabilities */
<> 150:02e0a0aed4ec 197
<> 150:02e0a0aed4ec 198 #define USART_PRESENT /**< USART is available in this part */
<> 150:02e0a0aed4ec 199 #define USART_COUNT 3 /**< 3 USARTs available */
<> 150:02e0a0aed4ec 200 #define UART_PRESENT /**< UART is available in this part */
<> 150:02e0a0aed4ec 201 #define UART_COUNT 2 /**< 2 UARTs available */
<> 150:02e0a0aed4ec 202 #define TIMER_PRESENT /**< TIMER is available in this part */
<> 150:02e0a0aed4ec 203 #define TIMER_COUNT 4 /**< 4 TIMERs available */
<> 150:02e0a0aed4ec 204 #define ACMP_PRESENT /**< ACMP is available in this part */
<> 150:02e0a0aed4ec 205 #define ACMP_COUNT 2 /**< 2 ACMPs available */
<> 150:02e0a0aed4ec 206 #define LEUART_PRESENT /**< LEUART is available in this part */
<> 150:02e0a0aed4ec 207 #define LEUART_COUNT 2 /**< 2 LEUARTs available */
<> 150:02e0a0aed4ec 208 #define LETIMER_PRESENT /**< LETIMER is available in this part */
<> 150:02e0a0aed4ec 209 #define LETIMER_COUNT 1 /**< 1 LETIMERs available */
<> 150:02e0a0aed4ec 210 #define PCNT_PRESENT /**< PCNT is available in this part */
<> 150:02e0a0aed4ec 211 #define PCNT_COUNT 3 /**< 3 PCNTs available */
<> 150:02e0a0aed4ec 212 #define I2C_PRESENT /**< I2C is available in this part */
<> 150:02e0a0aed4ec 213 #define I2C_COUNT 2 /**< 2 I2Cs available */
<> 150:02e0a0aed4ec 214 #define ADC_PRESENT /**< ADC is available in this part */
<> 150:02e0a0aed4ec 215 #define ADC_COUNT 1 /**< 1 ADCs available */
<> 150:02e0a0aed4ec 216 #define DAC_PRESENT /**< DAC is available in this part */
<> 150:02e0a0aed4ec 217 #define DAC_COUNT 1 /**< 1 DACs available */
<> 150:02e0a0aed4ec 218 #define DMA_PRESENT
<> 150:02e0a0aed4ec 219 #define DMA_COUNT 1
<> 150:02e0a0aed4ec 220 #define AES_PRESENT
<> 150:02e0a0aed4ec 221 #define AES_COUNT 1
<> 150:02e0a0aed4ec 222 #define LE_PRESENT
<> 150:02e0a0aed4ec 223 #define LE_COUNT 1
<> 150:02e0a0aed4ec 224 #define MSC_PRESENT
<> 150:02e0a0aed4ec 225 #define MSC_COUNT 1
<> 150:02e0a0aed4ec 226 #define EMU_PRESENT
<> 150:02e0a0aed4ec 227 #define EMU_COUNT 1
<> 150:02e0a0aed4ec 228 #define RMU_PRESENT
<> 150:02e0a0aed4ec 229 #define RMU_COUNT 1
<> 150:02e0a0aed4ec 230 #define CMU_PRESENT
<> 150:02e0a0aed4ec 231 #define CMU_COUNT 1
<> 150:02e0a0aed4ec 232 #define LESENSE_PRESENT
<> 150:02e0a0aed4ec 233 #define LESENSE_COUNT 1
<> 150:02e0a0aed4ec 234 #define EBI_PRESENT
<> 150:02e0a0aed4ec 235 #define EBI_COUNT 1
<> 150:02e0a0aed4ec 236 #define FPUEH_PRESENT
<> 150:02e0a0aed4ec 237 #define FPUEH_COUNT 1
<> 150:02e0a0aed4ec 238 #define RTC_PRESENT
<> 150:02e0a0aed4ec 239 #define RTC_COUNT 1
<> 150:02e0a0aed4ec 240 #define GPIO_PRESENT
<> 150:02e0a0aed4ec 241 #define GPIO_COUNT 1
<> 150:02e0a0aed4ec 242 #define VCMP_PRESENT
<> 150:02e0a0aed4ec 243 #define VCMP_COUNT 1
<> 150:02e0a0aed4ec 244 #define PRS_PRESENT
<> 150:02e0a0aed4ec 245 #define PRS_COUNT 1
<> 150:02e0a0aed4ec 246 #define OPAMP_PRESENT
<> 150:02e0a0aed4ec 247 #define OPAMP_COUNT 1
<> 150:02e0a0aed4ec 248 #define BU_PRESENT
<> 150:02e0a0aed4ec 249 #define BU_COUNT 1
<> 150:02e0a0aed4ec 250 #define LCD_PRESENT
<> 150:02e0a0aed4ec 251 #define LCD_COUNT 1
<> 150:02e0a0aed4ec 252 #define BURTC_PRESENT
<> 150:02e0a0aed4ec 253 #define BURTC_COUNT 1
<> 150:02e0a0aed4ec 254 #define HFXTAL_PRESENT
<> 150:02e0a0aed4ec 255 #define HFXTAL_COUNT 1
<> 150:02e0a0aed4ec 256 #define LFXTAL_PRESENT
<> 150:02e0a0aed4ec 257 #define LFXTAL_COUNT 1
<> 150:02e0a0aed4ec 258 #define WDOG_PRESENT
<> 150:02e0a0aed4ec 259 #define WDOG_COUNT 1
<> 150:02e0a0aed4ec 260 #define DBG_PRESENT
<> 150:02e0a0aed4ec 261 #define DBG_COUNT 1
<> 150:02e0a0aed4ec 262 #define ETM_PRESENT
<> 150:02e0a0aed4ec 263 #define ETM_COUNT 1
<> 150:02e0a0aed4ec 264 #define BOOTLOADER_PRESENT
<> 150:02e0a0aed4ec 265 #define BOOTLOADER_COUNT 1
<> 150:02e0a0aed4ec 266 #define ANALOG_PRESENT
<> 150:02e0a0aed4ec 267 #define ANALOG_COUNT 1
<> 150:02e0a0aed4ec 268
<> 150:02e0a0aed4ec 269 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
<> 150:02e0a0aed4ec 270 #include "system_efm32wg.h" /* System Header */
<> 150:02e0a0aed4ec 271
<> 150:02e0a0aed4ec 272 /** @} End of group EFM32WG895F128_Part */
<> 150:02e0a0aed4ec 273
<> 150:02e0a0aed4ec 274 /**************************************************************************//**
<> 150:02e0a0aed4ec 275 * @defgroup EFM32WG895F128_Peripheral_TypeDefs EFM32WG895F128 Peripheral TypeDefs
<> 150:02e0a0aed4ec 276 * @{
<> 150:02e0a0aed4ec 277 * @brief Device Specific Peripheral Register Structures
<> 150:02e0a0aed4ec 278 *****************************************************************************/
<> 150:02e0a0aed4ec 279
<> 150:02e0a0aed4ec 280 #include "efm32wg_dma_ch.h"
<> 150:02e0a0aed4ec 281 #include "efm32wg_dma.h"
<> 150:02e0a0aed4ec 282 #include "efm32wg_aes.h"
<> 150:02e0a0aed4ec 283 #include "efm32wg_msc.h"
<> 150:02e0a0aed4ec 284 #include "efm32wg_emu.h"
<> 150:02e0a0aed4ec 285 #include "efm32wg_rmu.h"
<> 150:02e0a0aed4ec 286
<> 150:02e0a0aed4ec 287 /**************************************************************************//**
<> 150:02e0a0aed4ec 288 * @defgroup EFM32WG895F128_CMU EFM32WG895F128 CMU
<> 150:02e0a0aed4ec 289 * @{
<> 150:02e0a0aed4ec 290 * @brief EFM32WG895F128_CMU Register Declaration
<> 150:02e0a0aed4ec 291 *****************************************************************************/
<> 150:02e0a0aed4ec 292 typedef struct
<> 150:02e0a0aed4ec 293 {
<> 150:02e0a0aed4ec 294 __IOM uint32_t CTRL; /**< CMU Control Register */
<> 150:02e0a0aed4ec 295 __IOM uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register */
<> 150:02e0a0aed4ec 296 __IOM uint32_t HFPERCLKDIV; /**< High Frequency Peripheral Clock Division Register */
<> 150:02e0a0aed4ec 297 __IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */
<> 150:02e0a0aed4ec 298 __IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */
<> 150:02e0a0aed4ec 299 __IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */
<> 150:02e0a0aed4ec 300 __IOM uint32_t CALCTRL; /**< Calibration Control Register */
<> 150:02e0a0aed4ec 301 __IOM uint32_t CALCNT; /**< Calibration Counter Register */
<> 150:02e0a0aed4ec 302 __IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */
<> 150:02e0a0aed4ec 303 __IOM uint32_t CMD; /**< Command Register */
<> 150:02e0a0aed4ec 304 __IOM uint32_t LFCLKSEL; /**< Low Frequency Clock Select Register */
<> 150:02e0a0aed4ec 305 __IM uint32_t STATUS; /**< Status Register */
<> 150:02e0a0aed4ec 306 __IM uint32_t IF; /**< Interrupt Flag Register */
<> 150:02e0a0aed4ec 307 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
<> 150:02e0a0aed4ec 308 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
<> 150:02e0a0aed4ec 309 __IOM uint32_t IEN; /**< Interrupt Enable Register */
<> 150:02e0a0aed4ec 310 __IOM uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0 */
<> 150:02e0a0aed4ec 311 __IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */
<> 150:02e0a0aed4ec 312 uint32_t RESERVED0[2]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 313 __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
<> 150:02e0a0aed4ec 314 __IOM uint32_t FREEZE; /**< Freeze Register */
<> 150:02e0a0aed4ec 315 __IOM uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */
<> 150:02e0a0aed4ec 316 uint32_t RESERVED1[1]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 317 __IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */
<> 150:02e0a0aed4ec 318
<> 150:02e0a0aed4ec 319 uint32_t RESERVED2[1]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 320 __IOM uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */
<> 150:02e0a0aed4ec 321 uint32_t RESERVED3[1]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 322 __IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */
<> 150:02e0a0aed4ec 323 uint32_t RESERVED4[1]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 324 __IOM uint32_t PCNTCTRL; /**< PCNT Control Register */
<> 150:02e0a0aed4ec 325 __IOM uint32_t LCDCTRL; /**< LCD Control Register */
<> 150:02e0a0aed4ec 326 __IOM uint32_t ROUTE; /**< I/O Routing Register */
<> 150:02e0a0aed4ec 327 __IOM uint32_t LOCK; /**< Configuration Lock Register */
<> 150:02e0a0aed4ec 328 } CMU_TypeDef; /** @} */
<> 150:02e0a0aed4ec 329
<> 150:02e0a0aed4ec 330 #include "efm32wg_lesense_st.h"
<> 150:02e0a0aed4ec 331 #include "efm32wg_lesense_buf.h"
<> 150:02e0a0aed4ec 332 #include "efm32wg_lesense_ch.h"
<> 150:02e0a0aed4ec 333 #include "efm32wg_lesense.h"
<> 150:02e0a0aed4ec 334 #include "efm32wg_ebi.h"
<> 150:02e0a0aed4ec 335 #include "efm32wg_fpueh.h"
<> 150:02e0a0aed4ec 336 #include "efm32wg_usart.h"
<> 150:02e0a0aed4ec 337 #include "efm32wg_timer_cc.h"
<> 150:02e0a0aed4ec 338 #include "efm32wg_timer.h"
<> 150:02e0a0aed4ec 339 #include "efm32wg_acmp.h"
<> 150:02e0a0aed4ec 340 #include "efm32wg_leuart.h"
<> 150:02e0a0aed4ec 341 #include "efm32wg_rtc.h"
<> 150:02e0a0aed4ec 342 #include "efm32wg_letimer.h"
<> 150:02e0a0aed4ec 343 #include "efm32wg_pcnt.h"
<> 150:02e0a0aed4ec 344 #include "efm32wg_i2c.h"
<> 150:02e0a0aed4ec 345 #include "efm32wg_gpio_p.h"
<> 150:02e0a0aed4ec 346 #include "efm32wg_gpio.h"
<> 150:02e0a0aed4ec 347 #include "efm32wg_vcmp.h"
<> 150:02e0a0aed4ec 348 #include "efm32wg_prs_ch.h"
<> 150:02e0a0aed4ec 349
<> 150:02e0a0aed4ec 350 /**************************************************************************//**
<> 150:02e0a0aed4ec 351 * @defgroup EFM32WG895F128_PRS EFM32WG895F128 PRS
<> 150:02e0a0aed4ec 352 * @{
<> 150:02e0a0aed4ec 353 * @brief EFM32WG895F128_PRS Register Declaration
<> 150:02e0a0aed4ec 354 *****************************************************************************/
<> 150:02e0a0aed4ec 355 typedef struct
<> 150:02e0a0aed4ec 356 {
<> 150:02e0a0aed4ec 357 __IOM uint32_t SWPULSE; /**< Software Pulse Register */
<> 150:02e0a0aed4ec 358 __IOM uint32_t SWLEVEL; /**< Software Level Register */
<> 150:02e0a0aed4ec 359 __IOM uint32_t ROUTE; /**< I/O Routing Register */
<> 150:02e0a0aed4ec 360
<> 150:02e0a0aed4ec 361 uint32_t RESERVED0[1]; /**< Reserved registers */
<> 150:02e0a0aed4ec 362 PRS_CH_TypeDef CH[12]; /**< Channel registers */
<> 150:02e0a0aed4ec 363 } PRS_TypeDef; /** @} */
<> 150:02e0a0aed4ec 364
<> 150:02e0a0aed4ec 365 #include "efm32wg_adc.h"
<> 150:02e0a0aed4ec 366 #include "efm32wg_dac.h"
<> 150:02e0a0aed4ec 367 #include "efm32wg_lcd.h"
<> 150:02e0a0aed4ec 368 #include "efm32wg_burtc_ret.h"
<> 150:02e0a0aed4ec 369 #include "efm32wg_burtc.h"
<> 150:02e0a0aed4ec 370 #include "efm32wg_wdog.h"
<> 150:02e0a0aed4ec 371 #include "efm32wg_etm.h"
<> 150:02e0a0aed4ec 372 #include "efm32wg_dma_descriptor.h"
<> 150:02e0a0aed4ec 373 #include "efm32wg_devinfo.h"
<> 150:02e0a0aed4ec 374 #include "efm32wg_romtable.h"
<> 150:02e0a0aed4ec 375 #include "efm32wg_calibrate.h"
<> 150:02e0a0aed4ec 376
<> 150:02e0a0aed4ec 377 /** @} End of group EFM32WG895F128_Peripheral_TypeDefs */
<> 150:02e0a0aed4ec 378
<> 150:02e0a0aed4ec 379 /**************************************************************************//**
<> 150:02e0a0aed4ec 380 * @defgroup EFM32WG895F128_Peripheral_Base EFM32WG895F128 Peripheral Memory Map
<> 150:02e0a0aed4ec 381 * @{
<> 150:02e0a0aed4ec 382 *****************************************************************************/
<> 150:02e0a0aed4ec 383
<> 150:02e0a0aed4ec 384 #define DMA_BASE (0x400C2000UL) /**< DMA base address */
<> 150:02e0a0aed4ec 385 #define AES_BASE (0x400E0000UL) /**< AES base address */
<> 150:02e0a0aed4ec 386 #define MSC_BASE (0x400C0000UL) /**< MSC base address */
<> 150:02e0a0aed4ec 387 #define EMU_BASE (0x400C6000UL) /**< EMU base address */
<> 150:02e0a0aed4ec 388 #define RMU_BASE (0x400CA000UL) /**< RMU base address */
<> 150:02e0a0aed4ec 389 #define CMU_BASE (0x400C8000UL) /**< CMU base address */
<> 150:02e0a0aed4ec 390 #define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */
<> 150:02e0a0aed4ec 391 #define EBI_BASE (0x40008000UL) /**< EBI base address */
<> 150:02e0a0aed4ec 392 #define FPUEH_BASE (0x400C1C00UL) /**< FPUEH base address */
<> 150:02e0a0aed4ec 393 #define USART0_BASE (0x4000C000UL) /**< USART0 base address */
<> 150:02e0a0aed4ec 394 #define USART1_BASE (0x4000C400UL) /**< USART1 base address */
<> 150:02e0a0aed4ec 395 #define USART2_BASE (0x4000C800UL) /**< USART2 base address */
<> 150:02e0a0aed4ec 396 #define UART0_BASE (0x4000E000UL) /**< UART0 base address */
<> 150:02e0a0aed4ec 397 #define UART1_BASE (0x4000E400UL) /**< UART1 base address */
<> 150:02e0a0aed4ec 398 #define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */
<> 150:02e0a0aed4ec 399 #define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */
<> 150:02e0a0aed4ec 400 #define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */
<> 150:02e0a0aed4ec 401 #define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */
<> 150:02e0a0aed4ec 402 #define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */
<> 150:02e0a0aed4ec 403 #define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */
<> 150:02e0a0aed4ec 404 #define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */
<> 150:02e0a0aed4ec 405 #define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */
<> 150:02e0a0aed4ec 406 #define RTC_BASE (0x40080000UL) /**< RTC base address */
<> 150:02e0a0aed4ec 407 #define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */
<> 150:02e0a0aed4ec 408 #define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */
<> 150:02e0a0aed4ec 409 #define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */
<> 150:02e0a0aed4ec 410 #define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */
<> 150:02e0a0aed4ec 411 #define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */
<> 150:02e0a0aed4ec 412 #define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */
<> 150:02e0a0aed4ec 413 #define GPIO_BASE (0x40006000UL) /**< GPIO base address */
<> 150:02e0a0aed4ec 414 #define VCMP_BASE (0x40000000UL) /**< VCMP base address */
<> 150:02e0a0aed4ec 415 #define PRS_BASE (0x400CC000UL) /**< PRS base address */
<> 150:02e0a0aed4ec 416 #define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
<> 150:02e0a0aed4ec 417 #define DAC0_BASE (0x40004000UL) /**< DAC0 base address */
<> 150:02e0a0aed4ec 418 #define LCD_BASE (0x4008A000UL) /**< LCD base address */
<> 150:02e0a0aed4ec 419 #define BURTC_BASE (0x40081000UL) /**< BURTC base address */
<> 150:02e0a0aed4ec 420 #define WDOG_BASE (0x40088000UL) /**< WDOG base address */
<> 150:02e0a0aed4ec 421 #define ETM_BASE (0xE0041000UL) /**< ETM base address */
<> 150:02e0a0aed4ec 422 #define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */
<> 150:02e0a0aed4ec 423 #define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
<> 150:02e0a0aed4ec 424 #define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
<> 150:02e0a0aed4ec 425 #define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
<> 150:02e0a0aed4ec 426 #define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
<> 150:02e0a0aed4ec 427
<> 150:02e0a0aed4ec 428 /** @} End of group EFM32WG895F128_Peripheral_Base */
<> 150:02e0a0aed4ec 429
<> 150:02e0a0aed4ec 430 /**************************************************************************//**
<> 150:02e0a0aed4ec 431 * @defgroup EFM32WG895F128_Peripheral_Declaration EFM32WG895F128 Peripheral Declarations
<> 150:02e0a0aed4ec 432 * @{
<> 150:02e0a0aed4ec 433 *****************************************************************************/
<> 150:02e0a0aed4ec 434
<> 150:02e0a0aed4ec 435 #define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
<> 150:02e0a0aed4ec 436 #define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
<> 150:02e0a0aed4ec 437 #define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
<> 150:02e0a0aed4ec 438 #define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
<> 150:02e0a0aed4ec 439 #define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
<> 150:02e0a0aed4ec 440 #define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
<> 150:02e0a0aed4ec 441 #define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */
<> 150:02e0a0aed4ec 442 #define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */
<> 150:02e0a0aed4ec 443 #define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */
<> 150:02e0a0aed4ec 444 #define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
<> 150:02e0a0aed4ec 445 #define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
<> 150:02e0a0aed4ec 446 #define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
<> 150:02e0a0aed4ec 447 #define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */
<> 150:02e0a0aed4ec 448 #define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */
<> 150:02e0a0aed4ec 449 #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
<> 150:02e0a0aed4ec 450 #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
<> 150:02e0a0aed4ec 451 #define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
<> 150:02e0a0aed4ec 452 #define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */
<> 150:02e0a0aed4ec 453 #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
<> 150:02e0a0aed4ec 454 #define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
<> 150:02e0a0aed4ec 455 #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
<> 150:02e0a0aed4ec 456 #define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
<> 150:02e0a0aed4ec 457 #define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
<> 150:02e0a0aed4ec 458 #define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
<> 150:02e0a0aed4ec 459 #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
<> 150:02e0a0aed4ec 460 #define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
<> 150:02e0a0aed4ec 461 #define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
<> 150:02e0a0aed4ec 462 #define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
<> 150:02e0a0aed4ec 463 #define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */
<> 150:02e0a0aed4ec 464 #define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
<> 150:02e0a0aed4ec 465 #define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
<> 150:02e0a0aed4ec 466 #define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
<> 150:02e0a0aed4ec 467 #define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
<> 150:02e0a0aed4ec 468 #define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
<> 150:02e0a0aed4ec 469 #define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */
<> 150:02e0a0aed4ec 470 #define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */
<> 150:02e0a0aed4ec 471 #define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
<> 150:02e0a0aed4ec 472 #define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */
<> 150:02e0a0aed4ec 473 #define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
<> 150:02e0a0aed4ec 474 #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
<> 150:02e0a0aed4ec 475 #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
<> 150:02e0a0aed4ec 476
<> 150:02e0a0aed4ec 477 /** @} End of group EFM32WG895F128_Peripheral_Declaration */
<> 150:02e0a0aed4ec 478
<> 150:02e0a0aed4ec 479 /**************************************************************************//**
<> 150:02e0a0aed4ec 480 * @defgroup EFM32WG895F128_BitFields EFM32WG895F128 Bit Fields
<> 150:02e0a0aed4ec 481 * @{
<> 150:02e0a0aed4ec 482 *****************************************************************************/
<> 150:02e0a0aed4ec 483
<> 150:02e0a0aed4ec 484 /**************************************************************************//**
<> 150:02e0a0aed4ec 485 * @addtogroup EFM32WG895F128_PRS_Signals
<> 150:02e0a0aed4ec 486 * @{
<> 150:02e0a0aed4ec 487 * @brief PRS Signal names
<> 150:02e0a0aed4ec 488 *****************************************************************************/
<> 150:02e0a0aed4ec 489 #define PRS_VCMP_OUT ((1 << 16) + 0) /**< PRS Voltage comparator output */
<> 150:02e0a0aed4ec 490 #define PRS_ACMP0_OUT ((2 << 16) + 0) /**< PRS Analog comparator output */
<> 150:02e0a0aed4ec 491 #define PRS_ACMP1_OUT ((3 << 16) + 0) /**< PRS Analog comparator output */
<> 150:02e0a0aed4ec 492 #define PRS_DAC0_CH0 ((6 << 16) + 0) /**< PRS DAC ch0 conversion done */
<> 150:02e0a0aed4ec 493 #define PRS_DAC0_CH1 ((6 << 16) + 1) /**< PRS DAC ch1 conversion done */
<> 150:02e0a0aed4ec 494 #define PRS_ADC0_SINGLE ((8 << 16) + 0) /**< PRS ADC single conversion done */
<> 150:02e0a0aed4ec 495 #define PRS_ADC0_SCAN ((8 << 16) + 1) /**< PRS ADC scan conversion done */
<> 150:02e0a0aed4ec 496 #define PRS_USART0_IRTX ((16 << 16) + 0) /**< PRS USART 0 IRDA out */
<> 150:02e0a0aed4ec 497 #define PRS_USART0_TXC ((16 << 16) + 1) /**< PRS USART 0 TX complete */
<> 150:02e0a0aed4ec 498 #define PRS_USART0_RXDATAV ((16 << 16) + 2) /**< PRS USART 0 RX Data Valid */
<> 150:02e0a0aed4ec 499 #define PRS_USART1_TXC ((17 << 16) + 1) /**< PRS USART 1 TX complete */
<> 150:02e0a0aed4ec 500 #define PRS_USART1_RXDATAV ((17 << 16) + 2) /**< PRS USART 1 RX Data Valid */
<> 150:02e0a0aed4ec 501 #define PRS_USART2_TXC ((18 << 16) + 1) /**< PRS USART 2 TX complete */
<> 150:02e0a0aed4ec 502 #define PRS_USART2_RXDATAV ((18 << 16) + 2) /**< PRS USART 2 RX Data Valid */
<> 150:02e0a0aed4ec 503 #define PRS_TIMER0_UF ((28 << 16) + 0) /**< PRS Timer 0 Underflow */
<> 150:02e0a0aed4ec 504 #define PRS_TIMER0_OF ((28 << 16) + 1) /**< PRS Timer 0 Overflow */
<> 150:02e0a0aed4ec 505 #define PRS_TIMER0_CC0 ((28 << 16) + 2) /**< PRS Timer 0 Compare/Capture 0 */
<> 150:02e0a0aed4ec 506 #define PRS_TIMER0_CC1 ((28 << 16) + 3) /**< PRS Timer 0 Compare/Capture 1 */
<> 150:02e0a0aed4ec 507 #define PRS_TIMER0_CC2 ((28 << 16) + 4) /**< PRS Timer 0 Compare/Capture 2 */
<> 150:02e0a0aed4ec 508 #define PRS_TIMER1_UF ((29 << 16) + 0) /**< PRS Timer 1 Underflow */
<> 150:02e0a0aed4ec 509 #define PRS_TIMER1_OF ((29 << 16) + 1) /**< PRS Timer 1 Overflow */
<> 150:02e0a0aed4ec 510 #define PRS_TIMER1_CC0 ((29 << 16) + 2) /**< PRS Timer 1 Compare/Capture 0 */
<> 150:02e0a0aed4ec 511 #define PRS_TIMER1_CC1 ((29 << 16) + 3) /**< PRS Timer 1 Compare/Capture 1 */
<> 150:02e0a0aed4ec 512 #define PRS_TIMER1_CC2 ((29 << 16) + 4) /**< PRS Timer 1 Compare/Capture 2 */
<> 150:02e0a0aed4ec 513 #define PRS_TIMER2_UF ((30 << 16) + 0) /**< PRS Timer 2 Underflow */
<> 150:02e0a0aed4ec 514 #define PRS_TIMER2_OF ((30 << 16) + 1) /**< PRS Timer 2 Overflow */
<> 150:02e0a0aed4ec 515 #define PRS_TIMER2_CC0 ((30 << 16) + 2) /**< PRS Timer 2 Compare/Capture 0 */
<> 150:02e0a0aed4ec 516 #define PRS_TIMER2_CC1 ((30 << 16) + 3) /**< PRS Timer 2 Compare/Capture 1 */
<> 150:02e0a0aed4ec 517 #define PRS_TIMER2_CC2 ((30 << 16) + 4) /**< PRS Timer 2 Compare/Capture 2 */
<> 150:02e0a0aed4ec 518 #define PRS_TIMER3_UF ((31 << 16) + 0) /**< PRS Timer 3 Underflow */
<> 150:02e0a0aed4ec 519 #define PRS_TIMER3_OF ((31 << 16) + 1) /**< PRS Timer 3 Overflow */
<> 150:02e0a0aed4ec 520 #define PRS_TIMER3_CC0 ((31 << 16) + 2) /**< PRS Timer 3 Compare/Capture 0 */
<> 150:02e0a0aed4ec 521 #define PRS_TIMER3_CC1 ((31 << 16) + 3) /**< PRS Timer 3 Compare/Capture 1 */
<> 150:02e0a0aed4ec 522 #define PRS_TIMER3_CC2 ((31 << 16) + 4) /**< PRS Timer 3 Compare/Capture 2 */
<> 150:02e0a0aed4ec 523 #define PRS_RTC_OF ((40 << 16) + 0) /**< PRS RTC Overflow */
<> 150:02e0a0aed4ec 524 #define PRS_RTC_COMP0 ((40 << 16) + 1) /**< PRS RTC Compare 0 */
<> 150:02e0a0aed4ec 525 #define PRS_RTC_COMP1 ((40 << 16) + 2) /**< PRS RTC Compare 1 */
<> 150:02e0a0aed4ec 526 #define PRS_UART0_TXC ((41 << 16) + 1) /**< PRS USART 0 TX complete */
<> 150:02e0a0aed4ec 527 #define PRS_UART0_RXDATAV ((41 << 16) + 2) /**< PRS USART 0 RX Data Valid */
<> 150:02e0a0aed4ec 528 #define PRS_UART1_TXC ((42 << 16) + 1) /**< PRS USART 0 TX complete */
<> 150:02e0a0aed4ec 529 #define PRS_UART1_RXDATAV ((42 << 16) + 2) /**< PRS USART 0 RX Data Valid */
<> 150:02e0a0aed4ec 530 #define PRS_GPIO_PIN0 ((48 << 16) + 0) /**< PRS GPIO pin 0 */
<> 150:02e0a0aed4ec 531 #define PRS_GPIO_PIN1 ((48 << 16) + 1) /**< PRS GPIO pin 1 */
<> 150:02e0a0aed4ec 532 #define PRS_GPIO_PIN2 ((48 << 16) + 2) /**< PRS GPIO pin 2 */
<> 150:02e0a0aed4ec 533 #define PRS_GPIO_PIN3 ((48 << 16) + 3) /**< PRS GPIO pin 3 */
<> 150:02e0a0aed4ec 534 #define PRS_GPIO_PIN4 ((48 << 16) + 4) /**< PRS GPIO pin 4 */
<> 150:02e0a0aed4ec 535 #define PRS_GPIO_PIN5 ((48 << 16) + 5) /**< PRS GPIO pin 5 */
<> 150:02e0a0aed4ec 536 #define PRS_GPIO_PIN6 ((48 << 16) + 6) /**< PRS GPIO pin 6 */
<> 150:02e0a0aed4ec 537 #define PRS_GPIO_PIN7 ((48 << 16) + 7) /**< PRS GPIO pin 7 */
<> 150:02e0a0aed4ec 538 #define PRS_GPIO_PIN8 ((49 << 16) + 0) /**< PRS GPIO pin 8 */
<> 150:02e0a0aed4ec 539 #define PRS_GPIO_PIN9 ((49 << 16) + 1) /**< PRS GPIO pin 9 */
<> 150:02e0a0aed4ec 540 #define PRS_GPIO_PIN10 ((49 << 16) + 2) /**< PRS GPIO pin 10 */
<> 150:02e0a0aed4ec 541 #define PRS_GPIO_PIN11 ((49 << 16) + 3) /**< PRS GPIO pin 11 */
<> 150:02e0a0aed4ec 542 #define PRS_GPIO_PIN12 ((49 << 16) + 4) /**< PRS GPIO pin 12 */
<> 150:02e0a0aed4ec 543 #define PRS_GPIO_PIN13 ((49 << 16) + 5) /**< PRS GPIO pin 13 */
<> 150:02e0a0aed4ec 544 #define PRS_GPIO_PIN14 ((49 << 16) + 6) /**< PRS GPIO pin 14 */
<> 150:02e0a0aed4ec 545 #define PRS_GPIO_PIN15 ((49 << 16) + 7) /**< PRS GPIO pin 15 */
<> 150:02e0a0aed4ec 546 #define PRS_LETIMER0_CH0 ((52 << 16) + 0) /**< PRS LETIMER CH0 Out */
<> 150:02e0a0aed4ec 547 #define PRS_LETIMER0_CH1 ((52 << 16) + 1) /**< PRS LETIMER CH1 Out */
<> 150:02e0a0aed4ec 548 #define PRS_BURTC_OF ((55 << 16) + 0) /**< PRS BURTC Overflow */
<> 150:02e0a0aed4ec 549 #define PRS_BURTC_COMP0 ((55 << 16) + 1) /**< PRS BURTC Compare 0 */
<> 150:02e0a0aed4ec 550 #define PRS_LESENSE_SCANRES0 ((57 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 0 */
<> 150:02e0a0aed4ec 551 #define PRS_LESENSE_SCANRES1 ((57 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 1 */
<> 150:02e0a0aed4ec 552 #define PRS_LESENSE_SCANRES2 ((57 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 2 */
<> 150:02e0a0aed4ec 553 #define PRS_LESENSE_SCANRES3 ((57 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 3 */
<> 150:02e0a0aed4ec 554 #define PRS_LESENSE_SCANRES4 ((57 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 4 */
<> 150:02e0a0aed4ec 555 #define PRS_LESENSE_SCANRES5 ((57 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 5 */
<> 150:02e0a0aed4ec 556 #define PRS_LESENSE_SCANRES6 ((57 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 6 */
<> 150:02e0a0aed4ec 557 #define PRS_LESENSE_SCANRES7 ((57 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 7 */
<> 150:02e0a0aed4ec 558 #define PRS_LESENSE_SCANRES8 ((58 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 8 */
<> 150:02e0a0aed4ec 559 #define PRS_LESENSE_SCANRES9 ((58 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 9 */
<> 150:02e0a0aed4ec 560 #define PRS_LESENSE_SCANRES10 ((58 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 10 */
<> 150:02e0a0aed4ec 561 #define PRS_LESENSE_SCANRES11 ((58 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 11 */
<> 150:02e0a0aed4ec 562 #define PRS_LESENSE_SCANRES12 ((58 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 12 */
<> 150:02e0a0aed4ec 563 #define PRS_LESENSE_SCANRES13 ((58 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 13 */
<> 150:02e0a0aed4ec 564 #define PRS_LESENSE_SCANRES14 ((58 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 14 */
<> 150:02e0a0aed4ec 565 #define PRS_LESENSE_SCANRES15 ((58 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 15 */
<> 150:02e0a0aed4ec 566 #define PRS_LESENSE_DEC0 ((59 << 16) + 0) /**< PRS LESENSE Decoder PRS out 0 */
<> 150:02e0a0aed4ec 567 #define PRS_LESENSE_DEC1 ((59 << 16) + 1) /**< PRS LESENSE Decoder PRS out 1 */
<> 150:02e0a0aed4ec 568 #define PRS_LESENSE_DEC2 ((59 << 16) + 2) /**< PRS LESENSE Decoder PRS out 2 */
<> 150:02e0a0aed4ec 569
<> 150:02e0a0aed4ec 570 /** @} End of group EFM32WG895F128_PRS */
<> 150:02e0a0aed4ec 571
<> 150:02e0a0aed4ec 572 #include "efm32wg_dmareq.h"
<> 150:02e0a0aed4ec 573 #include "efm32wg_dmactrl.h"
<> 150:02e0a0aed4ec 574 #include "efm32wg_uart.h"
<> 150:02e0a0aed4ec 575
<> 150:02e0a0aed4ec 576 /**************************************************************************//**
<> 150:02e0a0aed4ec 577 * @defgroup EFM32WG895F128_CMU_BitFields EFM32WG895F128_CMU Bit Fields
<> 150:02e0a0aed4ec 578 * @{
<> 150:02e0a0aed4ec 579 *****************************************************************************/
<> 150:02e0a0aed4ec 580
<> 150:02e0a0aed4ec 581 /* Bit fields for CMU CTRL */
<> 150:02e0a0aed4ec 582 #define _CMU_CTRL_RESETVALUE 0x000C262CUL /**< Default value for CMU_CTRL */
<> 150:02e0a0aed4ec 583 #define _CMU_CTRL_MASK 0x57FFFEEFUL /**< Mask for CMU_CTRL */
<> 150:02e0a0aed4ec 584 #define _CMU_CTRL_HFXOMODE_SHIFT 0 /**< Shift value for CMU_HFXOMODE */
<> 150:02e0a0aed4ec 585 #define _CMU_CTRL_HFXOMODE_MASK 0x3UL /**< Bit mask for CMU_HFXOMODE */
<> 150:02e0a0aed4ec 586 #define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 587 #define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */
<> 150:02e0a0aed4ec 588 #define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */
<> 150:02e0a0aed4ec 589 #define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */
<> 150:02e0a0aed4ec 590 #define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 591 #define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0) /**< Shifted mode XTAL for CMU_CTRL */
<> 150:02e0a0aed4ec 592 #define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0) /**< Shifted mode BUFEXTCLK for CMU_CTRL */
<> 150:02e0a0aed4ec 593 #define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_CTRL */
<> 150:02e0a0aed4ec 594 #define _CMU_CTRL_HFXOBOOST_SHIFT 2 /**< Shift value for CMU_HFXOBOOST */
<> 150:02e0a0aed4ec 595 #define _CMU_CTRL_HFXOBOOST_MASK 0xCUL /**< Bit mask for CMU_HFXOBOOST */
<> 150:02e0a0aed4ec 596 #define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL /**< Mode 50PCENT for CMU_CTRL */
<> 150:02e0a0aed4ec 597 #define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL /**< Mode 70PCENT for CMU_CTRL */
<> 150:02e0a0aed4ec 598 #define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL /**< Mode 80PCENT for CMU_CTRL */
<> 150:02e0a0aed4ec 599 #define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 600 #define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL /**< Mode 100PCENT for CMU_CTRL */
<> 150:02e0a0aed4ec 601 #define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2) /**< Shifted mode 50PCENT for CMU_CTRL */
<> 150:02e0a0aed4ec 602 #define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2) /**< Shifted mode 70PCENT for CMU_CTRL */
<> 150:02e0a0aed4ec 603 #define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2) /**< Shifted mode 80PCENT for CMU_CTRL */
<> 150:02e0a0aed4ec 604 #define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 605 #define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2) /**< Shifted mode 100PCENT for CMU_CTRL */
<> 150:02e0a0aed4ec 606 #define _CMU_CTRL_HFXOBUFCUR_SHIFT 5 /**< Shift value for CMU_HFXOBUFCUR */
<> 150:02e0a0aed4ec 607 #define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL /**< Bit mask for CMU_HFXOBUFCUR */
<> 150:02e0a0aed4ec 608 #define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 609 #define _CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ 0x00000001UL /**< Mode BOOSTUPTO32MHZ for CMU_CTRL */
<> 150:02e0a0aed4ec 610 #define _CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ 0x00000003UL /**< Mode BOOSTABOVE32MHZ for CMU_CTRL */
<> 150:02e0a0aed4ec 611 #define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 612 #define CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ << 5) /**< Shifted mode BOOSTUPTO32MHZ for CMU_CTRL */
<> 150:02e0a0aed4ec 613 #define CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ << 5) /**< Shifted mode BOOSTABOVE32MHZ for CMU_CTRL */
<> 150:02e0a0aed4ec 614 #define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7) /**< HFXO Glitch Detector Enable */
<> 150:02e0a0aed4ec 615 #define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7 /**< Shift value for CMU_HFXOGLITCHDETEN */
<> 150:02e0a0aed4ec 616 #define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL /**< Bit mask for CMU_HFXOGLITCHDETEN */
<> 150:02e0a0aed4ec 617 #define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 618 #define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 619 #define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9 /**< Shift value for CMU_HFXOTIMEOUT */
<> 150:02e0a0aed4ec 620 #define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL /**< Bit mask for CMU_HFXOTIMEOUT */
<> 150:02e0a0aed4ec 621 #define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */
<> 150:02e0a0aed4ec 622 #define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_CTRL */
<> 150:02e0a0aed4ec 623 #define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_CTRL */
<> 150:02e0a0aed4ec 624 #define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 625 #define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL /**< Mode 16KCYCLES for CMU_CTRL */
<> 150:02e0a0aed4ec 626 #define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9) /**< Shifted mode 8CYCLES for CMU_CTRL */
<> 150:02e0a0aed4ec 627 #define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9) /**< Shifted mode 256CYCLES for CMU_CTRL */
<> 150:02e0a0aed4ec 628 #define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9) /**< Shifted mode 1KCYCLES for CMU_CTRL */
<> 150:02e0a0aed4ec 629 #define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 630 #define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9) /**< Shifted mode 16KCYCLES for CMU_CTRL */
<> 150:02e0a0aed4ec 631 #define _CMU_CTRL_LFXOMODE_SHIFT 11 /**< Shift value for CMU_LFXOMODE */
<> 150:02e0a0aed4ec 632 #define _CMU_CTRL_LFXOMODE_MASK 0x1800UL /**< Bit mask for CMU_LFXOMODE */
<> 150:02e0a0aed4ec 633 #define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 634 #define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */
<> 150:02e0a0aed4ec 635 #define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */
<> 150:02e0a0aed4ec 636 #define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */
<> 150:02e0a0aed4ec 637 #define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 638 #define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11) /**< Shifted mode XTAL for CMU_CTRL */
<> 150:02e0a0aed4ec 639 #define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11) /**< Shifted mode BUFEXTCLK for CMU_CTRL */
<> 150:02e0a0aed4ec 640 #define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11) /**< Shifted mode DIGEXTCLK for CMU_CTRL */
<> 150:02e0a0aed4ec 641 #define CMU_CTRL_LFXOBOOST (0x1UL << 13) /**< LFXO Start-up Boost Current */
<> 150:02e0a0aed4ec 642 #define _CMU_CTRL_LFXOBOOST_SHIFT 13 /**< Shift value for CMU_LFXOBOOST */
<> 150:02e0a0aed4ec 643 #define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL /**< Bit mask for CMU_LFXOBOOST */
<> 150:02e0a0aed4ec 644 #define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL /**< Mode 70PCENT for CMU_CTRL */
<> 150:02e0a0aed4ec 645 #define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 646 #define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL /**< Mode 100PCENT for CMU_CTRL */
<> 150:02e0a0aed4ec 647 #define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13) /**< Shifted mode 70PCENT for CMU_CTRL */
<> 150:02e0a0aed4ec 648 #define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 649 #define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13) /**< Shifted mode 100PCENT for CMU_CTRL */
<> 150:02e0a0aed4ec 650 #define _CMU_CTRL_HFCLKDIV_SHIFT 14 /**< Shift value for CMU_HFCLKDIV */
<> 150:02e0a0aed4ec 651 #define _CMU_CTRL_HFCLKDIV_MASK 0x1C000UL /**< Bit mask for CMU_HFCLKDIV */
<> 150:02e0a0aed4ec 652 #define _CMU_CTRL_HFCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 653 #define CMU_CTRL_HFCLKDIV_DEFAULT (_CMU_CTRL_HFCLKDIV_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 654 #define CMU_CTRL_LFXOBUFCUR (0x1UL << 17) /**< LFXO Boost Buffer Current */
<> 150:02e0a0aed4ec 655 #define _CMU_CTRL_LFXOBUFCUR_SHIFT 17 /**< Shift value for CMU_LFXOBUFCUR */
<> 150:02e0a0aed4ec 656 #define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL /**< Bit mask for CMU_LFXOBUFCUR */
<> 150:02e0a0aed4ec 657 #define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 658 #define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 659 #define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18 /**< Shift value for CMU_LFXOTIMEOUT */
<> 150:02e0a0aed4ec 660 #define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL /**< Bit mask for CMU_LFXOTIMEOUT */
<> 150:02e0a0aed4ec 661 #define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */
<> 150:02e0a0aed4ec 662 #define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL /**< Mode 1KCYCLES for CMU_CTRL */
<> 150:02e0a0aed4ec 663 #define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL /**< Mode 16KCYCLES for CMU_CTRL */
<> 150:02e0a0aed4ec 664 #define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 665 #define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL /**< Mode 32KCYCLES for CMU_CTRL */
<> 150:02e0a0aed4ec 666 #define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18) /**< Shifted mode 8CYCLES for CMU_CTRL */
<> 150:02e0a0aed4ec 667 #define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18) /**< Shifted mode 1KCYCLES for CMU_CTRL */
<> 150:02e0a0aed4ec 668 #define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18) /**< Shifted mode 16KCYCLES for CMU_CTRL */
<> 150:02e0a0aed4ec 669 #define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 670 #define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18) /**< Shifted mode 32KCYCLES for CMU_CTRL */
<> 150:02e0a0aed4ec 671 #define _CMU_CTRL_CLKOUTSEL0_SHIFT 20 /**< Shift value for CMU_CLKOUTSEL0 */
<> 150:02e0a0aed4ec 672 #define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL /**< Bit mask for CMU_CLKOUTSEL0 */
<> 150:02e0a0aed4ec 673 #define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 674 #define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL /**< Mode HFRCO for CMU_CTRL */
<> 150:02e0a0aed4ec 675 #define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL /**< Mode HFXO for CMU_CTRL */
<> 150:02e0a0aed4ec 676 #define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL /**< Mode HFCLK2 for CMU_CTRL */
<> 150:02e0a0aed4ec 677 #define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL /**< Mode HFCLK4 for CMU_CTRL */
<> 150:02e0a0aed4ec 678 #define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL /**< Mode HFCLK8 for CMU_CTRL */
<> 150:02e0a0aed4ec 679 #define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL /**< Mode HFCLK16 for CMU_CTRL */
<> 150:02e0a0aed4ec 680 #define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL /**< Mode ULFRCO for CMU_CTRL */
<> 150:02e0a0aed4ec 681 #define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL /**< Mode AUXHFRCO for CMU_CTRL */
<> 150:02e0a0aed4ec 682 #define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 683 #define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20) /**< Shifted mode HFRCO for CMU_CTRL */
<> 150:02e0a0aed4ec 684 #define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20) /**< Shifted mode HFXO for CMU_CTRL */
<> 150:02e0a0aed4ec 685 #define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20) /**< Shifted mode HFCLK2 for CMU_CTRL */
<> 150:02e0a0aed4ec 686 #define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20) /**< Shifted mode HFCLK4 for CMU_CTRL */
<> 150:02e0a0aed4ec 687 #define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20) /**< Shifted mode HFCLK8 for CMU_CTRL */
<> 150:02e0a0aed4ec 688 #define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20) /**< Shifted mode HFCLK16 for CMU_CTRL */
<> 150:02e0a0aed4ec 689 #define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_CTRL */
<> 150:02e0a0aed4ec 690 #define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_CTRL */
<> 150:02e0a0aed4ec 691 #define _CMU_CTRL_CLKOUTSEL1_SHIFT 23 /**< Shift value for CMU_CLKOUTSEL1 */
<> 150:02e0a0aed4ec 692 #define _CMU_CTRL_CLKOUTSEL1_MASK 0x7800000UL /**< Bit mask for CMU_CLKOUTSEL1 */
<> 150:02e0a0aed4ec 693 #define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 694 #define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL /**< Mode LFRCO for CMU_CTRL */
<> 150:02e0a0aed4ec 695 #define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL /**< Mode LFXO for CMU_CTRL */
<> 150:02e0a0aed4ec 696 #define _CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL /**< Mode HFCLK for CMU_CTRL */
<> 150:02e0a0aed4ec 697 #define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL /**< Mode LFXOQ for CMU_CTRL */
<> 150:02e0a0aed4ec 698 #define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL /**< Mode HFXOQ for CMU_CTRL */
<> 150:02e0a0aed4ec 699 #define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL /**< Mode LFRCOQ for CMU_CTRL */
<> 150:02e0a0aed4ec 700 #define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL /**< Mode HFRCOQ for CMU_CTRL */
<> 150:02e0a0aed4ec 701 #define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL /**< Mode AUXHFRCOQ for CMU_CTRL */
<> 150:02e0a0aed4ec 702 #define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 703 #define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23) /**< Shifted mode LFRCO for CMU_CTRL */
<> 150:02e0a0aed4ec 704 #define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23) /**< Shifted mode LFXO for CMU_CTRL */
<> 150:02e0a0aed4ec 705 #define CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23) /**< Shifted mode HFCLK for CMU_CTRL */
<> 150:02e0a0aed4ec 706 #define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23) /**< Shifted mode LFXOQ for CMU_CTRL */
<> 150:02e0a0aed4ec 707 #define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23) /**< Shifted mode HFXOQ for CMU_CTRL */
<> 150:02e0a0aed4ec 708 #define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23) /**< Shifted mode LFRCOQ for CMU_CTRL */
<> 150:02e0a0aed4ec 709 #define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23) /**< Shifted mode HFRCOQ for CMU_CTRL */
<> 150:02e0a0aed4ec 710 #define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */
<> 150:02e0a0aed4ec 711 #define CMU_CTRL_DBGCLK (0x1UL << 28) /**< Debug Clock */
<> 150:02e0a0aed4ec 712 #define _CMU_CTRL_DBGCLK_SHIFT 28 /**< Shift value for CMU_DBGCLK */
<> 150:02e0a0aed4ec 713 #define _CMU_CTRL_DBGCLK_MASK 0x10000000UL /**< Bit mask for CMU_DBGCLK */
<> 150:02e0a0aed4ec 714 #define _CMU_CTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 715 #define _CMU_CTRL_DBGCLK_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_CTRL */
<> 150:02e0a0aed4ec 716 #define _CMU_CTRL_DBGCLK_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_CTRL */
<> 150:02e0a0aed4ec 717 #define CMU_CTRL_DBGCLK_DEFAULT (_CMU_CTRL_DBGCLK_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 718 #define CMU_CTRL_DBGCLK_AUXHFRCO (_CMU_CTRL_DBGCLK_AUXHFRCO << 28) /**< Shifted mode AUXHFRCO for CMU_CTRL */
<> 150:02e0a0aed4ec 719 #define CMU_CTRL_DBGCLK_HFCLK (_CMU_CTRL_DBGCLK_HFCLK << 28) /**< Shifted mode HFCLK for CMU_CTRL */
<> 150:02e0a0aed4ec 720 #define CMU_CTRL_HFLE (0x1UL << 30) /**< High-Frequency LE Interface */
<> 150:02e0a0aed4ec 721 #define _CMU_CTRL_HFLE_SHIFT 30 /**< Shift value for CMU_HFLE */
<> 150:02e0a0aed4ec 722 #define _CMU_CTRL_HFLE_MASK 0x40000000UL /**< Bit mask for CMU_HFLE */
<> 150:02e0a0aed4ec 723 #define _CMU_CTRL_HFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 724 #define CMU_CTRL_HFLE_DEFAULT (_CMU_CTRL_HFLE_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 725
<> 150:02e0a0aed4ec 726 /* Bit fields for CMU HFCORECLKDIV */
<> 150:02e0a0aed4ec 727 #define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 728 #define _CMU_HFCORECLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 729 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0 /**< Shift value for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 730 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 731 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 732 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 733 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 734 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 735 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 736 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 737 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 738 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 739 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 740 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 741 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 742 #define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 743 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 744 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 745 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 746 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 747 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 748 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 749 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 750 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 751 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 752 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 753 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV (0x1UL << 8) /**< Additional Division Factor For HFCORECLKLE */
<> 150:02e0a0aed4ec 754 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT 8 /**< Shift value for CMU_HFCORECLKLEDIV */
<> 150:02e0a0aed4ec 755 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK 0x100UL /**< Bit mask for CMU_HFCORECLKLEDIV */
<> 150:02e0a0aed4ec 756 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 757 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 758 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 759 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 760 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8) /**< Shifted mode DIV2 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 761 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8) /**< Shifted mode DIV4 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 762
<> 150:02e0a0aed4ec 763 /* Bit fields for CMU HFPERCLKDIV */
<> 150:02e0a0aed4ec 764 #define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL /**< Default value for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 765 #define _CMU_HFPERCLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 766 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0 /**< Shift value for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 767 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 768 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 769 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 770 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 771 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 772 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 773 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 774 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 775 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 776 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 777 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 778 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 779 #define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 780 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 781 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 782 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 783 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 784 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 785 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 786 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 787 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 788 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 789 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 790 #define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8) /**< HFPERCLK Enable */
<> 150:02e0a0aed4ec 791 #define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8 /**< Shift value for CMU_HFPERCLKEN */
<> 150:02e0a0aed4ec 792 #define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL /**< Bit mask for CMU_HFPERCLKEN */
<> 150:02e0a0aed4ec 793 #define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 794 #define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 795
<> 150:02e0a0aed4ec 796 /* Bit fields for CMU HFRCOCTRL */
<> 150:02e0a0aed4ec 797 #define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL /**< Default value for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 798 #define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL /**< Mask for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 799 #define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */
<> 150:02e0a0aed4ec 800 #define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */
<> 150:02e0a0aed4ec 801 #define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 802 #define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 803 #define _CMU_HFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */
<> 150:02e0a0aed4ec 804 #define _CMU_HFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */
<> 150:02e0a0aed4ec 805 #define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL /**< Mode 1MHZ for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 806 #define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL /**< Mode 7MHZ for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 807 #define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL /**< Mode 11MHZ for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 808 #define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 809 #define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL /**< Mode 14MHZ for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 810 #define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL /**< Mode 21MHZ for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 811 #define _CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL /**< Mode 28MHZ for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 812 #define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 813 #define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 814 #define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 815 #define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 816 #define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 817 #define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 818 #define CMU_HFRCOCTRL_BAND_28MHZ (_CMU_HFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 819 #define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12 /**< Shift value for CMU_SUDELAY */
<> 150:02e0a0aed4ec 820 #define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL /**< Bit mask for CMU_SUDELAY */
<> 150:02e0a0aed4ec 821 #define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 822 #define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 823
<> 150:02e0a0aed4ec 824 /* Bit fields for CMU LFRCOCTRL */
<> 150:02e0a0aed4ec 825 #define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL /**< Default value for CMU_LFRCOCTRL */
<> 150:02e0a0aed4ec 826 #define _CMU_LFRCOCTRL_MASK 0x0000007FUL /**< Mask for CMU_LFRCOCTRL */
<> 150:02e0a0aed4ec 827 #define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */
<> 150:02e0a0aed4ec 828 #define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */
<> 150:02e0a0aed4ec 829 #define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL /**< Mode DEFAULT for CMU_LFRCOCTRL */
<> 150:02e0a0aed4ec 830 #define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */
<> 150:02e0a0aed4ec 831
<> 150:02e0a0aed4ec 832 /* Bit fields for CMU AUXHFRCOCTRL */
<> 150:02e0a0aed4ec 833 #define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL /**< Default value for CMU_AUXHFRCOCTRL */
<> 150:02e0a0aed4ec 834 #define _CMU_AUXHFRCOCTRL_MASK 0x000007FFUL /**< Mask for CMU_AUXHFRCOCTRL */
<> 150:02e0a0aed4ec 835 #define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */
<> 150:02e0a0aed4ec 836 #define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */
<> 150:02e0a0aed4ec 837 #define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
<> 150:02e0a0aed4ec 838 #define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
<> 150:02e0a0aed4ec 839 #define _CMU_AUXHFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */
<> 150:02e0a0aed4ec 840 #define _CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */
<> 150:02e0a0aed4ec 841 #define _CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
<> 150:02e0a0aed4ec 842 #define _CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL /**< Mode 14MHZ for CMU_AUXHFRCOCTRL */
<> 150:02e0a0aed4ec 843 #define _CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL /**< Mode 11MHZ for CMU_AUXHFRCOCTRL */
<> 150:02e0a0aed4ec 844 #define _CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL /**< Mode 7MHZ for CMU_AUXHFRCOCTRL */
<> 150:02e0a0aed4ec 845 #define _CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL /**< Mode 1MHZ for CMU_AUXHFRCOCTRL */
<> 150:02e0a0aed4ec 846 #define _CMU_AUXHFRCOCTRL_BAND_28MHZ 0x00000006UL /**< Mode 28MHZ for CMU_AUXHFRCOCTRL */
<> 150:02e0a0aed4ec 847 #define _CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL /**< Mode 21MHZ for CMU_AUXHFRCOCTRL */
<> 150:02e0a0aed4ec 848 #define CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
<> 150:02e0a0aed4ec 849 #define CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_AUXHFRCOCTRL */
<> 150:02e0a0aed4ec 850 #define CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_AUXHFRCOCTRL */
<> 150:02e0a0aed4ec 851 #define CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_AUXHFRCOCTRL */
<> 150:02e0a0aed4ec 852 #define CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_AUXHFRCOCTRL */
<> 150:02e0a0aed4ec 853 #define CMU_AUXHFRCOCTRL_BAND_28MHZ (_CMU_AUXHFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_AUXHFRCOCTRL */
<> 150:02e0a0aed4ec 854 #define CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_AUXHFRCOCTRL */
<> 150:02e0a0aed4ec 855
<> 150:02e0a0aed4ec 856 /* Bit fields for CMU CALCTRL */
<> 150:02e0a0aed4ec 857 #define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */
<> 150:02e0a0aed4ec 858 #define _CMU_CALCTRL_MASK 0x0000007FUL /**< Mask for CMU_CALCTRL */
<> 150:02e0a0aed4ec 859 #define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */
<> 150:02e0a0aed4ec 860 #define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */
<> 150:02e0a0aed4ec 861 #define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */
<> 150:02e0a0aed4ec 862 #define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 863 #define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 864 #define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 865 #define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 866 #define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 867 #define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */
<> 150:02e0a0aed4ec 868 #define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 869 #define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 870 #define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 871 #define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 872 #define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 873 #define _CMU_CALCTRL_DOWNSEL_SHIFT 3 /**< Shift value for CMU_DOWNSEL */
<> 150:02e0a0aed4ec 874 #define _CMU_CALCTRL_DOWNSEL_MASK 0x38UL /**< Bit mask for CMU_DOWNSEL */
<> 150:02e0a0aed4ec 875 #define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */
<> 150:02e0a0aed4ec 876 #define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */
<> 150:02e0a0aed4ec 877 #define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 878 #define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 879 #define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 880 #define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 881 #define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 882 #define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CALCTRL */
<> 150:02e0a0aed4ec 883 #define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3) /**< Shifted mode HFCLK for CMU_CALCTRL */
<> 150:02e0a0aed4ec 884 #define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 885 #define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 886 #define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3) /**< Shifted mode HFRCO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 887 #define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3) /**< Shifted mode LFRCO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 888 #define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 889 #define CMU_CALCTRL_CONT (0x1UL << 6) /**< Continuous Calibration */
<> 150:02e0a0aed4ec 890 #define _CMU_CALCTRL_CONT_SHIFT 6 /**< Shift value for CMU_CONT */
<> 150:02e0a0aed4ec 891 #define _CMU_CALCTRL_CONT_MASK 0x40UL /**< Bit mask for CMU_CONT */
<> 150:02e0a0aed4ec 892 #define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */
<> 150:02e0a0aed4ec 893 #define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CALCTRL */
<> 150:02e0a0aed4ec 894
<> 150:02e0a0aed4ec 895 /* Bit fields for CMU CALCNT */
<> 150:02e0a0aed4ec 896 #define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */
<> 150:02e0a0aed4ec 897 #define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */
<> 150:02e0a0aed4ec 898 #define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */
<> 150:02e0a0aed4ec 899 #define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */
<> 150:02e0a0aed4ec 900 #define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */
<> 150:02e0a0aed4ec 901 #define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */
<> 150:02e0a0aed4ec 902
<> 150:02e0a0aed4ec 903 /* Bit fields for CMU OSCENCMD */
<> 150:02e0a0aed4ec 904 #define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 905 #define _CMU_OSCENCMD_MASK 0x000003FFUL /**< Mask for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 906 #define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */
<> 150:02e0a0aed4ec 907 #define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */
<> 150:02e0a0aed4ec 908 #define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */
<> 150:02e0a0aed4ec 909 #define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 910 #define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 911 #define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */
<> 150:02e0a0aed4ec 912 #define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */
<> 150:02e0a0aed4ec 913 #define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */
<> 150:02e0a0aed4ec 914 #define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 915 #define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 916 #define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */
<> 150:02e0a0aed4ec 917 #define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */
<> 150:02e0a0aed4ec 918 #define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */
<> 150:02e0a0aed4ec 919 #define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 920 #define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 921 #define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */
<> 150:02e0a0aed4ec 922 #define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */
<> 150:02e0a0aed4ec 923 #define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */
<> 150:02e0a0aed4ec 924 #define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 925 #define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 926 #define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */
<> 150:02e0a0aed4ec 927 #define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */
<> 150:02e0a0aed4ec 928 #define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */
<> 150:02e0a0aed4ec 929 #define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 930 #define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 931 #define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */
<> 150:02e0a0aed4ec 932 #define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */
<> 150:02e0a0aed4ec 933 #define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */
<> 150:02e0a0aed4ec 934 #define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 935 #define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 936 #define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */
<> 150:02e0a0aed4ec 937 #define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */
<> 150:02e0a0aed4ec 938 #define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */
<> 150:02e0a0aed4ec 939 #define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 940 #define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 941 #define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */
<> 150:02e0a0aed4ec 942 #define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */
<> 150:02e0a0aed4ec 943 #define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */
<> 150:02e0a0aed4ec 944 #define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 945 #define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 946 #define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */
<> 150:02e0a0aed4ec 947 #define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */
<> 150:02e0a0aed4ec 948 #define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */
<> 150:02e0a0aed4ec 949 #define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 950 #define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 951 #define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */
<> 150:02e0a0aed4ec 952 #define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */
<> 150:02e0a0aed4ec 953 #define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */
<> 150:02e0a0aed4ec 954 #define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 955 #define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 956
<> 150:02e0a0aed4ec 957 /* Bit fields for CMU CMD */
<> 150:02e0a0aed4ec 958 #define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */
<> 150:02e0a0aed4ec 959 #define _CMU_CMD_MASK 0x0000001FUL /**< Mask for CMU_CMD */
<> 150:02e0a0aed4ec 960 #define _CMU_CMD_HFCLKSEL_SHIFT 0 /**< Shift value for CMU_HFCLKSEL */
<> 150:02e0a0aed4ec 961 #define _CMU_CMD_HFCLKSEL_MASK 0x7UL /**< Bit mask for CMU_HFCLKSEL */
<> 150:02e0a0aed4ec 962 #define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */
<> 150:02e0a0aed4ec 963 #define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_CMD */
<> 150:02e0a0aed4ec 964 #define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CMD */
<> 150:02e0a0aed4ec 965 #define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */
<> 150:02e0a0aed4ec 966 #define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CMD */
<> 150:02e0a0aed4ec 967 #define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */
<> 150:02e0a0aed4ec 968 #define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CMD */
<> 150:02e0a0aed4ec 969 #define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CMD */
<> 150:02e0a0aed4ec 970 #define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CMD */
<> 150:02e0a0aed4ec 971 #define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CMD */
<> 150:02e0a0aed4ec 972 #define CMU_CMD_CALSTART (0x1UL << 3) /**< Calibration Start */
<> 150:02e0a0aed4ec 973 #define _CMU_CMD_CALSTART_SHIFT 3 /**< Shift value for CMU_CALSTART */
<> 150:02e0a0aed4ec 974 #define _CMU_CMD_CALSTART_MASK 0x8UL /**< Bit mask for CMU_CALSTART */
<> 150:02e0a0aed4ec 975 #define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */
<> 150:02e0a0aed4ec 976 #define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CMD */
<> 150:02e0a0aed4ec 977 #define CMU_CMD_CALSTOP (0x1UL << 4) /**< Calibration Stop */
<> 150:02e0a0aed4ec 978 #define _CMU_CMD_CALSTOP_SHIFT 4 /**< Shift value for CMU_CALSTOP */
<> 150:02e0a0aed4ec 979 #define _CMU_CMD_CALSTOP_MASK 0x10UL /**< Bit mask for CMU_CALSTOP */
<> 150:02e0a0aed4ec 980 #define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */
<> 150:02e0a0aed4ec 981 #define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */
<> 150:02e0a0aed4ec 982
<> 150:02e0a0aed4ec 983 /* Bit fields for CMU LFCLKSEL */
<> 150:02e0a0aed4ec 984 #define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL /**< Default value for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 985 #define _CMU_LFCLKSEL_MASK 0x0011000FUL /**< Mask for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 986 #define _CMU_LFCLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */
<> 150:02e0a0aed4ec 987 #define _CMU_LFCLKSEL_LFA_MASK 0x3UL /**< Bit mask for CMU_LFA */
<> 150:02e0a0aed4ec 988 #define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 989 #define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 990 #define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 991 #define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 992 #define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 993 #define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 994 #define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 995 #define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 996 #define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 997 #define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 998 #define _CMU_LFCLKSEL_LFB_SHIFT 2 /**< Shift value for CMU_LFB */
<> 150:02e0a0aed4ec 999 #define _CMU_LFCLKSEL_LFB_MASK 0xCUL /**< Bit mask for CMU_LFB */
<> 150:02e0a0aed4ec 1000 #define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 1001 #define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 1002 #define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 1003 #define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 1004 #define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 1005 #define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2) /**< Shifted mode DISABLED for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 1006 #define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 1007 #define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2) /**< Shifted mode LFRCO for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 1008 #define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2) /**< Shifted mode LFXO for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 1009 #define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 1010 #define CMU_LFCLKSEL_LFAE (0x1UL << 16) /**< Clock Select for LFA Extended */
<> 150:02e0a0aed4ec 1011 #define _CMU_LFCLKSEL_LFAE_SHIFT 16 /**< Shift value for CMU_LFAE */
<> 150:02e0a0aed4ec 1012 #define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL /**< Bit mask for CMU_LFAE */
<> 150:02e0a0aed4ec 1013 #define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 1014 #define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 1015 #define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 1016 #define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 1017 #define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16) /**< Shifted mode DISABLED for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 1018 #define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 1019 #define CMU_LFCLKSEL_LFBE (0x1UL << 20) /**< Clock Select for LFB Extended */
<> 150:02e0a0aed4ec 1020 #define _CMU_LFCLKSEL_LFBE_SHIFT 20 /**< Shift value for CMU_LFBE */
<> 150:02e0a0aed4ec 1021 #define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL /**< Bit mask for CMU_LFBE */
<> 150:02e0a0aed4ec 1022 #define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 1023 #define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 1024 #define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 1025 #define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 1026 #define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20) /**< Shifted mode DISABLED for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 1027 #define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 1028
<> 150:02e0a0aed4ec 1029 /* Bit fields for CMU STATUS */
<> 150:02e0a0aed4ec 1030 #define _CMU_STATUS_RESETVALUE 0x00000403UL /**< Default value for CMU_STATUS */
<> 150:02e0a0aed4ec 1031 #define _CMU_STATUS_MASK 0x00007FFFUL /**< Mask for CMU_STATUS */
<> 150:02e0a0aed4ec 1032 #define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */
<> 150:02e0a0aed4ec 1033 #define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */
<> 150:02e0a0aed4ec 1034 #define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */
<> 150:02e0a0aed4ec 1035 #define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 1036 #define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 1037 #define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */
<> 150:02e0a0aed4ec 1038 #define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */
<> 150:02e0a0aed4ec 1039 #define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */
<> 150:02e0a0aed4ec 1040 #define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 1041 #define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 1042 #define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */
<> 150:02e0a0aed4ec 1043 #define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */
<> 150:02e0a0aed4ec 1044 #define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */
<> 150:02e0a0aed4ec 1045 #define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 1046 #define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 1047 #define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */
<> 150:02e0a0aed4ec 1048 #define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */
<> 150:02e0a0aed4ec 1049 #define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */
<> 150:02e0a0aed4ec 1050 #define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 1051 #define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 1052 #define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */
<> 150:02e0a0aed4ec 1053 #define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */
<> 150:02e0a0aed4ec 1054 #define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */
<> 150:02e0a0aed4ec 1055 #define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 1056 #define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 1057 #define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */
<> 150:02e0a0aed4ec 1058 #define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */
<> 150:02e0a0aed4ec 1059 #define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */
<> 150:02e0a0aed4ec 1060 #define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 1061 #define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 1062 #define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */
<> 150:02e0a0aed4ec 1063 #define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */
<> 150:02e0a0aed4ec 1064 #define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */
<> 150:02e0a0aed4ec 1065 #define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 1066 #define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 1067 #define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */
<> 150:02e0a0aed4ec 1068 #define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */
<> 150:02e0a0aed4ec 1069 #define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */
<> 150:02e0a0aed4ec 1070 #define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 1071 #define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 1072 #define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */
<> 150:02e0a0aed4ec 1073 #define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */
<> 150:02e0a0aed4ec 1074 #define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */
<> 150:02e0a0aed4ec 1075 #define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 1076 #define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 1077 #define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */
<> 150:02e0a0aed4ec 1078 #define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */
<> 150:02e0a0aed4ec 1079 #define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */
<> 150:02e0a0aed4ec 1080 #define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 1081 #define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 1082 #define CMU_STATUS_HFRCOSEL (0x1UL << 10) /**< HFRCO Selected */
<> 150:02e0a0aed4ec 1083 #define _CMU_STATUS_HFRCOSEL_SHIFT 10 /**< Shift value for CMU_HFRCOSEL */
<> 150:02e0a0aed4ec 1084 #define _CMU_STATUS_HFRCOSEL_MASK 0x400UL /**< Bit mask for CMU_HFRCOSEL */
<> 150:02e0a0aed4ec 1085 #define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 1086 #define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 1087 #define CMU_STATUS_HFXOSEL (0x1UL << 11) /**< HFXO Selected */
<> 150:02e0a0aed4ec 1088 #define _CMU_STATUS_HFXOSEL_SHIFT 11 /**< Shift value for CMU_HFXOSEL */
<> 150:02e0a0aed4ec 1089 #define _CMU_STATUS_HFXOSEL_MASK 0x800UL /**< Bit mask for CMU_HFXOSEL */
<> 150:02e0a0aed4ec 1090 #define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 1091 #define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 1092 #define CMU_STATUS_LFRCOSEL (0x1UL << 12) /**< LFRCO Selected */
<> 150:02e0a0aed4ec 1093 #define _CMU_STATUS_LFRCOSEL_SHIFT 12 /**< Shift value for CMU_LFRCOSEL */
<> 150:02e0a0aed4ec 1094 #define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL /**< Bit mask for CMU_LFRCOSEL */
<> 150:02e0a0aed4ec 1095 #define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 1096 #define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 1097 #define CMU_STATUS_LFXOSEL (0x1UL << 13) /**< LFXO Selected */
<> 150:02e0a0aed4ec 1098 #define _CMU_STATUS_LFXOSEL_SHIFT 13 /**< Shift value for CMU_LFXOSEL */
<> 150:02e0a0aed4ec 1099 #define _CMU_STATUS_LFXOSEL_MASK 0x2000UL /**< Bit mask for CMU_LFXOSEL */
<> 150:02e0a0aed4ec 1100 #define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 1101 #define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 1102 #define CMU_STATUS_CALBSY (0x1UL << 14) /**< Calibration Busy */
<> 150:02e0a0aed4ec 1103 #define _CMU_STATUS_CALBSY_SHIFT 14 /**< Shift value for CMU_CALBSY */
<> 150:02e0a0aed4ec 1104 #define _CMU_STATUS_CALBSY_MASK 0x4000UL /**< Bit mask for CMU_CALBSY */
<> 150:02e0a0aed4ec 1105 #define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 1106 #define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 1107
<> 150:02e0a0aed4ec 1108 /* Bit fields for CMU IF */
<> 150:02e0a0aed4ec 1109 #define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */
<> 150:02e0a0aed4ec 1110 #define _CMU_IF_MASK 0x0000007FUL /**< Mask for CMU_IF */
<> 150:02e0a0aed4ec 1111 #define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */
<> 150:02e0a0aed4ec 1112 #define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */
<> 150:02e0a0aed4ec 1113 #define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */
<> 150:02e0a0aed4ec 1114 #define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */
<> 150:02e0a0aed4ec 1115 #define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */
<> 150:02e0a0aed4ec 1116 #define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */
<> 150:02e0a0aed4ec 1117 #define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */
<> 150:02e0a0aed4ec 1118 #define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */
<> 150:02e0a0aed4ec 1119 #define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
<> 150:02e0a0aed4ec 1120 #define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */
<> 150:02e0a0aed4ec 1121 #define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */
<> 150:02e0a0aed4ec 1122 #define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */
<> 150:02e0a0aed4ec 1123 #define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */
<> 150:02e0a0aed4ec 1124 #define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
<> 150:02e0a0aed4ec 1125 #define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */
<> 150:02e0a0aed4ec 1126 #define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */
<> 150:02e0a0aed4ec 1127 #define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */
<> 150:02e0a0aed4ec 1128 #define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */
<> 150:02e0a0aed4ec 1129 #define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
<> 150:02e0a0aed4ec 1130 #define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */
<> 150:02e0a0aed4ec 1131 #define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */
<> 150:02e0a0aed4ec 1132 #define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */
<> 150:02e0a0aed4ec 1133 #define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */
<> 150:02e0a0aed4ec 1134 #define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
<> 150:02e0a0aed4ec 1135 #define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */
<> 150:02e0a0aed4ec 1136 #define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */
<> 150:02e0a0aed4ec 1137 #define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */
<> 150:02e0a0aed4ec 1138 #define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */
<> 150:02e0a0aed4ec 1139 #define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
<> 150:02e0a0aed4ec 1140 #define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */
<> 150:02e0a0aed4ec 1141 #define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */
<> 150:02e0a0aed4ec 1142 #define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */
<> 150:02e0a0aed4ec 1143 #define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */
<> 150:02e0a0aed4ec 1144 #define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
<> 150:02e0a0aed4ec 1145 #define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */
<> 150:02e0a0aed4ec 1146
<> 150:02e0a0aed4ec 1147 /* Bit fields for CMU IFS */
<> 150:02e0a0aed4ec 1148 #define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */
<> 150:02e0a0aed4ec 1149 #define _CMU_IFS_MASK 0x0000007FUL /**< Mask for CMU_IFS */
<> 150:02e0a0aed4ec 1150 #define CMU_IFS_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Set */
<> 150:02e0a0aed4ec 1151 #define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */
<> 150:02e0a0aed4ec 1152 #define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */
<> 150:02e0a0aed4ec 1153 #define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
<> 150:02e0a0aed4ec 1154 #define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */
<> 150:02e0a0aed4ec 1155 #define CMU_IFS_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Set */
<> 150:02e0a0aed4ec 1156 #define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */
<> 150:02e0a0aed4ec 1157 #define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */
<> 150:02e0a0aed4ec 1158 #define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
<> 150:02e0a0aed4ec 1159 #define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */
<> 150:02e0a0aed4ec 1160 #define CMU_IFS_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Set */
<> 150:02e0a0aed4ec 1161 #define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */
<> 150:02e0a0aed4ec 1162 #define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */
<> 150:02e0a0aed4ec 1163 #define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
<> 150:02e0a0aed4ec 1164 #define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */
<> 150:02e0a0aed4ec 1165 #define CMU_IFS_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Set */
<> 150:02e0a0aed4ec 1166 #define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */
<> 150:02e0a0aed4ec 1167 #define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */
<> 150:02e0a0aed4ec 1168 #define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
<> 150:02e0a0aed4ec 1169 #define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */
<> 150:02e0a0aed4ec 1170 #define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Set */
<> 150:02e0a0aed4ec 1171 #define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */
<> 150:02e0a0aed4ec 1172 #define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */
<> 150:02e0a0aed4ec 1173 #define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
<> 150:02e0a0aed4ec 1174 #define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */
<> 150:02e0a0aed4ec 1175 #define CMU_IFS_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Set */
<> 150:02e0a0aed4ec 1176 #define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */
<> 150:02e0a0aed4ec 1177 #define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */
<> 150:02e0a0aed4ec 1178 #define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
<> 150:02e0a0aed4ec 1179 #define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */
<> 150:02e0a0aed4ec 1180 #define CMU_IFS_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Set */
<> 150:02e0a0aed4ec 1181 #define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */
<> 150:02e0a0aed4ec 1182 #define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */
<> 150:02e0a0aed4ec 1183 #define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
<> 150:02e0a0aed4ec 1184 #define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */
<> 150:02e0a0aed4ec 1185
<> 150:02e0a0aed4ec 1186 /* Bit fields for CMU IFC */
<> 150:02e0a0aed4ec 1187 #define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */
<> 150:02e0a0aed4ec 1188 #define _CMU_IFC_MASK 0x0000007FUL /**< Mask for CMU_IFC */
<> 150:02e0a0aed4ec 1189 #define CMU_IFC_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Clear */
<> 150:02e0a0aed4ec 1190 #define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */
<> 150:02e0a0aed4ec 1191 #define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */
<> 150:02e0a0aed4ec 1192 #define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
<> 150:02e0a0aed4ec 1193 #define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */
<> 150:02e0a0aed4ec 1194 #define CMU_IFC_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Clear */
<> 150:02e0a0aed4ec 1195 #define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */
<> 150:02e0a0aed4ec 1196 #define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */
<> 150:02e0a0aed4ec 1197 #define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
<> 150:02e0a0aed4ec 1198 #define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */
<> 150:02e0a0aed4ec 1199 #define CMU_IFC_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Clear */
<> 150:02e0a0aed4ec 1200 #define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */
<> 150:02e0a0aed4ec 1201 #define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */
<> 150:02e0a0aed4ec 1202 #define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
<> 150:02e0a0aed4ec 1203 #define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */
<> 150:02e0a0aed4ec 1204 #define CMU_IFC_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Clear */
<> 150:02e0a0aed4ec 1205 #define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */
<> 150:02e0a0aed4ec 1206 #define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */
<> 150:02e0a0aed4ec 1207 #define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
<> 150:02e0a0aed4ec 1208 #define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */
<> 150:02e0a0aed4ec 1209 #define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Clear */
<> 150:02e0a0aed4ec 1210 #define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */
<> 150:02e0a0aed4ec 1211 #define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */
<> 150:02e0a0aed4ec 1212 #define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
<> 150:02e0a0aed4ec 1213 #define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */
<> 150:02e0a0aed4ec 1214 #define CMU_IFC_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Clear */
<> 150:02e0a0aed4ec 1215 #define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */
<> 150:02e0a0aed4ec 1216 #define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */
<> 150:02e0a0aed4ec 1217 #define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
<> 150:02e0a0aed4ec 1218 #define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */
<> 150:02e0a0aed4ec 1219 #define CMU_IFC_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Clear */
<> 150:02e0a0aed4ec 1220 #define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */
<> 150:02e0a0aed4ec 1221 #define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */
<> 150:02e0a0aed4ec 1222 #define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
<> 150:02e0a0aed4ec 1223 #define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */
<> 150:02e0a0aed4ec 1224
<> 150:02e0a0aed4ec 1225 /* Bit fields for CMU IEN */
<> 150:02e0a0aed4ec 1226 #define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */
<> 150:02e0a0aed4ec 1227 #define _CMU_IEN_MASK 0x0000007FUL /**< Mask for CMU_IEN */
<> 150:02e0a0aed4ec 1228 #define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Enable */
<> 150:02e0a0aed4ec 1229 #define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */
<> 150:02e0a0aed4ec 1230 #define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */
<> 150:02e0a0aed4ec 1231 #define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
<> 150:02e0a0aed4ec 1232 #define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */
<> 150:02e0a0aed4ec 1233 #define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Enable */
<> 150:02e0a0aed4ec 1234 #define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */
<> 150:02e0a0aed4ec 1235 #define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */
<> 150:02e0a0aed4ec 1236 #define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
<> 150:02e0a0aed4ec 1237 #define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */
<> 150:02e0a0aed4ec 1238 #define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Enable */
<> 150:02e0a0aed4ec 1239 #define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */
<> 150:02e0a0aed4ec 1240 #define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */
<> 150:02e0a0aed4ec 1241 #define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
<> 150:02e0a0aed4ec 1242 #define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */
<> 150:02e0a0aed4ec 1243 #define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Enable */
<> 150:02e0a0aed4ec 1244 #define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */
<> 150:02e0a0aed4ec 1245 #define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */
<> 150:02e0a0aed4ec 1246 #define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
<> 150:02e0a0aed4ec 1247 #define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */
<> 150:02e0a0aed4ec 1248 #define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Enable */
<> 150:02e0a0aed4ec 1249 #define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */
<> 150:02e0a0aed4ec 1250 #define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */
<> 150:02e0a0aed4ec 1251 #define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
<> 150:02e0a0aed4ec 1252 #define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */
<> 150:02e0a0aed4ec 1253 #define CMU_IEN_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Enable */
<> 150:02e0a0aed4ec 1254 #define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */
<> 150:02e0a0aed4ec 1255 #define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */
<> 150:02e0a0aed4ec 1256 #define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
<> 150:02e0a0aed4ec 1257 #define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */
<> 150:02e0a0aed4ec 1258 #define CMU_IEN_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Enable */
<> 150:02e0a0aed4ec 1259 #define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */
<> 150:02e0a0aed4ec 1260 #define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */
<> 150:02e0a0aed4ec 1261 #define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
<> 150:02e0a0aed4ec 1262 #define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */
<> 150:02e0a0aed4ec 1263
<> 150:02e0a0aed4ec 1264 /* Bit fields for CMU HFCORECLKEN0 */
<> 150:02e0a0aed4ec 1265 #define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKEN0 */
<> 150:02e0a0aed4ec 1266 #define _CMU_HFCORECLKEN0_MASK 0x00000033UL /**< Mask for CMU_HFCORECLKEN0 */
<> 150:02e0a0aed4ec 1267 #define CMU_HFCORECLKEN0_DMA (0x1UL << 0) /**< Direct Memory Access Controller Clock Enable */
<> 150:02e0a0aed4ec 1268 #define _CMU_HFCORECLKEN0_DMA_SHIFT 0 /**< Shift value for CMU_DMA */
<> 150:02e0a0aed4ec 1269 #define _CMU_HFCORECLKEN0_DMA_MASK 0x1UL /**< Bit mask for CMU_DMA */
<> 150:02e0a0aed4ec 1270 #define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */
<> 150:02e0a0aed4ec 1271 #define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */
<> 150:02e0a0aed4ec 1272 #define CMU_HFCORECLKEN0_AES (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */
<> 150:02e0a0aed4ec 1273 #define _CMU_HFCORECLKEN0_AES_SHIFT 1 /**< Shift value for CMU_AES */
<> 150:02e0a0aed4ec 1274 #define _CMU_HFCORECLKEN0_AES_MASK 0x2UL /**< Bit mask for CMU_AES */
<> 150:02e0a0aed4ec 1275 #define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */
<> 150:02e0a0aed4ec 1276 #define CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */
<> 150:02e0a0aed4ec 1277 #define CMU_HFCORECLKEN0_LE (0x1UL << 4) /**< Low Energy Peripheral Interface Clock Enable */
<> 150:02e0a0aed4ec 1278 #define _CMU_HFCORECLKEN0_LE_SHIFT 4 /**< Shift value for CMU_LE */
<> 150:02e0a0aed4ec 1279 #define _CMU_HFCORECLKEN0_LE_MASK 0x10UL /**< Bit mask for CMU_LE */
<> 150:02e0a0aed4ec 1280 #define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */
<> 150:02e0a0aed4ec 1281 #define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */
<> 150:02e0a0aed4ec 1282 #define CMU_HFCORECLKEN0_EBI (0x1UL << 5) /**< External Bus Interface Clock Enable */
<> 150:02e0a0aed4ec 1283 #define _CMU_HFCORECLKEN0_EBI_SHIFT 5 /**< Shift value for CMU_EBI */
<> 150:02e0a0aed4ec 1284 #define _CMU_HFCORECLKEN0_EBI_MASK 0x20UL /**< Bit mask for CMU_EBI */
<> 150:02e0a0aed4ec 1285 #define _CMU_HFCORECLKEN0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */
<> 150:02e0a0aed4ec 1286 #define CMU_HFCORECLKEN0_EBI_DEFAULT (_CMU_HFCORECLKEN0_EBI_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */
<> 150:02e0a0aed4ec 1287
<> 150:02e0a0aed4ec 1288 /* Bit fields for CMU HFPERCLKEN0 */
<> 150:02e0a0aed4ec 1289 #define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 1290 #define _CMU_HFPERCLKEN0_MASK 0x0003FFFFUL /**< Mask for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 1291 #define CMU_HFPERCLKEN0_USART0 (0x1UL << 0) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */
<> 150:02e0a0aed4ec 1292 #define _CMU_HFPERCLKEN0_USART0_SHIFT 0 /**< Shift value for CMU_USART0 */
<> 150:02e0a0aed4ec 1293 #define _CMU_HFPERCLKEN0_USART0_MASK 0x1UL /**< Bit mask for CMU_USART0 */
<> 150:02e0a0aed4ec 1294 #define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 1295 #define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 1296 #define CMU_HFPERCLKEN0_USART1 (0x1UL << 1) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */
<> 150:02e0a0aed4ec 1297 #define _CMU_HFPERCLKEN0_USART1_SHIFT 1 /**< Shift value for CMU_USART1 */
<> 150:02e0a0aed4ec 1298 #define _CMU_HFPERCLKEN0_USART1_MASK 0x2UL /**< Bit mask for CMU_USART1 */
<> 150:02e0a0aed4ec 1299 #define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 1300 #define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 1301 #define CMU_HFPERCLKEN0_USART2 (0x1UL << 2) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */
<> 150:02e0a0aed4ec 1302 #define _CMU_HFPERCLKEN0_USART2_SHIFT 2 /**< Shift value for CMU_USART2 */
<> 150:02e0a0aed4ec 1303 #define _CMU_HFPERCLKEN0_USART2_MASK 0x4UL /**< Bit mask for CMU_USART2 */
<> 150:02e0a0aed4ec 1304 #define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 1305 #define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 1306 #define CMU_HFPERCLKEN0_UART0 (0x1UL << 3) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */
<> 150:02e0a0aed4ec 1307 #define _CMU_HFPERCLKEN0_UART0_SHIFT 3 /**< Shift value for CMU_UART0 */
<> 150:02e0a0aed4ec 1308 #define _CMU_HFPERCLKEN0_UART0_MASK 0x8UL /**< Bit mask for CMU_UART0 */
<> 150:02e0a0aed4ec 1309 #define _CMU_HFPERCLKEN0_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 1310 #define CMU_HFPERCLKEN0_UART0_DEFAULT (_CMU_HFPERCLKEN0_UART0_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 1311 #define CMU_HFPERCLKEN0_UART1 (0x1UL << 4) /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */
<> 150:02e0a0aed4ec 1312 #define _CMU_HFPERCLKEN0_UART1_SHIFT 4 /**< Shift value for CMU_UART1 */
<> 150:02e0a0aed4ec 1313 #define _CMU_HFPERCLKEN0_UART1_MASK 0x10UL /**< Bit mask for CMU_UART1 */
<> 150:02e0a0aed4ec 1314 #define _CMU_HFPERCLKEN0_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 1315 #define CMU_HFPERCLKEN0_UART1_DEFAULT (_CMU_HFPERCLKEN0_UART1_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 1316 #define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 5) /**< Timer 0 Clock Enable */
<> 150:02e0a0aed4ec 1317 #define _CMU_HFPERCLKEN0_TIMER0_SHIFT 5 /**< Shift value for CMU_TIMER0 */
<> 150:02e0a0aed4ec 1318 #define _CMU_HFPERCLKEN0_TIMER0_MASK 0x20UL /**< Bit mask for CMU_TIMER0 */
<> 150:02e0a0aed4ec 1319 #define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 1320 #define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 1321 #define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 6) /**< Timer 1 Clock Enable */
<> 150:02e0a0aed4ec 1322 #define _CMU_HFPERCLKEN0_TIMER1_SHIFT 6 /**< Shift value for CMU_TIMER1 */
<> 150:02e0a0aed4ec 1323 #define _CMU_HFPERCLKEN0_TIMER1_MASK 0x40UL /**< Bit mask for CMU_TIMER1 */
<> 150:02e0a0aed4ec 1324 #define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 1325 #define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 1326 #define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 7) /**< Timer 2 Clock Enable */
<> 150:02e0a0aed4ec 1327 #define _CMU_HFPERCLKEN0_TIMER2_SHIFT 7 /**< Shift value for CMU_TIMER2 */
<> 150:02e0a0aed4ec 1328 #define _CMU_HFPERCLKEN0_TIMER2_MASK 0x80UL /**< Bit mask for CMU_TIMER2 */
<> 150:02e0a0aed4ec 1329 #define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 1330 #define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 1331 #define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 8) /**< Timer 3 Clock Enable */
<> 150:02e0a0aed4ec 1332 #define _CMU_HFPERCLKEN0_TIMER3_SHIFT 8 /**< Shift value for CMU_TIMER3 */
<> 150:02e0a0aed4ec 1333 #define _CMU_HFPERCLKEN0_TIMER3_MASK 0x100UL /**< Bit mask for CMU_TIMER3 */
<> 150:02e0a0aed4ec 1334 #define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 1335 #define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 1336 #define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 9) /**< Analog Comparator 0 Clock Enable */
<> 150:02e0a0aed4ec 1337 #define _CMU_HFPERCLKEN0_ACMP0_SHIFT 9 /**< Shift value for CMU_ACMP0 */
<> 150:02e0a0aed4ec 1338 #define _CMU_HFPERCLKEN0_ACMP0_MASK 0x200UL /**< Bit mask for CMU_ACMP0 */
<> 150:02e0a0aed4ec 1339 #define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 1340 #define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 1341 #define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 10) /**< Analog Comparator 1 Clock Enable */
<> 150:02e0a0aed4ec 1342 #define _CMU_HFPERCLKEN0_ACMP1_SHIFT 10 /**< Shift value for CMU_ACMP1 */
<> 150:02e0a0aed4ec 1343 #define _CMU_HFPERCLKEN0_ACMP1_MASK 0x400UL /**< Bit mask for CMU_ACMP1 */
<> 150:02e0a0aed4ec 1344 #define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 1345 #define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 1346 #define CMU_HFPERCLKEN0_I2C0 (0x1UL << 11) /**< I2C 0 Clock Enable */
<> 150:02e0a0aed4ec 1347 #define _CMU_HFPERCLKEN0_I2C0_SHIFT 11 /**< Shift value for CMU_I2C0 */
<> 150:02e0a0aed4ec 1348 #define _CMU_HFPERCLKEN0_I2C0_MASK 0x800UL /**< Bit mask for CMU_I2C0 */
<> 150:02e0a0aed4ec 1349 #define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 1350 #define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 1351 #define CMU_HFPERCLKEN0_I2C1 (0x1UL << 12) /**< I2C 1 Clock Enable */
<> 150:02e0a0aed4ec 1352 #define _CMU_HFPERCLKEN0_I2C1_SHIFT 12 /**< Shift value for CMU_I2C1 */
<> 150:02e0a0aed4ec 1353 #define _CMU_HFPERCLKEN0_I2C1_MASK 0x1000UL /**< Bit mask for CMU_I2C1 */
<> 150:02e0a0aed4ec 1354 #define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 1355 #define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 1356 #define CMU_HFPERCLKEN0_GPIO (0x1UL << 13) /**< General purpose Input/Output Clock Enable */
<> 150:02e0a0aed4ec 1357 #define _CMU_HFPERCLKEN0_GPIO_SHIFT 13 /**< Shift value for CMU_GPIO */
<> 150:02e0a0aed4ec 1358 #define _CMU_HFPERCLKEN0_GPIO_MASK 0x2000UL /**< Bit mask for CMU_GPIO */
<> 150:02e0a0aed4ec 1359 #define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 1360 #define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 1361 #define CMU_HFPERCLKEN0_VCMP (0x1UL << 14) /**< Voltage Comparator Clock Enable */
<> 150:02e0a0aed4ec 1362 #define _CMU_HFPERCLKEN0_VCMP_SHIFT 14 /**< Shift value for CMU_VCMP */
<> 150:02e0a0aed4ec 1363 #define _CMU_HFPERCLKEN0_VCMP_MASK 0x4000UL /**< Bit mask for CMU_VCMP */
<> 150:02e0a0aed4ec 1364 #define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 1365 #define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 1366 #define CMU_HFPERCLKEN0_PRS (0x1UL << 15) /**< Peripheral Reflex System Clock Enable */
<> 150:02e0a0aed4ec 1367 #define _CMU_HFPERCLKEN0_PRS_SHIFT 15 /**< Shift value for CMU_PRS */
<> 150:02e0a0aed4ec 1368 #define _CMU_HFPERCLKEN0_PRS_MASK 0x8000UL /**< Bit mask for CMU_PRS */
<> 150:02e0a0aed4ec 1369 #define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 1370 #define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 1371 #define CMU_HFPERCLKEN0_ADC0 (0x1UL << 16) /**< Analog to Digital Converter 0 Clock Enable */
<> 150:02e0a0aed4ec 1372 #define _CMU_HFPERCLKEN0_ADC0_SHIFT 16 /**< Shift value for CMU_ADC0 */
<> 150:02e0a0aed4ec 1373 #define _CMU_HFPERCLKEN0_ADC0_MASK 0x10000UL /**< Bit mask for CMU_ADC0 */
<> 150:02e0a0aed4ec 1374 #define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 1375 #define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 1376 #define CMU_HFPERCLKEN0_DAC0 (0x1UL << 17) /**< Digital to Analog Converter 0 Clock Enable */
<> 150:02e0a0aed4ec 1377 #define _CMU_HFPERCLKEN0_DAC0_SHIFT 17 /**< Shift value for CMU_DAC0 */
<> 150:02e0a0aed4ec 1378 #define _CMU_HFPERCLKEN0_DAC0_MASK 0x20000UL /**< Bit mask for CMU_DAC0 */
<> 150:02e0a0aed4ec 1379 #define _CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 1380 #define CMU_HFPERCLKEN0_DAC0_DEFAULT (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 1381
<> 150:02e0a0aed4ec 1382 /* Bit fields for CMU SYNCBUSY */
<> 150:02e0a0aed4ec 1383 #define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */
<> 150:02e0a0aed4ec 1384 #define _CMU_SYNCBUSY_MASK 0x00000055UL /**< Mask for CMU_SYNCBUSY */
<> 150:02e0a0aed4ec 1385 #define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */
<> 150:02e0a0aed4ec 1386 #define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */
<> 150:02e0a0aed4ec 1387 #define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */
<> 150:02e0a0aed4ec 1388 #define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
<> 150:02e0a0aed4ec 1389 #define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
<> 150:02e0a0aed4ec 1390 #define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */
<> 150:02e0a0aed4ec 1391 #define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1392 #define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1393 #define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
<> 150:02e0a0aed4ec 1394 #define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
<> 150:02e0a0aed4ec 1395 #define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */
<> 150:02e0a0aed4ec 1396 #define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */
<> 150:02e0a0aed4ec 1397 #define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */
<> 150:02e0a0aed4ec 1398 #define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
<> 150:02e0a0aed4ec 1399 #define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
<> 150:02e0a0aed4ec 1400 #define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */
<> 150:02e0a0aed4ec 1401 #define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 1402 #define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 1403 #define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
<> 150:02e0a0aed4ec 1404 #define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
<> 150:02e0a0aed4ec 1405
<> 150:02e0a0aed4ec 1406 /* Bit fields for CMU FREEZE */
<> 150:02e0a0aed4ec 1407 #define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */
<> 150:02e0a0aed4ec 1408 #define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */
<> 150:02e0a0aed4ec 1409 #define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */
<> 150:02e0a0aed4ec 1410 #define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */
<> 150:02e0a0aed4ec 1411 #define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */
<> 150:02e0a0aed4ec 1412 #define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */
<> 150:02e0a0aed4ec 1413 #define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */
<> 150:02e0a0aed4ec 1414 #define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */
<> 150:02e0a0aed4ec 1415 #define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */
<> 150:02e0a0aed4ec 1416 #define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */
<> 150:02e0a0aed4ec 1417 #define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */
<> 150:02e0a0aed4ec 1418
<> 150:02e0a0aed4ec 1419 /* Bit fields for CMU LFACLKEN0 */
<> 150:02e0a0aed4ec 1420 #define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */
<> 150:02e0a0aed4ec 1421 #define _CMU_LFACLKEN0_MASK 0x0000000FUL /**< Mask for CMU_LFACLKEN0 */
<> 150:02e0a0aed4ec 1422 #define CMU_LFACLKEN0_LESENSE (0x1UL << 0) /**< Low Energy Sensor Interface Clock Enable */
<> 150:02e0a0aed4ec 1423 #define _CMU_LFACLKEN0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */
<> 150:02e0a0aed4ec 1424 #define _CMU_LFACLKEN0_LESENSE_MASK 0x1UL /**< Bit mask for CMU_LESENSE */
<> 150:02e0a0aed4ec 1425 #define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */
<> 150:02e0a0aed4ec 1426 #define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */
<> 150:02e0a0aed4ec 1427 #define CMU_LFACLKEN0_RTC (0x1UL << 1) /**< Real-Time Counter Clock Enable */
<> 150:02e0a0aed4ec 1428 #define _CMU_LFACLKEN0_RTC_SHIFT 1 /**< Shift value for CMU_RTC */
<> 150:02e0a0aed4ec 1429 #define _CMU_LFACLKEN0_RTC_MASK 0x2UL /**< Bit mask for CMU_RTC */
<> 150:02e0a0aed4ec 1430 #define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */
<> 150:02e0a0aed4ec 1431 #define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */
<> 150:02e0a0aed4ec 1432 #define CMU_LFACLKEN0_LETIMER0 (0x1UL << 2) /**< Low Energy Timer 0 Clock Enable */
<> 150:02e0a0aed4ec 1433 #define _CMU_LFACLKEN0_LETIMER0_SHIFT 2 /**< Shift value for CMU_LETIMER0 */
<> 150:02e0a0aed4ec 1434 #define _CMU_LFACLKEN0_LETIMER0_MASK 0x4UL /**< Bit mask for CMU_LETIMER0 */
<> 150:02e0a0aed4ec 1435 #define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */
<> 150:02e0a0aed4ec 1436 #define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */
<> 150:02e0a0aed4ec 1437 #define CMU_LFACLKEN0_LCD (0x1UL << 3) /**< Liquid Crystal Display Controller Clock Enable */
<> 150:02e0a0aed4ec 1438 #define _CMU_LFACLKEN0_LCD_SHIFT 3 /**< Shift value for CMU_LCD */
<> 150:02e0a0aed4ec 1439 #define _CMU_LFACLKEN0_LCD_MASK 0x8UL /**< Bit mask for CMU_LCD */
<> 150:02e0a0aed4ec 1440 #define _CMU_LFACLKEN0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */
<> 150:02e0a0aed4ec 1441 #define CMU_LFACLKEN0_LCD_DEFAULT (_CMU_LFACLKEN0_LCD_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */
<> 150:02e0a0aed4ec 1442
<> 150:02e0a0aed4ec 1443 /* Bit fields for CMU LFBCLKEN0 */
<> 150:02e0a0aed4ec 1444 #define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */
<> 150:02e0a0aed4ec 1445 #define _CMU_LFBCLKEN0_MASK 0x00000003UL /**< Mask for CMU_LFBCLKEN0 */
<> 150:02e0a0aed4ec 1446 #define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */
<> 150:02e0a0aed4ec 1447 #define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */
<> 150:02e0a0aed4ec 1448 #define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */
<> 150:02e0a0aed4ec 1449 #define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */
<> 150:02e0a0aed4ec 1450 #define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */
<> 150:02e0a0aed4ec 1451 #define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */
<> 150:02e0a0aed4ec 1452 #define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */
<> 150:02e0a0aed4ec 1453 #define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */
<> 150:02e0a0aed4ec 1454 #define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */
<> 150:02e0a0aed4ec 1455 #define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */
<> 150:02e0a0aed4ec 1456
<> 150:02e0a0aed4ec 1457 /* Bit fields for CMU LFAPRESC0 */
<> 150:02e0a0aed4ec 1458 #define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1459 #define _CMU_LFAPRESC0_MASK 0x00003FF3UL /**< Mask for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1460 #define _CMU_LFAPRESC0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */
<> 150:02e0a0aed4ec 1461 #define _CMU_LFAPRESC0_LESENSE_MASK 0x3UL /**< Bit mask for CMU_LESENSE */
<> 150:02e0a0aed4ec 1462 #define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1463 #define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1464 #define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1465 #define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1466 #define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1467 #define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1468 #define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1469 #define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1470 #define _CMU_LFAPRESC0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */
<> 150:02e0a0aed4ec 1471 #define _CMU_LFAPRESC0_RTC_MASK 0xF0UL /**< Bit mask for CMU_RTC */
<> 150:02e0a0aed4ec 1472 #define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1473 #define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1474 #define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1475 #define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1476 #define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1477 #define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1478 #define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1479 #define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1480 #define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1481 #define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1482 #define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1483 #define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1484 #define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1485 #define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1486 #define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1487 #define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1488 #define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1489 #define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1490 #define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1491 #define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1492 #define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1493 #define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1494 #define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1495 #define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1496 #define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1497 #define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1498 #define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1499 #define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1500 #define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1501 #define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1502 #define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1503 #define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1504 #define _CMU_LFAPRESC0_LETIMER0_SHIFT 8 /**< Shift value for CMU_LETIMER0 */
<> 150:02e0a0aed4ec 1505 #define _CMU_LFAPRESC0_LETIMER0_MASK 0xF00UL /**< Bit mask for CMU_LETIMER0 */
<> 150:02e0a0aed4ec 1506 #define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1507 #define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1508 #define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1509 #define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1510 #define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1511 #define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1512 #define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1513 #define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1514 #define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1515 #define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1516 #define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1517 #define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1518 #define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1519 #define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1520 #define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1521 #define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1522 #define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1523 #define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1524 #define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1525 #define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1526 #define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 8) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1527 #define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 8) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1528 #define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 8) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1529 #define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 8) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1530 #define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 8) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1531 #define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 8) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1532 #define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 8) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1533 #define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 8) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1534 #define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 8) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1535 #define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 8) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1536 #define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 8) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1537 #define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 8) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1538 #define _CMU_LFAPRESC0_LCD_SHIFT 12 /**< Shift value for CMU_LCD */
<> 150:02e0a0aed4ec 1539 #define _CMU_LFAPRESC0_LCD_MASK 0x3000UL /**< Bit mask for CMU_LCD */
<> 150:02e0a0aed4ec 1540 #define _CMU_LFAPRESC0_LCD_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1541 #define _CMU_LFAPRESC0_LCD_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1542 #define _CMU_LFAPRESC0_LCD_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1543 #define _CMU_LFAPRESC0_LCD_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1544 #define CMU_LFAPRESC0_LCD_DIV16 (_CMU_LFAPRESC0_LCD_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1545 #define CMU_LFAPRESC0_LCD_DIV32 (_CMU_LFAPRESC0_LCD_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1546 #define CMU_LFAPRESC0_LCD_DIV64 (_CMU_LFAPRESC0_LCD_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1547 #define CMU_LFAPRESC0_LCD_DIV128 (_CMU_LFAPRESC0_LCD_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 1548
<> 150:02e0a0aed4ec 1549 /* Bit fields for CMU LFBPRESC0 */
<> 150:02e0a0aed4ec 1550 #define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 1551 #define _CMU_LFBPRESC0_MASK 0x00000033UL /**< Mask for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 1552 #define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */
<> 150:02e0a0aed4ec 1553 #define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */
<> 150:02e0a0aed4ec 1554 #define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 1555 #define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 1556 #define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 1557 #define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 1558 #define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 1559 #define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 1560 #define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 1561 #define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 1562 #define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */
<> 150:02e0a0aed4ec 1563 #define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */
<> 150:02e0a0aed4ec 1564 #define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 1565 #define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 1566 #define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 1567 #define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 1568 #define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 1569 #define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 1570 #define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 1571 #define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 1572
<> 150:02e0a0aed4ec 1573 /* Bit fields for CMU PCNTCTRL */
<> 150:02e0a0aed4ec 1574 #define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 1575 #define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 1576 #define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */
<> 150:02e0a0aed4ec 1577 #define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */
<> 150:02e0a0aed4ec 1578 #define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */
<> 150:02e0a0aed4ec 1579 #define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 1580 #define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 1581 #define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */
<> 150:02e0a0aed4ec 1582 #define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */
<> 150:02e0a0aed4ec 1583 #define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */
<> 150:02e0a0aed4ec 1584 #define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 1585 #define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 1586 #define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 1587 #define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 1588 #define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 1589 #define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 1590 #define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */
<> 150:02e0a0aed4ec 1591 #define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */
<> 150:02e0a0aed4ec 1592 #define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */
<> 150:02e0a0aed4ec 1593 #define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 1594 #define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 1595 #define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */
<> 150:02e0a0aed4ec 1596 #define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */
<> 150:02e0a0aed4ec 1597 #define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */
<> 150:02e0a0aed4ec 1598 #define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 1599 #define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 1600 #define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 1601 #define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 1602 #define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 1603 #define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 1604 #define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */
<> 150:02e0a0aed4ec 1605 #define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */
<> 150:02e0a0aed4ec 1606 #define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */
<> 150:02e0a0aed4ec 1607 #define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 1608 #define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 1609 #define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */
<> 150:02e0a0aed4ec 1610 #define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */
<> 150:02e0a0aed4ec 1611 #define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */
<> 150:02e0a0aed4ec 1612 #define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 1613 #define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 1614 #define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 1615 #define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 1616 #define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 1617 #define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 1618
<> 150:02e0a0aed4ec 1619 /* Bit fields for CMU LCDCTRL */
<> 150:02e0a0aed4ec 1620 #define _CMU_LCDCTRL_RESETVALUE 0x00000020UL /**< Default value for CMU_LCDCTRL */
<> 150:02e0a0aed4ec 1621 #define _CMU_LCDCTRL_MASK 0x0000007FUL /**< Mask for CMU_LCDCTRL */
<> 150:02e0a0aed4ec 1622 #define _CMU_LCDCTRL_FDIV_SHIFT 0 /**< Shift value for CMU_FDIV */
<> 150:02e0a0aed4ec 1623 #define _CMU_LCDCTRL_FDIV_MASK 0x7UL /**< Bit mask for CMU_FDIV */
<> 150:02e0a0aed4ec 1624 #define _CMU_LCDCTRL_FDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LCDCTRL */
<> 150:02e0a0aed4ec 1625 #define CMU_LCDCTRL_FDIV_DEFAULT (_CMU_LCDCTRL_FDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LCDCTRL */
<> 150:02e0a0aed4ec 1626 #define CMU_LCDCTRL_VBOOSTEN (0x1UL << 3) /**< Voltage Boost Enable */
<> 150:02e0a0aed4ec 1627 #define _CMU_LCDCTRL_VBOOSTEN_SHIFT 3 /**< Shift value for CMU_VBOOSTEN */
<> 150:02e0a0aed4ec 1628 #define _CMU_LCDCTRL_VBOOSTEN_MASK 0x8UL /**< Bit mask for CMU_VBOOSTEN */
<> 150:02e0a0aed4ec 1629 #define _CMU_LCDCTRL_VBOOSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LCDCTRL */
<> 150:02e0a0aed4ec 1630 #define CMU_LCDCTRL_VBOOSTEN_DEFAULT (_CMU_LCDCTRL_VBOOSTEN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LCDCTRL */
<> 150:02e0a0aed4ec 1631 #define _CMU_LCDCTRL_VBFDIV_SHIFT 4 /**< Shift value for CMU_VBFDIV */
<> 150:02e0a0aed4ec 1632 #define _CMU_LCDCTRL_VBFDIV_MASK 0x70UL /**< Bit mask for CMU_VBFDIV */
<> 150:02e0a0aed4ec 1633 #define _CMU_LCDCTRL_VBFDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LCDCTRL */
<> 150:02e0a0aed4ec 1634 #define _CMU_LCDCTRL_VBFDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LCDCTRL */
<> 150:02e0a0aed4ec 1635 #define _CMU_LCDCTRL_VBFDIV_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LCDCTRL */
<> 150:02e0a0aed4ec 1636 #define _CMU_LCDCTRL_VBFDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LCDCTRL */
<> 150:02e0a0aed4ec 1637 #define _CMU_LCDCTRL_VBFDIV_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LCDCTRL */
<> 150:02e0a0aed4ec 1638 #define _CMU_LCDCTRL_VBFDIV_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LCDCTRL */
<> 150:02e0a0aed4ec 1639 #define _CMU_LCDCTRL_VBFDIV_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LCDCTRL */
<> 150:02e0a0aed4ec 1640 #define _CMU_LCDCTRL_VBFDIV_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LCDCTRL */
<> 150:02e0a0aed4ec 1641 #define _CMU_LCDCTRL_VBFDIV_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LCDCTRL */
<> 150:02e0a0aed4ec 1642 #define CMU_LCDCTRL_VBFDIV_DIV1 (_CMU_LCDCTRL_VBFDIV_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LCDCTRL */
<> 150:02e0a0aed4ec 1643 #define CMU_LCDCTRL_VBFDIV_DIV2 (_CMU_LCDCTRL_VBFDIV_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LCDCTRL */
<> 150:02e0a0aed4ec 1644 #define CMU_LCDCTRL_VBFDIV_DEFAULT (_CMU_LCDCTRL_VBFDIV_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_LCDCTRL */
<> 150:02e0a0aed4ec 1645 #define CMU_LCDCTRL_VBFDIV_DIV4 (_CMU_LCDCTRL_VBFDIV_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LCDCTRL */
<> 150:02e0a0aed4ec 1646 #define CMU_LCDCTRL_VBFDIV_DIV8 (_CMU_LCDCTRL_VBFDIV_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LCDCTRL */
<> 150:02e0a0aed4ec 1647 #define CMU_LCDCTRL_VBFDIV_DIV16 (_CMU_LCDCTRL_VBFDIV_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LCDCTRL */
<> 150:02e0a0aed4ec 1648 #define CMU_LCDCTRL_VBFDIV_DIV32 (_CMU_LCDCTRL_VBFDIV_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LCDCTRL */
<> 150:02e0a0aed4ec 1649 #define CMU_LCDCTRL_VBFDIV_DIV64 (_CMU_LCDCTRL_VBFDIV_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LCDCTRL */
<> 150:02e0a0aed4ec 1650 #define CMU_LCDCTRL_VBFDIV_DIV128 (_CMU_LCDCTRL_VBFDIV_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LCDCTRL */
<> 150:02e0a0aed4ec 1651
<> 150:02e0a0aed4ec 1652 /* Bit fields for CMU ROUTE */
<> 150:02e0a0aed4ec 1653 #define _CMU_ROUTE_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTE */
<> 150:02e0a0aed4ec 1654 #define _CMU_ROUTE_MASK 0x0000001FUL /**< Mask for CMU_ROUTE */
<> 150:02e0a0aed4ec 1655 #define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */
<> 150:02e0a0aed4ec 1656 #define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */
<> 150:02e0a0aed4ec 1657 #define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */
<> 150:02e0a0aed4ec 1658 #define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */
<> 150:02e0a0aed4ec 1659 #define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTE */
<> 150:02e0a0aed4ec 1660 #define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */
<> 150:02e0a0aed4ec 1661 #define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */
<> 150:02e0a0aed4ec 1662 #define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */
<> 150:02e0a0aed4ec 1663 #define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */
<> 150:02e0a0aed4ec 1664 #define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTE */
<> 150:02e0a0aed4ec 1665 #define _CMU_ROUTE_LOCATION_SHIFT 2 /**< Shift value for CMU_LOCATION */
<> 150:02e0a0aed4ec 1666 #define _CMU_ROUTE_LOCATION_MASK 0x1CUL /**< Bit mask for CMU_LOCATION */
<> 150:02e0a0aed4ec 1667 #define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTE */
<> 150:02e0a0aed4ec 1668 #define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */
<> 150:02e0a0aed4ec 1669 #define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTE */
<> 150:02e0a0aed4ec 1670 #define _CMU_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTE */
<> 150:02e0a0aed4ec 1671 #define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2) /**< Shifted mode LOC0 for CMU_ROUTE */
<> 150:02e0a0aed4ec 1672 #define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTE */
<> 150:02e0a0aed4ec 1673 #define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2) /**< Shifted mode LOC1 for CMU_ROUTE */
<> 150:02e0a0aed4ec 1674 #define CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2) /**< Shifted mode LOC2 for CMU_ROUTE */
<> 150:02e0a0aed4ec 1675
<> 150:02e0a0aed4ec 1676 /* Bit fields for CMU LOCK */
<> 150:02e0a0aed4ec 1677 #define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */
<> 150:02e0a0aed4ec 1678 #define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */
<> 150:02e0a0aed4ec 1679 #define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */
<> 150:02e0a0aed4ec 1680 #define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */
<> 150:02e0a0aed4ec 1681 #define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */
<> 150:02e0a0aed4ec 1682 #define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */
<> 150:02e0a0aed4ec 1683 #define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */
<> 150:02e0a0aed4ec 1684 #define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */
<> 150:02e0a0aed4ec 1685 #define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */
<> 150:02e0a0aed4ec 1686 #define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */
<> 150:02e0a0aed4ec 1687 #define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */
<> 150:02e0a0aed4ec 1688 #define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */
<> 150:02e0a0aed4ec 1689 #define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */
<> 150:02e0a0aed4ec 1690 #define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */
<> 150:02e0a0aed4ec 1691
<> 150:02e0a0aed4ec 1692 /** @} End of group EFM32WG895F128_CMU */
<> 150:02e0a0aed4ec 1693
<> 150:02e0a0aed4ec 1694
<> 150:02e0a0aed4ec 1695
<> 150:02e0a0aed4ec 1696 /**************************************************************************//**
<> 150:02e0a0aed4ec 1697 * @defgroup EFM32WG895F128_PRS_BitFields EFM32WG895F128_PRS Bit Fields
<> 150:02e0a0aed4ec 1698 * @{
<> 150:02e0a0aed4ec 1699 *****************************************************************************/
<> 150:02e0a0aed4ec 1700
<> 150:02e0a0aed4ec 1701 /* Bit fields for PRS SWPULSE */
<> 150:02e0a0aed4ec 1702 #define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */
<> 150:02e0a0aed4ec 1703 #define _PRS_SWPULSE_MASK 0x00000FFFUL /**< Mask for PRS_SWPULSE */
<> 150:02e0a0aed4ec 1704 #define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */
<> 150:02e0a0aed4ec 1705 #define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */
<> 150:02e0a0aed4ec 1706 #define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */
<> 150:02e0a0aed4ec 1707 #define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
<> 150:02e0a0aed4ec 1708 #define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */
<> 150:02e0a0aed4ec 1709 #define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */
<> 150:02e0a0aed4ec 1710 #define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */
<> 150:02e0a0aed4ec 1711 #define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */
<> 150:02e0a0aed4ec 1712 #define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
<> 150:02e0a0aed4ec 1713 #define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */
<> 150:02e0a0aed4ec 1714 #define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */
<> 150:02e0a0aed4ec 1715 #define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */
<> 150:02e0a0aed4ec 1716 #define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */
<> 150:02e0a0aed4ec 1717 #define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
<> 150:02e0a0aed4ec 1718 #define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */
<> 150:02e0a0aed4ec 1719 #define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */
<> 150:02e0a0aed4ec 1720 #define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */
<> 150:02e0a0aed4ec 1721 #define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */
<> 150:02e0a0aed4ec 1722 #define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
<> 150:02e0a0aed4ec 1723 #define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */
<> 150:02e0a0aed4ec 1724 #define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */
<> 150:02e0a0aed4ec 1725 #define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */
<> 150:02e0a0aed4ec 1726 #define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */
<> 150:02e0a0aed4ec 1727 #define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
<> 150:02e0a0aed4ec 1728 #define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */
<> 150:02e0a0aed4ec 1729 #define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */
<> 150:02e0a0aed4ec 1730 #define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */
<> 150:02e0a0aed4ec 1731 #define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */
<> 150:02e0a0aed4ec 1732 #define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
<> 150:02e0a0aed4ec 1733 #define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */
<> 150:02e0a0aed4ec 1734 #define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */
<> 150:02e0a0aed4ec 1735 #define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */
<> 150:02e0a0aed4ec 1736 #define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */
<> 150:02e0a0aed4ec 1737 #define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
<> 150:02e0a0aed4ec 1738 #define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */
<> 150:02e0a0aed4ec 1739 #define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */
<> 150:02e0a0aed4ec 1740 #define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */
<> 150:02e0a0aed4ec 1741 #define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */
<> 150:02e0a0aed4ec 1742 #define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
<> 150:02e0a0aed4ec 1743 #define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */
<> 150:02e0a0aed4ec 1744 #define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */
<> 150:02e0a0aed4ec 1745 #define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */
<> 150:02e0a0aed4ec 1746 #define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */
<> 150:02e0a0aed4ec 1747 #define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
<> 150:02e0a0aed4ec 1748 #define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */
<> 150:02e0a0aed4ec 1749 #define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */
<> 150:02e0a0aed4ec 1750 #define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */
<> 150:02e0a0aed4ec 1751 #define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */
<> 150:02e0a0aed4ec 1752 #define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
<> 150:02e0a0aed4ec 1753 #define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */
<> 150:02e0a0aed4ec 1754 #define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */
<> 150:02e0a0aed4ec 1755 #define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */
<> 150:02e0a0aed4ec 1756 #define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */
<> 150:02e0a0aed4ec 1757 #define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
<> 150:02e0a0aed4ec 1758 #define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */
<> 150:02e0a0aed4ec 1759 #define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */
<> 150:02e0a0aed4ec 1760 #define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */
<> 150:02e0a0aed4ec 1761 #define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */
<> 150:02e0a0aed4ec 1762 #define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
<> 150:02e0a0aed4ec 1763 #define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */
<> 150:02e0a0aed4ec 1764
<> 150:02e0a0aed4ec 1765 /* Bit fields for PRS SWLEVEL */
<> 150:02e0a0aed4ec 1766 #define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */
<> 150:02e0a0aed4ec 1767 #define _PRS_SWLEVEL_MASK 0x00000FFFUL /**< Mask for PRS_SWLEVEL */
<> 150:02e0a0aed4ec 1768 #define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */
<> 150:02e0a0aed4ec 1769 #define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */
<> 150:02e0a0aed4ec 1770 #define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */
<> 150:02e0a0aed4ec 1771 #define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
<> 150:02e0a0aed4ec 1772 #define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
<> 150:02e0a0aed4ec 1773 #define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */
<> 150:02e0a0aed4ec 1774 #define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */
<> 150:02e0a0aed4ec 1775 #define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */
<> 150:02e0a0aed4ec 1776 #define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
<> 150:02e0a0aed4ec 1777 #define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
<> 150:02e0a0aed4ec 1778 #define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */
<> 150:02e0a0aed4ec 1779 #define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */
<> 150:02e0a0aed4ec 1780 #define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */
<> 150:02e0a0aed4ec 1781 #define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
<> 150:02e0a0aed4ec 1782 #define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
<> 150:02e0a0aed4ec 1783 #define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */
<> 150:02e0a0aed4ec 1784 #define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */
<> 150:02e0a0aed4ec 1785 #define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */
<> 150:02e0a0aed4ec 1786 #define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
<> 150:02e0a0aed4ec 1787 #define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
<> 150:02e0a0aed4ec 1788 #define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */
<> 150:02e0a0aed4ec 1789 #define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */
<> 150:02e0a0aed4ec 1790 #define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */
<> 150:02e0a0aed4ec 1791 #define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
<> 150:02e0a0aed4ec 1792 #define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
<> 150:02e0a0aed4ec 1793 #define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */
<> 150:02e0a0aed4ec 1794 #define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */
<> 150:02e0a0aed4ec 1795 #define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */
<> 150:02e0a0aed4ec 1796 #define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
<> 150:02e0a0aed4ec 1797 #define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
<> 150:02e0a0aed4ec 1798 #define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */
<> 150:02e0a0aed4ec 1799 #define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */
<> 150:02e0a0aed4ec 1800 #define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */
<> 150:02e0a0aed4ec 1801 #define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
<> 150:02e0a0aed4ec 1802 #define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
<> 150:02e0a0aed4ec 1803 #define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */
<> 150:02e0a0aed4ec 1804 #define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */
<> 150:02e0a0aed4ec 1805 #define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */
<> 150:02e0a0aed4ec 1806 #define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
<> 150:02e0a0aed4ec 1807 #define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
<> 150:02e0a0aed4ec 1808 #define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */
<> 150:02e0a0aed4ec 1809 #define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */
<> 150:02e0a0aed4ec 1810 #define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */
<> 150:02e0a0aed4ec 1811 #define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
<> 150:02e0a0aed4ec 1812 #define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
<> 150:02e0a0aed4ec 1813 #define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */
<> 150:02e0a0aed4ec 1814 #define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */
<> 150:02e0a0aed4ec 1815 #define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */
<> 150:02e0a0aed4ec 1816 #define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
<> 150:02e0a0aed4ec 1817 #define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
<> 150:02e0a0aed4ec 1818 #define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */
<> 150:02e0a0aed4ec 1819 #define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */
<> 150:02e0a0aed4ec 1820 #define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */
<> 150:02e0a0aed4ec 1821 #define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
<> 150:02e0a0aed4ec 1822 #define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
<> 150:02e0a0aed4ec 1823 #define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */
<> 150:02e0a0aed4ec 1824 #define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */
<> 150:02e0a0aed4ec 1825 #define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */
<> 150:02e0a0aed4ec 1826 #define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
<> 150:02e0a0aed4ec 1827 #define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
<> 150:02e0a0aed4ec 1828
<> 150:02e0a0aed4ec 1829 /* Bit fields for PRS ROUTE */
<> 150:02e0a0aed4ec 1830 #define _PRS_ROUTE_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTE */
<> 150:02e0a0aed4ec 1831 #define _PRS_ROUTE_MASK 0x0000070FUL /**< Mask for PRS_ROUTE */
<> 150:02e0a0aed4ec 1832 #define PRS_ROUTE_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */
<> 150:02e0a0aed4ec 1833 #define _PRS_ROUTE_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */
<> 150:02e0a0aed4ec 1834 #define _PRS_ROUTE_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */
<> 150:02e0a0aed4ec 1835 #define _PRS_ROUTE_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */
<> 150:02e0a0aed4ec 1836 #define PRS_ROUTE_CH0PEN_DEFAULT (_PRS_ROUTE_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTE */
<> 150:02e0a0aed4ec 1837 #define PRS_ROUTE_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */
<> 150:02e0a0aed4ec 1838 #define _PRS_ROUTE_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */
<> 150:02e0a0aed4ec 1839 #define _PRS_ROUTE_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */
<> 150:02e0a0aed4ec 1840 #define _PRS_ROUTE_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */
<> 150:02e0a0aed4ec 1841 #define PRS_ROUTE_CH1PEN_DEFAULT (_PRS_ROUTE_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTE */
<> 150:02e0a0aed4ec 1842 #define PRS_ROUTE_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */
<> 150:02e0a0aed4ec 1843 #define _PRS_ROUTE_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */
<> 150:02e0a0aed4ec 1844 #define _PRS_ROUTE_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */
<> 150:02e0a0aed4ec 1845 #define _PRS_ROUTE_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */
<> 150:02e0a0aed4ec 1846 #define PRS_ROUTE_CH2PEN_DEFAULT (_PRS_ROUTE_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTE */
<> 150:02e0a0aed4ec 1847 #define PRS_ROUTE_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */
<> 150:02e0a0aed4ec 1848 #define _PRS_ROUTE_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */
<> 150:02e0a0aed4ec 1849 #define _PRS_ROUTE_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */
<> 150:02e0a0aed4ec 1850 #define _PRS_ROUTE_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */
<> 150:02e0a0aed4ec 1851 #define PRS_ROUTE_CH3PEN_DEFAULT (_PRS_ROUTE_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTE */
<> 150:02e0a0aed4ec 1852 #define _PRS_ROUTE_LOCATION_SHIFT 8 /**< Shift value for PRS_LOCATION */
<> 150:02e0a0aed4ec 1853 #define _PRS_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for PRS_LOCATION */
<> 150:02e0a0aed4ec 1854 #define _PRS_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTE */
<> 150:02e0a0aed4ec 1855 #define _PRS_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */
<> 150:02e0a0aed4ec 1856 #define _PRS_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTE */
<> 150:02e0a0aed4ec 1857 #define PRS_ROUTE_LOCATION_LOC0 (_PRS_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTE */
<> 150:02e0a0aed4ec 1858 #define PRS_ROUTE_LOCATION_DEFAULT (_PRS_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTE */
<> 150:02e0a0aed4ec 1859 #define PRS_ROUTE_LOCATION_LOC1 (_PRS_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTE */
<> 150:02e0a0aed4ec 1860
<> 150:02e0a0aed4ec 1861 /* Bit fields for PRS CH_CTRL */
<> 150:02e0a0aed4ec 1862 #define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1863 #define _PRS_CH_CTRL_MASK 0x133F0007UL /**< Mask for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1864 #define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */
<> 150:02e0a0aed4ec 1865 #define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */
<> 150:02e0a0aed4ec 1866 #define _PRS_CH_CTRL_SIGSEL_VCMPOUT 0x00000000UL /**< Mode VCMPOUT for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1867 #define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1868 #define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1869 #define _PRS_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1870 #define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1871 #define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1872 #define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1873 #define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1874 #define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1875 #define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1876 #define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1877 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1878 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1879 #define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1880 #define _PRS_CH_CTRL_SIGSEL_BURTCOF 0x00000000UL /**< Mode BURTCOF for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1881 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1882 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1883 #define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1884 #define _PRS_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1885 #define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1886 #define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1887 #define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1888 #define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1889 #define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1890 #define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1891 #define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1892 #define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1893 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1894 #define _PRS_CH_CTRL_SIGSEL_UART0TXC 0x00000001UL /**< Mode UART0TXC for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1895 #define _PRS_CH_CTRL_SIGSEL_UART1TXC 0x00000001UL /**< Mode UART1TXC for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1896 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1897 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1898 #define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1899 #define _PRS_CH_CTRL_SIGSEL_BURTCCOMP0 0x00000001UL /**< Mode BURTCCOMP0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1900 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1901 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1902 #define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1903 #define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1904 #define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1905 #define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1906 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1907 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1908 #define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1909 #define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1910 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1911 #define _PRS_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000002UL /**< Mode UART0RXDATAV for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1912 #define _PRS_CH_CTRL_SIGSEL_UART1RXDATAV 0x00000002UL /**< Mode UART1RXDATAV for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1913 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1914 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1915 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1916 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1917 #define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1918 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1919 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1920 #define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1921 #define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1922 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1923 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1924 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1925 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1926 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1927 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1928 #define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1929 #define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1930 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1931 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1932 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1933 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1934 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1935 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1936 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1937 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1938 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1939 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1940 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1941 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1942 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1943 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1944 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1945 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1946 #define PRS_CH_CTRL_SIGSEL_VCMPOUT (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0) /**< Shifted mode VCMPOUT for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1947 #define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1948 #define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1949 #define PRS_CH_CTRL_SIGSEL_DAC0CH0 (_PRS_CH_CTRL_SIGSEL_DAC0CH0 << 0) /**< Shifted mode DAC0CH0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1950 #define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1951 #define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1952 #define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1953 #define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1954 #define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1955 #define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1956 #define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1957 #define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1958 #define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1959 #define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1960 #define PRS_CH_CTRL_SIGSEL_BURTCOF (_PRS_CH_CTRL_SIGSEL_BURTCOF << 0) /**< Shifted mode BURTCOF for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1961 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1962 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1963 #define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1964 #define PRS_CH_CTRL_SIGSEL_DAC0CH1 (_PRS_CH_CTRL_SIGSEL_DAC0CH1 << 0) /**< Shifted mode DAC0CH1 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1965 #define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1966 #define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1967 #define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1968 #define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1969 #define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1970 #define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1971 #define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1972 #define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1973 #define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1974 #define PRS_CH_CTRL_SIGSEL_UART0TXC (_PRS_CH_CTRL_SIGSEL_UART0TXC << 0) /**< Shifted mode UART0TXC for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1975 #define PRS_CH_CTRL_SIGSEL_UART1TXC (_PRS_CH_CTRL_SIGSEL_UART1TXC << 0) /**< Shifted mode UART1TXC for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1976 #define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1977 #define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1978 #define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1979 #define PRS_CH_CTRL_SIGSEL_BURTCCOMP0 (_PRS_CH_CTRL_SIGSEL_BURTCCOMP0 << 0) /**< Shifted mode BURTCCOMP0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1980 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1981 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1982 #define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1983 #define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1984 #define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1985 #define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1986 #define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1987 #define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1988 #define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1989 #define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1990 #define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1991 #define PRS_CH_CTRL_SIGSEL_UART0RXDATAV (_PRS_CH_CTRL_SIGSEL_UART0RXDATAV << 0) /**< Shifted mode UART0RXDATAV for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1992 #define PRS_CH_CTRL_SIGSEL_UART1RXDATAV (_PRS_CH_CTRL_SIGSEL_UART1RXDATAV << 0) /**< Shifted mode UART1RXDATAV for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1993 #define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1994 #define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1995 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1996 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1997 #define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1998 #define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 1999 #define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2000 #define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2001 #define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2002 #define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2003 #define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2004 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2005 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2006 #define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2007 #define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2008 #define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2009 #define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2010 #define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2011 #define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2012 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2013 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2014 #define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2015 #define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2016 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2017 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2018 #define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2019 #define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2020 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2021 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2022 #define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2023 #define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2024 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2025 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2026 #define _PRS_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for PRS_SOURCESEL */
<> 150:02e0a0aed4ec 2027 #define _PRS_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for PRS_SOURCESEL */
<> 150:02e0a0aed4ec 2028 #define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2029 #define _PRS_CH_CTRL_SOURCESEL_VCMP 0x00000001UL /**< Mode VCMP for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2030 #define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000002UL /**< Mode ACMP0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2031 #define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000003UL /**< Mode ACMP1 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2032 #define _PRS_CH_CTRL_SOURCESEL_DAC0 0x00000006UL /**< Mode DAC0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2033 #define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2034 #define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000010UL /**< Mode USART0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2035 #define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000011UL /**< Mode USART1 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2036 #define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000012UL /**< Mode USART2 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2037 #define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mode TIMER0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2038 #define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000001DUL /**< Mode TIMER1 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2039 #define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000001EUL /**< Mode TIMER2 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2040 #define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x0000001FUL /**< Mode TIMER3 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2041 #define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000028UL /**< Mode RTC for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2042 #define _PRS_CH_CTRL_SOURCESEL_UART0 0x00000029UL /**< Mode UART0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2043 #define _PRS_CH_CTRL_SOURCESEL_UART1 0x0000002AUL /**< Mode UART1 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2044 #define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000030UL /**< Mode GPIOL for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2045 #define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x00000031UL /**< Mode GPIOH for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2046 #define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x00000034UL /**< Mode LETIMER0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2047 #define _PRS_CH_CTRL_SOURCESEL_BURTC 0x00000037UL /**< Mode BURTC for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2048 #define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000039UL /**< Mode LESENSEL for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2049 #define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x0000003AUL /**< Mode LESENSEH for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2050 #define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000003BUL /**< Mode LESENSED for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2051 #define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2052 #define PRS_CH_CTRL_SOURCESEL_VCMP (_PRS_CH_CTRL_SOURCESEL_VCMP << 16) /**< Shifted mode VCMP for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2053 #define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16) /**< Shifted mode ACMP0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2054 #define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 16) /**< Shifted mode ACMP1 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2055 #define PRS_CH_CTRL_SOURCESEL_DAC0 (_PRS_CH_CTRL_SOURCESEL_DAC0 << 16) /**< Shifted mode DAC0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2056 #define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2057 #define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2058 #define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2059 #define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2060 #define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2061 #define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2062 #define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2063 #define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2064 #define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 16) /**< Shifted mode RTC for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2065 #define PRS_CH_CTRL_SOURCESEL_UART0 (_PRS_CH_CTRL_SOURCESEL_UART0 << 16) /**< Shifted mode UART0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2066 #define PRS_CH_CTRL_SOURCESEL_UART1 (_PRS_CH_CTRL_SOURCESEL_UART1 << 16) /**< Shifted mode UART1 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2067 #define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16) /**< Shifted mode GPIOL for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2068 #define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16) /**< Shifted mode GPIOH for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2069 #define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 16) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2070 #define PRS_CH_CTRL_SOURCESEL_BURTC (_PRS_CH_CTRL_SOURCESEL_BURTC << 16) /**< Shifted mode BURTC for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2071 #define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 16) /**< Shifted mode LESENSEL for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2072 #define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 16) /**< Shifted mode LESENSEH for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2073 #define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 16) /**< Shifted mode LESENSED for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2074 #define _PRS_CH_CTRL_EDSEL_SHIFT 24 /**< Shift value for PRS_EDSEL */
<> 150:02e0a0aed4ec 2075 #define _PRS_CH_CTRL_EDSEL_MASK 0x3000000UL /**< Bit mask for PRS_EDSEL */
<> 150:02e0a0aed4ec 2076 #define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2077 #define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2078 #define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2079 #define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2080 #define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2081 #define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2082 #define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 24) /**< Shifted mode OFF for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2083 #define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 24) /**< Shifted mode POSEDGE for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2084 #define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2085 #define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2086 #define PRS_CH_CTRL_ASYNC (0x1UL << 28) /**< Asynchronous reflex */
<> 150:02e0a0aed4ec 2087 #define _PRS_CH_CTRL_ASYNC_SHIFT 28 /**< Shift value for PRS_ASYNC */
<> 150:02e0a0aed4ec 2088 #define _PRS_CH_CTRL_ASYNC_MASK 0x10000000UL /**< Bit mask for PRS_ASYNC */
<> 150:02e0a0aed4ec 2089 #define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2090 #define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 2091
<> 150:02e0a0aed4ec 2092 /** @} End of group EFM32WG895F128_PRS */
<> 150:02e0a0aed4ec 2093
<> 150:02e0a0aed4ec 2094
<> 150:02e0a0aed4ec 2095
<> 150:02e0a0aed4ec 2096 /**************************************************************************//**
<> 150:02e0a0aed4ec 2097 * @defgroup EFM32WG895F128_UNLOCK EFM32WG895F128 Unlock Codes
<> 150:02e0a0aed4ec 2098 * @{
<> 150:02e0a0aed4ec 2099 *****************************************************************************/
<> 150:02e0a0aed4ec 2100 #define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
<> 150:02e0a0aed4ec 2101 #define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
<> 150:02e0a0aed4ec 2102 #define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
<> 150:02e0a0aed4ec 2103 #define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
<> 150:02e0a0aed4ec 2104 #define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
<> 150:02e0a0aed4ec 2105 #define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */
<> 150:02e0a0aed4ec 2106
<> 150:02e0a0aed4ec 2107 /** @} End of group EFM32WG895F128_UNLOCK */
<> 150:02e0a0aed4ec 2108
<> 150:02e0a0aed4ec 2109 /** @} End of group EFM32WG895F128_BitFields */
<> 150:02e0a0aed4ec 2110
<> 150:02e0a0aed4ec 2111 /**************************************************************************//**
<> 150:02e0a0aed4ec 2112 * @defgroup EFM32WG895F128_Alternate_Function EFM32WG895F128 Alternate Function
<> 150:02e0a0aed4ec 2113 * @{
<> 150:02e0a0aed4ec 2114 *****************************************************************************/
<> 150:02e0a0aed4ec 2115
<> 150:02e0a0aed4ec 2116 #include "efm32wg_af_ports.h"
<> 150:02e0a0aed4ec 2117 #include "efm32wg_af_pins.h"
<> 150:02e0a0aed4ec 2118
<> 150:02e0a0aed4ec 2119 /** @} End of group EFM32WG895F128_Alternate_Function */
<> 150:02e0a0aed4ec 2120
<> 150:02e0a0aed4ec 2121 /**************************************************************************//**
<> 150:02e0a0aed4ec 2122 * @brief Set the value of a bit field within a register.
<> 150:02e0a0aed4ec 2123 *
<> 150:02e0a0aed4ec 2124 * @param REG
<> 150:02e0a0aed4ec 2125 * The register to update
<> 150:02e0a0aed4ec 2126 * @param MASK
<> 150:02e0a0aed4ec 2127 * The mask for the bit field to update
<> 150:02e0a0aed4ec 2128 * @param VALUE
<> 150:02e0a0aed4ec 2129 * The value to write to the bit field
<> 150:02e0a0aed4ec 2130 * @param OFFSET
<> 150:02e0a0aed4ec 2131 * The number of bits that the field is offset within the register.
<> 150:02e0a0aed4ec 2132 * 0 (zero) means LSB.
<> 150:02e0a0aed4ec 2133 *****************************************************************************/
<> 150:02e0a0aed4ec 2134 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
<> 150:02e0a0aed4ec 2135 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
<> 150:02e0a0aed4ec 2136
<> 150:02e0a0aed4ec 2137 /** @} End of group EFM32WG895F128 */
<> 150:02e0a0aed4ec 2138
<> 150:02e0a0aed4ec 2139 /** @} End of group Parts */
<> 150:02e0a0aed4ec 2140
<> 150:02e0a0aed4ec 2141 #ifdef __cplusplus
<> 150:02e0a0aed4ec 2142 }
<> 150:02e0a0aed4ec 2143 #endif
<> 150:02e0a0aed4ec 2144 #endif /* EFM32WG895F128_H */