Fawwaz Nadzmy / mbed-STM

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg332f256.h@153:9398a535854b, 2016-12-22 (annotated)

Committer:
fwndz
Date:
Thu Dec 22 05:12:40 2016 +0000
Revision:
153:9398a535854b
Parent:
150:02e0a0aed4ec 
device target maximize

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 150:02e0a0aed4ec 1 /**************************************************************************//**
<> 150:02e0a0aed4ec 2 * @file efm32wg332f256.h
<> 150:02e0a0aed4ec 3 * @brief CMSIS Cortex-M Peripheral Access Layer Header File
<> 150:02e0a0aed4ec 4 * for EFM32WG332F256
<> 150:02e0a0aed4ec 5 * @version 5.0.0
<> 150:02e0a0aed4ec 6 ******************************************************************************
<> 150:02e0a0aed4ec 7 * @section License
<> 150:02e0a0aed4ec 8 * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 150:02e0a0aed4ec 9 ******************************************************************************
<> 150:02e0a0aed4ec 10 *
<> 150:02e0a0aed4ec 11 * Permission is granted to anyone to use this software for any purpose,
<> 150:02e0a0aed4ec 12 * including commercial applications, and to alter it and redistribute it
<> 150:02e0a0aed4ec 13 * freely, subject to the following restrictions:
<> 150:02e0a0aed4ec 14 *
<> 150:02e0a0aed4ec 15 * 1. The origin of this software must not be misrepresented; you must not
<> 150:02e0a0aed4ec 16 * claim that you wrote the original software.@n
<> 150:02e0a0aed4ec 17 * 2. Altered source versions must be plainly marked as such, and must not be
<> 150:02e0a0aed4ec 18 * misrepresented as being the original software.@n
<> 150:02e0a0aed4ec 19 * 3. This notice may not be removed or altered from any source distribution.
<> 150:02e0a0aed4ec 20 *
<> 150:02e0a0aed4ec 21 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 150:02e0a0aed4ec 22 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 150:02e0a0aed4ec 23 * providing the Software "AS IS", with no express or implied warranties of any
<> 150:02e0a0aed4ec 24 * kind, including, but not limited to, any implied warranties of
<> 150:02e0a0aed4ec 25 * merchantability or fitness for any particular purpose or warranties against
<> 150:02e0a0aed4ec 26 * infringement of any proprietary rights of a third party.
<> 150:02e0a0aed4ec 27 *
<> 150:02e0a0aed4ec 28 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 150:02e0a0aed4ec 29 * incidental, or special damages, or any other relief, or for any claim by
<> 150:02e0a0aed4ec 30 * any third party, arising from your use of this Software.
<> 150:02e0a0aed4ec 31 *
<> 150:02e0a0aed4ec 32 *****************************************************************************/
<> 150:02e0a0aed4ec 33
<> 150:02e0a0aed4ec 34 #ifndef EFM32WG332F256_H
<> 150:02e0a0aed4ec 35 #define EFM32WG332F256_H
<> 150:02e0a0aed4ec 36
<> 150:02e0a0aed4ec 37 #ifdef __cplusplus
<> 150:02e0a0aed4ec 38 extern "C" {
<> 150:02e0a0aed4ec 39 #endif
<> 150:02e0a0aed4ec 40
<> 150:02e0a0aed4ec 41 /**************************************************************************//**
<> 150:02e0a0aed4ec 42 * @addtogroup Parts
<> 150:02e0a0aed4ec 43 * @{
<> 150:02e0a0aed4ec 44 *****************************************************************************/
<> 150:02e0a0aed4ec 45
<> 150:02e0a0aed4ec 46 /**************************************************************************//**
<> 150:02e0a0aed4ec 47 * @defgroup EFM32WG332F256 EFM32WG332F256
<> 150:02e0a0aed4ec 48 * @{
<> 150:02e0a0aed4ec 49 *****************************************************************************/
<> 150:02e0a0aed4ec 50
<> 150:02e0a0aed4ec 51 /** Interrupt Number Definition */
<> 150:02e0a0aed4ec 52 typedef enum IRQn
<> 150:02e0a0aed4ec 53 {
<> 150:02e0a0aed4ec 54 /****** Cortex-M4 Processor Exceptions Numbers ********************************************/
<> 150:02e0a0aed4ec 55 NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */
<> 150:02e0a0aed4ec 56 HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */
<> 150:02e0a0aed4ec 57 MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */
<> 150:02e0a0aed4ec 58 BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */
<> 150:02e0a0aed4ec 59 UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */
<> 150:02e0a0aed4ec 60 SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */
<> 150:02e0a0aed4ec 61 DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */
<> 150:02e0a0aed4ec 62 PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */
<> 150:02e0a0aed4ec 63 SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */
<> 150:02e0a0aed4ec 64
<> 150:02e0a0aed4ec 65 /****** EFM32WG Peripheral Interrupt Numbers **********************************************/
<> 150:02e0a0aed4ec 66 DMA_IRQn = 0, /*!< 0 EFM32 DMA Interrupt */
<> 150:02e0a0aed4ec 67 GPIO_EVEN_IRQn = 1, /*!< 1 EFM32 GPIO_EVEN Interrupt */
<> 150:02e0a0aed4ec 68 TIMER0_IRQn = 2, /*!< 2 EFM32 TIMER0 Interrupt */
<> 150:02e0a0aed4ec 69 USART0_RX_IRQn = 3, /*!< 3 EFM32 USART0_RX Interrupt */
<> 150:02e0a0aed4ec 70 USART0_TX_IRQn = 4, /*!< 4 EFM32 USART0_TX Interrupt */
<> 150:02e0a0aed4ec 71 USB_IRQn = 5, /*!< 5 EFM32 USB Interrupt */
<> 150:02e0a0aed4ec 72 ACMP0_IRQn = 6, /*!< 6 EFM32 ACMP0 Interrupt */
<> 150:02e0a0aed4ec 73 ADC0_IRQn = 7, /*!< 7 EFM32 ADC0 Interrupt */
<> 150:02e0a0aed4ec 74 DAC0_IRQn = 8, /*!< 8 EFM32 DAC0 Interrupt */
<> 150:02e0a0aed4ec 75 I2C0_IRQn = 9, /*!< 9 EFM32 I2C0 Interrupt */
<> 150:02e0a0aed4ec 76 I2C1_IRQn = 10, /*!< 10 EFM32 I2C1 Interrupt */
<> 150:02e0a0aed4ec 77 GPIO_ODD_IRQn = 11, /*!< 11 EFM32 GPIO_ODD Interrupt */
<> 150:02e0a0aed4ec 78 TIMER1_IRQn = 12, /*!< 12 EFM32 TIMER1 Interrupt */
<> 150:02e0a0aed4ec 79 TIMER2_IRQn = 13, /*!< 13 EFM32 TIMER2 Interrupt */
<> 150:02e0a0aed4ec 80 TIMER3_IRQn = 14, /*!< 14 EFM32 TIMER3 Interrupt */
<> 150:02e0a0aed4ec 81 USART1_RX_IRQn = 15, /*!< 15 EFM32 USART1_RX Interrupt */
<> 150:02e0a0aed4ec 82 USART1_TX_IRQn = 16, /*!< 16 EFM32 USART1_TX Interrupt */
<> 150:02e0a0aed4ec 83 LESENSE_IRQn = 17, /*!< 17 EFM32 LESENSE Interrupt */
<> 150:02e0a0aed4ec 84 USART2_RX_IRQn = 18, /*!< 18 EFM32 USART2_RX Interrupt */
<> 150:02e0a0aed4ec 85 USART2_TX_IRQn = 19, /*!< 19 EFM32 USART2_TX Interrupt */
<> 150:02e0a0aed4ec 86 LEUART0_IRQn = 24, /*!< 24 EFM32 LEUART0 Interrupt */
<> 150:02e0a0aed4ec 87 LEUART1_IRQn = 25, /*!< 25 EFM32 LEUART1 Interrupt */
<> 150:02e0a0aed4ec 88 LETIMER0_IRQn = 26, /*!< 26 EFM32 LETIMER0 Interrupt */
<> 150:02e0a0aed4ec 89 PCNT0_IRQn = 27, /*!< 27 EFM32 PCNT0 Interrupt */
<> 150:02e0a0aed4ec 90 PCNT1_IRQn = 28, /*!< 28 EFM32 PCNT1 Interrupt */
<> 150:02e0a0aed4ec 91 PCNT2_IRQn = 29, /*!< 29 EFM32 PCNT2 Interrupt */
<> 150:02e0a0aed4ec 92 RTC_IRQn = 30, /*!< 30 EFM32 RTC Interrupt */
<> 150:02e0a0aed4ec 93 BURTC_IRQn = 31, /*!< 31 EFM32 BURTC Interrupt */
<> 150:02e0a0aed4ec 94 CMU_IRQn = 32, /*!< 32 EFM32 CMU Interrupt */
<> 150:02e0a0aed4ec 95 VCMP_IRQn = 33, /*!< 33 EFM32 VCMP Interrupt */
<> 150:02e0a0aed4ec 96 MSC_IRQn = 35, /*!< 35 EFM32 MSC Interrupt */
<> 150:02e0a0aed4ec 97 AES_IRQn = 36, /*!< 36 EFM32 AES Interrupt */
<> 150:02e0a0aed4ec 98 EMU_IRQn = 38, /*!< 38 EFM32 EMU Interrupt */
<> 150:02e0a0aed4ec 99 FPUEH_IRQn = 39, /*!< 39 EFM32 FPUEH Interrupt */
<> 150:02e0a0aed4ec 100 } IRQn_Type;
<> 150:02e0a0aed4ec 101
<> 150:02e0a0aed4ec 102 /**************************************************************************//**
<> 150:02e0a0aed4ec 103 * @defgroup EFM32WG332F256_Core EFM32WG332F256 Core
<> 150:02e0a0aed4ec 104 * @{
<> 150:02e0a0aed4ec 105 * @brief Processor and Core Peripheral Section
<> 150:02e0a0aed4ec 106 *****************************************************************************/
<> 150:02e0a0aed4ec 107 #define __MPU_PRESENT 1 /**< Presence of MPU */
<> 150:02e0a0aed4ec 108 #define __FPU_PRESENT 1 /**< Presence of FPU */
<> 150:02e0a0aed4ec 109 #define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
<> 150:02e0a0aed4ec 110 #define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
<> 150:02e0a0aed4ec 111 #define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
<> 150:02e0a0aed4ec 112
<> 150:02e0a0aed4ec 113 /** @} End of group EFM32WG332F256_Core */
<> 150:02e0a0aed4ec 114
<> 150:02e0a0aed4ec 115 /**************************************************************************//**
<> 150:02e0a0aed4ec 116 * @defgroup EFM32WG332F256_Part EFM32WG332F256 Part
<> 150:02e0a0aed4ec 117 * @{
<> 150:02e0a0aed4ec 118 ******************************************************************************/
<> 150:02e0a0aed4ec 119
<> 150:02e0a0aed4ec 120 /** Part family */
<> 150:02e0a0aed4ec 121 #define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */
<> 150:02e0a0aed4ec 122 #define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */
<> 150:02e0a0aed4ec 123 #define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */
<> 150:02e0a0aed4ec 124 #define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */
<> 150:02e0a0aed4ec 125 #define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */
<> 150:02e0a0aed4ec 126 #define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */
<> 150:02e0a0aed4ec 127
<> 150:02e0a0aed4ec 128 /* If part number is not defined as compiler option, define it */
<> 150:02e0a0aed4ec 129 #if !defined(EFM32WG332F256)
<> 150:02e0a0aed4ec 130 #define EFM32WG332F256 1 /**< Wonder Gecko Part */
<> 150:02e0a0aed4ec 131 #endif
<> 150:02e0a0aed4ec 132
<> 150:02e0a0aed4ec 133 /** Configure part number */
<> 150:02e0a0aed4ec 134 #define PART_NUMBER "EFM32WG332F256" /**< Part Number */
<> 150:02e0a0aed4ec 135
<> 150:02e0a0aed4ec 136 /** Memory Base addresses and limits */
<> 150:02e0a0aed4ec 137 #define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
<> 150:02e0a0aed4ec 138 #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
<> 150:02e0a0aed4ec 139 #define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
<> 150:02e0a0aed4ec 140 #define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
<> 150:02e0a0aed4ec 141 #define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
<> 150:02e0a0aed4ec 142 #define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
<> 150:02e0a0aed4ec 143 #define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
<> 150:02e0a0aed4ec 144 #define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
<> 150:02e0a0aed4ec 145 #define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */
<> 150:02e0a0aed4ec 146 #define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */
<> 150:02e0a0aed4ec 147 #define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */
<> 150:02e0a0aed4ec 148 #define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */
<> 150:02e0a0aed4ec 149 #define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */
<> 150:02e0a0aed4ec 150 #define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */
<> 150:02e0a0aed4ec 151 #define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */
<> 150:02e0a0aed4ec 152 #define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */
<> 150:02e0a0aed4ec 153 #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
<> 150:02e0a0aed4ec 154 #define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
<> 150:02e0a0aed4ec 155 #define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
<> 150:02e0a0aed4ec 156 #define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
<> 150:02e0a0aed4ec 157 #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
<> 150:02e0a0aed4ec 158 #define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */
<> 150:02e0a0aed4ec 159 #define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */
<> 150:02e0a0aed4ec 160 #define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */
<> 150:02e0a0aed4ec 161 #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
<> 150:02e0a0aed4ec 162 #define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */
<> 150:02e0a0aed4ec 163 #define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */
<> 150:02e0a0aed4ec 164 #define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */
<> 150:02e0a0aed4ec 165 #define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
<> 150:02e0a0aed4ec 166 #define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */
<> 150:02e0a0aed4ec 167 #define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */
<> 150:02e0a0aed4ec 168 #define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */
<> 150:02e0a0aed4ec 169
<> 150:02e0a0aed4ec 170 /** Bit banding area */
<> 150:02e0a0aed4ec 171 #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
<> 150:02e0a0aed4ec 172 #define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
<> 150:02e0a0aed4ec 173
<> 150:02e0a0aed4ec 174 /** Flash and SRAM limits for EFM32WG332F256 */
<> 150:02e0a0aed4ec 175 #define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
<> 150:02e0a0aed4ec 176 #define FLASH_SIZE (0x00040000UL) /**< Available Flash Memory */
<> 150:02e0a0aed4ec 177 #define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size */
<> 150:02e0a0aed4ec 178 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
<> 150:02e0a0aed4ec 179 #define SRAM_SIZE (0x00008000UL) /**< Available SRAM Memory */
<> 150:02e0a0aed4ec 180 #define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */
<> 150:02e0a0aed4ec 181 #define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
<> 150:02e0a0aed4ec 182 #define DMA_CHAN_COUNT 12 /**< Number of DMA channels */
<> 150:02e0a0aed4ec 183 #define EXT_IRQ_COUNT 40 /**< Number of External (NVIC) interrupts */
<> 150:02e0a0aed4ec 184
<> 150:02e0a0aed4ec 185 /** AF channels connect the different on-chip peripherals with the af-mux */
<> 150:02e0a0aed4ec 186 #define AFCHAN_MAX 163
<> 150:02e0a0aed4ec 187 #define AFCHANLOC_MAX 7
<> 150:02e0a0aed4ec 188 /** Analog AF channels */
<> 150:02e0a0aed4ec 189 #define AFACHAN_MAX 53
<> 150:02e0a0aed4ec 190
<> 150:02e0a0aed4ec 191 /* Part number capabilities */
<> 150:02e0a0aed4ec 192
<> 150:02e0a0aed4ec 193 #define USART_PRESENT /**< USART is available in this part */
<> 150:02e0a0aed4ec 194 #define USART_COUNT 3 /**< 3 USARTs available */
<> 150:02e0a0aed4ec 195 #define TIMER_PRESENT /**< TIMER is available in this part */
<> 150:02e0a0aed4ec 196 #define TIMER_COUNT 4 /**< 4 TIMERs available */
<> 150:02e0a0aed4ec 197 #define ACMP_PRESENT /**< ACMP is available in this part */
<> 150:02e0a0aed4ec 198 #define ACMP_COUNT 2 /**< 2 ACMPs available */
<> 150:02e0a0aed4ec 199 #define LEUART_PRESENT /**< LEUART is available in this part */
<> 150:02e0a0aed4ec 200 #define LEUART_COUNT 2 /**< 2 LEUARTs available */
<> 150:02e0a0aed4ec 201 #define LETIMER_PRESENT /**< LETIMER is available in this part */
<> 150:02e0a0aed4ec 202 #define LETIMER_COUNT 1 /**< 1 LETIMERs available */
<> 150:02e0a0aed4ec 203 #define PCNT_PRESENT /**< PCNT is available in this part */
<> 150:02e0a0aed4ec 204 #define PCNT_COUNT 3 /**< 3 PCNTs available */
<> 150:02e0a0aed4ec 205 #define I2C_PRESENT /**< I2C is available in this part */
<> 150:02e0a0aed4ec 206 #define I2C_COUNT 2 /**< 2 I2Cs available */
<> 150:02e0a0aed4ec 207 #define ADC_PRESENT /**< ADC is available in this part */
<> 150:02e0a0aed4ec 208 #define ADC_COUNT 1 /**< 1 ADCs available */
<> 150:02e0a0aed4ec 209 #define DAC_PRESENT /**< DAC is available in this part */
<> 150:02e0a0aed4ec 210 #define DAC_COUNT 1 /**< 1 DACs available */
<> 150:02e0a0aed4ec 211 #define DMA_PRESENT
<> 150:02e0a0aed4ec 212 #define DMA_COUNT 1
<> 150:02e0a0aed4ec 213 #define AES_PRESENT
<> 150:02e0a0aed4ec 214 #define AES_COUNT 1
<> 150:02e0a0aed4ec 215 #define USBC_PRESENT
<> 150:02e0a0aed4ec 216 #define USBC_COUNT 1
<> 150:02e0a0aed4ec 217 #define USB_PRESENT
<> 150:02e0a0aed4ec 218 #define USB_COUNT 1
<> 150:02e0a0aed4ec 219 #define LE_PRESENT
<> 150:02e0a0aed4ec 220 #define LE_COUNT 1
<> 150:02e0a0aed4ec 221 #define MSC_PRESENT
<> 150:02e0a0aed4ec 222 #define MSC_COUNT 1
<> 150:02e0a0aed4ec 223 #define EMU_PRESENT
<> 150:02e0a0aed4ec 224 #define EMU_COUNT 1
<> 150:02e0a0aed4ec 225 #define RMU_PRESENT
<> 150:02e0a0aed4ec 226 #define RMU_COUNT 1
<> 150:02e0a0aed4ec 227 #define CMU_PRESENT
<> 150:02e0a0aed4ec 228 #define CMU_COUNT 1
<> 150:02e0a0aed4ec 229 #define LESENSE_PRESENT
<> 150:02e0a0aed4ec 230 #define LESENSE_COUNT 1
<> 150:02e0a0aed4ec 231 #define FPUEH_PRESENT
<> 150:02e0a0aed4ec 232 #define FPUEH_COUNT 1
<> 150:02e0a0aed4ec 233 #define RTC_PRESENT
<> 150:02e0a0aed4ec 234 #define RTC_COUNT 1
<> 150:02e0a0aed4ec 235 #define GPIO_PRESENT
<> 150:02e0a0aed4ec 236 #define GPIO_COUNT 1
<> 150:02e0a0aed4ec 237 #define VCMP_PRESENT
<> 150:02e0a0aed4ec 238 #define VCMP_COUNT 1
<> 150:02e0a0aed4ec 239 #define PRS_PRESENT
<> 150:02e0a0aed4ec 240 #define PRS_COUNT 1
<> 150:02e0a0aed4ec 241 #define OPAMP_PRESENT
<> 150:02e0a0aed4ec 242 #define OPAMP_COUNT 1
<> 150:02e0a0aed4ec 243 #define BU_PRESENT
<> 150:02e0a0aed4ec 244 #define BU_COUNT 1
<> 150:02e0a0aed4ec 245 #define BURTC_PRESENT
<> 150:02e0a0aed4ec 246 #define BURTC_COUNT 1
<> 150:02e0a0aed4ec 247 #define HFXTAL_PRESENT
<> 150:02e0a0aed4ec 248 #define HFXTAL_COUNT 1
<> 150:02e0a0aed4ec 249 #define LFXTAL_PRESENT
<> 150:02e0a0aed4ec 250 #define LFXTAL_COUNT 1
<> 150:02e0a0aed4ec 251 #define WDOG_PRESENT
<> 150:02e0a0aed4ec 252 #define WDOG_COUNT 1
<> 150:02e0a0aed4ec 253 #define DBG_PRESENT
<> 150:02e0a0aed4ec 254 #define DBG_COUNT 1
<> 150:02e0a0aed4ec 255 #define ETM_PRESENT
<> 150:02e0a0aed4ec 256 #define ETM_COUNT 1
<> 150:02e0a0aed4ec 257 #define BOOTLOADER_PRESENT
<> 150:02e0a0aed4ec 258 #define BOOTLOADER_COUNT 1
<> 150:02e0a0aed4ec 259 #define ANALOG_PRESENT
<> 150:02e0a0aed4ec 260 #define ANALOG_COUNT 1
<> 150:02e0a0aed4ec 261
<> 150:02e0a0aed4ec 262 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
<> 150:02e0a0aed4ec 263 #include "system_efm32wg.h" /* System Header */
<> 150:02e0a0aed4ec 264
<> 150:02e0a0aed4ec 265 /** @} End of group EFM32WG332F256_Part */
<> 150:02e0a0aed4ec 266
<> 150:02e0a0aed4ec 267 /**************************************************************************//**
<> 150:02e0a0aed4ec 268 * @defgroup EFM32WG332F256_Peripheral_TypeDefs EFM32WG332F256 Peripheral TypeDefs
<> 150:02e0a0aed4ec 269 * @{
<> 150:02e0a0aed4ec 270 * @brief Device Specific Peripheral Register Structures
<> 150:02e0a0aed4ec 271 *****************************************************************************/
<> 150:02e0a0aed4ec 272
<> 150:02e0a0aed4ec 273 #include "efm32wg_dma_ch.h"
<> 150:02e0a0aed4ec 274
<> 150:02e0a0aed4ec 275 /**************************************************************************//**
<> 150:02e0a0aed4ec 276 * @defgroup EFM32WG332F256_DMA EFM32WG332F256 DMA
<> 150:02e0a0aed4ec 277 * @{
<> 150:02e0a0aed4ec 278 * @brief EFM32WG332F256_DMA Register Declaration
<> 150:02e0a0aed4ec 279 *****************************************************************************/
<> 150:02e0a0aed4ec 280 typedef struct
<> 150:02e0a0aed4ec 281 {
<> 150:02e0a0aed4ec 282 __IM uint32_t STATUS; /**< DMA Status Registers */
<> 150:02e0a0aed4ec 283 __OM uint32_t CONFIG; /**< DMA Configuration Register */
<> 150:02e0a0aed4ec 284 __IOM uint32_t CTRLBASE; /**< Channel Control Data Base Pointer Register */
<> 150:02e0a0aed4ec 285 __IM uint32_t ALTCTRLBASE; /**< Channel Alternate Control Data Base Pointer Register */
<> 150:02e0a0aed4ec 286 __IM uint32_t CHWAITSTATUS; /**< Channel Wait on Request Status Register */
<> 150:02e0a0aed4ec 287 __OM uint32_t CHSWREQ; /**< Channel Software Request Register */
<> 150:02e0a0aed4ec 288 __IOM uint32_t CHUSEBURSTS; /**< Channel Useburst Set Register */
<> 150:02e0a0aed4ec 289 __OM uint32_t CHUSEBURSTC; /**< Channel Useburst Clear Register */
<> 150:02e0a0aed4ec 290 __IOM uint32_t CHREQMASKS; /**< Channel Request Mask Set Register */
<> 150:02e0a0aed4ec 291 __OM uint32_t CHREQMASKC; /**< Channel Request Mask Clear Register */
<> 150:02e0a0aed4ec 292 __IOM uint32_t CHENS; /**< Channel Enable Set Register */
<> 150:02e0a0aed4ec 293 __OM uint32_t CHENC; /**< Channel Enable Clear Register */
<> 150:02e0a0aed4ec 294 __IOM uint32_t CHALTS; /**< Channel Alternate Set Register */
<> 150:02e0a0aed4ec 295 __OM uint32_t CHALTC; /**< Channel Alternate Clear Register */
<> 150:02e0a0aed4ec 296 __IOM uint32_t CHPRIS; /**< Channel Priority Set Register */
<> 150:02e0a0aed4ec 297 __OM uint32_t CHPRIC; /**< Channel Priority Clear Register */
<> 150:02e0a0aed4ec 298 uint32_t RESERVED0[3]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 299 __IOM uint32_t ERRORC; /**< Bus Error Clear Register */
<> 150:02e0a0aed4ec 300
<> 150:02e0a0aed4ec 301 uint32_t RESERVED1[880]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 302 __IM uint32_t CHREQSTATUS; /**< Channel Request Status */
<> 150:02e0a0aed4ec 303 uint32_t RESERVED2[1]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 304 __IM uint32_t CHSREQSTATUS; /**< Channel Single Request Status */
<> 150:02e0a0aed4ec 305
<> 150:02e0a0aed4ec 306 uint32_t RESERVED3[121]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 307 __IM uint32_t IF; /**< Interrupt Flag Register */
<> 150:02e0a0aed4ec 308 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
<> 150:02e0a0aed4ec 309 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
<> 150:02e0a0aed4ec 310 __IOM uint32_t IEN; /**< Interrupt Enable register */
<> 150:02e0a0aed4ec 311 __IOM uint32_t CTRL; /**< DMA Control Register */
<> 150:02e0a0aed4ec 312 __IOM uint32_t RDS; /**< DMA Retain Descriptor State */
<> 150:02e0a0aed4ec 313
<> 150:02e0a0aed4ec 314 uint32_t RESERVED4[2]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 315 __IOM uint32_t LOOP0; /**< Channel 0 Loop Register */
<> 150:02e0a0aed4ec 316 __IOM uint32_t LOOP1; /**< Channel 1 Loop Register */
<> 150:02e0a0aed4ec 317 uint32_t RESERVED5[14]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 318 __IOM uint32_t RECT0; /**< Channel 0 Rectangle Register */
<> 150:02e0a0aed4ec 319
<> 150:02e0a0aed4ec 320 uint32_t RESERVED6[39]; /**< Reserved registers */
<> 150:02e0a0aed4ec 321 DMA_CH_TypeDef CH[12]; /**< Channel registers */
<> 150:02e0a0aed4ec 322 } DMA_TypeDef; /** @} */
<> 150:02e0a0aed4ec 323
<> 150:02e0a0aed4ec 324 #include "efm32wg_aes.h"
<> 150:02e0a0aed4ec 325 #include "efm32wg_usb_hc.h"
<> 150:02e0a0aed4ec 326 #include "efm32wg_usb_diep.h"
<> 150:02e0a0aed4ec 327 #include "efm32wg_usb_doep.h"
<> 150:02e0a0aed4ec 328 #include "efm32wg_usb.h"
<> 150:02e0a0aed4ec 329 #include "efm32wg_msc.h"
<> 150:02e0a0aed4ec 330 #include "efm32wg_emu.h"
<> 150:02e0a0aed4ec 331 #include "efm32wg_rmu.h"
<> 150:02e0a0aed4ec 332
<> 150:02e0a0aed4ec 333 /**************************************************************************//**
<> 150:02e0a0aed4ec 334 * @defgroup EFM32WG332F256_CMU EFM32WG332F256 CMU
<> 150:02e0a0aed4ec 335 * @{
<> 150:02e0a0aed4ec 336 * @brief EFM32WG332F256_CMU Register Declaration
<> 150:02e0a0aed4ec 337 *****************************************************************************/
<> 150:02e0a0aed4ec 338 typedef struct
<> 150:02e0a0aed4ec 339 {
<> 150:02e0a0aed4ec 340 __IOM uint32_t CTRL; /**< CMU Control Register */
<> 150:02e0a0aed4ec 341 __IOM uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register */
<> 150:02e0a0aed4ec 342 __IOM uint32_t HFPERCLKDIV; /**< High Frequency Peripheral Clock Division Register */
<> 150:02e0a0aed4ec 343 __IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */
<> 150:02e0a0aed4ec 344 __IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */
<> 150:02e0a0aed4ec 345 __IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */
<> 150:02e0a0aed4ec 346 __IOM uint32_t CALCTRL; /**< Calibration Control Register */
<> 150:02e0a0aed4ec 347 __IOM uint32_t CALCNT; /**< Calibration Counter Register */
<> 150:02e0a0aed4ec 348 __IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */
<> 150:02e0a0aed4ec 349 __IOM uint32_t CMD; /**< Command Register */
<> 150:02e0a0aed4ec 350 __IOM uint32_t LFCLKSEL; /**< Low Frequency Clock Select Register */
<> 150:02e0a0aed4ec 351 __IM uint32_t STATUS; /**< Status Register */
<> 150:02e0a0aed4ec 352 __IM uint32_t IF; /**< Interrupt Flag Register */
<> 150:02e0a0aed4ec 353 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
<> 150:02e0a0aed4ec 354 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
<> 150:02e0a0aed4ec 355 __IOM uint32_t IEN; /**< Interrupt Enable Register */
<> 150:02e0a0aed4ec 356 __IOM uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0 */
<> 150:02e0a0aed4ec 357 __IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */
<> 150:02e0a0aed4ec 358 uint32_t RESERVED0[2]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 359 __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
<> 150:02e0a0aed4ec 360 __IOM uint32_t FREEZE; /**< Freeze Register */
<> 150:02e0a0aed4ec 361 __IOM uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */
<> 150:02e0a0aed4ec 362 uint32_t RESERVED1[1]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 363 __IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */
<> 150:02e0a0aed4ec 364
<> 150:02e0a0aed4ec 365 uint32_t RESERVED2[1]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 366 __IOM uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */
<> 150:02e0a0aed4ec 367 uint32_t RESERVED3[1]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 368 __IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */
<> 150:02e0a0aed4ec 369 uint32_t RESERVED4[1]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 370 __IOM uint32_t PCNTCTRL; /**< PCNT Control Register */
<> 150:02e0a0aed4ec 371
<> 150:02e0a0aed4ec 372 uint32_t RESERVED5[1]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 373 __IOM uint32_t ROUTE; /**< I/O Routing Register */
<> 150:02e0a0aed4ec 374 __IOM uint32_t LOCK; /**< Configuration Lock Register */
<> 150:02e0a0aed4ec 375 } CMU_TypeDef; /** @} */
<> 150:02e0a0aed4ec 376
<> 150:02e0a0aed4ec 377 #include "efm32wg_lesense_st.h"
<> 150:02e0a0aed4ec 378 #include "efm32wg_lesense_buf.h"
<> 150:02e0a0aed4ec 379 #include "efm32wg_lesense_ch.h"
<> 150:02e0a0aed4ec 380 #include "efm32wg_lesense.h"
<> 150:02e0a0aed4ec 381 #include "efm32wg_fpueh.h"
<> 150:02e0a0aed4ec 382 #include "efm32wg_usart.h"
<> 150:02e0a0aed4ec 383 #include "efm32wg_timer_cc.h"
<> 150:02e0a0aed4ec 384 #include "efm32wg_timer.h"
<> 150:02e0a0aed4ec 385 #include "efm32wg_acmp.h"
<> 150:02e0a0aed4ec 386 #include "efm32wg_leuart.h"
<> 150:02e0a0aed4ec 387 #include "efm32wg_rtc.h"
<> 150:02e0a0aed4ec 388 #include "efm32wg_letimer.h"
<> 150:02e0a0aed4ec 389 #include "efm32wg_pcnt.h"
<> 150:02e0a0aed4ec 390 #include "efm32wg_i2c.h"
<> 150:02e0a0aed4ec 391 #include "efm32wg_gpio_p.h"
<> 150:02e0a0aed4ec 392 #include "efm32wg_gpio.h"
<> 150:02e0a0aed4ec 393 #include "efm32wg_vcmp.h"
<> 150:02e0a0aed4ec 394 #include "efm32wg_prs_ch.h"
<> 150:02e0a0aed4ec 395
<> 150:02e0a0aed4ec 396 /**************************************************************************//**
<> 150:02e0a0aed4ec 397 * @defgroup EFM32WG332F256_PRS EFM32WG332F256 PRS
<> 150:02e0a0aed4ec 398 * @{
<> 150:02e0a0aed4ec 399 * @brief EFM32WG332F256_PRS Register Declaration
<> 150:02e0a0aed4ec 400 *****************************************************************************/
<> 150:02e0a0aed4ec 401 typedef struct
<> 150:02e0a0aed4ec 402 {
<> 150:02e0a0aed4ec 403 __IOM uint32_t SWPULSE; /**< Software Pulse Register */
<> 150:02e0a0aed4ec 404 __IOM uint32_t SWLEVEL; /**< Software Level Register */
<> 150:02e0a0aed4ec 405 __IOM uint32_t ROUTE; /**< I/O Routing Register */
<> 150:02e0a0aed4ec 406
<> 150:02e0a0aed4ec 407 uint32_t RESERVED0[1]; /**< Reserved registers */
<> 150:02e0a0aed4ec 408 PRS_CH_TypeDef CH[12]; /**< Channel registers */
<> 150:02e0a0aed4ec 409 } PRS_TypeDef; /** @} */
<> 150:02e0a0aed4ec 410
<> 150:02e0a0aed4ec 411 #include "efm32wg_adc.h"
<> 150:02e0a0aed4ec 412 #include "efm32wg_dac.h"
<> 150:02e0a0aed4ec 413 #include "efm32wg_burtc_ret.h"
<> 150:02e0a0aed4ec 414 #include "efm32wg_burtc.h"
<> 150:02e0a0aed4ec 415 #include "efm32wg_wdog.h"
<> 150:02e0a0aed4ec 416 #include "efm32wg_etm.h"
<> 150:02e0a0aed4ec 417 #include "efm32wg_dma_descriptor.h"
<> 150:02e0a0aed4ec 418 #include "efm32wg_devinfo.h"
<> 150:02e0a0aed4ec 419 #include "efm32wg_romtable.h"
<> 150:02e0a0aed4ec 420 #include "efm32wg_calibrate.h"
<> 150:02e0a0aed4ec 421
<> 150:02e0a0aed4ec 422 /** @} End of group EFM32WG332F256_Peripheral_TypeDefs */
<> 150:02e0a0aed4ec 423
<> 150:02e0a0aed4ec 424 /**************************************************************************//**
<> 150:02e0a0aed4ec 425 * @defgroup EFM32WG332F256_Peripheral_Base EFM32WG332F256 Peripheral Memory Map
<> 150:02e0a0aed4ec 426 * @{
<> 150:02e0a0aed4ec 427 *****************************************************************************/
<> 150:02e0a0aed4ec 428
<> 150:02e0a0aed4ec 429 #define DMA_BASE (0x400C2000UL) /**< DMA base address */
<> 150:02e0a0aed4ec 430 #define AES_BASE (0x400E0000UL) /**< AES base address */
<> 150:02e0a0aed4ec 431 #define USB_BASE (0x400C4000UL) /**< USB base address */
<> 150:02e0a0aed4ec 432 #define MSC_BASE (0x400C0000UL) /**< MSC base address */
<> 150:02e0a0aed4ec 433 #define EMU_BASE (0x400C6000UL) /**< EMU base address */
<> 150:02e0a0aed4ec 434 #define RMU_BASE (0x400CA000UL) /**< RMU base address */
<> 150:02e0a0aed4ec 435 #define CMU_BASE (0x400C8000UL) /**< CMU base address */
<> 150:02e0a0aed4ec 436 #define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */
<> 150:02e0a0aed4ec 437 #define FPUEH_BASE (0x400C1C00UL) /**< FPUEH base address */
<> 150:02e0a0aed4ec 438 #define USART0_BASE (0x4000C000UL) /**< USART0 base address */
<> 150:02e0a0aed4ec 439 #define USART1_BASE (0x4000C400UL) /**< USART1 base address */
<> 150:02e0a0aed4ec 440 #define USART2_BASE (0x4000C800UL) /**< USART2 base address */
<> 150:02e0a0aed4ec 441 #define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */
<> 150:02e0a0aed4ec 442 #define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */
<> 150:02e0a0aed4ec 443 #define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */
<> 150:02e0a0aed4ec 444 #define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */
<> 150:02e0a0aed4ec 445 #define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */
<> 150:02e0a0aed4ec 446 #define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */
<> 150:02e0a0aed4ec 447 #define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */
<> 150:02e0a0aed4ec 448 #define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */
<> 150:02e0a0aed4ec 449 #define RTC_BASE (0x40080000UL) /**< RTC base address */
<> 150:02e0a0aed4ec 450 #define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */
<> 150:02e0a0aed4ec 451 #define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */
<> 150:02e0a0aed4ec 452 #define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */
<> 150:02e0a0aed4ec 453 #define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */
<> 150:02e0a0aed4ec 454 #define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */
<> 150:02e0a0aed4ec 455 #define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */
<> 150:02e0a0aed4ec 456 #define GPIO_BASE (0x40006000UL) /**< GPIO base address */
<> 150:02e0a0aed4ec 457 #define VCMP_BASE (0x40000000UL) /**< VCMP base address */
<> 150:02e0a0aed4ec 458 #define PRS_BASE (0x400CC000UL) /**< PRS base address */
<> 150:02e0a0aed4ec 459 #define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
<> 150:02e0a0aed4ec 460 #define DAC0_BASE (0x40004000UL) /**< DAC0 base address */
<> 150:02e0a0aed4ec 461 #define BURTC_BASE (0x40081000UL) /**< BURTC base address */
<> 150:02e0a0aed4ec 462 #define WDOG_BASE (0x40088000UL) /**< WDOG base address */
<> 150:02e0a0aed4ec 463 #define ETM_BASE (0xE0041000UL) /**< ETM base address */
<> 150:02e0a0aed4ec 464 #define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */
<> 150:02e0a0aed4ec 465 #define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
<> 150:02e0a0aed4ec 466 #define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
<> 150:02e0a0aed4ec 467 #define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
<> 150:02e0a0aed4ec 468 #define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
<> 150:02e0a0aed4ec 469
<> 150:02e0a0aed4ec 470 /** @} End of group EFM32WG332F256_Peripheral_Base */
<> 150:02e0a0aed4ec 471
<> 150:02e0a0aed4ec 472 /**************************************************************************//**
<> 150:02e0a0aed4ec 473 * @defgroup EFM32WG332F256_Peripheral_Declaration EFM32WG332F256 Peripheral Declarations
<> 150:02e0a0aed4ec 474 * @{
<> 150:02e0a0aed4ec 475 *****************************************************************************/
<> 150:02e0a0aed4ec 476
<> 150:02e0a0aed4ec 477 #define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
<> 150:02e0a0aed4ec 478 #define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
<> 150:02e0a0aed4ec 479 #define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */
<> 150:02e0a0aed4ec 480 #define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
<> 150:02e0a0aed4ec 481 #define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
<> 150:02e0a0aed4ec 482 #define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
<> 150:02e0a0aed4ec 483 #define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
<> 150:02e0a0aed4ec 484 #define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */
<> 150:02e0a0aed4ec 485 #define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */
<> 150:02e0a0aed4ec 486 #define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
<> 150:02e0a0aed4ec 487 #define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
<> 150:02e0a0aed4ec 488 #define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
<> 150:02e0a0aed4ec 489 #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
<> 150:02e0a0aed4ec 490 #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
<> 150:02e0a0aed4ec 491 #define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
<> 150:02e0a0aed4ec 492 #define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */
<> 150:02e0a0aed4ec 493 #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
<> 150:02e0a0aed4ec 494 #define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
<> 150:02e0a0aed4ec 495 #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
<> 150:02e0a0aed4ec 496 #define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
<> 150:02e0a0aed4ec 497 #define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
<> 150:02e0a0aed4ec 498 #define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
<> 150:02e0a0aed4ec 499 #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
<> 150:02e0a0aed4ec 500 #define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
<> 150:02e0a0aed4ec 501 #define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
<> 150:02e0a0aed4ec 502 #define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
<> 150:02e0a0aed4ec 503 #define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */
<> 150:02e0a0aed4ec 504 #define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
<> 150:02e0a0aed4ec 505 #define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
<> 150:02e0a0aed4ec 506 #define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
<> 150:02e0a0aed4ec 507 #define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
<> 150:02e0a0aed4ec 508 #define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
<> 150:02e0a0aed4ec 509 #define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */
<> 150:02e0a0aed4ec 510 #define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
<> 150:02e0a0aed4ec 511 #define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */
<> 150:02e0a0aed4ec 512 #define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
<> 150:02e0a0aed4ec 513 #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
<> 150:02e0a0aed4ec 514 #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
<> 150:02e0a0aed4ec 515
<> 150:02e0a0aed4ec 516 /** @} End of group EFM32WG332F256_Peripheral_Declaration */
<> 150:02e0a0aed4ec 517
<> 150:02e0a0aed4ec 518 /**************************************************************************//**
<> 150:02e0a0aed4ec 519 * @defgroup EFM32WG332F256_BitFields EFM32WG332F256 Bit Fields
<> 150:02e0a0aed4ec 520 * @{
<> 150:02e0a0aed4ec 521 *****************************************************************************/
<> 150:02e0a0aed4ec 522
<> 150:02e0a0aed4ec 523 /**************************************************************************//**
<> 150:02e0a0aed4ec 524 * @addtogroup EFM32WG332F256_PRS_Signals
<> 150:02e0a0aed4ec 525 * @{
<> 150:02e0a0aed4ec 526 * @brief PRS Signal names
<> 150:02e0a0aed4ec 527 *****************************************************************************/
<> 150:02e0a0aed4ec 528 #define PRS_VCMP_OUT ((1 << 16) + 0) /**< PRS Voltage comparator output */
<> 150:02e0a0aed4ec 529 #define PRS_ACMP0_OUT ((2 << 16) + 0) /**< PRS Analog comparator output */
<> 150:02e0a0aed4ec 530 #define PRS_ACMP1_OUT ((3 << 16) + 0) /**< PRS Analog comparator output */
<> 150:02e0a0aed4ec 531 #define PRS_DAC0_CH0 ((6 << 16) + 0) /**< PRS DAC ch0 conversion done */
<> 150:02e0a0aed4ec 532 #define PRS_DAC0_CH1 ((6 << 16) + 1) /**< PRS DAC ch1 conversion done */
<> 150:02e0a0aed4ec 533 #define PRS_ADC0_SINGLE ((8 << 16) + 0) /**< PRS ADC single conversion done */
<> 150:02e0a0aed4ec 534 #define PRS_ADC0_SCAN ((8 << 16) + 1) /**< PRS ADC scan conversion done */
<> 150:02e0a0aed4ec 535 #define PRS_USART0_IRTX ((16 << 16) + 0) /**< PRS USART 0 IRDA out */
<> 150:02e0a0aed4ec 536 #define PRS_USART0_TXC ((16 << 16) + 1) /**< PRS USART 0 TX complete */
<> 150:02e0a0aed4ec 537 #define PRS_USART0_RXDATAV ((16 << 16) + 2) /**< PRS USART 0 RX Data Valid */
<> 150:02e0a0aed4ec 538 #define PRS_USART1_TXC ((17 << 16) + 1) /**< PRS USART 1 TX complete */
<> 150:02e0a0aed4ec 539 #define PRS_USART1_RXDATAV ((17 << 16) + 2) /**< PRS USART 1 RX Data Valid */
<> 150:02e0a0aed4ec 540 #define PRS_USART2_TXC ((18 << 16) + 1) /**< PRS USART 2 TX complete */
<> 150:02e0a0aed4ec 541 #define PRS_USART2_RXDATAV ((18 << 16) + 2) /**< PRS USART 2 RX Data Valid */
<> 150:02e0a0aed4ec 542 #define PRS_TIMER0_UF ((28 << 16) + 0) /**< PRS Timer 0 Underflow */
<> 150:02e0a0aed4ec 543 #define PRS_TIMER0_OF ((28 << 16) + 1) /**< PRS Timer 0 Overflow */
<> 150:02e0a0aed4ec 544 #define PRS_TIMER0_CC0 ((28 << 16) + 2) /**< PRS Timer 0 Compare/Capture 0 */
<> 150:02e0a0aed4ec 545 #define PRS_TIMER0_CC1 ((28 << 16) + 3) /**< PRS Timer 0 Compare/Capture 1 */
<> 150:02e0a0aed4ec 546 #define PRS_TIMER0_CC2 ((28 << 16) + 4) /**< PRS Timer 0 Compare/Capture 2 */
<> 150:02e0a0aed4ec 547 #define PRS_TIMER1_UF ((29 << 16) + 0) /**< PRS Timer 1 Underflow */
<> 150:02e0a0aed4ec 548 #define PRS_TIMER1_OF ((29 << 16) + 1) /**< PRS Timer 1 Overflow */
<> 150:02e0a0aed4ec 549 #define PRS_TIMER1_CC0 ((29 << 16) + 2) /**< PRS Timer 1 Compare/Capture 0 */
<> 150:02e0a0aed4ec 550 #define PRS_TIMER1_CC1 ((29 << 16) + 3) /**< PRS Timer 1 Compare/Capture 1 */
<> 150:02e0a0aed4ec 551 #define PRS_TIMER1_CC2 ((29 << 16) + 4) /**< PRS Timer 1 Compare/Capture 2 */
<> 150:02e0a0aed4ec 552 #define PRS_TIMER2_UF ((30 << 16) + 0) /**< PRS Timer 2 Underflow */
<> 150:02e0a0aed4ec 553 #define PRS_TIMER2_OF ((30 << 16) + 1) /**< PRS Timer 2 Overflow */
<> 150:02e0a0aed4ec 554 #define PRS_TIMER2_CC0 ((30 << 16) + 2) /**< PRS Timer 2 Compare/Capture 0 */
<> 150:02e0a0aed4ec 555 #define PRS_TIMER2_CC1 ((30 << 16) + 3) /**< PRS Timer 2 Compare/Capture 1 */
<> 150:02e0a0aed4ec 556 #define PRS_TIMER2_CC2 ((30 << 16) + 4) /**< PRS Timer 2 Compare/Capture 2 */
<> 150:02e0a0aed4ec 557 #define PRS_TIMER3_UF ((31 << 16) + 0) /**< PRS Timer 3 Underflow */
<> 150:02e0a0aed4ec 558 #define PRS_TIMER3_OF ((31 << 16) + 1) /**< PRS Timer 3 Overflow */
<> 150:02e0a0aed4ec 559 #define PRS_TIMER3_CC0 ((31 << 16) + 2) /**< PRS Timer 3 Compare/Capture 0 */
<> 150:02e0a0aed4ec 560 #define PRS_TIMER3_CC1 ((31 << 16) + 3) /**< PRS Timer 3 Compare/Capture 1 */
<> 150:02e0a0aed4ec 561 #define PRS_TIMER3_CC2 ((31 << 16) + 4) /**< PRS Timer 3 Compare/Capture 2 */
<> 150:02e0a0aed4ec 562 #define PRS_USB_SOF ((36 << 16) + 0) /**< PRS USB Start of Frame */
<> 150:02e0a0aed4ec 563 #define PRS_USB_SOFSR ((36 << 16) + 1) /**< PRS USB Start of Frame Sent/Received */
<> 150:02e0a0aed4ec 564 #define PRS_RTC_OF ((40 << 16) + 0) /**< PRS RTC Overflow */
<> 150:02e0a0aed4ec 565 #define PRS_RTC_COMP0 ((40 << 16) + 1) /**< PRS RTC Compare 0 */
<> 150:02e0a0aed4ec 566 #define PRS_RTC_COMP1 ((40 << 16) + 2) /**< PRS RTC Compare 1 */
<> 150:02e0a0aed4ec 567 #define PRS_GPIO_PIN0 ((48 << 16) + 0) /**< PRS GPIO pin 0 */
<> 150:02e0a0aed4ec 568 #define PRS_GPIO_PIN1 ((48 << 16) + 1) /**< PRS GPIO pin 1 */
<> 150:02e0a0aed4ec 569 #define PRS_GPIO_PIN2 ((48 << 16) + 2) /**< PRS GPIO pin 2 */
<> 150:02e0a0aed4ec 570 #define PRS_GPIO_PIN3 ((48 << 16) + 3) /**< PRS GPIO pin 3 */
<> 150:02e0a0aed4ec 571 #define PRS_GPIO_PIN4 ((48 << 16) + 4) /**< PRS GPIO pin 4 */
<> 150:02e0a0aed4ec 572 #define PRS_GPIO_PIN5 ((48 << 16) + 5) /**< PRS GPIO pin 5 */
<> 150:02e0a0aed4ec 573 #define PRS_GPIO_PIN6 ((48 << 16) + 6) /**< PRS GPIO pin 6 */
<> 150:02e0a0aed4ec 574 #define PRS_GPIO_PIN7 ((48 << 16) + 7) /**< PRS GPIO pin 7 */
<> 150:02e0a0aed4ec 575 #define PRS_GPIO_PIN8 ((49 << 16) + 0) /**< PRS GPIO pin 8 */
<> 150:02e0a0aed4ec 576 #define PRS_GPIO_PIN9 ((49 << 16) + 1) /**< PRS GPIO pin 9 */
<> 150:02e0a0aed4ec 577 #define PRS_GPIO_PIN10 ((49 << 16) + 2) /**< PRS GPIO pin 10 */
<> 150:02e0a0aed4ec 578 #define PRS_GPIO_PIN11 ((49 << 16) + 3) /**< PRS GPIO pin 11 */
<> 150:02e0a0aed4ec 579 #define PRS_GPIO_PIN12 ((49 << 16) + 4) /**< PRS GPIO pin 12 */
<> 150:02e0a0aed4ec 580 #define PRS_GPIO_PIN13 ((49 << 16) + 5) /**< PRS GPIO pin 13 */
<> 150:02e0a0aed4ec 581 #define PRS_GPIO_PIN14 ((49 << 16) + 6) /**< PRS GPIO pin 14 */
<> 150:02e0a0aed4ec 582 #define PRS_GPIO_PIN15 ((49 << 16) + 7) /**< PRS GPIO pin 15 */
<> 150:02e0a0aed4ec 583 #define PRS_LETIMER0_CH0 ((52 << 16) + 0) /**< PRS LETIMER CH0 Out */
<> 150:02e0a0aed4ec 584 #define PRS_LETIMER0_CH1 ((52 << 16) + 1) /**< PRS LETIMER CH1 Out */
<> 150:02e0a0aed4ec 585 #define PRS_BURTC_OF ((55 << 16) + 0) /**< PRS BURTC Overflow */
<> 150:02e0a0aed4ec 586 #define PRS_BURTC_COMP0 ((55 << 16) + 1) /**< PRS BURTC Compare 0 */
<> 150:02e0a0aed4ec 587 #define PRS_LESENSE_SCANRES0 ((57 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 0 */
<> 150:02e0a0aed4ec 588 #define PRS_LESENSE_SCANRES1 ((57 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 1 */
<> 150:02e0a0aed4ec 589 #define PRS_LESENSE_SCANRES2 ((57 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 2 */
<> 150:02e0a0aed4ec 590 #define PRS_LESENSE_SCANRES3 ((57 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 3 */
<> 150:02e0a0aed4ec 591 #define PRS_LESENSE_SCANRES4 ((57 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 4 */
<> 150:02e0a0aed4ec 592 #define PRS_LESENSE_SCANRES5 ((57 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 5 */
<> 150:02e0a0aed4ec 593 #define PRS_LESENSE_SCANRES6 ((57 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 6 */
<> 150:02e0a0aed4ec 594 #define PRS_LESENSE_SCANRES7 ((57 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 7 */
<> 150:02e0a0aed4ec 595 #define PRS_LESENSE_SCANRES8 ((58 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 8 */
<> 150:02e0a0aed4ec 596 #define PRS_LESENSE_SCANRES9 ((58 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 9 */
<> 150:02e0a0aed4ec 597 #define PRS_LESENSE_SCANRES10 ((58 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 10 */
<> 150:02e0a0aed4ec 598 #define PRS_LESENSE_SCANRES11 ((58 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 11 */
<> 150:02e0a0aed4ec 599 #define PRS_LESENSE_SCANRES12 ((58 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 12 */
<> 150:02e0a0aed4ec 600 #define PRS_LESENSE_SCANRES13 ((58 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 13 */
<> 150:02e0a0aed4ec 601 #define PRS_LESENSE_SCANRES14 ((58 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 14 */
<> 150:02e0a0aed4ec 602 #define PRS_LESENSE_SCANRES15 ((58 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 15 */
<> 150:02e0a0aed4ec 603 #define PRS_LESENSE_DEC0 ((59 << 16) + 0) /**< PRS LESENSE Decoder PRS out 0 */
<> 150:02e0a0aed4ec 604 #define PRS_LESENSE_DEC1 ((59 << 16) + 1) /**< PRS LESENSE Decoder PRS out 1 */
<> 150:02e0a0aed4ec 605 #define PRS_LESENSE_DEC2 ((59 << 16) + 2) /**< PRS LESENSE Decoder PRS out 2 */
<> 150:02e0a0aed4ec 606
<> 150:02e0a0aed4ec 607 /** @} End of group EFM32WG332F256_PRS */
<> 150:02e0a0aed4ec 608
<> 150:02e0a0aed4ec 609 #include "efm32wg_dmareq.h"
<> 150:02e0a0aed4ec 610 #include "efm32wg_dmactrl.h"
<> 150:02e0a0aed4ec 611
<> 150:02e0a0aed4ec 612 /**************************************************************************//**
<> 150:02e0a0aed4ec 613 * @defgroup EFM32WG332F256_DMA_BitFields EFM32WG332F256_DMA Bit Fields
<> 150:02e0a0aed4ec 614 * @{
<> 150:02e0a0aed4ec 615 *****************************************************************************/
<> 150:02e0a0aed4ec 616
<> 150:02e0a0aed4ec 617 /* Bit fields for DMA STATUS */
<> 150:02e0a0aed4ec 618 #define _DMA_STATUS_RESETVALUE 0x100B0000UL /**< Default value for DMA_STATUS */
<> 150:02e0a0aed4ec 619 #define _DMA_STATUS_MASK 0x001F00F1UL /**< Mask for DMA_STATUS */
<> 150:02e0a0aed4ec 620 #define DMA_STATUS_EN (0x1UL << 0) /**< DMA Enable Status */
<> 150:02e0a0aed4ec 621 #define _DMA_STATUS_EN_SHIFT 0 /**< Shift value for DMA_EN */
<> 150:02e0a0aed4ec 622 #define _DMA_STATUS_EN_MASK 0x1UL /**< Bit mask for DMA_EN */
<> 150:02e0a0aed4ec 623 #define _DMA_STATUS_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_STATUS */
<> 150:02e0a0aed4ec 624 #define DMA_STATUS_EN_DEFAULT (_DMA_STATUS_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_STATUS */
<> 150:02e0a0aed4ec 625 #define _DMA_STATUS_STATE_SHIFT 4 /**< Shift value for DMA_STATE */
<> 150:02e0a0aed4ec 626 #define _DMA_STATUS_STATE_MASK 0xF0UL /**< Bit mask for DMA_STATE */
<> 150:02e0a0aed4ec 627 #define _DMA_STATUS_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_STATUS */
<> 150:02e0a0aed4ec 628 #define _DMA_STATUS_STATE_IDLE 0x00000000UL /**< Mode IDLE for DMA_STATUS */
<> 150:02e0a0aed4ec 629 #define _DMA_STATUS_STATE_RDCHCTRLDATA 0x00000001UL /**< Mode RDCHCTRLDATA for DMA_STATUS */
<> 150:02e0a0aed4ec 630 #define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL /**< Mode RDSRCENDPTR for DMA_STATUS */
<> 150:02e0a0aed4ec 631 #define _DMA_STATUS_STATE_RDDSTENDPTR 0x00000003UL /**< Mode RDDSTENDPTR for DMA_STATUS */
<> 150:02e0a0aed4ec 632 #define _DMA_STATUS_STATE_RDSRCDATA 0x00000004UL /**< Mode RDSRCDATA for DMA_STATUS */
<> 150:02e0a0aed4ec 633 #define _DMA_STATUS_STATE_WRDSTDATA 0x00000005UL /**< Mode WRDSTDATA for DMA_STATUS */
<> 150:02e0a0aed4ec 634 #define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL /**< Mode WAITREQCLR for DMA_STATUS */
<> 150:02e0a0aed4ec 635 #define _DMA_STATUS_STATE_WRCHCTRLDATA 0x00000007UL /**< Mode WRCHCTRLDATA for DMA_STATUS */
<> 150:02e0a0aed4ec 636 #define _DMA_STATUS_STATE_STALLED 0x00000008UL /**< Mode STALLED for DMA_STATUS */
<> 150:02e0a0aed4ec 637 #define _DMA_STATUS_STATE_DONE 0x00000009UL /**< Mode DONE for DMA_STATUS */
<> 150:02e0a0aed4ec 638 #define _DMA_STATUS_STATE_PERSCATTRANS 0x0000000AUL /**< Mode PERSCATTRANS for DMA_STATUS */
<> 150:02e0a0aed4ec 639 #define DMA_STATUS_STATE_DEFAULT (_DMA_STATUS_STATE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_STATUS */
<> 150:02e0a0aed4ec 640 #define DMA_STATUS_STATE_IDLE (_DMA_STATUS_STATE_IDLE << 4) /**< Shifted mode IDLE for DMA_STATUS */
<> 150:02e0a0aed4ec 641 #define DMA_STATUS_STATE_RDCHCTRLDATA (_DMA_STATUS_STATE_RDCHCTRLDATA << 4) /**< Shifted mode RDCHCTRLDATA for DMA_STATUS */
<> 150:02e0a0aed4ec 642 #define DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4) /**< Shifted mode RDSRCENDPTR for DMA_STATUS */
<> 150:02e0a0aed4ec 643 #define DMA_STATUS_STATE_RDDSTENDPTR (_DMA_STATUS_STATE_RDDSTENDPTR << 4) /**< Shifted mode RDDSTENDPTR for DMA_STATUS */
<> 150:02e0a0aed4ec 644 #define DMA_STATUS_STATE_RDSRCDATA (_DMA_STATUS_STATE_RDSRCDATA << 4) /**< Shifted mode RDSRCDATA for DMA_STATUS */
<> 150:02e0a0aed4ec 645 #define DMA_STATUS_STATE_WRDSTDATA (_DMA_STATUS_STATE_WRDSTDATA << 4) /**< Shifted mode WRDSTDATA for DMA_STATUS */
<> 150:02e0a0aed4ec 646 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< Shifted mode WAITREQCLR for DMA_STATUS */
<> 150:02e0a0aed4ec 647 #define DMA_STATUS_STATE_WRCHCTRLDATA (_DMA_STATUS_STATE_WRCHCTRLDATA << 4) /**< Shifted mode WRCHCTRLDATA for DMA_STATUS */
<> 150:02e0a0aed4ec 648 #define DMA_STATUS_STATE_STALLED (_DMA_STATUS_STATE_STALLED << 4) /**< Shifted mode STALLED for DMA_STATUS */
<> 150:02e0a0aed4ec 649 #define DMA_STATUS_STATE_DONE (_DMA_STATUS_STATE_DONE << 4) /**< Shifted mode DONE for DMA_STATUS */
<> 150:02e0a0aed4ec 650 #define DMA_STATUS_STATE_PERSCATTRANS (_DMA_STATUS_STATE_PERSCATTRANS << 4) /**< Shifted mode PERSCATTRANS for DMA_STATUS */
<> 150:02e0a0aed4ec 651 #define _DMA_STATUS_CHNUM_SHIFT 16 /**< Shift value for DMA_CHNUM */
<> 150:02e0a0aed4ec 652 #define _DMA_STATUS_CHNUM_MASK 0x1F0000UL /**< Bit mask for DMA_CHNUM */
<> 150:02e0a0aed4ec 653 #define _DMA_STATUS_CHNUM_DEFAULT 0x0000000BUL /**< Mode DEFAULT for DMA_STATUS */
<> 150:02e0a0aed4ec 654 #define DMA_STATUS_CHNUM_DEFAULT (_DMA_STATUS_CHNUM_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_STATUS */
<> 150:02e0a0aed4ec 655
<> 150:02e0a0aed4ec 656 /* Bit fields for DMA CONFIG */
<> 150:02e0a0aed4ec 657 #define _DMA_CONFIG_RESETVALUE 0x00000000UL /**< Default value for DMA_CONFIG */
<> 150:02e0a0aed4ec 658 #define _DMA_CONFIG_MASK 0x00000021UL /**< Mask for DMA_CONFIG */
<> 150:02e0a0aed4ec 659 #define DMA_CONFIG_EN (0x1UL << 0) /**< Enable DMA */
<> 150:02e0a0aed4ec 660 #define _DMA_CONFIG_EN_SHIFT 0 /**< Shift value for DMA_EN */
<> 150:02e0a0aed4ec 661 #define _DMA_CONFIG_EN_MASK 0x1UL /**< Bit mask for DMA_EN */
<> 150:02e0a0aed4ec 662 #define _DMA_CONFIG_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CONFIG */
<> 150:02e0a0aed4ec 663 #define DMA_CONFIG_EN_DEFAULT (_DMA_CONFIG_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CONFIG */
<> 150:02e0a0aed4ec 664 #define DMA_CONFIG_CHPROT (0x1UL << 5) /**< Channel Protection Control */
<> 150:02e0a0aed4ec 665 #define _DMA_CONFIG_CHPROT_SHIFT 5 /**< Shift value for DMA_CHPROT */
<> 150:02e0a0aed4ec 666 #define _DMA_CONFIG_CHPROT_MASK 0x20UL /**< Bit mask for DMA_CHPROT */
<> 150:02e0a0aed4ec 667 #define _DMA_CONFIG_CHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CONFIG */
<> 150:02e0a0aed4ec 668 #define DMA_CONFIG_CHPROT_DEFAULT (_DMA_CONFIG_CHPROT_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CONFIG */
<> 150:02e0a0aed4ec 669
<> 150:02e0a0aed4ec 670 /* Bit fields for DMA CTRLBASE */
<> 150:02e0a0aed4ec 671 #define _DMA_CTRLBASE_RESETVALUE 0x00000000UL /**< Default value for DMA_CTRLBASE */
<> 150:02e0a0aed4ec 672 #define _DMA_CTRLBASE_MASK 0xFFFFFFFFUL /**< Mask for DMA_CTRLBASE */
<> 150:02e0a0aed4ec 673 #define _DMA_CTRLBASE_CTRLBASE_SHIFT 0 /**< Shift value for DMA_CTRLBASE */
<> 150:02e0a0aed4ec 674 #define _DMA_CTRLBASE_CTRLBASE_MASK 0xFFFFFFFFUL /**< Bit mask for DMA_CTRLBASE */
<> 150:02e0a0aed4ec 675 #define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRLBASE */
<> 150:02e0a0aed4ec 676 #define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CTRLBASE */
<> 150:02e0a0aed4ec 677
<> 150:02e0a0aed4ec 678 /* Bit fields for DMA ALTCTRLBASE */
<> 150:02e0a0aed4ec 679 #define _DMA_ALTCTRLBASE_RESETVALUE 0x00000100UL /**< Default value for DMA_ALTCTRLBASE */
<> 150:02e0a0aed4ec 680 #define _DMA_ALTCTRLBASE_MASK 0xFFFFFFFFUL /**< Mask for DMA_ALTCTRLBASE */
<> 150:02e0a0aed4ec 681 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_SHIFT 0 /**< Shift value for DMA_ALTCTRLBASE */
<> 150:02e0a0aed4ec 682 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_MASK 0xFFFFFFFFUL /**< Bit mask for DMA_ALTCTRLBASE */
<> 150:02e0a0aed4ec 683 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT 0x00000100UL /**< Mode DEFAULT for DMA_ALTCTRLBASE */
<> 150:02e0a0aed4ec 684 #define DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT (_DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_ALTCTRLBASE */
<> 150:02e0a0aed4ec 685
<> 150:02e0a0aed4ec 686 /* Bit fields for DMA CHWAITSTATUS */
<> 150:02e0a0aed4ec 687 #define _DMA_CHWAITSTATUS_RESETVALUE 0x00000FFFUL /**< Default value for DMA_CHWAITSTATUS */
<> 150:02e0a0aed4ec 688 #define _DMA_CHWAITSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHWAITSTATUS */
<> 150:02e0a0aed4ec 689 #define DMA_CHWAITSTATUS_CH0WAITSTATUS (0x1UL << 0) /**< Channel 0 Wait on Request Status */
<> 150:02e0a0aed4ec 690 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_SHIFT 0 /**< Shift value for DMA_CH0WAITSTATUS */
<> 150:02e0a0aed4ec 691 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0WAITSTATUS */
<> 150:02e0a0aed4ec 692 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
<> 150:02e0a0aed4ec 693 #define DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
<> 150:02e0a0aed4ec 694 #define DMA_CHWAITSTATUS_CH1WAITSTATUS (0x1UL << 1) /**< Channel 1 Wait on Request Status */
<> 150:02e0a0aed4ec 695 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_SHIFT 1 /**< Shift value for DMA_CH1WAITSTATUS */
<> 150:02e0a0aed4ec 696 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1WAITSTATUS */
<> 150:02e0a0aed4ec 697 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
<> 150:02e0a0aed4ec 698 #define DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
<> 150:02e0a0aed4ec 699 #define DMA_CHWAITSTATUS_CH2WAITSTATUS (0x1UL << 2) /**< Channel 2 Wait on Request Status */
<> 150:02e0a0aed4ec 700 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_SHIFT 2 /**< Shift value for DMA_CH2WAITSTATUS */
<> 150:02e0a0aed4ec 701 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2WAITSTATUS */
<> 150:02e0a0aed4ec 702 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
<> 150:02e0a0aed4ec 703 #define DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
<> 150:02e0a0aed4ec 704 #define DMA_CHWAITSTATUS_CH3WAITSTATUS (0x1UL << 3) /**< Channel 3 Wait on Request Status */
<> 150:02e0a0aed4ec 705 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_SHIFT 3 /**< Shift value for DMA_CH3WAITSTATUS */
<> 150:02e0a0aed4ec 706 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3WAITSTATUS */
<> 150:02e0a0aed4ec 707 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
<> 150:02e0a0aed4ec 708 #define DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
<> 150:02e0a0aed4ec 709 #define DMA_CHWAITSTATUS_CH4WAITSTATUS (0x1UL << 4) /**< Channel 4 Wait on Request Status */
<> 150:02e0a0aed4ec 710 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_SHIFT 4 /**< Shift value for DMA_CH4WAITSTATUS */
<> 150:02e0a0aed4ec 711 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4WAITSTATUS */
<> 150:02e0a0aed4ec 712 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
<> 150:02e0a0aed4ec 713 #define DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
<> 150:02e0a0aed4ec 714 #define DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5) /**< Channel 5 Wait on Request Status */
<> 150:02e0a0aed4ec 715 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_SHIFT 5 /**< Shift value for DMA_CH5WAITSTATUS */
<> 150:02e0a0aed4ec 716 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5WAITSTATUS */
<> 150:02e0a0aed4ec 717 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
<> 150:02e0a0aed4ec 718 #define DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
<> 150:02e0a0aed4ec 719 #define DMA_CHWAITSTATUS_CH6WAITSTATUS (0x1UL << 6) /**< Channel 6 Wait on Request Status */
<> 150:02e0a0aed4ec 720 #define _DMA_CHWAITSTATUS_CH6WAITSTATUS_SHIFT 6 /**< Shift value for DMA_CH6WAITSTATUS */
<> 150:02e0a0aed4ec 721 #define _DMA_CHWAITSTATUS_CH6WAITSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6WAITSTATUS */
<> 150:02e0a0aed4ec 722 #define _DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
<> 150:02e0a0aed4ec 723 #define DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
<> 150:02e0a0aed4ec 724 #define DMA_CHWAITSTATUS_CH7WAITSTATUS (0x1UL << 7) /**< Channel 7 Wait on Request Status */
<> 150:02e0a0aed4ec 725 #define _DMA_CHWAITSTATUS_CH7WAITSTATUS_SHIFT 7 /**< Shift value for DMA_CH7WAITSTATUS */
<> 150:02e0a0aed4ec 726 #define _DMA_CHWAITSTATUS_CH7WAITSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7WAITSTATUS */
<> 150:02e0a0aed4ec 727 #define _DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
<> 150:02e0a0aed4ec 728 #define DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
<> 150:02e0a0aed4ec 729 #define DMA_CHWAITSTATUS_CH8WAITSTATUS (0x1UL << 8) /**< Channel 8 Wait on Request Status */
<> 150:02e0a0aed4ec 730 #define _DMA_CHWAITSTATUS_CH8WAITSTATUS_SHIFT 8 /**< Shift value for DMA_CH8WAITSTATUS */
<> 150:02e0a0aed4ec 731 #define _DMA_CHWAITSTATUS_CH8WAITSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8WAITSTATUS */
<> 150:02e0a0aed4ec 732 #define _DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
<> 150:02e0a0aed4ec 733 #define DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
<> 150:02e0a0aed4ec 734 #define DMA_CHWAITSTATUS_CH9WAITSTATUS (0x1UL << 9) /**< Channel 9 Wait on Request Status */
<> 150:02e0a0aed4ec 735 #define _DMA_CHWAITSTATUS_CH9WAITSTATUS_SHIFT 9 /**< Shift value for DMA_CH9WAITSTATUS */
<> 150:02e0a0aed4ec 736 #define _DMA_CHWAITSTATUS_CH9WAITSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9WAITSTATUS */
<> 150:02e0a0aed4ec 737 #define _DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
<> 150:02e0a0aed4ec 738 #define DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
<> 150:02e0a0aed4ec 739 #define DMA_CHWAITSTATUS_CH10WAITSTATUS (0x1UL << 10) /**< Channel 10 Wait on Request Status */
<> 150:02e0a0aed4ec 740 #define _DMA_CHWAITSTATUS_CH10WAITSTATUS_SHIFT 10 /**< Shift value for DMA_CH10WAITSTATUS */
<> 150:02e0a0aed4ec 741 #define _DMA_CHWAITSTATUS_CH10WAITSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10WAITSTATUS */
<> 150:02e0a0aed4ec 742 #define _DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
<> 150:02e0a0aed4ec 743 #define DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
<> 150:02e0a0aed4ec 744 #define DMA_CHWAITSTATUS_CH11WAITSTATUS (0x1UL << 11) /**< Channel 11 Wait on Request Status */
<> 150:02e0a0aed4ec 745 #define _DMA_CHWAITSTATUS_CH11WAITSTATUS_SHIFT 11 /**< Shift value for DMA_CH11WAITSTATUS */
<> 150:02e0a0aed4ec 746 #define _DMA_CHWAITSTATUS_CH11WAITSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11WAITSTATUS */
<> 150:02e0a0aed4ec 747 #define _DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
<> 150:02e0a0aed4ec 748 #define DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
<> 150:02e0a0aed4ec 749
<> 150:02e0a0aed4ec 750 /* Bit fields for DMA CHSWREQ */
<> 150:02e0a0aed4ec 751 #define _DMA_CHSWREQ_RESETVALUE 0x00000000UL /**< Default value for DMA_CHSWREQ */
<> 150:02e0a0aed4ec 752 #define _DMA_CHSWREQ_MASK 0x00000FFFUL /**< Mask for DMA_CHSWREQ */
<> 150:02e0a0aed4ec 753 #define DMA_CHSWREQ_CH0SWREQ (0x1UL << 0) /**< Channel 0 Software Request */
<> 150:02e0a0aed4ec 754 #define _DMA_CHSWREQ_CH0SWREQ_SHIFT 0 /**< Shift value for DMA_CH0SWREQ */
<> 150:02e0a0aed4ec 755 #define _DMA_CHSWREQ_CH0SWREQ_MASK 0x1UL /**< Bit mask for DMA_CH0SWREQ */
<> 150:02e0a0aed4ec 756 #define _DMA_CHSWREQ_CH0SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
<> 150:02e0a0aed4ec 757 #define DMA_CHSWREQ_CH0SWREQ_DEFAULT (_DMA_CHSWREQ_CH0SWREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
<> 150:02e0a0aed4ec 758 #define DMA_CHSWREQ_CH1SWREQ (0x1UL << 1) /**< Channel 1 Software Request */
<> 150:02e0a0aed4ec 759 #define _DMA_CHSWREQ_CH1SWREQ_SHIFT 1 /**< Shift value for DMA_CH1SWREQ */
<> 150:02e0a0aed4ec 760 #define _DMA_CHSWREQ_CH1SWREQ_MASK 0x2UL /**< Bit mask for DMA_CH1SWREQ */
<> 150:02e0a0aed4ec 761 #define _DMA_CHSWREQ_CH1SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
<> 150:02e0a0aed4ec 762 #define DMA_CHSWREQ_CH1SWREQ_DEFAULT (_DMA_CHSWREQ_CH1SWREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
<> 150:02e0a0aed4ec 763 #define DMA_CHSWREQ_CH2SWREQ (0x1UL << 2) /**< Channel 2 Software Request */
<> 150:02e0a0aed4ec 764 #define _DMA_CHSWREQ_CH2SWREQ_SHIFT 2 /**< Shift value for DMA_CH2SWREQ */
<> 150:02e0a0aed4ec 765 #define _DMA_CHSWREQ_CH2SWREQ_MASK 0x4UL /**< Bit mask for DMA_CH2SWREQ */
<> 150:02e0a0aed4ec 766 #define _DMA_CHSWREQ_CH2SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
<> 150:02e0a0aed4ec 767 #define DMA_CHSWREQ_CH2SWREQ_DEFAULT (_DMA_CHSWREQ_CH2SWREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
<> 150:02e0a0aed4ec 768 #define DMA_CHSWREQ_CH3SWREQ (0x1UL << 3) /**< Channel 3 Software Request */
<> 150:02e0a0aed4ec 769 #define _DMA_CHSWREQ_CH3SWREQ_SHIFT 3 /**< Shift value for DMA_CH3SWREQ */
<> 150:02e0a0aed4ec 770 #define _DMA_CHSWREQ_CH3SWREQ_MASK 0x8UL /**< Bit mask for DMA_CH3SWREQ */
<> 150:02e0a0aed4ec 771 #define _DMA_CHSWREQ_CH3SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
<> 150:02e0a0aed4ec 772 #define DMA_CHSWREQ_CH3SWREQ_DEFAULT (_DMA_CHSWREQ_CH3SWREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
<> 150:02e0a0aed4ec 773 #define DMA_CHSWREQ_CH4SWREQ (0x1UL << 4) /**< Channel 4 Software Request */
<> 150:02e0a0aed4ec 774 #define _DMA_CHSWREQ_CH4SWREQ_SHIFT 4 /**< Shift value for DMA_CH4SWREQ */
<> 150:02e0a0aed4ec 775 #define _DMA_CHSWREQ_CH4SWREQ_MASK 0x10UL /**< Bit mask for DMA_CH4SWREQ */
<> 150:02e0a0aed4ec 776 #define _DMA_CHSWREQ_CH4SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
<> 150:02e0a0aed4ec 777 #define DMA_CHSWREQ_CH4SWREQ_DEFAULT (_DMA_CHSWREQ_CH4SWREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
<> 150:02e0a0aed4ec 778 #define DMA_CHSWREQ_CH5SWREQ (0x1UL << 5) /**< Channel 5 Software Request */
<> 150:02e0a0aed4ec 779 #define _DMA_CHSWREQ_CH5SWREQ_SHIFT 5 /**< Shift value for DMA_CH5SWREQ */
<> 150:02e0a0aed4ec 780 #define _DMA_CHSWREQ_CH5SWREQ_MASK 0x20UL /**< Bit mask for DMA_CH5SWREQ */
<> 150:02e0a0aed4ec 781 #define _DMA_CHSWREQ_CH5SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
<> 150:02e0a0aed4ec 782 #define DMA_CHSWREQ_CH5SWREQ_DEFAULT (_DMA_CHSWREQ_CH5SWREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
<> 150:02e0a0aed4ec 783 #define DMA_CHSWREQ_CH6SWREQ (0x1UL << 6) /**< Channel 6 Software Request */
<> 150:02e0a0aed4ec 784 #define _DMA_CHSWREQ_CH6SWREQ_SHIFT 6 /**< Shift value for DMA_CH6SWREQ */
<> 150:02e0a0aed4ec 785 #define _DMA_CHSWREQ_CH6SWREQ_MASK 0x40UL /**< Bit mask for DMA_CH6SWREQ */
<> 150:02e0a0aed4ec 786 #define _DMA_CHSWREQ_CH6SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
<> 150:02e0a0aed4ec 787 #define DMA_CHSWREQ_CH6SWREQ_DEFAULT (_DMA_CHSWREQ_CH6SWREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
<> 150:02e0a0aed4ec 788 #define DMA_CHSWREQ_CH7SWREQ (0x1UL << 7) /**< Channel 7 Software Request */
<> 150:02e0a0aed4ec 789 #define _DMA_CHSWREQ_CH7SWREQ_SHIFT 7 /**< Shift value for DMA_CH7SWREQ */
<> 150:02e0a0aed4ec 790 #define _DMA_CHSWREQ_CH7SWREQ_MASK 0x80UL /**< Bit mask for DMA_CH7SWREQ */
<> 150:02e0a0aed4ec 791 #define _DMA_CHSWREQ_CH7SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
<> 150:02e0a0aed4ec 792 #define DMA_CHSWREQ_CH7SWREQ_DEFAULT (_DMA_CHSWREQ_CH7SWREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
<> 150:02e0a0aed4ec 793 #define DMA_CHSWREQ_CH8SWREQ (0x1UL << 8) /**< Channel 8 Software Request */
<> 150:02e0a0aed4ec 794 #define _DMA_CHSWREQ_CH8SWREQ_SHIFT 8 /**< Shift value for DMA_CH8SWREQ */
<> 150:02e0a0aed4ec 795 #define _DMA_CHSWREQ_CH8SWREQ_MASK 0x100UL /**< Bit mask for DMA_CH8SWREQ */
<> 150:02e0a0aed4ec 796 #define _DMA_CHSWREQ_CH8SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
<> 150:02e0a0aed4ec 797 #define DMA_CHSWREQ_CH8SWREQ_DEFAULT (_DMA_CHSWREQ_CH8SWREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
<> 150:02e0a0aed4ec 798 #define DMA_CHSWREQ_CH9SWREQ (0x1UL << 9) /**< Channel 9 Software Request */
<> 150:02e0a0aed4ec 799 #define _DMA_CHSWREQ_CH9SWREQ_SHIFT 9 /**< Shift value for DMA_CH9SWREQ */
<> 150:02e0a0aed4ec 800 #define _DMA_CHSWREQ_CH9SWREQ_MASK 0x200UL /**< Bit mask for DMA_CH9SWREQ */
<> 150:02e0a0aed4ec 801 #define _DMA_CHSWREQ_CH9SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
<> 150:02e0a0aed4ec 802 #define DMA_CHSWREQ_CH9SWREQ_DEFAULT (_DMA_CHSWREQ_CH9SWREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
<> 150:02e0a0aed4ec 803 #define DMA_CHSWREQ_CH10SWREQ (0x1UL << 10) /**< Channel 10 Software Request */
<> 150:02e0a0aed4ec 804 #define _DMA_CHSWREQ_CH10SWREQ_SHIFT 10 /**< Shift value for DMA_CH10SWREQ */
<> 150:02e0a0aed4ec 805 #define _DMA_CHSWREQ_CH10SWREQ_MASK 0x400UL /**< Bit mask for DMA_CH10SWREQ */
<> 150:02e0a0aed4ec 806 #define _DMA_CHSWREQ_CH10SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
<> 150:02e0a0aed4ec 807 #define DMA_CHSWREQ_CH10SWREQ_DEFAULT (_DMA_CHSWREQ_CH10SWREQ_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
<> 150:02e0a0aed4ec 808 #define DMA_CHSWREQ_CH11SWREQ (0x1UL << 11) /**< Channel 11 Software Request */
<> 150:02e0a0aed4ec 809 #define _DMA_CHSWREQ_CH11SWREQ_SHIFT 11 /**< Shift value for DMA_CH11SWREQ */
<> 150:02e0a0aed4ec 810 #define _DMA_CHSWREQ_CH11SWREQ_MASK 0x800UL /**< Bit mask for DMA_CH11SWREQ */
<> 150:02e0a0aed4ec 811 #define _DMA_CHSWREQ_CH11SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
<> 150:02e0a0aed4ec 812 #define DMA_CHSWREQ_CH11SWREQ_DEFAULT (_DMA_CHSWREQ_CH11SWREQ_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
<> 150:02e0a0aed4ec 813
<> 150:02e0a0aed4ec 814 /* Bit fields for DMA CHUSEBURSTS */
<> 150:02e0a0aed4ec 815 #define _DMA_CHUSEBURSTS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 816 #define _DMA_CHUSEBURSTS_MASK 0x00000FFFUL /**< Mask for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 817 #define DMA_CHUSEBURSTS_CH0USEBURSTS (0x1UL << 0) /**< Channel 0 Useburst Set */
<> 150:02e0a0aed4ec 818 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_SHIFT 0 /**< Shift value for DMA_CH0USEBURSTS */
<> 150:02e0a0aed4ec 819 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_MASK 0x1UL /**< Bit mask for DMA_CH0USEBURSTS */
<> 150:02e0a0aed4ec 820 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 821 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST 0x00000000UL /**< Mode SINGLEANDBURST for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 822 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY 0x00000001UL /**< Mode BURSTONLY for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 823 #define DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 824 #define DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST (_DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST << 0) /**< Shifted mode SINGLEANDBURST for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 825 #define DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY (_DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY << 0) /**< Shifted mode BURSTONLY for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 826 #define DMA_CHUSEBURSTS_CH1USEBURSTS (0x1UL << 1) /**< Channel 1 Useburst Set */
<> 150:02e0a0aed4ec 827 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_SHIFT 1 /**< Shift value for DMA_CH1USEBURSTS */
<> 150:02e0a0aed4ec 828 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_MASK 0x2UL /**< Bit mask for DMA_CH1USEBURSTS */
<> 150:02e0a0aed4ec 829 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 830 #define DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 831 #define DMA_CHUSEBURSTS_CH2USEBURSTS (0x1UL << 2) /**< Channel 2 Useburst Set */
<> 150:02e0a0aed4ec 832 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_SHIFT 2 /**< Shift value for DMA_CH2USEBURSTS */
<> 150:02e0a0aed4ec 833 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_MASK 0x4UL /**< Bit mask for DMA_CH2USEBURSTS */
<> 150:02e0a0aed4ec 834 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 835 #define DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 836 #define DMA_CHUSEBURSTS_CH3USEBURSTS (0x1UL << 3) /**< Channel 3 Useburst Set */
<> 150:02e0a0aed4ec 837 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_SHIFT 3 /**< Shift value for DMA_CH3USEBURSTS */
<> 150:02e0a0aed4ec 838 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_MASK 0x8UL /**< Bit mask for DMA_CH3USEBURSTS */
<> 150:02e0a0aed4ec 839 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 840 #define DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 841 #define DMA_CHUSEBURSTS_CH4USEBURSTS (0x1UL << 4) /**< Channel 4 Useburst Set */
<> 150:02e0a0aed4ec 842 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_SHIFT 4 /**< Shift value for DMA_CH4USEBURSTS */
<> 150:02e0a0aed4ec 843 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_MASK 0x10UL /**< Bit mask for DMA_CH4USEBURSTS */
<> 150:02e0a0aed4ec 844 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 845 #define DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 846 #define DMA_CHUSEBURSTS_CH5USEBURSTS (0x1UL << 5) /**< Channel 5 Useburst Set */
<> 150:02e0a0aed4ec 847 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_SHIFT 5 /**< Shift value for DMA_CH5USEBURSTS */
<> 150:02e0a0aed4ec 848 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_MASK 0x20UL /**< Bit mask for DMA_CH5USEBURSTS */
<> 150:02e0a0aed4ec 849 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 850 #define DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 851 #define DMA_CHUSEBURSTS_CH6USEBURSTS (0x1UL << 6) /**< Channel 6 Useburst Set */
<> 150:02e0a0aed4ec 852 #define _DMA_CHUSEBURSTS_CH6USEBURSTS_SHIFT 6 /**< Shift value for DMA_CH6USEBURSTS */
<> 150:02e0a0aed4ec 853 #define _DMA_CHUSEBURSTS_CH6USEBURSTS_MASK 0x40UL /**< Bit mask for DMA_CH6USEBURSTS */
<> 150:02e0a0aed4ec 854 #define _DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 855 #define DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 856 #define DMA_CHUSEBURSTS_CH7USEBURSTS (0x1UL << 7) /**< Channel 7 Useburst Set */
<> 150:02e0a0aed4ec 857 #define _DMA_CHUSEBURSTS_CH7USEBURSTS_SHIFT 7 /**< Shift value for DMA_CH7USEBURSTS */
<> 150:02e0a0aed4ec 858 #define _DMA_CHUSEBURSTS_CH7USEBURSTS_MASK 0x80UL /**< Bit mask for DMA_CH7USEBURSTS */
<> 150:02e0a0aed4ec 859 #define _DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 860 #define DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 861 #define DMA_CHUSEBURSTS_CH8USEBURSTS (0x1UL << 8) /**< Channel 8 Useburst Set */
<> 150:02e0a0aed4ec 862 #define _DMA_CHUSEBURSTS_CH8USEBURSTS_SHIFT 8 /**< Shift value for DMA_CH8USEBURSTS */
<> 150:02e0a0aed4ec 863 #define _DMA_CHUSEBURSTS_CH8USEBURSTS_MASK 0x100UL /**< Bit mask for DMA_CH8USEBURSTS */
<> 150:02e0a0aed4ec 864 #define _DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 865 #define DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 866 #define DMA_CHUSEBURSTS_CH9USEBURSTS (0x1UL << 9) /**< Channel 9 Useburst Set */
<> 150:02e0a0aed4ec 867 #define _DMA_CHUSEBURSTS_CH9USEBURSTS_SHIFT 9 /**< Shift value for DMA_CH9USEBURSTS */
<> 150:02e0a0aed4ec 868 #define _DMA_CHUSEBURSTS_CH9USEBURSTS_MASK 0x200UL /**< Bit mask for DMA_CH9USEBURSTS */
<> 150:02e0a0aed4ec 869 #define _DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 870 #define DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 871 #define DMA_CHUSEBURSTS_CH10USEBURSTS (0x1UL << 10) /**< Channel 10 Useburst Set */
<> 150:02e0a0aed4ec 872 #define _DMA_CHUSEBURSTS_CH10USEBURSTS_SHIFT 10 /**< Shift value for DMA_CH10USEBURSTS */
<> 150:02e0a0aed4ec 873 #define _DMA_CHUSEBURSTS_CH10USEBURSTS_MASK 0x400UL /**< Bit mask for DMA_CH10USEBURSTS */
<> 150:02e0a0aed4ec 874 #define _DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 875 #define DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 876 #define DMA_CHUSEBURSTS_CH11USEBURSTS (0x1UL << 11) /**< Channel 11 Useburst Set */
<> 150:02e0a0aed4ec 877 #define _DMA_CHUSEBURSTS_CH11USEBURSTS_SHIFT 11 /**< Shift value for DMA_CH11USEBURSTS */
<> 150:02e0a0aed4ec 878 #define _DMA_CHUSEBURSTS_CH11USEBURSTS_MASK 0x800UL /**< Bit mask for DMA_CH11USEBURSTS */
<> 150:02e0a0aed4ec 879 #define _DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 880 #define DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
<> 150:02e0a0aed4ec 881
<> 150:02e0a0aed4ec 882 /* Bit fields for DMA CHUSEBURSTC */
<> 150:02e0a0aed4ec 883 #define _DMA_CHUSEBURSTC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHUSEBURSTC */
<> 150:02e0a0aed4ec 884 #define _DMA_CHUSEBURSTC_MASK 0x00000FFFUL /**< Mask for DMA_CHUSEBURSTC */
<> 150:02e0a0aed4ec 885 #define DMA_CHUSEBURSTC_CH0USEBURSTC (0x1UL << 0) /**< Channel 0 Useburst Clear */
<> 150:02e0a0aed4ec 886 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_SHIFT 0 /**< Shift value for DMA_CH0USEBURSTC */
<> 150:02e0a0aed4ec 887 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_MASK 0x1UL /**< Bit mask for DMA_CH0USEBURSTC */
<> 150:02e0a0aed4ec 888 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
<> 150:02e0a0aed4ec 889 #define DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
<> 150:02e0a0aed4ec 890 #define DMA_CHUSEBURSTC_CH1USEBURSTC (0x1UL << 1) /**< Channel 1 Useburst Clear */
<> 150:02e0a0aed4ec 891 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_SHIFT 1 /**< Shift value for DMA_CH1USEBURSTC */
<> 150:02e0a0aed4ec 892 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_MASK 0x2UL /**< Bit mask for DMA_CH1USEBURSTC */
<> 150:02e0a0aed4ec 893 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
<> 150:02e0a0aed4ec 894 #define DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
<> 150:02e0a0aed4ec 895 #define DMA_CHUSEBURSTC_CH2USEBURSTC (0x1UL << 2) /**< Channel 2 Useburst Clear */
<> 150:02e0a0aed4ec 896 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_SHIFT 2 /**< Shift value for DMA_CH2USEBURSTC */
<> 150:02e0a0aed4ec 897 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_MASK 0x4UL /**< Bit mask for DMA_CH2USEBURSTC */
<> 150:02e0a0aed4ec 898 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
<> 150:02e0a0aed4ec 899 #define DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
<> 150:02e0a0aed4ec 900 #define DMA_CHUSEBURSTC_CH3USEBURSTC (0x1UL << 3) /**< Channel 3 Useburst Clear */
<> 150:02e0a0aed4ec 901 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_SHIFT 3 /**< Shift value for DMA_CH3USEBURSTC */
<> 150:02e0a0aed4ec 902 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_MASK 0x8UL /**< Bit mask for DMA_CH3USEBURSTC */
<> 150:02e0a0aed4ec 903 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
<> 150:02e0a0aed4ec 904 #define DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
<> 150:02e0a0aed4ec 905 #define DMA_CHUSEBURSTC_CH4USEBURSTC (0x1UL << 4) /**< Channel 4 Useburst Clear */
<> 150:02e0a0aed4ec 906 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_SHIFT 4 /**< Shift value for DMA_CH4USEBURSTC */
<> 150:02e0a0aed4ec 907 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_MASK 0x10UL /**< Bit mask for DMA_CH4USEBURSTC */
<> 150:02e0a0aed4ec 908 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
<> 150:02e0a0aed4ec 909 #define DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
<> 150:02e0a0aed4ec 910 #define DMA_CHUSEBURSTC_CH5USEBURSTC (0x1UL << 5) /**< Channel 5 Useburst Clear */
<> 150:02e0a0aed4ec 911 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_SHIFT 5 /**< Shift value for DMA_CH5USEBURSTC */
<> 150:02e0a0aed4ec 912 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_MASK 0x20UL /**< Bit mask for DMA_CH5USEBURSTC */
<> 150:02e0a0aed4ec 913 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
<> 150:02e0a0aed4ec 914 #define DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
<> 150:02e0a0aed4ec 915 #define DMA_CHUSEBURSTC_CH6USEBURSTC (0x1UL << 6) /**< Channel 6 Useburst Clear */
<> 150:02e0a0aed4ec 916 #define _DMA_CHUSEBURSTC_CH6USEBURSTC_SHIFT 6 /**< Shift value for DMA_CH6USEBURSTC */
<> 150:02e0a0aed4ec 917 #define _DMA_CHUSEBURSTC_CH6USEBURSTC_MASK 0x40UL /**< Bit mask for DMA_CH6USEBURSTC */
<> 150:02e0a0aed4ec 918 #define _DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
<> 150:02e0a0aed4ec 919 #define DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
<> 150:02e0a0aed4ec 920 #define DMA_CHUSEBURSTC_CH7USEBURSTC (0x1UL << 7) /**< Channel 7 Useburst Clear */
<> 150:02e0a0aed4ec 921 #define _DMA_CHUSEBURSTC_CH7USEBURSTC_SHIFT 7 /**< Shift value for DMA_CH7USEBURSTC */
<> 150:02e0a0aed4ec 922 #define _DMA_CHUSEBURSTC_CH7USEBURSTC_MASK 0x80UL /**< Bit mask for DMA_CH7USEBURSTC */
<> 150:02e0a0aed4ec 923 #define _DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
<> 150:02e0a0aed4ec 924 #define DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
<> 150:02e0a0aed4ec 925 #define DMA_CHUSEBURSTC_CH08USEBURSTC (0x1UL << 8) /**< Channel 8 Useburst Clear */
<> 150:02e0a0aed4ec 926 #define _DMA_CHUSEBURSTC_CH08USEBURSTC_SHIFT 8 /**< Shift value for DMA_CH08USEBURSTC */
<> 150:02e0a0aed4ec 927 #define _DMA_CHUSEBURSTC_CH08USEBURSTC_MASK 0x100UL /**< Bit mask for DMA_CH08USEBURSTC */
<> 150:02e0a0aed4ec 928 #define _DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
<> 150:02e0a0aed4ec 929 #define DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
<> 150:02e0a0aed4ec 930 #define DMA_CHUSEBURSTC_CH9USEBURSTC (0x1UL << 9) /**< Channel 9 Useburst Clear */
<> 150:02e0a0aed4ec 931 #define _DMA_CHUSEBURSTC_CH9USEBURSTC_SHIFT 9 /**< Shift value for DMA_CH9USEBURSTC */
<> 150:02e0a0aed4ec 932 #define _DMA_CHUSEBURSTC_CH9USEBURSTC_MASK 0x200UL /**< Bit mask for DMA_CH9USEBURSTC */
<> 150:02e0a0aed4ec 933 #define _DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
<> 150:02e0a0aed4ec 934 #define DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
<> 150:02e0a0aed4ec 935 #define DMA_CHUSEBURSTC_CH10USEBURSTC (0x1UL << 10) /**< Channel 10 Useburst Clear */
<> 150:02e0a0aed4ec 936 #define _DMA_CHUSEBURSTC_CH10USEBURSTC_SHIFT 10 /**< Shift value for DMA_CH10USEBURSTC */
<> 150:02e0a0aed4ec 937 #define _DMA_CHUSEBURSTC_CH10USEBURSTC_MASK 0x400UL /**< Bit mask for DMA_CH10USEBURSTC */
<> 150:02e0a0aed4ec 938 #define _DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
<> 150:02e0a0aed4ec 939 #define DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
<> 150:02e0a0aed4ec 940 #define DMA_CHUSEBURSTC_CH11USEBURSTC (0x1UL << 11) /**< Channel 11 Useburst Clear */
<> 150:02e0a0aed4ec 941 #define _DMA_CHUSEBURSTC_CH11USEBURSTC_SHIFT 11 /**< Shift value for DMA_CH11USEBURSTC */
<> 150:02e0a0aed4ec 942 #define _DMA_CHUSEBURSTC_CH11USEBURSTC_MASK 0x800UL /**< Bit mask for DMA_CH11USEBURSTC */
<> 150:02e0a0aed4ec 943 #define _DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
<> 150:02e0a0aed4ec 944 #define DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
<> 150:02e0a0aed4ec 945
<> 150:02e0a0aed4ec 946 /* Bit fields for DMA CHREQMASKS */
<> 150:02e0a0aed4ec 947 #define _DMA_CHREQMASKS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQMASKS */
<> 150:02e0a0aed4ec 948 #define _DMA_CHREQMASKS_MASK 0x00000FFFUL /**< Mask for DMA_CHREQMASKS */
<> 150:02e0a0aed4ec 949 #define DMA_CHREQMASKS_CH0REQMASKS (0x1UL << 0) /**< Channel 0 Request Mask Set */
<> 150:02e0a0aed4ec 950 #define _DMA_CHREQMASKS_CH0REQMASKS_SHIFT 0 /**< Shift value for DMA_CH0REQMASKS */
<> 150:02e0a0aed4ec 951 #define _DMA_CHREQMASKS_CH0REQMASKS_MASK 0x1UL /**< Bit mask for DMA_CH0REQMASKS */
<> 150:02e0a0aed4ec 952 #define _DMA_CHREQMASKS_CH0REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
<> 150:02e0a0aed4ec 953 #define DMA_CHREQMASKS_CH0REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH0REQMASKS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
<> 150:02e0a0aed4ec 954 #define DMA_CHREQMASKS_CH1REQMASKS (0x1UL << 1) /**< Channel 1 Request Mask Set */
<> 150:02e0a0aed4ec 955 #define _DMA_CHREQMASKS_CH1REQMASKS_SHIFT 1 /**< Shift value for DMA_CH1REQMASKS */
<> 150:02e0a0aed4ec 956 #define _DMA_CHREQMASKS_CH1REQMASKS_MASK 0x2UL /**< Bit mask for DMA_CH1REQMASKS */
<> 150:02e0a0aed4ec 957 #define _DMA_CHREQMASKS_CH1REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
<> 150:02e0a0aed4ec 958 #define DMA_CHREQMASKS_CH1REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH1REQMASKS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
<> 150:02e0a0aed4ec 959 #define DMA_CHREQMASKS_CH2REQMASKS (0x1UL << 2) /**< Channel 2 Request Mask Set */
<> 150:02e0a0aed4ec 960 #define _DMA_CHREQMASKS_CH2REQMASKS_SHIFT 2 /**< Shift value for DMA_CH2REQMASKS */
<> 150:02e0a0aed4ec 961 #define _DMA_CHREQMASKS_CH2REQMASKS_MASK 0x4UL /**< Bit mask for DMA_CH2REQMASKS */
<> 150:02e0a0aed4ec 962 #define _DMA_CHREQMASKS_CH2REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
<> 150:02e0a0aed4ec 963 #define DMA_CHREQMASKS_CH2REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH2REQMASKS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
<> 150:02e0a0aed4ec 964 #define DMA_CHREQMASKS_CH3REQMASKS (0x1UL << 3) /**< Channel 3 Request Mask Set */
<> 150:02e0a0aed4ec 965 #define _DMA_CHREQMASKS_CH3REQMASKS_SHIFT 3 /**< Shift value for DMA_CH3REQMASKS */
<> 150:02e0a0aed4ec 966 #define _DMA_CHREQMASKS_CH3REQMASKS_MASK 0x8UL /**< Bit mask for DMA_CH3REQMASKS */
<> 150:02e0a0aed4ec 967 #define _DMA_CHREQMASKS_CH3REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
<> 150:02e0a0aed4ec 968 #define DMA_CHREQMASKS_CH3REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH3REQMASKS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
<> 150:02e0a0aed4ec 969 #define DMA_CHREQMASKS_CH4REQMASKS (0x1UL << 4) /**< Channel 4 Request Mask Set */
<> 150:02e0a0aed4ec 970 #define _DMA_CHREQMASKS_CH4REQMASKS_SHIFT 4 /**< Shift value for DMA_CH4REQMASKS */
<> 150:02e0a0aed4ec 971 #define _DMA_CHREQMASKS_CH4REQMASKS_MASK 0x10UL /**< Bit mask for DMA_CH4REQMASKS */
<> 150:02e0a0aed4ec 972 #define _DMA_CHREQMASKS_CH4REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
<> 150:02e0a0aed4ec 973 #define DMA_CHREQMASKS_CH4REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH4REQMASKS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
<> 150:02e0a0aed4ec 974 #define DMA_CHREQMASKS_CH5REQMASKS (0x1UL << 5) /**< Channel 5 Request Mask Set */
<> 150:02e0a0aed4ec 975 #define _DMA_CHREQMASKS_CH5REQMASKS_SHIFT 5 /**< Shift value for DMA_CH5REQMASKS */
<> 150:02e0a0aed4ec 976 #define _DMA_CHREQMASKS_CH5REQMASKS_MASK 0x20UL /**< Bit mask for DMA_CH5REQMASKS */
<> 150:02e0a0aed4ec 977 #define _DMA_CHREQMASKS_CH5REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
<> 150:02e0a0aed4ec 978 #define DMA_CHREQMASKS_CH5REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH5REQMASKS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
<> 150:02e0a0aed4ec 979 #define DMA_CHREQMASKS_CH6REQMASKS (0x1UL << 6) /**< Channel 6 Request Mask Set */
<> 150:02e0a0aed4ec 980 #define _DMA_CHREQMASKS_CH6REQMASKS_SHIFT 6 /**< Shift value for DMA_CH6REQMASKS */
<> 150:02e0a0aed4ec 981 #define _DMA_CHREQMASKS_CH6REQMASKS_MASK 0x40UL /**< Bit mask for DMA_CH6REQMASKS */
<> 150:02e0a0aed4ec 982 #define _DMA_CHREQMASKS_CH6REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
<> 150:02e0a0aed4ec 983 #define DMA_CHREQMASKS_CH6REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH6REQMASKS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
<> 150:02e0a0aed4ec 984 #define DMA_CHREQMASKS_CH7REQMASKS (0x1UL << 7) /**< Channel 7 Request Mask Set */
<> 150:02e0a0aed4ec 985 #define _DMA_CHREQMASKS_CH7REQMASKS_SHIFT 7 /**< Shift value for DMA_CH7REQMASKS */
<> 150:02e0a0aed4ec 986 #define _DMA_CHREQMASKS_CH7REQMASKS_MASK 0x80UL /**< Bit mask for DMA_CH7REQMASKS */
<> 150:02e0a0aed4ec 987 #define _DMA_CHREQMASKS_CH7REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
<> 150:02e0a0aed4ec 988 #define DMA_CHREQMASKS_CH7REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH7REQMASKS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
<> 150:02e0a0aed4ec 989 #define DMA_CHREQMASKS_CH8REQMASKS (0x1UL << 8) /**< Channel 8 Request Mask Set */
<> 150:02e0a0aed4ec 990 #define _DMA_CHREQMASKS_CH8REQMASKS_SHIFT 8 /**< Shift value for DMA_CH8REQMASKS */
<> 150:02e0a0aed4ec 991 #define _DMA_CHREQMASKS_CH8REQMASKS_MASK 0x100UL /**< Bit mask for DMA_CH8REQMASKS */
<> 150:02e0a0aed4ec 992 #define _DMA_CHREQMASKS_CH8REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
<> 150:02e0a0aed4ec 993 #define DMA_CHREQMASKS_CH8REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH8REQMASKS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
<> 150:02e0a0aed4ec 994 #define DMA_CHREQMASKS_CH9REQMASKS (0x1UL << 9) /**< Channel 9 Request Mask Set */
<> 150:02e0a0aed4ec 995 #define _DMA_CHREQMASKS_CH9REQMASKS_SHIFT 9 /**< Shift value for DMA_CH9REQMASKS */
<> 150:02e0a0aed4ec 996 #define _DMA_CHREQMASKS_CH9REQMASKS_MASK 0x200UL /**< Bit mask for DMA_CH9REQMASKS */
<> 150:02e0a0aed4ec 997 #define _DMA_CHREQMASKS_CH9REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
<> 150:02e0a0aed4ec 998 #define DMA_CHREQMASKS_CH9REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH9REQMASKS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
<> 150:02e0a0aed4ec 999 #define DMA_CHREQMASKS_CH10REQMASKS (0x1UL << 10) /**< Channel 10 Request Mask Set */
<> 150:02e0a0aed4ec 1000 #define _DMA_CHREQMASKS_CH10REQMASKS_SHIFT 10 /**< Shift value for DMA_CH10REQMASKS */
<> 150:02e0a0aed4ec 1001 #define _DMA_CHREQMASKS_CH10REQMASKS_MASK 0x400UL /**< Bit mask for DMA_CH10REQMASKS */
<> 150:02e0a0aed4ec 1002 #define _DMA_CHREQMASKS_CH10REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
<> 150:02e0a0aed4ec 1003 #define DMA_CHREQMASKS_CH10REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH10REQMASKS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
<> 150:02e0a0aed4ec 1004 #define DMA_CHREQMASKS_CH11REQMASKS (0x1UL << 11) /**< Channel 11 Request Mask Set */
<> 150:02e0a0aed4ec 1005 #define _DMA_CHREQMASKS_CH11REQMASKS_SHIFT 11 /**< Shift value for DMA_CH11REQMASKS */
<> 150:02e0a0aed4ec 1006 #define _DMA_CHREQMASKS_CH11REQMASKS_MASK 0x800UL /**< Bit mask for DMA_CH11REQMASKS */
<> 150:02e0a0aed4ec 1007 #define _DMA_CHREQMASKS_CH11REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
<> 150:02e0a0aed4ec 1008 #define DMA_CHREQMASKS_CH11REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH11REQMASKS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
<> 150:02e0a0aed4ec 1009
<> 150:02e0a0aed4ec 1010 /* Bit fields for DMA CHREQMASKC */
<> 150:02e0a0aed4ec 1011 #define _DMA_CHREQMASKC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQMASKC */
<> 150:02e0a0aed4ec 1012 #define _DMA_CHREQMASKC_MASK 0x00000FFFUL /**< Mask for DMA_CHREQMASKC */
<> 150:02e0a0aed4ec 1013 #define DMA_CHREQMASKC_CH0REQMASKC (0x1UL << 0) /**< Channel 0 Request Mask Clear */
<> 150:02e0a0aed4ec 1014 #define _DMA_CHREQMASKC_CH0REQMASKC_SHIFT 0 /**< Shift value for DMA_CH0REQMASKC */
<> 150:02e0a0aed4ec 1015 #define _DMA_CHREQMASKC_CH0REQMASKC_MASK 0x1UL /**< Bit mask for DMA_CH0REQMASKC */
<> 150:02e0a0aed4ec 1016 #define _DMA_CHREQMASKC_CH0REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
<> 150:02e0a0aed4ec 1017 #define DMA_CHREQMASKC_CH0REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH0REQMASKC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
<> 150:02e0a0aed4ec 1018 #define DMA_CHREQMASKC_CH1REQMASKC (0x1UL << 1) /**< Channel 1 Request Mask Clear */
<> 150:02e0a0aed4ec 1019 #define _DMA_CHREQMASKC_CH1REQMASKC_SHIFT 1 /**< Shift value for DMA_CH1REQMASKC */
<> 150:02e0a0aed4ec 1020 #define _DMA_CHREQMASKC_CH1REQMASKC_MASK 0x2UL /**< Bit mask for DMA_CH1REQMASKC */
<> 150:02e0a0aed4ec 1021 #define _DMA_CHREQMASKC_CH1REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
<> 150:02e0a0aed4ec 1022 #define DMA_CHREQMASKC_CH1REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH1REQMASKC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
<> 150:02e0a0aed4ec 1023 #define DMA_CHREQMASKC_CH2REQMASKC (0x1UL << 2) /**< Channel 2 Request Mask Clear */
<> 150:02e0a0aed4ec 1024 #define _DMA_CHREQMASKC_CH2REQMASKC_SHIFT 2 /**< Shift value for DMA_CH2REQMASKC */
<> 150:02e0a0aed4ec 1025 #define _DMA_CHREQMASKC_CH2REQMASKC_MASK 0x4UL /**< Bit mask for DMA_CH2REQMASKC */
<> 150:02e0a0aed4ec 1026 #define _DMA_CHREQMASKC_CH2REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
<> 150:02e0a0aed4ec 1027 #define DMA_CHREQMASKC_CH2REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH2REQMASKC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
<> 150:02e0a0aed4ec 1028 #define DMA_CHREQMASKC_CH3REQMASKC (0x1UL << 3) /**< Channel 3 Request Mask Clear */
<> 150:02e0a0aed4ec 1029 #define _DMA_CHREQMASKC_CH3REQMASKC_SHIFT 3 /**< Shift value for DMA_CH3REQMASKC */
<> 150:02e0a0aed4ec 1030 #define _DMA_CHREQMASKC_CH3REQMASKC_MASK 0x8UL /**< Bit mask for DMA_CH3REQMASKC */
<> 150:02e0a0aed4ec 1031 #define _DMA_CHREQMASKC_CH3REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
<> 150:02e0a0aed4ec 1032 #define DMA_CHREQMASKC_CH3REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH3REQMASKC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
<> 150:02e0a0aed4ec 1033 #define DMA_CHREQMASKC_CH4REQMASKC (0x1UL << 4) /**< Channel 4 Request Mask Clear */
<> 150:02e0a0aed4ec 1034 #define _DMA_CHREQMASKC_CH4REQMASKC_SHIFT 4 /**< Shift value for DMA_CH4REQMASKC */
<> 150:02e0a0aed4ec 1035 #define _DMA_CHREQMASKC_CH4REQMASKC_MASK 0x10UL /**< Bit mask for DMA_CH4REQMASKC */
<> 150:02e0a0aed4ec 1036 #define _DMA_CHREQMASKC_CH4REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
<> 150:02e0a0aed4ec 1037 #define DMA_CHREQMASKC_CH4REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH4REQMASKC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
<> 150:02e0a0aed4ec 1038 #define DMA_CHREQMASKC_CH5REQMASKC (0x1UL << 5) /**< Channel 5 Request Mask Clear */
<> 150:02e0a0aed4ec 1039 #define _DMA_CHREQMASKC_CH5REQMASKC_SHIFT 5 /**< Shift value for DMA_CH5REQMASKC */
<> 150:02e0a0aed4ec 1040 #define _DMA_CHREQMASKC_CH5REQMASKC_MASK 0x20UL /**< Bit mask for DMA_CH5REQMASKC */
<> 150:02e0a0aed4ec 1041 #define _DMA_CHREQMASKC_CH5REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
<> 150:02e0a0aed4ec 1042 #define DMA_CHREQMASKC_CH5REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH5REQMASKC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
<> 150:02e0a0aed4ec 1043 #define DMA_CHREQMASKC_CH6REQMASKC (0x1UL << 6) /**< Channel 6 Request Mask Clear */
<> 150:02e0a0aed4ec 1044 #define _DMA_CHREQMASKC_CH6REQMASKC_SHIFT 6 /**< Shift value for DMA_CH6REQMASKC */
<> 150:02e0a0aed4ec 1045 #define _DMA_CHREQMASKC_CH6REQMASKC_MASK 0x40UL /**< Bit mask for DMA_CH6REQMASKC */
<> 150:02e0a0aed4ec 1046 #define _DMA_CHREQMASKC_CH6REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
<> 150:02e0a0aed4ec 1047 #define DMA_CHREQMASKC_CH6REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH6REQMASKC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
<> 150:02e0a0aed4ec 1048 #define DMA_CHREQMASKC_CH7REQMASKC (0x1UL << 7) /**< Channel 7 Request Mask Clear */
<> 150:02e0a0aed4ec 1049 #define _DMA_CHREQMASKC_CH7REQMASKC_SHIFT 7 /**< Shift value for DMA_CH7REQMASKC */
<> 150:02e0a0aed4ec 1050 #define _DMA_CHREQMASKC_CH7REQMASKC_MASK 0x80UL /**< Bit mask for DMA_CH7REQMASKC */
<> 150:02e0a0aed4ec 1051 #define _DMA_CHREQMASKC_CH7REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
<> 150:02e0a0aed4ec 1052 #define DMA_CHREQMASKC_CH7REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH7REQMASKC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
<> 150:02e0a0aed4ec 1053 #define DMA_CHREQMASKC_CH8REQMASKC (0x1UL << 8) /**< Channel 8 Request Mask Clear */
<> 150:02e0a0aed4ec 1054 #define _DMA_CHREQMASKC_CH8REQMASKC_SHIFT 8 /**< Shift value for DMA_CH8REQMASKC */
<> 150:02e0a0aed4ec 1055 #define _DMA_CHREQMASKC_CH8REQMASKC_MASK 0x100UL /**< Bit mask for DMA_CH8REQMASKC */
<> 150:02e0a0aed4ec 1056 #define _DMA_CHREQMASKC_CH8REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
<> 150:02e0a0aed4ec 1057 #define DMA_CHREQMASKC_CH8REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH8REQMASKC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
<> 150:02e0a0aed4ec 1058 #define DMA_CHREQMASKC_CH9REQMASKC (0x1UL << 9) /**< Channel 9 Request Mask Clear */
<> 150:02e0a0aed4ec 1059 #define _DMA_CHREQMASKC_CH9REQMASKC_SHIFT 9 /**< Shift value for DMA_CH9REQMASKC */
<> 150:02e0a0aed4ec 1060 #define _DMA_CHREQMASKC_CH9REQMASKC_MASK 0x200UL /**< Bit mask for DMA_CH9REQMASKC */
<> 150:02e0a0aed4ec 1061 #define _DMA_CHREQMASKC_CH9REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
<> 150:02e0a0aed4ec 1062 #define DMA_CHREQMASKC_CH9REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH9REQMASKC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
<> 150:02e0a0aed4ec 1063 #define DMA_CHREQMASKC_CH10REQMASKC (0x1UL << 10) /**< Channel 10 Request Mask Clear */
<> 150:02e0a0aed4ec 1064 #define _DMA_CHREQMASKC_CH10REQMASKC_SHIFT 10 /**< Shift value for DMA_CH10REQMASKC */
<> 150:02e0a0aed4ec 1065 #define _DMA_CHREQMASKC_CH10REQMASKC_MASK 0x400UL /**< Bit mask for DMA_CH10REQMASKC */
<> 150:02e0a0aed4ec 1066 #define _DMA_CHREQMASKC_CH10REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
<> 150:02e0a0aed4ec 1067 #define DMA_CHREQMASKC_CH10REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH10REQMASKC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
<> 150:02e0a0aed4ec 1068 #define DMA_CHREQMASKC_CH11REQMASKC (0x1UL << 11) /**< Channel 11 Request Mask Clear */
<> 150:02e0a0aed4ec 1069 #define _DMA_CHREQMASKC_CH11REQMASKC_SHIFT 11 /**< Shift value for DMA_CH11REQMASKC */
<> 150:02e0a0aed4ec 1070 #define _DMA_CHREQMASKC_CH11REQMASKC_MASK 0x800UL /**< Bit mask for DMA_CH11REQMASKC */
<> 150:02e0a0aed4ec 1071 #define _DMA_CHREQMASKC_CH11REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
<> 150:02e0a0aed4ec 1072 #define DMA_CHREQMASKC_CH11REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH11REQMASKC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
<> 150:02e0a0aed4ec 1073
<> 150:02e0a0aed4ec 1074 /* Bit fields for DMA CHENS */
<> 150:02e0a0aed4ec 1075 #define _DMA_CHENS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHENS */
<> 150:02e0a0aed4ec 1076 #define _DMA_CHENS_MASK 0x00000FFFUL /**< Mask for DMA_CHENS */
<> 150:02e0a0aed4ec 1077 #define DMA_CHENS_CH0ENS (0x1UL << 0) /**< Channel 0 Enable Set */
<> 150:02e0a0aed4ec 1078 #define _DMA_CHENS_CH0ENS_SHIFT 0 /**< Shift value for DMA_CH0ENS */
<> 150:02e0a0aed4ec 1079 #define _DMA_CHENS_CH0ENS_MASK 0x1UL /**< Bit mask for DMA_CH0ENS */
<> 150:02e0a0aed4ec 1080 #define _DMA_CHENS_CH0ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
<> 150:02e0a0aed4ec 1081 #define DMA_CHENS_CH0ENS_DEFAULT (_DMA_CHENS_CH0ENS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHENS */
<> 150:02e0a0aed4ec 1082 #define DMA_CHENS_CH1ENS (0x1UL << 1) /**< Channel 1 Enable Set */
<> 150:02e0a0aed4ec 1083 #define _DMA_CHENS_CH1ENS_SHIFT 1 /**< Shift value for DMA_CH1ENS */
<> 150:02e0a0aed4ec 1084 #define _DMA_CHENS_CH1ENS_MASK 0x2UL /**< Bit mask for DMA_CH1ENS */
<> 150:02e0a0aed4ec 1085 #define _DMA_CHENS_CH1ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
<> 150:02e0a0aed4ec 1086 #define DMA_CHENS_CH1ENS_DEFAULT (_DMA_CHENS_CH1ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHENS */
<> 150:02e0a0aed4ec 1087 #define DMA_CHENS_CH2ENS (0x1UL << 2) /**< Channel 2 Enable Set */
<> 150:02e0a0aed4ec 1088 #define _DMA_CHENS_CH2ENS_SHIFT 2 /**< Shift value for DMA_CH2ENS */
<> 150:02e0a0aed4ec 1089 #define _DMA_CHENS_CH2ENS_MASK 0x4UL /**< Bit mask for DMA_CH2ENS */
<> 150:02e0a0aed4ec 1090 #define _DMA_CHENS_CH2ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
<> 150:02e0a0aed4ec 1091 #define DMA_CHENS_CH2ENS_DEFAULT (_DMA_CHENS_CH2ENS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHENS */
<> 150:02e0a0aed4ec 1092 #define DMA_CHENS_CH3ENS (0x1UL << 3) /**< Channel 3 Enable Set */
<> 150:02e0a0aed4ec 1093 #define _DMA_CHENS_CH3ENS_SHIFT 3 /**< Shift value for DMA_CH3ENS */
<> 150:02e0a0aed4ec 1094 #define _DMA_CHENS_CH3ENS_MASK 0x8UL /**< Bit mask for DMA_CH3ENS */
<> 150:02e0a0aed4ec 1095 #define _DMA_CHENS_CH3ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
<> 150:02e0a0aed4ec 1096 #define DMA_CHENS_CH3ENS_DEFAULT (_DMA_CHENS_CH3ENS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHENS */
<> 150:02e0a0aed4ec 1097 #define DMA_CHENS_CH4ENS (0x1UL << 4) /**< Channel 4 Enable Set */
<> 150:02e0a0aed4ec 1098 #define _DMA_CHENS_CH4ENS_SHIFT 4 /**< Shift value for DMA_CH4ENS */
<> 150:02e0a0aed4ec 1099 #define _DMA_CHENS_CH4ENS_MASK 0x10UL /**< Bit mask for DMA_CH4ENS */
<> 150:02e0a0aed4ec 1100 #define _DMA_CHENS_CH4ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
<> 150:02e0a0aed4ec 1101 #define DMA_CHENS_CH4ENS_DEFAULT (_DMA_CHENS_CH4ENS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHENS */
<> 150:02e0a0aed4ec 1102 #define DMA_CHENS_CH5ENS (0x1UL << 5) /**< Channel 5 Enable Set */
<> 150:02e0a0aed4ec 1103 #define _DMA_CHENS_CH5ENS_SHIFT 5 /**< Shift value for DMA_CH5ENS */
<> 150:02e0a0aed4ec 1104 #define _DMA_CHENS_CH5ENS_MASK 0x20UL /**< Bit mask for DMA_CH5ENS */
<> 150:02e0a0aed4ec 1105 #define _DMA_CHENS_CH5ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
<> 150:02e0a0aed4ec 1106 #define DMA_CHENS_CH5ENS_DEFAULT (_DMA_CHENS_CH5ENS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHENS */
<> 150:02e0a0aed4ec 1107 #define DMA_CHENS_CH6ENS (0x1UL << 6) /**< Channel 6 Enable Set */
<> 150:02e0a0aed4ec 1108 #define _DMA_CHENS_CH6ENS_SHIFT 6 /**< Shift value for DMA_CH6ENS */
<> 150:02e0a0aed4ec 1109 #define _DMA_CHENS_CH6ENS_MASK 0x40UL /**< Bit mask for DMA_CH6ENS */
<> 150:02e0a0aed4ec 1110 #define _DMA_CHENS_CH6ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
<> 150:02e0a0aed4ec 1111 #define DMA_CHENS_CH6ENS_DEFAULT (_DMA_CHENS_CH6ENS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHENS */
<> 150:02e0a0aed4ec 1112 #define DMA_CHENS_CH7ENS (0x1UL << 7) /**< Channel 7 Enable Set */
<> 150:02e0a0aed4ec 1113 #define _DMA_CHENS_CH7ENS_SHIFT 7 /**< Shift value for DMA_CH7ENS */
<> 150:02e0a0aed4ec 1114 #define _DMA_CHENS_CH7ENS_MASK 0x80UL /**< Bit mask for DMA_CH7ENS */
<> 150:02e0a0aed4ec 1115 #define _DMA_CHENS_CH7ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
<> 150:02e0a0aed4ec 1116 #define DMA_CHENS_CH7ENS_DEFAULT (_DMA_CHENS_CH7ENS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHENS */
<> 150:02e0a0aed4ec 1117 #define DMA_CHENS_CH8ENS (0x1UL << 8) /**< Channel 8 Enable Set */
<> 150:02e0a0aed4ec 1118 #define _DMA_CHENS_CH8ENS_SHIFT 8 /**< Shift value for DMA_CH8ENS */
<> 150:02e0a0aed4ec 1119 #define _DMA_CHENS_CH8ENS_MASK 0x100UL /**< Bit mask for DMA_CH8ENS */
<> 150:02e0a0aed4ec 1120 #define _DMA_CHENS_CH8ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
<> 150:02e0a0aed4ec 1121 #define DMA_CHENS_CH8ENS_DEFAULT (_DMA_CHENS_CH8ENS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHENS */
<> 150:02e0a0aed4ec 1122 #define DMA_CHENS_CH9ENS (0x1UL << 9) /**< Channel 9 Enable Set */
<> 150:02e0a0aed4ec 1123 #define _DMA_CHENS_CH9ENS_SHIFT 9 /**< Shift value for DMA_CH9ENS */
<> 150:02e0a0aed4ec 1124 #define _DMA_CHENS_CH9ENS_MASK 0x200UL /**< Bit mask for DMA_CH9ENS */
<> 150:02e0a0aed4ec 1125 #define _DMA_CHENS_CH9ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
<> 150:02e0a0aed4ec 1126 #define DMA_CHENS_CH9ENS_DEFAULT (_DMA_CHENS_CH9ENS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHENS */
<> 150:02e0a0aed4ec 1127 #define DMA_CHENS_CH10ENS (0x1UL << 10) /**< Channel 10 Enable Set */
<> 150:02e0a0aed4ec 1128 #define _DMA_CHENS_CH10ENS_SHIFT 10 /**< Shift value for DMA_CH10ENS */
<> 150:02e0a0aed4ec 1129 #define _DMA_CHENS_CH10ENS_MASK 0x400UL /**< Bit mask for DMA_CH10ENS */
<> 150:02e0a0aed4ec 1130 #define _DMA_CHENS_CH10ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
<> 150:02e0a0aed4ec 1131 #define DMA_CHENS_CH10ENS_DEFAULT (_DMA_CHENS_CH10ENS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHENS */
<> 150:02e0a0aed4ec 1132 #define DMA_CHENS_CH11ENS (0x1UL << 11) /**< Channel 11 Enable Set */
<> 150:02e0a0aed4ec 1133 #define _DMA_CHENS_CH11ENS_SHIFT 11 /**< Shift value for DMA_CH11ENS */
<> 150:02e0a0aed4ec 1134 #define _DMA_CHENS_CH11ENS_MASK 0x800UL /**< Bit mask for DMA_CH11ENS */
<> 150:02e0a0aed4ec 1135 #define _DMA_CHENS_CH11ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
<> 150:02e0a0aed4ec 1136 #define DMA_CHENS_CH11ENS_DEFAULT (_DMA_CHENS_CH11ENS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHENS */
<> 150:02e0a0aed4ec 1137
<> 150:02e0a0aed4ec 1138 /* Bit fields for DMA CHENC */
<> 150:02e0a0aed4ec 1139 #define _DMA_CHENC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHENC */
<> 150:02e0a0aed4ec 1140 #define _DMA_CHENC_MASK 0x00000FFFUL /**< Mask for DMA_CHENC */
<> 150:02e0a0aed4ec 1141 #define DMA_CHENC_CH0ENC (0x1UL << 0) /**< Channel 0 Enable Clear */
<> 150:02e0a0aed4ec 1142 #define _DMA_CHENC_CH0ENC_SHIFT 0 /**< Shift value for DMA_CH0ENC */
<> 150:02e0a0aed4ec 1143 #define _DMA_CHENC_CH0ENC_MASK 0x1UL /**< Bit mask for DMA_CH0ENC */
<> 150:02e0a0aed4ec 1144 #define _DMA_CHENC_CH0ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
<> 150:02e0a0aed4ec 1145 #define DMA_CHENC_CH0ENC_DEFAULT (_DMA_CHENC_CH0ENC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHENC */
<> 150:02e0a0aed4ec 1146 #define DMA_CHENC_CH1ENC (0x1UL << 1) /**< Channel 1 Enable Clear */
<> 150:02e0a0aed4ec 1147 #define _DMA_CHENC_CH1ENC_SHIFT 1 /**< Shift value for DMA_CH1ENC */
<> 150:02e0a0aed4ec 1148 #define _DMA_CHENC_CH1ENC_MASK 0x2UL /**< Bit mask for DMA_CH1ENC */
<> 150:02e0a0aed4ec 1149 #define _DMA_CHENC_CH1ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
<> 150:02e0a0aed4ec 1150 #define DMA_CHENC_CH1ENC_DEFAULT (_DMA_CHENC_CH1ENC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHENC */
<> 150:02e0a0aed4ec 1151 #define DMA_CHENC_CH2ENC (0x1UL << 2) /**< Channel 2 Enable Clear */
<> 150:02e0a0aed4ec 1152 #define _DMA_CHENC_CH2ENC_SHIFT 2 /**< Shift value for DMA_CH2ENC */
<> 150:02e0a0aed4ec 1153 #define _DMA_CHENC_CH2ENC_MASK 0x4UL /**< Bit mask for DMA_CH2ENC */
<> 150:02e0a0aed4ec 1154 #define _DMA_CHENC_CH2ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
<> 150:02e0a0aed4ec 1155 #define DMA_CHENC_CH2ENC_DEFAULT (_DMA_CHENC_CH2ENC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHENC */
<> 150:02e0a0aed4ec 1156 #define DMA_CHENC_CH3ENC (0x1UL << 3) /**< Channel 3 Enable Clear */
<> 150:02e0a0aed4ec 1157 #define _DMA_CHENC_CH3ENC_SHIFT 3 /**< Shift value for DMA_CH3ENC */
<> 150:02e0a0aed4ec 1158 #define _DMA_CHENC_CH3ENC_MASK 0x8UL /**< Bit mask for DMA_CH3ENC */
<> 150:02e0a0aed4ec 1159 #define _DMA_CHENC_CH3ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
<> 150:02e0a0aed4ec 1160 #define DMA_CHENC_CH3ENC_DEFAULT (_DMA_CHENC_CH3ENC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHENC */
<> 150:02e0a0aed4ec 1161 #define DMA_CHENC_CH4ENC (0x1UL << 4) /**< Channel 4 Enable Clear */
<> 150:02e0a0aed4ec 1162 #define _DMA_CHENC_CH4ENC_SHIFT 4 /**< Shift value for DMA_CH4ENC */
<> 150:02e0a0aed4ec 1163 #define _DMA_CHENC_CH4ENC_MASK 0x10UL /**< Bit mask for DMA_CH4ENC */
<> 150:02e0a0aed4ec 1164 #define _DMA_CHENC_CH4ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
<> 150:02e0a0aed4ec 1165 #define DMA_CHENC_CH4ENC_DEFAULT (_DMA_CHENC_CH4ENC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHENC */
<> 150:02e0a0aed4ec 1166 #define DMA_CHENC_CH5ENC (0x1UL << 5) /**< Channel 5 Enable Clear */
<> 150:02e0a0aed4ec 1167 #define _DMA_CHENC_CH5ENC_SHIFT 5 /**< Shift value for DMA_CH5ENC */
<> 150:02e0a0aed4ec 1168 #define _DMA_CHENC_CH5ENC_MASK 0x20UL /**< Bit mask for DMA_CH5ENC */
<> 150:02e0a0aed4ec 1169 #define _DMA_CHENC_CH5ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
<> 150:02e0a0aed4ec 1170 #define DMA_CHENC_CH5ENC_DEFAULT (_DMA_CHENC_CH5ENC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHENC */
<> 150:02e0a0aed4ec 1171 #define DMA_CHENC_CH6ENC (0x1UL << 6) /**< Channel 6 Enable Clear */
<> 150:02e0a0aed4ec 1172 #define _DMA_CHENC_CH6ENC_SHIFT 6 /**< Shift value for DMA_CH6ENC */
<> 150:02e0a0aed4ec 1173 #define _DMA_CHENC_CH6ENC_MASK 0x40UL /**< Bit mask for DMA_CH6ENC */
<> 150:02e0a0aed4ec 1174 #define _DMA_CHENC_CH6ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
<> 150:02e0a0aed4ec 1175 #define DMA_CHENC_CH6ENC_DEFAULT (_DMA_CHENC_CH6ENC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHENC */
<> 150:02e0a0aed4ec 1176 #define DMA_CHENC_CH7ENC (0x1UL << 7) /**< Channel 7 Enable Clear */
<> 150:02e0a0aed4ec 1177 #define _DMA_CHENC_CH7ENC_SHIFT 7 /**< Shift value for DMA_CH7ENC */
<> 150:02e0a0aed4ec 1178 #define _DMA_CHENC_CH7ENC_MASK 0x80UL /**< Bit mask for DMA_CH7ENC */
<> 150:02e0a0aed4ec 1179 #define _DMA_CHENC_CH7ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
<> 150:02e0a0aed4ec 1180 #define DMA_CHENC_CH7ENC_DEFAULT (_DMA_CHENC_CH7ENC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHENC */
<> 150:02e0a0aed4ec 1181 #define DMA_CHENC_CH8ENC (0x1UL << 8) /**< Channel 8 Enable Clear */
<> 150:02e0a0aed4ec 1182 #define _DMA_CHENC_CH8ENC_SHIFT 8 /**< Shift value for DMA_CH8ENC */
<> 150:02e0a0aed4ec 1183 #define _DMA_CHENC_CH8ENC_MASK 0x100UL /**< Bit mask for DMA_CH8ENC */
<> 150:02e0a0aed4ec 1184 #define _DMA_CHENC_CH8ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
<> 150:02e0a0aed4ec 1185 #define DMA_CHENC_CH8ENC_DEFAULT (_DMA_CHENC_CH8ENC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHENC */
<> 150:02e0a0aed4ec 1186 #define DMA_CHENC_CH9ENC (0x1UL << 9) /**< Channel 9 Enable Clear */
<> 150:02e0a0aed4ec 1187 #define _DMA_CHENC_CH9ENC_SHIFT 9 /**< Shift value for DMA_CH9ENC */
<> 150:02e0a0aed4ec 1188 #define _DMA_CHENC_CH9ENC_MASK 0x200UL /**< Bit mask for DMA_CH9ENC */
<> 150:02e0a0aed4ec 1189 #define _DMA_CHENC_CH9ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
<> 150:02e0a0aed4ec 1190 #define DMA_CHENC_CH9ENC_DEFAULT (_DMA_CHENC_CH9ENC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHENC */
<> 150:02e0a0aed4ec 1191 #define DMA_CHENC_CH10ENC (0x1UL << 10) /**< Channel 10 Enable Clear */
<> 150:02e0a0aed4ec 1192 #define _DMA_CHENC_CH10ENC_SHIFT 10 /**< Shift value for DMA_CH10ENC */
<> 150:02e0a0aed4ec 1193 #define _DMA_CHENC_CH10ENC_MASK 0x400UL /**< Bit mask for DMA_CH10ENC */
<> 150:02e0a0aed4ec 1194 #define _DMA_CHENC_CH10ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
<> 150:02e0a0aed4ec 1195 #define DMA_CHENC_CH10ENC_DEFAULT (_DMA_CHENC_CH10ENC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHENC */
<> 150:02e0a0aed4ec 1196 #define DMA_CHENC_CH11ENC (0x1UL << 11) /**< Channel 11 Enable Clear */
<> 150:02e0a0aed4ec 1197 #define _DMA_CHENC_CH11ENC_SHIFT 11 /**< Shift value for DMA_CH11ENC */
<> 150:02e0a0aed4ec 1198 #define _DMA_CHENC_CH11ENC_MASK 0x800UL /**< Bit mask for DMA_CH11ENC */
<> 150:02e0a0aed4ec 1199 #define _DMA_CHENC_CH11ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
<> 150:02e0a0aed4ec 1200 #define DMA_CHENC_CH11ENC_DEFAULT (_DMA_CHENC_CH11ENC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHENC */
<> 150:02e0a0aed4ec 1201
<> 150:02e0a0aed4ec 1202 /* Bit fields for DMA CHALTS */
<> 150:02e0a0aed4ec 1203 #define _DMA_CHALTS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHALTS */
<> 150:02e0a0aed4ec 1204 #define _DMA_CHALTS_MASK 0x00000FFFUL /**< Mask for DMA_CHALTS */
<> 150:02e0a0aed4ec 1205 #define DMA_CHALTS_CH0ALTS (0x1UL << 0) /**< Channel 0 Alternate Structure Set */
<> 150:02e0a0aed4ec 1206 #define _DMA_CHALTS_CH0ALTS_SHIFT 0 /**< Shift value for DMA_CH0ALTS */
<> 150:02e0a0aed4ec 1207 #define _DMA_CHALTS_CH0ALTS_MASK 0x1UL /**< Bit mask for DMA_CH0ALTS */
<> 150:02e0a0aed4ec 1208 #define _DMA_CHALTS_CH0ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
<> 150:02e0a0aed4ec 1209 #define DMA_CHALTS_CH0ALTS_DEFAULT (_DMA_CHALTS_CH0ALTS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHALTS */
<> 150:02e0a0aed4ec 1210 #define DMA_CHALTS_CH1ALTS (0x1UL << 1) /**< Channel 1 Alternate Structure Set */
<> 150:02e0a0aed4ec 1211 #define _DMA_CHALTS_CH1ALTS_SHIFT 1 /**< Shift value for DMA_CH1ALTS */
<> 150:02e0a0aed4ec 1212 #define _DMA_CHALTS_CH1ALTS_MASK 0x2UL /**< Bit mask for DMA_CH1ALTS */
<> 150:02e0a0aed4ec 1213 #define _DMA_CHALTS_CH1ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
<> 150:02e0a0aed4ec 1214 #define DMA_CHALTS_CH1ALTS_DEFAULT (_DMA_CHALTS_CH1ALTS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHALTS */
<> 150:02e0a0aed4ec 1215 #define DMA_CHALTS_CH2ALTS (0x1UL << 2) /**< Channel 2 Alternate Structure Set */
<> 150:02e0a0aed4ec 1216 #define _DMA_CHALTS_CH2ALTS_SHIFT 2 /**< Shift value for DMA_CH2ALTS */
<> 150:02e0a0aed4ec 1217 #define _DMA_CHALTS_CH2ALTS_MASK 0x4UL /**< Bit mask for DMA_CH2ALTS */
<> 150:02e0a0aed4ec 1218 #define _DMA_CHALTS_CH2ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
<> 150:02e0a0aed4ec 1219 #define DMA_CHALTS_CH2ALTS_DEFAULT (_DMA_CHALTS_CH2ALTS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHALTS */
<> 150:02e0a0aed4ec 1220 #define DMA_CHALTS_CH3ALTS (0x1UL << 3) /**< Channel 3 Alternate Structure Set */
<> 150:02e0a0aed4ec 1221 #define _DMA_CHALTS_CH3ALTS_SHIFT 3 /**< Shift value for DMA_CH3ALTS */
<> 150:02e0a0aed4ec 1222 #define _DMA_CHALTS_CH3ALTS_MASK 0x8UL /**< Bit mask for DMA_CH3ALTS */
<> 150:02e0a0aed4ec 1223 #define _DMA_CHALTS_CH3ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
<> 150:02e0a0aed4ec 1224 #define DMA_CHALTS_CH3ALTS_DEFAULT (_DMA_CHALTS_CH3ALTS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHALTS */
<> 150:02e0a0aed4ec 1225 #define DMA_CHALTS_CH4ALTS (0x1UL << 4) /**< Channel 4 Alternate Structure Set */
<> 150:02e0a0aed4ec 1226 #define _DMA_CHALTS_CH4ALTS_SHIFT 4 /**< Shift value for DMA_CH4ALTS */
<> 150:02e0a0aed4ec 1227 #define _DMA_CHALTS_CH4ALTS_MASK 0x10UL /**< Bit mask for DMA_CH4ALTS */
<> 150:02e0a0aed4ec 1228 #define _DMA_CHALTS_CH4ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
<> 150:02e0a0aed4ec 1229 #define DMA_CHALTS_CH4ALTS_DEFAULT (_DMA_CHALTS_CH4ALTS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHALTS */
<> 150:02e0a0aed4ec 1230 #define DMA_CHALTS_CH5ALTS (0x1UL << 5) /**< Channel 5 Alternate Structure Set */
<> 150:02e0a0aed4ec 1231 #define _DMA_CHALTS_CH5ALTS_SHIFT 5 /**< Shift value for DMA_CH5ALTS */
<> 150:02e0a0aed4ec 1232 #define _DMA_CHALTS_CH5ALTS_MASK 0x20UL /**< Bit mask for DMA_CH5ALTS */
<> 150:02e0a0aed4ec 1233 #define _DMA_CHALTS_CH5ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
<> 150:02e0a0aed4ec 1234 #define DMA_CHALTS_CH5ALTS_DEFAULT (_DMA_CHALTS_CH5ALTS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHALTS */
<> 150:02e0a0aed4ec 1235 #define DMA_CHALTS_CH6ALTS (0x1UL << 6) /**< Channel 6 Alternate Structure Set */
<> 150:02e0a0aed4ec 1236 #define _DMA_CHALTS_CH6ALTS_SHIFT 6 /**< Shift value for DMA_CH6ALTS */
<> 150:02e0a0aed4ec 1237 #define _DMA_CHALTS_CH6ALTS_MASK 0x40UL /**< Bit mask for DMA_CH6ALTS */
<> 150:02e0a0aed4ec 1238 #define _DMA_CHALTS_CH6ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
<> 150:02e0a0aed4ec 1239 #define DMA_CHALTS_CH6ALTS_DEFAULT (_DMA_CHALTS_CH6ALTS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHALTS */
<> 150:02e0a0aed4ec 1240 #define DMA_CHALTS_CH7ALTS (0x1UL << 7) /**< Channel 7 Alternate Structure Set */
<> 150:02e0a0aed4ec 1241 #define _DMA_CHALTS_CH7ALTS_SHIFT 7 /**< Shift value for DMA_CH7ALTS */
<> 150:02e0a0aed4ec 1242 #define _DMA_CHALTS_CH7ALTS_MASK 0x80UL /**< Bit mask for DMA_CH7ALTS */
<> 150:02e0a0aed4ec 1243 #define _DMA_CHALTS_CH7ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
<> 150:02e0a0aed4ec 1244 #define DMA_CHALTS_CH7ALTS_DEFAULT (_DMA_CHALTS_CH7ALTS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHALTS */
<> 150:02e0a0aed4ec 1245 #define DMA_CHALTS_CH8ALTS (0x1UL << 8) /**< Channel 8 Alternate Structure Set */
<> 150:02e0a0aed4ec 1246 #define _DMA_CHALTS_CH8ALTS_SHIFT 8 /**< Shift value for DMA_CH8ALTS */
<> 150:02e0a0aed4ec 1247 #define _DMA_CHALTS_CH8ALTS_MASK 0x100UL /**< Bit mask for DMA_CH8ALTS */
<> 150:02e0a0aed4ec 1248 #define _DMA_CHALTS_CH8ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
<> 150:02e0a0aed4ec 1249 #define DMA_CHALTS_CH8ALTS_DEFAULT (_DMA_CHALTS_CH8ALTS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHALTS */
<> 150:02e0a0aed4ec 1250 #define DMA_CHALTS_CH9ALTS (0x1UL << 9) /**< Channel 9 Alternate Structure Set */
<> 150:02e0a0aed4ec 1251 #define _DMA_CHALTS_CH9ALTS_SHIFT 9 /**< Shift value for DMA_CH9ALTS */
<> 150:02e0a0aed4ec 1252 #define _DMA_CHALTS_CH9ALTS_MASK 0x200UL /**< Bit mask for DMA_CH9ALTS */
<> 150:02e0a0aed4ec 1253 #define _DMA_CHALTS_CH9ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
<> 150:02e0a0aed4ec 1254 #define DMA_CHALTS_CH9ALTS_DEFAULT (_DMA_CHALTS_CH9ALTS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHALTS */
<> 150:02e0a0aed4ec 1255 #define DMA_CHALTS_CH10ALTS (0x1UL << 10) /**< Channel 10 Alternate Structure Set */
<> 150:02e0a0aed4ec 1256 #define _DMA_CHALTS_CH10ALTS_SHIFT 10 /**< Shift value for DMA_CH10ALTS */
<> 150:02e0a0aed4ec 1257 #define _DMA_CHALTS_CH10ALTS_MASK 0x400UL /**< Bit mask for DMA_CH10ALTS */
<> 150:02e0a0aed4ec 1258 #define _DMA_CHALTS_CH10ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
<> 150:02e0a0aed4ec 1259 #define DMA_CHALTS_CH10ALTS_DEFAULT (_DMA_CHALTS_CH10ALTS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHALTS */
<> 150:02e0a0aed4ec 1260 #define DMA_CHALTS_CH11ALTS (0x1UL << 11) /**< Channel 11 Alternate Structure Set */
<> 150:02e0a0aed4ec 1261 #define _DMA_CHALTS_CH11ALTS_SHIFT 11 /**< Shift value for DMA_CH11ALTS */
<> 150:02e0a0aed4ec 1262 #define _DMA_CHALTS_CH11ALTS_MASK 0x800UL /**< Bit mask for DMA_CH11ALTS */
<> 150:02e0a0aed4ec 1263 #define _DMA_CHALTS_CH11ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
<> 150:02e0a0aed4ec 1264 #define DMA_CHALTS_CH11ALTS_DEFAULT (_DMA_CHALTS_CH11ALTS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHALTS */
<> 150:02e0a0aed4ec 1265
<> 150:02e0a0aed4ec 1266 /* Bit fields for DMA CHALTC */
<> 150:02e0a0aed4ec 1267 #define _DMA_CHALTC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHALTC */
<> 150:02e0a0aed4ec 1268 #define _DMA_CHALTC_MASK 0x00000FFFUL /**< Mask for DMA_CHALTC */
<> 150:02e0a0aed4ec 1269 #define DMA_CHALTC_CH0ALTC (0x1UL << 0) /**< Channel 0 Alternate Clear */
<> 150:02e0a0aed4ec 1270 #define _DMA_CHALTC_CH0ALTC_SHIFT 0 /**< Shift value for DMA_CH0ALTC */
<> 150:02e0a0aed4ec 1271 #define _DMA_CHALTC_CH0ALTC_MASK 0x1UL /**< Bit mask for DMA_CH0ALTC */
<> 150:02e0a0aed4ec 1272 #define _DMA_CHALTC_CH0ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
<> 150:02e0a0aed4ec 1273 #define DMA_CHALTC_CH0ALTC_DEFAULT (_DMA_CHALTC_CH0ALTC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHALTC */
<> 150:02e0a0aed4ec 1274 #define DMA_CHALTC_CH1ALTC (0x1UL << 1) /**< Channel 1 Alternate Clear */
<> 150:02e0a0aed4ec 1275 #define _DMA_CHALTC_CH1ALTC_SHIFT 1 /**< Shift value for DMA_CH1ALTC */
<> 150:02e0a0aed4ec 1276 #define _DMA_CHALTC_CH1ALTC_MASK 0x2UL /**< Bit mask for DMA_CH1ALTC */
<> 150:02e0a0aed4ec 1277 #define _DMA_CHALTC_CH1ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
<> 150:02e0a0aed4ec 1278 #define DMA_CHALTC_CH1ALTC_DEFAULT (_DMA_CHALTC_CH1ALTC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHALTC */
<> 150:02e0a0aed4ec 1279 #define DMA_CHALTC_CH2ALTC (0x1UL << 2) /**< Channel 2 Alternate Clear */
<> 150:02e0a0aed4ec 1280 #define _DMA_CHALTC_CH2ALTC_SHIFT 2 /**< Shift value for DMA_CH2ALTC */
<> 150:02e0a0aed4ec 1281 #define _DMA_CHALTC_CH2ALTC_MASK 0x4UL /**< Bit mask for DMA_CH2ALTC */
<> 150:02e0a0aed4ec 1282 #define _DMA_CHALTC_CH2ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
<> 150:02e0a0aed4ec 1283 #define DMA_CHALTC_CH2ALTC_DEFAULT (_DMA_CHALTC_CH2ALTC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHALTC */
<> 150:02e0a0aed4ec 1284 #define DMA_CHALTC_CH3ALTC (0x1UL << 3) /**< Channel 3 Alternate Clear */
<> 150:02e0a0aed4ec 1285 #define _DMA_CHALTC_CH3ALTC_SHIFT 3 /**< Shift value for DMA_CH3ALTC */
<> 150:02e0a0aed4ec 1286 #define _DMA_CHALTC_CH3ALTC_MASK 0x8UL /**< Bit mask for DMA_CH3ALTC */
<> 150:02e0a0aed4ec 1287 #define _DMA_CHALTC_CH3ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
<> 150:02e0a0aed4ec 1288 #define DMA_CHALTC_CH3ALTC_DEFAULT (_DMA_CHALTC_CH3ALTC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHALTC */
<> 150:02e0a0aed4ec 1289 #define DMA_CHALTC_CH4ALTC (0x1UL << 4) /**< Channel 4 Alternate Clear */
<> 150:02e0a0aed4ec 1290 #define _DMA_CHALTC_CH4ALTC_SHIFT 4 /**< Shift value for DMA_CH4ALTC */
<> 150:02e0a0aed4ec 1291 #define _DMA_CHALTC_CH4ALTC_MASK 0x10UL /**< Bit mask for DMA_CH4ALTC */
<> 150:02e0a0aed4ec 1292 #define _DMA_CHALTC_CH4ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
<> 150:02e0a0aed4ec 1293 #define DMA_CHALTC_CH4ALTC_DEFAULT (_DMA_CHALTC_CH4ALTC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHALTC */
<> 150:02e0a0aed4ec 1294 #define DMA_CHALTC_CH5ALTC (0x1UL << 5) /**< Channel 5 Alternate Clear */
<> 150:02e0a0aed4ec 1295 #define _DMA_CHALTC_CH5ALTC_SHIFT 5 /**< Shift value for DMA_CH5ALTC */
<> 150:02e0a0aed4ec 1296 #define _DMA_CHALTC_CH5ALTC_MASK 0x20UL /**< Bit mask for DMA_CH5ALTC */
<> 150:02e0a0aed4ec 1297 #define _DMA_CHALTC_CH5ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
<> 150:02e0a0aed4ec 1298 #define DMA_CHALTC_CH5ALTC_DEFAULT (_DMA_CHALTC_CH5ALTC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHALTC */
<> 150:02e0a0aed4ec 1299 #define DMA_CHALTC_CH6ALTC (0x1UL << 6) /**< Channel 6 Alternate Clear */
<> 150:02e0a0aed4ec 1300 #define _DMA_CHALTC_CH6ALTC_SHIFT 6 /**< Shift value for DMA_CH6ALTC */
<> 150:02e0a0aed4ec 1301 #define _DMA_CHALTC_CH6ALTC_MASK 0x40UL /**< Bit mask for DMA_CH6ALTC */
<> 150:02e0a0aed4ec 1302 #define _DMA_CHALTC_CH6ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
<> 150:02e0a0aed4ec 1303 #define DMA_CHALTC_CH6ALTC_DEFAULT (_DMA_CHALTC_CH6ALTC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHALTC */
<> 150:02e0a0aed4ec 1304 #define DMA_CHALTC_CH7ALTC (0x1UL << 7) /**< Channel 7 Alternate Clear */
<> 150:02e0a0aed4ec 1305 #define _DMA_CHALTC_CH7ALTC_SHIFT 7 /**< Shift value for DMA_CH7ALTC */
<> 150:02e0a0aed4ec 1306 #define _DMA_CHALTC_CH7ALTC_MASK 0x80UL /**< Bit mask for DMA_CH7ALTC */
<> 150:02e0a0aed4ec 1307 #define _DMA_CHALTC_CH7ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
<> 150:02e0a0aed4ec 1308 #define DMA_CHALTC_CH7ALTC_DEFAULT (_DMA_CHALTC_CH7ALTC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHALTC */
<> 150:02e0a0aed4ec 1309 #define DMA_CHALTC_CH8ALTC (0x1UL << 8) /**< Channel 8 Alternate Clear */
<> 150:02e0a0aed4ec 1310 #define _DMA_CHALTC_CH8ALTC_SHIFT 8 /**< Shift value for DMA_CH8ALTC */
<> 150:02e0a0aed4ec 1311 #define _DMA_CHALTC_CH8ALTC_MASK 0x100UL /**< Bit mask for DMA_CH8ALTC */
<> 150:02e0a0aed4ec 1312 #define _DMA_CHALTC_CH8ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
<> 150:02e0a0aed4ec 1313 #define DMA_CHALTC_CH8ALTC_DEFAULT (_DMA_CHALTC_CH8ALTC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHALTC */
<> 150:02e0a0aed4ec 1314 #define DMA_CHALTC_CH9ALTC (0x1UL << 9) /**< Channel 9 Alternate Clear */
<> 150:02e0a0aed4ec 1315 #define _DMA_CHALTC_CH9ALTC_SHIFT 9 /**< Shift value for DMA_CH9ALTC */
<> 150:02e0a0aed4ec 1316 #define _DMA_CHALTC_CH9ALTC_MASK 0x200UL /**< Bit mask for DMA_CH9ALTC */
<> 150:02e0a0aed4ec 1317 #define _DMA_CHALTC_CH9ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
<> 150:02e0a0aed4ec 1318 #define DMA_CHALTC_CH9ALTC_DEFAULT (_DMA_CHALTC_CH9ALTC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHALTC */
<> 150:02e0a0aed4ec 1319 #define DMA_CHALTC_CH10ALTC (0x1UL << 10) /**< Channel 10 Alternate Clear */
<> 150:02e0a0aed4ec 1320 #define _DMA_CHALTC_CH10ALTC_SHIFT 10 /**< Shift value for DMA_CH10ALTC */
<> 150:02e0a0aed4ec 1321 #define _DMA_CHALTC_CH10ALTC_MASK 0x400UL /**< Bit mask for DMA_CH10ALTC */
<> 150:02e0a0aed4ec 1322 #define _DMA_CHALTC_CH10ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
<> 150:02e0a0aed4ec 1323 #define DMA_CHALTC_CH10ALTC_DEFAULT (_DMA_CHALTC_CH10ALTC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHALTC */
<> 150:02e0a0aed4ec 1324 #define DMA_CHALTC_CH11ALTC (0x1UL << 11) /**< Channel 11 Alternate Clear */
<> 150:02e0a0aed4ec 1325 #define _DMA_CHALTC_CH11ALTC_SHIFT 11 /**< Shift value for DMA_CH11ALTC */
<> 150:02e0a0aed4ec 1326 #define _DMA_CHALTC_CH11ALTC_MASK 0x800UL /**< Bit mask for DMA_CH11ALTC */
<> 150:02e0a0aed4ec 1327 #define _DMA_CHALTC_CH11ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
<> 150:02e0a0aed4ec 1328 #define DMA_CHALTC_CH11ALTC_DEFAULT (_DMA_CHALTC_CH11ALTC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHALTC */
<> 150:02e0a0aed4ec 1329
<> 150:02e0a0aed4ec 1330 /* Bit fields for DMA CHPRIS */
<> 150:02e0a0aed4ec 1331 #define _DMA_CHPRIS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHPRIS */
<> 150:02e0a0aed4ec 1332 #define _DMA_CHPRIS_MASK 0x00000FFFUL /**< Mask for DMA_CHPRIS */
<> 150:02e0a0aed4ec 1333 #define DMA_CHPRIS_CH0PRIS (0x1UL << 0) /**< Channel 0 High Priority Set */
<> 150:02e0a0aed4ec 1334 #define _DMA_CHPRIS_CH0PRIS_SHIFT 0 /**< Shift value for DMA_CH0PRIS */
<> 150:02e0a0aed4ec 1335 #define _DMA_CHPRIS_CH0PRIS_MASK 0x1UL /**< Bit mask for DMA_CH0PRIS */
<> 150:02e0a0aed4ec 1336 #define _DMA_CHPRIS_CH0PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
<> 150:02e0a0aed4ec 1337 #define DMA_CHPRIS_CH0PRIS_DEFAULT (_DMA_CHPRIS_CH0PRIS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHPRIS */
<> 150:02e0a0aed4ec 1338 #define DMA_CHPRIS_CH1PRIS (0x1UL << 1) /**< Channel 1 High Priority Set */
<> 150:02e0a0aed4ec 1339 #define _DMA_CHPRIS_CH1PRIS_SHIFT 1 /**< Shift value for DMA_CH1PRIS */
<> 150:02e0a0aed4ec 1340 #define _DMA_CHPRIS_CH1PRIS_MASK 0x2UL /**< Bit mask for DMA_CH1PRIS */
<> 150:02e0a0aed4ec 1341 #define _DMA_CHPRIS_CH1PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
<> 150:02e0a0aed4ec 1342 #define DMA_CHPRIS_CH1PRIS_DEFAULT (_DMA_CHPRIS_CH1PRIS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHPRIS */
<> 150:02e0a0aed4ec 1343 #define DMA_CHPRIS_CH2PRIS (0x1UL << 2) /**< Channel 2 High Priority Set */
<> 150:02e0a0aed4ec 1344 #define _DMA_CHPRIS_CH2PRIS_SHIFT 2 /**< Shift value for DMA_CH2PRIS */
<> 150:02e0a0aed4ec 1345 #define _DMA_CHPRIS_CH2PRIS_MASK 0x4UL /**< Bit mask for DMA_CH2PRIS */
<> 150:02e0a0aed4ec 1346 #define _DMA_CHPRIS_CH2PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
<> 150:02e0a0aed4ec 1347 #define DMA_CHPRIS_CH2PRIS_DEFAULT (_DMA_CHPRIS_CH2PRIS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHPRIS */
<> 150:02e0a0aed4ec 1348 #define DMA_CHPRIS_CH3PRIS (0x1UL << 3) /**< Channel 3 High Priority Set */
<> 150:02e0a0aed4ec 1349 #define _DMA_CHPRIS_CH3PRIS_SHIFT 3 /**< Shift value for DMA_CH3PRIS */
<> 150:02e0a0aed4ec 1350 #define _DMA_CHPRIS_CH3PRIS_MASK 0x8UL /**< Bit mask for DMA_CH3PRIS */
<> 150:02e0a0aed4ec 1351 #define _DMA_CHPRIS_CH3PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
<> 150:02e0a0aed4ec 1352 #define DMA_CHPRIS_CH3PRIS_DEFAULT (_DMA_CHPRIS_CH3PRIS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHPRIS */
<> 150:02e0a0aed4ec 1353 #define DMA_CHPRIS_CH4PRIS (0x1UL << 4) /**< Channel 4 High Priority Set */
<> 150:02e0a0aed4ec 1354 #define _DMA_CHPRIS_CH4PRIS_SHIFT 4 /**< Shift value for DMA_CH4PRIS */
<> 150:02e0a0aed4ec 1355 #define _DMA_CHPRIS_CH4PRIS_MASK 0x10UL /**< Bit mask for DMA_CH4PRIS */
<> 150:02e0a0aed4ec 1356 #define _DMA_CHPRIS_CH4PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
<> 150:02e0a0aed4ec 1357 #define DMA_CHPRIS_CH4PRIS_DEFAULT (_DMA_CHPRIS_CH4PRIS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHPRIS */
<> 150:02e0a0aed4ec 1358 #define DMA_CHPRIS_CH5PRIS (0x1UL << 5) /**< Channel 5 High Priority Set */
<> 150:02e0a0aed4ec 1359 #define _DMA_CHPRIS_CH5PRIS_SHIFT 5 /**< Shift value for DMA_CH5PRIS */
<> 150:02e0a0aed4ec 1360 #define _DMA_CHPRIS_CH5PRIS_MASK 0x20UL /**< Bit mask for DMA_CH5PRIS */
<> 150:02e0a0aed4ec 1361 #define _DMA_CHPRIS_CH5PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
<> 150:02e0a0aed4ec 1362 #define DMA_CHPRIS_CH5PRIS_DEFAULT (_DMA_CHPRIS_CH5PRIS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHPRIS */
<> 150:02e0a0aed4ec 1363 #define DMA_CHPRIS_CH6PRIS (0x1UL << 6) /**< Channel 6 High Priority Set */
<> 150:02e0a0aed4ec 1364 #define _DMA_CHPRIS_CH6PRIS_SHIFT 6 /**< Shift value for DMA_CH6PRIS */
<> 150:02e0a0aed4ec 1365 #define _DMA_CHPRIS_CH6PRIS_MASK 0x40UL /**< Bit mask for DMA_CH6PRIS */
<> 150:02e0a0aed4ec 1366 #define _DMA_CHPRIS_CH6PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
<> 150:02e0a0aed4ec 1367 #define DMA_CHPRIS_CH6PRIS_DEFAULT (_DMA_CHPRIS_CH6PRIS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHPRIS */
<> 150:02e0a0aed4ec 1368 #define DMA_CHPRIS_CH7PRIS (0x1UL << 7) /**< Channel 7 High Priority Set */
<> 150:02e0a0aed4ec 1369 #define _DMA_CHPRIS_CH7PRIS_SHIFT 7 /**< Shift value for DMA_CH7PRIS */
<> 150:02e0a0aed4ec 1370 #define _DMA_CHPRIS_CH7PRIS_MASK 0x80UL /**< Bit mask for DMA_CH7PRIS */
<> 150:02e0a0aed4ec 1371 #define _DMA_CHPRIS_CH7PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
<> 150:02e0a0aed4ec 1372 #define DMA_CHPRIS_CH7PRIS_DEFAULT (_DMA_CHPRIS_CH7PRIS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHPRIS */
<> 150:02e0a0aed4ec 1373 #define DMA_CHPRIS_CH8PRIS (0x1UL << 8) /**< Channel 8 High Priority Set */
<> 150:02e0a0aed4ec 1374 #define _DMA_CHPRIS_CH8PRIS_SHIFT 8 /**< Shift value for DMA_CH8PRIS */
<> 150:02e0a0aed4ec 1375 #define _DMA_CHPRIS_CH8PRIS_MASK 0x100UL /**< Bit mask for DMA_CH8PRIS */
<> 150:02e0a0aed4ec 1376 #define _DMA_CHPRIS_CH8PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
<> 150:02e0a0aed4ec 1377 #define DMA_CHPRIS_CH8PRIS_DEFAULT (_DMA_CHPRIS_CH8PRIS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHPRIS */
<> 150:02e0a0aed4ec 1378 #define DMA_CHPRIS_CH9PRIS (0x1UL << 9) /**< Channel 9 High Priority Set */
<> 150:02e0a0aed4ec 1379 #define _DMA_CHPRIS_CH9PRIS_SHIFT 9 /**< Shift value for DMA_CH9PRIS */
<> 150:02e0a0aed4ec 1380 #define _DMA_CHPRIS_CH9PRIS_MASK 0x200UL /**< Bit mask for DMA_CH9PRIS */
<> 150:02e0a0aed4ec 1381 #define _DMA_CHPRIS_CH9PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
<> 150:02e0a0aed4ec 1382 #define DMA_CHPRIS_CH9PRIS_DEFAULT (_DMA_CHPRIS_CH9PRIS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHPRIS */
<> 150:02e0a0aed4ec 1383 #define DMA_CHPRIS_CH10PRIS (0x1UL << 10) /**< Channel 10 High Priority Set */
<> 150:02e0a0aed4ec 1384 #define _DMA_CHPRIS_CH10PRIS_SHIFT 10 /**< Shift value for DMA_CH10PRIS */
<> 150:02e0a0aed4ec 1385 #define _DMA_CHPRIS_CH10PRIS_MASK 0x400UL /**< Bit mask for DMA_CH10PRIS */
<> 150:02e0a0aed4ec 1386 #define _DMA_CHPRIS_CH10PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
<> 150:02e0a0aed4ec 1387 #define DMA_CHPRIS_CH10PRIS_DEFAULT (_DMA_CHPRIS_CH10PRIS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHPRIS */
<> 150:02e0a0aed4ec 1388 #define DMA_CHPRIS_CH11PRIS (0x1UL << 11) /**< Channel 11 High Priority Set */
<> 150:02e0a0aed4ec 1389 #define _DMA_CHPRIS_CH11PRIS_SHIFT 11 /**< Shift value for DMA_CH11PRIS */
<> 150:02e0a0aed4ec 1390 #define _DMA_CHPRIS_CH11PRIS_MASK 0x800UL /**< Bit mask for DMA_CH11PRIS */
<> 150:02e0a0aed4ec 1391 #define _DMA_CHPRIS_CH11PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
<> 150:02e0a0aed4ec 1392 #define DMA_CHPRIS_CH11PRIS_DEFAULT (_DMA_CHPRIS_CH11PRIS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHPRIS */
<> 150:02e0a0aed4ec 1393
<> 150:02e0a0aed4ec 1394 /* Bit fields for DMA CHPRIC */
<> 150:02e0a0aed4ec 1395 #define _DMA_CHPRIC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHPRIC */
<> 150:02e0a0aed4ec 1396 #define _DMA_CHPRIC_MASK 0x00000FFFUL /**< Mask for DMA_CHPRIC */
<> 150:02e0a0aed4ec 1397 #define DMA_CHPRIC_CH0PRIC (0x1UL << 0) /**< Channel 0 High Priority Clear */
<> 150:02e0a0aed4ec 1398 #define _DMA_CHPRIC_CH0PRIC_SHIFT 0 /**< Shift value for DMA_CH0PRIC */
<> 150:02e0a0aed4ec 1399 #define _DMA_CHPRIC_CH0PRIC_MASK 0x1UL /**< Bit mask for DMA_CH0PRIC */
<> 150:02e0a0aed4ec 1400 #define _DMA_CHPRIC_CH0PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
<> 150:02e0a0aed4ec 1401 #define DMA_CHPRIC_CH0PRIC_DEFAULT (_DMA_CHPRIC_CH0PRIC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHPRIC */
<> 150:02e0a0aed4ec 1402 #define DMA_CHPRIC_CH1PRIC (0x1UL << 1) /**< Channel 1 High Priority Clear */
<> 150:02e0a0aed4ec 1403 #define _DMA_CHPRIC_CH1PRIC_SHIFT 1 /**< Shift value for DMA_CH1PRIC */
<> 150:02e0a0aed4ec 1404 #define _DMA_CHPRIC_CH1PRIC_MASK 0x2UL /**< Bit mask for DMA_CH1PRIC */
<> 150:02e0a0aed4ec 1405 #define _DMA_CHPRIC_CH1PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
<> 150:02e0a0aed4ec 1406 #define DMA_CHPRIC_CH1PRIC_DEFAULT (_DMA_CHPRIC_CH1PRIC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHPRIC */
<> 150:02e0a0aed4ec 1407 #define DMA_CHPRIC_CH2PRIC (0x1UL << 2) /**< Channel 2 High Priority Clear */
<> 150:02e0a0aed4ec 1408 #define _DMA_CHPRIC_CH2PRIC_SHIFT 2 /**< Shift value for DMA_CH2PRIC */
<> 150:02e0a0aed4ec 1409 #define _DMA_CHPRIC_CH2PRIC_MASK 0x4UL /**< Bit mask for DMA_CH2PRIC */
<> 150:02e0a0aed4ec 1410 #define _DMA_CHPRIC_CH2PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
<> 150:02e0a0aed4ec 1411 #define DMA_CHPRIC_CH2PRIC_DEFAULT (_DMA_CHPRIC_CH2PRIC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHPRIC */
<> 150:02e0a0aed4ec 1412 #define DMA_CHPRIC_CH3PRIC (0x1UL << 3) /**< Channel 3 High Priority Clear */
<> 150:02e0a0aed4ec 1413 #define _DMA_CHPRIC_CH3PRIC_SHIFT 3 /**< Shift value for DMA_CH3PRIC */
<> 150:02e0a0aed4ec 1414 #define _DMA_CHPRIC_CH3PRIC_MASK 0x8UL /**< Bit mask for DMA_CH3PRIC */
<> 150:02e0a0aed4ec 1415 #define _DMA_CHPRIC_CH3PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
<> 150:02e0a0aed4ec 1416 #define DMA_CHPRIC_CH3PRIC_DEFAULT (_DMA_CHPRIC_CH3PRIC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHPRIC */
<> 150:02e0a0aed4ec 1417 #define DMA_CHPRIC_CH4PRIC (0x1UL << 4) /**< Channel 4 High Priority Clear */
<> 150:02e0a0aed4ec 1418 #define _DMA_CHPRIC_CH4PRIC_SHIFT 4 /**< Shift value for DMA_CH4PRIC */
<> 150:02e0a0aed4ec 1419 #define _DMA_CHPRIC_CH4PRIC_MASK 0x10UL /**< Bit mask for DMA_CH4PRIC */
<> 150:02e0a0aed4ec 1420 #define _DMA_CHPRIC_CH4PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
<> 150:02e0a0aed4ec 1421 #define DMA_CHPRIC_CH4PRIC_DEFAULT (_DMA_CHPRIC_CH4PRIC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHPRIC */
<> 150:02e0a0aed4ec 1422 #define DMA_CHPRIC_CH5PRIC (0x1UL << 5) /**< Channel 5 High Priority Clear */
<> 150:02e0a0aed4ec 1423 #define _DMA_CHPRIC_CH5PRIC_SHIFT 5 /**< Shift value for DMA_CH5PRIC */
<> 150:02e0a0aed4ec 1424 #define _DMA_CHPRIC_CH5PRIC_MASK 0x20UL /**< Bit mask for DMA_CH5PRIC */
<> 150:02e0a0aed4ec 1425 #define _DMA_CHPRIC_CH5PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
<> 150:02e0a0aed4ec 1426 #define DMA_CHPRIC_CH5PRIC_DEFAULT (_DMA_CHPRIC_CH5PRIC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHPRIC */
<> 150:02e0a0aed4ec 1427 #define DMA_CHPRIC_CH6PRIC (0x1UL << 6) /**< Channel 6 High Priority Clear */
<> 150:02e0a0aed4ec 1428 #define _DMA_CHPRIC_CH6PRIC_SHIFT 6 /**< Shift value for DMA_CH6PRIC */
<> 150:02e0a0aed4ec 1429 #define _DMA_CHPRIC_CH6PRIC_MASK 0x40UL /**< Bit mask for DMA_CH6PRIC */
<> 150:02e0a0aed4ec 1430 #define _DMA_CHPRIC_CH6PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
<> 150:02e0a0aed4ec 1431 #define DMA_CHPRIC_CH6PRIC_DEFAULT (_DMA_CHPRIC_CH6PRIC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHPRIC */
<> 150:02e0a0aed4ec 1432 #define DMA_CHPRIC_CH7PRIC (0x1UL << 7) /**< Channel 7 High Priority Clear */
<> 150:02e0a0aed4ec 1433 #define _DMA_CHPRIC_CH7PRIC_SHIFT 7 /**< Shift value for DMA_CH7PRIC */
<> 150:02e0a0aed4ec 1434 #define _DMA_CHPRIC_CH7PRIC_MASK 0x80UL /**< Bit mask for DMA_CH7PRIC */
<> 150:02e0a0aed4ec 1435 #define _DMA_CHPRIC_CH7PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
<> 150:02e0a0aed4ec 1436 #define DMA_CHPRIC_CH7PRIC_DEFAULT (_DMA_CHPRIC_CH7PRIC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHPRIC */
<> 150:02e0a0aed4ec 1437 #define DMA_CHPRIC_CH8PRIC (0x1UL << 8) /**< Channel 8 High Priority Clear */
<> 150:02e0a0aed4ec 1438 #define _DMA_CHPRIC_CH8PRIC_SHIFT 8 /**< Shift value for DMA_CH8PRIC */
<> 150:02e0a0aed4ec 1439 #define _DMA_CHPRIC_CH8PRIC_MASK 0x100UL /**< Bit mask for DMA_CH8PRIC */
<> 150:02e0a0aed4ec 1440 #define _DMA_CHPRIC_CH8PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
<> 150:02e0a0aed4ec 1441 #define DMA_CHPRIC_CH8PRIC_DEFAULT (_DMA_CHPRIC_CH8PRIC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHPRIC */
<> 150:02e0a0aed4ec 1442 #define DMA_CHPRIC_CH9PRIC (0x1UL << 9) /**< Channel 9 High Priority Clear */
<> 150:02e0a0aed4ec 1443 #define _DMA_CHPRIC_CH9PRIC_SHIFT 9 /**< Shift value for DMA_CH9PRIC */
<> 150:02e0a0aed4ec 1444 #define _DMA_CHPRIC_CH9PRIC_MASK 0x200UL /**< Bit mask for DMA_CH9PRIC */
<> 150:02e0a0aed4ec 1445 #define _DMA_CHPRIC_CH9PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
<> 150:02e0a0aed4ec 1446 #define DMA_CHPRIC_CH9PRIC_DEFAULT (_DMA_CHPRIC_CH9PRIC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHPRIC */
<> 150:02e0a0aed4ec 1447 #define DMA_CHPRIC_CH10PRIC (0x1UL << 10) /**< Channel 10 High Priority Clear */
<> 150:02e0a0aed4ec 1448 #define _DMA_CHPRIC_CH10PRIC_SHIFT 10 /**< Shift value for DMA_CH10PRIC */
<> 150:02e0a0aed4ec 1449 #define _DMA_CHPRIC_CH10PRIC_MASK 0x400UL /**< Bit mask for DMA_CH10PRIC */
<> 150:02e0a0aed4ec 1450 #define _DMA_CHPRIC_CH10PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
<> 150:02e0a0aed4ec 1451 #define DMA_CHPRIC_CH10PRIC_DEFAULT (_DMA_CHPRIC_CH10PRIC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHPRIC */
<> 150:02e0a0aed4ec 1452 #define DMA_CHPRIC_CH11PRIC (0x1UL << 11) /**< Channel 11 High Priority Clear */
<> 150:02e0a0aed4ec 1453 #define _DMA_CHPRIC_CH11PRIC_SHIFT 11 /**< Shift value for DMA_CH11PRIC */
<> 150:02e0a0aed4ec 1454 #define _DMA_CHPRIC_CH11PRIC_MASK 0x800UL /**< Bit mask for DMA_CH11PRIC */
<> 150:02e0a0aed4ec 1455 #define _DMA_CHPRIC_CH11PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
<> 150:02e0a0aed4ec 1456 #define DMA_CHPRIC_CH11PRIC_DEFAULT (_DMA_CHPRIC_CH11PRIC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHPRIC */
<> 150:02e0a0aed4ec 1457
<> 150:02e0a0aed4ec 1458 /* Bit fields for DMA ERRORC */
<> 150:02e0a0aed4ec 1459 #define _DMA_ERRORC_RESETVALUE 0x00000000UL /**< Default value for DMA_ERRORC */
<> 150:02e0a0aed4ec 1460 #define _DMA_ERRORC_MASK 0x00000001UL /**< Mask for DMA_ERRORC */
<> 150:02e0a0aed4ec 1461 #define DMA_ERRORC_ERRORC (0x1UL << 0) /**< Bus Error Clear */
<> 150:02e0a0aed4ec 1462 #define _DMA_ERRORC_ERRORC_SHIFT 0 /**< Shift value for DMA_ERRORC */
<> 150:02e0a0aed4ec 1463 #define _DMA_ERRORC_ERRORC_MASK 0x1UL /**< Bit mask for DMA_ERRORC */
<> 150:02e0a0aed4ec 1464 #define _DMA_ERRORC_ERRORC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_ERRORC */
<> 150:02e0a0aed4ec 1465 #define DMA_ERRORC_ERRORC_DEFAULT (_DMA_ERRORC_ERRORC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_ERRORC */
<> 150:02e0a0aed4ec 1466
<> 150:02e0a0aed4ec 1467 /* Bit fields for DMA CHREQSTATUS */
<> 150:02e0a0aed4ec 1468 #define _DMA_CHREQSTATUS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQSTATUS */
<> 150:02e0a0aed4ec 1469 #define _DMA_CHREQSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHREQSTATUS */
<> 150:02e0a0aed4ec 1470 #define DMA_CHREQSTATUS_CH0REQSTATUS (0x1UL << 0) /**< Channel 0 Request Status */
<> 150:02e0a0aed4ec 1471 #define _DMA_CHREQSTATUS_CH0REQSTATUS_SHIFT 0 /**< Shift value for DMA_CH0REQSTATUS */
<> 150:02e0a0aed4ec 1472 #define _DMA_CHREQSTATUS_CH0REQSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0REQSTATUS */
<> 150:02e0a0aed4ec 1473 #define _DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
<> 150:02e0a0aed4ec 1474 #define DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
<> 150:02e0a0aed4ec 1475 #define DMA_CHREQSTATUS_CH1REQSTATUS (0x1UL << 1) /**< Channel 1 Request Status */
<> 150:02e0a0aed4ec 1476 #define _DMA_CHREQSTATUS_CH1REQSTATUS_SHIFT 1 /**< Shift value for DMA_CH1REQSTATUS */
<> 150:02e0a0aed4ec 1477 #define _DMA_CHREQSTATUS_CH1REQSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1REQSTATUS */
<> 150:02e0a0aed4ec 1478 #define _DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
<> 150:02e0a0aed4ec 1479 #define DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
<> 150:02e0a0aed4ec 1480 #define DMA_CHREQSTATUS_CH2REQSTATUS (0x1UL << 2) /**< Channel 2 Request Status */
<> 150:02e0a0aed4ec 1481 #define _DMA_CHREQSTATUS_CH2REQSTATUS_SHIFT 2 /**< Shift value for DMA_CH2REQSTATUS */
<> 150:02e0a0aed4ec 1482 #define _DMA_CHREQSTATUS_CH2REQSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2REQSTATUS */
<> 150:02e0a0aed4ec 1483 #define _DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
<> 150:02e0a0aed4ec 1484 #define DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
<> 150:02e0a0aed4ec 1485 #define DMA_CHREQSTATUS_CH3REQSTATUS (0x1UL << 3) /**< Channel 3 Request Status */
<> 150:02e0a0aed4ec 1486 #define _DMA_CHREQSTATUS_CH3REQSTATUS_SHIFT 3 /**< Shift value for DMA_CH3REQSTATUS */
<> 150:02e0a0aed4ec 1487 #define _DMA_CHREQSTATUS_CH3REQSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3REQSTATUS */
<> 150:02e0a0aed4ec 1488 #define _DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
<> 150:02e0a0aed4ec 1489 #define DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
<> 150:02e0a0aed4ec 1490 #define DMA_CHREQSTATUS_CH4REQSTATUS (0x1UL << 4) /**< Channel 4 Request Status */
<> 150:02e0a0aed4ec 1491 #define _DMA_CHREQSTATUS_CH4REQSTATUS_SHIFT 4 /**< Shift value for DMA_CH4REQSTATUS */
<> 150:02e0a0aed4ec 1492 #define _DMA_CHREQSTATUS_CH4REQSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4REQSTATUS */
<> 150:02e0a0aed4ec 1493 #define _DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
<> 150:02e0a0aed4ec 1494 #define DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
<> 150:02e0a0aed4ec 1495 #define DMA_CHREQSTATUS_CH5REQSTATUS (0x1UL << 5) /**< Channel 5 Request Status */
<> 150:02e0a0aed4ec 1496 #define _DMA_CHREQSTATUS_CH5REQSTATUS_SHIFT 5 /**< Shift value for DMA_CH5REQSTATUS */
<> 150:02e0a0aed4ec 1497 #define _DMA_CHREQSTATUS_CH5REQSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5REQSTATUS */
<> 150:02e0a0aed4ec 1498 #define _DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
<> 150:02e0a0aed4ec 1499 #define DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
<> 150:02e0a0aed4ec 1500 #define DMA_CHREQSTATUS_CH6REQSTATUS (0x1UL << 6) /**< Channel 6 Request Status */
<> 150:02e0a0aed4ec 1501 #define _DMA_CHREQSTATUS_CH6REQSTATUS_SHIFT 6 /**< Shift value for DMA_CH6REQSTATUS */
<> 150:02e0a0aed4ec 1502 #define _DMA_CHREQSTATUS_CH6REQSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6REQSTATUS */
<> 150:02e0a0aed4ec 1503 #define _DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
<> 150:02e0a0aed4ec 1504 #define DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
<> 150:02e0a0aed4ec 1505 #define DMA_CHREQSTATUS_CH7REQSTATUS (0x1UL << 7) /**< Channel 7 Request Status */
<> 150:02e0a0aed4ec 1506 #define _DMA_CHREQSTATUS_CH7REQSTATUS_SHIFT 7 /**< Shift value for DMA_CH7REQSTATUS */
<> 150:02e0a0aed4ec 1507 #define _DMA_CHREQSTATUS_CH7REQSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7REQSTATUS */
<> 150:02e0a0aed4ec 1508 #define _DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
<> 150:02e0a0aed4ec 1509 #define DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
<> 150:02e0a0aed4ec 1510 #define DMA_CHREQSTATUS_CH8REQSTATUS (0x1UL << 8) /**< Channel 8 Request Status */
<> 150:02e0a0aed4ec 1511 #define _DMA_CHREQSTATUS_CH8REQSTATUS_SHIFT 8 /**< Shift value for DMA_CH8REQSTATUS */
<> 150:02e0a0aed4ec 1512 #define _DMA_CHREQSTATUS_CH8REQSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8REQSTATUS */
<> 150:02e0a0aed4ec 1513 #define _DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
<> 150:02e0a0aed4ec 1514 #define DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
<> 150:02e0a0aed4ec 1515 #define DMA_CHREQSTATUS_CH9REQSTATUS (0x1UL << 9) /**< Channel 9 Request Status */
<> 150:02e0a0aed4ec 1516 #define _DMA_CHREQSTATUS_CH9REQSTATUS_SHIFT 9 /**< Shift value for DMA_CH9REQSTATUS */
<> 150:02e0a0aed4ec 1517 #define _DMA_CHREQSTATUS_CH9REQSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9REQSTATUS */
<> 150:02e0a0aed4ec 1518 #define _DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
<> 150:02e0a0aed4ec 1519 #define DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
<> 150:02e0a0aed4ec 1520 #define DMA_CHREQSTATUS_CH10REQSTATUS (0x1UL << 10) /**< Channel 10 Request Status */
<> 150:02e0a0aed4ec 1521 #define _DMA_CHREQSTATUS_CH10REQSTATUS_SHIFT 10 /**< Shift value for DMA_CH10REQSTATUS */
<> 150:02e0a0aed4ec 1522 #define _DMA_CHREQSTATUS_CH10REQSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10REQSTATUS */
<> 150:02e0a0aed4ec 1523 #define _DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
<> 150:02e0a0aed4ec 1524 #define DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
<> 150:02e0a0aed4ec 1525 #define DMA_CHREQSTATUS_CH11REQSTATUS (0x1UL << 11) /**< Channel 11 Request Status */
<> 150:02e0a0aed4ec 1526 #define _DMA_CHREQSTATUS_CH11REQSTATUS_SHIFT 11 /**< Shift value for DMA_CH11REQSTATUS */
<> 150:02e0a0aed4ec 1527 #define _DMA_CHREQSTATUS_CH11REQSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11REQSTATUS */
<> 150:02e0a0aed4ec 1528 #define _DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
<> 150:02e0a0aed4ec 1529 #define DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
<> 150:02e0a0aed4ec 1530
<> 150:02e0a0aed4ec 1531 /* Bit fields for DMA CHSREQSTATUS */
<> 150:02e0a0aed4ec 1532 #define _DMA_CHSREQSTATUS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHSREQSTATUS */
<> 150:02e0a0aed4ec 1533 #define _DMA_CHSREQSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHSREQSTATUS */
<> 150:02e0a0aed4ec 1534 #define DMA_CHSREQSTATUS_CH0SREQSTATUS (0x1UL << 0) /**< Channel 0 Single Request Status */
<> 150:02e0a0aed4ec 1535 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_SHIFT 0 /**< Shift value for DMA_CH0SREQSTATUS */
<> 150:02e0a0aed4ec 1536 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0SREQSTATUS */
<> 150:02e0a0aed4ec 1537 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
<> 150:02e0a0aed4ec 1538 #define DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
<> 150:02e0a0aed4ec 1539 #define DMA_CHSREQSTATUS_CH1SREQSTATUS (0x1UL << 1) /**< Channel 1 Single Request Status */
<> 150:02e0a0aed4ec 1540 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_SHIFT 1 /**< Shift value for DMA_CH1SREQSTATUS */
<> 150:02e0a0aed4ec 1541 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1SREQSTATUS */
<> 150:02e0a0aed4ec 1542 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
<> 150:02e0a0aed4ec 1543 #define DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
<> 150:02e0a0aed4ec 1544 #define DMA_CHSREQSTATUS_CH2SREQSTATUS (0x1UL << 2) /**< Channel 2 Single Request Status */
<> 150:02e0a0aed4ec 1545 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_SHIFT 2 /**< Shift value for DMA_CH2SREQSTATUS */
<> 150:02e0a0aed4ec 1546 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2SREQSTATUS */
<> 150:02e0a0aed4ec 1547 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
<> 150:02e0a0aed4ec 1548 #define DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
<> 150:02e0a0aed4ec 1549 #define DMA_CHSREQSTATUS_CH3SREQSTATUS (0x1UL << 3) /**< Channel 3 Single Request Status */
<> 150:02e0a0aed4ec 1550 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_SHIFT 3 /**< Shift value for DMA_CH3SREQSTATUS */
<> 150:02e0a0aed4ec 1551 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3SREQSTATUS */
<> 150:02e0a0aed4ec 1552 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
<> 150:02e0a0aed4ec 1553 #define DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
<> 150:02e0a0aed4ec 1554 #define DMA_CHSREQSTATUS_CH4SREQSTATUS (0x1UL << 4) /**< Channel 4 Single Request Status */
<> 150:02e0a0aed4ec 1555 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_SHIFT 4 /**< Shift value for DMA_CH4SREQSTATUS */
<> 150:02e0a0aed4ec 1556 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4SREQSTATUS */
<> 150:02e0a0aed4ec 1557 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
<> 150:02e0a0aed4ec 1558 #define DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
<> 150:02e0a0aed4ec 1559 #define DMA_CHSREQSTATUS_CH5SREQSTATUS (0x1UL << 5) /**< Channel 5 Single Request Status */
<> 150:02e0a0aed4ec 1560 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_SHIFT 5 /**< Shift value for DMA_CH5SREQSTATUS */
<> 150:02e0a0aed4ec 1561 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5SREQSTATUS */
<> 150:02e0a0aed4ec 1562 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
<> 150:02e0a0aed4ec 1563 #define DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
<> 150:02e0a0aed4ec 1564 #define DMA_CHSREQSTATUS_CH6SREQSTATUS (0x1UL << 6) /**< Channel 6 Single Request Status */
<> 150:02e0a0aed4ec 1565 #define _DMA_CHSREQSTATUS_CH6SREQSTATUS_SHIFT 6 /**< Shift value for DMA_CH6SREQSTATUS */
<> 150:02e0a0aed4ec 1566 #define _DMA_CHSREQSTATUS_CH6SREQSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6SREQSTATUS */
<> 150:02e0a0aed4ec 1567 #define _DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
<> 150:02e0a0aed4ec 1568 #define DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
<> 150:02e0a0aed4ec 1569 #define DMA_CHSREQSTATUS_CH7SREQSTATUS (0x1UL << 7) /**< Channel 7 Single Request Status */
<> 150:02e0a0aed4ec 1570 #define _DMA_CHSREQSTATUS_CH7SREQSTATUS_SHIFT 7 /**< Shift value for DMA_CH7SREQSTATUS */
<> 150:02e0a0aed4ec 1571 #define _DMA_CHSREQSTATUS_CH7SREQSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7SREQSTATUS */
<> 150:02e0a0aed4ec 1572 #define _DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
<> 150:02e0a0aed4ec 1573 #define DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
<> 150:02e0a0aed4ec 1574 #define DMA_CHSREQSTATUS_CH8SREQSTATUS (0x1UL << 8) /**< Channel 8 Single Request Status */
<> 150:02e0a0aed4ec 1575 #define _DMA_CHSREQSTATUS_CH8SREQSTATUS_SHIFT 8 /**< Shift value for DMA_CH8SREQSTATUS */
<> 150:02e0a0aed4ec 1576 #define _DMA_CHSREQSTATUS_CH8SREQSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8SREQSTATUS */
<> 150:02e0a0aed4ec 1577 #define _DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
<> 150:02e0a0aed4ec 1578 #define DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
<> 150:02e0a0aed4ec 1579 #define DMA_CHSREQSTATUS_CH9SREQSTATUS (0x1UL << 9) /**< Channel 9 Single Request Status */
<> 150:02e0a0aed4ec 1580 #define _DMA_CHSREQSTATUS_CH9SREQSTATUS_SHIFT 9 /**< Shift value for DMA_CH9SREQSTATUS */
<> 150:02e0a0aed4ec 1581 #define _DMA_CHSREQSTATUS_CH9SREQSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9SREQSTATUS */
<> 150:02e0a0aed4ec 1582 #define _DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
<> 150:02e0a0aed4ec 1583 #define DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
<> 150:02e0a0aed4ec 1584 #define DMA_CHSREQSTATUS_CH10SREQSTATUS (0x1UL << 10) /**< Channel 10 Single Request Status */
<> 150:02e0a0aed4ec 1585 #define _DMA_CHSREQSTATUS_CH10SREQSTATUS_SHIFT 10 /**< Shift value for DMA_CH10SREQSTATUS */
<> 150:02e0a0aed4ec 1586 #define _DMA_CHSREQSTATUS_CH10SREQSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10SREQSTATUS */
<> 150:02e0a0aed4ec 1587 #define _DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
<> 150:02e0a0aed4ec 1588 #define DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
<> 150:02e0a0aed4ec 1589 #define DMA_CHSREQSTATUS_CH11SREQSTATUS (0x1UL << 11) /**< Channel 11 Single Request Status */
<> 150:02e0a0aed4ec 1590 #define _DMA_CHSREQSTATUS_CH11SREQSTATUS_SHIFT 11 /**< Shift value for DMA_CH11SREQSTATUS */
<> 150:02e0a0aed4ec 1591 #define _DMA_CHSREQSTATUS_CH11SREQSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11SREQSTATUS */
<> 150:02e0a0aed4ec 1592 #define _DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
<> 150:02e0a0aed4ec 1593 #define DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
<> 150:02e0a0aed4ec 1594
<> 150:02e0a0aed4ec 1595 /* Bit fields for DMA IF */
<> 150:02e0a0aed4ec 1596 #define _DMA_IF_RESETVALUE 0x00000000UL /**< Default value for DMA_IF */
<> 150:02e0a0aed4ec 1597 #define _DMA_IF_MASK 0x80000FFFUL /**< Mask for DMA_IF */
<> 150:02e0a0aed4ec 1598 #define DMA_IF_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag */
<> 150:02e0a0aed4ec 1599 #define _DMA_IF_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */
<> 150:02e0a0aed4ec 1600 #define _DMA_IF_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */
<> 150:02e0a0aed4ec 1601 #define _DMA_IF_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
<> 150:02e0a0aed4ec 1602 #define DMA_IF_CH0DONE_DEFAULT (_DMA_IF_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IF */
<> 150:02e0a0aed4ec 1603 #define DMA_IF_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag */
<> 150:02e0a0aed4ec 1604 #define _DMA_IF_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */
<> 150:02e0a0aed4ec 1605 #define _DMA_IF_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */
<> 150:02e0a0aed4ec 1606 #define _DMA_IF_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
<> 150:02e0a0aed4ec 1607 #define DMA_IF_CH1DONE_DEFAULT (_DMA_IF_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IF */
<> 150:02e0a0aed4ec 1608 #define DMA_IF_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag */
<> 150:02e0a0aed4ec 1609 #define _DMA_IF_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */
<> 150:02e0a0aed4ec 1610 #define _DMA_IF_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */
<> 150:02e0a0aed4ec 1611 #define _DMA_IF_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
<> 150:02e0a0aed4ec 1612 #define DMA_IF_CH2DONE_DEFAULT (_DMA_IF_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IF */
<> 150:02e0a0aed4ec 1613 #define DMA_IF_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag */
<> 150:02e0a0aed4ec 1614 #define _DMA_IF_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */
<> 150:02e0a0aed4ec 1615 #define _DMA_IF_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */
<> 150:02e0a0aed4ec 1616 #define _DMA_IF_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
<> 150:02e0a0aed4ec 1617 #define DMA_IF_CH3DONE_DEFAULT (_DMA_IF_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IF */
<> 150:02e0a0aed4ec 1618 #define DMA_IF_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag */
<> 150:02e0a0aed4ec 1619 #define _DMA_IF_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */
<> 150:02e0a0aed4ec 1620 #define _DMA_IF_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */
<> 150:02e0a0aed4ec 1621 #define _DMA_IF_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
<> 150:02e0a0aed4ec 1622 #define DMA_IF_CH4DONE_DEFAULT (_DMA_IF_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IF */
<> 150:02e0a0aed4ec 1623 #define DMA_IF_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag */
<> 150:02e0a0aed4ec 1624 #define _DMA_IF_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */
<> 150:02e0a0aed4ec 1625 #define _DMA_IF_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */
<> 150:02e0a0aed4ec 1626 #define _DMA_IF_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
<> 150:02e0a0aed4ec 1627 #define DMA_IF_CH5DONE_DEFAULT (_DMA_IF_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IF */
<> 150:02e0a0aed4ec 1628 #define DMA_IF_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag */
<> 150:02e0a0aed4ec 1629 #define _DMA_IF_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */
<> 150:02e0a0aed4ec 1630 #define _DMA_IF_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */
<> 150:02e0a0aed4ec 1631 #define _DMA_IF_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
<> 150:02e0a0aed4ec 1632 #define DMA_IF_CH6DONE_DEFAULT (_DMA_IF_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IF */
<> 150:02e0a0aed4ec 1633 #define DMA_IF_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag */
<> 150:02e0a0aed4ec 1634 #define _DMA_IF_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */
<> 150:02e0a0aed4ec 1635 #define _DMA_IF_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */
<> 150:02e0a0aed4ec 1636 #define _DMA_IF_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
<> 150:02e0a0aed4ec 1637 #define DMA_IF_CH7DONE_DEFAULT (_DMA_IF_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IF */
<> 150:02e0a0aed4ec 1638 #define DMA_IF_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag */
<> 150:02e0a0aed4ec 1639 #define _DMA_IF_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */
<> 150:02e0a0aed4ec 1640 #define _DMA_IF_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */
<> 150:02e0a0aed4ec 1641 #define _DMA_IF_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
<> 150:02e0a0aed4ec 1642 #define DMA_IF_CH8DONE_DEFAULT (_DMA_IF_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IF */
<> 150:02e0a0aed4ec 1643 #define DMA_IF_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag */
<> 150:02e0a0aed4ec 1644 #define _DMA_IF_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */
<> 150:02e0a0aed4ec 1645 #define _DMA_IF_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */
<> 150:02e0a0aed4ec 1646 #define _DMA_IF_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
<> 150:02e0a0aed4ec 1647 #define DMA_IF_CH9DONE_DEFAULT (_DMA_IF_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IF */
<> 150:02e0a0aed4ec 1648 #define DMA_IF_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag */
<> 150:02e0a0aed4ec 1649 #define _DMA_IF_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */
<> 150:02e0a0aed4ec 1650 #define _DMA_IF_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */
<> 150:02e0a0aed4ec 1651 #define _DMA_IF_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
<> 150:02e0a0aed4ec 1652 #define DMA_IF_CH10DONE_DEFAULT (_DMA_IF_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IF */
<> 150:02e0a0aed4ec 1653 #define DMA_IF_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag */
<> 150:02e0a0aed4ec 1654 #define _DMA_IF_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */
<> 150:02e0a0aed4ec 1655 #define _DMA_IF_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */
<> 150:02e0a0aed4ec 1656 #define _DMA_IF_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
<> 150:02e0a0aed4ec 1657 #define DMA_IF_CH11DONE_DEFAULT (_DMA_IF_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IF */
<> 150:02e0a0aed4ec 1658 #define DMA_IF_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag */
<> 150:02e0a0aed4ec 1659 #define _DMA_IF_ERR_SHIFT 31 /**< Shift value for DMA_ERR */
<> 150:02e0a0aed4ec 1660 #define _DMA_IF_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */
<> 150:02e0a0aed4ec 1661 #define _DMA_IF_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
<> 150:02e0a0aed4ec 1662 #define DMA_IF_ERR_DEFAULT (_DMA_IF_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IF */
<> 150:02e0a0aed4ec 1663
<> 150:02e0a0aed4ec 1664 /* Bit fields for DMA IFS */
<> 150:02e0a0aed4ec 1665 #define _DMA_IFS_RESETVALUE 0x00000000UL /**< Default value for DMA_IFS */
<> 150:02e0a0aed4ec 1666 #define _DMA_IFS_MASK 0x80000FFFUL /**< Mask for DMA_IFS */
<> 150:02e0a0aed4ec 1667 #define DMA_IFS_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag Set */
<> 150:02e0a0aed4ec 1668 #define _DMA_IFS_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */
<> 150:02e0a0aed4ec 1669 #define _DMA_IFS_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */
<> 150:02e0a0aed4ec 1670 #define _DMA_IFS_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
<> 150:02e0a0aed4ec 1671 #define DMA_IFS_CH0DONE_DEFAULT (_DMA_IFS_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IFS */
<> 150:02e0a0aed4ec 1672 #define DMA_IFS_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag Set */
<> 150:02e0a0aed4ec 1673 #define _DMA_IFS_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */
<> 150:02e0a0aed4ec 1674 #define _DMA_IFS_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */
<> 150:02e0a0aed4ec 1675 #define _DMA_IFS_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
<> 150:02e0a0aed4ec 1676 #define DMA_IFS_CH1DONE_DEFAULT (_DMA_IFS_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IFS */
<> 150:02e0a0aed4ec 1677 #define DMA_IFS_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag Set */
<> 150:02e0a0aed4ec 1678 #define _DMA_IFS_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */
<> 150:02e0a0aed4ec 1679 #define _DMA_IFS_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */
<> 150:02e0a0aed4ec 1680 #define _DMA_IFS_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
<> 150:02e0a0aed4ec 1681 #define DMA_IFS_CH2DONE_DEFAULT (_DMA_IFS_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IFS */
<> 150:02e0a0aed4ec 1682 #define DMA_IFS_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag Set */
<> 150:02e0a0aed4ec 1683 #define _DMA_IFS_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */
<> 150:02e0a0aed4ec 1684 #define _DMA_IFS_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */
<> 150:02e0a0aed4ec 1685 #define _DMA_IFS_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
<> 150:02e0a0aed4ec 1686 #define DMA_IFS_CH3DONE_DEFAULT (_DMA_IFS_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IFS */
<> 150:02e0a0aed4ec 1687 #define DMA_IFS_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag Set */
<> 150:02e0a0aed4ec 1688 #define _DMA_IFS_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */
<> 150:02e0a0aed4ec 1689 #define _DMA_IFS_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */
<> 150:02e0a0aed4ec 1690 #define _DMA_IFS_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
<> 150:02e0a0aed4ec 1691 #define DMA_IFS_CH4DONE_DEFAULT (_DMA_IFS_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IFS */
<> 150:02e0a0aed4ec 1692 #define DMA_IFS_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag Set */
<> 150:02e0a0aed4ec 1693 #define _DMA_IFS_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */
<> 150:02e0a0aed4ec 1694 #define _DMA_IFS_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */
<> 150:02e0a0aed4ec 1695 #define _DMA_IFS_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
<> 150:02e0a0aed4ec 1696 #define DMA_IFS_CH5DONE_DEFAULT (_DMA_IFS_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IFS */
<> 150:02e0a0aed4ec 1697 #define DMA_IFS_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag Set */
<> 150:02e0a0aed4ec 1698 #define _DMA_IFS_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */
<> 150:02e0a0aed4ec 1699 #define _DMA_IFS_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */
<> 150:02e0a0aed4ec 1700 #define _DMA_IFS_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
<> 150:02e0a0aed4ec 1701 #define DMA_IFS_CH6DONE_DEFAULT (_DMA_IFS_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IFS */
<> 150:02e0a0aed4ec 1702 #define DMA_IFS_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag Set */
<> 150:02e0a0aed4ec 1703 #define _DMA_IFS_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */
<> 150:02e0a0aed4ec 1704 #define _DMA_IFS_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */
<> 150:02e0a0aed4ec 1705 #define _DMA_IFS_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
<> 150:02e0a0aed4ec 1706 #define DMA_IFS_CH7DONE_DEFAULT (_DMA_IFS_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IFS */
<> 150:02e0a0aed4ec 1707 #define DMA_IFS_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag Set */
<> 150:02e0a0aed4ec 1708 #define _DMA_IFS_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */
<> 150:02e0a0aed4ec 1709 #define _DMA_IFS_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */
<> 150:02e0a0aed4ec 1710 #define _DMA_IFS_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
<> 150:02e0a0aed4ec 1711 #define DMA_IFS_CH8DONE_DEFAULT (_DMA_IFS_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IFS */
<> 150:02e0a0aed4ec 1712 #define DMA_IFS_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag Set */
<> 150:02e0a0aed4ec 1713 #define _DMA_IFS_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */
<> 150:02e0a0aed4ec 1714 #define _DMA_IFS_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */
<> 150:02e0a0aed4ec 1715 #define _DMA_IFS_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
<> 150:02e0a0aed4ec 1716 #define DMA_IFS_CH9DONE_DEFAULT (_DMA_IFS_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IFS */
<> 150:02e0a0aed4ec 1717 #define DMA_IFS_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag Set */
<> 150:02e0a0aed4ec 1718 #define _DMA_IFS_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */
<> 150:02e0a0aed4ec 1719 #define _DMA_IFS_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */
<> 150:02e0a0aed4ec 1720 #define _DMA_IFS_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
<> 150:02e0a0aed4ec 1721 #define DMA_IFS_CH10DONE_DEFAULT (_DMA_IFS_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IFS */
<> 150:02e0a0aed4ec 1722 #define DMA_IFS_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag Set */
<> 150:02e0a0aed4ec 1723 #define _DMA_IFS_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */
<> 150:02e0a0aed4ec 1724 #define _DMA_IFS_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */
<> 150:02e0a0aed4ec 1725 #define _DMA_IFS_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
<> 150:02e0a0aed4ec 1726 #define DMA_IFS_CH11DONE_DEFAULT (_DMA_IFS_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IFS */
<> 150:02e0a0aed4ec 1727 #define DMA_IFS_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Set */
<> 150:02e0a0aed4ec 1728 #define _DMA_IFS_ERR_SHIFT 31 /**< Shift value for DMA_ERR */
<> 150:02e0a0aed4ec 1729 #define _DMA_IFS_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */
<> 150:02e0a0aed4ec 1730 #define _DMA_IFS_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
<> 150:02e0a0aed4ec 1731 #define DMA_IFS_ERR_DEFAULT (_DMA_IFS_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IFS */
<> 150:02e0a0aed4ec 1732
<> 150:02e0a0aed4ec 1733 /* Bit fields for DMA IFC */
<> 150:02e0a0aed4ec 1734 #define _DMA_IFC_RESETVALUE 0x00000000UL /**< Default value for DMA_IFC */
<> 150:02e0a0aed4ec 1735 #define _DMA_IFC_MASK 0x80000FFFUL /**< Mask for DMA_IFC */
<> 150:02e0a0aed4ec 1736 #define DMA_IFC_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag Clear */
<> 150:02e0a0aed4ec 1737 #define _DMA_IFC_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */
<> 150:02e0a0aed4ec 1738 #define _DMA_IFC_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */
<> 150:02e0a0aed4ec 1739 #define _DMA_IFC_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
<> 150:02e0a0aed4ec 1740 #define DMA_IFC_CH0DONE_DEFAULT (_DMA_IFC_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IFC */
<> 150:02e0a0aed4ec 1741 #define DMA_IFC_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag Clear */
<> 150:02e0a0aed4ec 1742 #define _DMA_IFC_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */
<> 150:02e0a0aed4ec 1743 #define _DMA_IFC_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */
<> 150:02e0a0aed4ec 1744 #define _DMA_IFC_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
<> 150:02e0a0aed4ec 1745 #define DMA_IFC_CH1DONE_DEFAULT (_DMA_IFC_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IFC */
<> 150:02e0a0aed4ec 1746 #define DMA_IFC_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag Clear */
<> 150:02e0a0aed4ec 1747 #define _DMA_IFC_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */
<> 150:02e0a0aed4ec 1748 #define _DMA_IFC_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */
<> 150:02e0a0aed4ec 1749 #define _DMA_IFC_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
<> 150:02e0a0aed4ec 1750 #define DMA_IFC_CH2DONE_DEFAULT (_DMA_IFC_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IFC */
<> 150:02e0a0aed4ec 1751 #define DMA_IFC_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag Clear */
<> 150:02e0a0aed4ec 1752 #define _DMA_IFC_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */
<> 150:02e0a0aed4ec 1753 #define _DMA_IFC_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */
<> 150:02e0a0aed4ec 1754 #define _DMA_IFC_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
<> 150:02e0a0aed4ec 1755 #define DMA_IFC_CH3DONE_DEFAULT (_DMA_IFC_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IFC */
<> 150:02e0a0aed4ec 1756 #define DMA_IFC_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag Clear */
<> 150:02e0a0aed4ec 1757 #define _DMA_IFC_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */
<> 150:02e0a0aed4ec 1758 #define _DMA_IFC_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */
<> 150:02e0a0aed4ec 1759 #define _DMA_IFC_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
<> 150:02e0a0aed4ec 1760 #define DMA_IFC_CH4DONE_DEFAULT (_DMA_IFC_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IFC */
<> 150:02e0a0aed4ec 1761 #define DMA_IFC_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag Clear */
<> 150:02e0a0aed4ec 1762 #define _DMA_IFC_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */
<> 150:02e0a0aed4ec 1763 #define _DMA_IFC_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */
<> 150:02e0a0aed4ec 1764 #define _DMA_IFC_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
<> 150:02e0a0aed4ec 1765 #define DMA_IFC_CH5DONE_DEFAULT (_DMA_IFC_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IFC */
<> 150:02e0a0aed4ec 1766 #define DMA_IFC_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag Clear */
<> 150:02e0a0aed4ec 1767 #define _DMA_IFC_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */
<> 150:02e0a0aed4ec 1768 #define _DMA_IFC_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */
<> 150:02e0a0aed4ec 1769 #define _DMA_IFC_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
<> 150:02e0a0aed4ec 1770 #define DMA_IFC_CH6DONE_DEFAULT (_DMA_IFC_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IFC */
<> 150:02e0a0aed4ec 1771 #define DMA_IFC_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag Clear */
<> 150:02e0a0aed4ec 1772 #define _DMA_IFC_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */
<> 150:02e0a0aed4ec 1773 #define _DMA_IFC_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */
<> 150:02e0a0aed4ec 1774 #define _DMA_IFC_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
<> 150:02e0a0aed4ec 1775 #define DMA_IFC_CH7DONE_DEFAULT (_DMA_IFC_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IFC */
<> 150:02e0a0aed4ec 1776 #define DMA_IFC_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag Clear */
<> 150:02e0a0aed4ec 1777 #define _DMA_IFC_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */
<> 150:02e0a0aed4ec 1778 #define _DMA_IFC_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */
<> 150:02e0a0aed4ec 1779 #define _DMA_IFC_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
<> 150:02e0a0aed4ec 1780 #define DMA_IFC_CH8DONE_DEFAULT (_DMA_IFC_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IFC */
<> 150:02e0a0aed4ec 1781 #define DMA_IFC_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag Clear */
<> 150:02e0a0aed4ec 1782 #define _DMA_IFC_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */
<> 150:02e0a0aed4ec 1783 #define _DMA_IFC_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */
<> 150:02e0a0aed4ec 1784 #define _DMA_IFC_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
<> 150:02e0a0aed4ec 1785 #define DMA_IFC_CH9DONE_DEFAULT (_DMA_IFC_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IFC */
<> 150:02e0a0aed4ec 1786 #define DMA_IFC_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag Clear */
<> 150:02e0a0aed4ec 1787 #define _DMA_IFC_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */
<> 150:02e0a0aed4ec 1788 #define _DMA_IFC_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */
<> 150:02e0a0aed4ec 1789 #define _DMA_IFC_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
<> 150:02e0a0aed4ec 1790 #define DMA_IFC_CH10DONE_DEFAULT (_DMA_IFC_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IFC */
<> 150:02e0a0aed4ec 1791 #define DMA_IFC_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag Clear */
<> 150:02e0a0aed4ec 1792 #define _DMA_IFC_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */
<> 150:02e0a0aed4ec 1793 #define _DMA_IFC_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */
<> 150:02e0a0aed4ec 1794 #define _DMA_IFC_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
<> 150:02e0a0aed4ec 1795 #define DMA_IFC_CH11DONE_DEFAULT (_DMA_IFC_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IFC */
<> 150:02e0a0aed4ec 1796 #define DMA_IFC_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Clear */
<> 150:02e0a0aed4ec 1797 #define _DMA_IFC_ERR_SHIFT 31 /**< Shift value for DMA_ERR */
<> 150:02e0a0aed4ec 1798 #define _DMA_IFC_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */
<> 150:02e0a0aed4ec 1799 #define _DMA_IFC_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
<> 150:02e0a0aed4ec 1800 #define DMA_IFC_ERR_DEFAULT (_DMA_IFC_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IFC */
<> 150:02e0a0aed4ec 1801
<> 150:02e0a0aed4ec 1802 /* Bit fields for DMA IEN */
<> 150:02e0a0aed4ec 1803 #define _DMA_IEN_RESETVALUE 0x00000000UL /**< Default value for DMA_IEN */
<> 150:02e0a0aed4ec 1804 #define _DMA_IEN_MASK 0x80000FFFUL /**< Mask for DMA_IEN */
<> 150:02e0a0aed4ec 1805 #define DMA_IEN_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Enable */
<> 150:02e0a0aed4ec 1806 #define _DMA_IEN_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */
<> 150:02e0a0aed4ec 1807 #define _DMA_IEN_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */
<> 150:02e0a0aed4ec 1808 #define _DMA_IEN_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
<> 150:02e0a0aed4ec 1809 #define DMA_IEN_CH0DONE_DEFAULT (_DMA_IEN_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IEN */
<> 150:02e0a0aed4ec 1810 #define DMA_IEN_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Enable */
<> 150:02e0a0aed4ec 1811 #define _DMA_IEN_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */
<> 150:02e0a0aed4ec 1812 #define _DMA_IEN_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */
<> 150:02e0a0aed4ec 1813 #define _DMA_IEN_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
<> 150:02e0a0aed4ec 1814 #define DMA_IEN_CH1DONE_DEFAULT (_DMA_IEN_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IEN */
<> 150:02e0a0aed4ec 1815 #define DMA_IEN_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Enable */
<> 150:02e0a0aed4ec 1816 #define _DMA_IEN_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */
<> 150:02e0a0aed4ec 1817 #define _DMA_IEN_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */
<> 150:02e0a0aed4ec 1818 #define _DMA_IEN_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
<> 150:02e0a0aed4ec 1819 #define DMA_IEN_CH2DONE_DEFAULT (_DMA_IEN_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IEN */
<> 150:02e0a0aed4ec 1820 #define DMA_IEN_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Enable */
<> 150:02e0a0aed4ec 1821 #define _DMA_IEN_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */
<> 150:02e0a0aed4ec 1822 #define _DMA_IEN_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */
<> 150:02e0a0aed4ec 1823 #define _DMA_IEN_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
<> 150:02e0a0aed4ec 1824 #define DMA_IEN_CH3DONE_DEFAULT (_DMA_IEN_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IEN */
<> 150:02e0a0aed4ec 1825 #define DMA_IEN_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Enable */
<> 150:02e0a0aed4ec 1826 #define _DMA_IEN_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */
<> 150:02e0a0aed4ec 1827 #define _DMA_IEN_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */
<> 150:02e0a0aed4ec 1828 #define _DMA_IEN_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
<> 150:02e0a0aed4ec 1829 #define DMA_IEN_CH4DONE_DEFAULT (_DMA_IEN_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IEN */
<> 150:02e0a0aed4ec 1830 #define DMA_IEN_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Enable */
<> 150:02e0a0aed4ec 1831 #define _DMA_IEN_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */
<> 150:02e0a0aed4ec 1832 #define _DMA_IEN_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */
<> 150:02e0a0aed4ec 1833 #define _DMA_IEN_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
<> 150:02e0a0aed4ec 1834 #define DMA_IEN_CH5DONE_DEFAULT (_DMA_IEN_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IEN */
<> 150:02e0a0aed4ec 1835 #define DMA_IEN_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Enable */
<> 150:02e0a0aed4ec 1836 #define _DMA_IEN_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */
<> 150:02e0a0aed4ec 1837 #define _DMA_IEN_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */
<> 150:02e0a0aed4ec 1838 #define _DMA_IEN_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
<> 150:02e0a0aed4ec 1839 #define DMA_IEN_CH6DONE_DEFAULT (_DMA_IEN_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IEN */
<> 150:02e0a0aed4ec 1840 #define DMA_IEN_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Enable */
<> 150:02e0a0aed4ec 1841 #define _DMA_IEN_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */
<> 150:02e0a0aed4ec 1842 #define _DMA_IEN_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */
<> 150:02e0a0aed4ec 1843 #define _DMA_IEN_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
<> 150:02e0a0aed4ec 1844 #define DMA_IEN_CH7DONE_DEFAULT (_DMA_IEN_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IEN */
<> 150:02e0a0aed4ec 1845 #define DMA_IEN_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Enable */
<> 150:02e0a0aed4ec 1846 #define _DMA_IEN_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */
<> 150:02e0a0aed4ec 1847 #define _DMA_IEN_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */
<> 150:02e0a0aed4ec 1848 #define _DMA_IEN_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
<> 150:02e0a0aed4ec 1849 #define DMA_IEN_CH8DONE_DEFAULT (_DMA_IEN_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IEN */
<> 150:02e0a0aed4ec 1850 #define DMA_IEN_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Enable */
<> 150:02e0a0aed4ec 1851 #define _DMA_IEN_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */
<> 150:02e0a0aed4ec 1852 #define _DMA_IEN_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */
<> 150:02e0a0aed4ec 1853 #define _DMA_IEN_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
<> 150:02e0a0aed4ec 1854 #define DMA_IEN_CH9DONE_DEFAULT (_DMA_IEN_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IEN */
<> 150:02e0a0aed4ec 1855 #define DMA_IEN_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Enable */
<> 150:02e0a0aed4ec 1856 #define _DMA_IEN_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */
<> 150:02e0a0aed4ec 1857 #define _DMA_IEN_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */
<> 150:02e0a0aed4ec 1858 #define _DMA_IEN_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
<> 150:02e0a0aed4ec 1859 #define DMA_IEN_CH10DONE_DEFAULT (_DMA_IEN_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IEN */
<> 150:02e0a0aed4ec 1860 #define DMA_IEN_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Enable */
<> 150:02e0a0aed4ec 1861 #define _DMA_IEN_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */
<> 150:02e0a0aed4ec 1862 #define _DMA_IEN_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */
<> 150:02e0a0aed4ec 1863 #define _DMA_IEN_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
<> 150:02e0a0aed4ec 1864 #define DMA_IEN_CH11DONE_DEFAULT (_DMA_IEN_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IEN */
<> 150:02e0a0aed4ec 1865 #define DMA_IEN_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Enable */
<> 150:02e0a0aed4ec 1866 #define _DMA_IEN_ERR_SHIFT 31 /**< Shift value for DMA_ERR */
<> 150:02e0a0aed4ec 1867 #define _DMA_IEN_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */
<> 150:02e0a0aed4ec 1868 #define _DMA_IEN_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
<> 150:02e0a0aed4ec 1869 #define DMA_IEN_ERR_DEFAULT (_DMA_IEN_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IEN */
<> 150:02e0a0aed4ec 1870
<> 150:02e0a0aed4ec 1871 /* Bit fields for DMA CTRL */
<> 150:02e0a0aed4ec 1872 #define _DMA_CTRL_RESETVALUE 0x00000000UL /**< Default value for DMA_CTRL */
<> 150:02e0a0aed4ec 1873 #define _DMA_CTRL_MASK 0x00000003UL /**< Mask for DMA_CTRL */
<> 150:02e0a0aed4ec 1874 #define DMA_CTRL_DESCRECT (0x1UL << 0) /**< Descriptor Specifies Rectangle */
<> 150:02e0a0aed4ec 1875 #define _DMA_CTRL_DESCRECT_SHIFT 0 /**< Shift value for DMA_DESCRECT */
<> 150:02e0a0aed4ec 1876 #define _DMA_CTRL_DESCRECT_MASK 0x1UL /**< Bit mask for DMA_DESCRECT */
<> 150:02e0a0aed4ec 1877 #define _DMA_CTRL_DESCRECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRL */
<> 150:02e0a0aed4ec 1878 #define DMA_CTRL_DESCRECT_DEFAULT (_DMA_CTRL_DESCRECT_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CTRL */
<> 150:02e0a0aed4ec 1879 #define DMA_CTRL_PRDU (0x1UL << 1) /**< Prevent Rect Descriptor Update */
<> 150:02e0a0aed4ec 1880 #define _DMA_CTRL_PRDU_SHIFT 1 /**< Shift value for DMA_PRDU */
<> 150:02e0a0aed4ec 1881 #define _DMA_CTRL_PRDU_MASK 0x2UL /**< Bit mask for DMA_PRDU */
<> 150:02e0a0aed4ec 1882 #define _DMA_CTRL_PRDU_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRL */
<> 150:02e0a0aed4ec 1883 #define DMA_CTRL_PRDU_DEFAULT (_DMA_CTRL_PRDU_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CTRL */
<> 150:02e0a0aed4ec 1884
<> 150:02e0a0aed4ec 1885 /* Bit fields for DMA RDS */
<> 150:02e0a0aed4ec 1886 #define _DMA_RDS_RESETVALUE 0x00000000UL /**< Default value for DMA_RDS */
<> 150:02e0a0aed4ec 1887 #define _DMA_RDS_MASK 0x00000FFFUL /**< Mask for DMA_RDS */
<> 150:02e0a0aed4ec 1888 #define DMA_RDS_RDSCH0 (0x1UL << 0) /**< Retain Descriptor State */
<> 150:02e0a0aed4ec 1889 #define _DMA_RDS_RDSCH0_SHIFT 0 /**< Shift value for DMA_RDSCH0 */
<> 150:02e0a0aed4ec 1890 #define _DMA_RDS_RDSCH0_MASK 0x1UL /**< Bit mask for DMA_RDSCH0 */
<> 150:02e0a0aed4ec 1891 #define _DMA_RDS_RDSCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
<> 150:02e0a0aed4ec 1892 #define DMA_RDS_RDSCH0_DEFAULT (_DMA_RDS_RDSCH0_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_RDS */
<> 150:02e0a0aed4ec 1893 #define DMA_RDS_RDSCH1 (0x1UL << 1) /**< Retain Descriptor State */
<> 150:02e0a0aed4ec 1894 #define _DMA_RDS_RDSCH1_SHIFT 1 /**< Shift value for DMA_RDSCH1 */
<> 150:02e0a0aed4ec 1895 #define _DMA_RDS_RDSCH1_MASK 0x2UL /**< Bit mask for DMA_RDSCH1 */
<> 150:02e0a0aed4ec 1896 #define _DMA_RDS_RDSCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
<> 150:02e0a0aed4ec 1897 #define DMA_RDS_RDSCH1_DEFAULT (_DMA_RDS_RDSCH1_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_RDS */
<> 150:02e0a0aed4ec 1898 #define DMA_RDS_RDSCH2 (0x1UL << 2) /**< Retain Descriptor State */
<> 150:02e0a0aed4ec 1899 #define _DMA_RDS_RDSCH2_SHIFT 2 /**< Shift value for DMA_RDSCH2 */
<> 150:02e0a0aed4ec 1900 #define _DMA_RDS_RDSCH2_MASK 0x4UL /**< Bit mask for DMA_RDSCH2 */
<> 150:02e0a0aed4ec 1901 #define _DMA_RDS_RDSCH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
<> 150:02e0a0aed4ec 1902 #define DMA_RDS_RDSCH2_DEFAULT (_DMA_RDS_RDSCH2_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_RDS */
<> 150:02e0a0aed4ec 1903 #define DMA_RDS_RDSCH3 (0x1UL << 3) /**< Retain Descriptor State */
<> 150:02e0a0aed4ec 1904 #define _DMA_RDS_RDSCH3_SHIFT 3 /**< Shift value for DMA_RDSCH3 */
<> 150:02e0a0aed4ec 1905 #define _DMA_RDS_RDSCH3_MASK 0x8UL /**< Bit mask for DMA_RDSCH3 */
<> 150:02e0a0aed4ec 1906 #define _DMA_RDS_RDSCH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
<> 150:02e0a0aed4ec 1907 #define DMA_RDS_RDSCH3_DEFAULT (_DMA_RDS_RDSCH3_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_RDS */
<> 150:02e0a0aed4ec 1908 #define DMA_RDS_RDSCH4 (0x1UL << 4) /**< Retain Descriptor State */
<> 150:02e0a0aed4ec 1909 #define _DMA_RDS_RDSCH4_SHIFT 4 /**< Shift value for DMA_RDSCH4 */
<> 150:02e0a0aed4ec 1910 #define _DMA_RDS_RDSCH4_MASK 0x10UL /**< Bit mask for DMA_RDSCH4 */
<> 150:02e0a0aed4ec 1911 #define _DMA_RDS_RDSCH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
<> 150:02e0a0aed4ec 1912 #define DMA_RDS_RDSCH4_DEFAULT (_DMA_RDS_RDSCH4_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_RDS */
<> 150:02e0a0aed4ec 1913 #define DMA_RDS_RDSCH5 (0x1UL << 5) /**< Retain Descriptor State */
<> 150:02e0a0aed4ec 1914 #define _DMA_RDS_RDSCH5_SHIFT 5 /**< Shift value for DMA_RDSCH5 */
<> 150:02e0a0aed4ec 1915 #define _DMA_RDS_RDSCH5_MASK 0x20UL /**< Bit mask for DMA_RDSCH5 */
<> 150:02e0a0aed4ec 1916 #define _DMA_RDS_RDSCH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
<> 150:02e0a0aed4ec 1917 #define DMA_RDS_RDSCH5_DEFAULT (_DMA_RDS_RDSCH5_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_RDS */
<> 150:02e0a0aed4ec 1918 #define DMA_RDS_RDSCH6 (0x1UL << 6) /**< Retain Descriptor State */
<> 150:02e0a0aed4ec 1919 #define _DMA_RDS_RDSCH6_SHIFT 6 /**< Shift value for DMA_RDSCH6 */
<> 150:02e0a0aed4ec 1920 #define _DMA_RDS_RDSCH6_MASK 0x40UL /**< Bit mask for DMA_RDSCH6 */
<> 150:02e0a0aed4ec 1921 #define _DMA_RDS_RDSCH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
<> 150:02e0a0aed4ec 1922 #define DMA_RDS_RDSCH6_DEFAULT (_DMA_RDS_RDSCH6_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_RDS */
<> 150:02e0a0aed4ec 1923 #define DMA_RDS_RDSCH7 (0x1UL << 7) /**< Retain Descriptor State */
<> 150:02e0a0aed4ec 1924 #define _DMA_RDS_RDSCH7_SHIFT 7 /**< Shift value for DMA_RDSCH7 */
<> 150:02e0a0aed4ec 1925 #define _DMA_RDS_RDSCH7_MASK 0x80UL /**< Bit mask for DMA_RDSCH7 */
<> 150:02e0a0aed4ec 1926 #define _DMA_RDS_RDSCH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
<> 150:02e0a0aed4ec 1927 #define DMA_RDS_RDSCH7_DEFAULT (_DMA_RDS_RDSCH7_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_RDS */
<> 150:02e0a0aed4ec 1928 #define DMA_RDS_RDSCH8 (0x1UL << 8) /**< Retain Descriptor State */
<> 150:02e0a0aed4ec 1929 #define _DMA_RDS_RDSCH8_SHIFT 8 /**< Shift value for DMA_RDSCH8 */
<> 150:02e0a0aed4ec 1930 #define _DMA_RDS_RDSCH8_MASK 0x100UL /**< Bit mask for DMA_RDSCH8 */
<> 150:02e0a0aed4ec 1931 #define _DMA_RDS_RDSCH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
<> 150:02e0a0aed4ec 1932 #define DMA_RDS_RDSCH8_DEFAULT (_DMA_RDS_RDSCH8_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_RDS */
<> 150:02e0a0aed4ec 1933 #define DMA_RDS_RDSCH9 (0x1UL << 9) /**< Retain Descriptor State */
<> 150:02e0a0aed4ec 1934 #define _DMA_RDS_RDSCH9_SHIFT 9 /**< Shift value for DMA_RDSCH9 */
<> 150:02e0a0aed4ec 1935 #define _DMA_RDS_RDSCH9_MASK 0x200UL /**< Bit mask for DMA_RDSCH9 */
<> 150:02e0a0aed4ec 1936 #define _DMA_RDS_RDSCH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
<> 150:02e0a0aed4ec 1937 #define DMA_RDS_RDSCH9_DEFAULT (_DMA_RDS_RDSCH9_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_RDS */
<> 150:02e0a0aed4ec 1938 #define DMA_RDS_RDSCH10 (0x1UL << 10) /**< Retain Descriptor State */
<> 150:02e0a0aed4ec 1939 #define _DMA_RDS_RDSCH10_SHIFT 10 /**< Shift value for DMA_RDSCH10 */
<> 150:02e0a0aed4ec 1940 #define _DMA_RDS_RDSCH10_MASK 0x400UL /**< Bit mask for DMA_RDSCH10 */
<> 150:02e0a0aed4ec 1941 #define _DMA_RDS_RDSCH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
<> 150:02e0a0aed4ec 1942 #define DMA_RDS_RDSCH10_DEFAULT (_DMA_RDS_RDSCH10_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_RDS */
<> 150:02e0a0aed4ec 1943 #define DMA_RDS_RDSCH11 (0x1UL << 11) /**< Retain Descriptor State */
<> 150:02e0a0aed4ec 1944 #define _DMA_RDS_RDSCH11_SHIFT 11 /**< Shift value for DMA_RDSCH11 */
<> 150:02e0a0aed4ec 1945 #define _DMA_RDS_RDSCH11_MASK 0x800UL /**< Bit mask for DMA_RDSCH11 */
<> 150:02e0a0aed4ec 1946 #define _DMA_RDS_RDSCH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
<> 150:02e0a0aed4ec 1947 #define DMA_RDS_RDSCH11_DEFAULT (_DMA_RDS_RDSCH11_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_RDS */
<> 150:02e0a0aed4ec 1948
<> 150:02e0a0aed4ec 1949 /* Bit fields for DMA LOOP0 */
<> 150:02e0a0aed4ec 1950 #define _DMA_LOOP0_RESETVALUE 0x00000000UL /**< Default value for DMA_LOOP0 */
<> 150:02e0a0aed4ec 1951 #define _DMA_LOOP0_MASK 0x000103FFUL /**< Mask for DMA_LOOP0 */
<> 150:02e0a0aed4ec 1952 #define _DMA_LOOP0_WIDTH_SHIFT 0 /**< Shift value for DMA_WIDTH */
<> 150:02e0a0aed4ec 1953 #define _DMA_LOOP0_WIDTH_MASK 0x3FFUL /**< Bit mask for DMA_WIDTH */
<> 150:02e0a0aed4ec 1954 #define _DMA_LOOP0_WIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP0 */
<> 150:02e0a0aed4ec 1955 #define DMA_LOOP0_WIDTH_DEFAULT (_DMA_LOOP0_WIDTH_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_LOOP0 */
<> 150:02e0a0aed4ec 1956 #define DMA_LOOP0_EN (0x1UL << 16) /**< DMA Channel 0 Loop Enable */
<> 150:02e0a0aed4ec 1957 #define _DMA_LOOP0_EN_SHIFT 16 /**< Shift value for DMA_EN */
<> 150:02e0a0aed4ec 1958 #define _DMA_LOOP0_EN_MASK 0x10000UL /**< Bit mask for DMA_EN */
<> 150:02e0a0aed4ec 1959 #define _DMA_LOOP0_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP0 */
<> 150:02e0a0aed4ec 1960 #define DMA_LOOP0_EN_DEFAULT (_DMA_LOOP0_EN_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_LOOP0 */
<> 150:02e0a0aed4ec 1961
<> 150:02e0a0aed4ec 1962 /* Bit fields for DMA LOOP1 */
<> 150:02e0a0aed4ec 1963 #define _DMA_LOOP1_RESETVALUE 0x00000000UL /**< Default value for DMA_LOOP1 */
<> 150:02e0a0aed4ec 1964 #define _DMA_LOOP1_MASK 0x000103FFUL /**< Mask for DMA_LOOP1 */
<> 150:02e0a0aed4ec 1965 #define _DMA_LOOP1_WIDTH_SHIFT 0 /**< Shift value for DMA_WIDTH */
<> 150:02e0a0aed4ec 1966 #define _DMA_LOOP1_WIDTH_MASK 0x3FFUL /**< Bit mask for DMA_WIDTH */
<> 150:02e0a0aed4ec 1967 #define _DMA_LOOP1_WIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP1 */
<> 150:02e0a0aed4ec 1968 #define DMA_LOOP1_WIDTH_DEFAULT (_DMA_LOOP1_WIDTH_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_LOOP1 */
<> 150:02e0a0aed4ec 1969 #define DMA_LOOP1_EN (0x1UL << 16) /**< DMA Channel 1 Loop Enable */
<> 150:02e0a0aed4ec 1970 #define _DMA_LOOP1_EN_SHIFT 16 /**< Shift value for DMA_EN */
<> 150:02e0a0aed4ec 1971 #define _DMA_LOOP1_EN_MASK 0x10000UL /**< Bit mask for DMA_EN */
<> 150:02e0a0aed4ec 1972 #define _DMA_LOOP1_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP1 */
<> 150:02e0a0aed4ec 1973 #define DMA_LOOP1_EN_DEFAULT (_DMA_LOOP1_EN_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_LOOP1 */
<> 150:02e0a0aed4ec 1974
<> 150:02e0a0aed4ec 1975 /* Bit fields for DMA RECT0 */
<> 150:02e0a0aed4ec 1976 #define _DMA_RECT0_RESETVALUE 0x00000000UL /**< Default value for DMA_RECT0 */
<> 150:02e0a0aed4ec 1977 #define _DMA_RECT0_MASK 0xFFFFFFFFUL /**< Mask for DMA_RECT0 */
<> 150:02e0a0aed4ec 1978 #define _DMA_RECT0_HEIGHT_SHIFT 0 /**< Shift value for DMA_HEIGHT */
<> 150:02e0a0aed4ec 1979 #define _DMA_RECT0_HEIGHT_MASK 0x3FFUL /**< Bit mask for DMA_HEIGHT */
<> 150:02e0a0aed4ec 1980 #define _DMA_RECT0_HEIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */
<> 150:02e0a0aed4ec 1981 #define DMA_RECT0_HEIGHT_DEFAULT (_DMA_RECT0_HEIGHT_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_RECT0 */
<> 150:02e0a0aed4ec 1982 #define _DMA_RECT0_SRCSTRIDE_SHIFT 10 /**< Shift value for DMA_SRCSTRIDE */
<> 150:02e0a0aed4ec 1983 #define _DMA_RECT0_SRCSTRIDE_MASK 0x1FFC00UL /**< Bit mask for DMA_SRCSTRIDE */
<> 150:02e0a0aed4ec 1984 #define _DMA_RECT0_SRCSTRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */
<> 150:02e0a0aed4ec 1985 #define DMA_RECT0_SRCSTRIDE_DEFAULT (_DMA_RECT0_SRCSTRIDE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_RECT0 */
<> 150:02e0a0aed4ec 1986 #define _DMA_RECT0_DSTSTRIDE_SHIFT 21 /**< Shift value for DMA_DSTSTRIDE */
<> 150:02e0a0aed4ec 1987 #define _DMA_RECT0_DSTSTRIDE_MASK 0xFFE00000UL /**< Bit mask for DMA_DSTSTRIDE */
<> 150:02e0a0aed4ec 1988 #define _DMA_RECT0_DSTSTRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */
<> 150:02e0a0aed4ec 1989 #define DMA_RECT0_DSTSTRIDE_DEFAULT (_DMA_RECT0_DSTSTRIDE_DEFAULT << 21) /**< Shifted mode DEFAULT for DMA_RECT0 */
<> 150:02e0a0aed4ec 1990
<> 150:02e0a0aed4ec 1991 /* Bit fields for DMA CH_CTRL */
<> 150:02e0a0aed4ec 1992 #define _DMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1993 #define _DMA_CH_CTRL_MASK 0x003F000FUL /**< Mask for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1994 #define _DMA_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for DMA_SIGSEL */
<> 150:02e0a0aed4ec 1995 #define _DMA_CH_CTRL_SIGSEL_MASK 0xFUL /**< Bit mask for DMA_SIGSEL */
<> 150:02e0a0aed4ec 1996 #define _DMA_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1997 #define _DMA_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1998 #define _DMA_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000000UL /**< Mode USART0RXDATAV for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 1999 #define _DMA_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000000UL /**< Mode USART1RXDATAV for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2000 #define _DMA_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000000UL /**< Mode USART2RXDATAV for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2001 #define _DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV 0x00000000UL /**< Mode LEUART0RXDATAV for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2002 #define _DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV 0x00000000UL /**< Mode LEUART1RXDATAV for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2003 #define _DMA_CH_CTRL_SIGSEL_I2C0RXDATAV 0x00000000UL /**< Mode I2C0RXDATAV for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2004 #define _DMA_CH_CTRL_SIGSEL_I2C1RXDATAV 0x00000000UL /**< Mode I2C1RXDATAV for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2005 #define _DMA_CH_CTRL_SIGSEL_TIMER0UFOF 0x00000000UL /**< Mode TIMER0UFOF for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2006 #define _DMA_CH_CTRL_SIGSEL_TIMER1UFOF 0x00000000UL /**< Mode TIMER1UFOF for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2007 #define _DMA_CH_CTRL_SIGSEL_TIMER2UFOF 0x00000000UL /**< Mode TIMER2UFOF for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2008 #define _DMA_CH_CTRL_SIGSEL_TIMER3UFOF 0x00000000UL /**< Mode TIMER3UFOF for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2009 #define _DMA_CH_CTRL_SIGSEL_MSCWDATA 0x00000000UL /**< Mode MSCWDATA for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2010 #define _DMA_CH_CTRL_SIGSEL_AESDATAWR 0x00000000UL /**< Mode AESDATAWR for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2011 #define _DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV 0x00000000UL /**< Mode LESENSEBUFDATAV for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2012 #define _DMA_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2013 #define _DMA_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2014 #define _DMA_CH_CTRL_SIGSEL_USART0TXBL 0x00000001UL /**< Mode USART0TXBL for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2015 #define _DMA_CH_CTRL_SIGSEL_USART1TXBL 0x00000001UL /**< Mode USART1TXBL for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2016 #define _DMA_CH_CTRL_SIGSEL_USART2TXBL 0x00000001UL /**< Mode USART2TXBL for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2017 #define _DMA_CH_CTRL_SIGSEL_LEUART0TXBL 0x00000001UL /**< Mode LEUART0TXBL for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2018 #define _DMA_CH_CTRL_SIGSEL_LEUART1TXBL 0x00000001UL /**< Mode LEUART1TXBL for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2019 #define _DMA_CH_CTRL_SIGSEL_I2C0TXBL 0x00000001UL /**< Mode I2C0TXBL for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2020 #define _DMA_CH_CTRL_SIGSEL_I2C1TXBL 0x00000001UL /**< Mode I2C1TXBL for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2021 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC0 0x00000001UL /**< Mode TIMER0CC0 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2022 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC0 0x00000001UL /**< Mode TIMER1CC0 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2023 #define _DMA_CH_CTRL_SIGSEL_TIMER2CC0 0x00000001UL /**< Mode TIMER2CC0 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2024 #define _DMA_CH_CTRL_SIGSEL_TIMER3CC0 0x00000001UL /**< Mode TIMER3CC0 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2025 #define _DMA_CH_CTRL_SIGSEL_AESXORDATAWR 0x00000001UL /**< Mode AESXORDATAWR for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2026 #define _DMA_CH_CTRL_SIGSEL_USART0TXEMPTY 0x00000002UL /**< Mode USART0TXEMPTY for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2027 #define _DMA_CH_CTRL_SIGSEL_USART1TXEMPTY 0x00000002UL /**< Mode USART1TXEMPTY for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2028 #define _DMA_CH_CTRL_SIGSEL_USART2TXEMPTY 0x00000002UL /**< Mode USART2TXEMPTY for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2029 #define _DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY 0x00000002UL /**< Mode LEUART0TXEMPTY for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2030 #define _DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY 0x00000002UL /**< Mode LEUART1TXEMPTY for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2031 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC1 0x00000002UL /**< Mode TIMER0CC1 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2032 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC1 0x00000002UL /**< Mode TIMER1CC1 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2033 #define _DMA_CH_CTRL_SIGSEL_TIMER2CC1 0x00000002UL /**< Mode TIMER2CC1 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2034 #define _DMA_CH_CTRL_SIGSEL_TIMER3CC1 0x00000002UL /**< Mode TIMER3CC1 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2035 #define _DMA_CH_CTRL_SIGSEL_AESDATARD 0x00000002UL /**< Mode AESDATARD for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2036 #define _DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT 0x00000003UL /**< Mode USART1RXDATAVRIGHT for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2037 #define _DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT 0x00000003UL /**< Mode USART2RXDATAVRIGHT for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2038 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC2 0x00000003UL /**< Mode TIMER0CC2 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2039 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC2 0x00000003UL /**< Mode TIMER1CC2 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2040 #define _DMA_CH_CTRL_SIGSEL_TIMER2CC2 0x00000003UL /**< Mode TIMER2CC2 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2041 #define _DMA_CH_CTRL_SIGSEL_TIMER3CC2 0x00000003UL /**< Mode TIMER3CC2 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2042 #define _DMA_CH_CTRL_SIGSEL_AESKEYWR 0x00000003UL /**< Mode AESKEYWR for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2043 #define _DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT 0x00000004UL /**< Mode USART1TXBLRIGHT for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2044 #define _DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT 0x00000004UL /**< Mode USART2TXBLRIGHT for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2045 #define DMA_CH_CTRL_SIGSEL_ADC0SINGLE (_DMA_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2046 #define DMA_CH_CTRL_SIGSEL_DAC0CH0 (_DMA_CH_CTRL_SIGSEL_DAC0CH0 << 0) /**< Shifted mode DAC0CH0 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2047 #define DMA_CH_CTRL_SIGSEL_USART0RXDATAV (_DMA_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2048 #define DMA_CH_CTRL_SIGSEL_USART1RXDATAV (_DMA_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2049 #define DMA_CH_CTRL_SIGSEL_USART2RXDATAV (_DMA_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2050 #define DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV << 0) /**< Shifted mode LEUART0RXDATAV for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2051 #define DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV << 0) /**< Shifted mode LEUART1RXDATAV for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2052 #define DMA_CH_CTRL_SIGSEL_I2C0RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV << 0) /**< Shifted mode I2C0RXDATAV for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2053 #define DMA_CH_CTRL_SIGSEL_I2C1RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C1RXDATAV << 0) /**< Shifted mode I2C1RXDATAV for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2054 #define DMA_CH_CTRL_SIGSEL_TIMER0UFOF (_DMA_CH_CTRL_SIGSEL_TIMER0UFOF << 0) /**< Shifted mode TIMER0UFOF for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2055 #define DMA_CH_CTRL_SIGSEL_TIMER1UFOF (_DMA_CH_CTRL_SIGSEL_TIMER1UFOF << 0) /**< Shifted mode TIMER1UFOF for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2056 #define DMA_CH_CTRL_SIGSEL_TIMER2UFOF (_DMA_CH_CTRL_SIGSEL_TIMER2UFOF << 0) /**< Shifted mode TIMER2UFOF for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2057 #define DMA_CH_CTRL_SIGSEL_TIMER3UFOF (_DMA_CH_CTRL_SIGSEL_TIMER3UFOF << 0) /**< Shifted mode TIMER3UFOF for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2058 #define DMA_CH_CTRL_SIGSEL_MSCWDATA (_DMA_CH_CTRL_SIGSEL_MSCWDATA << 0) /**< Shifted mode MSCWDATA for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2059 #define DMA_CH_CTRL_SIGSEL_AESDATAWR (_DMA_CH_CTRL_SIGSEL_AESDATAWR << 0) /**< Shifted mode AESDATAWR for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2060 #define DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV (_DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV << 0) /**< Shifted mode LESENSEBUFDATAV for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2061 #define DMA_CH_CTRL_SIGSEL_ADC0SCAN (_DMA_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2062 #define DMA_CH_CTRL_SIGSEL_DAC0CH1 (_DMA_CH_CTRL_SIGSEL_DAC0CH1 << 0) /**< Shifted mode DAC0CH1 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2063 #define DMA_CH_CTRL_SIGSEL_USART0TXBL (_DMA_CH_CTRL_SIGSEL_USART0TXBL << 0) /**< Shifted mode USART0TXBL for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2064 #define DMA_CH_CTRL_SIGSEL_USART1TXBL (_DMA_CH_CTRL_SIGSEL_USART1TXBL << 0) /**< Shifted mode USART1TXBL for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2065 #define DMA_CH_CTRL_SIGSEL_USART2TXBL (_DMA_CH_CTRL_SIGSEL_USART2TXBL << 0) /**< Shifted mode USART2TXBL for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2066 #define DMA_CH_CTRL_SIGSEL_LEUART0TXBL (_DMA_CH_CTRL_SIGSEL_LEUART0TXBL << 0) /**< Shifted mode LEUART0TXBL for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2067 #define DMA_CH_CTRL_SIGSEL_LEUART1TXBL (_DMA_CH_CTRL_SIGSEL_LEUART1TXBL << 0) /**< Shifted mode LEUART1TXBL for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2068 #define DMA_CH_CTRL_SIGSEL_I2C0TXBL (_DMA_CH_CTRL_SIGSEL_I2C0TXBL << 0) /**< Shifted mode I2C0TXBL for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2069 #define DMA_CH_CTRL_SIGSEL_I2C1TXBL (_DMA_CH_CTRL_SIGSEL_I2C1TXBL << 0) /**< Shifted mode I2C1TXBL for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2070 #define DMA_CH_CTRL_SIGSEL_TIMER0CC0 (_DMA_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2071 #define DMA_CH_CTRL_SIGSEL_TIMER1CC0 (_DMA_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2072 #define DMA_CH_CTRL_SIGSEL_TIMER2CC0 (_DMA_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2073 #define DMA_CH_CTRL_SIGSEL_TIMER3CC0 (_DMA_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2074 #define DMA_CH_CTRL_SIGSEL_AESXORDATAWR (_DMA_CH_CTRL_SIGSEL_AESXORDATAWR << 0) /**< Shifted mode AESXORDATAWR for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2075 #define DMA_CH_CTRL_SIGSEL_USART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART0TXEMPTY << 0) /**< Shifted mode USART0TXEMPTY for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2076 #define DMA_CH_CTRL_SIGSEL_USART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART1TXEMPTY << 0) /**< Shifted mode USART1TXEMPTY for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2077 #define DMA_CH_CTRL_SIGSEL_USART2TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART2TXEMPTY << 0) /**< Shifted mode USART2TXEMPTY for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2078 #define DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY << 0) /**< Shifted mode LEUART0TXEMPTY for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2079 #define DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY << 0) /**< Shifted mode LEUART1TXEMPTY for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2080 #define DMA_CH_CTRL_SIGSEL_TIMER0CC1 (_DMA_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2081 #define DMA_CH_CTRL_SIGSEL_TIMER1CC1 (_DMA_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2082 #define DMA_CH_CTRL_SIGSEL_TIMER2CC1 (_DMA_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2083 #define DMA_CH_CTRL_SIGSEL_TIMER3CC1 (_DMA_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2084 #define DMA_CH_CTRL_SIGSEL_AESDATARD (_DMA_CH_CTRL_SIGSEL_AESDATARD << 0) /**< Shifted mode AESDATARD for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2085 #define DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT << 0) /**< Shifted mode USART1RXDATAVRIGHT for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2086 #define DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT << 0) /**< Shifted mode USART2RXDATAVRIGHT for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2087 #define DMA_CH_CTRL_SIGSEL_TIMER0CC2 (_DMA_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2088 #define DMA_CH_CTRL_SIGSEL_TIMER1CC2 (_DMA_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2089 #define DMA_CH_CTRL_SIGSEL_TIMER2CC2 (_DMA_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2090 #define DMA_CH_CTRL_SIGSEL_TIMER3CC2 (_DMA_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2091 #define DMA_CH_CTRL_SIGSEL_AESKEYWR (_DMA_CH_CTRL_SIGSEL_AESKEYWR << 0) /**< Shifted mode AESKEYWR for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2092 #define DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT << 0) /**< Shifted mode USART1TXBLRIGHT for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2093 #define DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT << 0) /**< Shifted mode USART2TXBLRIGHT for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2094 #define _DMA_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for DMA_SOURCESEL */
<> 150:02e0a0aed4ec 2095 #define _DMA_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for DMA_SOURCESEL */
<> 150:02e0a0aed4ec 2096 #define _DMA_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2097 #define _DMA_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2098 #define _DMA_CH_CTRL_SOURCESEL_DAC0 0x0000000AUL /**< Mode DAC0 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2099 #define _DMA_CH_CTRL_SOURCESEL_USART0 0x0000000CUL /**< Mode USART0 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2100 #define _DMA_CH_CTRL_SOURCESEL_USART1 0x0000000DUL /**< Mode USART1 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2101 #define _DMA_CH_CTRL_SOURCESEL_USART2 0x0000000EUL /**< Mode USART2 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2102 #define _DMA_CH_CTRL_SOURCESEL_LEUART0 0x00000010UL /**< Mode LEUART0 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2103 #define _DMA_CH_CTRL_SOURCESEL_LEUART1 0x00000011UL /**< Mode LEUART1 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2104 #define _DMA_CH_CTRL_SOURCESEL_I2C0 0x00000014UL /**< Mode I2C0 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2105 #define _DMA_CH_CTRL_SOURCESEL_I2C1 0x00000015UL /**< Mode I2C1 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2106 #define _DMA_CH_CTRL_SOURCESEL_TIMER0 0x00000018UL /**< Mode TIMER0 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2107 #define _DMA_CH_CTRL_SOURCESEL_TIMER1 0x00000019UL /**< Mode TIMER1 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2108 #define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL /**< Mode TIMER2 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2109 #define _DMA_CH_CTRL_SOURCESEL_TIMER3 0x0000001BUL /**< Mode TIMER3 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2110 #define _DMA_CH_CTRL_SOURCESEL_MSC 0x00000030UL /**< Mode MSC for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2111 #define _DMA_CH_CTRL_SOURCESEL_AES 0x00000031UL /**< Mode AES for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2112 #define _DMA_CH_CTRL_SOURCESEL_LESENSE 0x00000032UL /**< Mode LESENSE for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2113 #define DMA_CH_CTRL_SOURCESEL_NONE (_DMA_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2114 #define DMA_CH_CTRL_SOURCESEL_ADC0 (_DMA_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2115 #define DMA_CH_CTRL_SOURCESEL_DAC0 (_DMA_CH_CTRL_SOURCESEL_DAC0 << 16) /**< Shifted mode DAC0 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2116 #define DMA_CH_CTRL_SOURCESEL_USART0 (_DMA_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2117 #define DMA_CH_CTRL_SOURCESEL_USART1 (_DMA_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2118 #define DMA_CH_CTRL_SOURCESEL_USART2 (_DMA_CH_CTRL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2119 #define DMA_CH_CTRL_SOURCESEL_LEUART0 (_DMA_CH_CTRL_SOURCESEL_LEUART0 << 16) /**< Shifted mode LEUART0 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2120 #define DMA_CH_CTRL_SOURCESEL_LEUART1 (_DMA_CH_CTRL_SOURCESEL_LEUART1 << 16) /**< Shifted mode LEUART1 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2121 #define DMA_CH_CTRL_SOURCESEL_I2C0 (_DMA_CH_CTRL_SOURCESEL_I2C0 << 16) /**< Shifted mode I2C0 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2122 #define DMA_CH_CTRL_SOURCESEL_I2C1 (_DMA_CH_CTRL_SOURCESEL_I2C1 << 16) /**< Shifted mode I2C1 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2123 #define DMA_CH_CTRL_SOURCESEL_TIMER0 (_DMA_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2124 #define DMA_CH_CTRL_SOURCESEL_TIMER1 (_DMA_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2125 #define DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2126 #define DMA_CH_CTRL_SOURCESEL_TIMER3 (_DMA_CH_CTRL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2127 #define DMA_CH_CTRL_SOURCESEL_MSC (_DMA_CH_CTRL_SOURCESEL_MSC << 16) /**< Shifted mode MSC for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2128 #define DMA_CH_CTRL_SOURCESEL_AES (_DMA_CH_CTRL_SOURCESEL_AES << 16) /**< Shifted mode AES for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2129 #define DMA_CH_CTRL_SOURCESEL_LESENSE (_DMA_CH_CTRL_SOURCESEL_LESENSE << 16) /**< Shifted mode LESENSE for DMA_CH_CTRL */
<> 150:02e0a0aed4ec 2130
<> 150:02e0a0aed4ec 2131 /** @} End of group EFM32WG332F256_DMA */
<> 150:02e0a0aed4ec 2132
<> 150:02e0a0aed4ec 2133
<> 150:02e0a0aed4ec 2134
<> 150:02e0a0aed4ec 2135 /**************************************************************************//**
<> 150:02e0a0aed4ec 2136 * @defgroup EFM32WG332F256_CMU_BitFields EFM32WG332F256_CMU Bit Fields
<> 150:02e0a0aed4ec 2137 * @{
<> 150:02e0a0aed4ec 2138 *****************************************************************************/
<> 150:02e0a0aed4ec 2139
<> 150:02e0a0aed4ec 2140 /* Bit fields for CMU CTRL */
<> 150:02e0a0aed4ec 2141 #define _CMU_CTRL_RESETVALUE 0x000C262CUL /**< Default value for CMU_CTRL */
<> 150:02e0a0aed4ec 2142 #define _CMU_CTRL_MASK 0x57FFFEEFUL /**< Mask for CMU_CTRL */
<> 150:02e0a0aed4ec 2143 #define _CMU_CTRL_HFXOMODE_SHIFT 0 /**< Shift value for CMU_HFXOMODE */
<> 150:02e0a0aed4ec 2144 #define _CMU_CTRL_HFXOMODE_MASK 0x3UL /**< Bit mask for CMU_HFXOMODE */
<> 150:02e0a0aed4ec 2145 #define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 2146 #define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */
<> 150:02e0a0aed4ec 2147 #define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */
<> 150:02e0a0aed4ec 2148 #define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */
<> 150:02e0a0aed4ec 2149 #define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 2150 #define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0) /**< Shifted mode XTAL for CMU_CTRL */
<> 150:02e0a0aed4ec 2151 #define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0) /**< Shifted mode BUFEXTCLK for CMU_CTRL */
<> 150:02e0a0aed4ec 2152 #define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_CTRL */
<> 150:02e0a0aed4ec 2153 #define _CMU_CTRL_HFXOBOOST_SHIFT 2 /**< Shift value for CMU_HFXOBOOST */
<> 150:02e0a0aed4ec 2154 #define _CMU_CTRL_HFXOBOOST_MASK 0xCUL /**< Bit mask for CMU_HFXOBOOST */
<> 150:02e0a0aed4ec 2155 #define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL /**< Mode 50PCENT for CMU_CTRL */
<> 150:02e0a0aed4ec 2156 #define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL /**< Mode 70PCENT for CMU_CTRL */
<> 150:02e0a0aed4ec 2157 #define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL /**< Mode 80PCENT for CMU_CTRL */
<> 150:02e0a0aed4ec 2158 #define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 2159 #define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL /**< Mode 100PCENT for CMU_CTRL */
<> 150:02e0a0aed4ec 2160 #define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2) /**< Shifted mode 50PCENT for CMU_CTRL */
<> 150:02e0a0aed4ec 2161 #define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2) /**< Shifted mode 70PCENT for CMU_CTRL */
<> 150:02e0a0aed4ec 2162 #define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2) /**< Shifted mode 80PCENT for CMU_CTRL */
<> 150:02e0a0aed4ec 2163 #define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 2164 #define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2) /**< Shifted mode 100PCENT for CMU_CTRL */
<> 150:02e0a0aed4ec 2165 #define _CMU_CTRL_HFXOBUFCUR_SHIFT 5 /**< Shift value for CMU_HFXOBUFCUR */
<> 150:02e0a0aed4ec 2166 #define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL /**< Bit mask for CMU_HFXOBUFCUR */
<> 150:02e0a0aed4ec 2167 #define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 2168 #define _CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ 0x00000001UL /**< Mode BOOSTUPTO32MHZ for CMU_CTRL */
<> 150:02e0a0aed4ec 2169 #define _CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ 0x00000003UL /**< Mode BOOSTABOVE32MHZ for CMU_CTRL */
<> 150:02e0a0aed4ec 2170 #define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 2171 #define CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ << 5) /**< Shifted mode BOOSTUPTO32MHZ for CMU_CTRL */
<> 150:02e0a0aed4ec 2172 #define CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ << 5) /**< Shifted mode BOOSTABOVE32MHZ for CMU_CTRL */
<> 150:02e0a0aed4ec 2173 #define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7) /**< HFXO Glitch Detector Enable */
<> 150:02e0a0aed4ec 2174 #define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7 /**< Shift value for CMU_HFXOGLITCHDETEN */
<> 150:02e0a0aed4ec 2175 #define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL /**< Bit mask for CMU_HFXOGLITCHDETEN */
<> 150:02e0a0aed4ec 2176 #define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 2177 #define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 2178 #define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9 /**< Shift value for CMU_HFXOTIMEOUT */
<> 150:02e0a0aed4ec 2179 #define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL /**< Bit mask for CMU_HFXOTIMEOUT */
<> 150:02e0a0aed4ec 2180 #define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */
<> 150:02e0a0aed4ec 2181 #define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_CTRL */
<> 150:02e0a0aed4ec 2182 #define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_CTRL */
<> 150:02e0a0aed4ec 2183 #define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 2184 #define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL /**< Mode 16KCYCLES for CMU_CTRL */
<> 150:02e0a0aed4ec 2185 #define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9) /**< Shifted mode 8CYCLES for CMU_CTRL */
<> 150:02e0a0aed4ec 2186 #define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9) /**< Shifted mode 256CYCLES for CMU_CTRL */
<> 150:02e0a0aed4ec 2187 #define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9) /**< Shifted mode 1KCYCLES for CMU_CTRL */
<> 150:02e0a0aed4ec 2188 #define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 2189 #define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9) /**< Shifted mode 16KCYCLES for CMU_CTRL */
<> 150:02e0a0aed4ec 2190 #define _CMU_CTRL_LFXOMODE_SHIFT 11 /**< Shift value for CMU_LFXOMODE */
<> 150:02e0a0aed4ec 2191 #define _CMU_CTRL_LFXOMODE_MASK 0x1800UL /**< Bit mask for CMU_LFXOMODE */
<> 150:02e0a0aed4ec 2192 #define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 2193 #define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */
<> 150:02e0a0aed4ec 2194 #define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */
<> 150:02e0a0aed4ec 2195 #define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */
<> 150:02e0a0aed4ec 2196 #define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 2197 #define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11) /**< Shifted mode XTAL for CMU_CTRL */
<> 150:02e0a0aed4ec 2198 #define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11) /**< Shifted mode BUFEXTCLK for CMU_CTRL */
<> 150:02e0a0aed4ec 2199 #define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11) /**< Shifted mode DIGEXTCLK for CMU_CTRL */
<> 150:02e0a0aed4ec 2200 #define CMU_CTRL_LFXOBOOST (0x1UL << 13) /**< LFXO Start-up Boost Current */
<> 150:02e0a0aed4ec 2201 #define _CMU_CTRL_LFXOBOOST_SHIFT 13 /**< Shift value for CMU_LFXOBOOST */
<> 150:02e0a0aed4ec 2202 #define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL /**< Bit mask for CMU_LFXOBOOST */
<> 150:02e0a0aed4ec 2203 #define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL /**< Mode 70PCENT for CMU_CTRL */
<> 150:02e0a0aed4ec 2204 #define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 2205 #define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL /**< Mode 100PCENT for CMU_CTRL */
<> 150:02e0a0aed4ec 2206 #define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13) /**< Shifted mode 70PCENT for CMU_CTRL */
<> 150:02e0a0aed4ec 2207 #define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 2208 #define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13) /**< Shifted mode 100PCENT for CMU_CTRL */
<> 150:02e0a0aed4ec 2209 #define _CMU_CTRL_HFCLKDIV_SHIFT 14 /**< Shift value for CMU_HFCLKDIV */
<> 150:02e0a0aed4ec 2210 #define _CMU_CTRL_HFCLKDIV_MASK 0x1C000UL /**< Bit mask for CMU_HFCLKDIV */
<> 150:02e0a0aed4ec 2211 #define _CMU_CTRL_HFCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 2212 #define CMU_CTRL_HFCLKDIV_DEFAULT (_CMU_CTRL_HFCLKDIV_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 2213 #define CMU_CTRL_LFXOBUFCUR (0x1UL << 17) /**< LFXO Boost Buffer Current */
<> 150:02e0a0aed4ec 2214 #define _CMU_CTRL_LFXOBUFCUR_SHIFT 17 /**< Shift value for CMU_LFXOBUFCUR */
<> 150:02e0a0aed4ec 2215 #define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL /**< Bit mask for CMU_LFXOBUFCUR */
<> 150:02e0a0aed4ec 2216 #define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 2217 #define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 2218 #define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18 /**< Shift value for CMU_LFXOTIMEOUT */
<> 150:02e0a0aed4ec 2219 #define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL /**< Bit mask for CMU_LFXOTIMEOUT */
<> 150:02e0a0aed4ec 2220 #define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */
<> 150:02e0a0aed4ec 2221 #define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL /**< Mode 1KCYCLES for CMU_CTRL */
<> 150:02e0a0aed4ec 2222 #define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL /**< Mode 16KCYCLES for CMU_CTRL */
<> 150:02e0a0aed4ec 2223 #define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 2224 #define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL /**< Mode 32KCYCLES for CMU_CTRL */
<> 150:02e0a0aed4ec 2225 #define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18) /**< Shifted mode 8CYCLES for CMU_CTRL */
<> 150:02e0a0aed4ec 2226 #define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18) /**< Shifted mode 1KCYCLES for CMU_CTRL */
<> 150:02e0a0aed4ec 2227 #define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18) /**< Shifted mode 16KCYCLES for CMU_CTRL */
<> 150:02e0a0aed4ec 2228 #define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 2229 #define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18) /**< Shifted mode 32KCYCLES for CMU_CTRL */
<> 150:02e0a0aed4ec 2230 #define _CMU_CTRL_CLKOUTSEL0_SHIFT 20 /**< Shift value for CMU_CLKOUTSEL0 */
<> 150:02e0a0aed4ec 2231 #define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL /**< Bit mask for CMU_CLKOUTSEL0 */
<> 150:02e0a0aed4ec 2232 #define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 2233 #define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL /**< Mode HFRCO for CMU_CTRL */
<> 150:02e0a0aed4ec 2234 #define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL /**< Mode HFXO for CMU_CTRL */
<> 150:02e0a0aed4ec 2235 #define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL /**< Mode HFCLK2 for CMU_CTRL */
<> 150:02e0a0aed4ec 2236 #define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL /**< Mode HFCLK4 for CMU_CTRL */
<> 150:02e0a0aed4ec 2237 #define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL /**< Mode HFCLK8 for CMU_CTRL */
<> 150:02e0a0aed4ec 2238 #define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL /**< Mode HFCLK16 for CMU_CTRL */
<> 150:02e0a0aed4ec 2239 #define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL /**< Mode ULFRCO for CMU_CTRL */
<> 150:02e0a0aed4ec 2240 #define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL /**< Mode AUXHFRCO for CMU_CTRL */
<> 150:02e0a0aed4ec 2241 #define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 2242 #define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20) /**< Shifted mode HFRCO for CMU_CTRL */
<> 150:02e0a0aed4ec 2243 #define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20) /**< Shifted mode HFXO for CMU_CTRL */
<> 150:02e0a0aed4ec 2244 #define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20) /**< Shifted mode HFCLK2 for CMU_CTRL */
<> 150:02e0a0aed4ec 2245 #define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20) /**< Shifted mode HFCLK4 for CMU_CTRL */
<> 150:02e0a0aed4ec 2246 #define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20) /**< Shifted mode HFCLK8 for CMU_CTRL */
<> 150:02e0a0aed4ec 2247 #define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20) /**< Shifted mode HFCLK16 for CMU_CTRL */
<> 150:02e0a0aed4ec 2248 #define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_CTRL */
<> 150:02e0a0aed4ec 2249 #define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_CTRL */
<> 150:02e0a0aed4ec 2250 #define _CMU_CTRL_CLKOUTSEL1_SHIFT 23 /**< Shift value for CMU_CLKOUTSEL1 */
<> 150:02e0a0aed4ec 2251 #define _CMU_CTRL_CLKOUTSEL1_MASK 0x7800000UL /**< Bit mask for CMU_CLKOUTSEL1 */
<> 150:02e0a0aed4ec 2252 #define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 2253 #define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL /**< Mode LFRCO for CMU_CTRL */
<> 150:02e0a0aed4ec 2254 #define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL /**< Mode LFXO for CMU_CTRL */
<> 150:02e0a0aed4ec 2255 #define _CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL /**< Mode HFCLK for CMU_CTRL */
<> 150:02e0a0aed4ec 2256 #define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL /**< Mode LFXOQ for CMU_CTRL */
<> 150:02e0a0aed4ec 2257 #define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL /**< Mode HFXOQ for CMU_CTRL */
<> 150:02e0a0aed4ec 2258 #define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL /**< Mode LFRCOQ for CMU_CTRL */
<> 150:02e0a0aed4ec 2259 #define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL /**< Mode HFRCOQ for CMU_CTRL */
<> 150:02e0a0aed4ec 2260 #define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL /**< Mode AUXHFRCOQ for CMU_CTRL */
<> 150:02e0a0aed4ec 2261 #define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 2262 #define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23) /**< Shifted mode LFRCO for CMU_CTRL */
<> 150:02e0a0aed4ec 2263 #define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23) /**< Shifted mode LFXO for CMU_CTRL */
<> 150:02e0a0aed4ec 2264 #define CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23) /**< Shifted mode HFCLK for CMU_CTRL */
<> 150:02e0a0aed4ec 2265 #define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23) /**< Shifted mode LFXOQ for CMU_CTRL */
<> 150:02e0a0aed4ec 2266 #define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23) /**< Shifted mode HFXOQ for CMU_CTRL */
<> 150:02e0a0aed4ec 2267 #define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23) /**< Shifted mode LFRCOQ for CMU_CTRL */
<> 150:02e0a0aed4ec 2268 #define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23) /**< Shifted mode HFRCOQ for CMU_CTRL */
<> 150:02e0a0aed4ec 2269 #define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */
<> 150:02e0a0aed4ec 2270 #define CMU_CTRL_DBGCLK (0x1UL << 28) /**< Debug Clock */
<> 150:02e0a0aed4ec 2271 #define _CMU_CTRL_DBGCLK_SHIFT 28 /**< Shift value for CMU_DBGCLK */
<> 150:02e0a0aed4ec 2272 #define _CMU_CTRL_DBGCLK_MASK 0x10000000UL /**< Bit mask for CMU_DBGCLK */
<> 150:02e0a0aed4ec 2273 #define _CMU_CTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 2274 #define _CMU_CTRL_DBGCLK_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_CTRL */
<> 150:02e0a0aed4ec 2275 #define _CMU_CTRL_DBGCLK_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_CTRL */
<> 150:02e0a0aed4ec 2276 #define CMU_CTRL_DBGCLK_DEFAULT (_CMU_CTRL_DBGCLK_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 2277 #define CMU_CTRL_DBGCLK_AUXHFRCO (_CMU_CTRL_DBGCLK_AUXHFRCO << 28) /**< Shifted mode AUXHFRCO for CMU_CTRL */
<> 150:02e0a0aed4ec 2278 #define CMU_CTRL_DBGCLK_HFCLK (_CMU_CTRL_DBGCLK_HFCLK << 28) /**< Shifted mode HFCLK for CMU_CTRL */
<> 150:02e0a0aed4ec 2279 #define CMU_CTRL_HFLE (0x1UL << 30) /**< High-Frequency LE Interface */
<> 150:02e0a0aed4ec 2280 #define _CMU_CTRL_HFLE_SHIFT 30 /**< Shift value for CMU_HFLE */
<> 150:02e0a0aed4ec 2281 #define _CMU_CTRL_HFLE_MASK 0x40000000UL /**< Bit mask for CMU_HFLE */
<> 150:02e0a0aed4ec 2282 #define _CMU_CTRL_HFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 2283 #define CMU_CTRL_HFLE_DEFAULT (_CMU_CTRL_HFLE_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 150:02e0a0aed4ec 2284
<> 150:02e0a0aed4ec 2285 /* Bit fields for CMU HFCORECLKDIV */
<> 150:02e0a0aed4ec 2286 #define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 2287 #define _CMU_HFCORECLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 2288 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0 /**< Shift value for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 2289 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 2290 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 2291 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 2292 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 2293 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 2294 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 2295 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 2296 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 2297 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 2298 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 2299 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 2300 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 2301 #define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 2302 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 2303 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 2304 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 2305 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 2306 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 2307 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 2308 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 2309 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 2310 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 2311 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 2312 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV (0x1UL << 8) /**< Additional Division Factor For HFCORECLKLE */
<> 150:02e0a0aed4ec 2313 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT 8 /**< Shift value for CMU_HFCORECLKLEDIV */
<> 150:02e0a0aed4ec 2314 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK 0x100UL /**< Bit mask for CMU_HFCORECLKLEDIV */
<> 150:02e0a0aed4ec 2315 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 2316 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 2317 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 2318 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 2319 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8) /**< Shifted mode DIV2 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 2320 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8) /**< Shifted mode DIV4 for CMU_HFCORECLKDIV */
<> 150:02e0a0aed4ec 2321
<> 150:02e0a0aed4ec 2322 /* Bit fields for CMU HFPERCLKDIV */
<> 150:02e0a0aed4ec 2323 #define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL /**< Default value for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 2324 #define _CMU_HFPERCLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 2325 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0 /**< Shift value for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 2326 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 2327 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 2328 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 2329 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 2330 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 2331 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 2332 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 2333 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 2334 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 2335 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 2336 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 2337 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 2338 #define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 2339 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 2340 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 2341 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 2342 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 2343 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 2344 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 2345 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 2346 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 2347 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 2348 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 2349 #define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8) /**< HFPERCLK Enable */
<> 150:02e0a0aed4ec 2350 #define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8 /**< Shift value for CMU_HFPERCLKEN */
<> 150:02e0a0aed4ec 2351 #define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL /**< Bit mask for CMU_HFPERCLKEN */
<> 150:02e0a0aed4ec 2352 #define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 2353 #define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */
<> 150:02e0a0aed4ec 2354
<> 150:02e0a0aed4ec 2355 /* Bit fields for CMU HFRCOCTRL */
<> 150:02e0a0aed4ec 2356 #define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL /**< Default value for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 2357 #define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL /**< Mask for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 2358 #define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */
<> 150:02e0a0aed4ec 2359 #define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */
<> 150:02e0a0aed4ec 2360 #define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 2361 #define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 2362 #define _CMU_HFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */
<> 150:02e0a0aed4ec 2363 #define _CMU_HFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */
<> 150:02e0a0aed4ec 2364 #define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL /**< Mode 1MHZ for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 2365 #define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL /**< Mode 7MHZ for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 2366 #define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL /**< Mode 11MHZ for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 2367 #define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 2368 #define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL /**< Mode 14MHZ for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 2369 #define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL /**< Mode 21MHZ for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 2370 #define _CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL /**< Mode 28MHZ for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 2371 #define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 2372 #define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 2373 #define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 2374 #define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 2375 #define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 2376 #define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 2377 #define CMU_HFRCOCTRL_BAND_28MHZ (_CMU_HFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 2378 #define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12 /**< Shift value for CMU_SUDELAY */
<> 150:02e0a0aed4ec 2379 #define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL /**< Bit mask for CMU_SUDELAY */
<> 150:02e0a0aed4ec 2380 #define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 2381 #define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
<> 150:02e0a0aed4ec 2382
<> 150:02e0a0aed4ec 2383 /* Bit fields for CMU LFRCOCTRL */
<> 150:02e0a0aed4ec 2384 #define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL /**< Default value for CMU_LFRCOCTRL */
<> 150:02e0a0aed4ec 2385 #define _CMU_LFRCOCTRL_MASK 0x0000007FUL /**< Mask for CMU_LFRCOCTRL */
<> 150:02e0a0aed4ec 2386 #define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */
<> 150:02e0a0aed4ec 2387 #define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */
<> 150:02e0a0aed4ec 2388 #define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL /**< Mode DEFAULT for CMU_LFRCOCTRL */
<> 150:02e0a0aed4ec 2389 #define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */
<> 150:02e0a0aed4ec 2390
<> 150:02e0a0aed4ec 2391 /* Bit fields for CMU AUXHFRCOCTRL */
<> 150:02e0a0aed4ec 2392 #define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL /**< Default value for CMU_AUXHFRCOCTRL */
<> 150:02e0a0aed4ec 2393 #define _CMU_AUXHFRCOCTRL_MASK 0x000007FFUL /**< Mask for CMU_AUXHFRCOCTRL */
<> 150:02e0a0aed4ec 2394 #define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */
<> 150:02e0a0aed4ec 2395 #define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */
<> 150:02e0a0aed4ec 2396 #define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
<> 150:02e0a0aed4ec 2397 #define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
<> 150:02e0a0aed4ec 2398 #define _CMU_AUXHFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */
<> 150:02e0a0aed4ec 2399 #define _CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */
<> 150:02e0a0aed4ec 2400 #define _CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
<> 150:02e0a0aed4ec 2401 #define _CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL /**< Mode 14MHZ for CMU_AUXHFRCOCTRL */
<> 150:02e0a0aed4ec 2402 #define _CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL /**< Mode 11MHZ for CMU_AUXHFRCOCTRL */
<> 150:02e0a0aed4ec 2403 #define _CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL /**< Mode 7MHZ for CMU_AUXHFRCOCTRL */
<> 150:02e0a0aed4ec 2404 #define _CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL /**< Mode 1MHZ for CMU_AUXHFRCOCTRL */
<> 150:02e0a0aed4ec 2405 #define _CMU_AUXHFRCOCTRL_BAND_28MHZ 0x00000006UL /**< Mode 28MHZ for CMU_AUXHFRCOCTRL */
<> 150:02e0a0aed4ec 2406 #define _CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL /**< Mode 21MHZ for CMU_AUXHFRCOCTRL */
<> 150:02e0a0aed4ec 2407 #define CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
<> 150:02e0a0aed4ec 2408 #define CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_AUXHFRCOCTRL */
<> 150:02e0a0aed4ec 2409 #define CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_AUXHFRCOCTRL */
<> 150:02e0a0aed4ec 2410 #define CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_AUXHFRCOCTRL */
<> 150:02e0a0aed4ec 2411 #define CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_AUXHFRCOCTRL */
<> 150:02e0a0aed4ec 2412 #define CMU_AUXHFRCOCTRL_BAND_28MHZ (_CMU_AUXHFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_AUXHFRCOCTRL */
<> 150:02e0a0aed4ec 2413 #define CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_AUXHFRCOCTRL */
<> 150:02e0a0aed4ec 2414
<> 150:02e0a0aed4ec 2415 /* Bit fields for CMU CALCTRL */
<> 150:02e0a0aed4ec 2416 #define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */
<> 150:02e0a0aed4ec 2417 #define _CMU_CALCTRL_MASK 0x0000007FUL /**< Mask for CMU_CALCTRL */
<> 150:02e0a0aed4ec 2418 #define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */
<> 150:02e0a0aed4ec 2419 #define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */
<> 150:02e0a0aed4ec 2420 #define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */
<> 150:02e0a0aed4ec 2421 #define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 2422 #define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 2423 #define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 2424 #define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 2425 #define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 2426 #define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */
<> 150:02e0a0aed4ec 2427 #define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 2428 #define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 2429 #define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 2430 #define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 2431 #define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 2432 #define _CMU_CALCTRL_DOWNSEL_SHIFT 3 /**< Shift value for CMU_DOWNSEL */
<> 150:02e0a0aed4ec 2433 #define _CMU_CALCTRL_DOWNSEL_MASK 0x38UL /**< Bit mask for CMU_DOWNSEL */
<> 150:02e0a0aed4ec 2434 #define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */
<> 150:02e0a0aed4ec 2435 #define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */
<> 150:02e0a0aed4ec 2436 #define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 2437 #define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 2438 #define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 2439 #define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 2440 #define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 2441 #define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CALCTRL */
<> 150:02e0a0aed4ec 2442 #define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3) /**< Shifted mode HFCLK for CMU_CALCTRL */
<> 150:02e0a0aed4ec 2443 #define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 2444 #define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 2445 #define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3) /**< Shifted mode HFRCO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 2446 #define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3) /**< Shifted mode LFRCO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 2447 #define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */
<> 150:02e0a0aed4ec 2448 #define CMU_CALCTRL_CONT (0x1UL << 6) /**< Continuous Calibration */
<> 150:02e0a0aed4ec 2449 #define _CMU_CALCTRL_CONT_SHIFT 6 /**< Shift value for CMU_CONT */
<> 150:02e0a0aed4ec 2450 #define _CMU_CALCTRL_CONT_MASK 0x40UL /**< Bit mask for CMU_CONT */
<> 150:02e0a0aed4ec 2451 #define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */
<> 150:02e0a0aed4ec 2452 #define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CALCTRL */
<> 150:02e0a0aed4ec 2453
<> 150:02e0a0aed4ec 2454 /* Bit fields for CMU CALCNT */
<> 150:02e0a0aed4ec 2455 #define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */
<> 150:02e0a0aed4ec 2456 #define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */
<> 150:02e0a0aed4ec 2457 #define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */
<> 150:02e0a0aed4ec 2458 #define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */
<> 150:02e0a0aed4ec 2459 #define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */
<> 150:02e0a0aed4ec 2460 #define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */
<> 150:02e0a0aed4ec 2461
<> 150:02e0a0aed4ec 2462 /* Bit fields for CMU OSCENCMD */
<> 150:02e0a0aed4ec 2463 #define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 2464 #define _CMU_OSCENCMD_MASK 0x000003FFUL /**< Mask for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 2465 #define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */
<> 150:02e0a0aed4ec 2466 #define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */
<> 150:02e0a0aed4ec 2467 #define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */
<> 150:02e0a0aed4ec 2468 #define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 2469 #define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 2470 #define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */
<> 150:02e0a0aed4ec 2471 #define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */
<> 150:02e0a0aed4ec 2472 #define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */
<> 150:02e0a0aed4ec 2473 #define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 2474 #define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 2475 #define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */
<> 150:02e0a0aed4ec 2476 #define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */
<> 150:02e0a0aed4ec 2477 #define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */
<> 150:02e0a0aed4ec 2478 #define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 2479 #define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 2480 #define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */
<> 150:02e0a0aed4ec 2481 #define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */
<> 150:02e0a0aed4ec 2482 #define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */
<> 150:02e0a0aed4ec 2483 #define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 2484 #define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 2485 #define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */
<> 150:02e0a0aed4ec 2486 #define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */
<> 150:02e0a0aed4ec 2487 #define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */
<> 150:02e0a0aed4ec 2488 #define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 2489 #define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 2490 #define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */
<> 150:02e0a0aed4ec 2491 #define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */
<> 150:02e0a0aed4ec 2492 #define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */
<> 150:02e0a0aed4ec 2493 #define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 2494 #define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 2495 #define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */
<> 150:02e0a0aed4ec 2496 #define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */
<> 150:02e0a0aed4ec 2497 #define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */
<> 150:02e0a0aed4ec 2498 #define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 2499 #define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 2500 #define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */
<> 150:02e0a0aed4ec 2501 #define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */
<> 150:02e0a0aed4ec 2502 #define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */
<> 150:02e0a0aed4ec 2503 #define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 2504 #define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 2505 #define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */
<> 150:02e0a0aed4ec 2506 #define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */
<> 150:02e0a0aed4ec 2507 #define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */
<> 150:02e0a0aed4ec 2508 #define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 2509 #define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 2510 #define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */
<> 150:02e0a0aed4ec 2511 #define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */
<> 150:02e0a0aed4ec 2512 #define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */
<> 150:02e0a0aed4ec 2513 #define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 2514 #define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
<> 150:02e0a0aed4ec 2515
<> 150:02e0a0aed4ec 2516 /* Bit fields for CMU CMD */
<> 150:02e0a0aed4ec 2517 #define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */
<> 150:02e0a0aed4ec 2518 #define _CMU_CMD_MASK 0x000000FFUL /**< Mask for CMU_CMD */
<> 150:02e0a0aed4ec 2519 #define _CMU_CMD_HFCLKSEL_SHIFT 0 /**< Shift value for CMU_HFCLKSEL */
<> 150:02e0a0aed4ec 2520 #define _CMU_CMD_HFCLKSEL_MASK 0x7UL /**< Bit mask for CMU_HFCLKSEL */
<> 150:02e0a0aed4ec 2521 #define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */
<> 150:02e0a0aed4ec 2522 #define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_CMD */
<> 150:02e0a0aed4ec 2523 #define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CMD */
<> 150:02e0a0aed4ec 2524 #define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */
<> 150:02e0a0aed4ec 2525 #define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CMD */
<> 150:02e0a0aed4ec 2526 #define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */
<> 150:02e0a0aed4ec 2527 #define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CMD */
<> 150:02e0a0aed4ec 2528 #define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CMD */
<> 150:02e0a0aed4ec 2529 #define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CMD */
<> 150:02e0a0aed4ec 2530 #define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CMD */
<> 150:02e0a0aed4ec 2531 #define CMU_CMD_CALSTART (0x1UL << 3) /**< Calibration Start */
<> 150:02e0a0aed4ec 2532 #define _CMU_CMD_CALSTART_SHIFT 3 /**< Shift value for CMU_CALSTART */
<> 150:02e0a0aed4ec 2533 #define _CMU_CMD_CALSTART_MASK 0x8UL /**< Bit mask for CMU_CALSTART */
<> 150:02e0a0aed4ec 2534 #define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */
<> 150:02e0a0aed4ec 2535 #define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CMD */
<> 150:02e0a0aed4ec 2536 #define CMU_CMD_CALSTOP (0x1UL << 4) /**< Calibration Stop */
<> 150:02e0a0aed4ec 2537 #define _CMU_CMD_CALSTOP_SHIFT 4 /**< Shift value for CMU_CALSTOP */
<> 150:02e0a0aed4ec 2538 #define _CMU_CMD_CALSTOP_MASK 0x10UL /**< Bit mask for CMU_CALSTOP */
<> 150:02e0a0aed4ec 2539 #define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */
<> 150:02e0a0aed4ec 2540 #define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */
<> 150:02e0a0aed4ec 2541 #define _CMU_CMD_USBCCLKSEL_SHIFT 5 /**< Shift value for CMU_USBCCLKSEL */
<> 150:02e0a0aed4ec 2542 #define _CMU_CMD_USBCCLKSEL_MASK 0xE0UL /**< Bit mask for CMU_USBCCLKSEL */
<> 150:02e0a0aed4ec 2543 #define _CMU_CMD_USBCCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */
<> 150:02e0a0aed4ec 2544 #define _CMU_CMD_USBCCLKSEL_HFCLKNODIV 0x00000001UL /**< Mode HFCLKNODIV for CMU_CMD */
<> 150:02e0a0aed4ec 2545 #define _CMU_CMD_USBCCLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CMD */
<> 150:02e0a0aed4ec 2546 #define _CMU_CMD_USBCCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */
<> 150:02e0a0aed4ec 2547 #define CMU_CMD_USBCCLKSEL_DEFAULT (_CMU_CMD_USBCCLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CMD */
<> 150:02e0a0aed4ec 2548 #define CMU_CMD_USBCCLKSEL_HFCLKNODIV (_CMU_CMD_USBCCLKSEL_HFCLKNODIV << 5) /**< Shifted mode HFCLKNODIV for CMU_CMD */
<> 150:02e0a0aed4ec 2549 #define CMU_CMD_USBCCLKSEL_LFXO (_CMU_CMD_USBCCLKSEL_LFXO << 5) /**< Shifted mode LFXO for CMU_CMD */
<> 150:02e0a0aed4ec 2550 #define CMU_CMD_USBCCLKSEL_LFRCO (_CMU_CMD_USBCCLKSEL_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CMD */
<> 150:02e0a0aed4ec 2551
<> 150:02e0a0aed4ec 2552 /* Bit fields for CMU LFCLKSEL */
<> 150:02e0a0aed4ec 2553 #define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL /**< Default value for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 2554 #define _CMU_LFCLKSEL_MASK 0x0011000FUL /**< Mask for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 2555 #define _CMU_LFCLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */
<> 150:02e0a0aed4ec 2556 #define _CMU_LFCLKSEL_LFA_MASK 0x3UL /**< Bit mask for CMU_LFA */
<> 150:02e0a0aed4ec 2557 #define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 2558 #define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 2559 #define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 2560 #define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 2561 #define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 2562 #define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 2563 #define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 2564 #define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 2565 #define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 2566 #define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 2567 #define _CMU_LFCLKSEL_LFB_SHIFT 2 /**< Shift value for CMU_LFB */
<> 150:02e0a0aed4ec 2568 #define _CMU_LFCLKSEL_LFB_MASK 0xCUL /**< Bit mask for CMU_LFB */
<> 150:02e0a0aed4ec 2569 #define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 2570 #define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 2571 #define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 2572 #define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 2573 #define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 2574 #define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2) /**< Shifted mode DISABLED for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 2575 #define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 2576 #define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2) /**< Shifted mode LFRCO for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 2577 #define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2) /**< Shifted mode LFXO for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 2578 #define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 2579 #define CMU_LFCLKSEL_LFAE (0x1UL << 16) /**< Clock Select for LFA Extended */
<> 150:02e0a0aed4ec 2580 #define _CMU_LFCLKSEL_LFAE_SHIFT 16 /**< Shift value for CMU_LFAE */
<> 150:02e0a0aed4ec 2581 #define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL /**< Bit mask for CMU_LFAE */
<> 150:02e0a0aed4ec 2582 #define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 2583 #define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 2584 #define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 2585 #define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 2586 #define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16) /**< Shifted mode DISABLED for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 2587 #define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 2588 #define CMU_LFCLKSEL_LFBE (0x1UL << 20) /**< Clock Select for LFB Extended */
<> 150:02e0a0aed4ec 2589 #define _CMU_LFCLKSEL_LFBE_SHIFT 20 /**< Shift value for CMU_LFBE */
<> 150:02e0a0aed4ec 2590 #define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL /**< Bit mask for CMU_LFBE */
<> 150:02e0a0aed4ec 2591 #define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 2592 #define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 2593 #define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 2594 #define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 2595 #define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20) /**< Shifted mode DISABLED for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 2596 #define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */
<> 150:02e0a0aed4ec 2597
<> 150:02e0a0aed4ec 2598 /* Bit fields for CMU STATUS */
<> 150:02e0a0aed4ec 2599 #define _CMU_STATUS_RESETVALUE 0x00000403UL /**< Default value for CMU_STATUS */
<> 150:02e0a0aed4ec 2600 #define _CMU_STATUS_MASK 0x0003FFFFUL /**< Mask for CMU_STATUS */
<> 150:02e0a0aed4ec 2601 #define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */
<> 150:02e0a0aed4ec 2602 #define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */
<> 150:02e0a0aed4ec 2603 #define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */
<> 150:02e0a0aed4ec 2604 #define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 2605 #define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 2606 #define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */
<> 150:02e0a0aed4ec 2607 #define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */
<> 150:02e0a0aed4ec 2608 #define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */
<> 150:02e0a0aed4ec 2609 #define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 2610 #define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 2611 #define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */
<> 150:02e0a0aed4ec 2612 #define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */
<> 150:02e0a0aed4ec 2613 #define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */
<> 150:02e0a0aed4ec 2614 #define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 2615 #define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 2616 #define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */
<> 150:02e0a0aed4ec 2617 #define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */
<> 150:02e0a0aed4ec 2618 #define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */
<> 150:02e0a0aed4ec 2619 #define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 2620 #define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 2621 #define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */
<> 150:02e0a0aed4ec 2622 #define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */
<> 150:02e0a0aed4ec 2623 #define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */
<> 150:02e0a0aed4ec 2624 #define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 2625 #define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 2626 #define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */
<> 150:02e0a0aed4ec 2627 #define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */
<> 150:02e0a0aed4ec 2628 #define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */
<> 150:02e0a0aed4ec 2629 #define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 2630 #define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 2631 #define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */
<> 150:02e0a0aed4ec 2632 #define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */
<> 150:02e0a0aed4ec 2633 #define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */
<> 150:02e0a0aed4ec 2634 #define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 2635 #define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 2636 #define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */
<> 150:02e0a0aed4ec 2637 #define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */
<> 150:02e0a0aed4ec 2638 #define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */
<> 150:02e0a0aed4ec 2639 #define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 2640 #define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 2641 #define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */
<> 150:02e0a0aed4ec 2642 #define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */
<> 150:02e0a0aed4ec 2643 #define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */
<> 150:02e0a0aed4ec 2644 #define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 2645 #define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 2646 #define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */
<> 150:02e0a0aed4ec 2647 #define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */
<> 150:02e0a0aed4ec 2648 #define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */
<> 150:02e0a0aed4ec 2649 #define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 2650 #define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 2651 #define CMU_STATUS_HFRCOSEL (0x1UL << 10) /**< HFRCO Selected */
<> 150:02e0a0aed4ec 2652 #define _CMU_STATUS_HFRCOSEL_SHIFT 10 /**< Shift value for CMU_HFRCOSEL */
<> 150:02e0a0aed4ec 2653 #define _CMU_STATUS_HFRCOSEL_MASK 0x400UL /**< Bit mask for CMU_HFRCOSEL */
<> 150:02e0a0aed4ec 2654 #define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 2655 #define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 2656 #define CMU_STATUS_HFXOSEL (0x1UL << 11) /**< HFXO Selected */
<> 150:02e0a0aed4ec 2657 #define _CMU_STATUS_HFXOSEL_SHIFT 11 /**< Shift value for CMU_HFXOSEL */
<> 150:02e0a0aed4ec 2658 #define _CMU_STATUS_HFXOSEL_MASK 0x800UL /**< Bit mask for CMU_HFXOSEL */
<> 150:02e0a0aed4ec 2659 #define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 2660 #define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 2661 #define CMU_STATUS_LFRCOSEL (0x1UL << 12) /**< LFRCO Selected */
<> 150:02e0a0aed4ec 2662 #define _CMU_STATUS_LFRCOSEL_SHIFT 12 /**< Shift value for CMU_LFRCOSEL */
<> 150:02e0a0aed4ec 2663 #define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL /**< Bit mask for CMU_LFRCOSEL */
<> 150:02e0a0aed4ec 2664 #define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 2665 #define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 2666 #define CMU_STATUS_LFXOSEL (0x1UL << 13) /**< LFXO Selected */
<> 150:02e0a0aed4ec 2667 #define _CMU_STATUS_LFXOSEL_SHIFT 13 /**< Shift value for CMU_LFXOSEL */
<> 150:02e0a0aed4ec 2668 #define _CMU_STATUS_LFXOSEL_MASK 0x2000UL /**< Bit mask for CMU_LFXOSEL */
<> 150:02e0a0aed4ec 2669 #define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 2670 #define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 2671 #define CMU_STATUS_CALBSY (0x1UL << 14) /**< Calibration Busy */
<> 150:02e0a0aed4ec 2672 #define _CMU_STATUS_CALBSY_SHIFT 14 /**< Shift value for CMU_CALBSY */
<> 150:02e0a0aed4ec 2673 #define _CMU_STATUS_CALBSY_MASK 0x4000UL /**< Bit mask for CMU_CALBSY */
<> 150:02e0a0aed4ec 2674 #define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 2675 #define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 2676 #define CMU_STATUS_USBCHFCLKSEL (0x1UL << 15) /**< USBC HFCLK Selected */
<> 150:02e0a0aed4ec 2677 #define _CMU_STATUS_USBCHFCLKSEL_SHIFT 15 /**< Shift value for CMU_USBCHFCLKSEL */
<> 150:02e0a0aed4ec 2678 #define _CMU_STATUS_USBCHFCLKSEL_MASK 0x8000UL /**< Bit mask for CMU_USBCHFCLKSEL */
<> 150:02e0a0aed4ec 2679 #define _CMU_STATUS_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 2680 #define CMU_STATUS_USBCHFCLKSEL_DEFAULT (_CMU_STATUS_USBCHFCLKSEL_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 2681 #define CMU_STATUS_USBCLFXOSEL (0x1UL << 16) /**< USBC LFXO Selected */
<> 150:02e0a0aed4ec 2682 #define _CMU_STATUS_USBCLFXOSEL_SHIFT 16 /**< Shift value for CMU_USBCLFXOSEL */
<> 150:02e0a0aed4ec 2683 #define _CMU_STATUS_USBCLFXOSEL_MASK 0x10000UL /**< Bit mask for CMU_USBCLFXOSEL */
<> 150:02e0a0aed4ec 2684 #define _CMU_STATUS_USBCLFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 2685 #define CMU_STATUS_USBCLFXOSEL_DEFAULT (_CMU_STATUS_USBCLFXOSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 2686 #define CMU_STATUS_USBCLFRCOSEL (0x1UL << 17) /**< USBC LFRCO Selected */
<> 150:02e0a0aed4ec 2687 #define _CMU_STATUS_USBCLFRCOSEL_SHIFT 17 /**< Shift value for CMU_USBCLFRCOSEL */
<> 150:02e0a0aed4ec 2688 #define _CMU_STATUS_USBCLFRCOSEL_MASK 0x20000UL /**< Bit mask for CMU_USBCLFRCOSEL */
<> 150:02e0a0aed4ec 2689 #define _CMU_STATUS_USBCLFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 2690 #define CMU_STATUS_USBCLFRCOSEL_DEFAULT (_CMU_STATUS_USBCLFRCOSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 150:02e0a0aed4ec 2691
<> 150:02e0a0aed4ec 2692 /* Bit fields for CMU IF */
<> 150:02e0a0aed4ec 2693 #define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */
<> 150:02e0a0aed4ec 2694 #define _CMU_IF_MASK 0x000000FFUL /**< Mask for CMU_IF */
<> 150:02e0a0aed4ec 2695 #define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */
<> 150:02e0a0aed4ec 2696 #define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */
<> 150:02e0a0aed4ec 2697 #define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */
<> 150:02e0a0aed4ec 2698 #define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */
<> 150:02e0a0aed4ec 2699 #define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */
<> 150:02e0a0aed4ec 2700 #define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */
<> 150:02e0a0aed4ec 2701 #define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */
<> 150:02e0a0aed4ec 2702 #define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */
<> 150:02e0a0aed4ec 2703 #define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
<> 150:02e0a0aed4ec 2704 #define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */
<> 150:02e0a0aed4ec 2705 #define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */
<> 150:02e0a0aed4ec 2706 #define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */
<> 150:02e0a0aed4ec 2707 #define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */
<> 150:02e0a0aed4ec 2708 #define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
<> 150:02e0a0aed4ec 2709 #define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */
<> 150:02e0a0aed4ec 2710 #define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */
<> 150:02e0a0aed4ec 2711 #define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */
<> 150:02e0a0aed4ec 2712 #define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */
<> 150:02e0a0aed4ec 2713 #define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
<> 150:02e0a0aed4ec 2714 #define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */
<> 150:02e0a0aed4ec 2715 #define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */
<> 150:02e0a0aed4ec 2716 #define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */
<> 150:02e0a0aed4ec 2717 #define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */
<> 150:02e0a0aed4ec 2718 #define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
<> 150:02e0a0aed4ec 2719 #define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */
<> 150:02e0a0aed4ec 2720 #define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */
<> 150:02e0a0aed4ec 2721 #define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */
<> 150:02e0a0aed4ec 2722 #define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */
<> 150:02e0a0aed4ec 2723 #define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
<> 150:02e0a0aed4ec 2724 #define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */
<> 150:02e0a0aed4ec 2725 #define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */
<> 150:02e0a0aed4ec 2726 #define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */
<> 150:02e0a0aed4ec 2727 #define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */
<> 150:02e0a0aed4ec 2728 #define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
<> 150:02e0a0aed4ec 2729 #define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */
<> 150:02e0a0aed4ec 2730 #define CMU_IF_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Flag */
<> 150:02e0a0aed4ec 2731 #define _CMU_IF_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */
<> 150:02e0a0aed4ec 2732 #define _CMU_IF_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */
<> 150:02e0a0aed4ec 2733 #define _CMU_IF_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
<> 150:02e0a0aed4ec 2734 #define CMU_IF_USBCHFCLKSEL_DEFAULT (_CMU_IF_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IF */
<> 150:02e0a0aed4ec 2735
<> 150:02e0a0aed4ec 2736 /* Bit fields for CMU IFS */
<> 150:02e0a0aed4ec 2737 #define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */
<> 150:02e0a0aed4ec 2738 #define _CMU_IFS_MASK 0x000000FFUL /**< Mask for CMU_IFS */
<> 150:02e0a0aed4ec 2739 #define CMU_IFS_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Set */
<> 150:02e0a0aed4ec 2740 #define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */
<> 150:02e0a0aed4ec 2741 #define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */
<> 150:02e0a0aed4ec 2742 #define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
<> 150:02e0a0aed4ec 2743 #define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */
<> 150:02e0a0aed4ec 2744 #define CMU_IFS_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Set */
<> 150:02e0a0aed4ec 2745 #define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */
<> 150:02e0a0aed4ec 2746 #define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */
<> 150:02e0a0aed4ec 2747 #define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
<> 150:02e0a0aed4ec 2748 #define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */
<> 150:02e0a0aed4ec 2749 #define CMU_IFS_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Set */
<> 150:02e0a0aed4ec 2750 #define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */
<> 150:02e0a0aed4ec 2751 #define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */
<> 150:02e0a0aed4ec 2752 #define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
<> 150:02e0a0aed4ec 2753 #define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */
<> 150:02e0a0aed4ec 2754 #define CMU_IFS_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Set */
<> 150:02e0a0aed4ec 2755 #define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */
<> 150:02e0a0aed4ec 2756 #define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */
<> 150:02e0a0aed4ec 2757 #define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
<> 150:02e0a0aed4ec 2758 #define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */
<> 150:02e0a0aed4ec 2759 #define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Set */
<> 150:02e0a0aed4ec 2760 #define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */
<> 150:02e0a0aed4ec 2761 #define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */
<> 150:02e0a0aed4ec 2762 #define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
<> 150:02e0a0aed4ec 2763 #define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */
<> 150:02e0a0aed4ec 2764 #define CMU_IFS_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Set */
<> 150:02e0a0aed4ec 2765 #define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */
<> 150:02e0a0aed4ec 2766 #define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */
<> 150:02e0a0aed4ec 2767 #define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
<> 150:02e0a0aed4ec 2768 #define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */
<> 150:02e0a0aed4ec 2769 #define CMU_IFS_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Set */
<> 150:02e0a0aed4ec 2770 #define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */
<> 150:02e0a0aed4ec 2771 #define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */
<> 150:02e0a0aed4ec 2772 #define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
<> 150:02e0a0aed4ec 2773 #define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */
<> 150:02e0a0aed4ec 2774 #define CMU_IFS_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Flag Set */
<> 150:02e0a0aed4ec 2775 #define _CMU_IFS_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */
<> 150:02e0a0aed4ec 2776 #define _CMU_IFS_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */
<> 150:02e0a0aed4ec 2777 #define _CMU_IFS_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
<> 150:02e0a0aed4ec 2778 #define CMU_IFS_USBCHFCLKSEL_DEFAULT (_CMU_IFS_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFS */
<> 150:02e0a0aed4ec 2779
<> 150:02e0a0aed4ec 2780 /* Bit fields for CMU IFC */
<> 150:02e0a0aed4ec 2781 #define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */
<> 150:02e0a0aed4ec 2782 #define _CMU_IFC_MASK 0x000000FFUL /**< Mask for CMU_IFC */
<> 150:02e0a0aed4ec 2783 #define CMU_IFC_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Clear */
<> 150:02e0a0aed4ec 2784 #define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */
<> 150:02e0a0aed4ec 2785 #define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */
<> 150:02e0a0aed4ec 2786 #define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
<> 150:02e0a0aed4ec 2787 #define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */
<> 150:02e0a0aed4ec 2788 #define CMU_IFC_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Clear */
<> 150:02e0a0aed4ec 2789 #define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */
<> 150:02e0a0aed4ec 2790 #define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */
<> 150:02e0a0aed4ec 2791 #define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
<> 150:02e0a0aed4ec 2792 #define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */
<> 150:02e0a0aed4ec 2793 #define CMU_IFC_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Clear */
<> 150:02e0a0aed4ec 2794 #define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */
<> 150:02e0a0aed4ec 2795 #define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */
<> 150:02e0a0aed4ec 2796 #define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
<> 150:02e0a0aed4ec 2797 #define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */
<> 150:02e0a0aed4ec 2798 #define CMU_IFC_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Clear */
<> 150:02e0a0aed4ec 2799 #define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */
<> 150:02e0a0aed4ec 2800 #define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */
<> 150:02e0a0aed4ec 2801 #define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
<> 150:02e0a0aed4ec 2802 #define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */
<> 150:02e0a0aed4ec 2803 #define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Clear */
<> 150:02e0a0aed4ec 2804 #define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */
<> 150:02e0a0aed4ec 2805 #define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */
<> 150:02e0a0aed4ec 2806 #define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
<> 150:02e0a0aed4ec 2807 #define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */
<> 150:02e0a0aed4ec 2808 #define CMU_IFC_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Clear */
<> 150:02e0a0aed4ec 2809 #define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */
<> 150:02e0a0aed4ec 2810 #define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */
<> 150:02e0a0aed4ec 2811 #define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
<> 150:02e0a0aed4ec 2812 #define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */
<> 150:02e0a0aed4ec 2813 #define CMU_IFC_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Clear */
<> 150:02e0a0aed4ec 2814 #define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */
<> 150:02e0a0aed4ec 2815 #define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */
<> 150:02e0a0aed4ec 2816 #define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
<> 150:02e0a0aed4ec 2817 #define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */
<> 150:02e0a0aed4ec 2818 #define CMU_IFC_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Flag Clear */
<> 150:02e0a0aed4ec 2819 #define _CMU_IFC_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */
<> 150:02e0a0aed4ec 2820 #define _CMU_IFC_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */
<> 150:02e0a0aed4ec 2821 #define _CMU_IFC_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
<> 150:02e0a0aed4ec 2822 #define CMU_IFC_USBCHFCLKSEL_DEFAULT (_CMU_IFC_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFC */
<> 150:02e0a0aed4ec 2823
<> 150:02e0a0aed4ec 2824 /* Bit fields for CMU IEN */
<> 150:02e0a0aed4ec 2825 #define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */
<> 150:02e0a0aed4ec 2826 #define _CMU_IEN_MASK 0x000000FFUL /**< Mask for CMU_IEN */
<> 150:02e0a0aed4ec 2827 #define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Enable */
<> 150:02e0a0aed4ec 2828 #define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */
<> 150:02e0a0aed4ec 2829 #define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */
<> 150:02e0a0aed4ec 2830 #define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
<> 150:02e0a0aed4ec 2831 #define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */
<> 150:02e0a0aed4ec 2832 #define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Enable */
<> 150:02e0a0aed4ec 2833 #define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */
<> 150:02e0a0aed4ec 2834 #define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */
<> 150:02e0a0aed4ec 2835 #define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
<> 150:02e0a0aed4ec 2836 #define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */
<> 150:02e0a0aed4ec 2837 #define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Enable */
<> 150:02e0a0aed4ec 2838 #define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */
<> 150:02e0a0aed4ec 2839 #define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */
<> 150:02e0a0aed4ec 2840 #define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
<> 150:02e0a0aed4ec 2841 #define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */
<> 150:02e0a0aed4ec 2842 #define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Enable */
<> 150:02e0a0aed4ec 2843 #define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */
<> 150:02e0a0aed4ec 2844 #define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */
<> 150:02e0a0aed4ec 2845 #define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
<> 150:02e0a0aed4ec 2846 #define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */
<> 150:02e0a0aed4ec 2847 #define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Enable */
<> 150:02e0a0aed4ec 2848 #define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */
<> 150:02e0a0aed4ec 2849 #define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */
<> 150:02e0a0aed4ec 2850 #define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
<> 150:02e0a0aed4ec 2851 #define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */
<> 150:02e0a0aed4ec 2852 #define CMU_IEN_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Enable */
<> 150:02e0a0aed4ec 2853 #define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */
<> 150:02e0a0aed4ec 2854 #define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */
<> 150:02e0a0aed4ec 2855 #define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
<> 150:02e0a0aed4ec 2856 #define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */
<> 150:02e0a0aed4ec 2857 #define CMU_IEN_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Enable */
<> 150:02e0a0aed4ec 2858 #define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */
<> 150:02e0a0aed4ec 2859 #define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */
<> 150:02e0a0aed4ec 2860 #define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
<> 150:02e0a0aed4ec 2861 #define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */
<> 150:02e0a0aed4ec 2862 #define CMU_IEN_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Enable */
<> 150:02e0a0aed4ec 2863 #define _CMU_IEN_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */
<> 150:02e0a0aed4ec 2864 #define _CMU_IEN_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */
<> 150:02e0a0aed4ec 2865 #define _CMU_IEN_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
<> 150:02e0a0aed4ec 2866 #define CMU_IEN_USBCHFCLKSEL_DEFAULT (_CMU_IEN_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IEN */
<> 150:02e0a0aed4ec 2867
<> 150:02e0a0aed4ec 2868 /* Bit fields for CMU HFCORECLKEN0 */
<> 150:02e0a0aed4ec 2869 #define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKEN0 */
<> 150:02e0a0aed4ec 2870 #define _CMU_HFCORECLKEN0_MASK 0x0000001FUL /**< Mask for CMU_HFCORECLKEN0 */
<> 150:02e0a0aed4ec 2871 #define CMU_HFCORECLKEN0_DMA (0x1UL << 0) /**< Direct Memory Access Controller Clock Enable */
<> 150:02e0a0aed4ec 2872 #define _CMU_HFCORECLKEN0_DMA_SHIFT 0 /**< Shift value for CMU_DMA */
<> 150:02e0a0aed4ec 2873 #define _CMU_HFCORECLKEN0_DMA_MASK 0x1UL /**< Bit mask for CMU_DMA */
<> 150:02e0a0aed4ec 2874 #define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */
<> 150:02e0a0aed4ec 2875 #define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */
<> 150:02e0a0aed4ec 2876 #define CMU_HFCORECLKEN0_AES (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */
<> 150:02e0a0aed4ec 2877 #define _CMU_HFCORECLKEN0_AES_SHIFT 1 /**< Shift value for CMU_AES */
<> 150:02e0a0aed4ec 2878 #define _CMU_HFCORECLKEN0_AES_MASK 0x2UL /**< Bit mask for CMU_AES */
<> 150:02e0a0aed4ec 2879 #define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */
<> 150:02e0a0aed4ec 2880 #define CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */
<> 150:02e0a0aed4ec 2881 #define CMU_HFCORECLKEN0_USBC (0x1UL << 2) /**< Universal Serial Bus Interface Core Clock Enable */
<> 150:02e0a0aed4ec 2882 #define _CMU_HFCORECLKEN0_USBC_SHIFT 2 /**< Shift value for CMU_USBC */
<> 150:02e0a0aed4ec 2883 #define _CMU_HFCORECLKEN0_USBC_MASK 0x4UL /**< Bit mask for CMU_USBC */
<> 150:02e0a0aed4ec 2884 #define _CMU_HFCORECLKEN0_USBC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */
<> 150:02e0a0aed4ec 2885 #define CMU_HFCORECLKEN0_USBC_DEFAULT (_CMU_HFCORECLKEN0_USBC_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */
<> 150:02e0a0aed4ec 2886 #define CMU_HFCORECLKEN0_USB (0x1UL << 3) /**< Universal Serial Bus Interface Clock Enable */
<> 150:02e0a0aed4ec 2887 #define _CMU_HFCORECLKEN0_USB_SHIFT 3 /**< Shift value for CMU_USB */
<> 150:02e0a0aed4ec 2888 #define _CMU_HFCORECLKEN0_USB_MASK 0x8UL /**< Bit mask for CMU_USB */
<> 150:02e0a0aed4ec 2889 #define _CMU_HFCORECLKEN0_USB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */
<> 150:02e0a0aed4ec 2890 #define CMU_HFCORECLKEN0_USB_DEFAULT (_CMU_HFCORECLKEN0_USB_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */
<> 150:02e0a0aed4ec 2891 #define CMU_HFCORECLKEN0_LE (0x1UL << 4) /**< Low Energy Peripheral Interface Clock Enable */
<> 150:02e0a0aed4ec 2892 #define _CMU_HFCORECLKEN0_LE_SHIFT 4 /**< Shift value for CMU_LE */
<> 150:02e0a0aed4ec 2893 #define _CMU_HFCORECLKEN0_LE_MASK 0x10UL /**< Bit mask for CMU_LE */
<> 150:02e0a0aed4ec 2894 #define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */
<> 150:02e0a0aed4ec 2895 #define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */
<> 150:02e0a0aed4ec 2896
<> 150:02e0a0aed4ec 2897 /* Bit fields for CMU HFPERCLKEN0 */
<> 150:02e0a0aed4ec 2898 #define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 2899 #define _CMU_HFPERCLKEN0_MASK 0x0003FFE7UL /**< Mask for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 2900 #define CMU_HFPERCLKEN0_USART0 (0x1UL << 0) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */
<> 150:02e0a0aed4ec 2901 #define _CMU_HFPERCLKEN0_USART0_SHIFT 0 /**< Shift value for CMU_USART0 */
<> 150:02e0a0aed4ec 2902 #define _CMU_HFPERCLKEN0_USART0_MASK 0x1UL /**< Bit mask for CMU_USART0 */
<> 150:02e0a0aed4ec 2903 #define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 2904 #define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 2905 #define CMU_HFPERCLKEN0_USART1 (0x1UL << 1) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */
<> 150:02e0a0aed4ec 2906 #define _CMU_HFPERCLKEN0_USART1_SHIFT 1 /**< Shift value for CMU_USART1 */
<> 150:02e0a0aed4ec 2907 #define _CMU_HFPERCLKEN0_USART1_MASK 0x2UL /**< Bit mask for CMU_USART1 */
<> 150:02e0a0aed4ec 2908 #define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 2909 #define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 2910 #define CMU_HFPERCLKEN0_USART2 (0x1UL << 2) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */
<> 150:02e0a0aed4ec 2911 #define _CMU_HFPERCLKEN0_USART2_SHIFT 2 /**< Shift value for CMU_USART2 */
<> 150:02e0a0aed4ec 2912 #define _CMU_HFPERCLKEN0_USART2_MASK 0x4UL /**< Bit mask for CMU_USART2 */
<> 150:02e0a0aed4ec 2913 #define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 2914 #define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 2915 #define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 5) /**< Timer 0 Clock Enable */
<> 150:02e0a0aed4ec 2916 #define _CMU_HFPERCLKEN0_TIMER0_SHIFT 5 /**< Shift value for CMU_TIMER0 */
<> 150:02e0a0aed4ec 2917 #define _CMU_HFPERCLKEN0_TIMER0_MASK 0x20UL /**< Bit mask for CMU_TIMER0 */
<> 150:02e0a0aed4ec 2918 #define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 2919 #define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 2920 #define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 6) /**< Timer 1 Clock Enable */
<> 150:02e0a0aed4ec 2921 #define _CMU_HFPERCLKEN0_TIMER1_SHIFT 6 /**< Shift value for CMU_TIMER1 */
<> 150:02e0a0aed4ec 2922 #define _CMU_HFPERCLKEN0_TIMER1_MASK 0x40UL /**< Bit mask for CMU_TIMER1 */
<> 150:02e0a0aed4ec 2923 #define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 2924 #define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 2925 #define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 7) /**< Timer 2 Clock Enable */
<> 150:02e0a0aed4ec 2926 #define _CMU_HFPERCLKEN0_TIMER2_SHIFT 7 /**< Shift value for CMU_TIMER2 */
<> 150:02e0a0aed4ec 2927 #define _CMU_HFPERCLKEN0_TIMER2_MASK 0x80UL /**< Bit mask for CMU_TIMER2 */
<> 150:02e0a0aed4ec 2928 #define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 2929 #define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 2930 #define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 8) /**< Timer 3 Clock Enable */
<> 150:02e0a0aed4ec 2931 #define _CMU_HFPERCLKEN0_TIMER3_SHIFT 8 /**< Shift value for CMU_TIMER3 */
<> 150:02e0a0aed4ec 2932 #define _CMU_HFPERCLKEN0_TIMER3_MASK 0x100UL /**< Bit mask for CMU_TIMER3 */
<> 150:02e0a0aed4ec 2933 #define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 2934 #define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 2935 #define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 9) /**< Analog Comparator 0 Clock Enable */
<> 150:02e0a0aed4ec 2936 #define _CMU_HFPERCLKEN0_ACMP0_SHIFT 9 /**< Shift value for CMU_ACMP0 */
<> 150:02e0a0aed4ec 2937 #define _CMU_HFPERCLKEN0_ACMP0_MASK 0x200UL /**< Bit mask for CMU_ACMP0 */
<> 150:02e0a0aed4ec 2938 #define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 2939 #define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 2940 #define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 10) /**< Analog Comparator 1 Clock Enable */
<> 150:02e0a0aed4ec 2941 #define _CMU_HFPERCLKEN0_ACMP1_SHIFT 10 /**< Shift value for CMU_ACMP1 */
<> 150:02e0a0aed4ec 2942 #define _CMU_HFPERCLKEN0_ACMP1_MASK 0x400UL /**< Bit mask for CMU_ACMP1 */
<> 150:02e0a0aed4ec 2943 #define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 2944 #define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 2945 #define CMU_HFPERCLKEN0_I2C0 (0x1UL << 11) /**< I2C 0 Clock Enable */
<> 150:02e0a0aed4ec 2946 #define _CMU_HFPERCLKEN0_I2C0_SHIFT 11 /**< Shift value for CMU_I2C0 */
<> 150:02e0a0aed4ec 2947 #define _CMU_HFPERCLKEN0_I2C0_MASK 0x800UL /**< Bit mask for CMU_I2C0 */
<> 150:02e0a0aed4ec 2948 #define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 2949 #define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 2950 #define CMU_HFPERCLKEN0_I2C1 (0x1UL << 12) /**< I2C 1 Clock Enable */
<> 150:02e0a0aed4ec 2951 #define _CMU_HFPERCLKEN0_I2C1_SHIFT 12 /**< Shift value for CMU_I2C1 */
<> 150:02e0a0aed4ec 2952 #define _CMU_HFPERCLKEN0_I2C1_MASK 0x1000UL /**< Bit mask for CMU_I2C1 */
<> 150:02e0a0aed4ec 2953 #define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 2954 #define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 2955 #define CMU_HFPERCLKEN0_GPIO (0x1UL << 13) /**< General purpose Input/Output Clock Enable */
<> 150:02e0a0aed4ec 2956 #define _CMU_HFPERCLKEN0_GPIO_SHIFT 13 /**< Shift value for CMU_GPIO */
<> 150:02e0a0aed4ec 2957 #define _CMU_HFPERCLKEN0_GPIO_MASK 0x2000UL /**< Bit mask for CMU_GPIO */
<> 150:02e0a0aed4ec 2958 #define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 2959 #define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 2960 #define CMU_HFPERCLKEN0_VCMP (0x1UL << 14) /**< Voltage Comparator Clock Enable */
<> 150:02e0a0aed4ec 2961 #define _CMU_HFPERCLKEN0_VCMP_SHIFT 14 /**< Shift value for CMU_VCMP */
<> 150:02e0a0aed4ec 2962 #define _CMU_HFPERCLKEN0_VCMP_MASK 0x4000UL /**< Bit mask for CMU_VCMP */
<> 150:02e0a0aed4ec 2963 #define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 2964 #define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 2965 #define CMU_HFPERCLKEN0_PRS (0x1UL << 15) /**< Peripheral Reflex System Clock Enable */
<> 150:02e0a0aed4ec 2966 #define _CMU_HFPERCLKEN0_PRS_SHIFT 15 /**< Shift value for CMU_PRS */
<> 150:02e0a0aed4ec 2967 #define _CMU_HFPERCLKEN0_PRS_MASK 0x8000UL /**< Bit mask for CMU_PRS */
<> 150:02e0a0aed4ec 2968 #define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 2969 #define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 2970 #define CMU_HFPERCLKEN0_ADC0 (0x1UL << 16) /**< Analog to Digital Converter 0 Clock Enable */
<> 150:02e0a0aed4ec 2971 #define _CMU_HFPERCLKEN0_ADC0_SHIFT 16 /**< Shift value for CMU_ADC0 */
<> 150:02e0a0aed4ec 2972 #define _CMU_HFPERCLKEN0_ADC0_MASK 0x10000UL /**< Bit mask for CMU_ADC0 */
<> 150:02e0a0aed4ec 2973 #define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 2974 #define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 2975 #define CMU_HFPERCLKEN0_DAC0 (0x1UL << 17) /**< Digital to Analog Converter 0 Clock Enable */
<> 150:02e0a0aed4ec 2976 #define _CMU_HFPERCLKEN0_DAC0_SHIFT 17 /**< Shift value for CMU_DAC0 */
<> 150:02e0a0aed4ec 2977 #define _CMU_HFPERCLKEN0_DAC0_MASK 0x20000UL /**< Bit mask for CMU_DAC0 */
<> 150:02e0a0aed4ec 2978 #define _CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 2979 #define CMU_HFPERCLKEN0_DAC0_DEFAULT (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 150:02e0a0aed4ec 2980
<> 150:02e0a0aed4ec 2981 /* Bit fields for CMU SYNCBUSY */
<> 150:02e0a0aed4ec 2982 #define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */
<> 150:02e0a0aed4ec 2983 #define _CMU_SYNCBUSY_MASK 0x00000055UL /**< Mask for CMU_SYNCBUSY */
<> 150:02e0a0aed4ec 2984 #define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */
<> 150:02e0a0aed4ec 2985 #define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */
<> 150:02e0a0aed4ec 2986 #define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */
<> 150:02e0a0aed4ec 2987 #define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
<> 150:02e0a0aed4ec 2988 #define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
<> 150:02e0a0aed4ec 2989 #define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */
<> 150:02e0a0aed4ec 2990 #define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 2991 #define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 2992 #define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
<> 150:02e0a0aed4ec 2993 #define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
<> 150:02e0a0aed4ec 2994 #define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */
<> 150:02e0a0aed4ec 2995 #define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */
<> 150:02e0a0aed4ec 2996 #define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */
<> 150:02e0a0aed4ec 2997 #define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
<> 150:02e0a0aed4ec 2998 #define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
<> 150:02e0a0aed4ec 2999 #define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */
<> 150:02e0a0aed4ec 3000 #define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 3001 #define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 3002 #define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
<> 150:02e0a0aed4ec 3003 #define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
<> 150:02e0a0aed4ec 3004
<> 150:02e0a0aed4ec 3005 /* Bit fields for CMU FREEZE */
<> 150:02e0a0aed4ec 3006 #define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */
<> 150:02e0a0aed4ec 3007 #define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */
<> 150:02e0a0aed4ec 3008 #define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */
<> 150:02e0a0aed4ec 3009 #define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */
<> 150:02e0a0aed4ec 3010 #define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */
<> 150:02e0a0aed4ec 3011 #define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */
<> 150:02e0a0aed4ec 3012 #define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */
<> 150:02e0a0aed4ec 3013 #define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */
<> 150:02e0a0aed4ec 3014 #define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */
<> 150:02e0a0aed4ec 3015 #define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */
<> 150:02e0a0aed4ec 3016 #define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */
<> 150:02e0a0aed4ec 3017
<> 150:02e0a0aed4ec 3018 /* Bit fields for CMU LFACLKEN0 */
<> 150:02e0a0aed4ec 3019 #define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */
<> 150:02e0a0aed4ec 3020 #define _CMU_LFACLKEN0_MASK 0x00000007UL /**< Mask for CMU_LFACLKEN0 */
<> 150:02e0a0aed4ec 3021 #define CMU_LFACLKEN0_LESENSE (0x1UL << 0) /**< Low Energy Sensor Interface Clock Enable */
<> 150:02e0a0aed4ec 3022 #define _CMU_LFACLKEN0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */
<> 150:02e0a0aed4ec 3023 #define _CMU_LFACLKEN0_LESENSE_MASK 0x1UL /**< Bit mask for CMU_LESENSE */
<> 150:02e0a0aed4ec 3024 #define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */
<> 150:02e0a0aed4ec 3025 #define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */
<> 150:02e0a0aed4ec 3026 #define CMU_LFACLKEN0_RTC (0x1UL << 1) /**< Real-Time Counter Clock Enable */
<> 150:02e0a0aed4ec 3027 #define _CMU_LFACLKEN0_RTC_SHIFT 1 /**< Shift value for CMU_RTC */
<> 150:02e0a0aed4ec 3028 #define _CMU_LFACLKEN0_RTC_MASK 0x2UL /**< Bit mask for CMU_RTC */
<> 150:02e0a0aed4ec 3029 #define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */
<> 150:02e0a0aed4ec 3030 #define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */
<> 150:02e0a0aed4ec 3031 #define CMU_LFACLKEN0_LETIMER0 (0x1UL << 2) /**< Low Energy Timer 0 Clock Enable */
<> 150:02e0a0aed4ec 3032 #define _CMU_LFACLKEN0_LETIMER0_SHIFT 2 /**< Shift value for CMU_LETIMER0 */
<> 150:02e0a0aed4ec 3033 #define _CMU_LFACLKEN0_LETIMER0_MASK 0x4UL /**< Bit mask for CMU_LETIMER0 */
<> 150:02e0a0aed4ec 3034 #define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */
<> 150:02e0a0aed4ec 3035 #define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */
<> 150:02e0a0aed4ec 3036
<> 150:02e0a0aed4ec 3037 /* Bit fields for CMU LFBCLKEN0 */
<> 150:02e0a0aed4ec 3038 #define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */
<> 150:02e0a0aed4ec 3039 #define _CMU_LFBCLKEN0_MASK 0x00000003UL /**< Mask for CMU_LFBCLKEN0 */
<> 150:02e0a0aed4ec 3040 #define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */
<> 150:02e0a0aed4ec 3041 #define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */
<> 150:02e0a0aed4ec 3042 #define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */
<> 150:02e0a0aed4ec 3043 #define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */
<> 150:02e0a0aed4ec 3044 #define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */
<> 150:02e0a0aed4ec 3045 #define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */
<> 150:02e0a0aed4ec 3046 #define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */
<> 150:02e0a0aed4ec 3047 #define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */
<> 150:02e0a0aed4ec 3048 #define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */
<> 150:02e0a0aed4ec 3049 #define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */
<> 150:02e0a0aed4ec 3050
<> 150:02e0a0aed4ec 3051 /* Bit fields for CMU LFAPRESC0 */
<> 150:02e0a0aed4ec 3052 #define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3053 #define _CMU_LFAPRESC0_MASK 0x00000FF3UL /**< Mask for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3054 #define _CMU_LFAPRESC0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */
<> 150:02e0a0aed4ec 3055 #define _CMU_LFAPRESC0_LESENSE_MASK 0x3UL /**< Bit mask for CMU_LESENSE */
<> 150:02e0a0aed4ec 3056 #define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3057 #define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3058 #define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3059 #define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3060 #define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3061 #define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3062 #define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3063 #define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3064 #define _CMU_LFAPRESC0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */
<> 150:02e0a0aed4ec 3065 #define _CMU_LFAPRESC0_RTC_MASK 0xF0UL /**< Bit mask for CMU_RTC */
<> 150:02e0a0aed4ec 3066 #define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3067 #define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3068 #define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3069 #define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3070 #define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3071 #define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3072 #define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3073 #define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3074 #define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3075 #define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3076 #define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3077 #define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3078 #define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3079 #define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3080 #define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3081 #define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3082 #define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3083 #define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3084 #define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3085 #define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3086 #define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3087 #define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3088 #define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3089 #define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3090 #define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3091 #define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3092 #define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3093 #define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3094 #define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3095 #define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3096 #define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3097 #define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3098 #define _CMU_LFAPRESC0_LETIMER0_SHIFT 8 /**< Shift value for CMU_LETIMER0 */
<> 150:02e0a0aed4ec 3099 #define _CMU_LFAPRESC0_LETIMER0_MASK 0xF00UL /**< Bit mask for CMU_LETIMER0 */
<> 150:02e0a0aed4ec 3100 #define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3101 #define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3102 #define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3103 #define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3104 #define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3105 #define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3106 #define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3107 #define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3108 #define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3109 #define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3110 #define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3111 #define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3112 #define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3113 #define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3114 #define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3115 #define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3116 #define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3117 #define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3118 #define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3119 #define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3120 #define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 8) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3121 #define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 8) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3122 #define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 8) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3123 #define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 8) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3124 #define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 8) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3125 #define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 8) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3126 #define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 8) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3127 #define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 8) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3128 #define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 8) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3129 #define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 8) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3130 #define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 8) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3131 #define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 8) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */
<> 150:02e0a0aed4ec 3132
<> 150:02e0a0aed4ec 3133 /* Bit fields for CMU LFBPRESC0 */
<> 150:02e0a0aed4ec 3134 #define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 3135 #define _CMU_LFBPRESC0_MASK 0x00000033UL /**< Mask for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 3136 #define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */
<> 150:02e0a0aed4ec 3137 #define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */
<> 150:02e0a0aed4ec 3138 #define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 3139 #define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 3140 #define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 3141 #define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 3142 #define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 3143 #define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 3144 #define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 3145 #define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 3146 #define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */
<> 150:02e0a0aed4ec 3147 #define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */
<> 150:02e0a0aed4ec 3148 #define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 3149 #define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 3150 #define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 3151 #define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 3152 #define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 3153 #define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 3154 #define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 3155 #define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */
<> 150:02e0a0aed4ec 3156
<> 150:02e0a0aed4ec 3157 /* Bit fields for CMU PCNTCTRL */
<> 150:02e0a0aed4ec 3158 #define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 3159 #define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 3160 #define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */
<> 150:02e0a0aed4ec 3161 #define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */
<> 150:02e0a0aed4ec 3162 #define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */
<> 150:02e0a0aed4ec 3163 #define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 3164 #define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 3165 #define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */
<> 150:02e0a0aed4ec 3166 #define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */
<> 150:02e0a0aed4ec 3167 #define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */
<> 150:02e0a0aed4ec 3168 #define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 3169 #define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 3170 #define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 3171 #define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 3172 #define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 3173 #define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 3174 #define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */
<> 150:02e0a0aed4ec 3175 #define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */
<> 150:02e0a0aed4ec 3176 #define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */
<> 150:02e0a0aed4ec 3177 #define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 3178 #define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 3179 #define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */
<> 150:02e0a0aed4ec 3180 #define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */
<> 150:02e0a0aed4ec 3181 #define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */
<> 150:02e0a0aed4ec 3182 #define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 3183 #define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 3184 #define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 3185 #define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 3186 #define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 3187 #define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 3188 #define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */
<> 150:02e0a0aed4ec 3189 #define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */
<> 150:02e0a0aed4ec 3190 #define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */
<> 150:02e0a0aed4ec 3191 #define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 3192 #define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 3193 #define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */
<> 150:02e0a0aed4ec 3194 #define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */
<> 150:02e0a0aed4ec 3195 #define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */
<> 150:02e0a0aed4ec 3196 #define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 3197 #define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 3198 #define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 3199 #define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 3200 #define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 3201 #define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */
<> 150:02e0a0aed4ec 3202
<> 150:02e0a0aed4ec 3203 /* Bit fields for CMU ROUTE */
<> 150:02e0a0aed4ec 3204 #define _CMU_ROUTE_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTE */
<> 150:02e0a0aed4ec 3205 #define _CMU_ROUTE_MASK 0x0000001FUL /**< Mask for CMU_ROUTE */
<> 150:02e0a0aed4ec 3206 #define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */
<> 150:02e0a0aed4ec 3207 #define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */
<> 150:02e0a0aed4ec 3208 #define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */
<> 150:02e0a0aed4ec 3209 #define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */
<> 150:02e0a0aed4ec 3210 #define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTE */
<> 150:02e0a0aed4ec 3211 #define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */
<> 150:02e0a0aed4ec 3212 #define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */
<> 150:02e0a0aed4ec 3213 #define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */
<> 150:02e0a0aed4ec 3214 #define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */
<> 150:02e0a0aed4ec 3215 #define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTE */
<> 150:02e0a0aed4ec 3216 #define _CMU_ROUTE_LOCATION_SHIFT 2 /**< Shift value for CMU_LOCATION */
<> 150:02e0a0aed4ec 3217 #define _CMU_ROUTE_LOCATION_MASK 0x1CUL /**< Bit mask for CMU_LOCATION */
<> 150:02e0a0aed4ec 3218 #define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTE */
<> 150:02e0a0aed4ec 3219 #define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */
<> 150:02e0a0aed4ec 3220 #define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTE */
<> 150:02e0a0aed4ec 3221 #define _CMU_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTE */
<> 150:02e0a0aed4ec 3222 #define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2) /**< Shifted mode LOC0 for CMU_ROUTE */
<> 150:02e0a0aed4ec 3223 #define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTE */
<> 150:02e0a0aed4ec 3224 #define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2) /**< Shifted mode LOC1 for CMU_ROUTE */
<> 150:02e0a0aed4ec 3225 #define CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2) /**< Shifted mode LOC2 for CMU_ROUTE */
<> 150:02e0a0aed4ec 3226
<> 150:02e0a0aed4ec 3227 /* Bit fields for CMU LOCK */
<> 150:02e0a0aed4ec 3228 #define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */
<> 150:02e0a0aed4ec 3229 #define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */
<> 150:02e0a0aed4ec 3230 #define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */
<> 150:02e0a0aed4ec 3231 #define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */
<> 150:02e0a0aed4ec 3232 #define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */
<> 150:02e0a0aed4ec 3233 #define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */
<> 150:02e0a0aed4ec 3234 #define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */
<> 150:02e0a0aed4ec 3235 #define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */
<> 150:02e0a0aed4ec 3236 #define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */
<> 150:02e0a0aed4ec 3237 #define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */
<> 150:02e0a0aed4ec 3238 #define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */
<> 150:02e0a0aed4ec 3239 #define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */
<> 150:02e0a0aed4ec 3240 #define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */
<> 150:02e0a0aed4ec 3241 #define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */
<> 150:02e0a0aed4ec 3242
<> 150:02e0a0aed4ec 3243 /** @} End of group EFM32WG332F256_CMU */
<> 150:02e0a0aed4ec 3244
<> 150:02e0a0aed4ec 3245
<> 150:02e0a0aed4ec 3246
<> 150:02e0a0aed4ec 3247 /**************************************************************************//**
<> 150:02e0a0aed4ec 3248 * @defgroup EFM32WG332F256_PRS_BitFields EFM32WG332F256_PRS Bit Fields
<> 150:02e0a0aed4ec 3249 * @{
<> 150:02e0a0aed4ec 3250 *****************************************************************************/
<> 150:02e0a0aed4ec 3251
<> 150:02e0a0aed4ec 3252 /* Bit fields for PRS SWPULSE */
<> 150:02e0a0aed4ec 3253 #define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */
<> 150:02e0a0aed4ec 3254 #define _PRS_SWPULSE_MASK 0x00000FFFUL /**< Mask for PRS_SWPULSE */
<> 150:02e0a0aed4ec 3255 #define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */
<> 150:02e0a0aed4ec 3256 #define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */
<> 150:02e0a0aed4ec 3257 #define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */
<> 150:02e0a0aed4ec 3258 #define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
<> 150:02e0a0aed4ec 3259 #define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */
<> 150:02e0a0aed4ec 3260 #define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */
<> 150:02e0a0aed4ec 3261 #define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */
<> 150:02e0a0aed4ec 3262 #define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */
<> 150:02e0a0aed4ec 3263 #define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
<> 150:02e0a0aed4ec 3264 #define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */
<> 150:02e0a0aed4ec 3265 #define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */
<> 150:02e0a0aed4ec 3266 #define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */
<> 150:02e0a0aed4ec 3267 #define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */
<> 150:02e0a0aed4ec 3268 #define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
<> 150:02e0a0aed4ec 3269 #define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */
<> 150:02e0a0aed4ec 3270 #define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */
<> 150:02e0a0aed4ec 3271 #define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */
<> 150:02e0a0aed4ec 3272 #define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */
<> 150:02e0a0aed4ec 3273 #define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
<> 150:02e0a0aed4ec 3274 #define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */
<> 150:02e0a0aed4ec 3275 #define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */
<> 150:02e0a0aed4ec 3276 #define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */
<> 150:02e0a0aed4ec 3277 #define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */
<> 150:02e0a0aed4ec 3278 #define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
<> 150:02e0a0aed4ec 3279 #define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */
<> 150:02e0a0aed4ec 3280 #define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */
<> 150:02e0a0aed4ec 3281 #define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */
<> 150:02e0a0aed4ec 3282 #define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */
<> 150:02e0a0aed4ec 3283 #define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
<> 150:02e0a0aed4ec 3284 #define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */
<> 150:02e0a0aed4ec 3285 #define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */
<> 150:02e0a0aed4ec 3286 #define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */
<> 150:02e0a0aed4ec 3287 #define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */
<> 150:02e0a0aed4ec 3288 #define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
<> 150:02e0a0aed4ec 3289 #define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */
<> 150:02e0a0aed4ec 3290 #define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */
<> 150:02e0a0aed4ec 3291 #define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */
<> 150:02e0a0aed4ec 3292 #define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */
<> 150:02e0a0aed4ec 3293 #define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
<> 150:02e0a0aed4ec 3294 #define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */
<> 150:02e0a0aed4ec 3295 #define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */
<> 150:02e0a0aed4ec 3296 #define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */
<> 150:02e0a0aed4ec 3297 #define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */
<> 150:02e0a0aed4ec 3298 #define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
<> 150:02e0a0aed4ec 3299 #define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */
<> 150:02e0a0aed4ec 3300 #define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */
<> 150:02e0a0aed4ec 3301 #define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */
<> 150:02e0a0aed4ec 3302 #define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */
<> 150:02e0a0aed4ec 3303 #define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
<> 150:02e0a0aed4ec 3304 #define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */
<> 150:02e0a0aed4ec 3305 #define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */
<> 150:02e0a0aed4ec 3306 #define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */
<> 150:02e0a0aed4ec 3307 #define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */
<> 150:02e0a0aed4ec 3308 #define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
<> 150:02e0a0aed4ec 3309 #define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */
<> 150:02e0a0aed4ec 3310 #define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */
<> 150:02e0a0aed4ec 3311 #define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */
<> 150:02e0a0aed4ec 3312 #define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */
<> 150:02e0a0aed4ec 3313 #define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
<> 150:02e0a0aed4ec 3314 #define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */
<> 150:02e0a0aed4ec 3315
<> 150:02e0a0aed4ec 3316 /* Bit fields for PRS SWLEVEL */
<> 150:02e0a0aed4ec 3317 #define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */
<> 150:02e0a0aed4ec 3318 #define _PRS_SWLEVEL_MASK 0x00000FFFUL /**< Mask for PRS_SWLEVEL */
<> 150:02e0a0aed4ec 3319 #define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */
<> 150:02e0a0aed4ec 3320 #define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */
<> 150:02e0a0aed4ec 3321 #define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */
<> 150:02e0a0aed4ec 3322 #define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
<> 150:02e0a0aed4ec 3323 #define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
<> 150:02e0a0aed4ec 3324 #define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */
<> 150:02e0a0aed4ec 3325 #define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */
<> 150:02e0a0aed4ec 3326 #define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */
<> 150:02e0a0aed4ec 3327 #define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
<> 150:02e0a0aed4ec 3328 #define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
<> 150:02e0a0aed4ec 3329 #define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */
<> 150:02e0a0aed4ec 3330 #define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */
<> 150:02e0a0aed4ec 3331 #define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */
<> 150:02e0a0aed4ec 3332 #define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
<> 150:02e0a0aed4ec 3333 #define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
<> 150:02e0a0aed4ec 3334 #define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */
<> 150:02e0a0aed4ec 3335 #define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */
<> 150:02e0a0aed4ec 3336 #define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */
<> 150:02e0a0aed4ec 3337 #define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
<> 150:02e0a0aed4ec 3338 #define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
<> 150:02e0a0aed4ec 3339 #define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */
<> 150:02e0a0aed4ec 3340 #define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */
<> 150:02e0a0aed4ec 3341 #define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */
<> 150:02e0a0aed4ec 3342 #define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
<> 150:02e0a0aed4ec 3343 #define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
<> 150:02e0a0aed4ec 3344 #define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */
<> 150:02e0a0aed4ec 3345 #define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */
<> 150:02e0a0aed4ec 3346 #define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */
<> 150:02e0a0aed4ec 3347 #define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
<> 150:02e0a0aed4ec 3348 #define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
<> 150:02e0a0aed4ec 3349 #define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */
<> 150:02e0a0aed4ec 3350 #define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */
<> 150:02e0a0aed4ec 3351 #define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */
<> 150:02e0a0aed4ec 3352 #define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
<> 150:02e0a0aed4ec 3353 #define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
<> 150:02e0a0aed4ec 3354 #define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */
<> 150:02e0a0aed4ec 3355 #define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */
<> 150:02e0a0aed4ec 3356 #define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */
<> 150:02e0a0aed4ec 3357 #define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
<> 150:02e0a0aed4ec 3358 #define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
<> 150:02e0a0aed4ec 3359 #define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */
<> 150:02e0a0aed4ec 3360 #define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */
<> 150:02e0a0aed4ec 3361 #define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */
<> 150:02e0a0aed4ec 3362 #define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
<> 150:02e0a0aed4ec 3363 #define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
<> 150:02e0a0aed4ec 3364 #define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */
<> 150:02e0a0aed4ec 3365 #define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */
<> 150:02e0a0aed4ec 3366 #define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */
<> 150:02e0a0aed4ec 3367 #define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
<> 150:02e0a0aed4ec 3368 #define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
<> 150:02e0a0aed4ec 3369 #define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */
<> 150:02e0a0aed4ec 3370 #define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */
<> 150:02e0a0aed4ec 3371 #define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */
<> 150:02e0a0aed4ec 3372 #define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
<> 150:02e0a0aed4ec 3373 #define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
<> 150:02e0a0aed4ec 3374 #define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */
<> 150:02e0a0aed4ec 3375 #define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */
<> 150:02e0a0aed4ec 3376 #define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */
<> 150:02e0a0aed4ec 3377 #define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
<> 150:02e0a0aed4ec 3378 #define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
<> 150:02e0a0aed4ec 3379
<> 150:02e0a0aed4ec 3380 /* Bit fields for PRS ROUTE */
<> 150:02e0a0aed4ec 3381 #define _PRS_ROUTE_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTE */
<> 150:02e0a0aed4ec 3382 #define _PRS_ROUTE_MASK 0x0000070FUL /**< Mask for PRS_ROUTE */
<> 150:02e0a0aed4ec 3383 #define PRS_ROUTE_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */
<> 150:02e0a0aed4ec 3384 #define _PRS_ROUTE_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */
<> 150:02e0a0aed4ec 3385 #define _PRS_ROUTE_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */
<> 150:02e0a0aed4ec 3386 #define _PRS_ROUTE_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */
<> 150:02e0a0aed4ec 3387 #define PRS_ROUTE_CH0PEN_DEFAULT (_PRS_ROUTE_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTE */
<> 150:02e0a0aed4ec 3388 #define PRS_ROUTE_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */
<> 150:02e0a0aed4ec 3389 #define _PRS_ROUTE_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */
<> 150:02e0a0aed4ec 3390 #define _PRS_ROUTE_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */
<> 150:02e0a0aed4ec 3391 #define _PRS_ROUTE_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */
<> 150:02e0a0aed4ec 3392 #define PRS_ROUTE_CH1PEN_DEFAULT (_PRS_ROUTE_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTE */
<> 150:02e0a0aed4ec 3393 #define PRS_ROUTE_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */
<> 150:02e0a0aed4ec 3394 #define _PRS_ROUTE_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */
<> 150:02e0a0aed4ec 3395 #define _PRS_ROUTE_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */
<> 150:02e0a0aed4ec 3396 #define _PRS_ROUTE_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */
<> 150:02e0a0aed4ec 3397 #define PRS_ROUTE_CH2PEN_DEFAULT (_PRS_ROUTE_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTE */
<> 150:02e0a0aed4ec 3398 #define PRS_ROUTE_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */
<> 150:02e0a0aed4ec 3399 #define _PRS_ROUTE_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */
<> 150:02e0a0aed4ec 3400 #define _PRS_ROUTE_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */
<> 150:02e0a0aed4ec 3401 #define _PRS_ROUTE_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */
<> 150:02e0a0aed4ec 3402 #define PRS_ROUTE_CH3PEN_DEFAULT (_PRS_ROUTE_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTE */
<> 150:02e0a0aed4ec 3403 #define _PRS_ROUTE_LOCATION_SHIFT 8 /**< Shift value for PRS_LOCATION */
<> 150:02e0a0aed4ec 3404 #define _PRS_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for PRS_LOCATION */
<> 150:02e0a0aed4ec 3405 #define _PRS_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTE */
<> 150:02e0a0aed4ec 3406 #define _PRS_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */
<> 150:02e0a0aed4ec 3407 #define _PRS_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTE */
<> 150:02e0a0aed4ec 3408 #define PRS_ROUTE_LOCATION_LOC0 (_PRS_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTE */
<> 150:02e0a0aed4ec 3409 #define PRS_ROUTE_LOCATION_DEFAULT (_PRS_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTE */
<> 150:02e0a0aed4ec 3410 #define PRS_ROUTE_LOCATION_LOC1 (_PRS_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTE */
<> 150:02e0a0aed4ec 3411
<> 150:02e0a0aed4ec 3412 /* Bit fields for PRS CH_CTRL */
<> 150:02e0a0aed4ec 3413 #define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3414 #define _PRS_CH_CTRL_MASK 0x133F0007UL /**< Mask for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3415 #define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */
<> 150:02e0a0aed4ec 3416 #define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */
<> 150:02e0a0aed4ec 3417 #define _PRS_CH_CTRL_SIGSEL_VCMPOUT 0x00000000UL /**< Mode VCMPOUT for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3418 #define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3419 #define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3420 #define _PRS_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3421 #define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3422 #define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3423 #define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3424 #define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3425 #define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3426 #define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3427 #define _PRS_CH_CTRL_SIGSEL_USBSOF 0x00000000UL /**< Mode USBSOF for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3428 #define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3429 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3430 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3431 #define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3432 #define _PRS_CH_CTRL_SIGSEL_BURTCOF 0x00000000UL /**< Mode BURTCOF for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3433 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3434 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3435 #define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3436 #define _PRS_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3437 #define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3438 #define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3439 #define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3440 #define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3441 #define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3442 #define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3443 #define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3444 #define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3445 #define _PRS_CH_CTRL_SIGSEL_USBSOFSR 0x00000001UL /**< Mode USBSOFSR for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3446 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3447 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3448 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3449 #define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3450 #define _PRS_CH_CTRL_SIGSEL_BURTCCOMP0 0x00000001UL /**< Mode BURTCCOMP0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3451 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3452 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3453 #define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3454 #define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3455 #define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3456 #define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3457 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3458 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3459 #define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3460 #define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3461 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3462 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3463 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3464 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3465 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3466 #define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3467 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3468 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3469 #define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3470 #define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3471 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3472 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3473 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3474 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3475 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3476 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3477 #define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3478 #define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3479 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3480 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3481 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3482 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3483 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3484 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3485 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3486 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3487 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3488 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3489 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3490 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3491 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3492 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3493 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3494 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3495 #define PRS_CH_CTRL_SIGSEL_VCMPOUT (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0) /**< Shifted mode VCMPOUT for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3496 #define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3497 #define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3498 #define PRS_CH_CTRL_SIGSEL_DAC0CH0 (_PRS_CH_CTRL_SIGSEL_DAC0CH0 << 0) /**< Shifted mode DAC0CH0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3499 #define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3500 #define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3501 #define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3502 #define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3503 #define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3504 #define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3505 #define PRS_CH_CTRL_SIGSEL_USBSOF (_PRS_CH_CTRL_SIGSEL_USBSOF << 0) /**< Shifted mode USBSOF for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3506 #define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3507 #define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3508 #define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3509 #define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3510 #define PRS_CH_CTRL_SIGSEL_BURTCOF (_PRS_CH_CTRL_SIGSEL_BURTCOF << 0) /**< Shifted mode BURTCOF for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3511 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3512 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3513 #define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3514 #define PRS_CH_CTRL_SIGSEL_DAC0CH1 (_PRS_CH_CTRL_SIGSEL_DAC0CH1 << 0) /**< Shifted mode DAC0CH1 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3515 #define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3516 #define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3517 #define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3518 #define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3519 #define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3520 #define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3521 #define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3522 #define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3523 #define PRS_CH_CTRL_SIGSEL_USBSOFSR (_PRS_CH_CTRL_SIGSEL_USBSOFSR << 0) /**< Shifted mode USBSOFSR for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3524 #define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3525 #define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3526 #define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3527 #define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3528 #define PRS_CH_CTRL_SIGSEL_BURTCCOMP0 (_PRS_CH_CTRL_SIGSEL_BURTCCOMP0 << 0) /**< Shifted mode BURTCCOMP0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3529 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3530 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3531 #define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3532 #define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3533 #define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3534 #define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3535 #define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3536 #define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3537 #define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3538 #define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3539 #define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3540 #define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3541 #define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3542 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3543 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3544 #define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3545 #define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3546 #define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3547 #define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3548 #define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3549 #define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3550 #define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3551 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3552 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3553 #define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3554 #define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3555 #define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3556 #define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3557 #define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3558 #define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3559 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3560 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3561 #define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3562 #define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3563 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3564 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3565 #define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3566 #define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3567 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3568 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3569 #define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3570 #define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3571 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3572 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3573 #define _PRS_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for PRS_SOURCESEL */
<> 150:02e0a0aed4ec 3574 #define _PRS_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for PRS_SOURCESEL */
<> 150:02e0a0aed4ec 3575 #define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3576 #define _PRS_CH_CTRL_SOURCESEL_VCMP 0x00000001UL /**< Mode VCMP for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3577 #define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000002UL /**< Mode ACMP0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3578 #define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000003UL /**< Mode ACMP1 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3579 #define _PRS_CH_CTRL_SOURCESEL_DAC0 0x00000006UL /**< Mode DAC0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3580 #define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3581 #define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000010UL /**< Mode USART0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3582 #define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000011UL /**< Mode USART1 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3583 #define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000012UL /**< Mode USART2 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3584 #define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mode TIMER0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3585 #define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000001DUL /**< Mode TIMER1 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3586 #define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000001EUL /**< Mode TIMER2 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3587 #define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x0000001FUL /**< Mode TIMER3 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3588 #define _PRS_CH_CTRL_SOURCESEL_USB 0x00000024UL /**< Mode USB for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3589 #define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000028UL /**< Mode RTC for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3590 #define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000030UL /**< Mode GPIOL for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3591 #define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x00000031UL /**< Mode GPIOH for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3592 #define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x00000034UL /**< Mode LETIMER0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3593 #define _PRS_CH_CTRL_SOURCESEL_BURTC 0x00000037UL /**< Mode BURTC for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3594 #define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000039UL /**< Mode LESENSEL for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3595 #define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x0000003AUL /**< Mode LESENSEH for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3596 #define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000003BUL /**< Mode LESENSED for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3597 #define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3598 #define PRS_CH_CTRL_SOURCESEL_VCMP (_PRS_CH_CTRL_SOURCESEL_VCMP << 16) /**< Shifted mode VCMP for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3599 #define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16) /**< Shifted mode ACMP0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3600 #define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 16) /**< Shifted mode ACMP1 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3601 #define PRS_CH_CTRL_SOURCESEL_DAC0 (_PRS_CH_CTRL_SOURCESEL_DAC0 << 16) /**< Shifted mode DAC0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3602 #define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3603 #define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3604 #define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3605 #define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3606 #define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3607 #define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3608 #define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3609 #define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3610 #define PRS_CH_CTRL_SOURCESEL_USB (_PRS_CH_CTRL_SOURCESEL_USB << 16) /**< Shifted mode USB for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3611 #define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 16) /**< Shifted mode RTC for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3612 #define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16) /**< Shifted mode GPIOL for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3613 #define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16) /**< Shifted mode GPIOH for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3614 #define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 16) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3615 #define PRS_CH_CTRL_SOURCESEL_BURTC (_PRS_CH_CTRL_SOURCESEL_BURTC << 16) /**< Shifted mode BURTC for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3616 #define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 16) /**< Shifted mode LESENSEL for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3617 #define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 16) /**< Shifted mode LESENSEH for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3618 #define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 16) /**< Shifted mode LESENSED for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3619 #define _PRS_CH_CTRL_EDSEL_SHIFT 24 /**< Shift value for PRS_EDSEL */
<> 150:02e0a0aed4ec 3620 #define _PRS_CH_CTRL_EDSEL_MASK 0x3000000UL /**< Bit mask for PRS_EDSEL */
<> 150:02e0a0aed4ec 3621 #define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3622 #define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3623 #define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3624 #define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3625 #define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3626 #define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3627 #define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 24) /**< Shifted mode OFF for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3628 #define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 24) /**< Shifted mode POSEDGE for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3629 #define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3630 #define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3631 #define PRS_CH_CTRL_ASYNC (0x1UL << 28) /**< Asynchronous reflex */
<> 150:02e0a0aed4ec 3632 #define _PRS_CH_CTRL_ASYNC_SHIFT 28 /**< Shift value for PRS_ASYNC */
<> 150:02e0a0aed4ec 3633 #define _PRS_CH_CTRL_ASYNC_MASK 0x10000000UL /**< Bit mask for PRS_ASYNC */
<> 150:02e0a0aed4ec 3634 #define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3635 #define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */
<> 150:02e0a0aed4ec 3636
<> 150:02e0a0aed4ec 3637 /** @} End of group EFM32WG332F256_PRS */
<> 150:02e0a0aed4ec 3638
<> 150:02e0a0aed4ec 3639
<> 150:02e0a0aed4ec 3640
<> 150:02e0a0aed4ec 3641 /**************************************************************************//**
<> 150:02e0a0aed4ec 3642 * @defgroup EFM32WG332F256_UNLOCK EFM32WG332F256 Unlock Codes
<> 150:02e0a0aed4ec 3643 * @{
<> 150:02e0a0aed4ec 3644 *****************************************************************************/
<> 150:02e0a0aed4ec 3645 #define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
<> 150:02e0a0aed4ec 3646 #define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
<> 150:02e0a0aed4ec 3647 #define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
<> 150:02e0a0aed4ec 3648 #define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
<> 150:02e0a0aed4ec 3649 #define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
<> 150:02e0a0aed4ec 3650 #define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */
<> 150:02e0a0aed4ec 3651
<> 150:02e0a0aed4ec 3652 /** @} End of group EFM32WG332F256_UNLOCK */
<> 150:02e0a0aed4ec 3653
<> 150:02e0a0aed4ec 3654 /** @} End of group EFM32WG332F256_BitFields */
<> 150:02e0a0aed4ec 3655
<> 150:02e0a0aed4ec 3656 /**************************************************************************//**
<> 150:02e0a0aed4ec 3657 * @defgroup EFM32WG332F256_Alternate_Function EFM32WG332F256 Alternate Function
<> 150:02e0a0aed4ec 3658 * @{
<> 150:02e0a0aed4ec 3659 *****************************************************************************/
<> 150:02e0a0aed4ec 3660
<> 150:02e0a0aed4ec 3661 #include "efm32wg_af_ports.h"
<> 150:02e0a0aed4ec 3662 #include "efm32wg_af_pins.h"
<> 150:02e0a0aed4ec 3663
<> 150:02e0a0aed4ec 3664 /** @} End of group EFM32WG332F256_Alternate_Function */
<> 150:02e0a0aed4ec 3665
<> 150:02e0a0aed4ec 3666 /**************************************************************************//**
<> 150:02e0a0aed4ec 3667 * @brief Set the value of a bit field within a register.
<> 150:02e0a0aed4ec 3668 *
<> 150:02e0a0aed4ec 3669 * @param REG
<> 150:02e0a0aed4ec 3670 * The register to update
<> 150:02e0a0aed4ec 3671 * @param MASK
<> 150:02e0a0aed4ec 3672 * The mask for the bit field to update
<> 150:02e0a0aed4ec 3673 * @param VALUE
<> 150:02e0a0aed4ec 3674 * The value to write to the bit field
<> 150:02e0a0aed4ec 3675 * @param OFFSET
<> 150:02e0a0aed4ec 3676 * The number of bits that the field is offset within the register.
<> 150:02e0a0aed4ec 3677 * 0 (zero) means LSB.
<> 150:02e0a0aed4ec 3678 *****************************************************************************/
<> 150:02e0a0aed4ec 3679 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
<> 150:02e0a0aed4ec 3680 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
<> 150:02e0a0aed4ec 3681
<> 150:02e0a0aed4ec 3682 /** @} End of group EFM32WG332F256 */
<> 150:02e0a0aed4ec 3683
<> 150:02e0a0aed4ec 3684 /** @} End of group Parts */
<> 150:02e0a0aed4ec 3685
<> 150:02e0a0aed4ec 3686 #ifdef __cplusplus
<> 150:02e0a0aed4ec 3687 }
<> 150:02e0a0aed4ec 3688 #endif
<> 150:02e0a0aed4ec 3689 #endif /* EFM32WG332F256_H */