Fawwaz Nadzmy / mbed-STM

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/TARGET_256K/TOOLCHAIN_GCC_ARM/startup_efm32wg.S@153:9398a535854b, 2016-12-22 (annotated)

Committer:
fwndz
Date:
Thu Dec 22 05:12:40 2016 +0000
Revision:
153:9398a535854b
Parent:
150:02e0a0aed4ec 
device target maximize

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 150:02e0a0aed4ec 1 /* @file startup_efm32wg.S
<> 150:02e0a0aed4ec 2 * @brief startup file for Silicon Labs EFM32WG devices.
<> 150:02e0a0aed4ec 3 * For use with GCC for ARM Embedded Processors
<> 150:02e0a0aed4ec 4 * @version 4.2.1
<> 150:02e0a0aed4ec 5 * Date: 12 June 2014
<> 150:02e0a0aed4ec 6 *
<> 150:02e0a0aed4ec 7 */
<> 150:02e0a0aed4ec 8 /* Copyright (c) 2011 - 2014 ARM LIMITED
<> 150:02e0a0aed4ec 9
<> 150:02e0a0aed4ec 10 All rights reserved.
<> 150:02e0a0aed4ec 11 Redistribution and use in source and binary forms, with or without
<> 150:02e0a0aed4ec 12 modification, are permitted provided that the following conditions are met:
<> 150:02e0a0aed4ec 13 - Redistributions of source code must retain the above copyright
<> 150:02e0a0aed4ec 14 notice, this list of conditions and the following disclaimer.
<> 150:02e0a0aed4ec 15 - Redistributions in binary form must reproduce the above copyright
<> 150:02e0a0aed4ec 16 notice, this list of conditions and the following disclaimer in the
<> 150:02e0a0aed4ec 17 documentation and/or other materials provided with the distribution.
<> 150:02e0a0aed4ec 18 - Neither the name of ARM nor the names of its contributors may be used
<> 150:02e0a0aed4ec 19 to endorse or promote products derived from this software without
<> 150:02e0a0aed4ec 20 specific prior written permission.
<> 150:02e0a0aed4ec 21 *
<> 150:02e0a0aed4ec 22 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 150:02e0a0aed4ec 23 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 150:02e0a0aed4ec 24 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 150:02e0a0aed4ec 25 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<> 150:02e0a0aed4ec 26 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 150:02e0a0aed4ec 27 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 150:02e0a0aed4ec 28 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 150:02e0a0aed4ec 29 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 150:02e0a0aed4ec 30 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 150:02e0a0aed4ec 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 150:02e0a0aed4ec 32 POSSIBILITY OF SUCH DAMAGE.
<> 150:02e0a0aed4ec 33 ---------------------------------------------------------------------------*/
<> 150:02e0a0aed4ec 34
<> 150:02e0a0aed4ec 35 .syntax unified
<> 150:02e0a0aed4ec 36 .arch armv7-m
<> 150:02e0a0aed4ec 37 .section .stack
<> 150:02e0a0aed4ec 38 .align 3
<> 150:02e0a0aed4ec 39 #ifdef __STACK_SIZE
<> 150:02e0a0aed4ec 40 .equ Stack_Size, __STACK_SIZE
<> 150:02e0a0aed4ec 41 #else
<> 150:02e0a0aed4ec 42 .equ Stack_Size, 0x00000400
<> 150:02e0a0aed4ec 43 #endif
<> 150:02e0a0aed4ec 44 .globl __StackTop
<> 150:02e0a0aed4ec 45 .globl __StackLimit
<> 150:02e0a0aed4ec 46 __StackLimit:
<> 150:02e0a0aed4ec 47 .space Stack_Size
<> 150:02e0a0aed4ec 48 .size __StackLimit, . - __StackLimit
<> 150:02e0a0aed4ec 49 __StackTop:
<> 150:02e0a0aed4ec 50 .size __StackTop, . - __StackTop
<> 150:02e0a0aed4ec 51
<> 150:02e0a0aed4ec 52 .section .heap
<> 150:02e0a0aed4ec 53 .align 3
<> 150:02e0a0aed4ec 54 #ifdef __HEAP_SIZE
<> 150:02e0a0aed4ec 55 .equ Heap_Size, __HEAP_SIZE
<> 150:02e0a0aed4ec 56 #else
<> 150:02e0a0aed4ec 57 .equ Heap_Size, 0x00000C00
<> 150:02e0a0aed4ec 58 #endif
<> 150:02e0a0aed4ec 59 .globl __HeapBase
<> 150:02e0a0aed4ec 60 .globl __HeapLimit
<> 150:02e0a0aed4ec 61 __HeapBase:
<> 150:02e0a0aed4ec 62 .if Heap_Size
<> 150:02e0a0aed4ec 63 .space Heap_Size
<> 150:02e0a0aed4ec 64 .endif
<> 150:02e0a0aed4ec 65 .size __HeapBase, . - __HeapBase
<> 150:02e0a0aed4ec 66 __HeapLimit:
<> 150:02e0a0aed4ec 67 .size __HeapLimit, . - __HeapLimit
<> 150:02e0a0aed4ec 68
<> 150:02e0a0aed4ec 69 .section .vectors
<> 150:02e0a0aed4ec 70 .align 2
<> 150:02e0a0aed4ec 71 .globl __Vectors
<> 150:02e0a0aed4ec 72 __Vectors:
<> 150:02e0a0aed4ec 73 .long __StackTop /* Top of Stack */
<> 150:02e0a0aed4ec 74 .long Reset_Handler /* Reset Handler */
<> 150:02e0a0aed4ec 75 .long NMI_Handler /* NMI Handler */
<> 150:02e0a0aed4ec 76 .long HardFault_Handler /* Hard Fault Handler */
<> 150:02e0a0aed4ec 77 .long MemManage_Handler /* MPU Fault Handler */
<> 150:02e0a0aed4ec 78 .long BusFault_Handler /* Bus Fault Handler */
<> 150:02e0a0aed4ec 79 .long UsageFault_Handler /* Usage Fault Handler */
<> 150:02e0a0aed4ec 80 .long Default_Handler /* Reserved */
<> 150:02e0a0aed4ec 81 .long Default_Handler /* Reserved */
<> 150:02e0a0aed4ec 82 .long Default_Handler /* Reserved */
<> 150:02e0a0aed4ec 83 .long Default_Handler /* Reserved */
<> 150:02e0a0aed4ec 84 .long SVC_Handler /* SVCall Handler */
<> 150:02e0a0aed4ec 85 .long DebugMon_Handler /* Debug Monitor Handler */
<> 150:02e0a0aed4ec 86 .long Default_Handler /* Reserved */
<> 150:02e0a0aed4ec 87 .long PendSV_Handler /* PendSV Handler */
<> 150:02e0a0aed4ec 88 .long SysTick_Handler /* SysTick Handler */
<> 150:02e0a0aed4ec 89
<> 150:02e0a0aed4ec 90 /* External interrupts */
<> 150:02e0a0aed4ec 91
<> 150:02e0a0aed4ec 92 .long DMA_IRQHandler /* 0 - DMA */
<> 150:02e0a0aed4ec 93 .long GPIO_EVEN_IRQHandler /* 1 - GPIO_EVEN */
<> 150:02e0a0aed4ec 94 .long TIMER0_IRQHandler /* 2 - TIMER0 */
<> 150:02e0a0aed4ec 95 .long USART0_RX_IRQHandler /* 3 - USART0_RX */
<> 150:02e0a0aed4ec 96 .long USART0_TX_IRQHandler /* 4 - USART0_TX */
<> 150:02e0a0aed4ec 97 .long USB_IRQHandler /* 5 - USB */
<> 150:02e0a0aed4ec 98 .long ACMP0_IRQHandler /* 6 - ACMP0 */
<> 150:02e0a0aed4ec 99 .long ADC0_IRQHandler /* 7 - ADC0 */
<> 150:02e0a0aed4ec 100 .long DAC0_IRQHandler /* 8 - DAC0 */
<> 150:02e0a0aed4ec 101 .long I2C0_IRQHandler /* 9 - I2C0 */
<> 150:02e0a0aed4ec 102 .long I2C1_IRQHandler /* 10 - I2C1 */
<> 150:02e0a0aed4ec 103 .long GPIO_ODD_IRQHandler /* 11 - GPIO_ODD */
<> 150:02e0a0aed4ec 104 .long TIMER1_IRQHandler /* 12 - TIMER1 */
<> 150:02e0a0aed4ec 105 .long TIMER2_IRQHandler /* 13 - TIMER2 */
<> 150:02e0a0aed4ec 106 .long TIMER3_IRQHandler /* 14 - TIMER3 */
<> 150:02e0a0aed4ec 107 .long USART1_RX_IRQHandler /* 15 - USART1_RX */
<> 150:02e0a0aed4ec 108 .long USART1_TX_IRQHandler /* 16 - USART1_TX */
<> 150:02e0a0aed4ec 109 .long LESENSE_IRQHandler /* 17 - LESENSE */
<> 150:02e0a0aed4ec 110 .long USART2_RX_IRQHandler /* 18 - USART2_RX */
<> 150:02e0a0aed4ec 111 .long USART2_TX_IRQHandler /* 19 - USART2_TX */
<> 150:02e0a0aed4ec 112 .long UART0_RX_IRQHandler /* 20 - UART0_RX */
<> 150:02e0a0aed4ec 113 .long UART0_TX_IRQHandler /* 21 - UART0_TX */
<> 150:02e0a0aed4ec 114 .long UART1_RX_IRQHandler /* 22 - UART1_RX */
<> 150:02e0a0aed4ec 115 .long UART1_TX_IRQHandler /* 23 - UART1_TX */
<> 150:02e0a0aed4ec 116 .long LEUART0_IRQHandler /* 24 - LEUART0 */
<> 150:02e0a0aed4ec 117 .long LEUART1_IRQHandler /* 25 - LEUART1 */
<> 150:02e0a0aed4ec 118 .long LETIMER0_IRQHandler /* 26 - LETIMER0 */
<> 150:02e0a0aed4ec 119 .long PCNT0_IRQHandler /* 27 - PCNT0 */
<> 150:02e0a0aed4ec 120 .long PCNT1_IRQHandler /* 28 - PCNT1 */
<> 150:02e0a0aed4ec 121 .long PCNT2_IRQHandler /* 29 - PCNT2 */
<> 150:02e0a0aed4ec 122 .long RTC_IRQHandler /* 30 - RTC */
<> 150:02e0a0aed4ec 123 .long BURTC_IRQHandler /* 31 - BURTC */
<> 150:02e0a0aed4ec 124 .long CMU_IRQHandler /* 32 - CMU */
<> 150:02e0a0aed4ec 125 .long VCMP_IRQHandler /* 33 - VCMP */
<> 150:02e0a0aed4ec 126 .long LCD_IRQHandler /* 34 - LCD */
<> 150:02e0a0aed4ec 127 .long MSC_IRQHandler /* 35 - MSC */
<> 150:02e0a0aed4ec 128 .long AES_IRQHandler /* 36 - AES */
<> 150:02e0a0aed4ec 129 .long EBI_IRQHandler /* 37 - EBI */
<> 150:02e0a0aed4ec 130 .long EMU_IRQHandler /* 38 - EMU */
<> 150:02e0a0aed4ec 131 .long FPUEH_IRQHandler /* 39 - FPUEH */
<> 150:02e0a0aed4ec 132
<> 150:02e0a0aed4ec 133
<> 150:02e0a0aed4ec 134 .size __Vectors, . - __Vectors
<> 150:02e0a0aed4ec 135
<> 150:02e0a0aed4ec 136 .text
<> 150:02e0a0aed4ec 137 .thumb
<> 150:02e0a0aed4ec 138 .thumb_func
<> 150:02e0a0aed4ec 139 .align 2
<> 150:02e0a0aed4ec 140 .globl Reset_Handler
<> 150:02e0a0aed4ec 141 .type Reset_Handler, %function
<> 150:02e0a0aed4ec 142 Reset_Handler:
<> 150:02e0a0aed4ec 143 #ifndef __NO_SYSTEM_INIT
<> 150:02e0a0aed4ec 144 ldr r0, =SystemInit
<> 150:02e0a0aed4ec 145 blx r0
<> 150:02e0a0aed4ec 146 #endif
<> 150:02e0a0aed4ec 147
<> 150:02e0a0aed4ec 148 /* Firstly it copies data from read only memory to RAM. There are two schemes
<> 150:02e0a0aed4ec 149 * to copy. One can copy more than one sections. Another can only copy
<> 150:02e0a0aed4ec 150 * one section. The former scheme needs more instructions and read-only
<> 150:02e0a0aed4ec 151 * data to implement than the latter.
<> 150:02e0a0aed4ec 152 * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
<> 150:02e0a0aed4ec 153
<> 150:02e0a0aed4ec 154 #ifdef __STARTUP_COPY_MULTIPLE
<> 150:02e0a0aed4ec 155 /* Multiple sections scheme.
<> 150:02e0a0aed4ec 156 *
<> 150:02e0a0aed4ec 157 * Between symbol address __copy_table_start__ and __copy_table_end__,
<> 150:02e0a0aed4ec 158 * there are array of triplets, each of which specify:
<> 150:02e0a0aed4ec 159 * offset 0: LMA of start of a section to copy from
<> 150:02e0a0aed4ec 160 * offset 4: VMA of start of a section to copy to
<> 150:02e0a0aed4ec 161 * offset 8: size of the section to copy. Must be multiply of 4
<> 150:02e0a0aed4ec 162 *
<> 150:02e0a0aed4ec 163 * All addresses must be aligned to 4 bytes boundary.
<> 150:02e0a0aed4ec 164 */
<> 150:02e0a0aed4ec 165 ldr r4, =__copy_table_start__
<> 150:02e0a0aed4ec 166 ldr r5, =__copy_table_end__
<> 150:02e0a0aed4ec 167
<> 150:02e0a0aed4ec 168 .L_loop0:
<> 150:02e0a0aed4ec 169 cmp r4, r5
<> 150:02e0a0aed4ec 170 bge .L_loop0_done
<> 150:02e0a0aed4ec 171 ldr r1, [r4]
<> 150:02e0a0aed4ec 172 ldr r2, [r4, #4]
<> 150:02e0a0aed4ec 173 ldr r3, [r4, #8]
<> 150:02e0a0aed4ec 174
<> 150:02e0a0aed4ec 175 .L_loop0_0:
<> 150:02e0a0aed4ec 176 subs r3, #4
<> 150:02e0a0aed4ec 177 ittt ge
<> 150:02e0a0aed4ec 178 ldrge r0, [r1, r3]
<> 150:02e0a0aed4ec 179 strge r0, [r2, r3]
<> 150:02e0a0aed4ec 180 bge .L_loop0_0
<> 150:02e0a0aed4ec 181
<> 150:02e0a0aed4ec 182 adds r4, #12
<> 150:02e0a0aed4ec 183 b .L_loop0
<> 150:02e0a0aed4ec 184
<> 150:02e0a0aed4ec 185 .L_loop0_done:
<> 150:02e0a0aed4ec 186 #else
<> 150:02e0a0aed4ec 187 /* Single section scheme.
<> 150:02e0a0aed4ec 188 *
<> 150:02e0a0aed4ec 189 * The ranges of copy from/to are specified by following symbols
<> 150:02e0a0aed4ec 190 * __etext: LMA of start of the section to copy from. Usually end of text
<> 150:02e0a0aed4ec 191 * __data_start__: VMA of start of the section to copy to
<> 150:02e0a0aed4ec 192 * __data_end__: VMA of end of the section to copy to
<> 150:02e0a0aed4ec 193 *
<> 150:02e0a0aed4ec 194 * All addresses must be aligned to 4 bytes boundary.
<> 150:02e0a0aed4ec 195 */
<> 150:02e0a0aed4ec 196 ldr r1, =__etext
<> 150:02e0a0aed4ec 197 ldr r2, =__data_start__
<> 150:02e0a0aed4ec 198 ldr r3, =__data_end__
<> 150:02e0a0aed4ec 199
<> 150:02e0a0aed4ec 200 .L_loop1:
<> 150:02e0a0aed4ec 201 cmp r2, r3
<> 150:02e0a0aed4ec 202 ittt lt
<> 150:02e0a0aed4ec 203 ldrlt r0, [r1], #4
<> 150:02e0a0aed4ec 204 strlt r0, [r2], #4
<> 150:02e0a0aed4ec 205 blt .L_loop1
<> 150:02e0a0aed4ec 206 #endif /*__STARTUP_COPY_MULTIPLE */
<> 150:02e0a0aed4ec 207
<> 150:02e0a0aed4ec 208 /* This part of work usually is done in C library startup code. Otherwise,
<> 150:02e0a0aed4ec 209 * define this macro to enable it in this startup.
<> 150:02e0a0aed4ec 210 *
<> 150:02e0a0aed4ec 211 * There are two schemes too. One can clear multiple BSS sections. Another
<> 150:02e0a0aed4ec 212 * can only clear one section. The former is more size expensive than the
<> 150:02e0a0aed4ec 213 * latter.
<> 150:02e0a0aed4ec 214 *
<> 150:02e0a0aed4ec 215 * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
<> 150:02e0a0aed4ec 216 * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
<> 150:02e0a0aed4ec 217 */
<> 150:02e0a0aed4ec 218 #ifdef __STARTUP_CLEAR_BSS_MULTIPLE
<> 150:02e0a0aed4ec 219 /* Multiple sections scheme.
<> 150:02e0a0aed4ec 220 *
<> 150:02e0a0aed4ec 221 * Between symbol address __copy_table_start__ and __copy_table_end__,
<> 150:02e0a0aed4ec 222 * there are array of tuples specifying:
<> 150:02e0a0aed4ec 223 * offset 0: Start of a BSS section
<> 150:02e0a0aed4ec 224 * offset 4: Size of this BSS section. Must be multiply of 4
<> 150:02e0a0aed4ec 225 */
<> 150:02e0a0aed4ec 226 ldr r3, =__zero_table_start__
<> 150:02e0a0aed4ec 227 ldr r4, =__zero_table_end__
<> 150:02e0a0aed4ec 228
<> 150:02e0a0aed4ec 229 .L_loop2:
<> 150:02e0a0aed4ec 230 cmp r3, r4
<> 150:02e0a0aed4ec 231 bge .L_loop2_done
<> 150:02e0a0aed4ec 232 ldr r1, [r3]
<> 150:02e0a0aed4ec 233 ldr r2, [r3, #4]
<> 150:02e0a0aed4ec 234 movs r0, 0
<> 150:02e0a0aed4ec 235
<> 150:02e0a0aed4ec 236 .L_loop2_0:
<> 150:02e0a0aed4ec 237 subs r2, #4
<> 150:02e0a0aed4ec 238 itt ge
<> 150:02e0a0aed4ec 239 strge r0, [r1, r2]
<> 150:02e0a0aed4ec 240 bge .L_loop2_0
<> 150:02e0a0aed4ec 241 adds r3, #8
<> 150:02e0a0aed4ec 242 b .L_loop2
<> 150:02e0a0aed4ec 243 .L_loop2_done:
<> 150:02e0a0aed4ec 244 #elif defined (__STARTUP_CLEAR_BSS)
<> 150:02e0a0aed4ec 245 /* Single BSS section scheme.
<> 150:02e0a0aed4ec 246 *
<> 150:02e0a0aed4ec 247 * The BSS section is specified by following symbols
<> 150:02e0a0aed4ec 248 * __bss_start__: start of the BSS section.
<> 150:02e0a0aed4ec 249 * __bss_end__: end of the BSS section.
<> 150:02e0a0aed4ec 250 *
<> 150:02e0a0aed4ec 251 * Both addresses must be aligned to 4 bytes boundary.
<> 150:02e0a0aed4ec 252 */
<> 150:02e0a0aed4ec 253 ldr r1, =__bss_start__
<> 150:02e0a0aed4ec 254 ldr r2, =__bss_end__
<> 150:02e0a0aed4ec 255
<> 150:02e0a0aed4ec 256 movs r0, 0
<> 150:02e0a0aed4ec 257 .L_loop3:
<> 150:02e0a0aed4ec 258 cmp r1, r2
<> 150:02e0a0aed4ec 259 itt lt
<> 150:02e0a0aed4ec 260 strlt r0, [r1], #4
<> 150:02e0a0aed4ec 261 blt .L_loop3
<> 150:02e0a0aed4ec 262 #endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
<> 150:02e0a0aed4ec 263
<> 150:02e0a0aed4ec 264 #ifndef __START
<> 150:02e0a0aed4ec 265 #define __START _start
<> 150:02e0a0aed4ec 266 #endif
<> 150:02e0a0aed4ec 267 bl __START
<> 150:02e0a0aed4ec 268
<> 150:02e0a0aed4ec 269 .pool
<> 150:02e0a0aed4ec 270 .size Reset_Handler, . - Reset_Handler
<> 150:02e0a0aed4ec 271
<> 150:02e0a0aed4ec 272 .align 1
<> 150:02e0a0aed4ec 273 .thumb_func
<> 150:02e0a0aed4ec 274 .weak Default_Handler
<> 150:02e0a0aed4ec 275 .type Default_Handler, %function
<> 150:02e0a0aed4ec 276 Default_Handler:
<> 150:02e0a0aed4ec 277 b .
<> 150:02e0a0aed4ec 278 .size Default_Handler, . - Default_Handler
<> 150:02e0a0aed4ec 279
<> 150:02e0a0aed4ec 280 /* Macro to define default handlers. Default handler
<> 150:02e0a0aed4ec 281 * will be weak symbol and just dead loops. They can be
<> 150:02e0a0aed4ec 282 * overwritten by other handlers */
<> 150:02e0a0aed4ec 283 .macro def_irq_handler handler_name
<> 150:02e0a0aed4ec 284 .weak \handler_name
<> 150:02e0a0aed4ec 285 .set \handler_name, Default_Handler
<> 150:02e0a0aed4ec 286 .endm
<> 150:02e0a0aed4ec 287
<> 150:02e0a0aed4ec 288 def_irq_handler NMI_Handler
<> 150:02e0a0aed4ec 289 def_irq_handler HardFault_Handler
<> 150:02e0a0aed4ec 290 def_irq_handler MemManage_Handler
<> 150:02e0a0aed4ec 291 def_irq_handler BusFault_Handler
<> 150:02e0a0aed4ec 292 def_irq_handler UsageFault_Handler
<> 150:02e0a0aed4ec 293 def_irq_handler SVC_Handler
<> 150:02e0a0aed4ec 294 def_irq_handler DebugMon_Handler
<> 150:02e0a0aed4ec 295 def_irq_handler PendSV_Handler
<> 150:02e0a0aed4ec 296 def_irq_handler SysTick_Handler
<> 150:02e0a0aed4ec 297
<> 150:02e0a0aed4ec 298 def_irq_handler DMA_IRQHandler
<> 150:02e0a0aed4ec 299 def_irq_handler GPIO_EVEN_IRQHandler
<> 150:02e0a0aed4ec 300 def_irq_handler TIMER0_IRQHandler
<> 150:02e0a0aed4ec 301 def_irq_handler USART0_RX_IRQHandler
<> 150:02e0a0aed4ec 302 def_irq_handler USART0_TX_IRQHandler
<> 150:02e0a0aed4ec 303 def_irq_handler USB_IRQHandler
<> 150:02e0a0aed4ec 304 def_irq_handler ACMP0_IRQHandler
<> 150:02e0a0aed4ec 305 def_irq_handler ADC0_IRQHandler
<> 150:02e0a0aed4ec 306 def_irq_handler DAC0_IRQHandler
<> 150:02e0a0aed4ec 307 def_irq_handler I2C0_IRQHandler
<> 150:02e0a0aed4ec 308 def_irq_handler I2C1_IRQHandler
<> 150:02e0a0aed4ec 309 def_irq_handler GPIO_ODD_IRQHandler
<> 150:02e0a0aed4ec 310 def_irq_handler TIMER1_IRQHandler
<> 150:02e0a0aed4ec 311 def_irq_handler TIMER2_IRQHandler
<> 150:02e0a0aed4ec 312 def_irq_handler TIMER3_IRQHandler
<> 150:02e0a0aed4ec 313 def_irq_handler USART1_RX_IRQHandler
<> 150:02e0a0aed4ec 314 def_irq_handler USART1_TX_IRQHandler
<> 150:02e0a0aed4ec 315 def_irq_handler LESENSE_IRQHandler
<> 150:02e0a0aed4ec 316 def_irq_handler USART2_RX_IRQHandler
<> 150:02e0a0aed4ec 317 def_irq_handler USART2_TX_IRQHandler
<> 150:02e0a0aed4ec 318 def_irq_handler UART0_RX_IRQHandler
<> 150:02e0a0aed4ec 319 def_irq_handler UART0_TX_IRQHandler
<> 150:02e0a0aed4ec 320 def_irq_handler UART1_RX_IRQHandler
<> 150:02e0a0aed4ec 321 def_irq_handler UART1_TX_IRQHandler
<> 150:02e0a0aed4ec 322 def_irq_handler LEUART0_IRQHandler
<> 150:02e0a0aed4ec 323 def_irq_handler LEUART1_IRQHandler
<> 150:02e0a0aed4ec 324 def_irq_handler LETIMER0_IRQHandler
<> 150:02e0a0aed4ec 325 def_irq_handler PCNT0_IRQHandler
<> 150:02e0a0aed4ec 326 def_irq_handler PCNT1_IRQHandler
<> 150:02e0a0aed4ec 327 def_irq_handler PCNT2_IRQHandler
<> 150:02e0a0aed4ec 328 def_irq_handler RTC_IRQHandler
<> 150:02e0a0aed4ec 329 def_irq_handler BURTC_IRQHandler
<> 150:02e0a0aed4ec 330 def_irq_handler CMU_IRQHandler
<> 150:02e0a0aed4ec 331 def_irq_handler VCMP_IRQHandler
<> 150:02e0a0aed4ec 332 def_irq_handler LCD_IRQHandler
<> 150:02e0a0aed4ec 333 def_irq_handler MSC_IRQHandler
<> 150:02e0a0aed4ec 334 def_irq_handler AES_IRQHandler
<> 150:02e0a0aed4ec 335 def_irq_handler EBI_IRQHandler
<> 150:02e0a0aed4ec 336 def_irq_handler EMU_IRQHandler
<> 150:02e0a0aed4ec 337 def_irq_handler FPUEH_IRQHandler
<> 150:02e0a0aed4ec 338
<> 150:02e0a0aed4ec 339
<> 150:02e0a0aed4ec 340 .end