Fawwaz Nadzmy / mbed-STM

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/TARGET_256K/TOOLCHAIN_ARM_STD/startup_efm32wg.S@153:9398a535854b, 2016-12-22 (annotated)

Committer:
fwndz
Date:
Thu Dec 22 05:12:40 2016 +0000
Revision:
153:9398a535854b
Parent:
150:02e0a0aed4ec 
device target maximize

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 150:02e0a0aed4ec 1 ;/**************************************************************************//**
<> 150:02e0a0aed4ec 2 ; * @file startup_efm32wg.s
<> 150:02e0a0aed4ec 3 ; * @brief CMSIS Core Device Startup File for
<> 150:02e0a0aed4ec 4 ; * Silicon Labs EFM32WG Device Series
<> 150:02e0a0aed4ec 5 ; * @version 4.2.1
<> 150:02e0a0aed4ec 6 ; * @date 03. February 2012
<> 150:02e0a0aed4ec 7 ; *
<> 150:02e0a0aed4ec 8 ; * @note
<> 150:02e0a0aed4ec 9 ; * Copyright (C) 2012 ARM Limited. All rights reserved.
<> 150:02e0a0aed4ec 10 ; *
<> 150:02e0a0aed4ec 11 ; * @par
<> 150:02e0a0aed4ec 12 ; * ARM Limited (ARM) is supplying this software for use with Cortex-M
<> 150:02e0a0aed4ec 13 ; * processor based microcontrollers. This file can be freely distributed
<> 150:02e0a0aed4ec 14 ; * within development tools that are supporting such ARM based processors.
<> 150:02e0a0aed4ec 15 ; *
<> 150:02e0a0aed4ec 16 ; * @par
<> 150:02e0a0aed4ec 17 ; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 150:02e0a0aed4ec 18 ; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 150:02e0a0aed4ec 19 ; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 150:02e0a0aed4ec 20 ; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
<> 150:02e0a0aed4ec 21 ; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 150:02e0a0aed4ec 22 ; *
<> 150:02e0a0aed4ec 23 ; ******************************************************************************/
<> 150:02e0a0aed4ec 24 ;/*
<> 150:02e0a0aed4ec 25 ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
<> 150:02e0a0aed4ec 26 ;*/
<> 150:02e0a0aed4ec 27
<> 150:02e0a0aed4ec 28 ; <h> Stack Configuration
<> 150:02e0a0aed4ec 29 ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
<> 150:02e0a0aed4ec 30 ; </h>
<> 150:02e0a0aed4ec 31
<> 150:02e0a0aed4ec 32 Stack_Size EQU 0x00000400
<> 150:02e0a0aed4ec 33
<> 150:02e0a0aed4ec 34 AREA STACK, NOINIT, READWRITE, ALIGN=3
<> 150:02e0a0aed4ec 35 Stack_Mem SPACE Stack_Size
<> 150:02e0a0aed4ec 36 __initial_sp EQU 0x20008000
<> 150:02e0a0aed4ec 37
<> 150:02e0a0aed4ec 38
<> 150:02e0a0aed4ec 39 ; <h> Heap Configuration
<> 150:02e0a0aed4ec 40 ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
<> 150:02e0a0aed4ec 41 ; </h>
<> 150:02e0a0aed4ec 42
<> 150:02e0a0aed4ec 43 Heap_Size EQU 0x00000C00
<> 150:02e0a0aed4ec 44
<> 150:02e0a0aed4ec 45 AREA HEAP, NOINIT, READWRITE, ALIGN=3
<> 150:02e0a0aed4ec 46 __heap_base
<> 150:02e0a0aed4ec 47 Heap_Mem SPACE Heap_Size
<> 150:02e0a0aed4ec 48 __heap_limit
<> 150:02e0a0aed4ec 49
<> 150:02e0a0aed4ec 50
<> 150:02e0a0aed4ec 51 PRESERVE8
<> 150:02e0a0aed4ec 52 THUMB
<> 150:02e0a0aed4ec 53
<> 150:02e0a0aed4ec 54
<> 150:02e0a0aed4ec 55 ; Vector Table Mapped to Address 0 at Reset
<> 150:02e0a0aed4ec 56
<> 150:02e0a0aed4ec 57 AREA RESET, DATA, READONLY, ALIGN=8
<> 150:02e0a0aed4ec 58 EXPORT __Vectors
<> 150:02e0a0aed4ec 59 EXPORT __Vectors_End
<> 150:02e0a0aed4ec 60 EXPORT __Vectors_Size
<> 150:02e0a0aed4ec 61
<> 150:02e0a0aed4ec 62 __Vectors DCD __initial_sp ; Top of Stack
<> 150:02e0a0aed4ec 63 DCD Reset_Handler ; Reset Handler
<> 150:02e0a0aed4ec 64 DCD NMI_Handler ; NMI Handler
<> 150:02e0a0aed4ec 65 DCD HardFault_Handler ; Hard Fault Handler
<> 150:02e0a0aed4ec 66 DCD MemManage_Handler ; MPU Fault Handler
<> 150:02e0a0aed4ec 67 DCD BusFault_Handler ; Bus Fault Handler
<> 150:02e0a0aed4ec 68 DCD UsageFault_Handler ; Usage Fault Handler
<> 150:02e0a0aed4ec 69 DCD 0 ; Reserved
<> 150:02e0a0aed4ec 70 DCD 0 ; Reserved
<> 150:02e0a0aed4ec 71 DCD 0 ; Reserved
<> 150:02e0a0aed4ec 72 DCD 0 ; Reserved
<> 150:02e0a0aed4ec 73 DCD SVC_Handler ; SVCall Handler
<> 150:02e0a0aed4ec 74 DCD DebugMon_Handler ; Debug Monitor Handler
<> 150:02e0a0aed4ec 75 DCD 0 ; Reserved
<> 150:02e0a0aed4ec 76 DCD PendSV_Handler ; PendSV Handler
<> 150:02e0a0aed4ec 77 DCD SysTick_Handler ; SysTick Handler
<> 150:02e0a0aed4ec 78
<> 150:02e0a0aed4ec 79 ; External Interrupts
<> 150:02e0a0aed4ec 80
<> 150:02e0a0aed4ec 81 DCD DMA_IRQHandler ; 0: DMA Interrupt
<> 150:02e0a0aed4ec 82 DCD GPIO_EVEN_IRQHandler ; 1: GPIO_EVEN Interrupt
<> 150:02e0a0aed4ec 83 DCD TIMER0_IRQHandler ; 2: TIMER0 Interrupt
<> 150:02e0a0aed4ec 84 DCD USART0_RX_IRQHandler ; 3: USART0_RX Interrupt
<> 150:02e0a0aed4ec 85 DCD USART0_TX_IRQHandler ; 4: USART0_TX Interrupt
<> 150:02e0a0aed4ec 86 DCD USB_IRQHandler ; 5: USB Interrupt
<> 150:02e0a0aed4ec 87 DCD ACMP0_IRQHandler ; 6: ACMP0 Interrupt
<> 150:02e0a0aed4ec 88 DCD ADC0_IRQHandler ; 7: ADC0 Interrupt
<> 150:02e0a0aed4ec 89 DCD DAC0_IRQHandler ; 8: DAC0 Interrupt
<> 150:02e0a0aed4ec 90 DCD I2C0_IRQHandler ; 9: I2C0 Interrupt
<> 150:02e0a0aed4ec 91 DCD I2C1_IRQHandler ; 10: I2C1 Interrupt
<> 150:02e0a0aed4ec 92 DCD GPIO_ODD_IRQHandler ; 11: GPIO_ODD Interrupt
<> 150:02e0a0aed4ec 93 DCD TIMER1_IRQHandler ; 12: TIMER1 Interrupt
<> 150:02e0a0aed4ec 94 DCD TIMER2_IRQHandler ; 13: TIMER2 Interrupt
<> 150:02e0a0aed4ec 95 DCD TIMER3_IRQHandler ; 14: TIMER3 Interrupt
<> 150:02e0a0aed4ec 96 DCD USART1_RX_IRQHandler ; 15: USART1_RX Interrupt
<> 150:02e0a0aed4ec 97 DCD USART1_TX_IRQHandler ; 16: USART1_TX Interrupt
<> 150:02e0a0aed4ec 98 DCD LESENSE_IRQHandler ; 17: LESENSE Interrupt
<> 150:02e0a0aed4ec 99 DCD USART2_RX_IRQHandler ; 18: USART2_RX Interrupt
<> 150:02e0a0aed4ec 100 DCD USART2_TX_IRQHandler ; 19: USART2_TX Interrupt
<> 150:02e0a0aed4ec 101 DCD UART0_RX_IRQHandler ; 20: UART0_RX Interrupt
<> 150:02e0a0aed4ec 102 DCD UART0_TX_IRQHandler ; 21: UART0_TX Interrupt
<> 150:02e0a0aed4ec 103 DCD UART1_RX_IRQHandler ; 22: UART1_RX Interrupt
<> 150:02e0a0aed4ec 104 DCD UART1_TX_IRQHandler ; 23: UART1_TX Interrupt
<> 150:02e0a0aed4ec 105 DCD LEUART0_IRQHandler ; 24: LEUART0 Interrupt
<> 150:02e0a0aed4ec 106 DCD LEUART1_IRQHandler ; 25: LEUART1 Interrupt
<> 150:02e0a0aed4ec 107 DCD LETIMER0_IRQHandler ; 26: LETIMER0 Interrupt
<> 150:02e0a0aed4ec 108 DCD PCNT0_IRQHandler ; 27: PCNT0 Interrupt
<> 150:02e0a0aed4ec 109 DCD PCNT1_IRQHandler ; 28: PCNT1 Interrupt
<> 150:02e0a0aed4ec 110 DCD PCNT2_IRQHandler ; 29: PCNT2 Interrupt
<> 150:02e0a0aed4ec 111 DCD RTC_IRQHandler ; 30: RTC Interrupt
<> 150:02e0a0aed4ec 112 DCD BURTC_IRQHandler ; 31: BURTC Interrupt
<> 150:02e0a0aed4ec 113 DCD CMU_IRQHandler ; 32: CMU Interrupt
<> 150:02e0a0aed4ec 114 DCD VCMP_IRQHandler ; 33: VCMP Interrupt
<> 150:02e0a0aed4ec 115 DCD LCD_IRQHandler ; 34: LCD Interrupt
<> 150:02e0a0aed4ec 116 DCD MSC_IRQHandler ; 35: MSC Interrupt
<> 150:02e0a0aed4ec 117 DCD AES_IRQHandler ; 36: AES Interrupt
<> 150:02e0a0aed4ec 118 DCD EBI_IRQHandler ; 37: EBI Interrupt
<> 150:02e0a0aed4ec 119 DCD EMU_IRQHandler ; 38: EMU Interrupt
<> 150:02e0a0aed4ec 120 DCD FPUEH_IRQHandler ; 39: FPUEH Interrupt
<> 150:02e0a0aed4ec 121
<> 150:02e0a0aed4ec 122 __Vectors_End
<> 150:02e0a0aed4ec 123 __Vectors_Size EQU __Vectors_End - __Vectors
<> 150:02e0a0aed4ec 124
<> 150:02e0a0aed4ec 125 AREA |.text|, CODE, READONLY
<> 150:02e0a0aed4ec 126
<> 150:02e0a0aed4ec 127
<> 150:02e0a0aed4ec 128 ; Reset Handler
<> 150:02e0a0aed4ec 129
<> 150:02e0a0aed4ec 130 Reset_Handler PROC
<> 150:02e0a0aed4ec 131 EXPORT Reset_Handler [WEAK]
<> 150:02e0a0aed4ec 132 IMPORT SystemInit
<> 150:02e0a0aed4ec 133 IMPORT __main
<> 150:02e0a0aed4ec 134 LDR R0, =SystemInit
<> 150:02e0a0aed4ec 135 BLX R0
<> 150:02e0a0aed4ec 136 LDR R0, =__main
<> 150:02e0a0aed4ec 137 BX R0
<> 150:02e0a0aed4ec 138 ENDP
<> 150:02e0a0aed4ec 139
<> 150:02e0a0aed4ec 140
<> 150:02e0a0aed4ec 141 ; Dummy Exception Handlers (infinite loops which can be modified)
<> 150:02e0a0aed4ec 142
<> 150:02e0a0aed4ec 143 NMI_Handler PROC
<> 150:02e0a0aed4ec 144 EXPORT NMI_Handler [WEAK]
<> 150:02e0a0aed4ec 145 B .
<> 150:02e0a0aed4ec 146 ENDP
<> 150:02e0a0aed4ec 147 HardFault_Handler\
<> 150:02e0a0aed4ec 148 PROC
<> 150:02e0a0aed4ec 149 EXPORT HardFault_Handler [WEAK]
<> 150:02e0a0aed4ec 150 B .
<> 150:02e0a0aed4ec 151 ENDP
<> 150:02e0a0aed4ec 152 MemManage_Handler\
<> 150:02e0a0aed4ec 153 PROC
<> 150:02e0a0aed4ec 154 EXPORT MemManage_Handler [WEAK]
<> 150:02e0a0aed4ec 155 B .
<> 150:02e0a0aed4ec 156 ENDP
<> 150:02e0a0aed4ec 157 BusFault_Handler\
<> 150:02e0a0aed4ec 158 PROC
<> 150:02e0a0aed4ec 159 EXPORT BusFault_Handler [WEAK]
<> 150:02e0a0aed4ec 160 B .
<> 150:02e0a0aed4ec 161 ENDP
<> 150:02e0a0aed4ec 162 UsageFault_Handler\
<> 150:02e0a0aed4ec 163 PROC
<> 150:02e0a0aed4ec 164 EXPORT UsageFault_Handler [WEAK]
<> 150:02e0a0aed4ec 165 B .
<> 150:02e0a0aed4ec 166 ENDP
<> 150:02e0a0aed4ec 167 SVC_Handler PROC
<> 150:02e0a0aed4ec 168 EXPORT SVC_Handler [WEAK]
<> 150:02e0a0aed4ec 169 B .
<> 150:02e0a0aed4ec 170 ENDP
<> 150:02e0a0aed4ec 171 DebugMon_Handler\
<> 150:02e0a0aed4ec 172 PROC
<> 150:02e0a0aed4ec 173 EXPORT DebugMon_Handler [WEAK]
<> 150:02e0a0aed4ec 174 B .
<> 150:02e0a0aed4ec 175 ENDP
<> 150:02e0a0aed4ec 176 PendSV_Handler PROC
<> 150:02e0a0aed4ec 177 EXPORT PendSV_Handler [WEAK]
<> 150:02e0a0aed4ec 178 B .
<> 150:02e0a0aed4ec 179 ENDP
<> 150:02e0a0aed4ec 180 SysTick_Handler PROC
<> 150:02e0a0aed4ec 181 EXPORT SysTick_Handler [WEAK]
<> 150:02e0a0aed4ec 182 B .
<> 150:02e0a0aed4ec 183 ENDP
<> 150:02e0a0aed4ec 184
<> 150:02e0a0aed4ec 185 Default_Handler PROC
<> 150:02e0a0aed4ec 186 EXPORT DMA_IRQHandler [WEAK]
<> 150:02e0a0aed4ec 187 EXPORT GPIO_EVEN_IRQHandler [WEAK]
<> 150:02e0a0aed4ec 188 EXPORT TIMER0_IRQHandler [WEAK]
<> 150:02e0a0aed4ec 189 EXPORT USART0_RX_IRQHandler [WEAK]
<> 150:02e0a0aed4ec 190 EXPORT USART0_TX_IRQHandler [WEAK]
<> 150:02e0a0aed4ec 191 EXPORT USB_IRQHandler [WEAK]
<> 150:02e0a0aed4ec 192 EXPORT ACMP0_IRQHandler [WEAK]
<> 150:02e0a0aed4ec 193 EXPORT ADC0_IRQHandler [WEAK]
<> 150:02e0a0aed4ec 194 EXPORT DAC0_IRQHandler [WEAK]
<> 150:02e0a0aed4ec 195 EXPORT I2C0_IRQHandler [WEAK]
<> 150:02e0a0aed4ec 196 EXPORT I2C1_IRQHandler [WEAK]
<> 150:02e0a0aed4ec 197 EXPORT GPIO_ODD_IRQHandler [WEAK]
<> 150:02e0a0aed4ec 198 EXPORT TIMER1_IRQHandler [WEAK]
<> 150:02e0a0aed4ec 199 EXPORT TIMER2_IRQHandler [WEAK]
<> 150:02e0a0aed4ec 200 EXPORT TIMER3_IRQHandler [WEAK]
<> 150:02e0a0aed4ec 201 EXPORT USART1_RX_IRQHandler [WEAK]
<> 150:02e0a0aed4ec 202 EXPORT USART1_TX_IRQHandler [WEAK]
<> 150:02e0a0aed4ec 203 EXPORT LESENSE_IRQHandler [WEAK]
<> 150:02e0a0aed4ec 204 EXPORT USART2_RX_IRQHandler [WEAK]
<> 150:02e0a0aed4ec 205 EXPORT USART2_TX_IRQHandler [WEAK]
<> 150:02e0a0aed4ec 206 EXPORT UART0_RX_IRQHandler [WEAK]
<> 150:02e0a0aed4ec 207 EXPORT UART0_TX_IRQHandler [WEAK]
<> 150:02e0a0aed4ec 208 EXPORT UART1_RX_IRQHandler [WEAK]
<> 150:02e0a0aed4ec 209 EXPORT UART1_TX_IRQHandler [WEAK]
<> 150:02e0a0aed4ec 210 EXPORT LEUART0_IRQHandler [WEAK]
<> 150:02e0a0aed4ec 211 EXPORT LEUART1_IRQHandler [WEAK]
<> 150:02e0a0aed4ec 212 EXPORT LETIMER0_IRQHandler [WEAK]
<> 150:02e0a0aed4ec 213 EXPORT PCNT0_IRQHandler [WEAK]
<> 150:02e0a0aed4ec 214 EXPORT PCNT1_IRQHandler [WEAK]
<> 150:02e0a0aed4ec 215 EXPORT PCNT2_IRQHandler [WEAK]
<> 150:02e0a0aed4ec 216 EXPORT RTC_IRQHandler [WEAK]
<> 150:02e0a0aed4ec 217 EXPORT BURTC_IRQHandler [WEAK]
<> 150:02e0a0aed4ec 218 EXPORT CMU_IRQHandler [WEAK]
<> 150:02e0a0aed4ec 219 EXPORT VCMP_IRQHandler [WEAK]
<> 150:02e0a0aed4ec 220 EXPORT LCD_IRQHandler [WEAK]
<> 150:02e0a0aed4ec 221 EXPORT MSC_IRQHandler [WEAK]
<> 150:02e0a0aed4ec 222 EXPORT AES_IRQHandler [WEAK]
<> 150:02e0a0aed4ec 223 EXPORT EBI_IRQHandler [WEAK]
<> 150:02e0a0aed4ec 224 EXPORT EMU_IRQHandler [WEAK]
<> 150:02e0a0aed4ec 225 EXPORT FPUEH_IRQHandler [WEAK]
<> 150:02e0a0aed4ec 226
<> 150:02e0a0aed4ec 227
<> 150:02e0a0aed4ec 228 DMA_IRQHandler
<> 150:02e0a0aed4ec 229 GPIO_EVEN_IRQHandler
<> 150:02e0a0aed4ec 230 TIMER0_IRQHandler
<> 150:02e0a0aed4ec 231 USART0_RX_IRQHandler
<> 150:02e0a0aed4ec 232 USART0_TX_IRQHandler
<> 150:02e0a0aed4ec 233 USB_IRQHandler
<> 150:02e0a0aed4ec 234 ACMP0_IRQHandler
<> 150:02e0a0aed4ec 235 ADC0_IRQHandler
<> 150:02e0a0aed4ec 236 DAC0_IRQHandler
<> 150:02e0a0aed4ec 237 I2C0_IRQHandler
<> 150:02e0a0aed4ec 238 I2C1_IRQHandler
<> 150:02e0a0aed4ec 239 GPIO_ODD_IRQHandler
<> 150:02e0a0aed4ec 240 TIMER1_IRQHandler
<> 150:02e0a0aed4ec 241 TIMER2_IRQHandler
<> 150:02e0a0aed4ec 242 TIMER3_IRQHandler
<> 150:02e0a0aed4ec 243 USART1_RX_IRQHandler
<> 150:02e0a0aed4ec 244 USART1_TX_IRQHandler
<> 150:02e0a0aed4ec 245 LESENSE_IRQHandler
<> 150:02e0a0aed4ec 246 USART2_RX_IRQHandler
<> 150:02e0a0aed4ec 247 USART2_TX_IRQHandler
<> 150:02e0a0aed4ec 248 UART0_RX_IRQHandler
<> 150:02e0a0aed4ec 249 UART0_TX_IRQHandler
<> 150:02e0a0aed4ec 250 UART1_RX_IRQHandler
<> 150:02e0a0aed4ec 251 UART1_TX_IRQHandler
<> 150:02e0a0aed4ec 252 LEUART0_IRQHandler
<> 150:02e0a0aed4ec 253 LEUART1_IRQHandler
<> 150:02e0a0aed4ec 254 LETIMER0_IRQHandler
<> 150:02e0a0aed4ec 255 PCNT0_IRQHandler
<> 150:02e0a0aed4ec 256 PCNT1_IRQHandler
<> 150:02e0a0aed4ec 257 PCNT2_IRQHandler
<> 150:02e0a0aed4ec 258 RTC_IRQHandler
<> 150:02e0a0aed4ec 259 BURTC_IRQHandler
<> 150:02e0a0aed4ec 260 CMU_IRQHandler
<> 150:02e0a0aed4ec 261 VCMP_IRQHandler
<> 150:02e0a0aed4ec 262 LCD_IRQHandler
<> 150:02e0a0aed4ec 263 MSC_IRQHandler
<> 150:02e0a0aed4ec 264 AES_IRQHandler
<> 150:02e0a0aed4ec 265 EBI_IRQHandler
<> 150:02e0a0aed4ec 266 EMU_IRQHandler
<> 150:02e0a0aed4ec 267 FPUEH_IRQHandler
<> 150:02e0a0aed4ec 268 B .
<> 150:02e0a0aed4ec 269 ENDP
<> 150:02e0a0aed4ec 270
<> 150:02e0a0aed4ec 271 ALIGN
<> 150:02e0a0aed4ec 272
<> 150:02e0a0aed4ec 273 ; User Initial Stack & Heap
<> 150:02e0a0aed4ec 274
<> 150:02e0a0aed4ec 275 IMPORT __use_two_region_memory
<> 150:02e0a0aed4ec 276 EXPORT __user_initial_stackheap
<> 150:02e0a0aed4ec 277
<> 150:02e0a0aed4ec 278 __user_initial_stackheap PROC
<> 150:02e0a0aed4ec 279 LDR R0, = Heap_Mem
<> 150:02e0a0aed4ec 280 LDR R1, =(Stack_Mem + Stack_Size)
<> 150:02e0a0aed4ec 281 LDR R2, = (Heap_Mem + Heap_Size)
<> 150:02e0a0aed4ec 282 LDR R3, = Stack_Mem
<> 150:02e0a0aed4ec 283 BX LR
<> 150:02e0a0aed4ec 284 ENDP
<> 150:02e0a0aed4ec 285
<> 150:02e0a0aed4ec 286 ALIGN
<> 150:02e0a0aed4ec 287
<> 150:02e0a0aed4ec 288 END