Fawwaz Nadzmy / mbed-STM

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_can.c@153:9398a535854b, 2016-12-22 (annotated)

Committer:
fwndz
Date:
Thu Dec 22 05:12:40 2016 +0000
Revision:
153:9398a535854b
Parent:
149:156823d33999 
device target maximize

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f7xx_hal_can.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.1.0
<> 144:ef7eb2e8f9f7 6 * @date 22-April-2016
<> 144:ef7eb2e8f9f7 7 * @brief CAN HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the Controller Area Network (CAN) peripheral:
<> 144:ef7eb2e8f9f7 10 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 11 * + IO operation functions
<> 144:ef7eb2e8f9f7 12 * + Peripheral Control functions
<> 144:ef7eb2e8f9f7 13 * + Peripheral State and Error functions
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 @verbatim
<> 144:ef7eb2e8f9f7 16 ==============================================================================
<> 144:ef7eb2e8f9f7 17 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 18 ==============================================================================
<> 144:ef7eb2e8f9f7 19 [..]
<> 144:ef7eb2e8f9f7 20 (#) Enable the CAN controller interface clock using
<> 144:ef7eb2e8f9f7 21 __HAL_RCC_CAN1_CLK_ENABLE() for CAN1, __HAL_RCC_CAN2_CLK_ENABLE() for CAN2
<> 144:ef7eb2e8f9f7 22 and __HAL_RCC_CAN3_CLK_ENABLE() for CAN3
<> 144:ef7eb2e8f9f7 23 -@- In case you are using CAN2 only, you have to enable the CAN1 clock.
<> 144:ef7eb2e8f9f7 24
<> 144:ef7eb2e8f9f7 25 (#) CAN pins configuration
<> 144:ef7eb2e8f9f7 26 (++) Enable the clock for the CAN GPIOs using the following function:
<> 144:ef7eb2e8f9f7 27 __HAL_RCC_GPIOx_CLK_ENABLE()
<> 144:ef7eb2e8f9f7 28 (++) Connect and configure the involved CAN pins to AF9 using the
<> 144:ef7eb2e8f9f7 29 following function HAL_GPIO_Init()
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 (#) Initialize and configure the CAN using HAL_CAN_Init() function.
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 (#) Transmit the desired CAN frame using HAL_CAN_Transmit() function.
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 (#) Or transmit the desired CAN frame using HAL_CAN_Transmit_IT() function.
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 (#) Receive a CAN frame using HAL_CAN_Receive() function.
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 (#) Or receive a CAN frame using HAL_CAN_Receive_IT() function.
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 *** Polling mode IO operation ***
<> 144:ef7eb2e8f9f7 42 =================================
<> 144:ef7eb2e8f9f7 43 [..]
<> 144:ef7eb2e8f9f7 44 (+) Start the CAN peripheral transmission and wait the end of this operation
<> 144:ef7eb2e8f9f7 45 using HAL_CAN_Transmit(), at this stage user can specify the value of timeout
<> 144:ef7eb2e8f9f7 46 according to his end application
<> 144:ef7eb2e8f9f7 47 (+) Start the CAN peripheral reception and wait the end of this operation
<> 144:ef7eb2e8f9f7 48 using HAL_CAN_Receive(), at this stage user can specify the value of timeout
<> 144:ef7eb2e8f9f7 49 according to his end application
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 *** Interrupt mode IO operation ***
<> 144:ef7eb2e8f9f7 52 ===================================
<> 144:ef7eb2e8f9f7 53 [..]
<> 144:ef7eb2e8f9f7 54 (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT()
<> 144:ef7eb2e8f9f7 55 (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT()
<> 144:ef7eb2e8f9f7 56 (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine
<> 144:ef7eb2e8f9f7 57 (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can
<> 144:ef7eb2e8f9f7 58 add his own code by customization of function pointer HAL_CAN_TxCpltCallback
<> 144:ef7eb2e8f9f7 59 (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can
<> 144:ef7eb2e8f9f7 60 add his own code by customization of function pointer HAL_CAN_ErrorCallback
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 *** CAN HAL driver macros list ***
<> 144:ef7eb2e8f9f7 63 =============================================
<> 144:ef7eb2e8f9f7 64 [..]
<> 144:ef7eb2e8f9f7 65 Below the list of most used macros in CAN HAL driver.
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts
<> 144:ef7eb2e8f9f7 68 (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts
<> 144:ef7eb2e8f9f7 69 (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled
<> 144:ef7eb2e8f9f7 70 (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags
<> 144:ef7eb2e8f9f7 71 (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 [..]
<> 144:ef7eb2e8f9f7 74 (@) You can refer to the CAN HAL driver header file for more useful macros
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 @endverbatim
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 ******************************************************************************
<> 144:ef7eb2e8f9f7 79 * @attention
<> 144:ef7eb2e8f9f7 80 *
<> 144:ef7eb2e8f9f7 81 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 82 *
<> 144:ef7eb2e8f9f7 83 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 84 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 85 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 86 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 87 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 88 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 89 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 90 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 91 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 92 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 93 *
<> 144:ef7eb2e8f9f7 94 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 95 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 96 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 97 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 98 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 99 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 100 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 101 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 102 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 103 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 104 *
<> 144:ef7eb2e8f9f7 105 ******************************************************************************
<> 144:ef7eb2e8f9f7 106 */
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 109 #include "stm32f7xx_hal.h"
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 /** @addtogroup STM32F7xx_HAL_Driver
<> 144:ef7eb2e8f9f7 112 * @{
<> 144:ef7eb2e8f9f7 113 */
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 /** @defgroup CAN CAN
<> 144:ef7eb2e8f9f7 116 * @brief CAN driver modules
<> 144:ef7eb2e8f9f7 117 * @{
<> 144:ef7eb2e8f9f7 118 */
<> 144:ef7eb2e8f9f7 119
<> 144:ef7eb2e8f9f7 120 #ifdef HAL_CAN_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 124 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 125 /** @addtogroup CAN_Private_Constants
<> 144:ef7eb2e8f9f7 126 * @{
<> 144:ef7eb2e8f9f7 127 */
<> 144:ef7eb2e8f9f7 128 #define CAN_TIMEOUT_VALUE 10
<> 144:ef7eb2e8f9f7 129 /**
<> 144:ef7eb2e8f9f7 130 * @}
<> 144:ef7eb2e8f9f7 131 */
<> 144:ef7eb2e8f9f7 132 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 133 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 134 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 135 /** @addtogroup CAN_Private_Functions
<> 144:ef7eb2e8f9f7 136 * @{
<> 144:ef7eb2e8f9f7 137 */
<> 144:ef7eb2e8f9f7 138 static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber);
<> 144:ef7eb2e8f9f7 139 static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan);
<> 144:ef7eb2e8f9f7 140 /**
<> 144:ef7eb2e8f9f7 141 * @}
<> 144:ef7eb2e8f9f7 142 */
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 145 /** @defgroup CAN_Exported_Functions CAN Exported Functions
<> 144:ef7eb2e8f9f7 146 * @{
<> 144:ef7eb2e8f9f7 147 */
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 /** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 150 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 151 *
<> 144:ef7eb2e8f9f7 152 @verbatim
<> 144:ef7eb2e8f9f7 153 ==============================================================================
<> 144:ef7eb2e8f9f7 154 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 155 ==============================================================================
<> 144:ef7eb2e8f9f7 156 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 157 (+) Initialize and configure the CAN.
<> 144:ef7eb2e8f9f7 158 (+) De-initialize the CAN.
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 @endverbatim
<> 144:ef7eb2e8f9f7 161 * @{
<> 144:ef7eb2e8f9f7 162 */
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 /**
<> 144:ef7eb2e8f9f7 165 * @brief Initializes the CAN peripheral according to the specified
<> 144:ef7eb2e8f9f7 166 * parameters in the CAN_InitStruct.
<> 144:ef7eb2e8f9f7 167 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 168 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 169 * @retval HAL status
<> 144:ef7eb2e8f9f7 170 */
<> 144:ef7eb2e8f9f7 171 HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 172 {
<> 144:ef7eb2e8f9f7 173 uint32_t InitStatus = CAN_INITSTATUS_FAILED;
<> 144:ef7eb2e8f9f7 174 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 /* Check CAN handle */
<> 144:ef7eb2e8f9f7 177 if(hcan == NULL)
<> 144:ef7eb2e8f9f7 178 {
<> 144:ef7eb2e8f9f7 179 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 180 }
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 /* Check the parameters */
<> 144:ef7eb2e8f9f7 183 assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
<> 144:ef7eb2e8f9f7 184 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM));
<> 144:ef7eb2e8f9f7 185 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM));
<> 144:ef7eb2e8f9f7 186 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM));
<> 144:ef7eb2e8f9f7 187 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART));
<> 144:ef7eb2e8f9f7 188 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM));
<> 144:ef7eb2e8f9f7 189 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP));
<> 144:ef7eb2e8f9f7 190 assert_param(IS_CAN_MODE(hcan->Init.Mode));
<> 144:ef7eb2e8f9f7 191 assert_param(IS_CAN_SJW(hcan->Init.SJW));
<> 144:ef7eb2e8f9f7 192 assert_param(IS_CAN_BS1(hcan->Init.BS1));
<> 144:ef7eb2e8f9f7 193 assert_param(IS_CAN_BS2(hcan->Init.BS2));
<> 144:ef7eb2e8f9f7 194 assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler));
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 if(hcan->State == HAL_CAN_STATE_RESET)
<> 144:ef7eb2e8f9f7 198 {
<> 144:ef7eb2e8f9f7 199 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 200 hcan->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 201 /* Init the low level hardware */
<> 144:ef7eb2e8f9f7 202 HAL_CAN_MspInit(hcan);
<> 144:ef7eb2e8f9f7 203 }
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 /* Initialize the CAN state*/
<> 144:ef7eb2e8f9f7 206 hcan->State = HAL_CAN_STATE_BUSY;
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 /* Exit from sleep mode */
<> 144:ef7eb2e8f9f7 209 hcan->Instance->MCR &= (~(uint32_t)CAN_MCR_SLEEP);
<> 144:ef7eb2e8f9f7 210
<> 144:ef7eb2e8f9f7 211 /* Request initialisation */
<> 144:ef7eb2e8f9f7 212 hcan->Instance->MCR |= CAN_MCR_INRQ ;
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 /* Get tick */
<> 144:ef7eb2e8f9f7 215 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 /* Wait the acknowledge */
<> 144:ef7eb2e8f9f7 218 while((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
<> 144:ef7eb2e8f9f7 219 {
<> 144:ef7eb2e8f9f7 220 if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 221 {
<> 144:ef7eb2e8f9f7 222 hcan->State= HAL_CAN_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 223 /* Process unlocked */
<> 144:ef7eb2e8f9f7 224 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 225 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 226 }
<> 144:ef7eb2e8f9f7 227 }
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229 /* Check acknowledge */
<> 144:ef7eb2e8f9f7 230 if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
<> 144:ef7eb2e8f9f7 231 {
<> 144:ef7eb2e8f9f7 232 /* Set the time triggered communication mode */
<> 144:ef7eb2e8f9f7 233 if (hcan->Init.TTCM == ENABLE)
<> 144:ef7eb2e8f9f7 234 {
<> 144:ef7eb2e8f9f7 235 hcan->Instance->MCR |= CAN_MCR_TTCM;
<> 144:ef7eb2e8f9f7 236 }
<> 144:ef7eb2e8f9f7 237 else
<> 144:ef7eb2e8f9f7 238 {
<> 144:ef7eb2e8f9f7 239 hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TTCM;
<> 144:ef7eb2e8f9f7 240 }
<> 144:ef7eb2e8f9f7 241
<> 144:ef7eb2e8f9f7 242 /* Set the automatic bus-off management */
<> 144:ef7eb2e8f9f7 243 if (hcan->Init.ABOM == ENABLE)
<> 144:ef7eb2e8f9f7 244 {
<> 144:ef7eb2e8f9f7 245 hcan->Instance->MCR |= CAN_MCR_ABOM;
<> 144:ef7eb2e8f9f7 246 }
<> 144:ef7eb2e8f9f7 247 else
<> 144:ef7eb2e8f9f7 248 {
<> 144:ef7eb2e8f9f7 249 hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_ABOM;
<> 144:ef7eb2e8f9f7 250 }
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 /* Set the automatic wake-up mode */
<> 144:ef7eb2e8f9f7 253 if (hcan->Init.AWUM == ENABLE)
<> 144:ef7eb2e8f9f7 254 {
<> 144:ef7eb2e8f9f7 255 hcan->Instance->MCR |= CAN_MCR_AWUM;
<> 144:ef7eb2e8f9f7 256 }
<> 144:ef7eb2e8f9f7 257 else
<> 144:ef7eb2e8f9f7 258 {
<> 144:ef7eb2e8f9f7 259 hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_AWUM;
<> 144:ef7eb2e8f9f7 260 }
<> 144:ef7eb2e8f9f7 261
<> 144:ef7eb2e8f9f7 262 /* Set the no automatic retransmission */
<> 144:ef7eb2e8f9f7 263 if (hcan->Init.NART == ENABLE)
<> 144:ef7eb2e8f9f7 264 {
<> 144:ef7eb2e8f9f7 265 hcan->Instance->MCR |= CAN_MCR_NART;
<> 144:ef7eb2e8f9f7 266 }
<> 144:ef7eb2e8f9f7 267 else
<> 144:ef7eb2e8f9f7 268 {
<> 144:ef7eb2e8f9f7 269 hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_NART;
<> 144:ef7eb2e8f9f7 270 }
<> 144:ef7eb2e8f9f7 271
<> 144:ef7eb2e8f9f7 272 /* Set the receive FIFO locked mode */
<> 144:ef7eb2e8f9f7 273 if (hcan->Init.RFLM == ENABLE)
<> 144:ef7eb2e8f9f7 274 {
<> 144:ef7eb2e8f9f7 275 hcan->Instance->MCR |= CAN_MCR_RFLM;
<> 144:ef7eb2e8f9f7 276 }
<> 144:ef7eb2e8f9f7 277 else
<> 144:ef7eb2e8f9f7 278 {
<> 144:ef7eb2e8f9f7 279 hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_RFLM;
<> 144:ef7eb2e8f9f7 280 }
<> 144:ef7eb2e8f9f7 281
<> 144:ef7eb2e8f9f7 282 /* Set the transmit FIFO priority */
<> 144:ef7eb2e8f9f7 283 if (hcan->Init.TXFP == ENABLE)
<> 144:ef7eb2e8f9f7 284 {
<> 144:ef7eb2e8f9f7 285 hcan->Instance->MCR |= CAN_MCR_TXFP;
<> 144:ef7eb2e8f9f7 286 }
<> 144:ef7eb2e8f9f7 287 else
<> 144:ef7eb2e8f9f7 288 {
<> 144:ef7eb2e8f9f7 289 hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TXFP;
<> 144:ef7eb2e8f9f7 290 }
<> 144:ef7eb2e8f9f7 291
<> 144:ef7eb2e8f9f7 292 /* Set the bit timing register */
<> 144:ef7eb2e8f9f7 293 hcan->Instance->BTR = (uint32_t)((uint32_t)hcan->Init.Mode) | \
<> 144:ef7eb2e8f9f7 294 ((uint32_t)hcan->Init.SJW) | \
<> 144:ef7eb2e8f9f7 295 ((uint32_t)hcan->Init.BS1) | \
<> 144:ef7eb2e8f9f7 296 ((uint32_t)hcan->Init.BS2) | \
<> 144:ef7eb2e8f9f7 297 ((uint32_t)hcan->Init.Prescaler - 1);
<> 144:ef7eb2e8f9f7 298
<> 144:ef7eb2e8f9f7 299 /* Request leave initialisation */
<> 144:ef7eb2e8f9f7 300 hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ;
<> 144:ef7eb2e8f9f7 301
<> 144:ef7eb2e8f9f7 302 /* Get tick */
<> 144:ef7eb2e8f9f7 303 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 304
<> 144:ef7eb2e8f9f7 305 /* Wait the acknowledge */
<> 144:ef7eb2e8f9f7 306 while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
<> 144:ef7eb2e8f9f7 307 {
<> 144:ef7eb2e8f9f7 308 if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 309 {
<> 144:ef7eb2e8f9f7 310 hcan->State= HAL_CAN_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 311 /* Process unlocked */
<> 144:ef7eb2e8f9f7 312 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 313 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 314 }
<> 144:ef7eb2e8f9f7 315 }
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 /* Check acknowledged */
<> 144:ef7eb2e8f9f7 318 if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
<> 144:ef7eb2e8f9f7 319 {
<> 144:ef7eb2e8f9f7 320 InitStatus = CAN_INITSTATUS_SUCCESS;
<> 144:ef7eb2e8f9f7 321 }
<> 144:ef7eb2e8f9f7 322 }
<> 144:ef7eb2e8f9f7 323
<> 144:ef7eb2e8f9f7 324 if(InitStatus == CAN_INITSTATUS_SUCCESS)
<> 144:ef7eb2e8f9f7 325 {
<> 144:ef7eb2e8f9f7 326 /* Set CAN error code to none */
<> 144:ef7eb2e8f9f7 327 hcan->ErrorCode = HAL_CAN_ERROR_NONE;
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329 /* Initialize the CAN state */
<> 144:ef7eb2e8f9f7 330 hcan->State = HAL_CAN_STATE_READY;
<> 144:ef7eb2e8f9f7 331
<> 144:ef7eb2e8f9f7 332 /* Return function status */
<> 144:ef7eb2e8f9f7 333 return HAL_OK;
<> 144:ef7eb2e8f9f7 334 }
<> 144:ef7eb2e8f9f7 335 else
<> 144:ef7eb2e8f9f7 336 {
<> 144:ef7eb2e8f9f7 337 /* Initialize the CAN state */
<> 144:ef7eb2e8f9f7 338 hcan->State = HAL_CAN_STATE_ERROR;
<> 144:ef7eb2e8f9f7 339
<> 144:ef7eb2e8f9f7 340 /* Return function status */
<> 144:ef7eb2e8f9f7 341 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 342 }
<> 144:ef7eb2e8f9f7 343 }
<> 144:ef7eb2e8f9f7 344
<> 144:ef7eb2e8f9f7 345 /**
<> 144:ef7eb2e8f9f7 346 * @brief Configures the CAN reception filter according to the specified
<> 144:ef7eb2e8f9f7 347 * parameters in the CAN_FilterInitStruct.
<> 144:ef7eb2e8f9f7 348 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 349 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 350 * @param sFilterConfig: pointer to a CAN_FilterConfTypeDef structure that
<> 144:ef7eb2e8f9f7 351 * contains the filter configuration information.
<> 144:ef7eb2e8f9f7 352 * @retval None
<> 144:ef7eb2e8f9f7 353 */
<> 144:ef7eb2e8f9f7 354 HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig)
<> 144:ef7eb2e8f9f7 355 {
<> 144:ef7eb2e8f9f7 356 uint32_t filternbrbitpos = 0;
<> 144:ef7eb2e8f9f7 357 CAN_TypeDef *can_ip;
<> 144:ef7eb2e8f9f7 358
<> 144:ef7eb2e8f9f7 359 /* Check the parameters */
<> 144:ef7eb2e8f9f7 360 assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber));
<> 144:ef7eb2e8f9f7 361 assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode));
<> 144:ef7eb2e8f9f7 362 assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale));
<> 144:ef7eb2e8f9f7 363 assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment));
<> 144:ef7eb2e8f9f7 364 assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation));
<> 144:ef7eb2e8f9f7 365 assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber));
<> 144:ef7eb2e8f9f7 366
<> 144:ef7eb2e8f9f7 367 filternbrbitpos = ((uint32_t)1) << sFilterConfig->FilterNumber;
<> 144:ef7eb2e8f9f7 368 #if defined (CAN3)
<> 144:ef7eb2e8f9f7 369 /* Check the CAN instance */
<> 144:ef7eb2e8f9f7 370 if(hcan->Instance == CAN3)
<> 144:ef7eb2e8f9f7 371 {
<> 144:ef7eb2e8f9f7 372 can_ip = CAN3;
<> 144:ef7eb2e8f9f7 373 }
<> 144:ef7eb2e8f9f7 374 else
<> 144:ef7eb2e8f9f7 375 {
<> 144:ef7eb2e8f9f7 376 can_ip = CAN1;
<> 144:ef7eb2e8f9f7 377 }
<> 144:ef7eb2e8f9f7 378 #else
<> 144:ef7eb2e8f9f7 379 can_ip = CAN1;
<> 144:ef7eb2e8f9f7 380 #endif
<> 144:ef7eb2e8f9f7 381
<> 144:ef7eb2e8f9f7 382 /* Initialisation mode for the filter */
<> 144:ef7eb2e8f9f7 383 can_ip->FMR |= (uint32_t)CAN_FMR_FINIT;
<> 144:ef7eb2e8f9f7 384
<> 144:ef7eb2e8f9f7 385 /* Select the start slave bank */
<> 144:ef7eb2e8f9f7 386 can_ip->FMR &= ~((uint32_t)CAN_FMR_CAN2SB);
<> 144:ef7eb2e8f9f7 387 can_ip->FMR |= (uint32_t)(sFilterConfig->BankNumber << 8);
<> 144:ef7eb2e8f9f7 388
<> 144:ef7eb2e8f9f7 389 /* Filter Deactivation */
<> 144:ef7eb2e8f9f7 390 can_ip->FA1R &= ~(uint32_t)filternbrbitpos;
<> 144:ef7eb2e8f9f7 391
<> 144:ef7eb2e8f9f7 392 /* Filter Scale */
<> 144:ef7eb2e8f9f7 393 if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
<> 144:ef7eb2e8f9f7 394 {
<> 144:ef7eb2e8f9f7 395 /* 16-bit scale for the filter */
<> 144:ef7eb2e8f9f7 396 can_ip->FS1R &= ~(uint32_t)filternbrbitpos;
<> 144:ef7eb2e8f9f7 397
<> 144:ef7eb2e8f9f7 398 /* First 16-bit identifier and First 16-bit mask */
<> 144:ef7eb2e8f9f7 399 /* Or First 16-bit identifier and Second 16-bit identifier */
<> 144:ef7eb2e8f9f7 400 can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
<> 144:ef7eb2e8f9f7 401 ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16) |
<> 144:ef7eb2e8f9f7 402 (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow);
<> 144:ef7eb2e8f9f7 403
<> 144:ef7eb2e8f9f7 404 /* Second 16-bit identifier and Second 16-bit mask */
<> 144:ef7eb2e8f9f7 405 /* Or Third 16-bit identifier and Fourth 16-bit identifier */
<> 144:ef7eb2e8f9f7 406 can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
<> 144:ef7eb2e8f9f7 407 ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) |
<> 144:ef7eb2e8f9f7 408 (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh);
<> 144:ef7eb2e8f9f7 409 }
<> 144:ef7eb2e8f9f7 410
<> 144:ef7eb2e8f9f7 411 if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
<> 144:ef7eb2e8f9f7 412 {
<> 144:ef7eb2e8f9f7 413 /* 32-bit scale for the filter */
<> 144:ef7eb2e8f9f7 414 can_ip->FS1R |= filternbrbitpos;
<> 144:ef7eb2e8f9f7 415
<> 144:ef7eb2e8f9f7 416 /* 32-bit identifier or First 32-bit identifier */
<> 144:ef7eb2e8f9f7 417 can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
<> 144:ef7eb2e8f9f7 418 ((0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh) << 16) |
<> 144:ef7eb2e8f9f7 419 (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow);
<> 144:ef7eb2e8f9f7 420
<> 144:ef7eb2e8f9f7 421 /* 32-bit mask or Second 32-bit identifier */
<> 144:ef7eb2e8f9f7 422 can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
<> 144:ef7eb2e8f9f7 423 ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) |
<> 144:ef7eb2e8f9f7 424 (0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow);
<> 144:ef7eb2e8f9f7 425 }
<> 144:ef7eb2e8f9f7 426
<> 144:ef7eb2e8f9f7 427 /* Filter Mode */
<> 144:ef7eb2e8f9f7 428 if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
<> 144:ef7eb2e8f9f7 429 {
<> 144:ef7eb2e8f9f7 430 /*Id/Mask mode for the filter*/
<> 144:ef7eb2e8f9f7 431 can_ip->FM1R &= ~(uint32_t)filternbrbitpos;
<> 144:ef7eb2e8f9f7 432 }
<> 144:ef7eb2e8f9f7 433 else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
<> 144:ef7eb2e8f9f7 434 {
<> 144:ef7eb2e8f9f7 435 /*Identifier list mode for the filter*/
<> 144:ef7eb2e8f9f7 436 can_ip->FM1R |= (uint32_t)filternbrbitpos;
<> 144:ef7eb2e8f9f7 437 }
<> 144:ef7eb2e8f9f7 438
<> 144:ef7eb2e8f9f7 439 /* Filter FIFO assignment */
<> 144:ef7eb2e8f9f7 440 if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
<> 144:ef7eb2e8f9f7 441 {
<> 144:ef7eb2e8f9f7 442 /* FIFO 0 assignation for the filter */
<> 144:ef7eb2e8f9f7 443 can_ip->FFA1R &= ~(uint32_t)filternbrbitpos;
<> 144:ef7eb2e8f9f7 444 }
<> 144:ef7eb2e8f9f7 445
<> 144:ef7eb2e8f9f7 446 if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO1)
<> 144:ef7eb2e8f9f7 447 {
<> 144:ef7eb2e8f9f7 448 /* FIFO 1 assignation for the filter */
<> 144:ef7eb2e8f9f7 449 can_ip->FFA1R |= (uint32_t)filternbrbitpos;
<> 144:ef7eb2e8f9f7 450 }
<> 144:ef7eb2e8f9f7 451
<> 144:ef7eb2e8f9f7 452 /* Filter activation */
<> 144:ef7eb2e8f9f7 453 if (sFilterConfig->FilterActivation == ENABLE)
<> 144:ef7eb2e8f9f7 454 {
<> 144:ef7eb2e8f9f7 455 can_ip->FA1R |= filternbrbitpos;
<> 144:ef7eb2e8f9f7 456 }
<> 144:ef7eb2e8f9f7 457
<> 144:ef7eb2e8f9f7 458 /* Leave the initialisation mode for the filter */
<> 144:ef7eb2e8f9f7 459 can_ip->FMR &= ~((uint32_t)CAN_FMR_FINIT);
<> 144:ef7eb2e8f9f7 460
<> 144:ef7eb2e8f9f7 461 /* Return function status */
<> 144:ef7eb2e8f9f7 462 return HAL_OK;
<> 144:ef7eb2e8f9f7 463 }
<> 144:ef7eb2e8f9f7 464
<> 144:ef7eb2e8f9f7 465 /**
<> 144:ef7eb2e8f9f7 466 * @brief Deinitializes the CANx peripheral registers to their default reset values.
<> 144:ef7eb2e8f9f7 467 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 468 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 469 * @retval HAL status
<> 144:ef7eb2e8f9f7 470 */
<> 144:ef7eb2e8f9f7 471 HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 472 {
<> 144:ef7eb2e8f9f7 473 /* Check CAN handle */
<> 144:ef7eb2e8f9f7 474 if(hcan == NULL)
<> 144:ef7eb2e8f9f7 475 {
<> 144:ef7eb2e8f9f7 476 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 477 }
<> 144:ef7eb2e8f9f7 478
<> 144:ef7eb2e8f9f7 479 /* Check the parameters */
<> 144:ef7eb2e8f9f7 480 assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
<> 144:ef7eb2e8f9f7 481
<> 144:ef7eb2e8f9f7 482 /* Change CAN state */
<> 144:ef7eb2e8f9f7 483 hcan->State = HAL_CAN_STATE_BUSY;
<> 144:ef7eb2e8f9f7 484
<> 144:ef7eb2e8f9f7 485 /* DeInit the low level hardware */
<> 144:ef7eb2e8f9f7 486 HAL_CAN_MspDeInit(hcan);
<> 144:ef7eb2e8f9f7 487
<> 144:ef7eb2e8f9f7 488 /* Change CAN state */
<> 144:ef7eb2e8f9f7 489 hcan->State = HAL_CAN_STATE_RESET;
<> 144:ef7eb2e8f9f7 490
<> 144:ef7eb2e8f9f7 491 /* Release Lock */
<> 144:ef7eb2e8f9f7 492 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 493
<> 144:ef7eb2e8f9f7 494 /* Return function status */
<> 144:ef7eb2e8f9f7 495 return HAL_OK;
<> 144:ef7eb2e8f9f7 496 }
<> 144:ef7eb2e8f9f7 497
<> 144:ef7eb2e8f9f7 498 /**
<> 144:ef7eb2e8f9f7 499 * @brief Initializes the CAN MSP.
<> 144:ef7eb2e8f9f7 500 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 501 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 502 * @retval None
<> 144:ef7eb2e8f9f7 503 */
<> 144:ef7eb2e8f9f7 504 __weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 505 {
<> 144:ef7eb2e8f9f7 506 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 507 UNUSED(hcan);
<> 144:ef7eb2e8f9f7 508 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 509 the HAL_CAN_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 510 */
<> 144:ef7eb2e8f9f7 511 }
<> 144:ef7eb2e8f9f7 512
<> 144:ef7eb2e8f9f7 513 /**
<> 144:ef7eb2e8f9f7 514 * @brief DeInitializes the CAN MSP.
<> 144:ef7eb2e8f9f7 515 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 516 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 517 * @retval None
<> 144:ef7eb2e8f9f7 518 */
<> 144:ef7eb2e8f9f7 519 __weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 520 {
<> 144:ef7eb2e8f9f7 521 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 522 UNUSED(hcan);
<> 144:ef7eb2e8f9f7 523 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 524 the HAL_CAN_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 525 */
<> 144:ef7eb2e8f9f7 526 }
<> 144:ef7eb2e8f9f7 527
<> 144:ef7eb2e8f9f7 528 /**
<> 144:ef7eb2e8f9f7 529 * @}
<> 144:ef7eb2e8f9f7 530 */
<> 144:ef7eb2e8f9f7 531
<> 144:ef7eb2e8f9f7 532 /** @defgroup CAN_Exported_Functions_Group2 IO operation functions
<> 144:ef7eb2e8f9f7 533 * @brief IO operation functions
<> 144:ef7eb2e8f9f7 534 *
<> 144:ef7eb2e8f9f7 535 @verbatim
<> 144:ef7eb2e8f9f7 536 ==============================================================================
<> 144:ef7eb2e8f9f7 537 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 538 ==============================================================================
<> 144:ef7eb2e8f9f7 539 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 540 (+) Transmit a CAN frame message.
<> 144:ef7eb2e8f9f7 541 (+) Receive a CAN frame message.
<> 144:ef7eb2e8f9f7 542 (+) Enter CAN peripheral in sleep mode.
<> 144:ef7eb2e8f9f7 543 (+) Wake up the CAN peripheral from sleep mode.
<> 144:ef7eb2e8f9f7 544
<> 144:ef7eb2e8f9f7 545 @endverbatim
<> 144:ef7eb2e8f9f7 546 * @{
<> 144:ef7eb2e8f9f7 547 */
<> 144:ef7eb2e8f9f7 548
<> 144:ef7eb2e8f9f7 549 /**
<> 144:ef7eb2e8f9f7 550 * @brief Initiates and transmits a CAN frame message.
<> 144:ef7eb2e8f9f7 551 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 552 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 553 * @param Timeout: Specify Timeout value
<> 144:ef7eb2e8f9f7 554 * @retval HAL status
<> 144:ef7eb2e8f9f7 555 */
<> 144:ef7eb2e8f9f7 556 HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 557 {
<> 144:ef7eb2e8f9f7 558 uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
<> 144:ef7eb2e8f9f7 559 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 560
<> 144:ef7eb2e8f9f7 561 /* Check the parameters */
<> 144:ef7eb2e8f9f7 562 assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
<> 144:ef7eb2e8f9f7 563 assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
<> 144:ef7eb2e8f9f7 564 assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
<> 144:ef7eb2e8f9f7 565
<> 144:ef7eb2e8f9f7 566 if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
<> 144:ef7eb2e8f9f7 567 ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
<> 144:ef7eb2e8f9f7 568 ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
<> 144:ef7eb2e8f9f7 569 {
<> 144:ef7eb2e8f9f7 570 /* Process locked */
<> 144:ef7eb2e8f9f7 571 __HAL_LOCK(hcan);
<> 144:ef7eb2e8f9f7 572
<> 144:ef7eb2e8f9f7 573 if(hcan->State == HAL_CAN_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 574 {
<> 144:ef7eb2e8f9f7 575 /* Change CAN state */
<> 144:ef7eb2e8f9f7 576 hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
<> 144:ef7eb2e8f9f7 577 }
<> 144:ef7eb2e8f9f7 578 else
<> 144:ef7eb2e8f9f7 579 {
<> 144:ef7eb2e8f9f7 580 /* Change CAN state */
<> 144:ef7eb2e8f9f7 581 hcan->State = HAL_CAN_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 582 }
<> 144:ef7eb2e8f9f7 583
<> 144:ef7eb2e8f9f7 584 /* Select one empty transmit mailbox */
<> 144:ef7eb2e8f9f7 585 if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
<> 144:ef7eb2e8f9f7 586 {
<> 144:ef7eb2e8f9f7 587 transmitmailbox = CAN_TXMAILBOX_0;
<> 144:ef7eb2e8f9f7 588 }
<> 144:ef7eb2e8f9f7 589 else if ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
<> 144:ef7eb2e8f9f7 590 {
<> 144:ef7eb2e8f9f7 591 transmitmailbox = CAN_TXMAILBOX_1;
<> 144:ef7eb2e8f9f7 592 }
<> 144:ef7eb2e8f9f7 593 else
<> 144:ef7eb2e8f9f7 594 {
<> 144:ef7eb2e8f9f7 595 transmitmailbox = CAN_TXMAILBOX_2;
<> 144:ef7eb2e8f9f7 596 }
<> 144:ef7eb2e8f9f7 597
<> 144:ef7eb2e8f9f7 598 /* Set up the Id */
<> 144:ef7eb2e8f9f7 599 hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
<> 144:ef7eb2e8f9f7 600 if (hcan->pTxMsg->IDE == CAN_ID_STD)
<> 144:ef7eb2e8f9f7 601 {
<> 144:ef7eb2e8f9f7 602 assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
<> 144:ef7eb2e8f9f7 603 hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \
<> 144:ef7eb2e8f9f7 604 hcan->pTxMsg->RTR);
<> 144:ef7eb2e8f9f7 605 }
<> 144:ef7eb2e8f9f7 606 else
<> 144:ef7eb2e8f9f7 607 {
<> 144:ef7eb2e8f9f7 608 assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
<> 144:ef7eb2e8f9f7 609 hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \
<> 144:ef7eb2e8f9f7 610 hcan->pTxMsg->IDE | \
<> 144:ef7eb2e8f9f7 611 hcan->pTxMsg->RTR);
<> 144:ef7eb2e8f9f7 612 }
<> 144:ef7eb2e8f9f7 613
<> 144:ef7eb2e8f9f7 614 /* Set up the DLC */
<> 144:ef7eb2e8f9f7 615 hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU;
<> 144:ef7eb2e8f9f7 616 hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U;
<> 144:ef7eb2e8f9f7 617 hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
<> 144:ef7eb2e8f9f7 618
<> 144:ef7eb2e8f9f7 619 /* Set up the data field */
<> 144:ef7eb2e8f9f7 620 hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) |
<> 144:ef7eb2e8f9f7 621 ((uint32_t)hcan->pTxMsg->Data[2] << 16) |
<> 144:ef7eb2e8f9f7 622 ((uint32_t)hcan->pTxMsg->Data[1] << 8) |
<> 144:ef7eb2e8f9f7 623 ((uint32_t)hcan->pTxMsg->Data[0]));
<> 144:ef7eb2e8f9f7 624 hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) |
<> 144:ef7eb2e8f9f7 625 ((uint32_t)hcan->pTxMsg->Data[6] << 16) |
<> 144:ef7eb2e8f9f7 626 ((uint32_t)hcan->pTxMsg->Data[5] << 8) |
<> 144:ef7eb2e8f9f7 627 ((uint32_t)hcan->pTxMsg->Data[4]));
<> 144:ef7eb2e8f9f7 628 /* Request transmission */
<> 144:ef7eb2e8f9f7 629 hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
<> 144:ef7eb2e8f9f7 630
<> 144:ef7eb2e8f9f7 631 /* Get tick */
<> 144:ef7eb2e8f9f7 632 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 633
<> 144:ef7eb2e8f9f7 634 /* Check End of transmission flag */
<> 144:ef7eb2e8f9f7 635 while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox)))
<> 144:ef7eb2e8f9f7 636 {
<> 144:ef7eb2e8f9f7 637 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 638 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 639 {
<> 144:ef7eb2e8f9f7 640 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 641 {
<> 144:ef7eb2e8f9f7 642 hcan->State = HAL_CAN_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 643 /* Process unlocked */
<> 144:ef7eb2e8f9f7 644 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 645 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 646 }
<> 144:ef7eb2e8f9f7 647 }
<> 144:ef7eb2e8f9f7 648 }
<> 144:ef7eb2e8f9f7 649 if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
<> 144:ef7eb2e8f9f7 650 {
<> 144:ef7eb2e8f9f7 651 /* Change CAN state */
<> 144:ef7eb2e8f9f7 652 hcan->State = HAL_CAN_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 653 }
<> 144:ef7eb2e8f9f7 654 else
<> 144:ef7eb2e8f9f7 655 {
<> 144:ef7eb2e8f9f7 656 /* Change CAN state */
<> 144:ef7eb2e8f9f7 657 hcan->State = HAL_CAN_STATE_READY;
<> 144:ef7eb2e8f9f7 658 }
<> 144:ef7eb2e8f9f7 659
<> 144:ef7eb2e8f9f7 660 /* Process unlocked */
<> 144:ef7eb2e8f9f7 661 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 662
<> 144:ef7eb2e8f9f7 663 /* Return function status */
<> 144:ef7eb2e8f9f7 664 return HAL_OK;
<> 144:ef7eb2e8f9f7 665 }
<> 144:ef7eb2e8f9f7 666 else
<> 144:ef7eb2e8f9f7 667 {
<> 144:ef7eb2e8f9f7 668 /* Change CAN state */
<> 144:ef7eb2e8f9f7 669 hcan->State = HAL_CAN_STATE_ERROR;
<> 144:ef7eb2e8f9f7 670
<> 144:ef7eb2e8f9f7 671 /* Return function status */
<> 144:ef7eb2e8f9f7 672 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 673 }
<> 144:ef7eb2e8f9f7 674 }
<> 144:ef7eb2e8f9f7 675
<> 144:ef7eb2e8f9f7 676 /**
<> 144:ef7eb2e8f9f7 677 * @brief Initiates and transmits a CAN frame message.
<> 144:ef7eb2e8f9f7 678 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 679 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 680 * @retval HAL status
<> 144:ef7eb2e8f9f7 681 */
<> 144:ef7eb2e8f9f7 682 HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 683 {
<> 144:ef7eb2e8f9f7 684 uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
<> 144:ef7eb2e8f9f7 685
<> 144:ef7eb2e8f9f7 686 /* Check the parameters */
<> 144:ef7eb2e8f9f7 687 assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
<> 144:ef7eb2e8f9f7 688 assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
<> 144:ef7eb2e8f9f7 689 assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
<> 144:ef7eb2e8f9f7 690
<> 144:ef7eb2e8f9f7 691 if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
<> 144:ef7eb2e8f9f7 692 ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
<> 144:ef7eb2e8f9f7 693 ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
<> 144:ef7eb2e8f9f7 694 {
<> 144:ef7eb2e8f9f7 695 /* Process Locked */
<> 144:ef7eb2e8f9f7 696 __HAL_LOCK(hcan);
<> 144:ef7eb2e8f9f7 697
<> 144:ef7eb2e8f9f7 698 /* Select one empty transmit mailbox */
<> 144:ef7eb2e8f9f7 699 if((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
<> 144:ef7eb2e8f9f7 700 {
<> 144:ef7eb2e8f9f7 701 transmitmailbox = CAN_TXMAILBOX_0;
<> 144:ef7eb2e8f9f7 702 }
<> 144:ef7eb2e8f9f7 703 else if((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
<> 144:ef7eb2e8f9f7 704 {
<> 144:ef7eb2e8f9f7 705 transmitmailbox = CAN_TXMAILBOX_1;
<> 144:ef7eb2e8f9f7 706 }
<> 144:ef7eb2e8f9f7 707 else
<> 144:ef7eb2e8f9f7 708 {
<> 144:ef7eb2e8f9f7 709 transmitmailbox = CAN_TXMAILBOX_2;
<> 144:ef7eb2e8f9f7 710 }
<> 144:ef7eb2e8f9f7 711
<> 144:ef7eb2e8f9f7 712 /* Set up the Id */
<> 144:ef7eb2e8f9f7 713 hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
<> 144:ef7eb2e8f9f7 714 if(hcan->pTxMsg->IDE == CAN_ID_STD)
<> 144:ef7eb2e8f9f7 715 {
<> 144:ef7eb2e8f9f7 716 assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
<> 144:ef7eb2e8f9f7 717 hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \
<> 144:ef7eb2e8f9f7 718 hcan->pTxMsg->RTR);
<> 144:ef7eb2e8f9f7 719 }
<> 144:ef7eb2e8f9f7 720 else
<> 144:ef7eb2e8f9f7 721 {
<> 144:ef7eb2e8f9f7 722 assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
<> 144:ef7eb2e8f9f7 723 hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \
<> 144:ef7eb2e8f9f7 724 hcan->pTxMsg->IDE | \
<> 144:ef7eb2e8f9f7 725 hcan->pTxMsg->RTR);
<> 144:ef7eb2e8f9f7 726 }
<> 144:ef7eb2e8f9f7 727
<> 144:ef7eb2e8f9f7 728 /* Set up the DLC */
<> 144:ef7eb2e8f9f7 729 hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU;
<> 144:ef7eb2e8f9f7 730 hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U;
<> 144:ef7eb2e8f9f7 731 hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
<> 144:ef7eb2e8f9f7 732
<> 144:ef7eb2e8f9f7 733 /* Set up the data field */
<> 144:ef7eb2e8f9f7 734 hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) |
<> 144:ef7eb2e8f9f7 735 ((uint32_t)hcan->pTxMsg->Data[2] << 16) |
<> 144:ef7eb2e8f9f7 736 ((uint32_t)hcan->pTxMsg->Data[1] << 8) |
<> 144:ef7eb2e8f9f7 737 ((uint32_t)hcan->pTxMsg->Data[0]));
<> 144:ef7eb2e8f9f7 738 hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) |
<> 144:ef7eb2e8f9f7 739 ((uint32_t)hcan->pTxMsg->Data[6] << 16) |
<> 144:ef7eb2e8f9f7 740 ((uint32_t)hcan->pTxMsg->Data[5] << 8) |
<> 144:ef7eb2e8f9f7 741 ((uint32_t)hcan->pTxMsg->Data[4]));
<> 144:ef7eb2e8f9f7 742
<> 144:ef7eb2e8f9f7 743 if(hcan->State == HAL_CAN_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 744 {
<> 144:ef7eb2e8f9f7 745 /* Change CAN state */
<> 144:ef7eb2e8f9f7 746 hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
<> 144:ef7eb2e8f9f7 747 }
<> 144:ef7eb2e8f9f7 748 else
<> 144:ef7eb2e8f9f7 749 {
<> 144:ef7eb2e8f9f7 750 /* Change CAN state */
<> 144:ef7eb2e8f9f7 751 hcan->State = HAL_CAN_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 752 }
<> 144:ef7eb2e8f9f7 753
<> 144:ef7eb2e8f9f7 754 /* Set CAN error code to none */
<> 144:ef7eb2e8f9f7 755 hcan->ErrorCode = HAL_CAN_ERROR_NONE;
<> 144:ef7eb2e8f9f7 756
<> 144:ef7eb2e8f9f7 757 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 758 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 759
<> 144:ef7eb2e8f9f7 760 /* Enable Error warning, Error passive, Bus-off,
<> 144:ef7eb2e8f9f7 761 Last error and Error Interrupts */
<> 144:ef7eb2e8f9f7 762 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
<> 144:ef7eb2e8f9f7 763 CAN_IT_EPV |
<> 144:ef7eb2e8f9f7 764 CAN_IT_BOF |
<> 144:ef7eb2e8f9f7 765 CAN_IT_LEC |
<> 144:ef7eb2e8f9f7 766 CAN_IT_ERR |
<> 144:ef7eb2e8f9f7 767 CAN_IT_TME);
<> 144:ef7eb2e8f9f7 768
<> 144:ef7eb2e8f9f7 769 /* Request transmission */
<> 144:ef7eb2e8f9f7 770 hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
<> 144:ef7eb2e8f9f7 771 }
<> 144:ef7eb2e8f9f7 772 else
<> 144:ef7eb2e8f9f7 773 {
<> 144:ef7eb2e8f9f7 774 /* Change CAN state */
<> 144:ef7eb2e8f9f7 775 hcan->State = HAL_CAN_STATE_ERROR;
<> 144:ef7eb2e8f9f7 776
<> 144:ef7eb2e8f9f7 777 /* Return function status */
<> 144:ef7eb2e8f9f7 778 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 779 }
<> 144:ef7eb2e8f9f7 780
<> 144:ef7eb2e8f9f7 781 return HAL_OK;
<> 144:ef7eb2e8f9f7 782 }
<> 144:ef7eb2e8f9f7 783
<> 144:ef7eb2e8f9f7 784 /**
<> 144:ef7eb2e8f9f7 785 * @brief Receives a correct CAN frame.
<> 144:ef7eb2e8f9f7 786 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 787 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 788 * @param FIFONumber: FIFO Number value
<> 144:ef7eb2e8f9f7 789 * @param Timeout: Specify Timeout value
<> 144:ef7eb2e8f9f7 790 * @retval HAL status
<> 144:ef7eb2e8f9f7 791 */
<> 144:ef7eb2e8f9f7 792 HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 793 {
<> 144:ef7eb2e8f9f7 794 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 795
<> 144:ef7eb2e8f9f7 796 /* Check the parameters */
<> 144:ef7eb2e8f9f7 797 assert_param(IS_CAN_FIFO(FIFONumber));
<> 144:ef7eb2e8f9f7 798
<> 144:ef7eb2e8f9f7 799 /* Process locked */
<> 144:ef7eb2e8f9f7 800 __HAL_LOCK(hcan);
<> 144:ef7eb2e8f9f7 801
<> 144:ef7eb2e8f9f7 802 if(hcan->State == HAL_CAN_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 803 {
<> 144:ef7eb2e8f9f7 804 /* Change CAN state */
<> 144:ef7eb2e8f9f7 805 hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
<> 144:ef7eb2e8f9f7 806 }
<> 144:ef7eb2e8f9f7 807 else
<> 144:ef7eb2e8f9f7 808 {
<> 144:ef7eb2e8f9f7 809 /* Change CAN state */
<> 144:ef7eb2e8f9f7 810 hcan->State = HAL_CAN_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 811 }
<> 144:ef7eb2e8f9f7 812
<> 144:ef7eb2e8f9f7 813 /* Get tick */
<> 144:ef7eb2e8f9f7 814 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 815
<> 144:ef7eb2e8f9f7 816 /* Check pending message */
<> 144:ef7eb2e8f9f7 817 while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0)
<> 144:ef7eb2e8f9f7 818 {
<> 144:ef7eb2e8f9f7 819 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 820 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 821 {
<> 144:ef7eb2e8f9f7 822 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 823 {
<> 144:ef7eb2e8f9f7 824 hcan->State = HAL_CAN_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 825 /* Process unlocked */
<> 144:ef7eb2e8f9f7 826 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 827 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 828 }
<> 144:ef7eb2e8f9f7 829 }
<> 144:ef7eb2e8f9f7 830 }
<> 144:ef7eb2e8f9f7 831
<> 144:ef7eb2e8f9f7 832 /* Get the Id */
<> 144:ef7eb2e8f9f7 833 hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
<> 144:ef7eb2e8f9f7 834 if (hcan->pRxMsg->IDE == CAN_ID_STD)
<> 144:ef7eb2e8f9f7 835 {
<> 144:ef7eb2e8f9f7 836 hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21);
<> 144:ef7eb2e8f9f7 837 }
<> 144:ef7eb2e8f9f7 838 else
<> 144:ef7eb2e8f9f7 839 {
<> 144:ef7eb2e8f9f7 840 hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3);
<> 144:ef7eb2e8f9f7 841 }
<> 144:ef7eb2e8f9f7 842
<> 144:ef7eb2e8f9f7 843 hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
<> 144:ef7eb2e8f9f7 844 /* Get the DLC */
<> 144:ef7eb2e8f9f7 845 hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
<> 144:ef7eb2e8f9f7 846 /* Get the FMI */
<> 144:ef7eb2e8f9f7 847 hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8);
<> 144:ef7eb2e8f9f7 848 /* Get the data field */
<> 144:ef7eb2e8f9f7 849 hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
<> 144:ef7eb2e8f9f7 850 hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8);
<> 144:ef7eb2e8f9f7 851 hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16);
<> 144:ef7eb2e8f9f7 852 hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24);
<> 144:ef7eb2e8f9f7 853 hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
<> 144:ef7eb2e8f9f7 854 hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8);
<> 144:ef7eb2e8f9f7 855 hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16);
<> 144:ef7eb2e8f9f7 856 hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24);
<> 144:ef7eb2e8f9f7 857
<> 144:ef7eb2e8f9f7 858 /* Release the FIFO */
<> 144:ef7eb2e8f9f7 859 if(FIFONumber == CAN_FIFO0)
<> 144:ef7eb2e8f9f7 860 {
<> 144:ef7eb2e8f9f7 861 /* Release FIFO0 */
<> 144:ef7eb2e8f9f7 862 __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
<> 144:ef7eb2e8f9f7 863 }
<> 144:ef7eb2e8f9f7 864 else /* FIFONumber == CAN_FIFO1 */
<> 144:ef7eb2e8f9f7 865 {
<> 144:ef7eb2e8f9f7 866 /* Release FIFO1 */
<> 144:ef7eb2e8f9f7 867 __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
<> 144:ef7eb2e8f9f7 868 }
<> 144:ef7eb2e8f9f7 869
<> 144:ef7eb2e8f9f7 870 if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
<> 144:ef7eb2e8f9f7 871 {
<> 144:ef7eb2e8f9f7 872 /* Change CAN state */
<> 144:ef7eb2e8f9f7 873 hcan->State = HAL_CAN_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 874 }
<> 144:ef7eb2e8f9f7 875 else
<> 144:ef7eb2e8f9f7 876 {
<> 144:ef7eb2e8f9f7 877 /* Change CAN state */
<> 144:ef7eb2e8f9f7 878 hcan->State = HAL_CAN_STATE_READY;
<> 144:ef7eb2e8f9f7 879 }
<> 144:ef7eb2e8f9f7 880
<> 144:ef7eb2e8f9f7 881 /* Process unlocked */
<> 144:ef7eb2e8f9f7 882 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 883
<> 144:ef7eb2e8f9f7 884 /* Return function status */
<> 144:ef7eb2e8f9f7 885 return HAL_OK;
<> 144:ef7eb2e8f9f7 886 }
<> 144:ef7eb2e8f9f7 887
<> 144:ef7eb2e8f9f7 888 /**
<> 144:ef7eb2e8f9f7 889 * @brief Receives a correct CAN frame.
<> 144:ef7eb2e8f9f7 890 * @param hcan: Pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 891 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 892 * @param FIFONumber: Specify the FIFO number
<> 144:ef7eb2e8f9f7 893 * @retval HAL status
<> 144:ef7eb2e8f9f7 894 */
<> 144:ef7eb2e8f9f7 895 HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
<> 144:ef7eb2e8f9f7 896 {
<> 144:ef7eb2e8f9f7 897 uint32_t tmp = 0;
<> 144:ef7eb2e8f9f7 898
<> 144:ef7eb2e8f9f7 899 /* Check the parameters */
<> 144:ef7eb2e8f9f7 900 assert_param(IS_CAN_FIFO(FIFONumber));
<> 144:ef7eb2e8f9f7 901
<> 144:ef7eb2e8f9f7 902 tmp = hcan->State;
<> 144:ef7eb2e8f9f7 903 if((tmp == HAL_CAN_STATE_READY) || (tmp == HAL_CAN_STATE_BUSY_TX))
<> 144:ef7eb2e8f9f7 904 {
<> 144:ef7eb2e8f9f7 905 /* Process locked */
<> 144:ef7eb2e8f9f7 906 __HAL_LOCK(hcan);
<> 144:ef7eb2e8f9f7 907
<> 144:ef7eb2e8f9f7 908 if(hcan->State == HAL_CAN_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 909 {
<> 144:ef7eb2e8f9f7 910 /* Change CAN state */
<> 144:ef7eb2e8f9f7 911 hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
<> 144:ef7eb2e8f9f7 912 }
<> 144:ef7eb2e8f9f7 913 else
<> 144:ef7eb2e8f9f7 914 {
<> 144:ef7eb2e8f9f7 915 /* Change CAN state */
<> 144:ef7eb2e8f9f7 916 hcan->State = HAL_CAN_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 917 }
<> 144:ef7eb2e8f9f7 918
<> 144:ef7eb2e8f9f7 919 /* Set CAN error code to none */
<> 144:ef7eb2e8f9f7 920 hcan->ErrorCode = HAL_CAN_ERROR_NONE;
<> 144:ef7eb2e8f9f7 921
<> 144:ef7eb2e8f9f7 922 /* Enable Error warning, Error passive, Bus-off,
<> 144:ef7eb2e8f9f7 923 Last error and Error Interrupts */
<> 144:ef7eb2e8f9f7 924 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
<> 144:ef7eb2e8f9f7 925 CAN_IT_EPV |
<> 144:ef7eb2e8f9f7 926 CAN_IT_BOF |
<> 144:ef7eb2e8f9f7 927 CAN_IT_LEC |
<> 144:ef7eb2e8f9f7 928 CAN_IT_ERR);
<> 144:ef7eb2e8f9f7 929
<> 144:ef7eb2e8f9f7 930 /* Process unlocked */
<> 144:ef7eb2e8f9f7 931 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 932
<> 144:ef7eb2e8f9f7 933 if(FIFONumber == CAN_FIFO0)
<> 144:ef7eb2e8f9f7 934 {
<> 144:ef7eb2e8f9f7 935 /* Enable FIFO 0 message pending Interrupt */
<> 144:ef7eb2e8f9f7 936 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP0);
<> 144:ef7eb2e8f9f7 937 }
<> 144:ef7eb2e8f9f7 938 else
<> 144:ef7eb2e8f9f7 939 {
<> 144:ef7eb2e8f9f7 940 /* Enable FIFO 1 message pending Interrupt */
<> 144:ef7eb2e8f9f7 941 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP1);
<> 144:ef7eb2e8f9f7 942 }
<> 144:ef7eb2e8f9f7 943
<> 144:ef7eb2e8f9f7 944 }
<> 144:ef7eb2e8f9f7 945 else
<> 144:ef7eb2e8f9f7 946 {
<> 144:ef7eb2e8f9f7 947 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 948 }
<> 144:ef7eb2e8f9f7 949
<> 144:ef7eb2e8f9f7 950 /* Return function status */
<> 144:ef7eb2e8f9f7 951 return HAL_OK;
<> 144:ef7eb2e8f9f7 952 }
<> 144:ef7eb2e8f9f7 953
<> 144:ef7eb2e8f9f7 954 /**
<> 144:ef7eb2e8f9f7 955 * @brief Enters the Sleep (low power) mode.
<> 144:ef7eb2e8f9f7 956 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 957 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 958 * @retval HAL status.
<> 144:ef7eb2e8f9f7 959 */
<> 144:ef7eb2e8f9f7 960 HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 961 {
<> 144:ef7eb2e8f9f7 962 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 963
<> 144:ef7eb2e8f9f7 964 /* Process locked */
<> 144:ef7eb2e8f9f7 965 __HAL_LOCK(hcan);
<> 144:ef7eb2e8f9f7 966
<> 144:ef7eb2e8f9f7 967 /* Change CAN state */
<> 144:ef7eb2e8f9f7 968 hcan->State = HAL_CAN_STATE_BUSY;
<> 144:ef7eb2e8f9f7 969
<> 144:ef7eb2e8f9f7 970 /* Request Sleep mode */
<> 144:ef7eb2e8f9f7 971 hcan->Instance->MCR = (((hcan->Instance->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
<> 144:ef7eb2e8f9f7 972
<> 144:ef7eb2e8f9f7 973 /* Sleep mode status */
<> 144:ef7eb2e8f9f7 974 if ((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)
<> 144:ef7eb2e8f9f7 975 {
<> 144:ef7eb2e8f9f7 976 /* Process unlocked */
<> 144:ef7eb2e8f9f7 977 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 978
<> 144:ef7eb2e8f9f7 979 /* Return function status */
<> 144:ef7eb2e8f9f7 980 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 981 }
<> 144:ef7eb2e8f9f7 982
<> 144:ef7eb2e8f9f7 983 /* Get tick */
<> 144:ef7eb2e8f9f7 984 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 985
<> 144:ef7eb2e8f9f7 986 /* Wait the acknowledge */
<> 144:ef7eb2e8f9f7 987 while((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)
<> 144:ef7eb2e8f9f7 988 {
<> 144:ef7eb2e8f9f7 989 if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 990 {
<> 144:ef7eb2e8f9f7 991 hcan->State = HAL_CAN_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 992 /* Process unlocked */
<> 144:ef7eb2e8f9f7 993 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 994 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 995 }
<> 144:ef7eb2e8f9f7 996 }
<> 144:ef7eb2e8f9f7 997
<> 144:ef7eb2e8f9f7 998 /* Change CAN state */
<> 144:ef7eb2e8f9f7 999 hcan->State = HAL_CAN_STATE_READY;
<> 144:ef7eb2e8f9f7 1000
<> 144:ef7eb2e8f9f7 1001 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1002 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 1003
<> 144:ef7eb2e8f9f7 1004 /* Return function status */
<> 144:ef7eb2e8f9f7 1005 return HAL_OK;
<> 144:ef7eb2e8f9f7 1006 }
<> 144:ef7eb2e8f9f7 1007
<> 144:ef7eb2e8f9f7 1008 /**
<> 144:ef7eb2e8f9f7 1009 * @brief Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral
<> 144:ef7eb2e8f9f7 1010 * is in the normal mode.
<> 144:ef7eb2e8f9f7 1011 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1012 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 1013 * @retval HAL status.
<> 144:ef7eb2e8f9f7 1014 */
<> 144:ef7eb2e8f9f7 1015 HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 1016 {
<> 144:ef7eb2e8f9f7 1017 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 1018
<> 144:ef7eb2e8f9f7 1019 /* Process locked */
<> 144:ef7eb2e8f9f7 1020 __HAL_LOCK(hcan);
<> 144:ef7eb2e8f9f7 1021
<> 144:ef7eb2e8f9f7 1022 /* Change CAN state */
<> 144:ef7eb2e8f9f7 1023 hcan->State = HAL_CAN_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1024
<> 144:ef7eb2e8f9f7 1025 /* Wake up request */
<> 144:ef7eb2e8f9f7 1026 hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_SLEEP;
<> 144:ef7eb2e8f9f7 1027
<> 144:ef7eb2e8f9f7 1028 /* Get tick */
<> 144:ef7eb2e8f9f7 1029 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1030
<> 144:ef7eb2e8f9f7 1031 /* Sleep mode status */
<> 144:ef7eb2e8f9f7 1032 while((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
<> 144:ef7eb2e8f9f7 1033 {
<> 144:ef7eb2e8f9f7 1034 if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 1035 {
<> 144:ef7eb2e8f9f7 1036 hcan->State= HAL_CAN_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 1037 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1038 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 1039 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1040 }
<> 144:ef7eb2e8f9f7 1041 }
<> 144:ef7eb2e8f9f7 1042 if((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
<> 144:ef7eb2e8f9f7 1043 {
<> 144:ef7eb2e8f9f7 1044 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1045 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 1046
<> 144:ef7eb2e8f9f7 1047 /* Return function status */
<> 144:ef7eb2e8f9f7 1048 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1049 }
<> 144:ef7eb2e8f9f7 1050
<> 144:ef7eb2e8f9f7 1051 /* Change CAN state */
<> 144:ef7eb2e8f9f7 1052 hcan->State = HAL_CAN_STATE_READY;
<> 144:ef7eb2e8f9f7 1053
<> 144:ef7eb2e8f9f7 1054 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1055 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 1056
<> 144:ef7eb2e8f9f7 1057 /* Return function status */
<> 144:ef7eb2e8f9f7 1058 return HAL_OK;
<> 144:ef7eb2e8f9f7 1059 }
<> 144:ef7eb2e8f9f7 1060
<> 144:ef7eb2e8f9f7 1061 /**
<> 144:ef7eb2e8f9f7 1062 * @brief Handles CAN interrupt request
<> 144:ef7eb2e8f9f7 1063 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1064 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 1065 * @retval None
<> 144:ef7eb2e8f9f7 1066 */
<> 144:ef7eb2e8f9f7 1067 void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 1068 {
<> 144:ef7eb2e8f9f7 1069 uint32_t tmp1 = 0, tmp2 = 0, tmp3 = 0;
<> 144:ef7eb2e8f9f7 1070
<> 144:ef7eb2e8f9f7 1071 /* Check End of transmission flag */
<> 144:ef7eb2e8f9f7 1072 if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME))
<> 144:ef7eb2e8f9f7 1073 {
<> 144:ef7eb2e8f9f7 1074 tmp1 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0);
<> 144:ef7eb2e8f9f7 1075 tmp2 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1);
<> 144:ef7eb2e8f9f7 1076 tmp3 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2);
<> 144:ef7eb2e8f9f7 1077 if(tmp1 || tmp2 || tmp3)
<> 144:ef7eb2e8f9f7 1078 {
<> 144:ef7eb2e8f9f7 1079 /* Call transmit function */
<> 144:ef7eb2e8f9f7 1080 CAN_Transmit_IT(hcan);
<> 144:ef7eb2e8f9f7 1081 }
<> 144:ef7eb2e8f9f7 1082 }
<> 144:ef7eb2e8f9f7 1083
<> 144:ef7eb2e8f9f7 1084 tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0);
<> 144:ef7eb2e8f9f7 1085 tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0);
<> 144:ef7eb2e8f9f7 1086 /* Check End of reception flag for FIFO0 */
<> 144:ef7eb2e8f9f7 1087 if((tmp1 != 0) && tmp2)
<> 144:ef7eb2e8f9f7 1088 {
<> 144:ef7eb2e8f9f7 1089 /* Call receive function */
<> 144:ef7eb2e8f9f7 1090 CAN_Receive_IT(hcan, CAN_FIFO0);
<> 144:ef7eb2e8f9f7 1091 }
<> 144:ef7eb2e8f9f7 1092
<> 144:ef7eb2e8f9f7 1093 tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1);
<> 144:ef7eb2e8f9f7 1094 tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1);
<> 144:ef7eb2e8f9f7 1095 /* Check End of reception flag for FIFO1 */
<> 144:ef7eb2e8f9f7 1096 if((tmp1 != 0) && tmp2)
<> 144:ef7eb2e8f9f7 1097 {
<> 144:ef7eb2e8f9f7 1098 /* Call receive function */
<> 144:ef7eb2e8f9f7 1099 CAN_Receive_IT(hcan, CAN_FIFO1);
<> 144:ef7eb2e8f9f7 1100 }
<> 144:ef7eb2e8f9f7 1101
<> 144:ef7eb2e8f9f7 1102 tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG);
<> 144:ef7eb2e8f9f7 1103 tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG);
<> 144:ef7eb2e8f9f7 1104 tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
<> 144:ef7eb2e8f9f7 1105 /* Check Error Warning Flag */
<> 144:ef7eb2e8f9f7 1106 if(tmp1 && tmp2 && tmp3)
<> 144:ef7eb2e8f9f7 1107 {
<> 144:ef7eb2e8f9f7 1108 /* Set CAN error code to EWG error */
<> 144:ef7eb2e8f9f7 1109 hcan->ErrorCode |= HAL_CAN_ERROR_EWG;
<> 144:ef7eb2e8f9f7 1110 }
<> 144:ef7eb2e8f9f7 1111
<> 144:ef7eb2e8f9f7 1112 tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV);
<> 144:ef7eb2e8f9f7 1113 tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV);
<> 144:ef7eb2e8f9f7 1114 tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
<> 144:ef7eb2e8f9f7 1115 /* Check Error Passive Flag */
<> 144:ef7eb2e8f9f7 1116 if(tmp1 && tmp2 && tmp3)
<> 144:ef7eb2e8f9f7 1117 {
<> 144:ef7eb2e8f9f7 1118 /* Set CAN error code to EPV error */
<> 144:ef7eb2e8f9f7 1119 hcan->ErrorCode |= HAL_CAN_ERROR_EPV;
<> 144:ef7eb2e8f9f7 1120 }
<> 144:ef7eb2e8f9f7 1121
<> 144:ef7eb2e8f9f7 1122 tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF);
<> 144:ef7eb2e8f9f7 1123 tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF);
<> 144:ef7eb2e8f9f7 1124 tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
<> 144:ef7eb2e8f9f7 1125 /* Check Bus-Off Flag */
<> 144:ef7eb2e8f9f7 1126 if(tmp1 && tmp2 && tmp3)
<> 144:ef7eb2e8f9f7 1127 {
<> 144:ef7eb2e8f9f7 1128 /* Set CAN error code to BOF error */
<> 144:ef7eb2e8f9f7 1129 hcan->ErrorCode |= HAL_CAN_ERROR_BOF;
<> 144:ef7eb2e8f9f7 1130 }
<> 144:ef7eb2e8f9f7 1131
<> 144:ef7eb2e8f9f7 1132 tmp1 = HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC);
<> 144:ef7eb2e8f9f7 1133 tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC);
<> 144:ef7eb2e8f9f7 1134 tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
<> 144:ef7eb2e8f9f7 1135 /* Check Last error code Flag */
<> 144:ef7eb2e8f9f7 1136 if((!tmp1) && tmp2 && tmp3)
<> 144:ef7eb2e8f9f7 1137 {
<> 144:ef7eb2e8f9f7 1138 tmp1 = (hcan->Instance->ESR) & CAN_ESR_LEC;
<> 144:ef7eb2e8f9f7 1139 switch(tmp1)
<> 144:ef7eb2e8f9f7 1140 {
<> 144:ef7eb2e8f9f7 1141 case(CAN_ESR_LEC_0):
<> 144:ef7eb2e8f9f7 1142 /* Set CAN error code to STF error */
<> 144:ef7eb2e8f9f7 1143 hcan->ErrorCode |= HAL_CAN_ERROR_STF;
<> 144:ef7eb2e8f9f7 1144 break;
<> 144:ef7eb2e8f9f7 1145 case(CAN_ESR_LEC_1):
<> 144:ef7eb2e8f9f7 1146 /* Set CAN error code to FOR error */
<> 144:ef7eb2e8f9f7 1147 hcan->ErrorCode |= HAL_CAN_ERROR_FOR;
<> 144:ef7eb2e8f9f7 1148 break;
<> 144:ef7eb2e8f9f7 1149 case(CAN_ESR_LEC_1 | CAN_ESR_LEC_0):
<> 144:ef7eb2e8f9f7 1150 /* Set CAN error code to ACK error */
<> 144:ef7eb2e8f9f7 1151 hcan->ErrorCode |= HAL_CAN_ERROR_ACK;
<> 144:ef7eb2e8f9f7 1152 break;
<> 144:ef7eb2e8f9f7 1153 case(CAN_ESR_LEC_2):
<> 144:ef7eb2e8f9f7 1154 /* Set CAN error code to BR error */
<> 144:ef7eb2e8f9f7 1155 hcan->ErrorCode |= HAL_CAN_ERROR_BR;
<> 144:ef7eb2e8f9f7 1156 break;
<> 144:ef7eb2e8f9f7 1157 case(CAN_ESR_LEC_2 | CAN_ESR_LEC_0):
<> 144:ef7eb2e8f9f7 1158 /* Set CAN error code to BD error */
<> 144:ef7eb2e8f9f7 1159 hcan->ErrorCode |= HAL_CAN_ERROR_BD;
<> 144:ef7eb2e8f9f7 1160 break;
<> 144:ef7eb2e8f9f7 1161 case(CAN_ESR_LEC_2 | CAN_ESR_LEC_1):
<> 144:ef7eb2e8f9f7 1162 /* Set CAN error code to CRC error */
<> 144:ef7eb2e8f9f7 1163 hcan->ErrorCode |= HAL_CAN_ERROR_CRC;
<> 144:ef7eb2e8f9f7 1164 break;
<> 144:ef7eb2e8f9f7 1165 default:
<> 144:ef7eb2e8f9f7 1166 break;
<> 144:ef7eb2e8f9f7 1167 }
<> 144:ef7eb2e8f9f7 1168
<> 144:ef7eb2e8f9f7 1169 /* Clear Last error code Flag */
<> 144:ef7eb2e8f9f7 1170 hcan->Instance->ESR &= ~(CAN_ESR_LEC);
<> 144:ef7eb2e8f9f7 1171 }
<> 144:ef7eb2e8f9f7 1172
<> 144:ef7eb2e8f9f7 1173 /* Call the Error call Back in case of Errors */
<> 144:ef7eb2e8f9f7 1174 if(hcan->ErrorCode != HAL_CAN_ERROR_NONE)
<> 144:ef7eb2e8f9f7 1175 {
<> 144:ef7eb2e8f9f7 1176 /* Clear ERRI Flag */
<> 144:ef7eb2e8f9f7 1177 hcan->Instance->MSR = CAN_MSR_ERRI;
<> 144:ef7eb2e8f9f7 1178 /* Set the CAN state ready to be able to start again the process */
<> 144:ef7eb2e8f9f7 1179 hcan->State = HAL_CAN_STATE_READY;
<> 144:ef7eb2e8f9f7 1180 /* Call Error callback function */
<> 144:ef7eb2e8f9f7 1181 HAL_CAN_ErrorCallback(hcan);
<> 144:ef7eb2e8f9f7 1182 }
<> 144:ef7eb2e8f9f7 1183 }
<> 144:ef7eb2e8f9f7 1184
<> 144:ef7eb2e8f9f7 1185 /**
<> 144:ef7eb2e8f9f7 1186 * @brief Transmission complete callback in non blocking mode
<> 144:ef7eb2e8f9f7 1187 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1188 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 1189 * @retval None
<> 144:ef7eb2e8f9f7 1190 */
<> 144:ef7eb2e8f9f7 1191 __weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 1192 {
<> 144:ef7eb2e8f9f7 1193 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1194 UNUSED(hcan);
<> 144:ef7eb2e8f9f7 1195 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1196 the HAL_CAN_TxCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1197 */
<> 144:ef7eb2e8f9f7 1198 }
<> 144:ef7eb2e8f9f7 1199
<> 144:ef7eb2e8f9f7 1200 /**
<> 144:ef7eb2e8f9f7 1201 * @brief Transmission complete callback in non blocking mode
<> 144:ef7eb2e8f9f7 1202 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1203 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 1204 * @retval None
<> 144:ef7eb2e8f9f7 1205 */
<> 144:ef7eb2e8f9f7 1206 __weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 1207 {
<> 144:ef7eb2e8f9f7 1208 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1209 UNUSED(hcan);
<> 144:ef7eb2e8f9f7 1210 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1211 the HAL_CAN_RxCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1212 */
<> 144:ef7eb2e8f9f7 1213 }
<> 144:ef7eb2e8f9f7 1214
<> 144:ef7eb2e8f9f7 1215 /**
<> 144:ef7eb2e8f9f7 1216 * @brief Error CAN callback.
<> 144:ef7eb2e8f9f7 1217 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1218 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 1219 * @retval None
<> 144:ef7eb2e8f9f7 1220 */
<> 144:ef7eb2e8f9f7 1221 __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
<> 144:ef7eb2e8f9f7 1222 {
<> 144:ef7eb2e8f9f7 1223 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1224 UNUSED(hcan);
<> 144:ef7eb2e8f9f7 1225 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1226 the HAL_CAN_ErrorCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1227 */
<> 144:ef7eb2e8f9f7 1228 }
<> 144:ef7eb2e8f9f7 1229
<> 144:ef7eb2e8f9f7 1230 /**
<> 144:ef7eb2e8f9f7 1231 * @}
<> 144:ef7eb2e8f9f7 1232 */
<> 144:ef7eb2e8f9f7 1233
<> 144:ef7eb2e8f9f7 1234 /** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions
<> 144:ef7eb2e8f9f7 1235 * @brief CAN Peripheral State functions
<> 144:ef7eb2e8f9f7 1236 *
<> 144:ef7eb2e8f9f7 1237 @verbatim
<> 144:ef7eb2e8f9f7 1238 ==============================================================================
<> 144:ef7eb2e8f9f7 1239 ##### Peripheral State and Error functions #####
<> 144:ef7eb2e8f9f7 1240 ==============================================================================
<> 144:ef7eb2e8f9f7 1241 [..]
<> 144:ef7eb2e8f9f7 1242 This subsection provides functions allowing to :
<> 144:ef7eb2e8f9f7 1243 (+) Check the CAN state.
<> 144:ef7eb2e8f9f7 1244 (+) Check CAN Errors detected during interrupt process
<> 144:ef7eb2e8f9f7 1245
<> 144:ef7eb2e8f9f7 1246 @endverbatim
<> 144:ef7eb2e8f9f7 1247 * @{
<> 144:ef7eb2e8f9f7 1248 */
<> 144:ef7eb2e8f9f7 1249
<> 144:ef7eb2e8f9f7 1250 /**
<> 144:ef7eb2e8f9f7 1251 * @brief return the CAN state
<> 144:ef7eb2e8f9f7 1252 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1253 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 1254 * @retval HAL state
<> 144:ef7eb2e8f9f7 1255 */
<> 144:ef7eb2e8f9f7 1256 HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 1257 {
<> 144:ef7eb2e8f9f7 1258 /* Return CAN state */
<> 144:ef7eb2e8f9f7 1259 return hcan->State;
<> 144:ef7eb2e8f9f7 1260 }
<> 144:ef7eb2e8f9f7 1261
<> 144:ef7eb2e8f9f7 1262 /**
<> 144:ef7eb2e8f9f7 1263 * @brief Return the CAN error code
<> 144:ef7eb2e8f9f7 1264 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1265 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 1266 * @retval CAN Error Code
<> 144:ef7eb2e8f9f7 1267 */
<> 144:ef7eb2e8f9f7 1268 uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan)
<> 144:ef7eb2e8f9f7 1269 {
<> 144:ef7eb2e8f9f7 1270 return hcan->ErrorCode;
<> 144:ef7eb2e8f9f7 1271 }
<> 144:ef7eb2e8f9f7 1272
<> 144:ef7eb2e8f9f7 1273 /**
<> 144:ef7eb2e8f9f7 1274 * @}
<> 144:ef7eb2e8f9f7 1275 */
<> 144:ef7eb2e8f9f7 1276 /**
<> 144:ef7eb2e8f9f7 1277 * @brief Initiates and transmits a CAN frame message.
<> 144:ef7eb2e8f9f7 1278 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1279 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 1280 * @retval HAL status
<> 144:ef7eb2e8f9f7 1281 */
<> 144:ef7eb2e8f9f7 1282 static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 1283 {
<> 144:ef7eb2e8f9f7 1284 /* Disable Transmit mailbox empty Interrupt */
<> 144:ef7eb2e8f9f7 1285 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_TME);
<> 144:ef7eb2e8f9f7 1286
<> 144:ef7eb2e8f9f7 1287 if(hcan->State == HAL_CAN_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 1288 {
<> 144:ef7eb2e8f9f7 1289 /* Disable Error warning, Error passive, Bus-off, Last error code
<> 144:ef7eb2e8f9f7 1290 and Error Interrupts */
<> 144:ef7eb2e8f9f7 1291 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
<> 144:ef7eb2e8f9f7 1292 CAN_IT_EPV |
<> 144:ef7eb2e8f9f7 1293 CAN_IT_BOF |
<> 144:ef7eb2e8f9f7 1294 CAN_IT_LEC |
<> 144:ef7eb2e8f9f7 1295 CAN_IT_ERR );
<> 144:ef7eb2e8f9f7 1296 }
<> 144:ef7eb2e8f9f7 1297
<> 144:ef7eb2e8f9f7 1298 if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
<> 144:ef7eb2e8f9f7 1299 {
<> 144:ef7eb2e8f9f7 1300 /* Change CAN state */
<> 144:ef7eb2e8f9f7 1301 hcan->State = HAL_CAN_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 1302 }
<> 144:ef7eb2e8f9f7 1303 else
<> 144:ef7eb2e8f9f7 1304 {
<> 144:ef7eb2e8f9f7 1305 /* Change CAN state */
<> 144:ef7eb2e8f9f7 1306 hcan->State = HAL_CAN_STATE_READY;
<> 144:ef7eb2e8f9f7 1307 }
<> 144:ef7eb2e8f9f7 1308
<> 144:ef7eb2e8f9f7 1309 /* Transmission complete callback */
<> 144:ef7eb2e8f9f7 1310 HAL_CAN_TxCpltCallback(hcan);
<> 144:ef7eb2e8f9f7 1311
<> 144:ef7eb2e8f9f7 1312 return HAL_OK;
<> 144:ef7eb2e8f9f7 1313 }
<> 144:ef7eb2e8f9f7 1314
<> 144:ef7eb2e8f9f7 1315 /**
<> 144:ef7eb2e8f9f7 1316 * @brief Receives a correct CAN frame.
<> 144:ef7eb2e8f9f7 1317 * @param hcan: Pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1318 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 1319 * @param FIFONumber: Specify the FIFO number
<> 144:ef7eb2e8f9f7 1320 * @retval HAL status
<> 144:ef7eb2e8f9f7 1321 * @retval None
<> 144:ef7eb2e8f9f7 1322 */
<> 144:ef7eb2e8f9f7 1323 static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
<> 144:ef7eb2e8f9f7 1324 {
<> 144:ef7eb2e8f9f7 1325 /* Get the Id */
<> 144:ef7eb2e8f9f7 1326 hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
<> 144:ef7eb2e8f9f7 1327 if (hcan->pRxMsg->IDE == CAN_ID_STD)
<> 144:ef7eb2e8f9f7 1328 {
<> 144:ef7eb2e8f9f7 1329 hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21);
<> 144:ef7eb2e8f9f7 1330 }
<> 144:ef7eb2e8f9f7 1331 else
<> 144:ef7eb2e8f9f7 1332 {
<> 144:ef7eb2e8f9f7 1333 hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3);
<> 144:ef7eb2e8f9f7 1334 }
<> 144:ef7eb2e8f9f7 1335
<> 144:ef7eb2e8f9f7 1336 hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
<> 144:ef7eb2e8f9f7 1337 /* Get the DLC */
<> 144:ef7eb2e8f9f7 1338 hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
<> 144:ef7eb2e8f9f7 1339 /* Get the FMI */
<> 144:ef7eb2e8f9f7 1340 hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8);
<> 144:ef7eb2e8f9f7 1341 /* Get the data field */
<> 144:ef7eb2e8f9f7 1342 hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
<> 144:ef7eb2e8f9f7 1343 hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8);
<> 144:ef7eb2e8f9f7 1344 hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16);
<> 144:ef7eb2e8f9f7 1345 hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24);
<> 144:ef7eb2e8f9f7 1346 hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
<> 144:ef7eb2e8f9f7 1347 hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8);
<> 144:ef7eb2e8f9f7 1348 hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16);
<> 144:ef7eb2e8f9f7 1349 hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24);
<> 144:ef7eb2e8f9f7 1350 /* Release the FIFO */
<> 144:ef7eb2e8f9f7 1351 /* Release FIFO0 */
<> 144:ef7eb2e8f9f7 1352 if (FIFONumber == CAN_FIFO0)
<> 144:ef7eb2e8f9f7 1353 {
<> 144:ef7eb2e8f9f7 1354 __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
<> 144:ef7eb2e8f9f7 1355
<> 144:ef7eb2e8f9f7 1356 /* Disable FIFO 0 message pending Interrupt */
<> 144:ef7eb2e8f9f7 1357 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP0);
<> 144:ef7eb2e8f9f7 1358 }
<> 144:ef7eb2e8f9f7 1359 /* Release FIFO1 */
<> 144:ef7eb2e8f9f7 1360 else /* FIFONumber == CAN_FIFO1 */
<> 144:ef7eb2e8f9f7 1361 {
<> 144:ef7eb2e8f9f7 1362 __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
<> 144:ef7eb2e8f9f7 1363
<> 144:ef7eb2e8f9f7 1364 /* Disable FIFO 1 message pending Interrupt */
<> 144:ef7eb2e8f9f7 1365 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP1);
<> 144:ef7eb2e8f9f7 1366 }
<> 144:ef7eb2e8f9f7 1367
<> 144:ef7eb2e8f9f7 1368 if(hcan->State == HAL_CAN_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 1369 {
<> 144:ef7eb2e8f9f7 1370 /* Disable Error warning, Error passive, Bus-off, Last error code
<> 144:ef7eb2e8f9f7 1371 and Error Interrupts */
<> 144:ef7eb2e8f9f7 1372 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
<> 144:ef7eb2e8f9f7 1373 CAN_IT_EPV |
<> 144:ef7eb2e8f9f7 1374 CAN_IT_BOF |
<> 144:ef7eb2e8f9f7 1375 CAN_IT_LEC |
<> 144:ef7eb2e8f9f7 1376 CAN_IT_ERR);
<> 144:ef7eb2e8f9f7 1377 }
<> 144:ef7eb2e8f9f7 1378
<> 144:ef7eb2e8f9f7 1379 if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
<> 144:ef7eb2e8f9f7 1380 {
<> 144:ef7eb2e8f9f7 1381 /* Disable CAN state */
<> 144:ef7eb2e8f9f7 1382 hcan->State = HAL_CAN_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 1383 }
<> 144:ef7eb2e8f9f7 1384 else
<> 144:ef7eb2e8f9f7 1385 {
<> 144:ef7eb2e8f9f7 1386 /* Change CAN state */
<> 144:ef7eb2e8f9f7 1387 hcan->State = HAL_CAN_STATE_READY;
<> 144:ef7eb2e8f9f7 1388 }
<> 144:ef7eb2e8f9f7 1389
<> 144:ef7eb2e8f9f7 1390 /* Receive complete callback */
<> 144:ef7eb2e8f9f7 1391 HAL_CAN_RxCpltCallback(hcan);
<> 144:ef7eb2e8f9f7 1392
<> 144:ef7eb2e8f9f7 1393 /* Return function status */
<> 144:ef7eb2e8f9f7 1394 return HAL_OK;
<> 144:ef7eb2e8f9f7 1395 }
<> 144:ef7eb2e8f9f7 1396
<> 144:ef7eb2e8f9f7 1397 /**
<> 144:ef7eb2e8f9f7 1398 * @}
<> 144:ef7eb2e8f9f7 1399 */
<> 144:ef7eb2e8f9f7 1400
<> 144:ef7eb2e8f9f7 1401 #endif /* HAL_CAN_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1402 /**
<> 144:ef7eb2e8f9f7 1403 * @}
<> 144:ef7eb2e8f9f7 1404 */
<> 144:ef7eb2e8f9f7 1405
<> 144:ef7eb2e8f9f7 1406 /**
<> 144:ef7eb2e8f9f7 1407 * @}
<> 144:ef7eb2e8f9f7 1408 */
<> 144:ef7eb2e8f9f7 1409
<> 144:ef7eb2e8f9f7 1410 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/