Fawwaz Nadzmy / mbed-STM

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dac_ex.h@153:9398a535854b, 2016-12-22 (annotated)

Committer:
fwndz
Date:
Thu Dec 22 05:12:40 2016 +0000
Revision:
153:9398a535854b
Parent:
149:156823d33999 
device target maximize

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f1xx_hal_dac_ex.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.0.4
<> 144:ef7eb2e8f9f7 6 * @date 29-April-2016
<> 144:ef7eb2e8f9f7 7 * @brief Header file of DAC HAL Extension module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32F1xx_HAL_DAC_EX_H
<> 144:ef7eb2e8f9f7 40 #define __STM32F1xx_HAL_DAC_EX_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 #if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 49 #include "stm32f1xx_hal_def.h"
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 /** @addtogroup STM32F1xx_HAL_Driver
<> 144:ef7eb2e8f9f7 52 * @{
<> 144:ef7eb2e8f9f7 53 */
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 /** @addtogroup DACEx
<> 144:ef7eb2e8f9f7 56 * @{
<> 144:ef7eb2e8f9f7 57 */
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 /** @defgroup DACEx_Exported_Constants DACEx Exported Constants
<> 144:ef7eb2e8f9f7 64 * @{
<> 144:ef7eb2e8f9f7 65 */
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 /** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangleamplitude
<> 144:ef7eb2e8f9f7 68 * @{
<> 144:ef7eb2e8f9f7 69 */
<> 144:ef7eb2e8f9f7 70 #define DAC_LFSRUNMASK_BIT0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
<> 144:ef7eb2e8f9f7 71 #define DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
<> 144:ef7eb2e8f9f7 72 #define DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
<> 144:ef7eb2e8f9f7 73 #define DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
<> 144:ef7eb2e8f9f7 74 #define DAC_LFSRUNMASK_BITS4_0 ((uint32_t)DAC_CR_MAMP1_2) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
<> 144:ef7eb2e8f9f7 75 #define DAC_LFSRUNMASK_BITS5_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
<> 144:ef7eb2e8f9f7 76 #define DAC_LFSRUNMASK_BITS6_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
<> 144:ef7eb2e8f9f7 77 #define DAC_LFSRUNMASK_BITS7_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
<> 144:ef7eb2e8f9f7 78 #define DAC_LFSRUNMASK_BITS8_0 ((uint32_t)DAC_CR_MAMP1_3) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
<> 144:ef7eb2e8f9f7 79 #define DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
<> 144:ef7eb2e8f9f7 80 #define DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
<> 144:ef7eb2e8f9f7 81 #define DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
<> 144:ef7eb2e8f9f7 82 #define DAC_TRIANGLEAMPLITUDE_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
<> 144:ef7eb2e8f9f7 83 #define DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
<> 144:ef7eb2e8f9f7 84 #define DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */
<> 144:ef7eb2e8f9f7 85 #define DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
<> 144:ef7eb2e8f9f7 86 #define DAC_TRIANGLEAMPLITUDE_31 ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31 */
<> 144:ef7eb2e8f9f7 87 #define DAC_TRIANGLEAMPLITUDE_63 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
<> 144:ef7eb2e8f9f7 88 #define DAC_TRIANGLEAMPLITUDE_127 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127 */
<> 144:ef7eb2e8f9f7 89 #define DAC_TRIANGLEAMPLITUDE_255 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
<> 144:ef7eb2e8f9f7 90 #define DAC_TRIANGLEAMPLITUDE_511 ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511 */
<> 144:ef7eb2e8f9f7 91 #define DAC_TRIANGLEAMPLITUDE_1023 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
<> 144:ef7eb2e8f9f7 92 #define DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */
<> 144:ef7eb2e8f9f7 93 #define DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 /**
<> 144:ef7eb2e8f9f7 96 * @}
<> 144:ef7eb2e8f9f7 97 */
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 /** @defgroup DACEx_wave_generation DACEx wave generation
<> 144:ef7eb2e8f9f7 100 * @{
<> 144:ef7eb2e8f9f7 101 */
<> 144:ef7eb2e8f9f7 102 #define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0)
<> 144:ef7eb2e8f9f7 103 #define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 /**
<> 144:ef7eb2e8f9f7 106 * @}
<> 144:ef7eb2e8f9f7 107 */
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 /** @defgroup DACEx_trigger_selection DAC trigger selection
<> 144:ef7eb2e8f9f7 110 * @{
<> 144:ef7eb2e8f9f7 111 */
<> 144:ef7eb2e8f9f7 112 #define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
<> 144:ef7eb2e8f9f7 113 has been loaded, and not by external trigger */
<> 144:ef7eb2e8f9f7 114 #define DAC_TRIGGER_T6_TRGO ((uint32_t) DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
<> 144:ef7eb2e8f9f7 115 #define DAC_TRIGGER_T7_TRGO ((uint32_t)( DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
<> 144:ef7eb2e8f9f7 116 #define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
<> 144:ef7eb2e8f9f7 117 #define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
<> 144:ef7eb2e8f9f7 118 #define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
<> 144:ef7eb2e8f9f7 119 #define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121 #if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG)
<> 144:ef7eb2e8f9f7 122 /* For STM32F10x high-density and XL-density devices: TIM8 */
<> 144:ef7eb2e8f9f7 123 #define DAC_TRIGGER_T8_TRGO ((uint32_t) DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */
<> 144:ef7eb2e8f9f7 124 #endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 #if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F105xC) || defined (STM32F107xC)
<> 144:ef7eb2e8f9f7 127 /* For STM32F10x connectivity line devices and STM32F100x devices: TIM3 */
<> 144:ef7eb2e8f9f7 128 #define DAC_TRIGGER_T3_TRGO ((uint32_t) DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
<> 144:ef7eb2e8f9f7 129 #endif /* STM32F100xB || STM32F100xE || STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 /* Availability of trigger from TIM5 and TIM15: */
<> 144:ef7eb2e8f9f7 132 /* - For STM32F10x value line devices STM32F100xB: */
<> 144:ef7eb2e8f9f7 133 /* trigger from TIM15 is available, TIM5 not available. */
<> 144:ef7eb2e8f9f7 134 /* - For STM32F10x value line devices STM32F100xE: */
<> 144:ef7eb2e8f9f7 135 /* trigger from TIM15 and TIM5 are both available, */
<> 144:ef7eb2e8f9f7 136 /* selection depends on remap (with TIM5 as default configuration). */
<> 144:ef7eb2e8f9f7 137 /* - Other STM32F1 devices: */
<> 144:ef7eb2e8f9f7 138 /* trigger from TIM5 is available, TIM15 not available. */
<> 144:ef7eb2e8f9f7 139 #if defined (STM32F100xB)
<> 144:ef7eb2e8f9f7 140 #define DAC_TRIGGER_T15_TRGO ((uint32_t)( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */
<> 144:ef7eb2e8f9f7 141 #else
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 #define DAC_TRIGGER_T5_TRGO ((uint32_t)( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145 #if defined (STM32F100xE)
<> 144:ef7eb2e8f9f7 146 /*!< DAC trigger availability depending on STM32F1 devices:
<> 144:ef7eb2e8f9f7 147 For STM32F100x high-density value line devices, the TIM15 TRGO event can be selected
<> 144:ef7eb2e8f9f7 148 as replacement of TIM5 TRGO if the MISC_REMAP bit in the AFIO_MAPR2 register is set.
<> 144:ef7eb2e8f9f7 149 Refer to macro "__HAL_AFIO_REMAP_MISC_ENABLE()/__HAL_AFIO_REMAP_MISC_DISABLE()".
<> 144:ef7eb2e8f9f7 150 Otherwise, TIM5 TRGO is used and TIM15 TRGO is not used (default case).
<> 144:ef7eb2e8f9f7 151 For more details please refer to the AFIO section. */
<> 144:ef7eb2e8f9f7 152 #define DAC_TRIGGER_T15_TRGO DAC_TRIGGER_T5_TRGO
<> 144:ef7eb2e8f9f7 153 #endif /* STM32F100xE */
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 #endif /* STM32F100xB */
<> 144:ef7eb2e8f9f7 156 /**
<> 144:ef7eb2e8f9f7 157 * @}
<> 144:ef7eb2e8f9f7 158 */
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 #if defined (STM32F100xB) || defined (STM32F100xE)
<> 144:ef7eb2e8f9f7 161 /** @defgroup DAC_flags_definition DAC flags definition
<> 144:ef7eb2e8f9f7 162 * @{
<> 144:ef7eb2e8f9f7 163 */
<> 144:ef7eb2e8f9f7 164 #define DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
<> 144:ef7eb2e8f9f7 165 #define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 /**
<> 144:ef7eb2e8f9f7 168 * @}
<> 144:ef7eb2e8f9f7 169 */
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 /** @defgroup DAC_IT_definition DAC IT definition
<> 144:ef7eb2e8f9f7 172 * @{
<> 144:ef7eb2e8f9f7 173 */
<> 144:ef7eb2e8f9f7 174 #define DAC_IT_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
<> 144:ef7eb2e8f9f7 175 #define DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 /**
<> 144:ef7eb2e8f9f7 178 * @}
<> 144:ef7eb2e8f9f7 179 */
<> 144:ef7eb2e8f9f7 180 #endif /* STM32F100xB || STM32F100xE */
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 /**
<> 144:ef7eb2e8f9f7 183 * @}
<> 144:ef7eb2e8f9f7 184 */
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 #if defined (STM32F100xB) || defined (STM32F100xE)
<> 144:ef7eb2e8f9f7 189 /** @defgroup DACEx_Exported_Macros DACEx Exported Macros
<> 144:ef7eb2e8f9f7 190 * @{
<> 144:ef7eb2e8f9f7 191 */
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 /** @brief Enable the DAC interrupt
<> 144:ef7eb2e8f9f7 194 * @param __HANDLE__: specifies the DAC handle
<> 144:ef7eb2e8f9f7 195 * @param __INTERRUPT__: specifies the DAC interrupt.
<> 144:ef7eb2e8f9f7 196 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 197 * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
<> 144:ef7eb2e8f9f7 198 * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
<> 144:ef7eb2e8f9f7 199 * @retval None
<> 144:ef7eb2e8f9f7 200 */
<> 144:ef7eb2e8f9f7 201 #define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 /** @brief Disable the DAC interrupt
<> 144:ef7eb2e8f9f7 204 * @param __HANDLE__: specifies the DAC handle
<> 144:ef7eb2e8f9f7 205 * @param __INTERRUPT__: specifies the DAC interrupt.
<> 144:ef7eb2e8f9f7 206 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 207 * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
<> 144:ef7eb2e8f9f7 208 * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
<> 144:ef7eb2e8f9f7 209 * @retval None
<> 144:ef7eb2e8f9f7 210 */
<> 144:ef7eb2e8f9f7 211 #define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 /** @brief Checks if the specified DAC interrupt source is enabled or disabled.
<> 144:ef7eb2e8f9f7 214 * @param __HANDLE__: DAC handle
<> 144:ef7eb2e8f9f7 215 * @param __INTERRUPT__: DAC interrupt source to check
<> 144:ef7eb2e8f9f7 216 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 217 * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
<> 144:ef7eb2e8f9f7 218 * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
<> 144:ef7eb2e8f9f7 219 * @retval State of interruption (SET or RESET)
<> 144:ef7eb2e8f9f7 220 */
<> 144:ef7eb2e8f9f7 221 #define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 /** @brief Get the selected DAC's flag status.
<> 144:ef7eb2e8f9f7 224 * @param __HANDLE__: specifies the DAC handle.
<> 144:ef7eb2e8f9f7 225 * @param __FLAG__: specifies the DAC flag to get.
<> 144:ef7eb2e8f9f7 226 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 227 * @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
<> 144:ef7eb2e8f9f7 228 * @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
<> 144:ef7eb2e8f9f7 229 * @retval None
<> 144:ef7eb2e8f9f7 230 */
<> 144:ef7eb2e8f9f7 231 #define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
<> 144:ef7eb2e8f9f7 232
<> 144:ef7eb2e8f9f7 233 /** @brief Clear the DAC's flag.
<> 144:ef7eb2e8f9f7 234 * @param __HANDLE__: specifies the DAC handle.
<> 144:ef7eb2e8f9f7 235 * @param __FLAG__: specifies the DAC flag to clear.
<> 144:ef7eb2e8f9f7 236 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 237 * @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
<> 144:ef7eb2e8f9f7 238 * @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
<> 144:ef7eb2e8f9f7 239 * @retval None
<> 144:ef7eb2e8f9f7 240 */
<> 144:ef7eb2e8f9f7 241 #define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
<> 144:ef7eb2e8f9f7 242
<> 144:ef7eb2e8f9f7 243
<> 144:ef7eb2e8f9f7 244 /**
<> 144:ef7eb2e8f9f7 245 * @}
<> 144:ef7eb2e8f9f7 246 */
<> 144:ef7eb2e8f9f7 247 #endif /* STM32F100xB || STM32F100xE */
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 /** @defgroup DACEx_Private_Macros DACEx Private Macros
<> 144:ef7eb2e8f9f7 252 * @{
<> 144:ef7eb2e8f9f7 253 */
<> 144:ef7eb2e8f9f7 254 #if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG)
<> 144:ef7eb2e8f9f7 255 #define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
<> 144:ef7eb2e8f9f7 256 ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
<> 144:ef7eb2e8f9f7 257 ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
<> 144:ef7eb2e8f9f7 258 ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
<> 144:ef7eb2e8f9f7 259 ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
<> 144:ef7eb2e8f9f7 260 ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
<> 144:ef7eb2e8f9f7 261 ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
<> 144:ef7eb2e8f9f7 262 ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
<> 144:ef7eb2e8f9f7 263 ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
<> 144:ef7eb2e8f9f7 264 #endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
<> 144:ef7eb2e8f9f7 265 #if defined (STM32F100xE) || defined (STM32F105xC) || defined (STM32F107xC)
<> 144:ef7eb2e8f9f7 266 #define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
<> 144:ef7eb2e8f9f7 267 ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
<> 144:ef7eb2e8f9f7 268 ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
<> 144:ef7eb2e8f9f7 269 ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
<> 144:ef7eb2e8f9f7 270 ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
<> 144:ef7eb2e8f9f7 271 ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
<> 144:ef7eb2e8f9f7 272 ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
<> 144:ef7eb2e8f9f7 273 ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
<> 144:ef7eb2e8f9f7 274 ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
<> 144:ef7eb2e8f9f7 275 #endif /* STM32F100xE || STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 276 #if defined (STM32F100xB)
<> 144:ef7eb2e8f9f7 277 #define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
<> 144:ef7eb2e8f9f7 278 ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
<> 144:ef7eb2e8f9f7 279 ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
<> 144:ef7eb2e8f9f7 280 ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
<> 144:ef7eb2e8f9f7 281 ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
<> 144:ef7eb2e8f9f7 282 ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
<> 144:ef7eb2e8f9f7 283 ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
<> 144:ef7eb2e8f9f7 284 ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
<> 144:ef7eb2e8f9f7 285 ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
<> 144:ef7eb2e8f9f7 286 #endif /* STM32F100xB */
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 #define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
<> 144:ef7eb2e8f9f7 289 ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
<> 144:ef7eb2e8f9f7 290 ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
<> 144:ef7eb2e8f9f7 291 ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
<> 144:ef7eb2e8f9f7 292 ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
<> 144:ef7eb2e8f9f7 293 ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
<> 144:ef7eb2e8f9f7 294 ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
<> 144:ef7eb2e8f9f7 295 ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
<> 144:ef7eb2e8f9f7 296 ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
<> 144:ef7eb2e8f9f7 297 ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
<> 144:ef7eb2e8f9f7 298 ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
<> 144:ef7eb2e8f9f7 299 ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
<> 144:ef7eb2e8f9f7 300 ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
<> 144:ef7eb2e8f9f7 301 ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
<> 144:ef7eb2e8f9f7 302 ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
<> 144:ef7eb2e8f9f7 303 ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
<> 144:ef7eb2e8f9f7 304 ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
<> 144:ef7eb2e8f9f7 305 ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
<> 144:ef7eb2e8f9f7 306 ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
<> 144:ef7eb2e8f9f7 307 ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
<> 144:ef7eb2e8f9f7 308 ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
<> 144:ef7eb2e8f9f7 309 ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
<> 144:ef7eb2e8f9f7 310 ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
<> 144:ef7eb2e8f9f7 311 ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
<> 144:ef7eb2e8f9f7 312
<> 144:ef7eb2e8f9f7 313 /**
<> 144:ef7eb2e8f9f7 314 * @}
<> 144:ef7eb2e8f9f7 315 */
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317
<> 144:ef7eb2e8f9f7 318 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 319
<> 144:ef7eb2e8f9f7 320 /** @addtogroup DACEx_Exported_Functions
<> 144:ef7eb2e8f9f7 321 * @{
<> 144:ef7eb2e8f9f7 322 */
<> 144:ef7eb2e8f9f7 323
<> 144:ef7eb2e8f9f7 324 /** @addtogroup DACEx_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 325 * @{
<> 144:ef7eb2e8f9f7 326 */
<> 144:ef7eb2e8f9f7 327 /* Extension features functions ***********************************************/
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329 uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac);
<> 144:ef7eb2e8f9f7 330 HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
<> 144:ef7eb2e8f9f7 331 HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
<> 144:ef7eb2e8f9f7 332 HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
<> 144:ef7eb2e8f9f7 333
<> 144:ef7eb2e8f9f7 334 void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac);
<> 144:ef7eb2e8f9f7 335 void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac);
<> 144:ef7eb2e8f9f7 336 void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef* hdac);
<> 144:ef7eb2e8f9f7 337
<> 144:ef7eb2e8f9f7 338 #if defined (STM32F100xB) || defined (STM32F100xE)
<> 144:ef7eb2e8f9f7 339 void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
<> 144:ef7eb2e8f9f7 340 void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
<> 144:ef7eb2e8f9f7 341 void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac);
<> 144:ef7eb2e8f9f7 342 #endif /* STM32F100xB) || defined (STM32F100xE) */
<> 144:ef7eb2e8f9f7 343
<> 144:ef7eb2e8f9f7 344 /**
<> 144:ef7eb2e8f9f7 345 * @}
<> 144:ef7eb2e8f9f7 346 */
<> 144:ef7eb2e8f9f7 347
<> 144:ef7eb2e8f9f7 348
<> 144:ef7eb2e8f9f7 349
<> 144:ef7eb2e8f9f7 350
<> 144:ef7eb2e8f9f7 351 /**
<> 144:ef7eb2e8f9f7 352 * @}
<> 144:ef7eb2e8f9f7 353 */
<> 144:ef7eb2e8f9f7 354
<> 144:ef7eb2e8f9f7 355 /** @addtogroup DACEx_Private_Functions
<> 144:ef7eb2e8f9f7 356 * @{
<> 144:ef7eb2e8f9f7 357 */
<> 144:ef7eb2e8f9f7 358 void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 359 void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 360 void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 361
<> 144:ef7eb2e8f9f7 362 /**
<> 144:ef7eb2e8f9f7 363 * @}
<> 144:ef7eb2e8f9f7 364 */
<> 144:ef7eb2e8f9f7 365
<> 144:ef7eb2e8f9f7 366 /**
<> 144:ef7eb2e8f9f7 367 * @}
<> 144:ef7eb2e8f9f7 368 */
<> 144:ef7eb2e8f9f7 369
<> 144:ef7eb2e8f9f7 370 /**
<> 144:ef7eb2e8f9f7 371 * @}
<> 144:ef7eb2e8f9f7 372 */
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374 #endif /* STM32F100xB || STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 375
<> 144:ef7eb2e8f9f7 376 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 377 }
<> 144:ef7eb2e8f9f7 378 #endif
<> 144:ef7eb2e8f9f7 379
<> 144:ef7eb2e8f9f7 380 #endif /*__STM32F1xx_HAL_DAC_EX_H */
<> 144:ef7eb2e8f9f7 381
<> 144:ef7eb2e8f9f7 382 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/