Fawwaz Nadzmy / mbed-STM

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/TARGET_NXP/TARGET_LPC23XX/device/system_LPC23xx.c@153:9398a535854b, 2016-12-22 (annotated)

Committer:
fwndz
Date:
Thu Dec 22 05:12:40 2016 +0000
Revision:
153:9398a535854b
Parent:
149:156823d33999 
device target maximize

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (C) 2008-2009 ARM Limited. All rights reserved.
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * ARM7 version of CMSIS-like functionality - not advised for use outside mbed!
<> 144:ef7eb2e8f9f7 5 */
<> 144:ef7eb2e8f9f7 6
<> 144:ef7eb2e8f9f7 7 #include <stdint.h>
<> 144:ef7eb2e8f9f7 8 #include "LPC23xx.h"
<> 144:ef7eb2e8f9f7 9
<> 144:ef7eb2e8f9f7 10 #define CLOCK_SETUP 1
<> 144:ef7eb2e8f9f7 11 #define SCS_Val 0x00000020
<> 144:ef7eb2e8f9f7 12 #define CLKSRCSEL_Val 0x00000001
<> 144:ef7eb2e8f9f7 13
<> 144:ef7eb2e8f9f7 14 #define PLL0_SETUP 1
<> 144:ef7eb2e8f9f7 15 #define PLL0CFG_Val 0x00000013
<> 144:ef7eb2e8f9f7 16 #define CCLKCFG_Val 0x00000007
<> 144:ef7eb2e8f9f7 17 #define USBCLKCFG_Val 0x00000009
<> 144:ef7eb2e8f9f7 18 #define PCLKSEL0_Val 0x00000000
<> 144:ef7eb2e8f9f7 19 #define PCLKSEL1_Val 0x00000000
<> 144:ef7eb2e8f9f7 20 #define PCONP_Val 0x042887DE
<> 144:ef7eb2e8f9f7 21 #define CLKOUTCFG_Val 0x00000000
<> 144:ef7eb2e8f9f7 22 #define MAMCR_Val 0x00000001 // there is a bug in the MAM so it should never be fully enabled (only disabled or partially enabled)
<> 144:ef7eb2e8f9f7 23 #define MAMTIM_Val 0x00000004
<> 144:ef7eb2e8f9f7 24
<> 144:ef7eb2e8f9f7 25 /*----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 26 DEFINES
<> 144:ef7eb2e8f9f7 27 *----------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 28
<> 144:ef7eb2e8f9f7 29 #define XTAL (12000000UL) /* Oscillator frequency */
<> 144:ef7eb2e8f9f7 30 #define OSC_CLK ( XTAL) /* Main oscillator frequency */
<> 144:ef7eb2e8f9f7 31 #define RTC_CLK ( 32000UL) /* RTC oscillator frequency */
<> 144:ef7eb2e8f9f7 32 #define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 /* F_cco0 = (2 * M * F_in) / N */
<> 144:ef7eb2e8f9f7 35 #define __M (((PLL0CFG_Val ) & 0x7FFF) + 1)
<> 144:ef7eb2e8f9f7 36 #define __N (((PLL0CFG_Val >> 16) & 0x00FF) + 1)
<> 144:ef7eb2e8f9f7 37 #define __FCCO(__F_IN) ((2 * __M * __F_IN) / __N)
<> 144:ef7eb2e8f9f7 38 #define __CCLK_DIV (((CCLKCFG_Val ) & 0x00FF) + 1)
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 /* Determine core clock frequency according to settings */
<> 144:ef7eb2e8f9f7 41 #if (PLL0_SETUP)
<> 144:ef7eb2e8f9f7 42 #if ((CLKSRCSEL_Val & 0x03) == 1)
<> 144:ef7eb2e8f9f7 43 #define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV)
<> 144:ef7eb2e8f9f7 44 #elif ((CLKSRCSEL_Val & 0x03) == 2)
<> 144:ef7eb2e8f9f7 45 #define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV)
<> 144:ef7eb2e8f9f7 46 #else
<> 144:ef7eb2e8f9f7 47 #define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV)
<> 144:ef7eb2e8f9f7 48 #endif
<> 144:ef7eb2e8f9f7 49 #endif
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 /*----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 53 Clock Variable definitions
<> 144:ef7eb2e8f9f7 54 *----------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 55 uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /*----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 58 Clock functions
<> 144:ef7eb2e8f9f7 59 *----------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 60 void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
<> 144:ef7eb2e8f9f7 61 {
<> 144:ef7eb2e8f9f7 62 /* Determine clock frequency according to clock register values */
<> 144:ef7eb2e8f9f7 63 if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */
<> 144:ef7eb2e8f9f7 64 switch (LPC_SC->CLKSRCSEL & 0x03) {
<> 144:ef7eb2e8f9f7 65 case 0: /* Int. RC oscillator => PLL0 */
<> 144:ef7eb2e8f9f7 66 case 3: /* Reserved, default to Int. RC */
<> 144:ef7eb2e8f9f7 67 SystemCoreClock = (IRC_OSC *
<> 144:ef7eb2e8f9f7 68 (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
<> 144:ef7eb2e8f9f7 69 (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)) /
<> 144:ef7eb2e8f9f7 70 ((LPC_SC->CCLKCFG & 0xFF)+ 1));
<> 144:ef7eb2e8f9f7 71 break;
<> 144:ef7eb2e8f9f7 72 case 1: /* Main oscillator => PLL0 */
<> 144:ef7eb2e8f9f7 73 SystemCoreClock = (OSC_CLK *
<> 144:ef7eb2e8f9f7 74 (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
<> 144:ef7eb2e8f9f7 75 (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)) /
<> 144:ef7eb2e8f9f7 76 ((LPC_SC->CCLKCFG & 0xFF)+ 1));
<> 144:ef7eb2e8f9f7 77 break;
<> 144:ef7eb2e8f9f7 78 case 2: /* RTC oscillator => PLL0 */
<> 144:ef7eb2e8f9f7 79 SystemCoreClock = (RTC_CLK *
<> 144:ef7eb2e8f9f7 80 (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
<> 144:ef7eb2e8f9f7 81 (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)) /
<> 144:ef7eb2e8f9f7 82 ((LPC_SC->CCLKCFG & 0xFF)+ 1));
<> 144:ef7eb2e8f9f7 83 break;
<> 144:ef7eb2e8f9f7 84 }
<> 144:ef7eb2e8f9f7 85 } else {
<> 144:ef7eb2e8f9f7 86 switch (LPC_SC->CLKSRCSEL & 0x03) {
<> 144:ef7eb2e8f9f7 87 case 0: /* Int. RC oscillator => PLL0 */
<> 144:ef7eb2e8f9f7 88 case 3: /* Reserved, default to Int. RC */
<> 144:ef7eb2e8f9f7 89 SystemCoreClock = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
<> 144:ef7eb2e8f9f7 90 break;
<> 144:ef7eb2e8f9f7 91 case 1: /* Main oscillator => PLL0 */
<> 144:ef7eb2e8f9f7 92 SystemCoreClock = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
<> 144:ef7eb2e8f9f7 93 break;
<> 144:ef7eb2e8f9f7 94 case 2: /* RTC oscillator => PLL0 */
<> 144:ef7eb2e8f9f7 95 SystemCoreClock = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
<> 144:ef7eb2e8f9f7 96 break;
<> 144:ef7eb2e8f9f7 97 }
<> 144:ef7eb2e8f9f7 98 }
<> 144:ef7eb2e8f9f7 99 }
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 /**
<> 144:ef7eb2e8f9f7 102 * Initialize the system
<> 144:ef7eb2e8f9f7 103 *
<> 144:ef7eb2e8f9f7 104 * @param none
<> 144:ef7eb2e8f9f7 105 * @return none
<> 144:ef7eb2e8f9f7 106 *
<> 144:ef7eb2e8f9f7 107 * @brief Setup the microcontroller system.
<> 144:ef7eb2e8f9f7 108 * Initialize the System and update the SystemFrequency variable.
<> 144:ef7eb2e8f9f7 109 */
<> 144:ef7eb2e8f9f7 110 void SystemInit (void)
<> 144:ef7eb2e8f9f7 111 {
<> 144:ef7eb2e8f9f7 112 #if (CLOCK_SETUP) /* Clock Setup */
<> 144:ef7eb2e8f9f7 113 LPC_SC->SCS = SCS_Val;
<> 144:ef7eb2e8f9f7 114 if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */
<> 144:ef7eb2e8f9f7 115 while ((LPC_SC->SCS & (1 << 6)) == 0); /* Wait for Oscillator to be ready */
<> 144:ef7eb2e8f9f7 116 }
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 LPC_SC->CCLKCFG = CCLKCFG_Val; /* Setup Clock Divider */
<> 144:ef7eb2e8f9f7 119
<> 144:ef7eb2e8f9f7 120 #if (PLL0_SETUP)
<> 144:ef7eb2e8f9f7 121 LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for PLL0 */
<> 144:ef7eb2e8f9f7 122 LPC_SC->PLL0CFG = PLL0CFG_Val;
<> 144:ef7eb2e8f9f7 123 LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */
<> 144:ef7eb2e8f9f7 124 LPC_SC->PLL0FEED = 0xAA;
<> 144:ef7eb2e8f9f7 125 LPC_SC->PLL0FEED = 0x55;
<> 144:ef7eb2e8f9f7 126 while (!(LPC_SC->PLL0STAT & (1 << 26))); /* Wait for PLOCK0 */
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 LPC_SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */
<> 144:ef7eb2e8f9f7 129 LPC_SC->PLL0FEED = 0xAA;
<> 144:ef7eb2e8f9f7 130 LPC_SC->PLL0FEED = 0x55;
<> 144:ef7eb2e8f9f7 131 #endif
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 LPC_SC->USBCLKCFG = USBCLKCFG_Val; /* Setup USB Clock Divider */
<> 144:ef7eb2e8f9f7 134 #endif
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */
<> 144:ef7eb2e8f9f7 137 LPC_SC->PCLKSEL1 = PCLKSEL1_Val;
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 // Setup MAM
<> 144:ef7eb2e8f9f7 142 LPC_SC->MAMTIM = MAMTIM_Val;
<> 144:ef7eb2e8f9f7 143 LPC_SC->MAMCR = MAMCR_Val;
<> 144:ef7eb2e8f9f7 144 }