Fawwaz Nadzmy / mbed-STM

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/TARGET_NXP/TARGET_LPC15XX/device/TOOLCHAIN_ARM_MICRO/startup_LPC15xx.S@153:9398a535854b, 2016-12-22 (annotated)

Committer:
fwndz
Date:
Thu Dec 22 05:12:40 2016 +0000
Revision:
153:9398a535854b
Parent:
149:156823d33999 
device target maximize

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 ;/**************************************************************************//**
<> 144:ef7eb2e8f9f7 2 ; * @file startup_LPC15xx.s
<> 144:ef7eb2e8f9f7 3 ; * @brief CMSIS Cortex-M3 Core Device Startup File for
<> 144:ef7eb2e8f9f7 4 ; * NXP LPC15xx Device Series
<> 144:ef7eb2e8f9f7 5 ; * @version V1.00
<> 144:ef7eb2e8f9f7 6 ; * @date 17. July 2013
<> 144:ef7eb2e8f9f7 7 ; *
<> 144:ef7eb2e8f9f7 8 ; * @note
<> 144:ef7eb2e8f9f7 9 ; * Copyright (C) 2009-2013 ARM Limited. All rights reserved.
<> 144:ef7eb2e8f9f7 10 ; *
<> 144:ef7eb2e8f9f7 11 ; * @par
<> 144:ef7eb2e8f9f7 12 ; * ARM Limited (ARM) is supplying this software for use with Cortex-M
<> 144:ef7eb2e8f9f7 13 ; * processor based microcontrollers. This file can be freely distributed
<> 144:ef7eb2e8f9f7 14 ; * within development tools that are supporting such ARM based processors.
<> 144:ef7eb2e8f9f7 15 ; *
<> 144:ef7eb2e8f9f7 16 ; * @par
<> 144:ef7eb2e8f9f7 17 ; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 144:ef7eb2e8f9f7 18 ; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 144:ef7eb2e8f9f7 19 ; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 144:ef7eb2e8f9f7 20 ; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
<> 144:ef7eb2e8f9f7 21 ; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 144:ef7eb2e8f9f7 22 ; *
<> 144:ef7eb2e8f9f7 23 ; ******************************************************************************/
<> 144:ef7eb2e8f9f7 24
<> 144:ef7eb2e8f9f7 25 ; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
<> 144:ef7eb2e8f9f7 26
<> 144:ef7eb2e8f9f7 27 ; <h> Stack Configuration
<> 144:ef7eb2e8f9f7 28 ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
<> 144:ef7eb2e8f9f7 29 ; </h>
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 Stack_Size EQU 0x00000200
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 AREA STACK, NOINIT, READWRITE, ALIGN=3
<> 144:ef7eb2e8f9f7 34 EXPORT __initial_sp
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 __initial_sp EQU 0x02009000 ; Top of RAM from LPC1549
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 ; <h> Heap Configuration
<> 144:ef7eb2e8f9f7 40 ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
<> 144:ef7eb2e8f9f7 41 ; </h>
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 Heap_Size EQU 0x00000000
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 AREA HEAP, NOINIT, READWRITE, ALIGN=3
<> 144:ef7eb2e8f9f7 46 __heap_base
<> 144:ef7eb2e8f9f7 47 Heap_Mem SPACE Heap_Size
<> 144:ef7eb2e8f9f7 48 __heap_limit
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 PRESERVE8
<> 144:ef7eb2e8f9f7 52 THUMB
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 ; Vector Table Mapped to Address 0 at Reset
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 AREA RESET, DATA, READONLY
<> 144:ef7eb2e8f9f7 58 EXPORT __Vectors
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 __Vectors DCD __initial_sp ; Top of Stack
<> 144:ef7eb2e8f9f7 61 DCD Reset_Handler ; Reset Handler
<> 144:ef7eb2e8f9f7 62 DCD NMI_Handler ; NMI Handler
<> 144:ef7eb2e8f9f7 63 DCD HardFault_Handler ; Hard Fault Handler
<> 144:ef7eb2e8f9f7 64 DCD MemManage_Handler ; MPU Fault Handler
<> 144:ef7eb2e8f9f7 65 DCD BusFault_Handler ; Bus Fault Handler
<> 144:ef7eb2e8f9f7 66 DCD UsageFault_Handler ; Usage Fault Handler
<> 144:ef7eb2e8f9f7 67 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 68 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 69 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 70 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 71 DCD SVC_Handler ; SVCall Handler
<> 144:ef7eb2e8f9f7 72 DCD DebugMon_Handler ; Debug Monitor Handler
<> 144:ef7eb2e8f9f7 73 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 74 DCD PendSV_Handler ; PendSV Handler
<> 144:ef7eb2e8f9f7 75 DCD SysTick_Handler ; SysTick Handler
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 ; External Interrupts
<> 144:ef7eb2e8f9f7 78 DCD WDT_IRQHandler ; 16+ 0 Windowed watchdog timer interrupt
<> 144:ef7eb2e8f9f7 79 DCD BOD_IRQHandler ; 16+ 1 BOD interrupt
<> 144:ef7eb2e8f9f7 80 DCD FLASH_IRQHandler ; 16+ 2 Flash controller interrupt
<> 144:ef7eb2e8f9f7 81 DCD EE_IRQHandler ; 16+ 3 EEPROM controller interrupt
<> 144:ef7eb2e8f9f7 82 DCD DMA_IRQHandler ; 16+ 4 DMA interrupt
<> 144:ef7eb2e8f9f7 83 DCD GINT0_IRQHandler ; 16+ 5 GPIO group0 interrupt
<> 144:ef7eb2e8f9f7 84 DCD GINT1_IRQHandler ; 16+ 6 GPIO group1 interrupt
<> 144:ef7eb2e8f9f7 85 DCD PIN_INT0_IRQHandler ; 16+ 7 Pin interrupt 0 or pattern match engine slice 0 interrupt
<> 144:ef7eb2e8f9f7 86 DCD PIN_INT1_IRQHandler ; 16+ 8 Pin interrupt 1 or pattern match engine slice 1 interrupt
<> 144:ef7eb2e8f9f7 87 DCD PIN_INT2_IRQHandler ; 16+ 9 Pin interrupt 2 or pattern match engine slice 2 interrupt
<> 144:ef7eb2e8f9f7 88 DCD PIN_INT3_IRQHandler ; 16+10 Pin interrupt 3 or pattern match engine slice 3 interrupt
<> 144:ef7eb2e8f9f7 89 DCD PIN_INT4_IRQHandler ; 16+11 Pin interrupt 4 or pattern match engine slice 4 interrupt
<> 144:ef7eb2e8f9f7 90 DCD PIN_INT5_IRQHandler ; 16+12 Pin interrupt 5 or pattern match engine slice 5 interrupt
<> 144:ef7eb2e8f9f7 91 DCD PIN_INT6_IRQHandler ; 16+13 Pin interrupt 6 or pattern match engine slice 6 interrupt
<> 144:ef7eb2e8f9f7 92 DCD PIN_INT7_IRQHandler ; 16+14 Pin interrupt 7 or pattern match engine slice 7 interrupt
<> 144:ef7eb2e8f9f7 93 DCD RIT_IRQHandler ; 16+15 RIT interrupt
<> 144:ef7eb2e8f9f7 94 DCD SCT0_IRQHandler ; 16+16 State configurable timer interrupt
<> 144:ef7eb2e8f9f7 95 DCD SCT1_IRQHandler ; 16+17 State configurable timer interrupt
<> 144:ef7eb2e8f9f7 96 DCD SCT2_IRQHandler ; 16+18 State configurable timer interrupt
<> 144:ef7eb2e8f9f7 97 DCD SCT3_IRQHandler ; 16+19 State configurable timer interrupt
<> 144:ef7eb2e8f9f7 98 DCD MRT_IRQHandler ; 16+20 Multi-rate timer interrupt
<> 144:ef7eb2e8f9f7 99 DCD UART0_IRQHandler ; 16+21 USART0 interrupt
<> 144:ef7eb2e8f9f7 100 DCD UART1_IRQHandler ; 16+22 USART1 interrupt
<> 144:ef7eb2e8f9f7 101 DCD UART2_IRQHandler ; 16+23 USART2 interrupt
<> 144:ef7eb2e8f9f7 102 DCD I2C0_IRQHandler ; 16+24 I2C0 interrupt
<> 144:ef7eb2e8f9f7 103 DCD SPI0_IRQHandler ; 16+25 SPI0 interrupt
<> 144:ef7eb2e8f9f7 104 DCD SPI1_IRQHandler ; 16+26 SPI1 interrupt
<> 144:ef7eb2e8f9f7 105 DCD C_CAN0_IRQHandler ; 16+27 C_CAN0 interrupt
<> 144:ef7eb2e8f9f7 106 DCD USB_IRQ_IRQHandler ; 16+28 USB interrupt
<> 144:ef7eb2e8f9f7 107 DCD USB_FIQ_IRQHandler ; 16+29 USB interrupt
<> 144:ef7eb2e8f9f7 108 DCD USBWAKEUP_IRQHandler ; 16+30 USB wake-up interrupt
<> 144:ef7eb2e8f9f7 109 DCD ADC0_SEQA_IRQHandler ; 16+31 ADC0 sequence A completion.
<> 144:ef7eb2e8f9f7 110 DCD ADC0_SEQB_IRQHandler ; 16+32 ADC0 sequence B completion.
<> 144:ef7eb2e8f9f7 111 DCD ADC0_THCMP_IRQHandler ; 16+33 ADC0 threshold compare
<> 144:ef7eb2e8f9f7 112 DCD ADC0_OVR_IRQHandler ; 16+34 ADC0 overrun
<> 144:ef7eb2e8f9f7 113 DCD ADC1_SEQA_IRQHandler ; 16+35 ADC1 sequence A completion.
<> 144:ef7eb2e8f9f7 114 DCD ADC1_SEQB_IRQHandler ; 16+36 ADC1 sequence B completion.
<> 144:ef7eb2e8f9f7 115 DCD ADC1_THCMP_IRQHandler ; 16+37 ADC1 threshold compare
<> 144:ef7eb2e8f9f7 116 DCD ADC1_OVR_IRQHandler ; 16+38 ADC1 overrun
<> 144:ef7eb2e8f9f7 117 DCD DAC_IRQHandler ; 16+39 DAC interrupt
<> 144:ef7eb2e8f9f7 118 DCD CMP0_IRQHandler ; 16+40 Analog comparator 0 interrupt (ACMP0)
<> 144:ef7eb2e8f9f7 119 DCD CMP1_IRQHandler ; 16+41 Analog comparator 1 interrupt (ACMP1)
<> 144:ef7eb2e8f9f7 120 DCD CMP2_IRQHandler ; 16+42 Analog comparator 2 interrupt (ACMP2)
<> 144:ef7eb2e8f9f7 121 DCD CMP3_IRQHandler ; 16+43 Analog comparator 3 interrupt (ACMP3)
<> 144:ef7eb2e8f9f7 122 DCD QEI_IRQHandler ; 16+44 QEI interrupt
<> 144:ef7eb2e8f9f7 123 DCD RTC_ALARM_IRQHandler ; 16+45 RTC alarm interrupt
<> 144:ef7eb2e8f9f7 124 DCD RTC_WAKE_IRQHandler ; 16+46 RTC wake-up interrut
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 ; <h> Code Read Protection
<> 144:ef7eb2e8f9f7 127 ; <o> Code Read Protection <0xFFFFFFFF=>CRP Disabled
<> 144:ef7eb2e8f9f7 128 ; <0x12345678=>CRP Level 1
<> 144:ef7eb2e8f9f7 129 ; <0x87654321=>CRP Level 2
<> 144:ef7eb2e8f9f7 130 ; <0x43218765=>CRP Level 3 (ARE YOU SURE?)
<> 144:ef7eb2e8f9f7 131 ; <0x4E697370=>NO ISP (ARE YOU SURE?)
<> 144:ef7eb2e8f9f7 132 ; </h>
<> 144:ef7eb2e8f9f7 133 IF :LNOT::DEF:NO_CRP
<> 144:ef7eb2e8f9f7 134 AREA |.ARM.__at_0x02FC|, CODE, READONLY
<> 144:ef7eb2e8f9f7 135 DCD 0xFFFFFFFF
<> 144:ef7eb2e8f9f7 136 ENDIF
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 AREA |.text|, CODE, READONLY
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 ; Reset Handler
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 Reset_Handler PROC
<> 144:ef7eb2e8f9f7 144 EXPORT Reset_Handler [WEAK]
<> 144:ef7eb2e8f9f7 145 IMPORT SystemInit
<> 144:ef7eb2e8f9f7 146 IMPORT __main
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 ;--- enable SRAM1 and SRAM2 memory
<> 144:ef7eb2e8f9f7 149 LDR R0, =0x400740C4 ; SYSAHBCLKCTRL0 register addr
<> 144:ef7eb2e8f9f7 150 LDR R2, [R0] ; read SYSAHBCLKCTRL0
<> 144:ef7eb2e8f9f7 151 ORR R2, R2, #0x18 ; enable SRAM1, SRAM2
<> 144:ef7eb2e8f9f7 152 STR R2, [R0] ; store SYSAHBCLKCTRL0
<> 144:ef7eb2e8f9f7 153 ;---
<> 144:ef7eb2e8f9f7 154 LDR R0, =SystemInit
<> 144:ef7eb2e8f9f7 155 BLX R0
<> 144:ef7eb2e8f9f7 156 LDR R0, =__main
<> 144:ef7eb2e8f9f7 157 BX R0
<> 144:ef7eb2e8f9f7 158 ENDP
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 ; Dummy Exception Handlers (infinite loops which can be modified)
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 NMI_Handler PROC
<> 144:ef7eb2e8f9f7 164 EXPORT NMI_Handler [WEAK]
<> 144:ef7eb2e8f9f7 165 B .
<> 144:ef7eb2e8f9f7 166 ENDP
<> 144:ef7eb2e8f9f7 167 HardFault_Handler\
<> 144:ef7eb2e8f9f7 168 PROC
<> 144:ef7eb2e8f9f7 169 EXPORT HardFault_Handler [WEAK]
<> 144:ef7eb2e8f9f7 170 B .
<> 144:ef7eb2e8f9f7 171 ENDP
<> 144:ef7eb2e8f9f7 172 MemManage_Handler\
<> 144:ef7eb2e8f9f7 173 PROC
<> 144:ef7eb2e8f9f7 174 EXPORT MemManage_Handler [WEAK]
<> 144:ef7eb2e8f9f7 175 B .
<> 144:ef7eb2e8f9f7 176 ENDP
<> 144:ef7eb2e8f9f7 177 BusFault_Handler\
<> 144:ef7eb2e8f9f7 178 PROC
<> 144:ef7eb2e8f9f7 179 EXPORT BusFault_Handler [WEAK]
<> 144:ef7eb2e8f9f7 180 B .
<> 144:ef7eb2e8f9f7 181 ENDP
<> 144:ef7eb2e8f9f7 182 UsageFault_Handler\
<> 144:ef7eb2e8f9f7 183 PROC
<> 144:ef7eb2e8f9f7 184 EXPORT UsageFault_Handler [WEAK]
<> 144:ef7eb2e8f9f7 185 B .
<> 144:ef7eb2e8f9f7 186 ENDP
<> 144:ef7eb2e8f9f7 187 SVC_Handler PROC
<> 144:ef7eb2e8f9f7 188 EXPORT SVC_Handler [WEAK]
<> 144:ef7eb2e8f9f7 189 B .
<> 144:ef7eb2e8f9f7 190 ENDP
<> 144:ef7eb2e8f9f7 191 DebugMon_Handler\
<> 144:ef7eb2e8f9f7 192 PROC
<> 144:ef7eb2e8f9f7 193 EXPORT DebugMon_Handler [WEAK]
<> 144:ef7eb2e8f9f7 194 B .
<> 144:ef7eb2e8f9f7 195 ENDP
<> 144:ef7eb2e8f9f7 196 PendSV_Handler PROC
<> 144:ef7eb2e8f9f7 197 EXPORT PendSV_Handler [WEAK]
<> 144:ef7eb2e8f9f7 198 B .
<> 144:ef7eb2e8f9f7 199 ENDP
<> 144:ef7eb2e8f9f7 200 SysTick_Handler PROC
<> 144:ef7eb2e8f9f7 201 EXPORT SysTick_Handler [WEAK]
<> 144:ef7eb2e8f9f7 202 B .
<> 144:ef7eb2e8f9f7 203 ENDP
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 Default_Handler PROC
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 EXPORT WDT_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 208 EXPORT BOD_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 209 EXPORT FLASH_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 210 EXPORT EE_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 211 EXPORT DMA_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 212 EXPORT GINT0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 213 EXPORT GINT1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 214 EXPORT PIN_INT0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 215 EXPORT PIN_INT1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 216 EXPORT PIN_INT2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 217 EXPORT PIN_INT3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 218 EXPORT PIN_INT4_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 219 EXPORT PIN_INT5_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 220 EXPORT PIN_INT6_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 221 EXPORT PIN_INT7_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 222 EXPORT RIT_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 223 EXPORT SCT0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 224 EXPORT SCT1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 225 EXPORT SCT2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 226 EXPORT SCT3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 227 EXPORT MRT_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 228 EXPORT UART0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 229 EXPORT UART1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 230 EXPORT UART2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 231 EXPORT I2C0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 232 EXPORT SPI0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 233 EXPORT SPI1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 234 EXPORT C_CAN0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 235 EXPORT USB_IRQ_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 236 EXPORT USB_FIQ_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 237 EXPORT USBWAKEUP_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 238 EXPORT ADC0_SEQA_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 239 EXPORT ADC0_SEQB_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 240 EXPORT ADC0_THCMP_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 241 EXPORT ADC0_OVR_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 242 EXPORT ADC1_SEQA_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 243 EXPORT ADC1_SEQB_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 244 EXPORT ADC1_THCMP_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 245 EXPORT ADC1_OVR_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 246 EXPORT DAC_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 247 EXPORT CMP0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 248 EXPORT CMP1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 249 EXPORT CMP2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 250 EXPORT CMP3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 251 EXPORT QEI_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 252 EXPORT RTC_ALARM_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 253 EXPORT RTC_WAKE_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 WDT_IRQHandler
<> 144:ef7eb2e8f9f7 256 BOD_IRQHandler
<> 144:ef7eb2e8f9f7 257 FLASH_IRQHandler
<> 144:ef7eb2e8f9f7 258 EE_IRQHandler
<> 144:ef7eb2e8f9f7 259 DMA_IRQHandler
<> 144:ef7eb2e8f9f7 260 GINT0_IRQHandler
<> 144:ef7eb2e8f9f7 261 GINT1_IRQHandler
<> 144:ef7eb2e8f9f7 262 PIN_INT0_IRQHandler
<> 144:ef7eb2e8f9f7 263 PIN_INT1_IRQHandler
<> 144:ef7eb2e8f9f7 264 PIN_INT2_IRQHandler
<> 144:ef7eb2e8f9f7 265 PIN_INT3_IRQHandler
<> 144:ef7eb2e8f9f7 266 PIN_INT4_IRQHandler
<> 144:ef7eb2e8f9f7 267 PIN_INT5_IRQHandler
<> 144:ef7eb2e8f9f7 268 PIN_INT6_IRQHandler
<> 144:ef7eb2e8f9f7 269 PIN_INT7_IRQHandler
<> 144:ef7eb2e8f9f7 270 RIT_IRQHandler
<> 144:ef7eb2e8f9f7 271 SCT0_IRQHandler
<> 144:ef7eb2e8f9f7 272 SCT1_IRQHandler
<> 144:ef7eb2e8f9f7 273 SCT2_IRQHandler
<> 144:ef7eb2e8f9f7 274 SCT3_IRQHandler
<> 144:ef7eb2e8f9f7 275 MRT_IRQHandler
<> 144:ef7eb2e8f9f7 276 UART0_IRQHandler
<> 144:ef7eb2e8f9f7 277 UART1_IRQHandler
<> 144:ef7eb2e8f9f7 278 UART2_IRQHandler
<> 144:ef7eb2e8f9f7 279 I2C0_IRQHandler
<> 144:ef7eb2e8f9f7 280 SPI0_IRQHandler
<> 144:ef7eb2e8f9f7 281 SPI1_IRQHandler
<> 144:ef7eb2e8f9f7 282 C_CAN0_IRQHandler
<> 144:ef7eb2e8f9f7 283 USB_IRQ_IRQHandler
<> 144:ef7eb2e8f9f7 284 USB_FIQ_IRQHandler
<> 144:ef7eb2e8f9f7 285 USBWAKEUP_IRQHandler
<> 144:ef7eb2e8f9f7 286 ADC0_SEQA_IRQHandler
<> 144:ef7eb2e8f9f7 287 ADC0_SEQB_IRQHandler
<> 144:ef7eb2e8f9f7 288 ADC0_THCMP_IRQHandler
<> 144:ef7eb2e8f9f7 289 ADC0_OVR_IRQHandler
<> 144:ef7eb2e8f9f7 290 ADC1_SEQA_IRQHandler
<> 144:ef7eb2e8f9f7 291 ADC1_SEQB_IRQHandler
<> 144:ef7eb2e8f9f7 292 ADC1_THCMP_IRQHandler
<> 144:ef7eb2e8f9f7 293 ADC1_OVR_IRQHandler
<> 144:ef7eb2e8f9f7 294 DAC_IRQHandler
<> 144:ef7eb2e8f9f7 295 CMP0_IRQHandler
<> 144:ef7eb2e8f9f7 296 CMP1_IRQHandler
<> 144:ef7eb2e8f9f7 297 CMP2_IRQHandler
<> 144:ef7eb2e8f9f7 298 CMP3_IRQHandler
<> 144:ef7eb2e8f9f7 299 QEI_IRQHandler
<> 144:ef7eb2e8f9f7 300 RTC_ALARM_IRQHandler
<> 144:ef7eb2e8f9f7 301 RTC_WAKE_IRQHandler
<> 144:ef7eb2e8f9f7 302
<> 144:ef7eb2e8f9f7 303 B .
<> 144:ef7eb2e8f9f7 304
<> 144:ef7eb2e8f9f7 305 ENDP
<> 144:ef7eb2e8f9f7 306
<> 144:ef7eb2e8f9f7 307
<> 144:ef7eb2e8f9f7 308 ALIGN
<> 144:ef7eb2e8f9f7 309
<> 144:ef7eb2e8f9f7 310
<> 144:ef7eb2e8f9f7 311 ; User Initial Stack & Heap
<> 144:ef7eb2e8f9f7 312
<> 144:ef7eb2e8f9f7 313 EXPORT __initial_sp
<> 144:ef7eb2e8f9f7 314 EXPORT __heap_base
<> 144:ef7eb2e8f9f7 315 EXPORT __heap_limit
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 END